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build failed on intel fpga platform #2

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franz-git opened this issue May 20, 2020 · 3 comments
Open

build failed on intel fpga platform #2

franz-git opened this issue May 20, 2020 · 3 comments

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@franz-git
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test platform: DE10_Nano
Got Error while Quartus Analysis & Synthesis:

Info: Command: quartus_map --rev=top top
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS
in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Error (10170): Verilog HDL syntax error at top.v(1888) near text: """; expecting "(". Check for and fix any syntax errors that appear immediately before or at
the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: //wsl$/Ubuntu/home/franz/projects/lambdaconcept/lambdasoc/build/top.v Line: 1888
Error (10170): Verilog HDL syntax error at top.v(1891) near text: """; expecting "(". Check for and fix any syntax errors that appear immediately before or at
the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: //wsl$/Ubuntu/home/franz/projects/lambdaconcept/lambdasoc/build/top.v Line: 1891

Error (10170): Verilog HDL syntax error at top.v(1895) near text: """; expecting "(". Check for and fix any syntax errors that appear immediately before or at
the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: //wsl$/Ubuntu/home/franz/projects/lambdaconcept/lambdasoc/build/top.v Line: 1895
Error (10170): Verilog HDL syntax error at top.v(1900) near text: """; expecting "(". Check for and fix any syntax errors that appear immediately before or at
the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: //wsl$/Ubuntu/home/franz/projects/lambdaconcept/lambdasoc/build/top.v Line: 1900
Error (10170): Verilog HDL syntax error at top.v(1903) near text: """; expecting "(". Check for and fix any syntax errors that appear immediately before or at

@franz-git
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I think the problem should be also forwarded to nmigen group...

@jeanthom
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Hi Franz,
This effectively seems to be an nMigen or Yosys issue rather than a LambdaSOC one. Could you tell us which versions of nMigen and Yosys you are using?

@franz-git
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Hi ,
I have update nMigen/Yosys to latest version then retry, got same problem:
Yosys : 0.9+2406(git shal 574812d9, clang 6.0.0-1ubuntu2 -fPIC -Os)
nmigen (0.3.dev57+geaf33fb, /usr/local/lib/python3.6/dist-packages/nmigen-0.3.dev57+geaf33fb-py3.6.egg)
nmigen-boards (0.1.dev103+g2f02b39.dirty)
nmigen-soc (0.1.dev30+g425692a, /usr/local/lib/python3.6/dist-packages)
nmigen-stdio (0.1.dev6+gb5ff8b8, /usr/local/lib/python3.6/dist-packages)

Thanks.

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