diff --git a/stm32/.mxproject b/stm32/.mxproject index 8e2c23a..eaec126 100644 --- a/stm32/.mxproject +++ b/stm32/.mxproject @@ -1,27 +1,27 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dcmi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcmi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_adc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_adc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dma_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crs.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_system.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_gpio.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dmamux.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pwr.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_cortex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_crc.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_crc_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_dcmi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_i2c.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_i2c_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pka.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_pka.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rng.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rng_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_spi.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_spi_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_tim_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_smartcard_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd_ex.h;Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usb.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Drivers/CMSIS/Include/core_cm85.h;Drivers/CMSIS/Include/cachel1_armv7.h;Drivers/CMSIS/Include/pac_armv81.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm35p.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv81mml.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm55.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/pmu_armv8.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_starmc1.h;Drivers/CMSIS/Include/cmsis_armclang_ltm.h; +LibFiles=Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_adc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_adc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_adc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_crc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_crc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dcmi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_hash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_i2c.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_i2c.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_i2c_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pka.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pka.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rng.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rng.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rng_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_spi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_spi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_spi_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_smartcard.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_smartcard_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pcd.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pcd_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usb.h;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dcmi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_hash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pka.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usb.c;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_adc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_adc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_adc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_bus.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rcc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crs.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_system.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_utils.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_gpio.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dma.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_dmamux.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pwr.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_cortex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_exti.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_crc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_crc.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_crc_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dcmi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_hash.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_i2c.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_i2c.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_i2c_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_icache.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pka.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_pka.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rng.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_rng.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rng_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_spi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_spi.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_spi_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_tim.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_smartcard.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_smartcard_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pcd.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pcd_ex.h;Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_ll_usb.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h573xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core/Src/main.c;Core/Src/linked_list.c;Core/Src/stm32h5xx_it.c;Core/Src/stm32h5xx_hal_msp.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcmi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_adc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_crc_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dcmi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_i2c_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pka.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rng_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_rng.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_spi_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_tim_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_smartcard_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd_ex.c;Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c;Core/Src/system_stm32h5xx.c;;; -HeaderPath=Drivers/STM32H5xx_HAL_Driver/Inc;Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32H5xx/Include;Drivers/CMSIS/Include;Core/Inc; +SourceFiles=Core\Src\main.c;Core\Src\linked_list.c;Core\Src\stm32h5xx_it.c;Core\Src\stm32h5xx_hal_msp.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dcmi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_hash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pka.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_adc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_crc_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dcmi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_hash.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_i2c_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pka.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rng_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_rng.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_spi_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_smartcard_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pcd_ex.c;Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_ll_usb.c;Drivers\CMSIS\Device\ST\STM32H5xx\Source\Templates\system_stm32h5xx.c;Core\Src\system_stm32h5xx.c;;; +HeaderPath=Drivers\STM32H5xx_HAL_Driver\Inc;Drivers\STM32H5xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32H5xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32H573xx;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=4 -HeaderFiles#0=../Core/Inc/linked_list.h -HeaderFiles#1=../Core/Inc/stm32h5xx_it.h -HeaderFiles#2=../Core/Inc/stm32h5xx_hal_conf.h -HeaderFiles#3=../Core/Inc/main.h +HeaderFiles#0=..\Core\Inc\linked_list.h +HeaderFiles#1=..\Core\Inc\stm32h5xx_it.h +HeaderFiles#2=..\Core\Inc\stm32h5xx_hal_conf.h +HeaderFiles#3=..\Core\Inc\main.h HeaderFolderListSize=1 -HeaderPath#0=../Core/Inc +HeaderPath#0=..\Core\Inc HeaderFiles=; SourceFileListSize=4 -SourceFiles#0=../Core/Src/linked_list.c -SourceFiles#1=../Core/Src/stm32h5xx_it.c -SourceFiles#2=../Core/Src/stm32h5xx_hal_msp.c -SourceFiles#3=../Core/Src/main.c +SourceFiles#0=..\Core\Src\linked_list.c +SourceFiles#1=..\Core\Src\stm32h5xx_it.c +SourceFiles#2=..\Core\Src\stm32h5xx_hal_msp.c +SourceFiles#3=..\Core\Src\main.c SourceFolderListSize=1 -SourcePath#0=../Core/Src +SourcePath#0=..\Core\Src SourceFiles=; diff --git a/stm32/Core/Inc/stm32h5xx_it.h b/stm32/Core/Inc/stm32h5xx_it.h index 2841e9d..b5fb3a8 100644 --- a/stm32/Core/Inc/stm32h5xx_it.h +++ b/stm32/Core/Inc/stm32h5xx_it.h @@ -22,7 +22,7 @@ #define __STM32H5xx_IT_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Private includes ----------------------------------------------------------*/ diff --git a/stm32/Core/Src/main.c b/stm32/Core/Src/main.c index de7f508..5a7ff46 100644 --- a/stm32/Core/Src/main.c +++ b/stm32/Core/Src/main.c @@ -922,8 +922,8 @@ void MX_USB_PCD_Init(void) void MX_GPIO_Init(void) { GPIO_InitTypeDef GPIO_InitStruct = {0}; -/* USER CODE BEGIN MX_GPIO_Init_1 */ -/* USER CODE END MX_GPIO_Init_1 */ + /* USER CODE BEGIN MX_GPIO_Init_1 */ + /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOE_CLK_ENABLE(); @@ -1072,8 +1072,8 @@ void MX_GPIO_Init(void) HAL_NVIC_SetPriority(EXTI13_IRQn, 2, 0); HAL_NVIC_EnableIRQ(EXTI13_IRQn); -/* USER CODE BEGIN MX_GPIO_Init_2 */ -/* USER CODE END MX_GPIO_Init_2 */ + /* USER CODE BEGIN MX_GPIO_Init_2 */ + /* USER CODE END MX_GPIO_Init_2 */ } /* USER CODE BEGIN 4 */ diff --git a/stm32/Core/Src/stm32h5xx_hal_msp.c b/stm32/Core/Src/stm32h5xx_hal_msp.c index 38f8430..5ee0180 100644 --- a/stm32/Core/Src/stm32h5xx_hal_msp.c +++ b/stm32/Core/Src/stm32h5xx_hal_msp.c @@ -72,6 +72,9 @@ void HAL_MspInit(void) /* System interrupt init*/ + /* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */ + HAL_PWREx_DisableUCPDDeadBattery(); + /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ @@ -80,19 +83,19 @@ void HAL_MspInit(void) static uint32_t HAL_RCC_ADC_CLK_ENABLED=0; /** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ + * @brief ADC MSP Initialization + * This function configures the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hadc->Instance==ADC1) { - /* USER CODE BEGIN ADC1_MspInit 0 */ + /* USER CODE BEGIN ADC1_MspInit 0 */ - /* USER CODE END ADC1_MspInit 0 */ + /* USER CODE END ADC1_MspInit 0 */ /** Initializes the peripherals clock */ @@ -108,15 +111,15 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); } - /* USER CODE BEGIN ADC1_MspInit 1 */ + /* USER CODE BEGIN ADC1_MspInit 1 */ - /* USER CODE END ADC1_MspInit 1 */ + /* USER CODE END ADC1_MspInit 1 */ } else if(hadc->Instance==ADC2) { - /* USER CODE BEGIN ADC2_MspInit 0 */ + /* USER CODE BEGIN ADC2_MspInit 0 */ - /* USER CODE END ADC2_MspInit 0 */ + /* USER CODE END ADC2_MspInit 0 */ /** Initializes the peripherals clock */ @@ -132,111 +135,111 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) if(HAL_RCC_ADC_CLK_ENABLED==1){ __HAL_RCC_ADC_CLK_ENABLE(); } - /* USER CODE BEGIN ADC2_MspInit 1 */ + /* USER CODE BEGIN ADC2_MspInit 1 */ - /* USER CODE END ADC2_MspInit 1 */ + /* USER CODE END ADC2_MspInit 1 */ } } /** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ + * @brief ADC MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hadc: ADC handle pointer + * @retval None + */ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) { if(hadc->Instance==ADC1) { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ + /* USER CODE BEGIN ADC1_MspDeInit 0 */ - /* USER CODE END ADC1_MspDeInit 0 */ + /* USER CODE END ADC1_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC_CLK_ENABLED--; if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); } - /* USER CODE BEGIN ADC1_MspDeInit 1 */ + /* USER CODE BEGIN ADC1_MspDeInit 1 */ - /* USER CODE END ADC1_MspDeInit 1 */ + /* USER CODE END ADC1_MspDeInit 1 */ } else if(hadc->Instance==ADC2) { - /* USER CODE BEGIN ADC2_MspDeInit 0 */ + /* USER CODE BEGIN ADC2_MspDeInit 0 */ - /* USER CODE END ADC2_MspDeInit 0 */ + /* USER CODE END ADC2_MspDeInit 0 */ /* Peripheral clock disable */ HAL_RCC_ADC_CLK_ENABLED--; if(HAL_RCC_ADC_CLK_ENABLED==0){ __HAL_RCC_ADC_CLK_DISABLE(); } - /* USER CODE BEGIN ADC2_MspDeInit 1 */ + /* USER CODE BEGIN ADC2_MspDeInit 1 */ - /* USER CODE END ADC2_MspDeInit 1 */ + /* USER CODE END ADC2_MspDeInit 1 */ } } /** -* @brief CRC MSP Initialization -* This function configures the hardware resources used in this example -* @param hcrc: CRC handle pointer -* @retval None -*/ + * @brief CRC MSP Initialization + * This function configures the hardware resources used in this example + * @param hcrc: CRC handle pointer + * @retval None + */ void HAL_CRC_MspInit(CRC_HandleTypeDef* hcrc) { if(hcrc->Instance==CRC) { - /* USER CODE BEGIN CRC_MspInit 0 */ + /* USER CODE BEGIN CRC_MspInit 0 */ - /* USER CODE END CRC_MspInit 0 */ + /* USER CODE END CRC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_CRC_CLK_ENABLE(); - /* USER CODE BEGIN CRC_MspInit 1 */ + /* USER CODE BEGIN CRC_MspInit 1 */ - /* USER CODE END CRC_MspInit 1 */ + /* USER CODE END CRC_MspInit 1 */ } } /** -* @brief CRC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hcrc: CRC handle pointer -* @retval None -*/ + * @brief CRC MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hcrc: CRC handle pointer + * @retval None + */ void HAL_CRC_MspDeInit(CRC_HandleTypeDef* hcrc) { if(hcrc->Instance==CRC) { - /* USER CODE BEGIN CRC_MspDeInit 0 */ + /* USER CODE BEGIN CRC_MspDeInit 0 */ - /* USER CODE END CRC_MspDeInit 0 */ + /* USER CODE END CRC_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_CRC_CLK_DISABLE(); - /* USER CODE BEGIN CRC_MspDeInit 1 */ + /* USER CODE BEGIN CRC_MspDeInit 1 */ - /* USER CODE END CRC_MspDeInit 1 */ + /* USER CODE END CRC_MspDeInit 1 */ } } /** -* @brief DCMI MSP Initialization -* This function configures the hardware resources used in this example -* @param hdcmi: DCMI handle pointer -* @retval None -*/ + * @brief DCMI MSP Initialization + * This function configures the hardware resources used in this example + * @param hdcmi: DCMI handle pointer + * @retval None + */ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) { GPIO_InitTypeDef GPIO_InitStruct = {0}; if(hdcmi->Instance==DCMI) { - /* USER CODE BEGIN DCMI_MspInit 0 */ + /* USER CODE BEGIN DCMI_MspInit 0 */ - /* USER CODE END DCMI_MspInit 0 */ + /* USER CODE END DCMI_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_DCMI_PSSI_CLK_ENABLE(); @@ -281,27 +284,27 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) /* DCMI interrupt Init */ HAL_NVIC_SetPriority(DCMI_PSSI_IRQn, 2, 0); HAL_NVIC_EnableIRQ(DCMI_PSSI_IRQn); - /* USER CODE BEGIN DCMI_MspInit 1 */ + /* USER CODE BEGIN DCMI_MspInit 1 */ - /* USER CODE END DCMI_MspInit 1 */ + /* USER CODE END DCMI_MspInit 1 */ } } /** -* @brief DCMI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hdcmi: DCMI handle pointer -* @retval None -*/ + * @brief DCMI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hdcmi: DCMI handle pointer + * @retval None + */ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) { if(hdcmi->Instance==DCMI) { - /* USER CODE BEGIN DCMI_MspDeInit 0 */ + /* USER CODE BEGIN DCMI_MspDeInit 0 */ - /* USER CODE END DCMI_MspDeInit 0 */ + /* USER CODE END DCMI_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_DCMI_PSSI_CLK_DISABLE(); @@ -327,66 +330,66 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi) /* DCMI interrupt DeInit */ HAL_NVIC_DisableIRQ(DCMI_PSSI_IRQn); - /* USER CODE BEGIN DCMI_MspDeInit 1 */ + /* USER CODE BEGIN DCMI_MspDeInit 1 */ - /* USER CODE END DCMI_MspDeInit 1 */ + /* USER CODE END DCMI_MspDeInit 1 */ } } /** -* @brief HASH MSP Initialization -* This function configures the hardware resources used in this example -* @param hhash: HASH handle pointer -* @retval None -*/ + * @brief HASH MSP Initialization + * This function configures the hardware resources used in this example + * @param hhash: HASH handle pointer + * @retval None + */ void HAL_HASH_MspInit(HASH_HandleTypeDef* hhash) { - /* USER CODE BEGIN HASH_MspInit 0 */ + /* USER CODE BEGIN HASH_MspInit 0 */ - /* USER CODE END HASH_MspInit 0 */ + /* USER CODE END HASH_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_HASH_CLK_ENABLE(); - /* USER CODE BEGIN HASH_MspInit 1 */ + /* USER CODE BEGIN HASH_MspInit 1 */ - /* USER CODE END HASH_MspInit 1 */ + /* USER CODE END HASH_MspInit 1 */ } /** -* @brief HASH MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hhash: HASH handle pointer -* @retval None -*/ + * @brief HASH MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hhash: HASH handle pointer + * @retval None + */ void HAL_HASH_MspDeInit(HASH_HandleTypeDef* hhash) { - /* USER CODE BEGIN HASH_MspDeInit 0 */ + /* USER CODE BEGIN HASH_MspDeInit 0 */ - /* USER CODE END HASH_MspDeInit 0 */ + /* USER CODE END HASH_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_HASH_CLK_DISABLE(); - /* USER CODE BEGIN HASH_MspDeInit 1 */ + /* USER CODE BEGIN HASH_MspDeInit 1 */ - /* USER CODE END HASH_MspDeInit 1 */ + /* USER CODE END HASH_MspDeInit 1 */ } /** -* @brief I2C MSP Initialization -* This function configures the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ + * @brief I2C MSP Initialization + * This function configures the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hi2c->Instance==I2C2) { - /* USER CODE BEGIN I2C2_MspInit 0 */ + /* USER CODE BEGIN I2C2_MspInit 0 */ - /* USER CODE END I2C2_MspInit 0 */ + /* USER CODE END I2C2_MspInit 0 */ /** Initializes the peripherals clock */ @@ -411,27 +414,27 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) /* Peripheral clock enable */ __HAL_RCC_I2C2_CLK_ENABLE(); - /* USER CODE BEGIN I2C2_MspInit 1 */ + /* USER CODE BEGIN I2C2_MspInit 1 */ - /* USER CODE END I2C2_MspInit 1 */ + /* USER CODE END I2C2_MspInit 1 */ } } /** -* @brief I2C MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ + * @brief I2C MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hi2c: I2C handle pointer + * @retval None + */ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) { if(hi2c->Instance==I2C2) { - /* USER CODE BEGIN I2C2_MspDeInit 0 */ + /* USER CODE BEGIN I2C2_MspDeInit 0 */ - /* USER CODE END I2C2_MspDeInit 0 */ + /* USER CODE END I2C2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_I2C2_CLK_DISABLE(); @@ -443,72 +446,72 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12); - /* USER CODE BEGIN I2C2_MspDeInit 1 */ + /* USER CODE BEGIN I2C2_MspDeInit 1 */ - /* USER CODE END I2C2_MspDeInit 1 */ + /* USER CODE END I2C2_MspDeInit 1 */ } } /** -* @brief PKA MSP Initialization -* This function configures the hardware resources used in this example -* @param hpka: PKA handle pointer -* @retval None -*/ + * @brief PKA MSP Initialization + * This function configures the hardware resources used in this example + * @param hpka: PKA handle pointer + * @retval None + */ void HAL_PKA_MspInit(PKA_HandleTypeDef* hpka) { if(hpka->Instance==PKA) { - /* USER CODE BEGIN PKA_MspInit 0 */ + /* USER CODE BEGIN PKA_MspInit 0 */ - /* USER CODE END PKA_MspInit 0 */ + /* USER CODE END PKA_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_PKA_CLK_ENABLE(); - /* USER CODE BEGIN PKA_MspInit 1 */ + /* USER CODE BEGIN PKA_MspInit 1 */ - /* USER CODE END PKA_MspInit 1 */ + /* USER CODE END PKA_MspInit 1 */ } } /** -* @brief PKA MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hpka: PKA handle pointer -* @retval None -*/ + * @brief PKA MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hpka: PKA handle pointer + * @retval None + */ void HAL_PKA_MspDeInit(PKA_HandleTypeDef* hpka) { if(hpka->Instance==PKA) { - /* USER CODE BEGIN PKA_MspDeInit 0 */ + /* USER CODE BEGIN PKA_MspDeInit 0 */ - /* USER CODE END PKA_MspDeInit 0 */ + /* USER CODE END PKA_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_PKA_CLK_DISABLE(); - /* USER CODE BEGIN PKA_MspDeInit 1 */ + /* USER CODE BEGIN PKA_MspDeInit 1 */ - /* USER CODE END PKA_MspDeInit 1 */ + /* USER CODE END PKA_MspDeInit 1 */ } } /** -* @brief RNG MSP Initialization -* This function configures the hardware resources used in this example -* @param hrng: RNG handle pointer -* @retval None -*/ + * @brief RNG MSP Initialization + * This function configures the hardware resources used in this example + * @param hrng: RNG handle pointer + * @retval None + */ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hrng->Instance==RNG) { - /* USER CODE BEGIN RNG_MspInit 0 */ + /* USER CODE BEGIN RNG_MspInit 0 */ - /* USER CODE END RNG_MspInit 0 */ + /* USER CODE END RNG_MspInit 0 */ /** Initializes the peripherals clock */ @@ -521,51 +524,51 @@ void HAL_RNG_MspInit(RNG_HandleTypeDef* hrng) /* Peripheral clock enable */ __HAL_RCC_RNG_CLK_ENABLE(); - /* USER CODE BEGIN RNG_MspInit 1 */ + /* USER CODE BEGIN RNG_MspInit 1 */ - /* USER CODE END RNG_MspInit 1 */ + /* USER CODE END RNG_MspInit 1 */ } } /** -* @brief RNG MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hrng: RNG handle pointer -* @retval None -*/ + * @brief RNG MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hrng: RNG handle pointer + * @retval None + */ void HAL_RNG_MspDeInit(RNG_HandleTypeDef* hrng) { if(hrng->Instance==RNG) { - /* USER CODE BEGIN RNG_MspDeInit 0 */ + /* USER CODE BEGIN RNG_MspDeInit 0 */ - /* USER CODE END RNG_MspDeInit 0 */ + /* USER CODE END RNG_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_RNG_CLK_DISABLE(); - /* USER CODE BEGIN RNG_MspDeInit 1 */ + /* USER CODE BEGIN RNG_MspDeInit 1 */ - /* USER CODE END RNG_MspDeInit 1 */ + /* USER CODE END RNG_MspDeInit 1 */ } } /** -* @brief SPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ + * @brief SPI MSP Initialization + * This function configures the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hspi->Instance==SPI6) { - /* USER CODE BEGIN SPI6_MspInit 0 */ + /* USER CODE BEGIN SPI6_MspInit 0 */ - /* USER CODE END SPI6_MspInit 0 */ + /* USER CODE END SPI6_MspInit 0 */ /** Initializes the peripherals clock */ @@ -630,27 +633,27 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) /* SPI6 interrupt Init */ HAL_NVIC_SetPriority(SPI6_IRQn, 2, 0); HAL_NVIC_EnableIRQ(SPI6_IRQn); - /* USER CODE BEGIN SPI6_MspInit 1 */ + /* USER CODE BEGIN SPI6_MspInit 1 */ - /* USER CODE END SPI6_MspInit 1 */ + /* USER CODE END SPI6_MspInit 1 */ } } /** -* @brief SPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ + * @brief SPI MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hspi: SPI handle pointer + * @retval None + */ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) { if(hspi->Instance==SPI6) { - /* USER CODE BEGIN SPI6_MspDeInit 0 */ + /* USER CODE BEGIN SPI6_MspDeInit 0 */ - /* USER CODE END SPI6_MspDeInit 0 */ + /* USER CODE END SPI6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_SPI6_CLK_DISABLE(); @@ -667,73 +670,73 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) /* SPI6 interrupt DeInit */ HAL_NVIC_DisableIRQ(SPI6_IRQn); - /* USER CODE BEGIN SPI6_MspDeInit 1 */ + /* USER CODE BEGIN SPI6_MspDeInit 1 */ - /* USER CODE END SPI6_MspDeInit 1 */ + /* USER CODE END SPI6_MspDeInit 1 */ } } /** -* @brief TIM_Base MSP Initialization -* This function configures the hardware resources used in this example -* @param htim_base: TIM_Base handle pointer -* @retval None -*/ + * @brief TIM_Base MSP Initialization + * This function configures the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { if(htim_base->Instance==TIM2) { - /* USER CODE BEGIN TIM2_MspInit 0 */ + /* USER CODE BEGIN TIM2_MspInit 0 */ - /* USER CODE END TIM2_MspInit 0 */ + /* USER CODE END TIM2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM2_CLK_ENABLE(); /* TIM2 interrupt Init */ HAL_NVIC_SetPriority(TIM2_IRQn, 2, 0); HAL_NVIC_EnableIRQ(TIM2_IRQn); - /* USER CODE BEGIN TIM2_MspInit 1 */ + /* USER CODE BEGIN TIM2_MspInit 1 */ - /* USER CODE END TIM2_MspInit 1 */ + /* USER CODE END TIM2_MspInit 1 */ } else if(htim_base->Instance==TIM3) { - /* USER CODE BEGIN TIM3_MspInit 0 */ + /* USER CODE BEGIN TIM3_MspInit 0 */ - /* USER CODE END TIM3_MspInit 0 */ + /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); /* TIM3 interrupt Init */ HAL_NVIC_SetPriority(TIM3_IRQn, 2, 0); HAL_NVIC_EnableIRQ(TIM3_IRQn); - /* USER CODE BEGIN TIM3_MspInit 1 */ + /* USER CODE BEGIN TIM3_MspInit 1 */ - /* USER CODE END TIM3_MspInit 1 */ + /* USER CODE END TIM3_MspInit 1 */ } else if(htim_base->Instance==TIM5) { - /* USER CODE BEGIN TIM5_MspInit 0 */ + /* USER CODE BEGIN TIM5_MspInit 0 */ - /* USER CODE END TIM5_MspInit 0 */ + /* USER CODE END TIM5_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM5_CLK_ENABLE(); /* TIM5 interrupt Init */ HAL_NVIC_SetPriority(TIM5_IRQn, 2, 0); HAL_NVIC_EnableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspInit 1 */ + /* USER CODE BEGIN TIM5_MspInit 1 */ - /* USER CODE END TIM5_MspInit 1 */ + /* USER CODE END TIM5_MspInit 1 */ } else if(htim_base->Instance==TIM6) { - /* USER CODE BEGIN TIM6_MspInit 0 */ + /* USER CODE BEGIN TIM6_MspInit 0 */ - /* USER CODE END TIM6_MspInit 0 */ + /* USER CODE END TIM6_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM6_CLK_ENABLE(); - /* USER CODE BEGIN TIM6_MspInit 1 */ + /* USER CODE BEGIN TIM6_MspInit 1 */ - /* USER CODE END TIM6_MspInit 1 */ + /* USER CODE END TIM6_MspInit 1 */ } } @@ -743,9 +746,9 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) GPIO_InitTypeDef GPIO_InitStruct = {0}; if(htim->Instance==TIM2) { - /* USER CODE BEGIN TIM2_MspPostInit 0 */ + /* USER CODE BEGIN TIM2_MspPostInit 0 */ - /* USER CODE END TIM2_MspPostInit 0 */ + /* USER CODE END TIM2_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); /**TIM2 GPIO Configuration @@ -758,91 +761,91 @@ void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; HAL_GPIO_Init(PWM_LCD_BL_GPIO_Port, &GPIO_InitStruct); - /* USER CODE BEGIN TIM2_MspPostInit 1 */ + /* USER CODE BEGIN TIM2_MspPostInit 1 */ - /* USER CODE END TIM2_MspPostInit 1 */ + /* USER CODE END TIM2_MspPostInit 1 */ } } /** -* @brief TIM_Base MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param htim_base: TIM_Base handle pointer -* @retval None -*/ + * @brief TIM_Base MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param htim_base: TIM_Base handle pointer + * @retval None + */ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base) { if(htim_base->Instance==TIM2) { - /* USER CODE BEGIN TIM2_MspDeInit 0 */ + /* USER CODE BEGIN TIM2_MspDeInit 0 */ - /* USER CODE END TIM2_MspDeInit 0 */ + /* USER CODE END TIM2_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM2_CLK_DISABLE(); /* TIM2 interrupt DeInit */ HAL_NVIC_DisableIRQ(TIM2_IRQn); - /* USER CODE BEGIN TIM2_MspDeInit 1 */ + /* USER CODE BEGIN TIM2_MspDeInit 1 */ - /* USER CODE END TIM2_MspDeInit 1 */ + /* USER CODE END TIM2_MspDeInit 1 */ } else if(htim_base->Instance==TIM3) { - /* USER CODE BEGIN TIM3_MspDeInit 0 */ + /* USER CODE BEGIN TIM3_MspDeInit 0 */ - /* USER CODE END TIM3_MspDeInit 0 */ + /* USER CODE END TIM3_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM3_CLK_DISABLE(); /* TIM3 interrupt DeInit */ HAL_NVIC_DisableIRQ(TIM3_IRQn); - /* USER CODE BEGIN TIM3_MspDeInit 1 */ + /* USER CODE BEGIN TIM3_MspDeInit 1 */ - /* USER CODE END TIM3_MspDeInit 1 */ + /* USER CODE END TIM3_MspDeInit 1 */ } else if(htim_base->Instance==TIM5) { - /* USER CODE BEGIN TIM5_MspDeInit 0 */ + /* USER CODE BEGIN TIM5_MspDeInit 0 */ - /* USER CODE END TIM5_MspDeInit 0 */ + /* USER CODE END TIM5_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM5_CLK_DISABLE(); /* TIM5 interrupt DeInit */ HAL_NVIC_DisableIRQ(TIM5_IRQn); - /* USER CODE BEGIN TIM5_MspDeInit 1 */ + /* USER CODE BEGIN TIM5_MspDeInit 1 */ - /* USER CODE END TIM5_MspDeInit 1 */ + /* USER CODE END TIM5_MspDeInit 1 */ } else if(htim_base->Instance==TIM6) { - /* USER CODE BEGIN TIM6_MspDeInit 0 */ + /* USER CODE BEGIN TIM6_MspDeInit 0 */ - /* USER CODE END TIM6_MspDeInit 0 */ + /* USER CODE END TIM6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM6_CLK_DISABLE(); - /* USER CODE BEGIN TIM6_MspDeInit 1 */ + /* USER CODE BEGIN TIM6_MspDeInit 1 */ - /* USER CODE END TIM6_MspDeInit 1 */ + /* USER CODE END TIM6_MspDeInit 1 */ } } /** -* @brief SMARTCARD MSP Initialization -* This function configures the hardware resources used in this example -* @param hsmartcard: SMARTCARD handle pointer -* @retval None -*/ + * @brief SMARTCARD MSP Initialization + * This function configures the hardware resources used in this example + * @param hsmartcard: SMARTCARD handle pointer + * @retval None + */ void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef* hsmartcard) { GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hsmartcard->Instance==USART6) { - /* USER CODE BEGIN USART6_MspInit 0 */ + /* USER CODE BEGIN USART6_MspInit 0 */ - /* USER CODE END USART6_MspInit 0 */ + /* USER CODE END USART6_MspInit 0 */ /** Initializes the peripherals clock */ @@ -888,27 +891,27 @@ void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef* hsmartcard) /* USART6 interrupt Init */ HAL_NVIC_SetPriority(USART6_IRQn, 2, 0); HAL_NVIC_EnableIRQ(USART6_IRQn); - /* USER CODE BEGIN USART6_MspInit 1 */ + /* USER CODE BEGIN USART6_MspInit 1 */ - /* USER CODE END USART6_MspInit 1 */ + /* USER CODE END USART6_MspInit 1 */ } } /** -* @brief SMARTCARD MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hsmartcard: SMARTCARD handle pointer -* @retval None -*/ + * @brief SMARTCARD MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hsmartcard: SMARTCARD handle pointer + * @retval None + */ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef* hsmartcard) { if(hsmartcard->Instance==USART6) { - /* USER CODE BEGIN USART6_MspDeInit 0 */ + /* USER CODE BEGIN USART6_MspDeInit 0 */ - /* USER CODE END USART6_MspDeInit 0 */ + /* USER CODE END USART6_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USART6_CLK_DISABLE(); @@ -920,27 +923,27 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef* hsmartcard) /* USART6 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART6_IRQn); - /* USER CODE BEGIN USART6_MspDeInit 1 */ + /* USER CODE BEGIN USART6_MspDeInit 1 */ - /* USER CODE END USART6_MspDeInit 1 */ + /* USER CODE END USART6_MspDeInit 1 */ } } /** -* @brief PCD MSP Initialization -* This function configures the hardware resources used in this example -* @param hpcd: PCD handle pointer -* @retval None -*/ + * @brief PCD MSP Initialization + * This function configures the hardware resources used in this example + * @param hpcd: PCD handle pointer + * @retval None + */ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) { RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; if(hpcd->Instance==USB_DRD_FS) { - /* USER CODE BEGIN USB_DRD_FS_MspInit 0 */ + /* USER CODE BEGIN USB_DRD_FS_MspInit 0 */ - /* USER CODE END USB_DRD_FS_MspInit 0 */ + /* USER CODE END USB_DRD_FS_MspInit 0 */ /** Initializes the peripherals clock */ @@ -958,35 +961,35 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) /* USB_DRD_FS interrupt Init */ HAL_NVIC_SetPriority(USB_DRD_FS_IRQn, 2, 0); HAL_NVIC_EnableIRQ(USB_DRD_FS_IRQn); - /* USER CODE BEGIN USB_DRD_FS_MspInit 1 */ + /* USER CODE BEGIN USB_DRD_FS_MspInit 1 */ - /* USER CODE END USB_DRD_FS_MspInit 1 */ + /* USER CODE END USB_DRD_FS_MspInit 1 */ } } /** -* @brief PCD MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hpcd: PCD handle pointer -* @retval None -*/ + * @brief PCD MSP De-Initialization + * This function freeze the hardware resources used in this example + * @param hpcd: PCD handle pointer + * @retval None + */ void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) { if(hpcd->Instance==USB_DRD_FS) { - /* USER CODE BEGIN USB_DRD_FS_MspDeInit 0 */ + /* USER CODE BEGIN USB_DRD_FS_MspDeInit 0 */ - /* USER CODE END USB_DRD_FS_MspDeInit 0 */ + /* USER CODE END USB_DRD_FS_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_USB_CLK_DISABLE(); /* USB_DRD_FS interrupt DeInit */ HAL_NVIC_DisableIRQ(USB_DRD_FS_IRQn); - /* USER CODE BEGIN USB_DRD_FS_MspDeInit 1 */ + /* USER CODE BEGIN USB_DRD_FS_MspDeInit 1 */ - /* USER CODE END USB_DRD_FS_MspDeInit 1 */ + /* USER CODE END USB_DRD_FS_MspDeInit 1 */ } } diff --git a/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h index a2d20dd..99bb85d 100644 --- a/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h +++ b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -266,11 +266,6 @@ typedef struct uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ - uint32_t RESERVED3[246]; /*!< Reserved, */ - __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ - __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ } CRC_TypeDef; /** @@ -4424,7 +4419,7 @@ typedef struct #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ -#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ /******************** Bit definition for ADC_DIFSEL register ****************/ #define ADC_DIFSEL_DIFSEL_Pos (0U) @@ -11973,7 +11968,7 @@ typedef struct #define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ #define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk #define GPIO_HSLVR_HSLV11_Pos (11U) -#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ #define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk #define GPIO_HSLVR_HSLV12_Pos (12U) #define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ @@ -12023,7 +12018,7 @@ typedef struct #define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ #define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk #define GPIO_SECCFGR_SEC11_Pos (11U) -#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ #define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk #define GPIO_SECCFGR_SEC12_Pos (12U) #define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ diff --git a/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h index db0071a..ec95db9 100644 --- a/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h +++ b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -81,11 +81,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.1 + * @brief CMSIS Device version number 1.4.0 */ #define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32H5_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32H5_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\ @@ -99,7 +99,15 @@ /** @addtogroup Device_Included * @{ */ -#if defined(STM32H573xx) +#if defined(STM32H5F5xx) + #include "stm32h5f5xx.h" +#elif defined(STM32H5F4xx) + #include "stm32h5f4xx.h" +#elif defined(STM32H5E5xx) + #include "stm32h5e5xx.h" +#elif defined(STM32H5E4xx) + #include "stm32h5e4xx.h" +#elif defined(STM32H573xx) #include "stm32h573xx.h" #elif defined(STM32H563xx) #include "stm32h563xx.h" diff --git a/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md new file mode 100644 index 0000000..d1a7d01 --- /dev/null +++ b/stm32/Drivers/CMSIS/Device/ST/STM32H5xx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2021 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index 996abd9..f719763 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -538,6 +538,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -1299,22 +1303,22 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL #endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1481,7 +1485,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -3695,7 +3699,8 @@ extern "C" { #endif #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3946,8 +3951,8 @@ extern "C" { */ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ - defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) + defined (STM32WBA) || defined (STM32H5) || \ + defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h index aff3a51..3725b52 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h @@ -490,6 +490,26 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP */ + #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) #define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) #define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP) @@ -530,6 +550,25 @@ extern HAL_TickFreqTypeDef uwTickFreq; #define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP) #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */ +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP */ /** * @} */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h index 0c70003..07560a1 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h @@ -198,7 +198,7 @@ typedef struct #if defined (FLASH_EDATAR_EDATA_EN) #define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash high-cycle data half-word (16-bit)at a specified address */ -#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash +#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash high-cycle data half-word (32-bit)at a specified address */ #endif /* FLASH_EDATAR_EDATA_EN */ #endif /* __ARM_FEATURE_CMSE */ @@ -650,6 +650,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); /* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); + /** * @} */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h index 5921a69..938835a 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash_ex.h @@ -570,61 +570,58 @@ byte configuration */ /** @defgroup FLASH_OB_Write_Protection_Sectors FLASH Option Bytes Write Protection Sectors * @{ */ -#if (FLASH_SECTOR_NB == 128) -#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ -#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ -#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ -#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ -#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ -#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ -#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ -#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ -#define OB_WRP_SECTOR_32TO35 0x00000100U /*!< Write protection of Sector32 to Sector35 */ -#define OB_WRP_SECTOR_36TO39 0x00000200U /*!< Write protection of Sector36 to Sector39 */ -#define OB_WRP_SECTOR_40TO43 0x00000400U /*!< Write protection of Sector40 to Sector43 */ -#define OB_WRP_SECTOR_44TO47 0x00000800U /*!< Write protection of Sector44 to Sector47 */ -#define OB_WRP_SECTOR_48TO51 0x00001000U /*!< Write protection of Sector48 to Sector51 */ -#define OB_WRP_SECTOR_52TO55 0x00002000U /*!< Write protection of Sector52 to Sector55 */ -#define OB_WRP_SECTOR_56TO59 0x00004000U /*!< Write protection of Sector56 to Sector59 */ -#define OB_WRP_SECTOR_60TO63 0x00008000U /*!< Write protection of Sector60 to Sector63 */ -#define OB_WRP_SECTOR_64TO67 0x00010000U /*!< Write protection of Sector64 to Sector67 */ -#define OB_WRP_SECTOR_68TO71 0x00020000U /*!< Write protection of Sector68 to Sector71 */ -#define OB_WRP_SECTOR_72TO75 0x00040000U /*!< Write protection of Sector72 to Sector75 */ -#define OB_WRP_SECTOR_76TO79 0x00080000U /*!< Write protection of Sector76 to Sector79 */ -#define OB_WRP_SECTOR_80TO83 0x00100000U /*!< Write protection of Sector80 to Sector83 */ -#define OB_WRP_SECTOR_84TO87 0x00200000U /*!< Write protection of Sector84 to Sector87 */ -#define OB_WRP_SECTOR_88TO91 0x00400000U /*!< Write protection of Sector88 to Sector91 */ -#define OB_WRP_SECTOR_92TO95 0x00800000U /*!< Write protection of Sector92 to Sector95 */ -#define OB_WRP_SECTOR_96TO99 0x01000000U /*!< Write protection of Sector96 to Sector99 */ -#define OB_WRP_SECTOR_100TO103 0x02000000U /*!< Write protection of Sector100 to Sector103 */ -#define OB_WRP_SECTOR_104TO107 0x04000000U /*!< Write protection of Sector104 to Sector107 */ -#define OB_WRP_SECTOR_108TO111 0x08000000U /*!< Write protection of Sector108 to Sector111 */ -#define OB_WRP_SECTOR_112TO115 0x10000000U /*!< Write protection of Sector112 to Sector115 */ -#define OB_WRP_SECTOR_116TO119 0x20000000U /*!< Write protection of Sector116 to Sector119 */ -#define OB_WRP_SECTOR_120TO123 0x40000000U /*!< Write protection of Sector120 to Sector123 */ -#define OB_WRP_SECTOR_124TO127 0x80000000U /*!< Write protection of Sector124 to Sector127 */ -#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU /*!< Write protection of all Sectors */ -#elif (FLASH_SECTOR_NB == 32) -#define OB_WRP_SECTOR_0TO3 0x00000001U /*!< Write protection of Sector0 to Sector3 */ -#define OB_WRP_SECTOR_4TO7 0x00000002U /*!< Write protection of Sector4 to Sector7 */ -#define OB_WRP_SECTOR_8TO11 0x00000004U /*!< Write protection of Sector8 to Sector11 */ -#define OB_WRP_SECTOR_12TO15 0x00000008U /*!< Write protection of Sector12 to Sector15 */ -#define OB_WRP_SECTOR_16TO19 0x00000010U /*!< Write protection of Sector16 to Sector19 */ -#define OB_WRP_SECTOR_20TO23 0x00000020U /*!< Write protection of Sector20 to Sector23 */ -#define OB_WRP_SECTOR_24TO27 0x00000040U /*!< Write protection of Sector24 to Sector27 */ -#define OB_WRP_SECTOR_28TO31 0x00000080U /*!< Write protection of Sector28 to Sector31 */ -#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#if (FLASH_SECTOR_NB == 8) +#define OB_WRP_SECTOR_0 0x0000000000000001U /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 0x0000000000000002U /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 0x0000000000000004U /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 0x0000000000000008U /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 0x0000000000000010U /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 0x0000000000000020U /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 0x0000000000000040U /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 0x0000000000000080U /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_ALL 0x00000000000000FFU /*!< Write protection of all Sectors */ #else -#define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_ALL 0x000000FFU /*!< Write protection of all Sectors */ +#define OB_WRP_SECTOR_0TO3 0x0000000000000001U /*!< Write protection of Sector0 to Sector3 */ +#define OB_WRP_SECTOR_4TO7 0x0000000000000002U /*!< Write protection of Sector4 to Sector7 */ +#define OB_WRP_SECTOR_8TO11 0x0000000000000004U /*!< Write protection of Sector8 to Sector11 */ +#define OB_WRP_SECTOR_12TO15 0x0000000000000008U /*!< Write protection of Sector12 to Sector15 */ +#define OB_WRP_SECTOR_16TO19 0x0000000000000010U /*!< Write protection of Sector16 to Sector19 */ +#define OB_WRP_SECTOR_20TO23 0x0000000000000020U /*!< Write protection of Sector20 to Sector23 */ +#define OB_WRP_SECTOR_24TO27 0x0000000000000040U /*!< Write protection of Sector24 to Sector27 */ +#define OB_WRP_SECTOR_28TO31 0x0000000000000080U /*!< Write protection of Sector28 to Sector31 */ +#if (FLASH_SECTOR_NB == 128) +#define OB_WRP_SECTOR_32TO35 0x0000000000000100U /*!< Write protection of Sector32 to Sector35 */ +#define OB_WRP_SECTOR_36TO39 0x0000000000000200U /*!< Write protection of Sector36 to Sector39 */ +#define OB_WRP_SECTOR_40TO43 0x0000000000000400U /*!< Write protection of Sector40 to Sector43 */ +#define OB_WRP_SECTOR_44TO47 0x0000000000000800U /*!< Write protection of Sector44 to Sector47 */ +#define OB_WRP_SECTOR_48TO51 0x0000000000001000U /*!< Write protection of Sector48 to Sector51 */ +#define OB_WRP_SECTOR_52TO55 0x0000000000002000U /*!< Write protection of Sector52 to Sector55 */ +#define OB_WRP_SECTOR_56TO59 0x0000000000004000U /*!< Write protection of Sector56 to Sector59 */ +#define OB_WRP_SECTOR_60TO63 0x0000000000008000U /*!< Write protection of Sector60 to Sector63 */ +#define OB_WRP_SECTOR_64TO67 0x0000000000010000U /*!< Write protection of Sector64 to Sector67 */ +#define OB_WRP_SECTOR_68TO71 0x0000000000020000U /*!< Write protection of Sector68 to Sector71 */ +#define OB_WRP_SECTOR_72TO75 0x0000000000040000U /*!< Write protection of Sector72 to Sector75 */ +#define OB_WRP_SECTOR_76TO79 0x0000000000080000U /*!< Write protection of Sector76 to Sector79 */ +#define OB_WRP_SECTOR_80TO83 0x0000000000100000U /*!< Write protection of Sector80 to Sector83 */ +#define OB_WRP_SECTOR_84TO87 0x0000000000200000U /*!< Write protection of Sector84 to Sector87 */ +#define OB_WRP_SECTOR_88TO91 0x0000000000400000U /*!< Write protection of Sector88 to Sector91 */ +#define OB_WRP_SECTOR_92TO95 0x0000000000800000U /*!< Write protection of Sector92 to Sector95 */ +#define OB_WRP_SECTOR_96TO99 0x0000000001000000U /*!< Write protection of Sector96 to Sector99 */ +#define OB_WRP_SECTOR_100TO103 0x0000000002000000U /*!< Write protection of Sector100 to Sector103 */ +#define OB_WRP_SECTOR_104TO107 0x0000000004000000U /*!< Write protection of Sector104 to Sector107 */ +#define OB_WRP_SECTOR_108TO111 0x0000000008000000U /*!< Write protection of Sector108 to Sector111 */ +#define OB_WRP_SECTOR_112TO115 0x0000000010000000U /*!< Write protection of Sector112 to Sector115 */ +#define OB_WRP_SECTOR_116TO119 0x0000000020000000U /*!< Write protection of Sector116 to Sector119 */ +#define OB_WRP_SECTOR_120TO123 0x0000000040000000U /*!< Write protection of Sector120 to Sector123 */ +#define OB_WRP_SECTOR_124TO127 0x0000000080000000U /*!< Write protection of Sector124 to Sector127 */ #endif /* (FLASH_SECTOR_NB == 128) */ +#endif /* (FLASH_SECTOR_NB == 8) */ +#if (FLASH_SECTOR_NB == 32) +#define OB_WRP_SECTOR_ALL 0x00000000000000FFU /*!< Write protection of all Sectors */ +#elif (FLASH_SECTOR_NB == 128) +#define OB_WRP_SECTOR_ALL 0x00000000FFFFFFFFU /*!< Write protection of all Sectors */ +#endif /* FLASH_SECTOR_NB == 32 */ + /** * @} */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h index cc0cd19..13613c1 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_gpio_ex.h @@ -248,7 +248,7 @@ extern "C" { #if defined(USART11) #define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */ #endif /* USART11 */ -#define GPIO_AF7_ETH ((uint8_t)0x07) /* ETH Alternate Function mapping */ + /** * @brief AF 8 selection */ @@ -340,6 +340,9 @@ extern "C" { #if defined(USB_DRD_FS) #define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ #endif /* USB_DRD_FS */ +#if defined(LTDC) +#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */ +#endif /* LTDC */ /** * @brief AF 11 selection diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h index 5c5720d..e382f25 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_hash.h @@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); -HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h index 86a762c..ab9f8e3 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pcd.h @@ -524,6 +524,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); #define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND #define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS USB_DRD_SET_CHEP_KIND +#define PCD_CLEAR_OUT_STATUS USB_DRD_CLEAR_CHEP_KIND /** * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h index d2f37a2..8063f9d 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc.h @@ -189,8 +189,8 @@ typedef struct */ #define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock */ -#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock */ +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Analog clock source for LSE clock Bypassed*/ +#define RCC_LSE_BYPASS_DIGITAL ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External Digital clock source for LSE clock Bypassed */ /** * @} */ @@ -873,7 +873,6 @@ typedef struct #define __HAL_RCC_ETHTX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHTXEN) #define __HAL_RCC_ETHRX_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHRXEN) - #endif /*ETH*/ #define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TZSC1EN) @@ -1123,6 +1122,9 @@ typedef struct #define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) #endif /* SAES */ +#if defined(CCB) +#define __HAL_RCC_CCB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CCBEN) +#endif /* CCB */ #define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) @@ -1210,7 +1212,6 @@ typedef struct #if defined(OCTOSPI1) #define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_OCTOSPI1EN) #endif /* OCTOSPI1 */ - /** * @} */ @@ -1763,7 +1764,6 @@ typedef struct } while(0) #endif /*USB_DRD_FS*/ - #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) @@ -1981,7 +1981,6 @@ typedef struct #endif /* VREFBUF */ #define __HAL_RCC_RTC_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) - /** * @} */ @@ -2942,7 +2941,6 @@ typedef struct #if defined(SAES) #define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) #endif /* SAES*/ - /** * @} */ @@ -3416,7 +3414,6 @@ typedef struct #if defined(VREFBUF) #define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) #endif /* VREFBUF */ - /** * @} */ @@ -4094,7 +4091,6 @@ typedef struct #endif /* VREFBUF */ #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3LPENR, RCC_APB3LPENR_RTCAPBLPEN) - /** * @} */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h index 3675a1c..d3a9507 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_rcc_ex.h @@ -541,7 +541,6 @@ typedef struct #if defined(I3C2) #define RCC_PERIPHCLK_I3C2 ((uint64_t)0x100000000000U) #endif /* I3C2 */ - /** * @} */ @@ -1267,9 +1266,11 @@ typedef struct /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource * @{ */ -#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ -#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00000000U) /*!< Synchro Signal source GPIO */ +#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#if defined(USB_DRD_FS) +#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +#endif /* USB_DRD_FS */ /** * @} */ @@ -1383,7 +1384,6 @@ typedef struct #define __HAL_RCC_TIMIC_ENABLE() SET_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< HSI/1024, CSI/128 and HSI/8 generation for Timers 12,15 and LPTimer2 Input capture */ #define __HAL_RCC_TIMIC_DISABLE() CLEAR_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) /*!< No clock available for Timers Input capture */ - /** @brief Macro to configure the PLL2 clock source. * @note This function must be used only when all PLL2 is disabled. * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. @@ -3736,10 +3736,11 @@ typedef struct ((VALUE) == RCC_TIMPRES_ACTIVATED)) #if defined(CRS) - +#if defined(USB_DRD_FS) #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) +#endif /* USB_DRD_FS */ #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h index 6a50b17..c698bbd 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_bus.h @@ -733,7 +733,6 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG * @arg @ref LL_AHB1_GRP1_PERIPH_ETH (*) * @arg @ref LL_AHB1_GRP1_PERIPH_ETHTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHRX (*) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 (*) diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h index e17e145..4a68b98 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_dma.h @@ -2936,7 +2936,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, ui * @brief Set trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -2963,7 +2963,7 @@ __STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t * @brief Get trigger polarity. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -2988,7 +2988,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint * @brief Set trigger Mode. * @note This API is used for all available DMA channels. * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode - * @param DMAx DMAx Instance + * @param DMAx DMAx Instance * @param Channel This parameter can be one of the following values: * @arg @ref LL_DMA_CHANNEL_0 * @arg @ref LL_DMA_CHANNEL_1 @@ -6314,7 +6314,7 @@ uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +uint32_t LL_DMA_CreateLinkNode(const LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h index e19224a..12a6c19 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_exti.h @@ -975,7 +975,6 @@ __STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1019,10 +1018,10 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) * @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63 * @param ExtiLine This parameter can be a combination of the following values: * @arg @ref LL_EXTI_LINE_46 + * @arg @ref LL_EXTI_LINE_49 * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1147,7 +1146,6 @@ __STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1193,7 +1191,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -1412,7 +1409,6 @@ __STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval None */ @@ -1462,7 +1458,6 @@ __STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_50 * @arg @ref LL_EXTI_LINE_53 * - * (*) : Not available for all stm32h5xxxx family lines. * @note Please check each device line mapping for EXTI Line availability * @retval State of bit (1 or 0). */ @@ -2034,7 +2029,6 @@ __STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) * @arg @ref LL_EXTI_LINE_56 * @arg @ref LL_EXTI_LINE_57 * @arg @ref LL_EXTI_LINE_58 - * @arg @ref LL_EXTI_LINE_63 * @arg @ref LL_EXTI_LINE_ALL_32_63 * @note Please check each device line mapping for EXTI Line availability * @retval None diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h index 44040c9..5787274 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_rcc.h @@ -167,6 +167,10 @@ typedef struct #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/ #endif /* EXTERNAL_CLOCK_VALUE */ +/** + * @} + */ + /** * @} */ @@ -1178,6 +1182,96 @@ typedef struct * @} */ +#if defined(PLAY1) +/** @defgroup RCC_LL_EC_PLAY1 Peripheral PLAY1 get clock source + * @{ + */ +#define LL_RCC_PLAY1_CLKSOURCE RCC_CCIPR3_PLAY1SEL /*!< PLAY1 Clock source selection */ +/** + * @} + */ +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** @defgroup RCC_LL_EC_OTGFS Peripheral OTGFS get clock source + * @{ + */ +#define LL_RCC_OTGFS_CLKSOURCE RCC_CCIPR4_OTGFSSEL /*!< OTGFS Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** @defgroup RCC_LL_EC_OTGHS Peripheral OTGHS get clock source + * @{ + */ +#define LL_RCC_OTGHS_CLKSOURCE RCC_CCIPR4_OTGHSSEL /*!< OTGHS Clock source selection */ +/** + * @} + */ +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** @defgroup RCC_LL_EC_OTGPHY Peripheral OTGPHY get clock source + * @{ + */ +#define LL_RCC_OTGPHY_CLKSOURCE RCC_CCIPR4_OTGPHYREFCKSEL /*!< OTGPHY Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** @defgroup RCC_LL_EC_ETH Peripheral ETH get clock source + * @{ + */ +#define LL_RCC_ETH_CLKSOURCE RCC_CCIPR4_ETHCLKSEL /*!< ETH Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(OCTOSPI2) +/** @defgroup RCC_LL_EC_OCTOSPI2 Peripheral OCTOSPI2 get clock source + * @{ + */ +#define LL_RCC_OCTOSPI2_CLKSOURCE RCC_CCIPR5_OCTOSPI2SEL /*!< OctoSPI2 Clock source selection */ +/** + * @} + */ +#endif /* OCTOSOI2 */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR5_LTDCSEL /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(ADF1) +/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source + * @{ + */ +#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR5_ADF1SEL /*!< ADF1 Clock source selection */ +/** + * @} + */ +#endif /* ADF1 */ + +#if defined(MDF1) +/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source + * @{ + */ +#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR5_MDF1SEL /*!< MDF1 Clock source selection */ +/** + * @} + */ +#endif /* MDF1 */ + /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source * @{ */ @@ -1186,6 +1280,36 @@ typedef struct * @} */ +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** @defgroup RCC_LL_EC_ETHPTP Peripheral ETHPTP get clock source + * @{ + */ +#define LL_RCC_ETHPTP_CLKSOURCE RCC_CCIPR5_ETHPTPCLKSEL /*!< ETHPTP Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHT1SCLKSEL) +/** @defgroup RCC_LL_EC_ETHT1S Peripheral ETHT1S get clock source + * @{ + */ +#define LL_RCC_ETHT1S_CLKSOURCE RCC_CCIPR5_ETHT1SCLKSEL /*!< ETHT1S Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** @defgroup RCC_LL_EC_ETHREF Peripheral ETHREF get clock source + * @{ + */ +#define LL_RCC_ETHREF_CLKSOURCE RCC_CCIPR5_ETHREFCLKSEL /*!< ETHREF Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ + /** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source * @{ */ @@ -2548,9 +2672,12 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*) * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P @@ -2813,13 +2940,16 @@ __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) * @rmtoll CCIPR4 I3C1SEL LL_RCC_SetI3CClockSource\n * CCIPR4 I3C2SEL LL_RCC_SetI3CClockSource * @param I3CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I3C1_CLKSOURCE_PCLK1 (***) * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL3R (*) * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 (***) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (***) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * @retval None * @@ -3092,6 +3222,211 @@ __STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t OCTOSPIxSource) } #endif /* OCTOSPI1 */ +#if defined(PLAY1) +/** + * @brief Configure PLAY1 kernel clock source + * @rmtoll CCIPR3 PLAY1SEL LL_RCC_SetPLAY1ClockSource + * @param PLAYxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PCLK3 + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL2Q + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSE + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_LSI + * @arg @ref LL_RCC_PLAY1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPLAY1ClockSource(uint32_t PLAYxSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_PLAY1SEL, PLAYxSource); +} +#endif /* PLAY1 */ + +#if defined(USB_OTG_FS) +/** + * @brief Configure OTGFSx kernel clock source + * @rmtoll CCIPR4 OTGFSSEL LL_RCC_SetOTGFSClockSource + * @param OTGFSxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_HSI48 + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGFS_CLKSOURCE_CLK48 (*) + * @retval None + * + * (*) : Available only on STM32H5E5x/STM32H5F5x when OTG_HS PHY is enabled. + */ +__STATIC_INLINE void LL_RCC_SetOTGFSClockSource(uint32_t OTGFSxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGFSSEL, OTGFSxSource); +} +#endif /* USB_OTG_FS */ + +#if defined(USB_OTG_HS) +/** + * @brief Configure OTGHSx kernel clock source + * @rmtoll CCIPR4 OTGHSSEL LL_RCC_SetOTGHSClockSource + * @param OTGHSxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL3Q + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_HSE_DIV2 + * @arg @ref LL_RCC_OTGHS_CLKSOURCE_PLL1Q_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGHSClockSource(uint32_t OTGHSxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGHSSEL, OTGHSxSource); +} +#endif /* USB_OTG_HS */ + +#if defined(RCC_CCIPR4_OTGPHYREFCKSEL) +/** + * @brief Configure OTGPHYx kernel clock source + * @rmtoll CCIPR4 OTGPHYREFCKSEL LL_RCC_SetOTGPHYClockSource + * @param OTGPHYxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_16M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_19_2M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_20M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_24M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_26M + * @arg @ref LL_RCC_OTGPHYREFCKCLKSOURCE_32M + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOTGPHYClockSource(uint32_t OTGPHYxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_OTGPHYREFCKSEL, OTGPHYxSource); +} +#endif /* RCC_CCIPR4_OTGPHYREFCKSEL */ + +#if defined(OCTOSPI2) +/** + * @brief Configure OCTOSPI2 kernel clock source + * @rmtoll CCIPR5 OCTOSPI2SEL LL_RCC_SetOCTOSPI2ClockSource + * @param OCTOSPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_HCLK + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_PLL2R + * @arg @ref LL_RCC_OSPI2_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetOCTOSPI2ClockSource(uint32_t OCTOSPIxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_OCTOSPI2SEL, OCTOSPIxSource); +} +#endif /* OCTOSPI2 */ + +#if defined(LTDC) +/** + * @brief Configure LTDCx kernel clock source + * @rmtoll CCIPR5 LTDCSEL LL_RCC_SetLTDCClockSource + * @param LTDCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3R + * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t LTDCxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_LTDCSEL, LTDCxSource); +} +#endif /* LTDC */ + +#if defined(ADF1) +/** + * @brief Configure ADF1 kernel clock source + * @rmtoll CCIPR5 ADF1SEL LL_RCC_SetADF1ClockSource + * @param ADFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_ADF1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t ADFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ADF1SEL, ADFxSource); +} +#endif /* ADF1 */ + +#if defined(MDF1) +/** + * @brief Configure MDF1 kernel clock source + * @rmtoll CCIPR5 MDF1SEL LL_RCC_SetMDF1ClockSource + * @param MDFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL2P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3P + * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN + * @arg @ref LL_RCC_MDF1_CLKSOURCE_CLKP + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t MDFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_MDF1SEL, MDFxSource); +} +#endif /* MDF1 */ + +#if defined(RCC_CCIPR4_ETHCLKSEL) +/** + * @brief Configure ETH kernel clock source + * @rmtoll CCIPR4 ETHSEL LL_RCC_SetETHClockSource + * @param ETHxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETH_CLKSOURCE_HSE + * @arg @ref LL_RCC_ETH_CLKSOURCE_PLL1Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHClockSource(uint32_t ETHxSource) +{ + MODIFY_REG(RCC->CCIPR4, RCC_CCIPR4_ETHCLKSEL, ETHxSource); +} +#endif /* RCC_CCIPR4_ETHCLKSEL */ + +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +/** + * @brief Configure ETHPTP kernel clock source + * @rmtoll CCIPR5 ETHPTPSEL LL_RCC_SetETHPTPClockSource + * @param ETHPTPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1R + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHPTP_CLKSOURCE_PLL3P + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHPTPClockSource(uint32_t ETHPTPxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHPTPCLKSEL, ETHPTPxSource); +} +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + +#if defined(RCC_CCIPR5_ETHT1SCLKSEL) +/** + * @brief Configure ETHT1S kernel clock source + * @rmtoll CCIPR5 ETHT1SSEL LL_RCC_SetETHT1SClockSource + * @param ETHT1SxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHT1S_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHT1S_CLKSOURCE_PLL1R + * @arg @ref LL_RCC_ETHT1S_CLKSOURCE_PLL3P + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHT1SClockSource(uint32_t ETHT1SxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHT1SCLKSEL, ETHT1SxSource); +} +#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ + +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +/** + * @brief Configure ETHREF kernel clock source + * @rmtoll CCIPR5 ETHREFSEL LL_RCC_SetETHREFClockSource + * @param ETHREFxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1Q + * @arg @ref LL_RCC_ETHREF_CLKSOURCE_PLL1R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetETHREFClockSource(uint32_t ETHREFxSource) +{ + MODIFY_REG(RCC->CCIPR5, RCC_CCIPR5_ETHREFCLKSEL, ETHREFxSource); +} +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ + /** * @brief Configure CLKP Kernel clock source * @rmtoll CCIPR5 CKPERSEL LL_RCC_SetCLKPClockSource @@ -3252,9 +3587,11 @@ __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource) * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (*) * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (*) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (*) * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL1Q * @arg @ref LL_RCC_SPI1_CLKSOURCE_PLL2P @@ -3542,13 +3879,16 @@ __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) * @arg @ref LL_RCC_I3C1_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I3C1_CLKSOURCE_HSI * @arg @ref LL_RCC_I3C1_CLKSOURCE_NONE + * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK1 (***) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PCLK3 (**) * @arg @ref LL_RCC_I3C2_CLKSOURCE_PLL2R (**) * @arg @ref LL_RCC_I3C2_CLKSOURCE_HSI (**) + * @arg @ref LL_RCC_I3C2_CLKSOURCE_CSI (***) * @arg @ref LL_RCC_I3C2_CLKSOURCE_NONE (**) * - * (*) : For stm32h56xxx and stm32h57xxx family lines. + * (*) : For stm32h56xxx, stm32h57xxx, stm32h5exxx and stm32h5fxxx family lines. * (**) : For stm32h503xx family line. + * (***) : For stm32h5exxx and stm32h5fxxx family lines. */ __STATIC_INLINE uint32_t LL_RCC_GetI3CClockSource(uint32_t I3Cx) { @@ -3737,7 +4077,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) /** * @brief Get SDMMCx kernel clock source * @rmtoll CCIPR4 SDMMC1SEL LL_RCC_GetSDMMCClockSource - * rmtoll CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * @rmtoll CCIPR4 SDMMC2SEL LL_RCC_GetSDMMCClockSource * @param SDMMCx This parameter can be one of the following values: * @arg @ref LL_RCC_SDMMC1_CLKSOURCE * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) @@ -6061,6 +6401,39 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); #if defined(CEC) uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); #endif /* CEC */ +#if defined(PLAY1) +uint32_t LL_RCC_GetPLAY1ClockFreq(uint32_t PLAYxSource); +#endif /* PLAY1 */ +#if defined(USB_OTG_FS) +uint32_t LL_RCC_GetOTGFSClockFreq(uint32_t OTGFSxSource); +#endif /* USB_OTG_FS */ +#if defined(USB_OTG_HS) +uint32_t LL_RCC_GetOTGHSClockFreq(uint32_t OTGHSxSource); +#endif /* USB_OTG_HS */ +#if defined(OCTOSPI2) +uint32_t LL_RCC_GetOCTOSPI2ClockFreq(uint32_t OCTOSPIxSource); +#endif /* OCTOSPI2 */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(ADF1) +uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADFxSource); +#endif /* ADF1 */ +#if defined(MDF1) +uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDFxSource); +#endif /* MDF1 */ +#if defined(RCC_CCIPR4_ETHCLKSEL) +uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource); +#endif /* RCC_CCIPR4_ETHCLKSEL */ +#if defined(RCC_CCIPR5_ETHPTPCLKSEL) +uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHPTPxSource); +#endif /* RCC_CCIPR5_ETHPTPCLKSEL */ +#if defined(RCC_CCIPR5_ETHT1SCLKSEL) +uint32_t LL_RCC_GetETHT1SClockFreq(uint32_t ETHT1SxSource); +#endif /* RCC_CCIPR5_ETHT1SCLKSEL */ +#if defined(RCC_CCIPR5_ETHREFCLKSEL) +uint32_t LL_RCC_GetETHREFClockFreq(uint32_t ETHREFxSource); +#endif /* RCC_CCIPR5_ETHREFCLKSEL */ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource); /** * @} diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h index aab1063..95be707 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_utils.h @@ -205,6 +205,7 @@ typedef struct #define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */ #define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */ + /** * @} */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/LICENSE.md b/stm32/Drivers/STM32H5xx_HAL_Driver/LICENSE.md new file mode 100644 index 0000000..9226612 --- /dev/null +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2021 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c index 994ce67..d4809b8 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal.c @@ -48,10 +48,10 @@ /* Private typedef ---------------------------------------------------------------------------------------------------*/ /* Private define ----------------------------------------------------------------------------------------------------*/ /** - * @brief STM32H5xx HAL Driver version number 1.4.0 + * @brief STM32H5xx HAL Driver version number 1.5.0.RC1 */ #define __STM32H5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32H5XX_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32H5XX_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ #define __STM32H5XX_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32H5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32H5XX_HAL_VERSION ((__STM32H5XX_HAL_VERSION_MAIN << 24U)\ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c index e29c115..cc1ab31 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c @@ -280,6 +280,17 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) /* Allocate lock resource */ __HAL_UNLOCK(hdma); + /* Initialize the callbacks */ + if (hdma->State == HAL_DMA_STATE_RESET) + { + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + } + /* Update the DMA channel state */ hdma->State = HAL_DMA_STATE_BUSY; @@ -474,6 +485,12 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); @@ -529,6 +546,12 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); @@ -910,7 +933,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Data Transfer Error Interrupt management *************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) @@ -924,7 +947,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Update Linked-list Error Interrupt management ********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) @@ -938,7 +961,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* User Setting Error Interrupt management **************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) @@ -952,7 +975,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Trigger Overrun Interrupt management *****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) @@ -966,7 +989,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Half Transfer Complete Interrupt management **********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) @@ -984,7 +1007,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Suspend Transfer Interrupt management ****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) @@ -1042,7 +1065,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) } /* Transfer Complete Interrupt management ***************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) + if (__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U) { /* Check if interrupt source is enabled */ if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) @@ -1539,7 +1562,7 @@ HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const h */ HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) { - DMA_TypeDef *p_dma_instance; + const DMA_TypeDef *p_dma_instance; uint32_t channel_idx; /* Check the DMA peripheral handle and lock state parameters */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c index 27d2c19..b225e71 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c @@ -824,6 +824,12 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) return HAL_ERROR; } + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check DMA channel state */ dma_state = hdma->State; ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; @@ -886,6 +892,12 @@ HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) return HAL_ERROR; } + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check DMA channel state */ dma_state = hdma->State; ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; @@ -3109,6 +3121,12 @@ HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + /* Get DMA state */ state = hdma->State; @@ -3189,6 +3207,12 @@ HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) return HAL_ERROR; } + /* Check the DMA Mode is not DMA_NORMAL */ + if (hdma->Mode == DMA_NORMAL) + { + return HAL_ERROR; + } + /* Get DMA state */ state = hdma->State; @@ -3257,6 +3281,12 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); @@ -3297,6 +3327,12 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); @@ -3345,6 +3381,12 @@ HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, return HAL_ERROR; } + /* Check the DMA Mode is DMA_NORMAL */ + if (hdma->Mode != DMA_NORMAL) + { + return HAL_ERROR; + } + /* Check parameters */ assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); @@ -4467,7 +4509,7 @@ static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, uint32_t contextnode_reg_counter = 0U; uint32_t cllr_idx; uint32_t cllr_mask; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + const DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c index db13a53..962c3a8 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_flash_ex.c @@ -1054,7 +1054,6 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) { /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); - if ((Banks & FLASH_BANK_1) == FLASH_BANK_1) { /* Enable Write Protection for bank 1 */ diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c index a59d2ca..9fdffd7 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c @@ -237,7 +237,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) GPIOx->OTYPER = tmp; } - if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) + if (((pGPIO_Init->Mode & GPIO_MODE) != GPIO_MODE_ANALOG) || + (((pGPIO_Init->Mode & GPIO_MODE) == GPIO_MODE_ANALOG) && (pGPIO_Init->Pull != GPIO_PULLUP))) { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c index d96e47c..5f27a9c 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_hash.c @@ -305,7 +305,7 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) * the configuration information for HASH module * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, const HASH_ConfigTypeDef *pConf) { uint32_t cr_value; @@ -1868,11 +1868,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_ { return HAL_BUSY; } - + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); /* Return function status */ return status; @@ -1949,10 +1948,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const u /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; } + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); } else { @@ -1999,10 +1998,10 @@ HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, con hhash->Size = Size; /* Set multi buffers accumulation flag */ hhash->Accumulation = 0U; + status = HASH_WriteData_IT(hhash); /* Enable the specified HASH interrupt*/ __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); - status = HASH_WriteData_IT(hhash); } else { @@ -2252,7 +2251,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) } /* If Peripheral ready to accept new data */ - if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) + if (((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) && ((itflag & HASH_FLAG_DCIS) != HASH_FLAG_DCIS)) { if ((itsource & HASH_IT_DINI) == HASH_IT_DINI) { @@ -2958,7 +2957,7 @@ static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash) } } } - else if ((hhash->State == HAL_HASH_STATE_SUSPENDED)) + else if (hhash->State == HAL_HASH_STATE_SUSPENDED) { return HAL_OK; } diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c index b1f98c3..bc69dac 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pcd.c @@ -1485,7 +1485,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) { hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; @@ -2301,6 +2301,7 @@ HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t tes case TEST_SE0_NAK: case TEST_PACKET: case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; break; @@ -2602,6 +2603,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -2622,27 +2635,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else + { + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -2708,7 +2721,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -2721,6 +2733,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -2762,7 +2775,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2838,7 +2851,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2870,11 +2883,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2924,6 +2937,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2935,10 +2954,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2969,7 +2990,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2997,6 +3018,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -3009,10 +3036,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -3042,7 +3071,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -3051,7 +3080,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c index 84eb931..71a0183 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc_ex.c @@ -141,6 +141,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); * @arg @ref RCC_PERIPHCLK_LPTIM6 LPTIM6 peripheral clock (*) * @arg @ref RCC_PERIPHCLK_DAC_LP DAC peripheral low-power clock * @arg @ref RCC_PERIPHCLK_TIM TIM peripheral clock + * @arg @ref RCC_PERIPHCLK_ETH ETH peripheral clock * * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select * the RTC clock source: in this case the access to Backup domain is enabled. diff --git a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c index 7904b05..950f815 100644 --- a/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c +++ b/stm32/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_ll_usb.c @@ -799,12 +799,12 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); if (ep->type == EP_TYPE_ISOC) { USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (pktcnt << 29)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); } } @@ -1335,8 +1335,8 @@ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) * @param USBx Selected device * @retval return core mode : Host or Device * This parameter can be one of these values: - * 0 : Host - * 1 : Device + * 1 : Host + * 0 : Device */ uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) { @@ -2616,6 +2616,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -2720,7 +2724,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -2822,9 +2826,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -2856,19 +2860,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -2877,15 +2887,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -2896,18 +2904,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -2951,26 +2949,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/stm32/stm32.ioc b/stm32/stm32.ioc index ffadc00..6ef0c42 100644 --- a/stm32/stm32.ioc +++ b/stm32/stm32.ioc @@ -233,8 +233,8 @@ Mcu.PinsNb=61 Mcu.ThirdPartyNb=0 Mcu.UserConstants=KEYPAD_POLL_MS,5;SC_DEFAULT_PSC,25;SC_DEFAULT_BAUD_RATE,10752;HALT_REQ_MS,10 Mcu.UserName=STM32H573VITx -MxCube.Version=6.13.0 -MxDb.Version=DB.6.0.130 +MxCube.Version=6.14.0 +MxDb.Version=DB.6.0.140 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DCMI_PSSI_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -422,6 +422,7 @@ PD2.Signal=GPIO_Output PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC ProjectManager.CompilerOptimize=6 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=false @@ -429,7 +430,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H573VITx -ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.4.0 +ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.5.0 ProjectManager.FreePins=true ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x0