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rockchip.backup.dts
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/dts-v1/;
/ {
interrupt-parent = <0x01>;
#address-cells = <0x02>;
#size-cells = <0x02>;
compatible = "seewo,sv21-rk3568\0rockchip,rk3568";
model = "seewo sv21-rk3568";
aliases {
gpio0 = "/pinctrl/gpio@fdd60000";
gpio1 = "/pinctrl/gpio@fe740000";
gpio2 = "/pinctrl/gpio@fe750000";
gpio3 = "/pinctrl/gpio@fe760000";
gpio4 = "/pinctrl/gpio@fe770000";
i2c0 = "/i2c@fdd40000";
i2c1 = "/i2c@fe5a0000";
i2c2 = "/i2c@fe5b0000";
i2c3 = "/i2c@fe5c0000";
i2c4 = "/i2c@fe5d0000";
i2c5 = "/i2c@fe5e0000";
serial0 = "/serial@fdd50000";
serial1 = "/serial@fe650000";
serial2 = "/serial@fe660000";
serial3 = "/serial@fe670000";
serial4 = "/serial@fe680000";
serial5 = "/serial@fe690000";
serial6 = "/serial@fe6a0000";
serial7 = "/serial@fe6b0000";
serial8 = "/serial@fe6c0000";
serial9 = "/serial@fe6d0000";
spi0 = "/spi@fe610000";
spi1 = "/spi@fe620000";
spi2 = "/spi@fe630000";
spi3 = "/spi@fe640000";
ethernet0 = "/ethernet@fe010000";
ethernet1 = "/usb@fd000000/device@2";
mmc0 = "/mmc@fe2b0000";
mmc1 = "/mmc@fe310000";
mmc2 = "/mmc@fe2c0000";
};
cpus {
#address-cells = <0x02>;
#size-cells = <0x00>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x00 0x00>;
clocks = <0x02 0x00>;
#cooling-cells = <0x02>;
enable-method = "psci";
operating-points-v2 = <0x03>;
cpu-supply = <0x04>;
phandle = <0x06>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x00 0x100>;
#cooling-cells = <0x02>;
enable-method = "psci";
operating-points-v2 = <0x03>;
cpu-supply = <0x04>;
phandle = <0x07>;
};
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x00 0x200>;
#cooling-cells = <0x02>;
enable-method = "psci";
operating-points-v2 = <0x03>;
cpu-supply = <0x04>;
phandle = <0x08>;
};
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x00 0x300>;
#cooling-cells = <0x02>;
enable-method = "psci";
operating-points-v2 = <0x03>;
cpu-supply = <0x04>;
phandle = <0x09>;
};
};
cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
phandle = <0x03>;
opp-408000000 {
opp-hz = <0x00 0x18519600>;
opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
clock-latency-ns = <0x9c40>;
};
opp-600000000 {
opp-hz = <0x00 0x23c34600>;
opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
};
opp-816000000 {
opp-hz = <0x00 0x30a32c00>;
opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
opp-suspend;
};
opp-1104000000 {
opp-hz = <0x00 0x41cdb400>;
opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
};
opp-1416000000 {
opp-hz = <0x00 0x54667200>;
opp-microvolt = <0xdbba0 0xdbba0 0x118c30>;
};
opp-1608000000 {
opp-hz = <0x00 0x5fd82200>;
opp-microvolt = <0xee098 0xee098 0x118c30>;
};
opp-1800000000 {
opp-hz = <0x00 0x6b49d200>;
opp-microvolt = <0x100590 0x100590 0x118c30>;
};
opp-1992000000 {
opp-hz = <0x00 0x76bb8200>;
opp-microvolt = <0x118c30 0x118c30 0x118c30>;
};
};
firmware {
scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82000010>;
shmem = <0x05>;
#address-cells = <0x01>;
#size-cells = <0x00>;
protocol@14 {
reg = <0x14>;
#clock-cells = <0x01>;
phandle = <0x02>;
};
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <0x00 0xe4 0x04 0x00 0xe5 0x04 0x00 0xe6 0x04 0x00 0xe7 0x04>;
interrupt-affinity = <0x06 0x07 0x08 0x09>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
arm,no-tick-in-suspend;
};
xin24m {
compatible = "fixed-clock";
clock-frequency = <0x16e3600>;
clock-output-names = "xin24m";
#clock-cells = <0x00>;
phandle = <0x1a>;
};
xin32k {
compatible = "fixed-clock";
clock-frequency = <0x8000>;
clock-output-names = "xin32k";
pinctrl-0 = <0x0a>;
pinctrl-names = "default";
#clock-cells = <0x00>;
};
sram@10f000 {
compatible = "mmio-sram";
reg = <0x00 0x10f000 0x00 0x100>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges = <0x00 0x00 0x10f000 0x100>;
sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x00 0x100>;
phandle = <0x05>;
};
};
sata@fc400000 {
compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci";
reg = <0x00 0xfc400000 0x00 0x1000>;
clocks = <0x0b 0x9b 0x0b 0x9c 0x0b 0x9d>;
clock-names = "sata\0pmalive\0rxoob";
interrupts = <0x00 0x5f 0x04>;
phys = <0x0c 0x01>;
phy-names = "sata-phy";
ports-implemented = <0x01>;
power-domains = <0x0d 0x0f>;
status = "disabled";
};
sata@fc800000 {
compatible = "rockchip,rk3568-dwc-ahci\0snps,dwc-ahci";
reg = <0x00 0xfc800000 0x00 0x1000>;
clocks = <0x0b 0xa0 0x0b 0xa1 0x0b 0xa2>;
clock-names = "sata\0pmalive\0rxoob";
interrupts = <0x00 0x60 0x04>;
phys = <0x0e 0x01>;
phy-names = "sata-phy";
ports-implemented = <0x01>;
power-domains = <0x0d 0x0f>;
status = "okay";
};
usb@fcc00000 {
compatible = "rockchip,rk3568-dwc3\0snps,dwc3";
reg = <0x00 0xfcc00000 0x00 0x400000>;
interrupts = <0x00 0xa9 0x04>;
clocks = <0x0b 0xa6 0x0b 0xa7 0x0b 0xa5>;
clock-names = "ref_clk\0suspend_clk\0bus_clk";
dr_mode = "host";
phy_type = "utmi_wide";
power-domains = <0x0d 0x0f>;
resets = <0x0b 0x94>;
snps,dis_u2_susphy_quirk;
status = "okay";
phys = <0x0f 0x10 0x04>;
phy-names = "usb2-phy\0usb3-phy";
extcon = <0x11>;
};
usb@fd000000 {
compatible = "rockchip,rk3568-dwc3\0snps,dwc3";
reg = <0x00 0xfd000000 0x00 0x400000>;
interrupts = <0x00 0xaa 0x04>;
clocks = <0x0b 0xa9 0x0b 0xaa 0x0b 0xa8>;
clock-names = "ref_clk\0suspend_clk\0bus_clk";
dr_mode = "host";
phys = <0x12 0x0c 0x04>;
phy-names = "usb2-phy\0usb3-phy";
phy_type = "utmi_wide";
power-domains = <0x0d 0x0f>;
resets = <0x0b 0x95>;
snps,dis_u2_susphy_quirk;
status = "okay";
device@2 {
compatible = "usbbda,8153";
reg = <0x02>;
realtek,led-data = <0x87>;
};
};
interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <0x03>;
#address-cells = <0x02>;
#size-cells = <0x02>;
ranges;
interrupt-controller;
reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>;
interrupts = <0x01 0x09 0x04>;
phandle = <0x01>;
interrupt-controller@fd440000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <0x01>;
reg = <0x00 0xfd440000 0x00 0x20000>;
phandle = <0x4e>;
};
};
usb@fd800000 {
compatible = "generic-ehci";
reg = <0x00 0xfd800000 0x00 0x40000>;
interrupts = <0x00 0x82 0x04>;
clocks = <0x0b 0xbd 0x0b 0xbe 0x0b 0xbc>;
phys = <0x13>;
phy-names = "usb";
status = "okay";
};
usb@fd840000 {
compatible = "generic-ohci";
reg = <0x00 0xfd840000 0x00 0x40000>;
interrupts = <0x00 0x83 0x04>;
clocks = <0x0b 0xbd 0x0b 0xbe 0x0b 0xbc>;
phys = <0x13>;
phy-names = "usb";
status = "okay";
};
usb@fd880000 {
compatible = "generic-ehci";
reg = <0x00 0xfd880000 0x00 0x40000>;
interrupts = <0x00 0x85 0x04>;
clocks = <0x0b 0xbf 0x0b 0xc0 0x0b 0xbc>;
phys = <0x14>;
phy-names = "usb";
status = "okay";
};
usb@fd8c0000 {
compatible = "generic-ohci";
reg = <0x00 0xfd8c0000 0x00 0x40000>;
interrupts = <0x00 0x86 0x04>;
clocks = <0x0b 0xbf 0x0b 0xc0 0x0b 0xbc>;
phys = <0x14>;
phy-names = "usb";
status = "okay";
};
syscon@fda00000 {
compatible = "rockchip,rk3568-xpcs\0syscon";
reg = <0x00 0xfda00000 0x00 0x200000>;
status = "disabled";
};
syscon@fdc20000 {
compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd";
reg = <0x00 0xfdc20000 0x00 0x10000>;
phandle = <0x9d>;
io-domains {
compatible = "rockchip,rk3568-pmu-io-voltage-domain";
status = "okay";
pmuio1-supply = <0x15>;
pmuio2-supply = <0x15>;
vccio1-supply = <0x16>;
vccio2-supply = <0x17>;
vccio3-supply = <0x18>;
vccio4-supply = <0x19>;
vccio5-supply = <0x19>;
vccio6-supply = <0x19>;
vccio7-supply = <0x19>;
};
};
syscon@fdc50000 {
reg = <0x00 0xfdc50000 0x00 0x1000>;
compatible = "rockchip,rk3568-pipe-grf\0syscon";
phandle = <0x96>;
};
syscon@fdc60000 {
compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd";
reg = <0x00 0xfdc60000 0x00 0x10000>;
phandle = <0x1c>;
};
syscon@fdc80000 {
compatible = "rockchip,rk3568-pipe-phy-grf\0syscon";
reg = <0x00 0xfdc80000 0x00 0x1000>;
phandle = <0x97>;
};
syscon@fdc90000 {
compatible = "rockchip,rk3568-pipe-phy-grf\0syscon";
reg = <0x00 0xfdc90000 0x00 0x1000>;
phandle = <0x98>;
};
syscon@fdca0000 {
compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
reg = <0x00 0xfdca0000 0x00 0x8000>;
phandle = <0x99>;
};
syscon@fdca8000 {
compatible = "rockchip,rk3568-usb2phy-grf\0syscon";
reg = <0x00 0xfdca8000 0x00 0x8000>;
phandle = <0x9c>;
};
clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x00 0xfdd00000 0x00 0x1000>;
#clock-cells = <0x01>;
#reset-cells = <0x01>;
phandle = <0x1b>;
};
clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0x00 0xfdd20000 0x00 0x1000>;
clocks = <0x1a>;
clock-names = "xin24m";
#clock-cells = <0x01>;
#reset-cells = <0x01>;
assigned-clocks = <0x1b 0x05 0x0b 0x04 0x1b 0x01>;
assigned-clock-rates = <0x8000 0x47868c00 0xbebc200>;
assigned-clock-parents = <0x1b 0x08>;
rockchip,grf = <0x1c>;
phandle = <0x0b>;
};
i2c@fdd40000 {
compatible = "rockchip,rk3568-i2c\0rockchip,rk3399-i2c";
reg = <0x00 0xfdd40000 0x00 0x1000>;
interrupts = <0x00 0x2e 0x04>;
clocks = <0x1b 0x07 0x1b 0x2d>;
clock-names = "i2c\0pclk";
pinctrl-0 = <0x1d>;
pinctrl-names = "default";
#address-cells = <0x01>;
#size-cells = <0x00>;
status = "okay";
regulator@1c {
compatible = "tcs,tcs4525";
reg = <0x40>;
fcs,suspend-voltage-selector = <0x01>;
regulator-name = "vdd_cpu";
regulator-min-microvolt = "\0\f5";
regulator-max-microvolt = <0x118c30>;
regulator-ramp-delay = <0x3e8>;
regulator-always-on;
regulator-boot-on;
vin-supply = <0x1e>;
phandle = <0x04>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
pmic@20 {
compatible = "rockchip,rk809";
reg = <0x20>;
interrupt-parent = <0x1f>;
interrupts = <0x03 0x08>;
assigned-clocks = <0x0b 0x48>;
assigned-clock-parents = <0x0b 0x196>;
#clock-cells = <0x01>;
clock-names = "mclk";
clocks = <0x0b 0x48>;
clock-output-names = "rk808-clkout1\0rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <0x20 0x21>;
rockchip,system-power-controller;
#sound-dai-cells = <0x00>;
wakeup-source;
vcc1-supply = <0x22>;
vcc2-supply = <0x22>;
vcc3-supply = <0x22>;
vcc4-supply = <0x22>;
vcc5-supply = <0x22>;
vcc6-supply = <0x22>;
vcc7-supply = <0x22>;
vcc8-supply = <0x22>;
vcc9-supply = <0x22>;
regulators {
DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x7a120>;
regulator-max-microvolt = <0x149970>;
regulator-init-microvolt = <0xdbba0>;
regulator-ramp-delay = <0x1771>;
regulator-initial-mode = <0x02>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x7a120>;
regulator-max-microvolt = <0x149970>;
regulator-init-microvolt = <0xdbba0>;
regulator-ramp-delay = <0x1771>;
regulator-initial-mode = <0x02>;
regulator-state-mem {
regulator-on-in-suspend;
};
};
DCDC_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-initial-mode = <0x02>;
regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
DCDC_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x7a120>;
regulator-max-microvolt = <0x149970>;
regulator-init-microvolt = <0xdbba0>;
regulator-initial-mode = <0x02>;
regulator-name = "vdd_npu";
regulator-state-mem {
regulator-off-in-suspend;
};
};
DCDC_REG5 {
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
phandle = <0x17>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG1 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0xdbba0>;
regulator-max-microvolt = <0xdbba0>;
regulator-name = "vdda0v9_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG2 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0xdbba0>;
regulator-max-microvolt = <0xdbba0>;
regulator-name = "vdda_0v9";
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG3 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0xdbba0>;
regulator-max-microvolt = <0xdbba0>;
regulator-name = "vdda0v9_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <0xdbba0>;
};
};
LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
regulator-name = "vccio_acodec";
phandle = <0x16>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG5 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x325aa0>;
regulator-name = "vccio_sd";
phandle = <0x18>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG6 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
regulator-name = "vcc3v3_pmu";
phandle = <0x15>;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <0x325aa0>;
};
};
LDO_REG7 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
regulator-name = "vcca_1v8";
phandle = <0x89>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
LDO_REG8 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
regulator-name = "vcca1v8_pmu";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <0x1b7740>;
};
};
LDO_REG9 {
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0x1b7740>;
regulator-max-microvolt = <0x1b7740>;
regulator-name = "vcca1v8_image";
regulator-state-mem {
regulator-off-in-suspend;
};
};
SWITCH_REG1 {
regulator-name = "vcc_3v3";
phandle = <0x19>;
regulator-state-mem {
regulator-off-in-suspend;
};
};
SWITCH_REG2 {
regulator-name = "vcc3v3_sd";
regulator-state-mem {
regulator-off-in-suspend;
};
};
codec {
mic-in-differential;
};
};
};
};
serial@fdd50000 {
compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart";
reg = <0x00 0xfdd50000 0x00 0x100>;
interrupts = <0x00 0x74 0x04>;
clocks = <0x1b 0x0b 0x1b 0x2c>;
clock-names = "baudclk\0apb_pclk";
dmas = <0x23 0x00 0x23 0x01>;
pinctrl-0 = <0x24>;
pinctrl-names = "default";
reg-io-width = <0x04>;
reg-shift = <0x02>;
status = "disabled";
};
pwm@fdd70000 {
compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
reg = <0x00 0xfdd70000 0x00 0x10>;
clocks = <0x1b 0x0d 0x1b 0x30>;
clock-names = "pwm\0pclk";
pinctrl-0 = <0x25>;
pinctrl-names = "default";
#pwm-cells = <0x03>;
status = "disabled";
};
pwm@fdd70010 {
compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
reg = <0x00 0xfdd70010 0x00 0x10>;
clocks = <0x1b 0x0d 0x1b 0x30>;
clock-names = "pwm\0pclk";
pinctrl-0 = <0x26>;
pinctrl-names = "default";
#pwm-cells = <0x03>;
status = "disabled";
};
pwm@fdd70020 {
compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
reg = <0x00 0xfdd70020 0x00 0x10>;
clocks = <0x1b 0x0d 0x1b 0x30>;
clock-names = "pwm\0pclk";
pinctrl-0 = <0x27>;
pinctrl-names = "default";
#pwm-cells = <0x03>;
status = "disabled";
};
pwm@fdd70030 {
compatible = "rockchip,rk3568-pwm\0rockchip,rk3328-pwm";
reg = <0x00 0xfdd70030 0x00 0x10>;
clocks = <0x1b 0x0d 0x1b 0x30>;
clock-names = "pwm\0pclk";
pinctrl-0 = <0x28>;
pinctrl-names = "default";
#pwm-cells = <0x03>;
status = "disabled";
};
power-management@fdd90000 {
compatible = "rockchip,rk3568-pmu\0syscon\0simple-mfd";
reg = <0x00 0xfdd90000 0x00 0x1000>;
power-controller {
compatible = "rockchip,rk3568-power-controller";
#power-domain-cells = <0x01>;
#address-cells = <0x01>;
#size-cells = <0x00>;
phandle = <0x0d>;
power-domain@7 {
reg = <0x07>;
clocks = <0x0b 0x19 0x0b 0x1a>;
pm_qos = <0x29>;
#power-domain-cells = <0x00>;
};
power-domain@8 {
reg = <0x08>;
clocks = <0x0b 0xcc 0x0b 0xcd>;
pm_qos = <0x2a 0x2b 0x2c>;
#power-domain-cells = <0x00>;
};
power-domain@9 {
reg = <0x09>;
clocks = <0x0b 0xda 0x0b 0xdb 0x0b 0xdc>;
pm_qos = <0x2d 0x2e 0x2f>;
#power-domain-cells = <0x00>;
};
power-domain@10 {
reg = <0x0a>;
clocks = <0x0b 0xf1 0x0b 0xf2>;
pm_qos = <0x30 0x31 0x32 0x33 0x34 0x35>;
#power-domain-cells = <0x00>;
};
power-domain@11 {
reg = <0x0b>;
clocks = <0x0b 0xed>;
pm_qos = <0x36>;
#power-domain-cells = <0x00>;
};
power-domain@13 {
clocks = <0x0b 0x107>;
reg = <0x0d>;
pm_qos = <0x37>;
#power-domain-cells = <0x00>;
};
power-domain@14 {
reg = <0x0e>;
clocks = <0x0b 0x102>;
pm_qos = <0x38 0x39 0x3a>;
#power-domain-cells = <0x00>;
};
power-domain@15 {
reg = <0x0f>;
clocks = <0x0b 0x7f>;
pm_qos = <0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42>;
#power-domain-cells = <0x00>;
};
};
};
mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc\0rockchip,rk3288-dw-mshc";
reg = <0x00 0xfe000000 0x00 0x4000>;
interrupts = <0x00 0x64 0x04>;
clocks = <0x0b 0xc1 0x0b 0xc2 0x0b 0x18e 0x0b 0x18f>;
clock-names = "biu\0ciu\0ciu-drive\0ciu-sample";
fifo-depth = <0x100>;
max-frequency = <0x8f0d180>;
resets = <0x0b 0xeb>;
reset-names = "reset";
status = "disabled";
};
ethernet@fe010000 {
compatible = "rockchip,rk3568-gmac\0snps,dwmac-4.20a";
reg = <0x00 0xfe010000 0x00 0x10000>;
interrupts = <0x00 0x20 0x04 0x00 0x1d 0x04>;
interrupt-names = "macirq\0eth_wake_irq";
clocks = <0x0b 0x186 0x0b 0x189 0x0b 0x189 0x0b 0xc7 0x0b 0xc3 0x0b 0xc4 0x0b 0x189 0x0b 0xc8>;
clock-names = "stmmaceth\0mac_clk_rx\0mac_clk_tx\0clk_mac_refout\0aclk_mac\0pclk_mac\0clk_mac_speed\0ptp_ref";
resets = <0x0b 0xec>;
reset-names = "stmmaceth";
rockchip,grf = <0x1c>;
snps,axi-config = <0x43>;
snps,mixed-burst;
snps,mtl-rx-config = <0x44>;
snps,mtl-tx-config = <0x45>;
snps,tso;
status = "okay";
assigned-clocks = <0x0b 0x189 0x0b 0x186>;
assigned-clock-parents = <0x0b 0x187>;
assigned-clock-rates = <0x00 0x7735940>;
clock_in_out = "output";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <0x46 0x47 0x48 0x49 0x4a>;
snps,reset-gpio = <0x4b 0x19 0x00>;
snps,reset-active-high;
snps,reset-delays-us = <0x00 0xf4240 0x1e8480>;
tx_delay = <0x2a>;
rx_delay = <0x2a>;
fixed-link = <0x01 0x01 0x3e8 0x01 0x01>;
phy-handle = <0x4c>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x01>;
#size-cells = <0x00>;
ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x00>;
phandle = <0x4c>;
};
};
stmmac-axi-config {
snps,blen = <0x00 0x00 0x00 0x00 0x10 0x08 0x04>;
snps,rd_osr_lmt = <0x08>;
snps,wr_osr_lmt = <0x04>;
phandle = <0x43>;
};
rx-queues-config {
snps,rx-queues-to-use = <0x01>;
phandle = <0x44>;
queue0 {
};
};
tx-queues-config {
snps,tx-queues-to-use = <0x01>;
phandle = <0x45>;
queue0 {
};
};
};
qos@fe128000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe128000 0x00 0x20>;
phandle = <0x29>;
};
qos@fe138080 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe138080 0x00 0x20>;
phandle = <0x38>;
};
qos@fe138100 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe138100 0x00 0x20>;
phandle = <0x39>;
};
qos@fe138180 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe138180 0x00 0x20>;
phandle = <0x3a>;
};
qos@fe148000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe148000 0x00 0x20>;
phandle = <0x2a>;
};
qos@fe148080 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe148080 0x00 0x20>;
phandle = <0x2b>;
};
qos@fe148100 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe148100 0x00 0x20>;
phandle = <0x2c>;
};
qos@fe150000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe150000 0x00 0x20>;
phandle = <0x36>;
};
qos@fe158000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158000 0x00 0x20>;
phandle = <0x30>;
};
qos@fe158100 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158100 0x00 0x20>;
phandle = <0x31>;
};
qos@fe158180 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158180 0x00 0x20>;
phandle = <0x32>;
};
qos@fe158200 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158200 0x00 0x20>;
phandle = <0x33>;
};
qos@fe158280 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158280 0x00 0x20>;
phandle = <0x34>;
};
qos@fe158300 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe158300 0x00 0x20>;
phandle = <0x35>;
};
qos@fe180000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe180000 0x00 0x20>;
};
qos@fe190000 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe190000 0x00 0x20>;
phandle = <0x3b>;
};
qos@fe190280 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe190280 0x00 0x20>;
phandle = <0x3f>;
};
qos@fe190300 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe190300 0x00 0x20>;
phandle = <0x40>;
};
qos@fe190380 {
compatible = "rockchip,rk3568-qos\0syscon";
reg = <0x00 0xfe190380 0x00 0x20>;
phandle = <0x41>;
};
qos@fe190400 {