In this part of the project, we were tasked with designing and testing 4 modules: an XOR gate, an XNOR gate, a positive edge-triggered D flip-flop and a D flip-flop with asynchronous active-high preset and clear.
In this part of the project, we were tasked with implementing a characterization flow and using it to characterize the standard cells designed in the first part of the project. The final result is a library file.