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backlight_controller_3x2.pro
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update=Fri 02 Nov 2018 02:49:47 PM EDT
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[cvpcb/libraries]
EquName1=devcms
[general]
version=1
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=backlight_controller_3x2.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2032
MinViaDiameter=0.508
MinViaDrill=0.2032
MinMicroViaDiameter=0.508
MinMicroViaDrill=0.127
MinHoleToHole=0.25
TrackWidth1=0.254
ViaDiameter1=0.889
ViaDrill1=0.635
dPairWidth1=0.254
dPairGap1=0.254
dPairViaGap1=0.25
SilkLineWidth=0.381
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2286
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.2286
CourtyardLineWidth=0.05
OthersLineWidth=0.381
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=GND
Clearance=0.1016
TrackWidth=0.8128
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.254
dPairGap=0.254
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=LEDPOWER
Clearance=0.1016
TrackWidth=0.254
ViaDiameter=0.635
ViaDrill=0.381
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.254
dPairGap=0.254
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=POWER
Clearance=0.1016
TrackWidth=0.4064
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.254
dPairGap=0.254
dPairViaGap=0.25
[pcbnew/Netclasses/4]
Name=SIGNAL
Clearance=0.1016
TrackWidth=0.2032
ViaDiameter=0.635
ViaDrill=0.381
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.254
dPairGap=0.254
dPairViaGap=0.25
[pcbnew/Netclasses/5]
Name=SUPERPOWER
Clearance=0.1016
TrackWidth=0.8128
ViaDiameter=0.889
ViaDrill=0.635
uViaDiameter=0.508
uViaDrill=0.127
dPairWidth=0.254
dPairGap=0.254
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=schematic/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=60
ERC_TestSimilarLabels=1