R7 3700X + X570 Aorus Master - VDDG CCD not shown

[pandavova]

VDDG CCD is not shown:

Here is the Debug Report of my R7 3700X + X570 Aorus Master (rev 1.0).
Debug_Report_28482436.8494351.txt
If anything else is needed, please tell me.

[irusanov]

Hi,
Do you know what are CLDO VDDP, VDDG CCD and VDDG IO set to?
If you have a ryzen mster installed, a screenshot from it might help.

There are these values present in the report, but I can't tell with 100% certainty which is which

Offset 1F0: 0,95038550
Offset 1F4: 0,94743530
Offset 1F8: 1,04774500

Currently the last 2 are read as VDDP and VDDG IOD, but that might not be entirely correct.

[pandavova]

Here is the Ryzen Master screenshot:

CLDO VDDP is set to 950
CLDO VDDG is set to 1050

VDDG CCD is set to 950
VDDG IOD is set to 1050

Should I change some of the values to specific ones so you can be sure which offsets are which values? If so, tell me what voltage to set.

[irusanov]

You can try to set vddg ccd to something different like 965, so we can see if the other offset changes, but it is possible that the vddg ccd voltage is not reported in the table. If the offset 1F0 changes to ~0.965, then that would be VDDG CCD. I'm not sure separate voltages were available on Zen2, IIRC the split was introduced for Zen3.

[pandavova]

Looks like 1F0 is not it, it doesn't change by setting VDDG CCD to 965.

Debug_Report_28482719.2992037.txt

Either it's not reported or the voltage split is on Zen 3, I don't know that.
Is there anything else I should test with my setup for you that could help improve the program?

[irusanov]

I guess it would be better to change the layout for Zen2 to show just one VDDG. I have CPUs from all generations to validate each release. Don't think we can do anything else, unless this voltage is at a different offset in the table.