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Use of VHDL-2019 Interfaces #240

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DavidMonk00 opened this issue Apr 9, 2024 · 0 comments

DavidMonk00 commented Apr 9, 2024

In VHDL-2019 (and supported in Vivado 2023.2), there is the ability to bundle entity signals into a single line of code.

Implementing this for ipbus components would significantly reduce code verbosity and simplify designs.

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