Update libpfm4 to commit 161297

src/libpfm4/docs/Makefile

@@ -126,7 +126,10 @@ ARCH_MAN=libpfm_intel_core.3	\
 	 libpfm_intel_icx_unc_m3upi.3 \
 	 libpfm_intel_icx_unc_ubox.3 \
 	 libpfm_intel_icx_unc_m2pcie.3 \
-	 libpfm_intel_icx_unc_irp.3
+	 libpfm_intel_icx_unc_irp.3 \
+	 libpfm_intel_spr_unc_imc.3 \
+	 libpfm_intel_spr_unc_upi.3 \
+	 libpfm_intel_spr_unc_cha.3
 
 
 ifeq ($(CONFIG_PFMLIB_ARCH_I386),y)

src/libpfm4/docs/man3/libpfm_intel_spr_unc_cha.3

@@ -0,0 +1,37 @@
+.TH LIBPFM 3  "January, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_intel_spr_unc_cha - support for Intel IcelakeX Server CHA uncore PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: spr_unc_cha[0-59]
+.B PMU desc: Intel SapphireRapids CHA uncore PMU
+.sp
+.SH DESCRIPTION
+The library supports the Intel SapphireRapids CHA (coherency and home agent) uncore PMU.
+There is one CHA-box PMU per physical core. Therefore there are up forty identical CHA
+PMU instances numbered from 0 up to possibly 59. On dual-socket systems, the number refers to the CHA
+PMUs on the socket where the program runs.
+
+Each CHA PMU implements 4 generic counters.
+
+.SH MODIFIERS
+The following modifiers are supported on Intel SapphireRapids CHA uncore PMU:
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one.  This is a boolean modifier.
+.TP
+.B t
+Set the threshold value. When set to a non-zero value, the counter counts the number
+of CHA clockticks in which the number of occurrences of the event is greater or equal to
+the threshold.  This is an integer modifier with values in the range [0:255].
+.TP
+.B i
+Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier.
+
+.SH AUTHORS
+.nf
+Stephane Eranian <[email protected]>
+.if
+.PP

src/libpfm4/docs/man3/libpfm_intel_spr_unc_imc.3

@@ -0,0 +1,30 @@
+.TH LIBPFM 3  "January, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_intel_spr_unc_imc - support for Intel SapphireRapids Server Integrated Memory Controller (IMC)  uncore PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: spr_unc_imc[0-11]
+.B PMU desc: Intel SapphireRapids Server IMC uncore PMU
+.sp
+.SH DESCRIPTION
+The library supports the Intel SapphireRapids Server Integrated Memory Controller (IMC) uncore PMU.
+
+.SH MODIFIERS
+The following modifiers are supported on Intel SapphireRapids server IMC uncore PMU:
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one.  This is a boolean modifier.
+.TP
+.B t
+Set the threshold value. When set to a non-zero value, the counter counts the number
+of IMC cycles in which the number of occurrences of the event is greater or equal to
+the threshold.  This is an integer modifier with values in the range [0:255].
+.B i
+Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier.
+.SH AUTHORS
+.nf
+Stephane Eranian <[email protected]>
+.if
+.PP

src/libpfm4/docs/man3/libpfm_intel_spr_unc_upi.3

@@ -0,0 +1,31 @@
+.TH LIBPFM 3  "January, 2024" "" "Linux Programmer's Manual"
+.SH NAME
+libpfm_intel_spr_unc_upi - support for Intel SapphireRapids Server UPI uncore PMU
+.SH SYNOPSIS
+.nf
+.B #include <perfmon/pfmlib.h>
+.sp
+.B PMU name: spr_unc_upi[0-3]
+.B PMU desc: Intel SapphireRapids UPI uncore PMU
+.sp
+.SH DESCRIPTION
+The library supports the Intel SapphireRapids UPI (Ultra Path Interconnect) uncore PMU.
+Each UPI PMU implements 4 generic counters.
+
+.SH MODIFIERS
+The following modifiers are supported on Intel SapphireRapids UPI uncore PMU:
+.TP
+.B e
+Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one.  This is a boolean modifier.
+.TP
+.B t
+Set the threshold value. When set to a non-zero value, the counter counts the number
+of IRP clockticks in which the number of occurrences of the event is greater or equal to
+the threshold.  This is an integer modifier with values in the range [0:255].
+.B i
+Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier.
+.SH AUTHORS
+.nf
+Stephane Eranian <[email protected]>
+.if
+.PP

src/libpfm4/include/perfmon/pfmlib.h

@@ -730,6 +730,86 @@ typedef enum {
 
 	PFM_PMU_INTEL_ADL_GLC,		/* Intel AlderLake Goldencove (P-Core) */
 	PFM_PMU_INTEL_ADL_GRT,		/* Intel AlderLake Gracemont (E-Core) */
+
+	PFM_PMU_INTEL_SPR_UNC_IMC0,	/* Intel SapphireRapids IMC channel 0 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC1,	/* Intel SapphireRapids IMC channel 1 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC2,	/* Intel SapphireRapids IMC channel 2 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC3,	/* Intel SapphireRapids IMC channel 3 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC4,	/* Intel SapphireRapids IMC channel 4 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC5,	/* Intel SapphireRapids IMC channel 5 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC6,	/* Intel SapphireRapids IMC channel 6 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC7,	/* Intel SapphireRapids IMC channel 7 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC8,	/* Intel SapphireRapids IMC channel 8 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC9,	/* Intel SapphireRapids IMC channel 9 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC10,	/* Intel SapphireRapids IMC channel 10 uncore */
+	PFM_PMU_INTEL_SPR_UNC_IMC11,	/* Intel SapphireRapids IMC channel 11 uncore */
+
+	PFM_PMU_INTEL_SPR_UNC_UPI0,	/* Intel SapphireRapids UPI0 uncore */
+	PFM_PMU_INTEL_SPR_UNC_UPI1,	/* Intel SapphireRapids UPI1 uncore */
+	PFM_PMU_INTEL_SPR_UNC_UPI2,	/* Intel SapphireRapids UPI2 uncore */
+	PFM_PMU_INTEL_SPR_UNC_UPI3,	/* Intel SapphireRapids UPI3 uncore */
+
+	PFM_PMU_INTEL_SPR_UNC_CHA0,	/* Intel SapphireRapids CHA core 0 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA1,	/* Intel SapphireRapids CHA core 1 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA2,	/* Intel SapphireRapids CHA core 2 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA3,	/* Intel SapphireRapids CHA core 3 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA4,	/* Intel SapphireRapids CHA core 4 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA5,	/* Intel SapphireRapids CHA core 5 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA6,	/* Intel SapphireRapids CHA core 6 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA7,	/* Intel SapphireRapids CHA core 7 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA8,	/* Intel SapphireRapids CHA core 8 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA9,	/* Intel SapphireRapids CHA core 9 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA10,	/* Intel SapphireRapids CHA core 10 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA11,	/* Intel SapphireRapids CHA core 11 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA12,	/* Intel SapphireRapids CHA core 12 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA13,	/* Intel SapphireRapids CHA core 13 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA14,	/* Intel SapphireRapids CHA core 14 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA15,	/* Intel SapphireRapids CHA core 15 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA16,	/* Intel SapphireRapids CHA core 16 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA17,	/* Intel SapphireRapids CHA core 17 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA18,	/* Intel SapphireRapids CHA core 18 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA19,	/* Intel SapphireRapids CHA core 19 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA20,	/* Intel SapphireRapids CHA core 20 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA21,	/* Intel SapphireRapids CHA core 21 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA22,	/* Intel SapphireRapids CHA core 22 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA23,	/* Intel SapphireRapids CHA core 23 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA24,	/* Intel SapphireRapids CHA core 24 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA25,	/* Intel SapphireRapids CHA core 25 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA26,	/* Intel SapphireRapids CHA core 26 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA27,	/* Intel SapphireRapids CHA core 27 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA28,	/* Intel SapphireRapids CHA core 28 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA29,	/* Intel SapphireRapids CHA core 39 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA30,	/* Intel SapphireRapids CHA core 30 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA31,	/* Intel SapphireRapids CHA core 31 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA32,	/* Intel SapphireRapids CHA core 32 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA33,	/* Intel SapphireRapids CHA core 33 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA34,	/* Intel SapphireRapids CHA core 34 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA35,	/* Intel SapphireRapids CHA core 35 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA36,	/* Intel SapphireRapids CHA core 36 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA37,	/* Intel SapphireRapids CHA core 37 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA38,	/* Intel SapphireRapids CHA core 38 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA39,	/* Intel SapphireRapids CHA core 39 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA40,	/* Intel SapphireRapids CHA core 40 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA41,	/* Intel SapphireRapids CHA core 41 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA42,	/* Intel SapphireRapids CHA core 42 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA43,	/* Intel SapphireRapids CHA core 43 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA44,	/* Intel SapphireRapids CHA core 44 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA45,	/* Intel SapphireRapids CHA core 45 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA46,	/* Intel SapphireRapids CHA core 46 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA47,	/* Intel SapphireRapids CHA core 47 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA48,	/* Intel SapphireRapids CHA core 48 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA49,	/* Intel SapphireRapids CHA core 49 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA50,	/* Intel SapphireRapids CHA core 50 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA51,	/* Intel SapphireRapids CHA core 51 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA52,	/* Intel SapphireRapids CHA core 52 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA53,	/* Intel SapphireRapids CHA core 53 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA54,	/* Intel SapphireRapids CHA core 54 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA55,	/* Intel SapphireRapids CHA core 55 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA56,	/* Intel SapphireRapids CHA core 56 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA57,	/* Intel SapphireRapids CHA core 57 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA58,	/* Intel SapphireRapids CHA core 58 uncore */
+	PFM_PMU_INTEL_SPR_UNC_CHA59,	/* Intel SapphireRapids CHA core 59 uncore */
+
 	/* MUST ADD NEW PMU MODELS HERE */
 
 	PFM_PMU_MAX			/* end marker */

src/libpfm4/lib/Makefile

@@ -126,6 +126,9 @@ SRCS   += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \
 	  pfmlib_intel_icx_unc_m3upi.c \
 	  pfmlib_intel_icx_unc_ubox.c \
 	  pfmlib_intel_icx_unc_m2pcie.c \
+	  pfmlib_intel_spr_unc_imc.c \
+	  pfmlib_intel_spr_unc_upi.c \
+	  pfmlib_intel_spr_unc_cha.c \
 	  pfmlib_intel_knc.c \
 	  pfmlib_intel_slm.c \
 	  pfmlib_intel_tmt.c \
@@ -360,6 +363,9 @@ INC_X86= pfmlib_intel_x86_priv.h	\
 	events/intel_icx_unc_m3upi_events.h \
 	events/intel_icx_unc_ubox_events.h \
 	events/intel_icx_unc_m2pcie_events.h \
+	events/intel_spr_unc_imc_events.h \
+	events/intel_spr_unc_upi_events.h \
+	events/intel_spr_unc_cha_events.h \
 	events/intel_slm_events.h
 
 INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h