From b170053931c0f3784717d4750220f6412b29212a Mon Sep 17 00:00:00 2001 From: Giuseppe Congiu Date: Wed, 3 Jan 2024 09:35:24 +0100 Subject: [PATCH] libpfm4: update to commit 90f61a0 Original commits: commit 90f61a008cdee50d085b5041414df55e16e045fe Author: Stephane Eranian Date: Mon Dec 18 01:00:31 2023 -0800 Add Intel IcelakeX uncore PMU support for M2PCIE Adds the Mesh to IIO PMU (M2PCIE) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 22afed4c1020b579205ac8e8f9d6e8599307b9ee Author: Stephane Eranian Date: Sun Dec 17 21:25:51 2023 -0800 Add Intel IcelakeX uncore PMU support for UBOX Adds the UBOX PMU (UBOX) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit cdbe2eed7bdcf5d45086d6730033defc1939a722 Author: Stephane Eranian Date: Tue Dec 12 23:27:19 2023 -0800 Add Intel IcelakeX uncore PMU support for M3UPI Adds the Mesh to UPI PMU (M3UPI) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 17dddc2f4cde87f37f041f40586654190da5a8c2 Author: Stephane Eranian Date: Tue Dec 12 22:13:47 2023 -0800 Add Intel IcelakeX uncore PMU support for UPI Adds the Ultra Path Interconnect PMU support (UPI) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 32fcf6fe2eaf2f2bf105f7543dcc0b07c097baaf Author: Stephane Eranian Date: Sun Dec 10 22:45:04 2023 -0800 Add Intel IcelakeX uncore PMU support for PCU Adds the Power Control unit PMU support (PCU) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 20ff7523ffaae04f6762d51e32fe35e04fa70cad Author: Stephane Eranian Date: Fri Dec 8 23:24:44 2023 -0800 Add Intel IcelakeX uncore PMU support for M2M Adds the Mesh to Memory PMU support (M2M) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit d5ed0e03686c051f5311fc1993824245eb10e1d2 Author: Stephane Eranian Date: Tue Dec 5 21:17:16 2023 -0800 Add Intel IcelakeX uncore PMU support for IRP Adds the PCIe IIO Ring Port PMU support (IRP) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 30afdce909bcc7313af7599cfbf6484ae4b1fc3e Author: Stephane Eranian Date: Mon Dec 4 22:08:00 2023 -0800 Add Intel IcelakeX uncore PMU support for IIO Adds the PCIe I/O controller PMU support (IIO) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 6237022aa77bc9c845b1c48d741e54bdc22ac077 Author: Stephane Eranian Date: Wed Nov 22 16:37:53 2023 -0800 Add Intel IcelakeX uncore PMU support for IMC Adds the memory controller PMU support (IMC) for Intel IcelakeX. Based on Intel JSON events v1.21 published from github.com/intel/perfmon/ICX Signed-off-by: Stephane Eranian commit 05f04adec932cd2cd28e83f718e4e0ae6ba2eab4 Author: Stephane Eranian Date: Wed Nov 22 15:46:42 2023 -0800 Add Intel IcelakeX uncore PMU support for CHA Adds Intel IcelakeX CHA (Coherency and Home Agent) uncore PMU support. Based on Intel published uncore JSON events v1.21 from github.com/intel/perfmon/ICX. Signed-off-by: Stephane Eranian commit 94e82e27c02ef01f288a1b40904d72b2954d3f31 Author: Stephane Eranian Date: Sun Dec 10 22:28:11 2023 -0800 check umasks[] bounds in intel_x86_uflag() Otherwise may run into SEGFAULT for some events. Signed-off-by: Stephane Eranian commit d058479bd048d2742df298097da86bc86dd1a5ce Author: Stephane Eranian Date: Fri Dec 8 22:25:25 2023 -0800 Enable RAPL support on AMD Zen4 Just like other AMD EPYC processors, only ENERGY_PKG is supported. Signed-off-by: Stephane Eranian --- src/libpfm4/docs/Makefile | 12 +- .../docs/man3/libpfm_intel_icx_unc_cha.3 | 37 + .../docs/man3/libpfm_intel_icx_unc_iio.3 | 34 + .../docs/man3/libpfm_intel_icx_unc_imc.3 | 30 + .../docs/man3/libpfm_intel_icx_unc_irp.3 | 33 + .../docs/man3/libpfm_intel_icx_unc_m2m.3 | 30 + .../docs/man3/libpfm_intel_icx_unc_m2pcie.3 | 33 + .../docs/man3/libpfm_intel_icx_unc_m3upi.3 | 31 + .../docs/man3/libpfm_intel_icx_unc_pcu.3 | 40 + .../docs/man3/libpfm_intel_icx_unc_ubox.3 | 33 + .../docs/man3/libpfm_intel_icx_unc_upi.3 | 31 + src/libpfm4/include/perfmon/pfmlib.h | 87 + src/libpfm4/lib/Makefile | 19 + .../lib/events/intel_icx_unc_cha_events.h | 5896 +++++++++++++++++ .../lib/events/intel_icx_unc_iio_events.h | 2310 +++++++ .../lib/events/intel_icx_unc_imc_events.h | 1244 ++++ .../lib/events/intel_icx_unc_irp_events.h | 521 ++ .../lib/events/intel_icx_unc_m2m_events.h | 3910 +++++++++++ .../lib/events/intel_icx_unc_m2pcie_events.h | 2969 +++++++++ .../lib/events/intel_icx_unc_m3upi_events.h | 3985 +++++++++++ .../lib/events/intel_icx_unc_pcu_events.h | 196 + .../lib/events/intel_icx_unc_ubox_events.h | 256 + .../lib/events/intel_icx_unc_upi_events.h | 754 +++ src/libpfm4/lib/pfmlib_amd64_rapl.c | 3 +- src/libpfm4/lib/pfmlib_common.c | 79 + src/libpfm4/lib/pfmlib_intel_icx_unc_cha.c | 155 + src/libpfm4/lib/pfmlib_intel_icx_unc_iio.c | 91 + src/libpfm4/lib/pfmlib_intel_icx_unc_imc.c | 95 + src/libpfm4/lib/pfmlib_intel_icx_unc_irp.c | 89 + src/libpfm4/lib/pfmlib_intel_icx_unc_m2m.c | 85 + src/libpfm4/lib/pfmlib_intel_icx_unc_m2pcie.c | 86 + src/libpfm4/lib/pfmlib_intel_icx_unc_m3upi.c | 87 + src/libpfm4/lib/pfmlib_intel_icx_unc_pcu.c | 85 + src/libpfm4/lib/pfmlib_intel_icx_unc_ubox.c | 81 + src/libpfm4/lib/pfmlib_intel_icx_unc_upi.c | 87 + src/libpfm4/lib/pfmlib_intel_snbep_unc.c | 48 + src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h | 76 + src/libpfm4/lib/pfmlib_intel_x86_priv.h | 4 +- src/libpfm4/lib/pfmlib_priv.h | 79 + src/libpfm4/tests/validate_x86.c | 480 ++ 40 files changed, 24197 insertions(+), 4 deletions(-) create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_cha.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_iio.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_imc.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_irp.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2m.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2pcie.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_m3upi.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_pcu.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_ubox.3 create mode 100644 src/libpfm4/docs/man3/libpfm_intel_icx_unc_upi.3 create mode 100644 src/libpfm4/lib/events/intel_icx_unc_cha_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_iio_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_imc_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_irp_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_m2m_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_m2pcie_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_m3upi_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_pcu_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_ubox_events.h create mode 100644 src/libpfm4/lib/events/intel_icx_unc_upi_events.h create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_cha.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_iio.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_imc.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_irp.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_m2m.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_m2pcie.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_m3upi.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_pcu.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_ubox.c create mode 100644 src/libpfm4/lib/pfmlib_intel_icx_unc_upi.c diff --git a/src/libpfm4/docs/Makefile b/src/libpfm4/docs/Makefile index ce9223dc8..b07797402 100644 --- a/src/libpfm4/docs/Makefile +++ b/src/libpfm4/docs/Makefile @@ -114,7 +114,17 @@ ARCH_MAN=libpfm_intel_core.3 \ libpfm_intel_skx_unc_m3upi.3 \ libpfm_intel_skx_unc_pcu.3 \ libpfm_intel_skx_unc_ubo.3 \ - libpfm_intel_skx_unc_upi.3 + libpfm_intel_skx_unc_upi.3 \ + libpfm_intel_icx_unc_cha.3 \ + libpfm_intel_icx_unc_imc.3 \ + libpfm_intel_icx_unc_m2m.3 \ + libpfm_intel_icx_unc_iio.3 \ + libpfm_intel_icx_unc_pcu.3 \ + libpfm_intel_icx_unc_upi.3 \ + libpfm_intel_icx_unc_m3upi.3 \ + libpfm_intel_icx_unc_ubox.3 \ + libpfm_intel_icx_unc_m2pcie.3 \ + libpfm_intel_icx_unc_irp.3 ifeq ($(CONFIG_PFMLIB_ARCH_I386),y) diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_cha.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_cha.3 new file mode 100644 index 000000000..6c5afca86 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_cha.3 @@ -0,0 +1,37 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_cha - support for Intel IcelakeX Server CHA uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_cha[0-39] +.B PMU desc: Intel IcelakeX CHA uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX CHA (coherency and home agent) uncore PMU. +There is one CHA-box PMU per physical core. Therefore there are up forty identical CHA +PMU instances numbered from 0 up to possibly 39. On dual-socket systems, the number refers to the CHA +PMUs on the socket where the program runs. + +Each CHA PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX CHA uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of CHA clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_iio.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_iio.3 new file mode 100644 index 000000000..63b032539 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_iio.3 @@ -0,0 +1,34 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_iio - support for Intel IcelakeX Server IIO uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_iio[0-5] +.B PMU desc: Intel IcelakeX IIO uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX IIO (I/O controller) uncore PMU. +Each IIO PMU implements 4 generic counters and free running counters (not yet supported by libpfm4). +The current version of libpfm4 does not expose the \fBfc_mask\fR and \fBch_mask\fR filter because these are +hardcoded in the events provided by the library. +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX IIO uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IIO clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_imc.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_imc.3 new file mode 100644 index 000000000..cffaebda5 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_imc.3 @@ -0,0 +1,30 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_imc - support for Intel Icelake X Server Integrated Memory Controller (IMC) uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_imc[0-11] +.B PMU desc: Intel Icelake X Server IMC uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Icelake X Server Integrated Memory Controller (IMC) uncore PMU. + +.SH MODIFIERS +The following modifiers are supported on Intel Icelake X server IMC uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IMC cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_irp.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_irp.3 new file mode 100644 index 000000000..7e1e5eff5 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_irp.3 @@ -0,0 +1,33 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_irp - support for Intel IcelakeX Server IRP uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_irp[0-5] +.B PMU desc: Intel IcelakeX IRP uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX IRP (IIO Ring Port) uncore PMU. There is one IRP per IIO. +Each IRP PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX IRP uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IRP clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2m.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2m.3 new file mode 100644 index 000000000..79b04211d --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2m.3 @@ -0,0 +1,30 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_m2m - support for Intel Icelake X Server Mesh to Memory (M2M) uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_m2m[0-1] +.B PMU desc: Intel Icelake X Server M2M uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel Icelake X Server Mesh to Memory (M2M) uncore PMU. + +.SH MODIFIERS +The following modifiers are supported on Intel Icelake X server M2M uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of M2M cycles in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2pcie.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2pcie.3 new file mode 100644 index 000000000..aabc9e7b5 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m2pcie.3 @@ -0,0 +1,33 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_m2pcie - support for Intel IcelakeX Server M2PCIE uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_m2pcie[0-2] +.B PMU desc: Intel IcelakeX M2PCIE uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX M2PCIE (Mesh to IIO) uncore PMU. +Each M2PCIE PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX M2PCIE uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of M2PCIE clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m3upi.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m3upi.3 new file mode 100644 index 000000000..0dbeee0ea --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_m3upi.3 @@ -0,0 +1,31 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_m3upi - support for Intel IcelakeX Server M3UPI uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_m3upi[0-3] +.B PMU desc: Intel IcelakeX M3UPI uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX M3UPI (Mesh to UPI) uncore PMU. +Each M3UPI PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX M3UPI uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IRP clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_pcu.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_pcu.3 new file mode 100644 index 000000000..6d4be14db --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_pcu.3 @@ -0,0 +1,40 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_pcu - support for Intel IcelakeX Server PCU uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_pcu +.B PMU desc: Intel IcelakeX PCU uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX PCU (Power Control Unit) uncore PMU. There is one PCU per system. +Each PCU PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX PCU uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IRP clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:63]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. +.TP +.B occ_i +Invert the threshold (t) for occupancy events \fBPOWER_STATE_OCCUPANY\fR test from strictly greater than to less or equal to. This is a boolean modifier. +.TP +.B occ_e +Enable edge detection for occupancy events \fBPOWER_STATE_OCCUPANCY\fR, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_ubox.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_ubox.3 new file mode 100644 index 000000000..8e61f7054 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_ubox.3 @@ -0,0 +1,33 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_ubox - support for Intel IcelakeX Server UBOX uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_ubox +.B PMU desc: Intel IcelakeX UBOX uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX UBOX (System configuration controller) uncore PMU. There is one UBOX per processor. +Each UBOX PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX UBOX uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of UBOX clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.TP +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. + +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/docs/man3/libpfm_intel_icx_unc_upi.3 b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_upi.3 new file mode 100644 index 000000000..b405b7a19 --- /dev/null +++ b/src/libpfm4/docs/man3/libpfm_intel_icx_unc_upi.3 @@ -0,0 +1,31 @@ +.TH LIBPFM 3 "November, 2023" "" "Linux Programmer's Manual" +.SH NAME +libpfm_intel_icx_unc_upi - support for Intel IcelakeX Server UPI uncore PMU +.SH SYNOPSIS +.nf +.B #include +.sp +.B PMU name: icx_unc_upi[0-3] +.B PMU desc: Intel IcelakeX UPI uncore PMU +.sp +.SH DESCRIPTION +The library supports the Intel IcelakeX UPI (Ultra Path Interconnect) uncore PMU. +Each UPI PMU implements 4 generic counters. + +.SH MODIFIERS +The following modifiers are supported on Intel IcelakeX UPI uncore PMU: +.TP +.B e +Enable edge detection, i.e., count only when there is a state transition from no occurrence of the event to at least one occurrence. This modifier must be combined with a threshold modifier (t) with a value greater or equal to one. This is a boolean modifier. +.TP +.B t +Set the threshold value. When set to a non-zero value, the counter counts the number +of IRP clockticks in which the number of occurrences of the event is greater or equal to +the threshold. This is an integer modifier with values in the range [0:255]. +.B i +Invert the threshold (t) test from strictly greater than to less or equal to. This is a boolean modifier. +.SH AUTHORS +.nf +Stephane Eranian +.if +.PP diff --git a/src/libpfm4/include/perfmon/pfmlib.h b/src/libpfm4/include/perfmon/pfmlib.h index 4bad406e6..f96f53ec1 100644 --- a/src/libpfm4/include/perfmon/pfmlib.h +++ b/src/libpfm4/include/perfmon/pfmlib.h @@ -640,6 +640,93 @@ typedef enum { PFM_PMU_ARM_V2, /* Arm Neoverse V2 */ PFM_PMU_INTEL_EMR, /* Intel EmeraldRapid */ + PFM_PMU_INTEL_ICX_UNC_CHA0, /* Intel Icelake-X CHA core 0 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA1, /* Intel Icelake-X CHA core 1 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA2, /* Intel Icelake-X CHA core 2 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA3, /* Intel Icelake-X CHA core 3 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA4, /* Intel Icelake-X CHA core 4 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA5, /* Intel Icelake-X CHA core 5 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA6, /* Intel Icelake-X CHA core 6 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA7, /* Intel Icelake-X CHA core 7 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA8, /* Intel Icelake-X CHA core 8 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA9, /* Intel Icelake-X CHA core 9 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA10, /* Intel Icelake-X CHA core 10 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA11, /* Intel Icelake-X CHA core 11 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA12, /* Intel Icelake-X CHA core 12 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA13, /* Intel Icelake-X CHA core 13 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA14, /* Intel Icelake-X CHA core 14 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA15, /* Intel Icelake-X CHA core 15 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA16, /* Intel Icelake-X CHA core 16 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA17, /* Intel Icelake-X CHA core 17 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA18, /* Intel Icelake-X CHA core 18 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA19, /* Intel Icelake-X CHA core 19 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA20, /* Intel Icelake-X CHA core 20 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA21, /* Intel Icelake-X CHA core 21 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA22, /* Intel Icelake-X CHA core 22 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA23, /* Intel Icelake-X CHA core 23 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA24, /* Intel Icelake-X CHA core 24 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA25, /* Intel Icelake-X CHA core 25 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA26, /* Intel Icelake-X CHA core 26 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA27, /* Intel Icelake-X CHA core 27 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA28, /* Intel Icelake-X CHA core 28 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA29, /* Intel Icelake-X CHA core 39 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA30, /* Intel Icelake-X CHA core 30 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA31, /* Intel Icelake-X CHA core 31 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA32, /* Intel Icelake-X CHA core 32 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA33, /* Intel Icelake-X CHA core 33 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA34, /* Intel Icelake-X CHA core 34 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA35, /* Intel Icelake-X CHA core 35 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA36, /* Intel Icelake-X CHA core 36 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA37, /* Intel Icelake-X CHA core 37 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA38, /* Intel Icelake-X CHA core 38 uncore */ + PFM_PMU_INTEL_ICX_UNC_CHA39, /* Intel Icelake-X CHA core 39 uncore */ + + PFM_PMU_INTEL_ICX_UNC_IMC0, /* Intel Icelake-X IMC channel 0 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC1, /* Intel Icelake-X IMC channel 1 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC2, /* Intel Icelake-X IMC channel 2 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC3, /* Intel Icelake-X IMC channel 3 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC4, /* Intel Icelake-X IMC channel 4 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC5, /* Intel Icelake-X IMC channel 5 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC6, /* Intel Icelake-X IMC channel 6 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC7, /* Intel Icelake-X IMC channel 7 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC8, /* Intel Icelake-X IMC channel 8 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC9, /* Intel Icelake-X IMC channel 9 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC10, /* Intel Icelake-X IMC channel 10 uncore */ + PFM_PMU_INTEL_ICX_UNC_IMC11, /* Intel Icelake-X IMC channel 11 uncore */ + + PFM_PMU_INTEL_ICX_UNC_IIO0, /* Intel Icelake-X IIO 0 uncore */ + PFM_PMU_INTEL_ICX_UNC_IIO1, /* Intel Icelake-X IIO 1 uncore */ + PFM_PMU_INTEL_ICX_UNC_IIO2, /* Intel Icelake-X IIO 2 uncore */ + PFM_PMU_INTEL_ICX_UNC_IIO3, /* Intel Icelake-X IIO 3 uncore */ + PFM_PMU_INTEL_ICX_UNC_IIO4, /* Intel Icelake-X IIO 4 uncore */ + PFM_PMU_INTEL_ICX_UNC_IIO5, /* Intel Icelake-X IIO 5 uncore */ + + PFM_PMU_INTEL_ICX_UNC_IRP0, /* Intel Icelake-X IRP 0 uncore */ + PFM_PMU_INTEL_ICX_UNC_IRP1, /* Intel Icelake-X IRP 1 uncore */ + PFM_PMU_INTEL_ICX_UNC_IRP2, /* Intel Icelake-X IRP 2 uncore */ + PFM_PMU_INTEL_ICX_UNC_IRP3, /* Intel Icelake-X IRP 3 uncore */ + PFM_PMU_INTEL_ICX_UNC_IRP4, /* Intel Icelake-X IRP 4 uncore */ + PFM_PMU_INTEL_ICX_UNC_IRP5, /* Intel Icelake-X IRP 5 uncore */ + + PFM_PMU_INTEL_ICX_UNC_M2M0, /* Intel Icelake-X M2M 0 uncore */ + PFM_PMU_INTEL_ICX_UNC_M2M1, /* Intel Icelake-X M2M 1 uncore */ + + PFM_PMU_INTEL_ICX_UNC_PCU, /* Intel Icelake-X PCU uncore */ + + PFM_PMU_INTEL_ICX_UNC_UPI0, /* Intel Icelake-X UPI0 uncore */ + PFM_PMU_INTEL_ICX_UNC_UPI1, /* Intel Icelake-X UPI1 uncore */ + PFM_PMU_INTEL_ICX_UNC_UPI2, /* Intel Icelake-X UPI2 uncore */ + PFM_PMU_INTEL_ICX_UNC_UPI3, /* Intel Icelake-X UPI3 uncore */ + + PFM_PMU_INTEL_ICX_UNC_M3UPI0, /* Intel Icelake-X M3UPI0 uncore */ + PFM_PMU_INTEL_ICX_UNC_M3UPI1, /* Intel Icelake-X M3UPI1 uncore */ + PFM_PMU_INTEL_ICX_UNC_M3UPI2, /* Intel Icelake-X M3UPI2 uncore */ + PFM_PMU_INTEL_ICX_UNC_M3UPI3, /* Intel Icelake-X M3UPI3 uncore */ + + PFM_PMU_INTEL_ICX_UNC_UBOX, /* Intel Icelake-X UBOX uncore */ + PFM_PMU_INTEL_ICX_UNC_M2PCIE0, /* Intel Icelake-X M2PCIE0 uncore */ + PFM_PMU_INTEL_ICX_UNC_M2PCIE1, /* Intel Icelake-X M2PCIE1 uncore */ + PFM_PMU_INTEL_ICX_UNC_M2PCIE2, /* Intel Icelake-X M2PCIE2 uncore */ /* MUST ADD NEW PMU MODELS HERE */ PFM_PMU_MAX /* end marker */ diff --git a/src/libpfm4/lib/Makefile b/src/libpfm4/lib/Makefile index aae64a117..c25b5b5fd 100644 --- a/src/libpfm4/lib/Makefile +++ b/src/libpfm4/lib/Makefile @@ -116,6 +116,16 @@ SRCS += pfmlib_amd64.c pfmlib_intel_core.c pfmlib_intel_x86.c \ pfmlib_intel_skx_unc_pcu.c \ pfmlib_intel_skx_unc_ubo.c \ pfmlib_intel_skx_unc_upi.c \ + pfmlib_intel_icx_unc_cha.c \ + pfmlib_intel_icx_unc_imc.c \ + pfmlib_intel_icx_unc_m2m.c \ + pfmlib_intel_icx_unc_iio.c \ + pfmlib_intel_icx_unc_irp.c \ + pfmlib_intel_icx_unc_pcu.c \ + pfmlib_intel_icx_unc_upi.c \ + pfmlib_intel_icx_unc_m3upi.c \ + pfmlib_intel_icx_unc_ubox.c \ + pfmlib_intel_icx_unc_m2pcie.c \ pfmlib_intel_knc.c \ pfmlib_intel_slm.c \ pfmlib_intel_tmt.c \ @@ -338,6 +348,15 @@ INC_X86= pfmlib_intel_x86_priv.h \ events/intel_knl_unc_edc_events.h \ events/intel_knl_unc_cha_events.h \ events/intel_knl_unc_m2pcie_events.h \ + events/intel_icx_unc_cha_events.h \ + events/intel_icx_unc_imc_events.h \ + events/intel_icx_unc_m2m_events.h \ + events/intel_icx_unc_irp_events.h \ + events/intel_icx_unc_pcu_events.h \ + events/intel_icx_unc_upi_events.h \ + events/intel_icx_unc_m3upi_events.h \ + events/intel_icx_unc_ubox_events.h \ + events/intel_icx_unc_m2pcie_events.h \ events/intel_slm_events.h INC_MIPS=events/mips_74k_events.h events/mips_74k_events.h diff --git a/src/libpfm4/lib/events/intel_icx_unc_cha_events.h b/src/libpfm4/lib/events/intel_icx_unc_cha_events.h new file mode 100644 index 000000000..271dbe7ca --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_cha_events.h @@ -0,0 +1,5896 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_cha (IcelakeX Uncore CHA) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_cha_2lm_nm_setconflicts[]={ + { .uname = "LLC", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TOR", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_2lm_nm_setconflicts2[]={ + { .uname = "MEMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEMWRNI", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag0_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag0_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag0_bl_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag0_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag1_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag1_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag1_bl_crd_acquired0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ag1_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_bypass_cha_imc[]={ + { .uname = "INTERMEDIATE", + .udesc = "Intermediate bypass Taken (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_TAKEN", + .udesc = "Not Taken (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TAKEN", + .udesc = "Taken (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_core_snp[]={ + { .uname = "ANY_GTONE", + .udesc = "Any Cycle with Multiple Snoops (experimental)", + .ucode = 0xf200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY_ONE", + .udesc = "Any Single Snoop (experimental)", + .ucode = 0xf100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORE_GTONE", + .udesc = "Multiple Core Requests (experimental)", + .ucode = 0x4200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORE_ONE", + .udesc = "Single Core Requests (experimental)", + .ucode = 0x4100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EVICT_GTONE", + .udesc = "Multiple Eviction (experimental)", + .ucode = 0x8200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EVICT_ONE", + .udesc = "Single Eviction (experimental)", + .ucode = 0x8100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EXT_GTONE", + .udesc = "Multiple External Snoops (experimental)", + .ucode = 0x2200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EXT_ONE", + .udesc = "Single External Snoops (experimental)", + .ucode = 0x2100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_GTONE", + .udesc = "Multiple Snoop Targets from Remote (experimental)", + .ucode = 0x1200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_ONE", + .udesc = "Single Snoop Target from Remote (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_direct_go[]={ + { .uname = "HA_SUPPRESS_DRD", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA_SUPPRESS_NO_D2C", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA_TOR_DEALLOC", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_direct_go_opc[]={ + { .uname = "EXTCMP", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAST_GO", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAST_GO_PULL", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GO", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GO_PULL", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IDLE_DUE_SUPPRESS", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOP", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PULL", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_dir_lookup[]={ + { .uname = "NO_SNP", + .udesc = "Snoop Not Needed (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Snoop Needed (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_dir_update[]={ + { .uname = "HA", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TOR", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_distress_asserted[]={ + { .uname = "DPT_LOCAL", + .udesc = "DPT Local (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_NONLOCAL", + .udesc = "DPT Remote (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_IV", + .udesc = "DPT Stalled - IV (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_NOCRD", + .udesc = "DPT Stalled - No Credit (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HORZ", + .udesc = "Horizontal (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_LOCAL", + .udesc = "PMM Local (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_NONLOCAL", + .udesc = "PMM Remote (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VERT", + .udesc = "Vertical (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_egress_ordering[]={ + { .uname = "IV_SNOOPGO_DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_SNOOPGO_UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_hitme_hit[]={ + { .uname = "EX_RDS", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SHARED_OWNREQ", + .udesc = "Remote socket ownership read requests that hit in S state. (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBMTOE", + .udesc = "Remote socket WBMtoE requests (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBMTOI_OR_S", + .udesc = "Remote socket writeback to I or S requests (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_hitme_lookup[]={ + { .uname = "READ", + .udesc = "Remote socket read requests (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITE", + .udesc = "Remote socket write (i.e. writeback) requests (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_hitme_miss[]={ + { .uname = "NOTSHARED_RDINVOWN", + .udesc = "Remote socket RdInvOwn requests that are not to shared line (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_OR_INV", + .udesc = "Remote socket read or invalidate requests (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SHARED_RDINVOWN", + .udesc = "Remote socket RdInvOwn requests to shared line (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_hitme_update[]={ + { .uname = "DEALLOCATE", + .udesc = "Deallocate HitME$ on Reads without RspFwdI* (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DEALLOCATE_RSPFWDI_LOC", + .udesc = "op is RspIFwd or RspIFwdWb for a local request (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDINVOWN", + .udesc = "Update HitMe Cache on RdInvOwn even if not RspFwdI* (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPFWDI_REM", + .udesc = "op is RspIFwd or RspIFwdWb for a remote request (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SHARED", + .udesc = "Update HitMe Cache to SHARed (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_horz_ring_akc_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_horz_ring_bl_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_horz_ring_iv_in_use[]={ + { .uname = "LEFT", + .udesc = "Left (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT", + .udesc = "Right (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_imc_reads_count[]={ + { .uname = "NORMAL", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRIORITY", + .udesc = "ISOCH (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_imc_writes_count[]={ + { .uname = "FULL", + .udesc = "Full Line Non-ISOCH", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FULL_PRIORITY", + .udesc = "ISOCH Full Line (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL", + .udesc = "Partial Non-ISOCH (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL_PRIORITY", + .udesc = "ISOCH Partial (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_llc_lookup[]={ + { .uname = "ALL", + .udesc = "TBD (experimental)", + .ucode = 0x1fff0000ff00ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "ALL_REMOTE", + .udesc = "All transactions from Remote Agents (experimental)", + .ucode = 0x1e200000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY_F", + .udesc = "All Request Filter (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE", + .udesc = "TBD (experimental)", + .ucode = 0x1bd00000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x19d00000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_READ", + .udesc = "Code Reads (experimental)", + .ucode = 0x1bd00000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_READ_F", + .udesc = "CRd Request Filter (experimental)", + .ucode = 0x1000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_READ_LOCAL", + .udesc = "CRd Requests that come from the local socket (usually the core) (experimental)", + .ucode = 0x19d00000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_READ_MISS", + .udesc = "Code Read Misses (experimental)", + .ucode = 0x1bd000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_READ_REMOTE", + .udesc = "CRd Requests that come from a Remote socket. (experimental)", + .ucode = 0x1a100000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CODE_REMOTE", + .udesc = "TBD (experimental)", + .ucode = 0x1a100000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "COREPREF_OR_DMND_LOCAL_F", + .udesc = "Local request Filter (experimental)", + .ucode = 0x4000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_RD", + .udesc = "TBD (experimental)", + .ucode = 0x1bc10000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ", + .udesc = "TBD", + .ucode = 0x1bc10000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ_ALL", + .udesc = "TBD (experimental)", + .ucode = 0x1fc10000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ_F", + .udesc = "Data Read Request Filter (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x19c10000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ_MISS", + .udesc = "Data Read Misses (experimental)", + .ucode = 0x1bc100000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA_READ_REMOTE", + .udesc = "TBD (experimental)", + .ucode = 0x1a010000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DMND_READ_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x8410000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "E", + .udesc = "E State (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "F", + .udesc = "F State (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLUSH_INV", + .udesc = "Flush or Invalidate Requests (experimental)", + .ucode = 0x1a440000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLUSH_INV_LOCAL", + .udesc = "Flush or Invalidate Requests that come from the local socket (usually the core) (experimental)", + .ucode = 0x18440000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLUSH_INV_REMOTE", + .udesc = "Flush or Invalidate requests that come from a Remote socket. (experimental)", + .ucode = 0x1a040000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLUSH_OR_INV_F", + .udesc = "Flush or Invalidate Filter (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "I", + .udesc = "I State (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCPREF_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x189d0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCPREF_LOCAL_F", + .udesc = "Local LLC prefetch requests (from LLC) Filter (experimental)", + .ucode = 0x8000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_PF_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x189d0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCALLY_HOMED_ADDRESS", + .udesc = "TBD (experimental)", + .ucode = 0xbdf0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_F", + .udesc = "Transactions homed locally Filter (experimental)", + .ucode = 0x80000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_HOM", + .udesc = "Transactions homed locally (experimental)", + .ucode = 0xbdf0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M", + .udesc = "M State (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS_ALL", + .udesc = "All Misses (experimental)", + .ucode = 0x1fe000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OTHER_REQ_F", + .udesc = "Write Request Filter (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PREF_OR_DMND_REMOTE_F", + .udesc = "Remote non-snoop request Filter (experimental)", + .ucode = 0x20000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ", + .udesc = "Reads (experimental)", + .ucode = 0x1bd90000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_LOCAL_LOC_HOM", + .udesc = "Locally Requested Reads that are Locally HOMed (experimental)", + .ucode = 0x9d90000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_LOCAL_REM_HOM", + .udesc = "Locally Requested Reads that are Remotely HOMed (experimental)", + .ucode = 0x11d90000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_MISS", + .udesc = "Read Misses (experimental)", + .ucode = 0x1bd900000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_MISS_LOC_HOM", + .udesc = "Locally HOMed Read Misses (experimental)", + .ucode = 0xbd900000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_MISS_REM_HOM", + .udesc = "Remotely HOMed Read Misses (experimental)", + .ucode = 0x13d900000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_OR_SNOOP_REMOTE_MISS_REM_HOM", + .udesc = "Remotely requested Read or Snoop Misses that are Remotely HOMed (experimental)", + .ucode = 0x161900000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_REMOTE_LOC_HOM", + .udesc = "Remotely Requested Reads that are Locally HOMed (experimental)", + .ucode = 0xa190000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READ_SF_HIT", + .udesc = "Reads that Hit the Snoop Filter (experimental)", + .ucode = 0x1bd900000e00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTELY_HOMED_ADDRESS", + .udesc = "TBD (experimental)", + .ucode = 0x15df0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_F", + .udesc = "Transactions homed remotely Filter (experimental)", + .ucode = 0x100000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_SNOOP_F", + .udesc = "Remote snoop request Filter (experimental)", + .ucode = 0x40000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_SNP", + .udesc = "TBD (experimental)", + .ucode = 0x1c190000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REM_HOM", + .udesc = "Transactions homed remotely (experimental)", + .ucode = 0x15df0000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO", + .udesc = "RFO Requests (experimental)", + .ucode = 0x1bc80000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_F", + .udesc = "RFO Request Filter (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_LOCAL", + .udesc = "RFO Requests that come from the local socket (usually the core) (experimental)", + .ucode = 0x19c80000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_MISS", + .udesc = "RFO Misses (experimental)", + .ucode = 0x1bc800000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_PREF_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x8880000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_REMOTE", + .udesc = "RFO Requests that come from a Remote socket. (experimental)", + .ucode = 0x1a080000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S", + .udesc = "S State (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_E", + .udesc = "SnoopFilter - E State (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_H", + .udesc = "SnoopFilter - H State (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_S", + .udesc = "SnoopFilter - S State (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES_AND_OTHER", + .udesc = "Filters Requests for those that write info into the cache (experimental)", + .ucode = 0x1a420000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITE_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x8420000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITE_REMOTE", + .udesc = "TBD (experimental)", + .ucode = 0x17c20000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_llc_victims[]={ + { .uname = "ALL", + .udesc = "All Lines Victimized", + .ucode = 0x0f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "E_STATE", + .udesc = "Lines in E state (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_ALL", + .udesc = "Local - All Lines (experimental)", + .ucode = 0x2000000f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_E", + .udesc = "Local - Lines in E State (experimental)", + .ucode = 0x2000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_M", + .udesc = "Local - Lines in M State (experimental)", + .ucode = 0x2000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_ONLY", + .udesc = "Local Only (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_S", + .udesc = "Local - Lines in S State (experimental)", + .ucode = 0x2000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M_STATE", + .udesc = "Lines in M state (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_ALL", + .udesc = "Remote - All Lines (experimental)", + .ucode = 0x8000000f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_E", + .udesc = "Remote - Lines in E State (experimental)", + .ucode = 0x8000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_M", + .udesc = "Remote - Lines in M State (experimental)", + .ucode = 0x8000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_ONLY", + .udesc = "Remote Only (experimental)", + .ucode = 0x8000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_S", + .udesc = "Remote - Lines in S State (experimental)", + .ucode = 0x8000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S_STATE", + .udesc = "Lines in S State (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_misc[]={ + { .uname = "CV0_PREF_MISS", + .udesc = "CV0 Prefetch Miss (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CV0_PREF_VIC", + .udesc = "CV0 Prefetch Victim (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_HIT_S", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPI_WAS_FSE", + .udesc = "Silent Snoop Eviction (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WC_ALIASING", + .udesc = "Write Combining Aliasing (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_misc_external[]={ + { .uname = "MBE_INST0", + .udesc = "Number of cycles MBE is high for MS2IDI0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MBE_INST1", + .udesc = "Number of cycles MBE is high for MS2IDI1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_osb[]={ + { .uname = "LOCAL_INVITOE", + .udesc = "Local InvItoE (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_READ", + .udesc = "Local Rd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OFF_PWRHEURISTIC", + .udesc = "Off (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_READ", + .udesc = "Remote Rd (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_READINVITOE", + .udesc = "Remote Rd InvItoE (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO_HITS_SNP_BCAST", + .udesc = "RFO HitS Snoop Broadcast (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pipe_reject[]={ + { .uname = "ADEGRCREDIT", + .udesc = "TBD (experimental)", + .ucode = 0x10000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKEGRCREDIT", + .udesc = "TBD (experimental)", + .ucode = 0x20000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALLRSFWAYS_RES", + .udesc = "TBD (experimental)", + .ucode = 0x80000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BLEGRCREDIT", + .udesc = "TBD (experimental)", + .ucode = 0x8000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FSF_VICP", + .udesc = "TBD (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GOTRACK_ALLOWSNP", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GOTRACK_ALLWAYRSV", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GOTRACK_PAMATCH", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GOTRACK_WAYMATCH", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HACREDIT", + .udesc = "TBD (experimental)", + .ucode = 0x40000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IDX_INPIPE", + .udesc = "TBD (experimental)", + .ucode = 0x10000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IPQ_SETMATCH_VICP", + .udesc = "TBD (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_PMM", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_SETMATCH_VICP", + .udesc = "TBD (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ISMQ_SETMATCH_VICP", + .udesc = "TBD (experimental)", + .ucode = 0x200000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IVEGRCREDIT", + .udesc = "TBD (experimental)", + .ucode = 0x4000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_WAYS_RES", + .udesc = "TBD (experimental)", + .ucode = 0x800000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOTALLOWSNOOP", + .udesc = "TBD (experimental)", + .ucode = 0x1000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ONE_FSF_VIC", + .udesc = "TBD (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ONE_RSP_CON", + .udesc = "TBD (experimental)", + .ucode = 0x8000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_MEMMODE_TORMATCH_MULTI", + .udesc = "TBD (experimental)", + .ucode = 0x40000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_MEMMODE_TOR_MATCH", + .udesc = "TBD (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ_PMM", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PTL_INPIPE", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RMW_SETMATCH", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RRQ_SETMATCH_VICP", + .udesc = "TBD (experimental)", + .ucode = 0x100000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SETMATCHENTRYWSCT", + .udesc = "TBD (experimental)", + .ucode = 0x20000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_WAYS_RES", + .udesc = "TBD (experimental)", + .ucode = 0x400000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TOPA_MATCH", + .udesc = "TBD (experimental)", + .ucode = 0x2000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TORID_MATCH_GO_P", + .udesc = "TBD (experimental)", + .ucode = 0x1000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_AD_REQ", + .udesc = "TBD (experimental)", + .ucode = 0x80000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_AD_RSP", + .udesc = "TBD (experimental)", + .ucode = 0x100000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_BL_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x800000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_BL_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x1000000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_BL_RSP", + .udesc = "TBD (experimental)", + .ucode = 0x200000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN_BL_WB", + .udesc = "TBD (experimental)", + .ucode = 0x400000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WAY_MATCH", + .udesc = "TBD (experimental)", + .ucode = 0x4000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pmm_memmode_nm_invitox[]={ + { .uname = "LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SETCONFLICT", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pmm_memmode_nm_setconflicts[]={ + { .uname = "LLC", + .udesc = "Counts the number of times CHA saw NM Set conflict in SF/LLC (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF", + .udesc = "Counts the number of times CHA saw NM Set conflict in SF/LLC (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TOR", + .udesc = "Counts the number of times CHA saw NM Set conflict in TOR (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pmm_memmode_nm_setconflicts2[]={ + { .uname = "IODC", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEMWRNI", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pmm_qos[]={ + { .uname = "DDR4_FAST_INSERT", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REJ_IRQ", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOWTORQ_SKIP", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOW_INSERT", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "THROTTLE", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "THROTTLE_IRQ", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "THROTTLE_PRQ", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_pmm_qos_occupancy[]={ + { .uname = "DDR_FAST_FIFO", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DDR_SLOW_FIFO", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_requests[]={ + { .uname = "INVITOE", + .udesc = "TBD (experimental)", + .ucode = 0x3000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INVITOE_LOCAL", + .udesc = "TBD", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INVITOE_REMOTE", + .udesc = "TBD", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READS", + .udesc = "TBD", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READS_LOCAL", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "READS_REMOTE", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES", + .udesc = "TBD", + .ucode = 0x0c00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES_LOCAL", + .udesc = "TBD", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES_REMOTE", + .udesc = "TBD", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ring_bounces_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ring_sink_starved_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "Acknowledgements to Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_ring_sink_starved_vert[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "Acknowledgements to core (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "Data Responses to core (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "Snoops of processor's cache. (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_inserts[]={ + { .uname = "IPQ", + .udesc = "IPQ (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ", + .udesc = "IRQ (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_REJ", + .udesc = "IRQ Rejected (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ", + .udesc = "PRQ (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ_REJ", + .udesc = "PRQ (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RRQ", + .udesc = "RRQ (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBQ", + .udesc = "WBQ (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_irq0_reject[]={ + { .uname = "AD_REQ_VN0", + .udesc = "AD REQ on VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP_VN0", + .udesc = "AD RSP on VN0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_NON_UPI", + .udesc = "Non UPI AK Request (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB_VN0", + .udesc = "BL NCB on VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS_VN0", + .udesc = "BL NCS on VN0 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP_VN0", + .udesc = "BL RSP on VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB_VN0", + .udesc = "BL WB on VN0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_NON_UPI", + .udesc = "Non UPI IV Request (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_irq1_reject[]={ + { .uname = "ALLOW_SNP", + .udesc = "Allow Snoop (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY0", + .udesc = "ANY0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA", + .udesc = "HA (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_OR_SF_WAY", + .udesc = "LLC or SF Way (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_VICTIM", + .udesc = "LLC Victim (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PA_MATCH", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_VICTIM", + .udesc = "SF Victim (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VICTIM", + .udesc = "Victim (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_ismq0_retry[]={ + { .uname = "AD_REQ_VN0", + .udesc = "AD REQ on VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP_VN0", + .udesc = "AD RSP on VN0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_NON_UPI", + .udesc = "Non UPI AK Request (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB_VN0", + .udesc = "BL NCB on VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS_VN0", + .udesc = "BL NCS on VN0 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP_VN0", + .udesc = "BL RSP on VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB_VN0", + .udesc = "BL WB on VN0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_NON_UPI", + .udesc = "Non UPI IV Request (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_ismq1_retry[]={ + { .uname = "ANY0", + .udesc = "ANY0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA", + .udesc = "HA (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_occupancy[]={ + { .uname = "IPQ", + .udesc = "IPQ (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ", + .udesc = "IRQ (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RRQ", + .udesc = "RRQ (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBQ", + .udesc = "WBQ (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_other1_retry[]={ + { .uname = "ALLOW_SNP", + .udesc = "Allow Snoop (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY0", + .udesc = "ANY0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA", + .udesc = "HA (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_OR_SF_WAY", + .udesc = "LLC OR SF Way (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_VICTIM", + .udesc = "LLC Victim (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PA_MATCH", + .udesc = "PhyAddr Match (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_VICTIM", + .udesc = "SF Victim (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VICTIM", + .udesc = "Victim (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_prq0_reject[]={ + { .uname = "AD_REQ_VN0", + .udesc = "AD REQ on VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP_VN0", + .udesc = "AD RSP on VN0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_NON_UPI", + .udesc = "Non UPI AK Request (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB_VN0", + .udesc = "BL NCB on VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS_VN0", + .udesc = "BL NCS on VN0 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP_VN0", + .udesc = "BL RSP on VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB_VN0", + .udesc = "BL WB on VN0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_NON_UPI", + .udesc = "Non UPI IV Request (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_req_q1_retry[]={ + { .uname = "ALLOW_SNP", + .udesc = "Allow Snoop (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY0", + .udesc = "ANY0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA", + .udesc = "HA (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_OR_SF_WAY", + .udesc = "LLC OR SF Way (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_VICTIM", + .udesc = "LLC Victim (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PA_MATCH", + .udesc = "PhyAddr Match (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_VICTIM", + .udesc = "SF Victim (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VICTIM", + .udesc = "Victim (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_rrq0_reject[]={ + { .uname = "AD_REQ_VN0", + .udesc = "AD REQ on VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP_VN0", + .udesc = "AD RSP on VN0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_NON_UPI", + .udesc = "Non UPI AK Request (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB_VN0", + .udesc = "BL NCB on VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS_VN0", + .udesc = "BL NCS on VN0 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP_VN0", + .udesc = "BL RSP on VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB_VN0", + .udesc = "BL WB on VN0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_NON_UPI", + .udesc = "Non UPI IV Request (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_wbq0_reject[]={ + { .uname = "AD_REQ_VN0", + .udesc = "AD REQ on VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP_VN0", + .udesc = "AD RSP on VN0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_NON_UPI", + .udesc = "Non UPI AK Request (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB_VN0", + .udesc = "BL NCB on VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS_VN0", + .udesc = "BL NCS on VN0 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP_VN0", + .udesc = "BL RSP on VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB_VN0", + .udesc = "BL WB on VN0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_NON_UPI", + .udesc = "Non UPI IV Request (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxc_wbq1_reject[]={ + { .uname = "ALLOW_SNP", + .udesc = "Allow Snoop (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY0", + .udesc = "ANY0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HA", + .udesc = "HA (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_OR_SF_WAY", + .udesc = "LLC OR SF Way (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLC_VICTIM", + .udesc = "LLC Victim (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PA_MATCH", + .udesc = "PhyAddr Match (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SF_VICTIM", + .udesc = "SF Victim (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VICTIM", + .udesc = "Victim (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxr_crd_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IFV", + .udesc = "IFV - Credited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxr_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_rxr_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_sf_eviction[]={ + { .uname = "E_STATE", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M_STATE", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S_STATE", + .udesc = "TBD", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_snoops_sent[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BCST_LOCAL", + .udesc = "Broadcast snoops for Local Requests (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BCST_REMOTE", + .udesc = "Broadcast snoops for Remote Requests (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRECT_LOCAL", + .udesc = "Directed snoops for Local Requests (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRECT_REMOTE", + .udesc = "Directed snoops for Remote Requests (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL", + .udesc = "Snoops sent for Local Requests (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE", + .udesc = "Snoops sent for Remote Requests (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_snoop_resp[]={ + { .uname = "RSPCNFLCT", + .udesc = "RSPCNFLCT* (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPFWD", + .udesc = "RspFwd (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPFWDWB", + .udesc = "Rsp*Fwd*WB (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPI", + .udesc = "RspI (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPIFWD", + .udesc = "RspIFwd (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPS", + .udesc = "RspS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPSFWD", + .udesc = "RspSFwd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPWB", + .udesc = "Rsp*WB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_snoop_resp_local[]={ + { .uname = "RSPCNFLCT", + .udesc = "RspCnflct (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPFWD", + .udesc = "RspFwd (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPFWDWB", + .udesc = "Rsp*FWD*WB (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPI", + .udesc = "RspI (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPIFWD", + .udesc = "RspIFwd (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPS", + .udesc = "RspS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPSFWD", + .udesc = "RspSFwd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPWB", + .udesc = "Rsp*WB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_snoop_rsp_misc[]={ + { .uname = "MTOI_RSPDATAM", + .udesc = "MtoI RspIDataM (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MTOI_RSPIFWDM", + .udesc = "MtoI RspIFwdM (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PULLDATAPTL_HITLLC", + .udesc = "Pull Data Partial - Hit LLC (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PULLDATAPTL_HITSF", + .udesc = "Pull Data Partial - Hit SF (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPIFWDMPTL_HITLLC", + .udesc = "RspIFwdPtl Hit LLC (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPIFWDMPTL_HITSF", + .udesc = "RspIFwdPtl Hit SF (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_stall0_no_txr_horz_crd_ad_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_stall0_no_txr_horz_crd_bl_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_stall0_no_txr_horz_crd_bl_ag1[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_stall1_no_txr_horz_crd_ad_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_stall1_no_txr_horz_crd_bl_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_tor_inserts[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0xc001ff0000ff00ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "DDR", + .udesc = "DDR4 Access (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DDR4", + .udesc = "TBD (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EVICT", + .udesc = "SF/LLC Evictions (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HIT", + .udesc = "Just Hits (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA", + .udesc = "All requests from iA Cores", + .ucode = 0xc001ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CLFLUSH", + .udesc = "CLFlushes issued by iA Cores", + .ucode = 0xc8c7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CLFLUSHOPT", + .udesc = "CLFlushOpts issued by iA Cores (experimental)", + .ucode = 0xc8d7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CRD", + .udesc = "CRDs issued by iA Cores", + .ucode = 0xc80fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CRD_PREF", + .udesc = "TBD (experimental)", + .ucode = 0xc88fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD", + .udesc = "DRds issued by iA Cores (experimental)", + .ucode = 0xc817ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRDPTE", + .udesc = "DRd PTEs issued by iA Cores (experimental)", + .ucode = 0xc837ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_OPT", + .udesc = "DRd_Opts issued by iA Cores (experimental)", + .ucode = 0xc827ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores (experimental)", + .ucode = 0xc8a7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores", + .ucode = 0xc897ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT", + .udesc = "All requests from iA Cores that Hit the LLC", + .ucode = 0xc001fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_CRD", + .udesc = "CRds issued by iA Cores that Hit the LLC", + .ucode = 0xc80ffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_CRD_PREF", + .udesc = "CRd_Prefs issued by iA Cores that hit the LLC", + .ucode = 0xc88ffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD", + .udesc = "DRds issued by iA Cores that Hit the LLC", + .ucode = 0xc817fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRDPTE", + .udesc = "DRd PTEs issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc837fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_OPT", + .udesc = "DRd_Opts issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xc827fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xc8a7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores that Hit the LLC", + .ucode = 0xc897fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_ITOM", + .udesc = "ItoMs issued by iA Cores that Hit LLC (experimental)", + .ucode = 0xcc47fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xcccffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFCRD", + .udesc = "TBD (experimental)", + .ucode = 0xcccffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xccd7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFDRD", + .udesc = "TBD (experimental)", + .ucode = 0xccd7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores that hit the LLC", + .ucode = 0xccc7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_RFO", + .udesc = "RFOs issued by iA Cores that Hit the LLC", + .ucode = 0xc807fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores that Hit the LLC", + .ucode = 0xc887fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_SPECITOM", + .udesc = "SpecItoMs issued by iA Cores that hit in the LLC (experimental)", + .ucode = 0xcc57fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_ITOM", + .udesc = "ItoMs issued by iA Cores (experimental)", + .ucode = 0xcc47ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_ITOMCACHENEAR", + .udesc = "ItoMCacheNears issued by iA Cores (experimental)", + .ucode = 0xcd47ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores (experimental)", + .ucode = 0xcccfff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores", + .ucode = 0xccd7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores", + .ucode = 0xccc7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS", + .udesc = "All requests from iA Cores that Missed the LLC", + .ucode = 0xc001fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD", + .udesc = "CRds issued by iA Cores that Missed the LLC", + .ucode = 0xc80ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_LOCAL", + .udesc = "CRd issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc80efe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC", + .ucode = 0xc88ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF_LOCAL", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc88efe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF_REMOTE", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc88f7e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_REMOTE", + .udesc = "CRd issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc80f7e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD", + .udesc = "DRds issued by iA Cores that Missed the LLC", + .ucode = 0xc817fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRDPTE", + .udesc = "DRd PTEs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc837fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + .ucode = 0xc8178600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL", + .udesc = "DRds issued by iA Cores that Missed the LLC - HOMed locally", + .ucode = 0xc816fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + .ucode = 0xc8168600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + .ucode = 0xc8168a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_OPT", + .udesc = "DRd_Opt issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xc827fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xc8a7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + .ucode = 0xc8178a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores that Missed the LLC", + .ucode = 0xc897fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC (experimental)", + .ucode = 0xc8978600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL", + .udesc = "TBD", + .ucode = 0xc896fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8968600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8968a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC (experimental)", + .ucode = 0xc8978a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE", + .udesc = "TBD", + .ucode = 0xc8977e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8970600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8970a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE", + .udesc = "DRds issued by iA Cores that Missed the LLC - HOMed remotely", + .ucode = 0xc8177e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + .ucode = 0xc8170600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + .ucode = 0xc8170a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR", + .udesc = "TBD", + .ucode = 0xc867fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8678600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc8678600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8668600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc8668600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8668a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8678a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8670600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc8670600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8670a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_ITOM", + .udesc = "ItoMs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xcc47fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xcccffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores that missed the LLC", + .ucode = 0xccd7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores that missed the LLC", + .ucode = 0xccc7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8668600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8668a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc86e8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc86e8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR", + .udesc = "TBD", + .ucode = 0xc86ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86f8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86e8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc86e8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86e8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86f0600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f0600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f0a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8670600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory (experimental)", + .ucode = 0xc8670a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc86f0600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc86f0a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO", + .udesc = "RFOs issued by iA Cores that Missed the LLC", + .ucode = 0xc807fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_LOCAL", + .udesc = "RFOs issued by iA Cores that Missed the LLC - HOMed locally", + .ucode = 0xc806fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC", + .ucode = 0xc887fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF_LOCAL", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + .ucode = 0xc886fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF_REMOTE", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + .ucode = 0xc8877e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_REMOTE", + .udesc = "RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + .ucode = 0xc8077e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_SPECITOM", + .udesc = "SpecItoMs issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xcc57fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_UCRDF", + .udesc = "UCRdFs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xc877de00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL", + .udesc = "WCiLs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc86ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF", + .udesc = "WCiLF issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc867fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC (experimental)", + .ucode = 0xc8678600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC (experimental)", + .ucode = 0xc8678a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC (experimental)", + .ucode = 0xc86f8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC (experimental)", + .ucode = 0xc86f8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WIL", + .udesc = "WiLs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xc87fde00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_RFO", + .udesc = "RFOs issued by iA Cores", + .ucode = 0xc807ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores", + .ucode = 0xc887ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_SPECITOM", + .udesc = "SpecItoMs issued by iA Cores", + .ucode = 0xcc57ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBEFTOE", + .udesc = "WBEFtoEs issued by an IA Core. Non Modified Write Backs (experimental)", + .ucode = 0xcc3fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBEFTOI", + .udesc = "WBEFtoIs issued by an IA Core. Non Modified Write Backs (experimental)", + .ucode = 0xcc37ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBMTOE", + .udesc = "WBMtoEs issued by an IA Core. Non Modified Write Backs (experimental)", + .ucode = 0xcc2fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBMTOI", + .udesc = "WbMtoIs issued by an iA Cores. Modified Write Backs (experimental)", + .ucode = 0xcc27ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBSTOI", + .udesc = "WBStoIs issued by an IA Core. Non Modified Write Backs (experimental)", + .ucode = 0xcc67ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WCIL", + .udesc = "WCiLs issued by iA Cores (experimental)", + .ucode = 0xc86fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WCILF", + .udesc = "WCiLF issued by iA Cores (experimental)", + .ucode = 0xc867ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO", + .udesc = "All requests from IO Devices", + .ucode = 0xc001ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_CLFLUSH", + .udesc = "CLFlushes issued by IO Devices (experimental)", + .ucode = 0xc8c3ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT", + .udesc = "All requests from IO Devices that hit the LLC", + .ucode = 0xc001fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_ITOM", + .udesc = "ItoMs issued by IO Devices that Hit the LLC", + .ucode = 0xcc43fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + .ucode = 0xcd43fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices that hit the LLC", + .ucode = 0xc8f3fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_RFO", + .udesc = "RFOs issued by IO Devices that hit the LLC (experimental)", + .ucode = 0xc803fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOM", + .udesc = "ItoMs issued by IO Devices", + .ucode = 0xcc43ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices", + .ucode = 0xcd43ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOMCACHENEAR_LOCAL", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + .ucode = 0xcd42ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOMCACHENEAR_REMOTE", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + .ucode = 0xcd437f00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOM_LOCAL", + .udesc = "ItoMs issued by IO Devices to locally HOMed memory", + .ucode = 0xcc42ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOM_REMOTE", + .udesc = "ItoMs issued by IO Devices to remotely HOMed memory", + .ucode = 0xcc437f00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS", + .udesc = "All requests from IO Devices that missed the LLC", + .ucode = 0xc001fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_ITOM", + .udesc = "ItoMs issued by IO Devices that missed the LLC", + .ucode = 0xcc43fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + .ucode = 0xcd43fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices that missed the LLC", + .ucode = 0xc8f3fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_RFO", + .udesc = "RFOs issued by IO Devices that missed the LLC (experimental)", + .ucode = 0xc803fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices", + .ucode = 0xc8f3ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_RFO", + .udesc = "RFOs issued by IO Devices (experimental)", + .ucode = 0xc803ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WBMTOI", + .udesc = "WbMtoIs issued by IO Devices (experimental)", + .ucode = 0xcc23ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IPQ", + .udesc = "IPQ (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_IA", + .udesc = "IRQ - iA (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_NON_IA", + .udesc = "IRQ - Non iA (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ISOC", + .udesc = "Just ISOC (experimental)", + .ucode = 0x200000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_TGT", + .udesc = "Just Local Targets (experimental)", + .ucode = 0x8000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_ALL", + .udesc = "All from Local iA and IO (experimental)", + .ucode = 0xc000ff00000500ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_IA", + .udesc = "All from Local iA (experimental)", + .ucode = 0xc000ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_IO", + .udesc = "All from Local IO (experimental)", + .ucode = 0xc000ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MATCH_OPC", + .udesc = "Match the Opcode in b[29:19] of the extended umask field (experimental)", + .ucode = 0x20000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS", + .udesc = "Just Misses (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MMCFG", + .udesc = "MMCFG Access (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NEARMEM", + .udesc = "Just NearMem (experimental)", + .ucode = 0x40000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NONCOH", + .udesc = "Just NonCoherent (experimental)", + .ucode = 0x100000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_NEARMEM", + .udesc = "Just NotNearMem (experimental)", + .ucode = 0x80000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM", + .udesc = "PMM Access (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PREMORPH_OPC", + .udesc = "Match the PreMorphed Opcode in b[29:19] of the extended umask field (experimental)", + .ucode = 0x40000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ_IOSF", + .udesc = "PRQ - IOSF (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ_NON_IOSF", + .udesc = "PRQ - Non IOSF (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_TGT", + .udesc = "Just Remote Targets (experimental)", + .ucode = 0x10000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RRQ", + .udesc = "RRQ (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBQ", + .udesc = "WBQ (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_tor_occupancy[]={ + { .uname = "DDR", + .udesc = "DDR4 Access (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "EVICT", + .udesc = "SF/LLC Evictions (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HIT", + .udesc = "Just Hits (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA", + .udesc = "All requests from iA Cores", + .ucode = 0xc001ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CLFLUSH", + .udesc = "CLFlushes issued by iA Cores (experimental)", + .ucode = 0xc8c7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CLFLUSHOPT", + .udesc = "CLFlushOpts issued by iA Cores (experimental)", + .ucode = 0xc8d7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CRD", + .udesc = "CRDs issued by iA Cores", + .ucode = 0xc80fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_CRD_PREF", + .udesc = "TBD (experimental)", + .ucode = 0xc88fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD", + .udesc = "DRds issued by iA Cores", + .ucode = 0xc817ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRDPTE", + .udesc = "DRdPte issued by iA Cores due to a page walk (experimental)", + .ucode = 0xc837ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_OPT", + .udesc = "DRd_Opts issued by iA Cores (experimental)", + .ucode = 0xc827ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores (experimental)", + .ucode = 0xc8a7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores (experimental)", + .ucode = 0xc897ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT", + .udesc = "All requests from iA Cores that Hit the LLC", + .ucode = 0xc001fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_CRD", + .udesc = "CRds issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc80ffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_CRD_PREF", + .udesc = "CRd_Prefs issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xc88ffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD", + .udesc = "DRds issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc817fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRDPTE", + .udesc = "DRdPte issued by iA Cores due to a page walk that hit the LLC (experimental)", + .ucode = 0xc837fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_OPT", + .udesc = "DRd_Opts issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xc827fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xc8a7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc897fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_ITOM", + .udesc = "ItoMs issued by iA Cores that Hit LLC (experimental)", + .ucode = 0xcc47fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xcccffd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xccd7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores that hit the LLC (experimental)", + .ucode = 0xccc7fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_RFO", + .udesc = "RFOs issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc807fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_HIT_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores that Hit the LLC (experimental)", + .ucode = 0xc887fd00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_ITOM", + .udesc = "ItoMs issued by iA Cores (experimental)", + .ucode = 0xcc47ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_ITOMCACHENEAR", + .udesc = "ItoMCacheNears issued by iA Cores (experimental)", + .ucode = 0xcd47ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores (experimental)", + .ucode = 0xcccfff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores (experimental)", + .ucode = 0xccd7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores (experimental)", + .ucode = 0xccc7ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS", + .udesc = "All requests from iA Cores that Missed the LLC", + .ucode = 0xc001fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD", + .udesc = "CRds issued by iA Cores that Missed the LLC", + .ucode = 0xc80ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_LOCAL", + .udesc = "CRd issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc80efe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc88ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF_LOCAL", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc88efe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_PREF_REMOTE", + .udesc = "CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc88f7e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_CRD_REMOTE", + .udesc = "CRd issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc80f7e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD", + .udesc = "DRds issued by iA Cores that Missed the LLC", + .ucode = 0xc817fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRDPTE", + .udesc = "DRdPte issued by iA Cores due to a page walk that missed the LLC (experimental)", + .ucode = 0xc837fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + .ucode = 0xc8178600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL", + .udesc = "DRds issued by iA Cores that Missed the LLC - HOMed locally", + .ucode = 0xc816fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8168600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_LOCAL_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8168a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_OPT", + .udesc = "DRd_Opt issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xc827fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_OPT_PREF", + .udesc = "DRd_Opt_Prefs issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xc8a7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + .ucode = 0xc8178a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF", + .udesc = "DRd_Prefs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc897fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC (experimental)", + .ucode = 0xc8978600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL", + .udesc = "TBD (experimental)", + .ucode = 0xc896fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8968600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_LOCAL_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8968a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC (experimental)", + .ucode = 0xc8978a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE", + .udesc = "TBD (experimental)", + .ucode = 0xc8977e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE_DDR", + .udesc = "DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8970600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_PREF_REMOTE_PMM", + .udesc = "DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8970a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE", + .udesc = "DRds issued by iA Cores that Missed the LLC - HOMed remotely", + .ucode = 0xc8177e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE_DDR", + .udesc = "DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8170600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_DRD_REMOTE_PMM", + .udesc = "DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8170a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR", + .udesc = "TBD (experimental)", + .ucode = 0xc867fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8678600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8668600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8668a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8678a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc8670600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc8670a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_ITOM", + .udesc = "ItoMs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xcc47fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFCODE", + .udesc = "LLCPrefCode issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xcccffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFDATA", + .udesc = "LLCPrefData issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xccd7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LLCPREFRFO", + .udesc = "LLCPrefRFO issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xccc7fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8668600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc8668a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc86e8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_LOCAL_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally (experimental)", + .ucode = 0xc86e8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR", + .udesc = "TBD (experimental)", + .ucode = 0xc86ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86f8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86e8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86e8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", + .udesc = "TBD (experimental)", + .ucode = 0xc86f0600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + .udesc = "TBD (experimental)", + .ucode = 0xc86f0a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8670600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8670a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc86f0600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_REMOTE_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc86f0a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO", + .udesc = "RFOs issued by iA Cores that Missed the LLC", + .ucode = 0xc807fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_LOCAL", + .udesc = "RFOs issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc806fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc887fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF_LOCAL", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally (experimental)", + .ucode = 0xc886fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_PREF_REMOTE", + .udesc = "RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8877e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_RFO_REMOTE", + .udesc = "RFOs issued by iA Cores that Missed the LLC - HOMed remotely (experimental)", + .ucode = 0xc8077e00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_SPECITOM", + .udesc = "SpecItoMs issued by iA Cores that missed the LLC (experimental)", + .ucode = 0xcc57fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_UCRDF", + .udesc = "UCRdFs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xc877de00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL", + .udesc = "WCiLs issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc86ffe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF", + .udesc = "WCiLF issued by iA Cores that Missed the LLC (experimental)", + .ucode = 0xc867fe00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF_DDR", + .udesc = "WCiLFs issued by iA Cores targeting DDR that missed the LLC (experimental)", + .ucode = 0xc8678600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCILF_PMM", + .udesc = "WCiLFs issued by iA Cores targeting PMM that missed the LLC (experimental)", + .ucode = 0xc8678a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL_DDR", + .udesc = "WCiLs issued by iA Cores targeting DDR that missed the LLC (experimental)", + .ucode = 0xc86f8600000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WCIL_PMM", + .udesc = "WCiLs issued by iA Cores targeting PMM that missed the LLC (experimental)", + .ucode = 0xc86f8a00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_MISS_WIL", + .udesc = "WiLs issued by iA Cores that Missed LLC (experimental)", + .ucode = 0xc87fde00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_RFO", + .udesc = "RFOs issued by iA Cores", + .ucode = 0xc807ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_RFO_PREF", + .udesc = "RFO_Prefs issued by iA Cores (experimental)", + .ucode = 0xc887ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_SPECITOM", + .udesc = "SpecItoMs issued by iA Cores (experimental)", + .ucode = 0xcc57ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WBMTOI", + .udesc = "WbMtoIs issued by iA Cores (experimental)", + .ucode = 0xcc27ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WCIL", + .udesc = "WCiLs issued by iA Cores (experimental)", + .ucode = 0xc86fff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IA_WCILF", + .udesc = "WCiLF issued by iA Cores (experimental)", + .ucode = 0xc867ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO", + .udesc = "All requests from IO Devices", + .ucode = 0xc001ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_CLFLUSH", + .udesc = "CLFlushes issued by IO Devices (experimental)", + .ucode = 0xc8c3ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT", + .udesc = "All requests from IO Devices that hit the LLC", + .ucode = 0xc001fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_ITOM", + .udesc = "ItoMs issued by IO Devices that Hit the LLC (experimental)", + .ucode = 0xcc43fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC (experimental)", + .ucode = 0xcd43fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices that hit the LLC (experimental)", + .ucode = 0xc8f3fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_HIT_RFO", + .udesc = "RFOs issued by IO Devices that hit the LLC (experimental)", + .ucode = 0xc803fd00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOM", + .udesc = "ItoMs issued by IO Devices (experimental)", + .ucode = 0xcc43ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices (experimental)", + .ucode = 0xcd43ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS", + .udesc = "All requests from IO Devices that missed the LLC", + .ucode = 0xc001fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_ITOM", + .udesc = "ItoMs issued by IO Devices that missed the LLC (experimental)", + .ucode = 0xcc43fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_ITOMCACHENEAR", + .udesc = "ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC (experimental)", + .ucode = 0xcd43fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices that missed the LLC", + .ucode = 0xc8f3fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_MISS_RFO", + .udesc = "RFOs issued by IO Devices that missed the LLC (experimental)", + .ucode = 0xc803fe00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_PCIRDCUR", + .udesc = "PCIRdCurs issued by IO Devices", + .ucode = 0xc8f3ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_RFO", + .udesc = "RFOs issued by IO Devices (experimental)", + .ucode = 0xc803ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WBMTOI", + .udesc = "WbMtoIs issued by IO Devices (experimental)", + .ucode = 0xcc23ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IPQ", + .udesc = "IPQ (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_IA", + .udesc = "IRQ - iA (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IRQ_NON_IA", + .udesc = "IRQ - Non iA (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ISOC", + .udesc = "Just ISOC (experimental)", + .ucode = 0x200000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_TGT", + .udesc = "Just Local Targets (experimental)", + .ucode = 0x8000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_ALL", + .udesc = "All from Local iA and IO (experimental)", + .ucode = 0xc000ff00000500ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_IA", + .udesc = "All from Local iA (experimental)", + .ucode = 0xc000ff00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_IO", + .udesc = "All from Local IO (experimental)", + .ucode = 0xc000ff00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MATCH_OPC", + .udesc = "Match the Opcode in b[29:19] of the extended umask field (experimental)", + .ucode = 0x20000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS", + .udesc = "Just Misses (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MMCFG", + .udesc = "MMCFG Access (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NEARMEM", + .udesc = "Just NearMem (experimental)", + .ucode = 0x40000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NONCOH", + .udesc = "Just NonCoherent (experimental)", + .ucode = 0x100000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_NEARMEM", + .udesc = "Just NotNearMem (experimental)", + .ucode = 0x80000000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM", + .udesc = "PMM Access (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PREMORPH_OPC", + .udesc = "Match the PreMorphed Opcode in b[29:19] of the extended umask field (experimental)", + .ucode = 0x40000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ", + .udesc = "PRQ - IOSF (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ_NON_IOSF", + .udesc = "PRQ - Non IOSF (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_TGT", + .udesc = "Just Remote Targets (experimental)", + .ucode = 0x10000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_horz_ads_used[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_horz_cycles_full[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_horz_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_horz_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_horz_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_ads_used[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_bypass[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG1", + .udesc = "IV - Agent 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_cycles_full1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_cycles_ne0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_inserts1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_occupancy0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_occupancy1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_starved0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_txr_vert_starved1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGC", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_vert_ring_akc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_vert_ring_bl_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_vert_ring_iv_in_use[]={ + { .uname = "DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_vert_ring_tgc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_wb_push_mtoi[]={ + { .uname = "LLC", + .udesc = "Pushed to LLC (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM", + .udesc = "Pushed to Memory (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_write_no_credits[]={ + { .uname = "MC0", + .udesc = "MC0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC1", + .udesc = "MC1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC10", + .udesc = "MC10 (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC11", + .udesc = "MC11 (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC12", + .udesc = "MC12 (experimental)", + .ucode = 0x1000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC13", + .udesc = "MC13 (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC2", + .udesc = "MC2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC3", + .udesc = "MC3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC4", + .udesc = "MC4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC5", + .udesc = "MC5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC6", + .udesc = "MC6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC7", + .udesc = "MC7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC8", + .udesc = "MC8 (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MC9", + .udesc = "MC9 (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_cha_xpt_pref[]={ + { .uname = "DROP0_CONFLICT", + .udesc = "Dropped (on 0?) - Conflict (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DROP0_NOCRD", + .udesc = "Dropped (on 0?) - No Credits (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DROP1_CONFLICT", + .udesc = "Dropped (on 1?) - Conflict (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DROP1_NOCRD", + .udesc = "Dropped (on 1?) - No Credits (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SENT0", + .udesc = "Sent (on 0?) (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SENT1", + .udesc = "Sent (on 1?) (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_cha_pe[]={ + { .name = "UNC_CHA_2LM_NM_INVITOX", + .desc = "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + .code = 0x0065, + .equiv = "UNC_CHA_PMM_MEMMODE_NM_INVITOX", + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_memmode_nm_invitox), /* shared */ + .umasks = icx_unc_cha_pmm_memmode_nm_invitox, + }, + { .name = "UNC_CHA_2LM_NM_SETCONFLICTS", + .desc = "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + .code = 0x0064, + .equiv = "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS", + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_2lm_nm_setconflicts), + .umasks = icx_unc_cha_2lm_nm_setconflicts, + }, + { .name = "UNC_CHA_2LM_NM_SETCONFLICTS2", + .desc = "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + .code = 0x0070, + .equiv = "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2", + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_2lm_nm_setconflicts2), + .umasks = icx_unc_cha_2lm_nm_setconflicts2, + }, + { .name = "UNC_CHA_AG0_AD_CRD_ACQUIRED0", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0080, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_cha_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_CHA_AG0_AD_CRD_ACQUIRED1", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0081, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_cha_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_CHA_AG0_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0082, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_ad_crd_occupancy0), + .umasks = icx_unc_cha_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_CHA_AG0_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0083, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_ad_crd_occupancy1), + .umasks = icx_unc_cha_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_CHA_AG0_BL_CRD_ACQUIRED0", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0088, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_bl_crd_occupancy0), /* shared */ + .umasks = icx_unc_cha_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_CHA_AG0_BL_CRD_ACQUIRED1", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0089, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_cha_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_CHA_AG0_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008a, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_bl_crd_occupancy0), + .umasks = icx_unc_cha_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_CHA_AG0_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008b, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag0_bl_crd_occupancy1), + .umasks = icx_unc_cha_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_CHA_AG1_AD_CRD_ACQUIRED0", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0084, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_cha_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_CHA_AG1_AD_CRD_ACQUIRED1", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0085, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_cha_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_CHA_AG1_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0086, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_ad_crd_occupancy0), + .umasks = icx_unc_cha_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_CHA_AG1_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0087, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_ad_crd_occupancy1), + .umasks = icx_unc_cha_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_CHA_AG1_BL_CRD_ACQUIRED0", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008c, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_bl_crd_acquired0), + .umasks = icx_unc_cha_ag1_bl_crd_acquired0, + }, + { .name = "UNC_CHA_AG1_BL_CRD_ACQUIRED1", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_cha_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_CHA_AG1_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008e, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall0_no_txr_horz_crd_ad_ag0), /* shared */ + .umasks = icx_unc_cha_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_CHA_AG1_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008f, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ag1_bl_crd_occupancy1), + .umasks = icx_unc_cha_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_CHA_BYPASS_CHA_IMC", + .desc = "CHA to iMC Bypass", + .code = 0x0057, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_bypass_cha_imc), + .umasks = icx_unc_cha_bypass_cha_imc, + }, + { .name = "UNC_CHA_CLOCKTICKS", + .desc = "Clockticks of the uncore caching and home agent (CHA)", + .code = 0x0000, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_CHA_CMS_CLOCKTICKS", + .desc = "CMS Clockticks", + .code = 0x00c0, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_CHA_CORE_SNP", + .desc = "Core Cross Snoops Issued", + .code = 0x0033, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_core_snp), + .umasks = icx_unc_cha_core_snp, + }, + { .name = "UNC_CHA_COUNTER0_OCCUPANCY", + .desc = "Counter 0 Occupancy (experimental)", + .code = 0x001f, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_CHA_DIRECT_GO", + .desc = "Direct GO", + .code = 0x006e, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_direct_go), + .umasks = icx_unc_cha_direct_go, + }, + { .name = "UNC_CHA_DIRECT_GO_OPC", + .desc = "Direct GO", + .code = 0x006d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_direct_go_opc), + .umasks = icx_unc_cha_direct_go_opc, + }, + { .name = "UNC_CHA_DIR_LOOKUP", + .desc = "Multi-socket cacheline directory state lookups", + .code = 0x0053, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_dir_lookup), + .umasks = icx_unc_cha_dir_lookup, + }, + { .name = "UNC_CHA_DIR_UPDATE", + .desc = "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe", + .code = 0x0054, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_dir_update), + .umasks = icx_unc_cha_dir_update, + }, + { .name = "UNC_CHA_DISTRESS_ASSERTED", + .desc = "Distress signal asserted", + .code = 0x00af, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_distress_asserted), + .umasks = icx_unc_cha_distress_asserted, + }, + { .name = "UNC_CHA_EGRESS_ORDERING", + .desc = "Egress Blocking due to Ordering requirements", + .code = 0x00ba, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_egress_ordering), + .umasks = icx_unc_cha_egress_ordering, + }, + { .name = "UNC_CHA_HITME_HIT", + .desc = "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + .code = 0x005f, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_hitme_hit), + .umasks = icx_unc_cha_hitme_hit, + }, + { .name = "UNC_CHA_HITME_LOOKUP", + .desc = "Counts Number of times HitMe Cache is accessed", + .code = 0x005e, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_hitme_lookup), + .umasks = icx_unc_cha_hitme_lookup, + }, + { .name = "UNC_CHA_HITME_MISS", + .desc = "Counts Number of Misses in HitMe Cache", + .code = 0x0060, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_hitme_miss), + .umasks = icx_unc_cha_hitme_miss, + }, + { .name = "UNC_CHA_HITME_UPDATE", + .desc = "Counts the number of Allocate/Update to HitMe Cache", + .code = 0x0061, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_hitme_update), + .umasks = icx_unc_cha_hitme_update, + }, + { .name = "UNC_CHA_HORZ_RING_AD_IN_USE", + .desc = "Horizontal AD Ring In Use", + .code = 0x00b6, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_horz_ring_akc_in_use), /* shared */ + .umasks = icx_unc_cha_horz_ring_akc_in_use, + }, + { .name = "UNC_CHA_HORZ_RING_AKC_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00bb, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_horz_ring_akc_in_use), + .umasks = icx_unc_cha_horz_ring_akc_in_use, + }, + { .name = "UNC_CHA_HORZ_RING_AK_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00b7, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_horz_ring_bl_in_use), /* shared */ + .umasks = icx_unc_cha_horz_ring_bl_in_use, + }, + { .name = "UNC_CHA_HORZ_RING_BL_IN_USE", + .desc = "Horizontal BL Ring in Use", + .code = 0x00b8, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_horz_ring_bl_in_use), + .umasks = icx_unc_cha_horz_ring_bl_in_use, + }, + { .name = "UNC_CHA_HORZ_RING_IV_IN_USE", + .desc = "Horizontal IV Ring in Use", + .code = 0x00b9, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_horz_ring_iv_in_use), + .umasks = icx_unc_cha_horz_ring_iv_in_use, + }, + { .name = "UNC_CHA_IMC_READS_COUNT", + .desc = "Normal priority reads issued to the memory controller from the CHA", + .code = 0x0059, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_imc_reads_count), + .umasks = icx_unc_cha_imc_reads_count, + }, + { .name = "UNC_CHA_IMC_WRITES_COUNT", + .desc = "CHA to iMC Full Line Writes Issued", + .code = 0x005b, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_imc_writes_count), + .umasks = icx_unc_cha_imc_writes_count, + }, + { .name = "UNC_CHA_LLC_LOOKUP", + .desc = "Cache and Snoop Filter Lookups; Data Read Request", + .code = 0x0034, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_llc_lookup), + .umasks = icx_unc_cha_llc_lookup, + }, + { .name = "UNC_CHA_LLC_VICTIMS", + .desc = "Lines Victimized", + .code = 0x0037, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_llc_victims), + .umasks = icx_unc_cha_llc_victims, + }, + { .name = "UNC_CHA_MISC", + .desc = "Number of times that an RFO hit in S state.", + .code = 0x0039, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_misc), + .umasks = icx_unc_cha_misc, + }, + { .name = "UNC_CHA_MISC_EXTERNAL", + .desc = "Miscellaneous Events (mostly from MS2IDI)", + .code = 0x00e6, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_misc_external), + .umasks = icx_unc_cha_misc_external, + }, + { .name = "UNC_CHA_OSB", + .desc = "OSB Snoop Broadcast", + .code = 0x0055, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_osb), + .umasks = icx_unc_cha_osb, + }, + { .name = "UNC_CHA_PIPE_REJECT", + .desc = "Pipe Rejects", + .code = 0x0042, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pipe_reject), + .umasks = icx_unc_cha_pipe_reject, + }, + { .name = "UNC_CHA_PMM_MEMMODE_NM_INVITOX", + .desc = "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + .code = 0x0065, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_memmode_nm_invitox), + .umasks = icx_unc_cha_pmm_memmode_nm_invitox, + }, + { .name = "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS", + .desc = "PMM Memory Mode related events", + .code = 0x0064, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_memmode_nm_setconflicts), + .umasks = icx_unc_cha_pmm_memmode_nm_setconflicts, + }, + { .name = "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2", + .desc = "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + .code = 0x0070, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_memmode_nm_setconflicts2), + .umasks = icx_unc_cha_pmm_memmode_nm_setconflicts2, + }, + { .name = "UNC_CHA_PMM_QOS", + .desc = "UNC_CHA_PMM_QOS.SLOW_INSERT", + .code = 0x0066, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_qos), + .umasks = icx_unc_cha_pmm_qos, + }, + { .name = "UNC_CHA_PMM_QOS_OCCUPANCY", + .desc = "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + .code = 0x0067, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_pmm_qos_occupancy), + .umasks = icx_unc_cha_pmm_qos_occupancy, + }, + { .name = "UNC_CHA_READ_NO_CREDITS", + .desc = "CHA iMC CHNx READ Credits Empty", + .code = 0x0058, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_write_no_credits), /* shared */ + .umasks = icx_unc_cha_write_no_credits, + }, + { .name = "UNC_CHA_REQUESTS", + .desc = "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent", + .code = 0x0050, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_requests), + .umasks = icx_unc_cha_requests, + }, + { .name = "UNC_CHA_RING_BOUNCES_HORZ", + .desc = "Messages that bounced on the Horizontal Ring.", + .code = 0x00ac, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ring_bounces_horz), + .umasks = icx_unc_cha_ring_bounces_horz, + }, + { .name = "UNC_CHA_RING_BOUNCES_VERT", + .desc = "Messages that bounced on the Vertical Ring.", + .code = 0x00aa, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ring_sink_starved_vert), /* shared */ + .umasks = icx_unc_cha_ring_sink_starved_vert, + }, + { .name = "UNC_CHA_RING_SINK_STARVED_HORZ", + .desc = "Sink Starvation on Horizontal Ring", + .code = 0x00ad, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ring_sink_starved_horz), + .umasks = icx_unc_cha_ring_sink_starved_horz, + }, + { .name = "UNC_CHA_RING_SINK_STARVED_VERT", + .desc = "Sink Starvation on Vertical Ring", + .code = 0x00ab, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_ring_sink_starved_vert), + .umasks = icx_unc_cha_ring_sink_starved_vert, + }, + { .name = "UNC_CHA_RING_SRC_THRTL", + .desc = "Source Throttle (experimental)", + .code = 0x00ae, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_CHA_RxC_INSERTS", + .desc = "Ingress (from CMS) Allocations", + .code = 0x0013, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_inserts), + .umasks = icx_unc_cha_rxc_inserts, + }, + { .name = "UNC_CHA_RxC_IPQ0_REJECT", + .desc = "IPQ Requests (from CMS) Rejected - Set 0", + .code = 0x0022, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_irq0_reject), /* shared */ + .umasks = icx_unc_cha_rxc_irq0_reject, + }, + { .name = "UNC_CHA_RxC_IPQ1_REJECT", + .desc = "IPQ Requests (from CMS) Rejected - Set 1", + .code = 0x0023, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_other1_retry), /* shared */ + .umasks = icx_unc_cha_rxc_other1_retry, + }, + { .name = "UNC_CHA_RxC_IRQ0_REJECT", + .desc = "IRQ Requests (from CMS) Rejected - Set 0", + .code = 0x0018, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_irq0_reject), + .umasks = icx_unc_cha_rxc_irq0_reject, + }, + { .name = "UNC_CHA_RxC_IRQ1_REJECT", + .desc = "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + .code = 0x0019, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_irq1_reject), + .umasks = icx_unc_cha_rxc_irq1_reject, + }, + { .name = "UNC_CHA_RxC_ISMQ0_REJECT", + .desc = "ISMQ Rejects - Set 0", + .code = 0x0024, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_ismq0_retry), /* shared */ + .umasks = icx_unc_cha_rxc_ismq0_retry, + }, + { .name = "UNC_CHA_RxC_ISMQ0_RETRY", + .desc = "ISMQ Retries - Set 0", + .code = 0x002c, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_ismq0_retry), + .umasks = icx_unc_cha_rxc_ismq0_retry, + }, + { .name = "UNC_CHA_RxC_ISMQ1_REJECT", + .desc = "ISMQ Rejects - Set 1", + .code = 0x0025, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_ismq1_retry), /* shared */ + .umasks = icx_unc_cha_rxc_ismq1_retry, + }, + { .name = "UNC_CHA_RxC_ISMQ1_RETRY", + .desc = "ISMQ Retries - Set 1", + .code = 0x002d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_ismq1_retry), + .umasks = icx_unc_cha_rxc_ismq1_retry, + }, + { .name = "UNC_CHA_RxC_OCCUPANCY", + .desc = "Ingress (from CMS) Occupancy", + .code = 0x0011, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0x1ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_occupancy), + .umasks = icx_unc_cha_rxc_occupancy, + }, + { .name = "UNC_CHA_RxC_OTHER0_RETRY", + .desc = "Other Retries - Set 0", + .code = 0x002e, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_prq0_reject), /* shared */ + .umasks = icx_unc_cha_rxc_prq0_reject, + }, + { .name = "UNC_CHA_RxC_OTHER1_RETRY", + .desc = "Other Retries - Set 1", + .code = 0x002f, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_other1_retry), + .umasks = icx_unc_cha_rxc_other1_retry, + }, + { .name = "UNC_CHA_RxC_PRQ0_REJECT", + .desc = "PRQ Requests (from CMS) Rejected - Set 0", + .code = 0x0020, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_prq0_reject), + .umasks = icx_unc_cha_rxc_prq0_reject, + }, + { .name = "UNC_CHA_RxC_PRQ1_REJECT", + .desc = "PRQ Requests (from CMS) Rejected - Set 1", + .code = 0x0021, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_req_q1_retry), /* shared */ + .umasks = icx_unc_cha_rxc_req_q1_retry, + }, + { .name = "UNC_CHA_RxC_REQ_Q0_RETRY", + .desc = "Request Queue Retries - Set 0", + .code = 0x002a, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_rrq0_reject), /* shared */ + .umasks = icx_unc_cha_rxc_rrq0_reject, + }, + { .name = "UNC_CHA_RxC_REQ_Q1_RETRY", + .desc = "Request Queue Retries - Set 1", + .code = 0x002b, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_req_q1_retry), + .umasks = icx_unc_cha_rxc_req_q1_retry, + }, + { .name = "UNC_CHA_RxC_RRQ0_REJECT", + .desc = "RRQ Rejects - Set 0", + .code = 0x0026, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_rrq0_reject), + .umasks = icx_unc_cha_rxc_rrq0_reject, + }, + { .name = "UNC_CHA_RxC_RRQ1_REJECT", + .desc = "RRQ Rejects - Set 1", + .code = 0x0027, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_wbq1_reject), /* shared */ + .umasks = icx_unc_cha_rxc_wbq1_reject, + }, + { .name = "UNC_CHA_RxC_WBQ0_REJECT", + .desc = "WBQ Rejects - Set 0", + .code = 0x0028, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_wbq0_reject), + .umasks = icx_unc_cha_rxc_wbq0_reject, + }, + { .name = "UNC_CHA_RxC_WBQ1_REJECT", + .desc = "WBQ Rejects - Set 1", + .code = 0x0029, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxc_wbq1_reject), + .umasks = icx_unc_cha_rxc_wbq1_reject, + }, + { .name = "UNC_CHA_RxR_BUSY_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e5, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_ads_used), /* shared */ + .umasks = icx_unc_cha_txr_horz_ads_used, + }, + { .name = "UNC_CHA_RxR_BYPASS", + .desc = "Transgress Ingress Bypass", + .code = 0x00e2, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxr_inserts), /* shared */ + .umasks = icx_unc_cha_rxr_inserts, + }, + { .name = "UNC_CHA_RxR_CRD_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e3, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxr_crd_starved), + .umasks = icx_unc_cha_rxr_crd_starved, + }, + { .name = "UNC_CHA_RxR_CRD_STARVED_1", + .desc = "Transgress Injection Starvation (experimental)", + .code = 0x00e4, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_CHA_RxR_INSERTS", + .desc = "Transgress Ingress Allocations", + .code = 0x00e1, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxr_inserts), + .umasks = icx_unc_cha_rxr_inserts, + }, + { .name = "UNC_CHA_RxR_OCCUPANCY", + .desc = "Transgress Ingress Occupancy", + .code = 0x00e0, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_rxr_occupancy), + .umasks = icx_unc_cha_rxr_occupancy, + }, + { .name = "UNC_CHA_SF_EVICTION", + .desc = "Snoop filter capacity evictions for E-state entries.", + .code = 0x003d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_sf_eviction), + .umasks = icx_unc_cha_sf_eviction, + }, + { .name = "UNC_CHA_SNOOPS_SENT", + .desc = "Snoops Sent", + .code = 0x0051, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_snoops_sent), + .umasks = icx_unc_cha_snoops_sent, + }, + { .name = "UNC_CHA_SNOOP_RESP", + .desc = "Snoop Responses Received", + .code = 0x005c, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_snoop_resp), + .umasks = icx_unc_cha_snoop_resp, + }, + { .name = "UNC_CHA_SNOOP_RESP_LOCAL", + .desc = "Snoop Responses Received Local", + .code = 0x005d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_snoop_resp_local), + .umasks = icx_unc_cha_snoop_resp_local, + }, + { .name = "UNC_CHA_SNOOP_RSP_MISC", + .desc = "Misc Snoop Responses Received", + .code = 0x006b, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_snoop_rsp_misc), + .umasks = icx_unc_cha_snoop_rsp_misc, + }, + { .name = "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d0, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall0_no_txr_horz_crd_ad_ag0), + .umasks = icx_unc_cha_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d2, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall0_no_txr_horz_crd_bl_ag0), /* shared */ + .umasks = icx_unc_cha_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d4, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall0_no_txr_horz_crd_bl_ag0), + .umasks = icx_unc_cha_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d6, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall0_no_txr_horz_crd_bl_ag1), + .umasks = icx_unc_cha_stall0_no_txr_horz_crd_bl_ag1, + }, + { .name = "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d1, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall1_no_txr_horz_crd_ad_ag1_1), /* shared */ + .umasks = icx_unc_cha_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d3, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall1_no_txr_horz_crd_ad_ag1_1), + .umasks = icx_unc_cha_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d5, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall1_no_txr_horz_crd_bl_ag1_1), /* shared */ + .umasks = icx_unc_cha_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d7, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_stall1_no_txr_horz_crd_bl_ag1_1), + .umasks = icx_unc_cha_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_CHA_TOR_INSERTS", + .desc = "TOR Inserts", + .code = 0x0035, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_tor_inserts), + .umasks = icx_unc_cha_tor_inserts, + }, + { .name = "UNC_CHA_TOR_OCCUPANCY", + .desc = "TOR Occupancy", + .code = 0x0036, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0x1ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_tor_occupancy), + .umasks = icx_unc_cha_tor_occupancy, + }, + { .name = "UNC_CHA_TxR_HORZ_ADS_USED", + .desc = "CMS Horizontal ADS Used", + .code = 0x00a6, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_ads_used), + .umasks = icx_unc_cha_txr_horz_ads_used, + }, + { .name = "UNC_CHA_TxR_HORZ_BYPASS", + .desc = "CMS Horizontal Bypass Used", + .code = 0x00a7, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_cycles_full), /* shared */ + .umasks = icx_unc_cha_txr_horz_cycles_full, + }, + { .name = "UNC_CHA_TxR_HORZ_CYCLES_FULL", + .desc = "Cycles CMS Horizontal Egress Queue is Full", + .code = 0x00a2, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_cycles_full), + .umasks = icx_unc_cha_txr_horz_cycles_full, + }, + { .name = "UNC_CHA_TxR_HORZ_CYCLES_NE", + .desc = "Cycles CMS Horizontal Egress Queue is Not Empty", + .code = 0x00a3, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_inserts), /* shared */ + .umasks = icx_unc_cha_txr_horz_inserts, + }, + { .name = "UNC_CHA_TxR_HORZ_INSERTS", + .desc = "CMS Horizontal Egress Inserts", + .code = 0x00a1, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_inserts), + .umasks = icx_unc_cha_txr_horz_inserts, + }, + { .name = "UNC_CHA_TxR_HORZ_NACK", + .desc = "CMS Horizontal Egress NACKs", + .code = 0x00a4, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_occupancy), /* shared */ + .umasks = icx_unc_cha_txr_horz_occupancy, + }, + { .name = "UNC_CHA_TxR_HORZ_OCCUPANCY", + .desc = "CMS Horizontal Egress Occupancy", + .code = 0x00a0, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_occupancy), + .umasks = icx_unc_cha_txr_horz_occupancy, + }, + { .name = "UNC_CHA_TxR_HORZ_STARVED", + .desc = "CMS Horizontal Egress Injection Starvation", + .code = 0x00a5, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_horz_starved), + .umasks = icx_unc_cha_txr_horz_starved, + }, + { .name = "UNC_CHA_TxR_VERT_ADS_USED", + .desc = "CMS Vertical ADS Used", + .code = 0x009c, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_ads_used), + .umasks = icx_unc_cha_txr_vert_ads_used, + }, + { .name = "UNC_CHA_TxR_VERT_BYPASS", + .desc = "CMS Vertical ADS Used", + .code = 0x009d, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_bypass), + .umasks = icx_unc_cha_txr_vert_bypass, + }, + { .name = "UNC_CHA_TxR_VERT_BYPASS_1", + .desc = "CMS Vertical ADS Used", + .code = 0x009e, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_cycles_full1), /* shared */ + .umasks = icx_unc_cha_txr_vert_cycles_full1, + }, + { .name = "UNC_CHA_TxR_VERT_CYCLES_FULL0", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0094, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_cycles_ne0), /* shared */ + .umasks = icx_unc_cha_txr_vert_cycles_ne0, + }, + { .name = "UNC_CHA_TxR_VERT_CYCLES_FULL1", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0095, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_cycles_full1), + .umasks = icx_unc_cha_txr_vert_cycles_full1, + }, + { .name = "UNC_CHA_TxR_VERT_CYCLES_NE0", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0096, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_cycles_ne0), + .umasks = icx_unc_cha_txr_vert_cycles_ne0, + }, + { .name = "UNC_CHA_TxR_VERT_CYCLES_NE1", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0097, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_inserts1), /* shared */ + .umasks = icx_unc_cha_txr_vert_inserts1, + }, + { .name = "UNC_CHA_TxR_VERT_INSERTS0", + .desc = "CMS Vert Egress Allocations", + .code = 0x0092, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_occupancy0), /* shared */ + .umasks = icx_unc_cha_txr_vert_occupancy0, + }, + { .name = "UNC_CHA_TxR_VERT_INSERTS1", + .desc = "CMS Vert Egress Allocations", + .code = 0x0093, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_inserts1), + .umasks = icx_unc_cha_txr_vert_inserts1, + }, + { .name = "UNC_CHA_TxR_VERT_NACK0", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0098, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_starved0), /* shared */ + .umasks = icx_unc_cha_txr_vert_starved0, + }, + { .name = "UNC_CHA_TxR_VERT_NACK1", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0099, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_occupancy1), /* shared */ + .umasks = icx_unc_cha_txr_vert_occupancy1, + }, + { .name = "UNC_CHA_TxR_VERT_OCCUPANCY0", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0090, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_occupancy0), + .umasks = icx_unc_cha_txr_vert_occupancy0, + }, + { .name = "UNC_CHA_TxR_VERT_OCCUPANCY1", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0091, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_occupancy1), + .umasks = icx_unc_cha_txr_vert_occupancy1, + }, + { .name = "UNC_CHA_TxR_VERT_STARVED0", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009a, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_starved0), + .umasks = icx_unc_cha_txr_vert_starved0, + }, + { .name = "UNC_CHA_TxR_VERT_STARVED1", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009b, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_txr_vert_starved1), + .umasks = icx_unc_cha_txr_vert_starved1, + }, + { .name = "UNC_CHA_VERT_RING_AD_IN_USE", + .desc = "Vertical AD Ring In Use", + .code = 0x00b0, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_akc_in_use), /* shared */ + .umasks = icx_unc_cha_vert_ring_akc_in_use, + }, + { .name = "UNC_CHA_VERT_RING_AKC_IN_USE", + .desc = "Vertical AKC Ring In Use", + .code = 0x00b4, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_akc_in_use), + .umasks = icx_unc_cha_vert_ring_akc_in_use, + }, + { .name = "UNC_CHA_VERT_RING_AK_IN_USE", + .desc = "Vertical AK Ring In Use", + .code = 0x00b1, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_bl_in_use), /* shared */ + .umasks = icx_unc_cha_vert_ring_bl_in_use, + }, + { .name = "UNC_CHA_VERT_RING_BL_IN_USE", + .desc = "Vertical BL Ring in Use", + .code = 0x00b2, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_bl_in_use), + .umasks = icx_unc_cha_vert_ring_bl_in_use, + }, + { .name = "UNC_CHA_VERT_RING_IV_IN_USE", + .desc = "Vertical IV Ring in Use", + .code = 0x00b3, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_iv_in_use), + .umasks = icx_unc_cha_vert_ring_iv_in_use, + }, + { .name = "UNC_CHA_VERT_RING_TGC_IN_USE", + .desc = "Vertical TGC Ring In Use", + .code = 0x00b5, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_vert_ring_tgc_in_use), + .umasks = icx_unc_cha_vert_ring_tgc_in_use, + }, + { .name = "UNC_CHA_WB_PUSH_MTOI", + .desc = "WbPushMtoI", + .code = 0x0056, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_wb_push_mtoi), + .umasks = icx_unc_cha_wb_push_mtoi, + }, + { .name = "UNC_CHA_WRITE_NO_CREDITS", + .desc = "CHA iMC CHNx WRITE Credits Empty", + .code = 0x005a, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_write_no_credits), + .umasks = icx_unc_cha_write_no_credits, + }, + { .name = "UNC_CHA_XPT_PREF", + .desc = "XPT Prefetches", + .code = 0x006f, + .modmsk = ICX_UNC_CHA_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_cha_xpt_pref), + .umasks = icx_unc_cha_xpt_pref, + }, +}; +/* 132 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_iio_events.h b/src/libpfm4/lib/events/intel_icx_unc_iio_events.h new file mode 100644 index 000000000..e7d667f58 --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_iio_events.h @@ -0,0 +1,2310 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_iio (IcelakeX Uncore IIO) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_iio_bandwidth_in[]={ + { .uname = "PART0_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART1_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART2_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART3_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART4_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART5_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART6_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART7_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_bandwidth_out[]={ + { .uname = "PART0_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART1_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART2_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART3_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART4_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART5_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART6_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PART7_FREERUN", + .udesc = "TBD (experimental)", + .ucode = 0x0000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_comp_buf_occupancy[]={ + { .uname = "CMPD_ALL", + .udesc = "Part 0-7 (experimental)", + .ucode = 0x400000000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_ALL_PARTS", + .udesc = "Part 0-7", + .ucode = 0x400000000ff00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART0", + .udesc = "Part 0", + .ucode = 0x4000000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART1", + .udesc = "Part 1", + .ucode = 0x4000000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART2", + .udesc = "Part 2", + .ucode = 0x4000000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART3", + .udesc = "Part 3", + .ucode = 0x4000000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART4", + .udesc = "Part 4", + .ucode = 0x4000000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART5", + .udesc = "Part 5", + .ucode = 0x4000000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART6", + .udesc = "Part 6", + .ucode = 0x4000000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART7", + .udesc = "Part 7", + .ucode = 0x4000000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_data_req_by_cpu[]={ + { .uname = "CFG_READ_IOMMU0", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7100000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_IOMMU1", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7200000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART0", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7001000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART1", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7002000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART2", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7004000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART3", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7008000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART4", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7010000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART5", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7020000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART6", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7040000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART7", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7080000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_IOMMU0", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7100000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_IOMMU1", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7200000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART0", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7001000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART1", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7002000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART2", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7004000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART3", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7008000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART4", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7010000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART5", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7020000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART6", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7040000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART7", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7080000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_IOMMU0", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7100000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_IOMMU1", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7200000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART0", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7001000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART1", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7002000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART2", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7004000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART3", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7008000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART4", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7010000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART5", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7020000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART6", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7040000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART7", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7080000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_IOMMU0", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7100000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_IOMMU1", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7200000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART0", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7001000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART1", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7002000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART2", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7004000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART3", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7008000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART4", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7010000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART5", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7020000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART6", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7040000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART7", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7080000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU0", + .udesc = "Core reporting completion of Card read from Core DRAM (experimental)", + .ucode = 0x7100000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU1", + .udesc = "Core reporting completion of Card read from Core DRAM (experimental)", + .ucode = 0x7200000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART0", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7001000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART1", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7002000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART2", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7004000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART3", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7008000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART4", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7010000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART5", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7020000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART6", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7040000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART7", + .udesc = "Core reporting completion of Card read from Core DRAM", + .ucode = 0x7080000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU0", + .udesc = "Core writing to Card's MMIO space (experimental)", + .ucode = 0x7100000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU1", + .udesc = "Core writing to Card's MMIO space (experimental)", + .ucode = 0x7200000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART0", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7001000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART1", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7002000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART2", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7004000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART3", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7008000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART4", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7010000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART5", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7020000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART6", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7040000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART7", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7080000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU0", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7100000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU1", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7200000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART0", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7001000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART1", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7002000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART2", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7004000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART3", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7008000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART4", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7010000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART5", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7020000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART6", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7040000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART7", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7080000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU0", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7100000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU1", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7200000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART0", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7001000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART1", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7002000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART2", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7004000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART3", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7008000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART4", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7010000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART5", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7020000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART6", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7040000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART7", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7080000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_data_req_of_cpu[]={ + { .uname = "ATOMIC_IOMMU0", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7100000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_IOMMU1", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7200000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART0", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7001000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART1", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7002000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART2", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7004000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART3", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7008000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART4", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7010000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART5", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7020000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART6", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7040000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART7", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7080000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_IOMMU0", + .udesc = "CmpD - device sending completion to CPU request (experimental)", + .ucode = 0x7100000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_IOMMU1", + .udesc = "CmpD - device sending completion to CPU request (experimental)", + .ucode = 0x7200000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART0", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7001000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART1", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7002000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART2", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7004000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART3", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7008000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART4", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7010000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART5", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7020000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART6", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7040000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART7", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7080000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU0", + .udesc = "Card reading from DRAM (experimental)", + .ucode = 0x7100000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU1", + .udesc = "Card reading from DRAM (experimental)", + .ucode = 0x7200000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART0", + .udesc = "Card reading from DRAM", + .ucode = 0x7001000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART1", + .udesc = "Card reading from DRAM", + .ucode = 0x7002000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART2", + .udesc = "Card reading from DRAM", + .ucode = 0x7004000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART3", + .udesc = "Card reading from DRAM", + .ucode = 0x7008000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART4", + .udesc = "Card reading from DRAM", + .ucode = 0x7010000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART5", + .udesc = "Card reading from DRAM", + .ucode = 0x7020000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART6", + .udesc = "Card reading from DRAM", + .ucode = 0x7040000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART7", + .udesc = "Card reading from DRAM", + .ucode = 0x7080000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU0", + .udesc = "Card writing to DRAM (experimental)", + .ucode = 0x7100000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU1", + .udesc = "Card writing to DRAM (experimental)", + .ucode = 0x7200000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART0", + .udesc = "Card writing to DRAM", + .ucode = 0x7001000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART1", + .udesc = "Card writing to DRAM", + .ucode = 0x7002000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART2", + .udesc = "Card writing to DRAM", + .ucode = 0x7004000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART3", + .udesc = "Card writing to DRAM", + .ucode = 0x7008000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART4", + .udesc = "Card writing to DRAM", + .ucode = 0x7010000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART5", + .udesc = "Card writing to DRAM", + .ucode = 0x7020000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART6", + .udesc = "Card writing to DRAM", + .ucode = 0x7040000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART7", + .udesc = "Card writing to DRAM", + .ucode = 0x7080000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_IOMMU0", + .udesc = "Messages (experimental)", + .ucode = 0x7100000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_IOMMU1", + .udesc = "Messages (experimental)", + .ucode = 0x7200000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART0", + .udesc = "Messages (experimental)", + .ucode = 0x7001000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART1", + .udesc = "Messages (experimental)", + .ucode = 0x7002000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART2", + .udesc = "Messages (experimental)", + .ucode = 0x7004000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART3", + .udesc = "Messages (experimental)", + .ucode = 0x7008000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART4", + .udesc = "Messages (experimental)", + .ucode = 0x7010000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART5", + .udesc = "Messages (experimental)", + .ucode = 0x7020000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART6", + .udesc = "Messages (experimental)", + .ucode = 0x7040000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART7", + .udesc = "Messages (experimental)", + .ucode = 0x7080000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU0", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7100000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU1", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7200000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART0", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7001000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART1", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7002000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART2", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7004000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART3", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7008000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART4", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7010000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART5", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7020000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART6", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7040000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART7", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7080000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU0", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7100000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU1", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7200000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART0", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7001000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART1", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7002000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART2", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7004000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART3", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7008000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART4", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7010000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART5", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7020000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART6", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7040000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART7", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7080000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_inbound_arb_won[]={ + { .uname = "DATA", + .udesc = "Passing data to be written (experimental)", + .ucode = 0x70ff000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FINAL_RD_WR", + .udesc = "Issuing final read or write of line (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_HIT", + .udesc = "Processing response from IOMMU (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_REQ", + .udesc = "Issuing to IOMMU (experimental)", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_OWN", + .udesc = "Request Ownership (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Writing line (experimental)", + .ucode = 0x70ff000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_iommu0[]={ + { .uname = "1G_HITS", + .udesc = "IOTLB Hits to a 1G Page (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "2M_HITS", + .udesc = "IOTLB Hits to a 2M Page (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "4K_HITS", + .udesc = "IOTLB Hits to a 4K Page (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_LOOKUPS", + .udesc = "IOTLB lookups all (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CTXT_CACHE_HITS", + .udesc = "Context cache hits (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CTXT_CACHE_LOOKUPS", + .udesc = "Context cache lookups (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FIRST_LOOKUPS", + .udesc = "IOTLB lookups first (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISSES", + .udesc = "IOTLB Fills (same as IOTLB miss) (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_iommu1[]={ + { .uname = "CYC_PWT_FULL", + .udesc = "Cycles PWT full (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_MEM_ACCESSES", + .udesc = "IOMMU memory access (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWC_1G_HITS", + .udesc = "PWC Hit to a 1G page (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWC_2M_HITS", + .udesc = "PWC Hit to a 2M page (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWC_4K_HITS", + .udesc = "PWC Hit to a 4K page (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWC_512G_HITS", + .udesc = "PWT Hit to a 256T page (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWC_CACHE_FILLS", + .udesc = "PageWalk cache fill (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWT_CACHE_LOOKUPS", + .udesc = "PageWalk cache lookup (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_iommu3[]={ + { .uname = "INT_CACHE_HITS", + .udesc = "Interrupt Entry cache hit (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INT_CACHE_LOOKUPS", + .udesc = "Interrupt Entry cache lookup (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_CTXT_CACHE_INVAL_DEVICE", + .udesc = "Device-selective Context cache invalidation cycles (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_CTXT_CACHE_INVAL_DOMAIN", + .udesc = "Domain-selective Context cache invalidation cycles (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_CTXT_CACHE_INVAL_GBL", + .udesc = "Context cache global invalidation cycles (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_INVAL_DOMAIN", + .udesc = "Domain-selective IOTLB invalidation cycles (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_INVAL_GBL", + .udesc = "Global IOTLB invalidation cycles (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NUM_INVAL_PAGE", + .udesc = "Page-selective IOTLB invalidation cycles (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_mask_match_or[]={ + { .uname = "BUS0", + .udesc = "Non-PCIE bus (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BUS0_BUS1", + .udesc = "Non-PCIE bus and PCIE bus (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BUS0_NOT_BUS1", + .udesc = "Non-PCIE bus and !(PCIE bus) (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BUS1", + .udesc = "PCIE bus (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_BUS0_BUS1", + .udesc = "!(Non-PCIE bus) and PCIE bus (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_BUS0_NOT_BUS1", + .udesc = "!(Non-PCIE bus) and !(PCIE bus) (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_num_oustanding_req_from_cpu[]={ + { .uname = "TO_IO", + .udesc = "To device (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_num_outstanding_req_of_cpu[]={ + { .uname = "DATA", + .udesc = "Passing data to be written (experimental)", + .ucode = 0x70ff000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FINAL_RD_WR", + .udesc = "Issuing final read or write of line (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_HIT", + .udesc = "Processing response from IOMMU (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_REQ", + .udesc = "Issuing to IOMMU (experimental)", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_OWN", + .udesc = "Request Ownership (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Writing line (experimental)", + .ucode = 0x70ff000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_num_req_from_cpu[]={ + { .uname = "IRP", + .udesc = "From IRP (experimental)", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ITC", + .udesc = "From ITC (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PREALLOC", + .udesc = "Completion allocations (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_num_req_of_cpu[]={ + { .uname = "ALL_DROP", + .udesc = "Drop request (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "COMMIT_ALL", + .udesc = "All", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_num_req_of_cpu_by_tgt[]={ + { .uname = "ABORT", + .udesc = "Abort (experimental)", + .ucode = 0x70ff000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CONFINED_P2P", + .udesc = "Confined P2P (experimental)", + .ucode = 0x70ff000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_P2P", + .udesc = "Local P2P (experimental)", + .ucode = 0x70ff000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MCAST", + .udesc = "Multi-cast (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM", + .udesc = "Memory (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSGB", + .udesc = "MsgB (experimental)", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REM_P2P", + .udesc = "Remote P2P (experimental)", + .ucode = 0x70ff000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UBOX", + .udesc = "Ubox (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_outbound_cl_reqs_issued[]={ + { .uname = "TO_IO", + .udesc = "64B requests issued to device (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_outbound_tlp_reqs_issued[]={ + { .uname = "TO_IO", + .udesc = "To device (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_req_from_pcie_cmpl[]={ + { .uname = "DATA", + .udesc = "Passing data to be written (experimental)", + .ucode = 0x70ff000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FINAL_RD_WR", + .udesc = "Issuing final read or write of line (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_HIT", + .udesc = "Processing response from IOMMU (experimental)", + .ucode = 0x70ff000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IOMMU_REQ", + .udesc = "Issuing to IOMMU (experimental)", + .ucode = 0x70ff000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_OWN", + .udesc = "Request Ownership (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Writing line (experimental)", + .ucode = 0x70ff000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_req_from_pcie_pass_cmpl[]={ + { .uname = "DATA", + .udesc = "Passing data to be written (experimental)", + .ucode = 0x70ff000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FINAL_RD_WR", + .udesc = "Issuing final read or write of line (experimental)", + .ucode = 0x70ff000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_OWN", + .udesc = "Request Ownership (experimental)", + .ucode = 0x70ff000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Writing line (experimental)", + .ucode = 0x70ff000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_txn_req_by_cpu[]={ + { .uname = "CFG_READ_IOMMU0", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7100000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_IOMMU1", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7200000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART0", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7001000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART1", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7002000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART2", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7004000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART3", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7008000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART4", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7010000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART5", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7020000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART6", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7040000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_READ_PART7", + .udesc = "Core reading from Card's PCICFG space (experimental)", + .ucode = 0x7080000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_IOMMU0", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7100000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_IOMMU1", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7200000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART0", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7001000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART1", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7002000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART2", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7004000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART3", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7008000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART4", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7010000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART5", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7020000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART6", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7040000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CFG_WRITE_PART7", + .udesc = "Core writing to Card's PCICFG space (experimental)", + .ucode = 0x7080000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_IOMMU0", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7100000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_IOMMU1", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7200000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART0", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7001000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART1", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7002000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART2", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7004000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART3", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7008000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART4", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7010000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART5", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7020000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART6", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7040000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_READ_PART7", + .udesc = "Core reading from Card's IO space (experimental)", + .ucode = 0x7080000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_IOMMU0", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7100000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_IOMMU1", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7200000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART0", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7001000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART1", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7002000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART2", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7004000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART3", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7008000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART4", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7010000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART5", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7020000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART6", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7040000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IO_WRITE_PART7", + .udesc = "Core writing to Card's IO space (experimental)", + .ucode = 0x7080000002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU0", + .udesc = "Core reading from Card's MMIO space (experimental)", + .ucode = 0x7100000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU1", + .udesc = "Core reading from Card's MMIO space (experimental)", + .ucode = 0x7200000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART0", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7001000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART1", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7002000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART2", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7004000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART3", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7008000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART4", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7010000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART5", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7020000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART6", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7040000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART7", + .udesc = "Core reading from Card's MMIO space", + .ucode = 0x7080000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU0", + .udesc = "Core writing to Card's MMIO space (experimental)", + .ucode = 0x7100000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU1", + .udesc = "Core writing to Card's MMIO space (experimental)", + .ucode = 0x7200000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART0", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7001000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART1", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7002000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART2", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7004000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART3", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7008000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART4", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7010000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART5", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7020000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART6", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7040000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART7", + .udesc = "Core writing to Card's MMIO space", + .ucode = 0x7080000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU0", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7100000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU1", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7200000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART0", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7001000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART1", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7002000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART2", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7004000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART3", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7008000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART4", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7010000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART5", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7020000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART6", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7040000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART7", + .udesc = "Another card (different IIO stack) reading from this card. (experimental)", + .ucode = 0x7080000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU0", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7200000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART0", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7001000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART1", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7002000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART2", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7004000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART3", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7008000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART4", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7010000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART5", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7020000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART6", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7040000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART7", + .udesc = "Another card (different IIO stack) writing to this card. (experimental)", + .ucode = 0x7080000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_iio_txn_req_of_cpu[]={ + { .uname = "ATOMIC_IOMMU0", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7100000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_IOMMU1", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7200000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART0", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7001000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART1", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7002000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART2", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7004000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART3", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7008000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART4", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7010000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART5", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7020000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART6", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7040000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ATOMIC_PART7", + .udesc = "Atomic requests targeting DRAM (experimental)", + .ucode = 0x7080000001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_IOMMU0", + .udesc = "CmpD - device sending completion to CPU request (experimental)", + .ucode = 0x7100000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_IOMMU1", + .udesc = "CmpD - device sending completion to CPU request (experimental)", + .ucode = 0x7200000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART0", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7001000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART1", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7002000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART2", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7004000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART3", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7008000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART4", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7010000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART5", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7020000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART6", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7040000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMPD_PART7", + .udesc = "CmpD - device sending completion to CPU request", + .ucode = 0x7080000008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU0", + .udesc = "Card reading from DRAM (experimental)", + .ucode = 0x7100000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_IOMMU1", + .udesc = "Card reading from DRAM (experimental)", + .ucode = 0x7200000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART0", + .udesc = "Card reading from DRAM", + .ucode = 0x7001000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART1", + .udesc = "Card reading from DRAM", + .ucode = 0x7002000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART2", + .udesc = "Card reading from DRAM", + .ucode = 0x7004000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART3", + .udesc = "Card reading from DRAM", + .ucode = 0x7008000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART4", + .udesc = "Card reading from DRAM", + .ucode = 0x7010000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART5", + .udesc = "Card reading from DRAM", + .ucode = 0x7020000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART6", + .udesc = "Card reading from DRAM", + .ucode = 0x7040000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_READ_PART7", + .udesc = "Card reading from DRAM", + .ucode = 0x7080000000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU0", + .udesc = "Card writing to DRAM (experimental)", + .ucode = 0x7100000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_IOMMU1", + .udesc = "Card writing to DRAM (experimental)", + .ucode = 0x7200000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART0", + .udesc = "Card writing to DRAM", + .ucode = 0x7001000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART1", + .udesc = "Card writing to DRAM", + .ucode = 0x7002000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART2", + .udesc = "Card writing to DRAM", + .ucode = 0x7004000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART3", + .udesc = "Card writing to DRAM", + .ucode = 0x7008000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART4", + .udesc = "Card writing to DRAM", + .ucode = 0x7010000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART5", + .udesc = "Card writing to DRAM", + .ucode = 0x7020000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART6", + .udesc = "Card writing to DRAM", + .ucode = 0x7040000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM_WRITE_PART7", + .udesc = "Card writing to DRAM", + .ucode = 0x7080000000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_IOMMU0", + .udesc = "Messages (experimental)", + .ucode = 0x7100000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_IOMMU1", + .udesc = "Messages (experimental)", + .ucode = 0x7200000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART0", + .udesc = "Messages (experimental)", + .ucode = 0x7001000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART1", + .udesc = "Messages (experimental)", + .ucode = 0x7002000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART2", + .udesc = "Messages (experimental)", + .ucode = 0x7004000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART3", + .udesc = "Messages (experimental)", + .ucode = 0x7008000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART4", + .udesc = "Messages (experimental)", + .ucode = 0x7010000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART5", + .udesc = "Messages (experimental)", + .ucode = 0x7020000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART6", + .udesc = "Messages (experimental)", + .ucode = 0x7040000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG_PART7", + .udesc = "Messages (experimental)", + .ucode = 0x7080000004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU0", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7100000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_IOMMU1", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7200000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART0", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7001000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART1", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7002000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART2", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7004000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART3", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7008000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART4", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7010000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART5", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7020000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART6", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7040000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_READ_PART7", + .udesc = "Card reading from another Card (same or different stack) (experimental)", + .ucode = 0x7080000000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU0", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7100000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_IOMMU1", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7200000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART0", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7001000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART1", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7002000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART2", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7004000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART3", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7008000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART4", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7010000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART5", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7020000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART6", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7040000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PEER_WRITE_PART7", + .udesc = "Card writing to another Card (same or different stack) (experimental)", + .ucode = 0x7080000000200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_iio_pe[]={ + { .name = "UNC_IIO_BANDWIDTH_IN", + .desc = "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + .code = 0x0000, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x2ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_bandwidth_in), + .umasks = icx_unc_iio_bandwidth_in, + }, + { .name = "UNC_IIO_BANDWIDTH_OUT", + .desc = "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + .code = 0x0000, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x200ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_bandwidth_out), + .umasks = icx_unc_iio_bandwidth_out, + }, + { .name = "UNC_IIO_CLOCKTICKS", + .desc = "Clockticks of the integrated IO (IIO) traffic controller", + .code = 0x0001, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_IIO_CLOCKTICKS_FREERUN", + .desc = "Free running counter that increments for IIO clocktick", + .code = 0x0000, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x1ull, + }, + { .name = "UNC_IIO_COMP_BUF_OCCUPANCY", + .desc = "PCIe Completion Buffer Occupancy of completions with data", + .code = 0x00d5, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xcull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_comp_buf_occupancy), + .umasks = icx_unc_iio_comp_buf_occupancy, + }, + { .name = "UNC_IIO_DATA_REQ_BY_CPU", + .desc = "Data requested by the CPU", + .code = 0x00c0, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xcull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_data_req_by_cpu), + .umasks = icx_unc_iio_data_req_by_cpu, + }, + { .name = "UNC_IIO_DATA_REQ_OF_CPU", + .desc = "Four byte data request of the CPU", + .code = 0x0083, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_data_req_of_cpu), + .umasks = icx_unc_iio_data_req_of_cpu, + }, + { .name = "UNC_IIO_INBOUND_ARB_REQ", + .desc = "Incoming arbitration requests", + .code = 0x0086, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_inbound_arb_won), /* shared */ + .umasks = icx_unc_iio_inbound_arb_won, + }, + { .name = "UNC_IIO_INBOUND_ARB_WON", + .desc = "Incoming arbitration requests granted", + .code = 0x0087, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_inbound_arb_won), + .umasks = icx_unc_iio_inbound_arb_won, + }, + { .name = "UNC_IIO_IOMMU0", + .desc = "TBD", + .code = 0x0040, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_iommu0), + .umasks = icx_unc_iio_iommu0, + }, + { .name = "UNC_IIO_IOMMU1", + .desc = "TBD", + .code = 0x0041, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_iommu1), + .umasks = icx_unc_iio_iommu1, + }, + { .name = "UNC_IIO_IOMMU3", + .desc = "TBD", + .code = 0x0043, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_iommu3), + .umasks = icx_unc_iio_iommu3, + }, + { .name = "UNC_IIO_MASK_MATCH_AND", + .desc = "AND Mask/match for debug bus", + .code = 0x0002, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_mask_match_or), /* shared */ + .umasks = icx_unc_iio_mask_match_or, + }, + { .name = "UNC_IIO_MASK_MATCH_OR", + .desc = "OR Mask/match for debug bus", + .code = 0x0003, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_mask_match_or), + .umasks = icx_unc_iio_mask_match_or, + }, + { .name = "UNC_IIO_NOTHING", + .desc = "Counting disabled (experimental)", + .code = 0x0080, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU", + .desc = "Occupancy of outbound request queue", + .code = 0x00c5, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xcull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_num_oustanding_req_from_cpu), + .umasks = icx_unc_iio_num_oustanding_req_from_cpu, + }, + { .name = "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU", + .desc = "TBD", + .code = 0x0088, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xcull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_num_outstanding_req_of_cpu), + .umasks = icx_unc_iio_num_outstanding_req_of_cpu, + }, + { .name = "UNC_IIO_NUM_REQ_FROM_CPU", + .desc = "Number requests sent to PCIe from main die", + .code = 0x00c2, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_num_req_from_cpu), + .umasks = icx_unc_iio_num_req_from_cpu, + }, + { .name = "UNC_IIO_NUM_REQ_OF_CPU", + .desc = "Number requests PCIe makes of the main die", + .code = 0x0085, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_num_req_of_cpu), + .umasks = icx_unc_iio_num_req_of_cpu, + }, + { .name = "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT", + .desc = "Num requests sent by PCIe - by target", + .code = 0x008e, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_num_req_of_cpu_by_tgt), + .umasks = icx_unc_iio_num_req_of_cpu_by_tgt, + }, + { .name = "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + .desc = "ITC address map 1 (experimental)", + .code = 0x008f, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_IIO_OUTBOUND_CL_REQS_ISSUED", + .desc = "Outbound cacheline requests issued", + .code = 0x00d0, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_outbound_cl_reqs_issued), + .umasks = icx_unc_iio_outbound_cl_reqs_issued, + }, + { .name = "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED", + .desc = "Outbound TLP (transaction layer packet) requests issued", + .code = 0x00d1, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_outbound_tlp_reqs_issued), + .umasks = icx_unc_iio_outbound_tlp_reqs_issued, + }, + { .name = "UNC_IIO_PWT_OCCUPANCY", + .desc = "PWT occupancy (experimental)", + .code = 0x0042, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_IIO_REQ_FROM_PCIE_CL_CMPL", + .desc = "PCIe Request - cacheline complete", + .code = 0x0091, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_req_from_pcie_pass_cmpl), /* shared */ + .umasks = icx_unc_iio_req_from_pcie_pass_cmpl, + }, + { .name = "UNC_IIO_REQ_FROM_PCIE_CMPL", + .desc = "PCIe Request complete", + .code = 0x0092, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_req_from_pcie_cmpl), + .umasks = icx_unc_iio_req_from_pcie_cmpl, + }, + { .name = "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL", + .desc = "PCIe Request - pass complete", + .code = 0x0090, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_req_from_pcie_pass_cmpl), + .umasks = icx_unc_iio_req_from_pcie_pass_cmpl, + }, + { .name = "UNC_IIO_SYMBOL_TIMES", + .desc = "Symbol Times on Link (experimental)", + .code = 0x0082, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_IIO_TXN_REQ_BY_CPU", + .desc = "Number Transactions requested by the CPU", + .code = 0x00c1, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_txn_req_by_cpu), + .umasks = icx_unc_iio_txn_req_by_cpu, + }, + { .name = "UNC_IIO_TXN_REQ_OF_CPU", + .desc = "Number Transactions requested of the CPU", + .code = 0x0084, + .modmsk = ICX_UNC_IIO_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_iio_txn_req_of_cpu), + .umasks = icx_unc_iio_txn_req_of_cpu, + }, +}; +/* 31 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_imc_events.h b/src/libpfm4/lib/events/intel_icx_unc_imc_events.h new file mode 100644 index 000000000..a3390cf3d --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_imc_events.h @@ -0,0 +1,1244 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_imc (IcelakeX Uncore IMC) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_m_act_count[]={ + { .uname = "ALL", + .udesc = "All Activates", + .ucode = 0x0b00ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "BYP", + .udesc = "Activate due to Bypass (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_cas_count[]={ + { .uname = "ALL", + .udesc = "TBD", + .ucode = 0x3f00ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "RD", + .udesc = "TBD", + .ucode = 0x0f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_PRE_REG", + .udesc = "DRAM RD_CAS commands w/auto-pre (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_PRE_UNDERFILL", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_REG", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_UNDERFILL", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "TBD", + .ucode = 0x3000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_NONPRE", + .udesc = "DRAM WR_CAS commands w/o auto-pre (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_PRE", + .udesc = "DRAM WR_CAS commands w/ auto-pre (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_dram_refresh[]={ + { .uname = "HIGH", + .udesc = "TBD", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OPPORTUNISTIC", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PANIC", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pcls[]={ + { .uname = "RD", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TOTAL", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pmm_cmd1[]={ + { .uname = "ALL", + .udesc = "All", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "MISC", + .udesc = "Misc Commands (error, flow ACKs) (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISC_GNT", + .udesc = "Misc GNTs (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD", + .udesc = "Reads - RPQ", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RPQ_GNTS", + .udesc = "RPQ GNTs (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UFILL_RD", + .udesc = "Underfill reads", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WPQ_GNTS", + .udesc = "Underfill GNTs (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Writes", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pmm_cmd2[]={ + { .uname = "NODATA_EXP", + .udesc = "Expected No data packet (ERID matched NDP encoding) (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NODATA_UNEXP", + .udesc = "Unexpected No data packet (ERID matched a Read, but data was a NDP) (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OPP_RD", + .udesc = "Opportunistic Reads (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_ECC_ERROR", + .udesc = "ECC Errors (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_ERID_ERROR", + .udesc = "ERID detectable parity error (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_ERID_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQS_SLOT0", + .udesc = "Read Requests - Slot 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQS_SLOT1", + .udesc = "Read Requests - Slot 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pmm_rpq_occupancy[]={ + { .uname = "ALL", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "GNT_WAIT", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_GNT", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pmm_wpq_occupancy[]={ + { .uname = "ALL", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CAS", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PWR", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_power_cke_cycles[]={ + { .uname = "LOW_0", + .udesc = "DIMM ID (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOW_1", + .udesc = "DIMM ID (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOW_2", + .udesc = "DIMM ID (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOW_3", + .udesc = "DIMM ID (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_power_throttle_cycles[]={ + { .uname = "SLOT0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT1", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_pre_count[]={ + { .uname = "ALL", + .udesc = "TBD", + .ucode = 0x1c00ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "PAGE_MISS", + .udesc = "Precharge due to page miss (experimental)", + .ucode = 0x0c00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PGT", + .udesc = "Precharge due to page table", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD", + .udesc = "Precharge due to read", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "Precharge due to write", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_rpq_inserts[]={ + { .uname = "PCH0", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PCH1", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_accesses[]={ + { .uname = "ACCEPTS", + .udesc = "Scoreboard Accesses Accepted (experimental)", + .ucode = 0x0500ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMRD_CMPS", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMWR_CMPS", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_RD_CMPS", + .udesc = "Write Accepts (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_WR_CMPS", + .udesc = "Write Rejects (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMRD_CMPS", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMWR_CMPS", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD_CMPS", + .udesc = "FM read completions (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_WR_CMPS", + .udesc = "FM write completions (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_ACCEPTS", + .udesc = "Read Accepts (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_REJECTS", + .udesc = "Read Rejects (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REJECTS", + .udesc = "Scoreboard Accesses Rejected (experimental)", + .ucode = 0x0a00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_ACCEPTS", + .udesc = "NM read completions (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_REJECTS", + .udesc = "NM write completions (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_canary[]={ + { .uname = "ALLOC", + .udesc = "Alloc (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DEALLOC", + .udesc = "Dealloc (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMRD_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMTGRWR_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMWR_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_RD_STARVED", + .udesc = "Near Mem Write Starved (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_TGR_WR_STARVED", + .udesc = "Far Mem Write Starved (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_WR_STARVED", + .udesc = "Far Mem Read Starved (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMRD_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMWR_STARVED", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD_STARVED", + .udesc = "Valid (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_WR_STARVED", + .udesc = "Near Mem Read Starved (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VLD", + .udesc = "Reject (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_inserts[]={ + { .uname = "BLOCK_RDS", + .udesc = "Block region reads (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BLOCK_WRS", + .udesc = "Block region writes (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_RDS", + .udesc = "Persistent Mem reads (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_WRS", + .udesc = "Persistent Mem writes (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDS", + .udesc = "Reads (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRS", + .udesc = "Writes (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_occupancy[]={ + { .uname = "BLOCK_RDS", + .udesc = "Block region reads (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BLOCK_WRS", + .udesc = "Block region writes (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_RDS", + .udesc = "Persistent Mem reads (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_WRS", + .udesc = "Persistent Mem writes (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDS", + .udesc = "Reads (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_pref_inserts[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "DDR", + .udesc = "DDR4 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM", + .udesc = "Persistent Mem (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_pref_occupancy[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "DDR", + .udesc = "DDR4 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMEM", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM", + .udesc = "Persistent Mem (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_reject[]={ + { .uname = "CANARY", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DDR_EARLY_CMP", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_ADDR_CNFLT", + .udesc = "FM requests rejected due to full address conflict (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_SET_CNFLT", + .udesc = "NM requests rejected due to set conflict (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PATROL_SET_CNFLT", + .udesc = "Patrol requests rejected due to set conflict (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_strv_dealloc[]={ + { .uname = "FMRD", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMTGR", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_RD", + .udesc = "Far Mem Read - Set (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_TGR", + .udesc = "Near Mem Read - Clear (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_WR", + .udesc = "Far Mem Write - Set (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMRD", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD", + .udesc = "Near Mem Read - Set (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_WR", + .udesc = "Near Mem Write - Set (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_strv_occ[]={ + { .uname = "FMRD", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMTGR", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_RD", + .udesc = "Far Mem Read (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_TGR", + .udesc = "Near Mem Read - Clear (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FM_WR", + .udesc = "Far Mem Write (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMRD", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NMWR", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD", + .udesc = "Near Mem Read (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_WR", + .udesc = "Near Mem Write (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_sb_tagged[]={ + { .uname = "DDR4_CMP", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NEW", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OCC", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM0_CMP", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM1_CMP", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM2_CMP", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_HIT", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD_MISS", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_tagchk[]={ + { .uname = "HIT", + .udesc = "Hit in Near Memory Cache", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS_CLEAN", + .udesc = "Miss, no data in this line", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS_DIRTY", + .udesc = "Miss, existing data may be evicted to Far Memory", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD_HIT", + .udesc = "Read Hit in Near Memory Cache", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_WR_HIT", + .udesc = "Write Hit in Near Memory Cache", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_wpq_inserts[]={ + { .uname = "PCH0", + .udesc = "TBD", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PCH1", + .udesc = "TBD", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m_wpq_write_hit[]={ + { .uname = "PCH0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PCH1", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_imc_pe[]={ + { .name = "UNC_M_ACT_COUNT", + .desc = "DRAM Activate Count", + .code = 0x0001, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_act_count), + .umasks = icx_unc_m_act_count, + }, + { .name = "UNC_M_CAS_COUNT", + .desc = "All DRAM read CAS commands issued (including underfills)", + .code = 0x0004, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_cas_count), + .umasks = icx_unc_m_cas_count, + }, + { .name = "UNC_M_CLOCKTICKS", + .desc = "DRAM Clockticks", + .code = 0x0000, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_CLOCKTICKS_FREERUN", + .desc = "Free running counter that increments for the Memory Controller (experimental)", + .code = 0x0000, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0x10ull, + }, + { .name = "UNC_M_DRAM_PRE_ALL", + .desc = "DRAM Precharge All Commands (experimental)", + .code = 0x0044, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_DRAM_REFRESH", + .desc = "Number of DRAM Refreshes Issued", + .code = 0x0045, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_dram_refresh), + .umasks = icx_unc_m_dram_refresh, + }, + { .name = "UNC_M_HCLOCKTICKS", + .desc = "Half clockticks for IMC", + .code = 0x0000, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0x1ull, + }, + { .name = "UNC_M_PARITY_ERRORS", + .desc = "UNC_M_PARITY_ERRORS (experimental)", + .code = 0x002c, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PCLS", + .desc = "UNC_M_PCLS.RD", + .code = 0x00a0, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pcls), + .umasks = icx_unc_m_pcls, + }, + { .name = "UNC_M_PMM_CMD1", + .desc = "PMM Commands", + .code = 0x00ea, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pmm_cmd1), + .umasks = icx_unc_m_pmm_cmd1, + }, + { .name = "UNC_M_PMM_CMD2", + .desc = "PMM Commands - Part 2", + .code = 0x00eb, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pmm_cmd2), + .umasks = icx_unc_m_pmm_cmd2, + }, + { .name = "UNC_M_PMM_RPQ_CYCLES_FULL", + .desc = "PMM Read Queue Cycles Full (experimental)", + .code = 0x00e2, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_RPQ_CYCLES_NE", + .desc = "PMM Read Queue Cycles Not Empty (experimental)", + .code = 0x00e1, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_RPQ_INSERTS", + .desc = "PMM Read Queue Inserts", + .code = 0x00e3, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_RPQ_OCCUPANCY", + .desc = "PMM Read Pending Queue Occupancy", + .code = 0x00e0, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pmm_rpq_occupancy), + .umasks = icx_unc_m_pmm_rpq_occupancy, + }, + { .name = "UNC_M_PMM_WPQ_CYCLES_FULL", + .desc = "PMM Write Queue Cycles Full (experimental)", + .code = 0x00e6, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_WPQ_CYCLES_NE", + .desc = "PMM Write Queue Cycles Not Empty (experimental)", + .code = 0x00e5, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_WPQ_FLUSH", + .desc = "UNC_M_PMM_WPQ_FLUSH (experimental)", + .code = 0x00e8, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_WPQ_FLUSH_CYC", + .desc = "UNC_M_PMM_WPQ_FLUSH_CYC (experimental)", + .code = 0x00e9, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_WPQ_INSERTS", + .desc = "PMM Write Queue Inserts", + .code = 0x00e7, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_PMM_WPQ_OCCUPANCY", + .desc = "PMM Write Pending Queue Occupancy", + .code = 0x00e4, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pmm_wpq_occupancy), + .umasks = icx_unc_m_pmm_wpq_occupancy, + }, + { .name = "UNC_M_POWER_CHANNEL_PPD", + .desc = "Channel PPD Cycles (experimental)", + .code = 0x0085, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_POWER_CKE_CYCLES", + .desc = "CKE_ON_CYCLES by Rank", + .code = 0x0047, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_power_cke_cycles), + .umasks = icx_unc_m_power_cke_cycles, + }, + { .name = "UNC_M_POWER_CRIT_THROTTLE_CYCLES", + .desc = "Throttle Cycles for Rank 0", + .code = 0x0086, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_power_throttle_cycles), /* shared */ + .umasks = icx_unc_m_power_throttle_cycles, + }, + { .name = "UNC_M_POWER_SELF_REFRESH", + .desc = "Clock-Enabled Self-Refresh (experimental)", + .code = 0x0043, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_POWER_THROTTLE_CYCLES", + .desc = "Throttle Cycles for Rank 0", + .code = 0x0046, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_power_throttle_cycles), + .umasks = icx_unc_m_power_throttle_cycles, + }, + { .name = "UNC_M_PRE_COUNT", + .desc = "DRAM Precharge commands.", + .code = 0x0002, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_pre_count), + .umasks = icx_unc_m_pre_count, + }, + { .name = "UNC_M_RDB_FULL", + .desc = "Read Data Buffer Full (experimental)", + .code = 0x0019, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RDB_INSERTS", + .desc = "Read Data Buffer Inserts (experimental)", + .code = 0x0017, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RDB_NOT_EMPTY", + .desc = "Read Data Buffer Not Empty (experimental)", + .code = 0x0018, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RDB_OCCUPANCY", + .desc = "Read Data Buffer Occupancy (experimental)", + .code = 0x001a, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RPQ_CYCLES_FULL_PCH0", + .desc = "Read Pending Queue Full Cycles (experimental)", + .code = 0x0012, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RPQ_CYCLES_FULL_PCH1", + .desc = "Read Pending Queue Full Cycles (experimental)", + .code = 0x0015, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RPQ_CYCLES_NE", + .desc = "Read Pending Queue Not Empty", + .code = 0x0011, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_rpq_inserts), /* shared */ + .umasks = icx_unc_m_rpq_inserts, + }, + { .name = "UNC_M_RPQ_INSERTS", + .desc = "Read Pending Queue Allocations", + .code = 0x0010, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_rpq_inserts), + .umasks = icx_unc_m_rpq_inserts, + }, + { .name = "UNC_M_RPQ_OCCUPANCY_PCH0", + .desc = "Read Pending Queue Occupancy", + .code = 0x0080, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_RPQ_OCCUPANCY_PCH1", + .desc = "Read Pending Queue Occupancy", + .code = 0x0081, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_SB_ACCESSES", + .desc = "Scoreboard Accesses", + .code = 0x00d2, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_accesses), + .umasks = icx_unc_m_sb_accesses, + }, + { .name = "UNC_M_SB_CANARY", + .desc = "TBD", + .code = 0x00d9, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_canary), + .umasks = icx_unc_m_sb_canary, + }, + { .name = "UNC_M_SB_CYCLES_FULL", + .desc = "Scoreboard Cycles Full (experimental)", + .code = 0x00d1, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_SB_CYCLES_NE", + .desc = "Scoreboard Cycles Not-Empty (experimental)", + .code = 0x00d0, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_SB_INSERTS", + .desc = "Scoreboard Inserts", + .code = 0x00d6, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_inserts), + .umasks = icx_unc_m_sb_inserts, + }, + { .name = "UNC_M_SB_OCCUPANCY", + .desc = "Scoreboard Occupancy", + .code = 0x00d5, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_occupancy), + .umasks = icx_unc_m_sb_occupancy, + }, + { .name = "UNC_M_SB_PREF_INSERTS", + .desc = "Scoreboard Prefetch Inserts", + .code = 0x00da, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_pref_inserts), + .umasks = icx_unc_m_sb_pref_inserts, + }, + { .name = "UNC_M_SB_PREF_OCCUPANCY", + .desc = "Scoreboard Prefetch Occupancy", + .code = 0x00db, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_pref_occupancy), + .umasks = icx_unc_m_sb_pref_occupancy, + }, + { .name = "UNC_M_SB_REJECT", + .desc = "Number of Scoreboard Requests Rejected", + .code = 0x00d4, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_reject), + .umasks = icx_unc_m_sb_reject, + }, + { .name = "UNC_M_SB_STRV_ALLOC", + .desc = "This event is deprecated. Refer to new event UNC_M_SB_STRV_ALLOC.NM_RD", + .code = 0x00d7, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_strv_dealloc), /* shared */ + .umasks = icx_unc_m_sb_strv_dealloc, + }, + { .name = "UNC_M_SB_STRV_DEALLOC", + .desc = "This event is deprecated. Refer to new event UNC_M_SB_STRV_DEALLOC.NM_RD", + .code = 0x00de, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_strv_dealloc), + .umasks = icx_unc_m_sb_strv_dealloc, + }, + { .name = "UNC_M_SB_STRV_OCC", + .desc = "This event is deprecated. Refer to new event UNC_M_SB_STRV_OCC.NM_RD", + .code = 0x00d8, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_strv_occ), + .umasks = icx_unc_m_sb_strv_occ, + }, + { .name = "UNC_M_SB_TAGGED", + .desc = "UNC_M_SB_TAGGED.NEW", + .code = 0x00dd, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_sb_tagged), + .umasks = icx_unc_m_sb_tagged, + }, + { .name = "UNC_M_TAGCHK", + .desc = "2LM Tag Check", + .code = 0x00d3, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_tagchk), + .umasks = icx_unc_m_tagchk, + }, + { .name = "UNC_M_WPQ_CYCLES_FULL_PCH0", + .desc = "Write Pending Queue Full Cycles (experimental)", + .code = 0x0022, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_WPQ_CYCLES_FULL_PCH1", + .desc = "Write Pending Queue Full Cycles (experimental)", + .code = 0x0016, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_WPQ_CYCLES_NE", + .desc = "Write Pending Queue Not Empty", + .code = 0x0021, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_wpq_inserts), /* shared */ + .umasks = icx_unc_m_wpq_inserts, + }, + { .name = "UNC_M_WPQ_INSERTS", + .desc = "Write Pending Queue Allocations", + .code = 0x0020, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_wpq_inserts), + .umasks = icx_unc_m_wpq_inserts, + }, + { .name = "UNC_M_WPQ_OCCUPANCY_PCH0", + .desc = "Write Pending Queue Occupancy", + .code = 0x0082, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_WPQ_OCCUPANCY_PCH1", + .desc = "Write Pending Queue Occupancy", + .code = 0x0083, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M_WPQ_READ_HIT", + .desc = "Write Pending Queue CAM Match", + .code = 0x0023, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_wpq_write_hit), /* shared */ + .umasks = icx_unc_m_wpq_write_hit, + }, + { .name = "UNC_M_WPQ_WRITE_HIT", + .desc = "Write Pending Queue CAM Match", + .code = 0x0024, + .modmsk = ICX_UNC_IMC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m_wpq_write_hit), + .umasks = icx_unc_m_wpq_write_hit, + }, +}; +/* 59 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_irp_events.h b/src/libpfm4/lib/events/intel_icx_unc_irp_events.h new file mode 100644 index 000000000..cb508373c --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_irp_events.h @@ -0,0 +1,521 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_irp (IcelakeX Uncore IRP) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ + +static const intel_x86_umask_t icx_unc_i_cache_total_occupancy[]={ + { .uname = "ANY", + .udesc = "Any Source (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "IV_Q", + .udesc = "Snoops (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MEM", + .udesc = "TBD", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_coherent_ops[]={ + { .uname = "CLFLUSH", + .udesc = "CLFlush (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PCITOM", + .udesc = "TBD", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RFO", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WBMTOI", + .udesc = "WbMtoI", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_irp_all[]={ + { .uname = "EVICTS", + .udesc = "All Inserts Outbound (BL, AK, Snoops) (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INBOUND_INSERTS", + .udesc = "All Inserts Inbound (p2p + faf + cset)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OUTBOUND_INSERTS", + .udesc = "All Inserts Outbound (BL, AK, Snoops) (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_misc0[]={ + { .uname = "2ND_ATOMIC_INSERT", + .udesc = "Cache Inserts of Atomic Transactions as Secondary (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "2ND_RD_INSERT", + .udesc = "Cache Inserts of Read Transactions as Secondary (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "2ND_WR_INSERT", + .udesc = "Cache Inserts of Write Transactions as Secondary (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAST_REJ", + .udesc = "Fastpath Rejects (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAST_REQ", + .udesc = "Fastpath Requests (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FAST_XFER", + .udesc = "Fastpath Transfers From Primary to Secondary (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_ACK_HINT", + .udesc = "Prefetch Ack Hints From Primary to Secondary (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOWPATH_FWPF_NO_PRF", + .udesc = "Slow path fwpf didn't find prefetch (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_misc1[]={ + { .uname = "LOST_FWD", + .udesc = "Lost Forward", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SEC_RCVD_INVLD", + .udesc = "Received Invalid (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SEC_RCVD_VLD", + .udesc = "Received Valid (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOW_E", + .udesc = "Slow Transfer of E Line (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOW_I", + .udesc = "Slow Transfer of I Line (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOW_M", + .udesc = "Slow Transfer of M Line (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOW_S", + .udesc = "Slow Transfer of S Line (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_p2p_transactions[]={ + { .uname = "CMPL", + .udesc = "P2P completions (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC", + .udesc = "match if local only (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOC_AND_TGT_MATCH", + .udesc = "match if local and target matches (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSG", + .udesc = "P2P Message (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RD", + .udesc = "P2P reads (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REM", + .udesc = "Match if remote only (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REM_AND_TGT_MATCH", + .udesc = "match if remote and target matches (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR", + .udesc = "P2P Writes (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_snoop_resp[]={ + { .uname = "ALL_HIT", + .udesc = "TBD (experimental)", + .ucode = 0x7e00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_HIT_ES", + .udesc = "TBD (experimental)", + .ucode = 0x7400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_HIT_I", + .udesc = "TBD (experimental)", + .ucode = 0x7200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_HIT_M", + .udesc = "TBD", + .ucode = 0x7800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_MISS", + .udesc = "TBD (experimental)", + .ucode = 0x7100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HIT_ES", + .udesc = "Hit E or S (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HIT_I", + .udesc = "Hit I (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HIT_M", + .udesc = "Hit M (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MISS", + .udesc = "Miss (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNPCODE", + .udesc = "SnpCode (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNPDATA", + .udesc = "SnpData (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNPINV", + .udesc = "SnpInv (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_i_transactions[]={ + { .uname = "ATOMIC", + .udesc = "Atomic (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ORDERINGQ", + .udesc = "Select Source (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "OTHER", + .udesc = "Other (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRITES", + .udesc = "Writes (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WR_PREF", + .udesc = "TBD", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_irp_pe[]={ + { .name = "UNC_I_CACHE_TOTAL_OCCUPANCY", + .desc = "Total IRP occupancy of inbound read and write requests to coherent memory.", + .code = 0x000f, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_cache_total_occupancy), + .umasks = icx_unc_i_cache_total_occupancy, + }, + { .name = "UNC_I_CLOCKTICKS", + .desc = "Clockticks of the IO coherency tracker (IRP)", + .code = 0x0001, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_COHERENT_OPS", + .desc = "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + .code = 0x0010, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_coherent_ops), + .umasks = icx_unc_i_coherent_ops, + }, + { .name = "UNC_I_FAF_FULL", + .desc = "FAF RF full", + .code = 0x0017, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_FAF_INSERTS", + .desc = "Inbound read requests received by the IRP and inserted into the FAF queue.", + .code = 0x0018, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_FAF_OCCUPANCY", + .desc = "Occupancy of the IRP FAF queue.", + .code = 0x0019, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_FAF_TRANSACTIONS", + .desc = "FAF allocation -- sent to ADQ", + .code = 0x0016, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_IRP_ALL", + .desc = "TBD", + .code = 0x0020, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_irp_all), + .umasks = icx_unc_i_irp_all, + }, + { .name = "UNC_I_MISC0", + .desc = "Counts Timeouts - Set 0", + .code = 0x001e, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_misc0), + .umasks = icx_unc_i_misc0, + }, + { .name = "UNC_I_MISC1", + .desc = "Misc Events - Set 1", + .code = 0x001f, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_misc1), + .umasks = icx_unc_i_misc1, + }, + { .name = "UNC_I_P2P_INSERTS", + .desc = "P2P Requests (experimental)", + .code = 0x0014, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_P2P_OCCUPANCY", + .desc = "P2P Occupancy (experimental)", + .code = 0x0015, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_P2P_TRANSACTIONS", + .desc = "P2P Transactions", + .code = 0x0013, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_p2p_transactions), + .umasks = icx_unc_i_p2p_transactions, + }, + { .name = "UNC_I_SNOOP_RESP", + .desc = "Responses to snoops of any type that hit M line in the IIO cache", + .code = 0x0012, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_snoop_resp), + .umasks = icx_unc_i_snoop_resp, + }, + { .name = "UNC_I_TRANSACTIONS", + .desc = "Inbound write (fast path) requests received by the IRP.", + .code = 0x0011, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_i_transactions), + .umasks = icx_unc_i_transactions, + }, + { .name = "UNC_I_TxC_AK_INSERTS", + .desc = "AK Egress Allocations (experimental)", + .code = 0x000b, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_DRS_CYCLES_FULL", + .desc = "BL DRS Egress Cycles Full (experimental)", + .code = 0x0005, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_DRS_INSERTS", + .desc = "BL DRS Egress Inserts (experimental)", + .code = 0x0002, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_DRS_OCCUPANCY", + .desc = "BL DRS Egress Occupancy (experimental)", + .code = 0x0008, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCB_CYCLES_FULL", + .desc = "BL NCB Egress Cycles Full (experimental)", + .code = 0x0006, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCB_INSERTS", + .desc = "BL NCB Egress Inserts (experimental)", + .code = 0x0003, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCB_OCCUPANCY", + .desc = "BL NCB Egress Occupancy (experimental)", + .code = 0x0009, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCS_CYCLES_FULL", + .desc = "BL NCS Egress Cycles Full (experimental)", + .code = 0x0007, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCS_INSERTS", + .desc = "BL NCS Egress Inserts (experimental)", + .code = 0x0004, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxC_BL_NCS_OCCUPANCY", + .desc = "BL NCS Egress Occupancy (experimental)", + .code = 0x000a, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + .desc = "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES (experimental)", + .code = 0x001c, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + .desc = "No AD0 Egress Credits Stalls (experimental)", + .code = 0x001a, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + .desc = "No AD1 Egress Credits Stalls (experimental)", + .code = 0x001b, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + .desc = "No BL Egress Credit Stalls (experimental)", + .code = 0x001d, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxS_DATA_INSERTS_NCB", + .desc = "Outbound Read Requests (experimental)", + .code = 0x000d, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxS_DATA_INSERTS_NCS", + .desc = "Outbound Read Requests (experimental)", + .code = 0x000e, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_I_TxS_REQUEST_OCCUPANCY", + .desc = "Outbound Request Queue Occupancy (experimental)", + .code = 0x000c, + .modmsk = ICX_UNC_IRP_ATTRS, + .cntmsk = 0x3ull, + }, +}; +/* 32 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_m2m_events.h b/src/libpfm4/lib/events/intel_icx_unc_m2m_events.h new file mode 100644 index 000000000..8c93e8b94 --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_m2m_events.h @@ -0,0 +1,3910 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_m2m (IcelakeX Uncore M2M) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_m2m_ag0_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag0_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag0_bl_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag0_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag1_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag1_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag1_bl_crd_acquired0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ag1_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_bypass_m2m_ingress[]={ + { .uname = "NOT_TAKEN", + .udesc = "Not Taken (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TAKEN", + .udesc = "Taken (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_directory_lookup[]={ + { .uname = "ANY", + .udesc = "Found in any state", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_A", + .udesc = "Found in A state", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_I", + .udesc = "Found in I state", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STATE_S", + .udesc = "Found in S state", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_directory_miss[]={ + { .uname = "CLEAN_A", + .udesc = "On NonDirty Line in A State (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CLEAN_I", + .udesc = "On NonDirty Line in I State (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CLEAN_P", + .udesc = "On NonDirty Line in L State (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CLEAN_S", + .udesc = "On NonDirty Line in S State (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRTY_A", + .udesc = "On Dirty Line in A State (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRTY_I", + .udesc = "On Dirty Line in I State (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRTY_P", + .udesc = "On Dirty Line in L State (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DIRTY_S", + .udesc = "On Dirty Line in S State (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_directory_update[]={ + { .uname = "ANY", + .udesc = "From/to any state. Note: event counts are incorrect in 2LM mode.", + .ucode = 0x0100ull, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_distress_asserted[]={ + { .uname = "DPT_LOCAL", + .udesc = "DPT Local (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_NONLOCAL", + .udesc = "DPT Remote (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_IV", + .udesc = "DPT Stalled - IV (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_NOCRD", + .udesc = "DPT Stalled - No Credit (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HORZ", + .udesc = "Horizontal (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_LOCAL", + .udesc = "PMM Local (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_NONLOCAL", + .udesc = "PMM Remote (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VERT", + .udesc = "Vertical (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_egress_ordering[]={ + { .uname = "IV_SNOOPGO_DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_SNOOPGO_UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_horz_ring_akc_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_horz_ring_bl_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_horz_ring_iv_in_use[]={ + { .uname = "LEFT", + .udesc = "Left (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT", + .udesc = "Right (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_imc_reads[]={ + { .uname = "ALL", + .udesc = "All, regardless of priority. - All Channels (experimental)", + .ucode = 0x700000400ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CH0_ALL", + .udesc = "All, regardless of priority. - Ch0 (experimental)", + .ucode = 0x100000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_FROM_TGR", + .udesc = "From TGR - Ch0 (experimental)", + .ucode = 0x100004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_ISOCH", + .udesc = "Critical Priority - Ch0 (experimental)", + .ucode = 0x100000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_NORMAL", + .udesc = "Normal Priority - Ch0 (experimental)", + .ucode = 0x100000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - Ch0 (experimental)", + .ucode = 0x100001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_DDR_AS_MEM", + .udesc = "DDR - Ch0 (experimental)", + .ucode = 0x100000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_PMM", + .udesc = "PMM - Ch0 (experimental)", + .ucode = 0x100002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_ALL", + .udesc = "All, regardless of priority. - Ch1 (experimental)", + .ucode = 0x200000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_FROM_TGR", + .udesc = "From TGR - Ch1 (experimental)", + .ucode = 0x200004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_ISOCH", + .udesc = "Critical Priority - Ch1 (experimental)", + .ucode = 0x200000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_NORMAL", + .udesc = "Normal Priority - Ch1 (experimental)", + .ucode = 0x200000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - Ch1 (experimental)", + .ucode = 0x200001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_DDR_AS_MEM", + .udesc = "DDR - Ch1 (experimental)", + .ucode = 0x200000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_PMM", + .udesc = "PMM - Ch1 (experimental)", + .ucode = 0x200002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_FROM_TGR", + .udesc = "From TGR - Ch2 (experimental)", + .ucode = 0x400004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FROM_TGR", + .udesc = "From TGR - All Channels (experimental)", + .ucode = 0x700004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ISOCH", + .udesc = "Critical Priority - All Channels (experimental)", + .ucode = 0x700000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NORMAL", + .udesc = "Normal Priority - All Channels (experimental)", + .ucode = 0x700000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - All Channels (experimental)", + .ucode = 0x700001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_DDR_AS_MEM", + .udesc = "DDR - All Channels (experimental)", + .ucode = 0x700000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_PMM", + .udesc = "PMM - All Channels", + .ucode = 0x700002000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_imc_writes[]={ + { .uname = "ALL", + .udesc = "All Writes - All Channels (experimental)", + .ucode = 0x1c00001000ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CH0_ALL", + .udesc = "All Writes - Ch0 (experimental)", + .ucode = 0x400001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_FROM_TGR", + .udesc = "From TGR - Ch0 (experimental)", + .ucode = 0x500000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_FULL", + .udesc = "Full Line Non-ISOCH - Ch0 (experimental)", + .ucode = 0x400000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_FULL_ISOCH", + .udesc = "ISOCH Full Line - Ch0 (experimental)", + .ucode = 0x400000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_NI", + .udesc = "Non-Inclusive - Ch0 (experimental)", + .ucode = 0x600000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_NI_MISS", + .udesc = "Non-Inclusive Miss - Ch0 (experimental)", + .ucode = 0x2000000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_PARTIAL", + .udesc = "Partial Non-ISOCH - Ch0 (experimental)", + .ucode = 0x400000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_PARTIAL_ISOCH", + .udesc = "ISOCH Partial - Ch0 (experimental)", + .ucode = 0x400000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - Ch0 (experimental)", + .ucode = 0x400004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_DDR_AS_MEM", + .udesc = "DDR - Ch0 (experimental)", + .ucode = 0x400002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_TO_PMM", + .udesc = "PMM - Ch0 (experimental)", + .ucode = 0x400008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_ALL", + .udesc = "All Writes - Ch1 (experimental)", + .ucode = 0x800001000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_FROM_TGR", + .udesc = "From TGR - Ch1 (experimental)", + .ucode = 0x900000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_FULL", + .udesc = "Full Line Non-ISOCH - Ch1 (experimental)", + .ucode = 0x800000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_FULL_ISOCH", + .udesc = "ISOCH Full Line - Ch1 (experimental)", + .ucode = 0x800000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_NI", + .udesc = "Non-Inclusive - Ch1 (experimental)", + .ucode = 0xa00000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_NI_MISS", + .udesc = "Non-Inclusive Miss - Ch1 (experimental)", + .ucode = 0xc00000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_PARTIAL", + .udesc = "Partial Non-ISOCH - Ch1 (experimental)", + .ucode = 0x800000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_PARTIAL_ISOCH", + .udesc = "ISOCH Partial - Ch1 (experimental)", + .ucode = 0x800000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - Ch1 (experimental)", + .ucode = 0x800004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_DDR_AS_MEM", + .udesc = "DDR - Ch1 (experimental)", + .ucode = 0x800002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_TO_PMM", + .udesc = "PMM - Ch1 (experimental)", + .ucode = 0x800008000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FROM_TGR", + .udesc = "From TGR - All Channels (experimental)", + .ucode = 0x1d00000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FULL", + .udesc = "Full Line Non-ISOCH - All Channels (experimental)", + .ucode = 0x1c00000100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FULL_ISOCH", + .udesc = "ISOCH Full Line - All Channels (experimental)", + .ucode = 0x1c00000400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NI", + .udesc = "Non-Inclusive - All Channels (experimental)", + .ucode = 0x1e00000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NI_MISS", + .udesc = "Non-Inclusive Miss - All Channels (experimental)", + .ucode = 0x1c00000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL", + .udesc = "Partial Non-ISOCH - All Channels (experimental)", + .ucode = 0x1c00000200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARTIAL_ISOCH", + .udesc = "ISOCH Partial - All Channels (experimental)", + .ucode = 0x1c00000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_DDR_AS_CACHE", + .udesc = "DDR, acting as Cache - All Channels (experimental)", + .ucode = 0x1c00004000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_DDR_AS_MEM", + .udesc = "DDR - All Channels (experimental)", + .ucode = 0x1c00002000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TO_PMM", + .udesc = "PMM - All Channels", + .ucode = 0x1c00008000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_misc_external[]={ + { .uname = "MBE_INST0", + .udesc = "Number of cycles MBE is high for MS2IDI0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MBE_INST1", + .udesc = "Number of cycles MBE is high for MS2IDI1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_pkt_match[]={ + { .uname = "MC", + .udesc = "MC Match (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MESH", + .udesc = "Mesh Match (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_cycles_ne[]={ + { .uname = "ALLCH", + .udesc = "All Channels (experimental)", + .ucode = 0x0700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_deallocs[]={ + { .uname = "CH0_HITA0_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_HITA1_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_MISS_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_RSP_PDRESET", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_HITA0_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_HITA1_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_MISS_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_RSP_PDRESET", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_HITA0_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_HITA1_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_MISS_INVAL", + .udesc = "TBD (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_RSP_PDRESET", + .udesc = "TBD (experimental)", + .ucode = 0x800000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_demand_merge[]={ + { .uname = "CH0_XPTUPI", + .udesc = "XPT & UPI- Ch 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_XPTUPI", + .udesc = "XPT & UPI - Ch 1 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_XPTUPI", + .udesc = "XPT & UPI- Ch 2 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XPTUPI_ALLCH", + .udesc = "XPT & UPI- All Channels (experimental)", + .ucode = 0x1500ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_demand_no_merge[]={ + { .uname = "CH0_XPTUPI", + .udesc = "XPT & UPI - Ch 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_XPTUPI", + .udesc = "XPT & UPI - Ch 1 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_XPTUPI", + .udesc = "XPT & UPI - Ch 2 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XPTUPI_ALLCH", + .udesc = "XPT & UPI - All Channels (experimental)", + .ucode = 0x1500ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_drop_reasons_ch1[]={ + { .uname = "ERRORBLK_RxC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_PF_SAD_REGION", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_AD_CRD", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_CAM_FULL", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_CAM_HIT", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_SECURE_DROP", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RPQ_PROXY", + .udesc = "TBD (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STOP_B2B", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WPQ_PROXY", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XPT_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_drop_reasons_ch2[]={ + { .uname = "ERRORBLK_RxC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NOT_PF_SAD_REGION", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_AD_CRD", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_CAM_FULL", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_CAM_HIT", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PF_SECURE_DROP", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RPQ_PROXY", + .udesc = "TBD (experimental)", + .ucode = 0x100000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "STOP_B2B", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x400000000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WPQ_PROXY", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XPT_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x200000000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_inserts[]={ + { .uname = "CH0_UPI", + .udesc = "UPI - Ch 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0_XPT", + .udesc = "XPT - Ch 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_UPI", + .udesc = "UPI - Ch 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1_XPT", + .udesc = "XPT - Ch 1 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_UPI", + .udesc = "UPI - Ch 2 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2_XPT", + .udesc = "XPT - Ch 2 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI_ALLCH", + .udesc = "UPI - All Channels (experimental)", + .ucode = 0x2a00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "XPT_ALLCH", + .udesc = "XPT - All Channels (experimental)", + .ucode = 0x1500ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_resp_miss[]={ + { .uname = "ALLCH", + .udesc = "All Channels (experimental)", + .ucode = 0x0700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_prefcam_rxc_deallocs[]={ + { .uname = "1LM_POSTED", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CIS", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_MEMMODE_ACCEPT", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SQUASHED", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ring_bounces_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ring_sink_starved_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "Acknowledgements to Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_ring_sink_starved_vert[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "Acknowledgements to core (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "Data Responses to core (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "Snoops of processor's cache. (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_rpq_no_spec_crd[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_rxr_crd_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IFV", + .udesc = "IFV - Credited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_rxr_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_rxr_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_stall0_no_txr_horz_crd_ad_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag1[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_tag_hit[]={ + { .uname = "NM_RD_HIT_CLEAN", + .udesc = "Clean NearMem Read Hit", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_RD_HIT_DIRTY", + .udesc = "Dirty NearMem Read Hit", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_UFILL_HIT_CLEAN", + .udesc = "Clean NearMem Underfill Hit (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NM_UFILL_HIT_DIRTY", + .udesc = "Dirty NearMem Underfill Hit (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_tracker_inserts[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_tracker_occupancy[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_ak[]={ + { .uname = "CRD_CBO", + .udesc = "CRD Transactions to Cbo (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NDR", + .udesc = "NDR Transactions (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_ak_cycles_full[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDCRD0", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDCRD1", + .udesc = "TBD (experimental)", + .ucode = 0x8800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCMP0", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCMP1", + .udesc = "TBD (experimental)", + .ucode = 0xa000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCRD0", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCRD1", + .udesc = "TBD (experimental)", + .ucode = 0x9000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_ak_inserts[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PREF_RD_CAM_HIT", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDCRD", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCMP", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCRD", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_ak_no_credit_cycles[]={ + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_ak_occupancy[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDCRD", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCMP", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WRCRD", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_bl[]={ + { .uname = "DRS_CACHE", + .udesc = "Data to Cache (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_CORE", + .udesc = "Data to Core (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_UPI", + .udesc = "Data to QPI (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_bl_credits_acquired[]={ + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_bl_cycles_ne[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_bl_inserts[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0300ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txc_bl_no_credit_stalled[]={ + { .uname = "CMS0", + .udesc = "Common Mesh Stop - Near Side (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CMS1", + .udesc = "Common Mesh Stop - Far Side (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_horz_ads_used[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_horz_cycles_full[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_horz_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_horz_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_horz_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_ads_used[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_bypass[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG1", + .udesc = "IV - Agent 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_cycles_full1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_cycles_ne0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_inserts1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_occupancy0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_occupancy1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_starved0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_txr_vert_starved1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGC", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_vert_ring_akc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_vert_ring_bl_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_vert_ring_iv_in_use[]={ + { .uname = "DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_vert_ring_tgc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wpq_no_reg_crd[]={ + { .uname = "CHN0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wpq_no_spec_crd[]={ + { .uname = "CHN0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHN2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wr_tracker_full[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MIRR", + .udesc = "Mirror (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wr_tracker_inserts[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wr_tracker_nonposted_occupancy[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wr_tracker_occupancy[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MIRR", + .udesc = "Mirror (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MIRR_NONTGR", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MIRR_PWR", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2m_wr_tracker_posted_occupancy[]={ + { .uname = "CH0", + .udesc = "Channel 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH1", + .udesc = "Channel 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CH2", + .udesc = "Channel 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_m2m_pe[]={ + { .name = "UNC_M2M_AG0_AD_CRD_ACQUIRED0", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0080, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2m_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M2M_AG0_AD_CRD_ACQUIRED1", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0081, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2m_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M2M_AG0_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0082, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_ad_crd_occupancy0), + .umasks = icx_unc_m2m_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M2M_AG0_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0083, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_ad_crd_occupancy1), + .umasks = icx_unc_m2m_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M2M_AG0_BL_CRD_ACQUIRED0", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0088, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_bl_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2m_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M2M_AG0_BL_CRD_ACQUIRED1", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0089, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2m_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M2M_AG0_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_bl_crd_occupancy0), + .umasks = icx_unc_m2m_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M2M_AG0_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag0_bl_crd_occupancy1), + .umasks = icx_unc_m2m_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M2M_AG1_AD_CRD_ACQUIRED0", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0084, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2m_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M2M_AG1_AD_CRD_ACQUIRED1", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0085, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2m_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M2M_AG1_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0086, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_ad_crd_occupancy0), + .umasks = icx_unc_m2m_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M2M_AG1_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0087, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_ad_crd_occupancy1), + .umasks = icx_unc_m2m_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M2M_AG1_BL_CRD_ACQUIRED0", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_bl_crd_acquired0), + .umasks = icx_unc_m2m_ag1_bl_crd_acquired0, + }, + { .name = "UNC_M2M_AG1_BL_CRD_ACQUIRED1", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2m_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M2M_AG1_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall0_no_txr_horz_crd_ad_ag0), /* shared */ + .umasks = icx_unc_m2m_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M2M_AG1_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ag1_bl_crd_occupancy1), + .umasks = icx_unc_m2m_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M2M_BYPASS_M2M_EGRESS", + .desc = "M2M to iMC Bypass", + .code = 0x0022, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_bypass_m2m_ingress), /* shared */ + .umasks = icx_unc_m2m_bypass_m2m_ingress, + }, + { .name = "UNC_M2M_BYPASS_M2M_INGRESS", + .desc = "M2M to iMC Bypass", + .code = 0x0021, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_bypass_m2m_ingress), + .umasks = icx_unc_m2m_bypass_m2m_ingress, + }, + { .name = "UNC_M2M_CLOCKTICKS", + .desc = "Clockticks of the mesh to memory (M2M)", + .code = 0x0000, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_CMS_CLOCKTICKS", + .desc = "CMS Clockticks", + .code = 0x00c0, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + .desc = "Cycles when direct to core mode, which bypasses the CHA, was disabled (experimental)", + .code = 0x0024, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + .desc = "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED (experimental)", + .code = 0x0060, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + .desc = "Number of reads in which direct to core transaction was overridden (experimental)", + .code = 0x0025, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + .desc = "Number of reads in which direct to Intel UPI transactions were overridden (experimental)", + .code = 0x0028, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + .desc = "Cycles when Direct2UPI was Disabled (experimental)", + .code = 0x0027, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + .desc = "Number of reads that a message sent direct2 Intel UPI was overridden (experimental)", + .code = 0x0029, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DIRECTORY_HIT", + .desc = "Directory Hit", + .code = 0x002a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_directory_miss), /* shared */ + .umasks = icx_unc_m2m_directory_miss, + }, + { .name = "UNC_M2M_DIRECTORY_LOOKUP", + .desc = "Multi-socket cacheline Directory Lookups", + .code = 0x002d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_directory_lookup), + .umasks = icx_unc_m2m_directory_lookup, + }, + { .name = "UNC_M2M_DIRECTORY_MISS", + .desc = "Directory Miss", + .code = 0x002b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_directory_miss), + .umasks = icx_unc_m2m_directory_miss, + }, + { .name = "UNC_M2M_DIRECTORY_UPDATE", + .desc = "Multi-socket cacheline Directory Updates", + .code = 0x002e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_directory_update), + .umasks = icx_unc_m2m_directory_update, + }, + { .name = "UNC_M2M_DISTRESS_ASSERTED", + .desc = "Distress signal asserted", + .code = 0x00af, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_distress_asserted), + .umasks = icx_unc_m2m_distress_asserted, + }, + { .name = "UNC_M2M_DISTRESS_PMM", + .desc = "UNC_M2M_DISTRESS_PMM (experimental)", + .code = 0x00f2, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_DISTRESS_PMM_MEMMODE", + .desc = "UNC_M2M_DISTRESS_PMM_MEMMODE (experimental)", + .code = 0x00f1, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_EGRESS_ORDERING", + .desc = "Egress Blocking due to Ordering requirements", + .code = 0x00ba, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_egress_ordering), + .umasks = icx_unc_m2m_egress_ordering, + }, + { .name = "UNC_M2M_HORZ_RING_AD_IN_USE", + .desc = "Horizontal AD Ring In Use", + .code = 0x00b6, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_horz_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m2m_horz_ring_akc_in_use, + }, + { .name = "UNC_M2M_HORZ_RING_AKC_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00bb, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_horz_ring_akc_in_use), + .umasks = icx_unc_m2m_horz_ring_akc_in_use, + }, + { .name = "UNC_M2M_HORZ_RING_AK_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00b7, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_horz_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m2m_horz_ring_bl_in_use, + }, + { .name = "UNC_M2M_HORZ_RING_BL_IN_USE", + .desc = "Horizontal BL Ring in Use", + .code = 0x00b8, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_horz_ring_bl_in_use), + .umasks = icx_unc_m2m_horz_ring_bl_in_use, + }, + { .name = "UNC_M2M_HORZ_RING_IV_IN_USE", + .desc = "Horizontal IV Ring in Use", + .code = 0x00b9, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_horz_ring_iv_in_use), + .umasks = icx_unc_m2m_horz_ring_iv_in_use, + }, + { .name = "UNC_M2M_IMC_READS", + .desc = "M2M Reads Issued to iMC", + .code = 0x0037, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_imc_reads), + .umasks = icx_unc_m2m_imc_reads, + }, + { .name = "UNC_M2M_IMC_WRITES", + .desc = "M2M Writes Issued to iMC", + .code = 0x0038, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_imc_writes), + .umasks = icx_unc_m2m_imc_writes, + }, + { .name = "UNC_M2M_MIRR_WRQ_INSERTS", + .desc = "Write Tracker Inserts (experimental)", + .code = 0x0064, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_MIRR_WRQ_OCCUPANCY", + .desc = "Write Tracker Occupancy (experimental)", + .code = 0x0065, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_MISC_EXTERNAL", + .desc = "Miscellaneous Events (mostly from MS2IDI)", + .code = 0x00e6, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_misc_external), + .umasks = icx_unc_m2m_misc_external, + }, + { .name = "UNC_M2M_PKT_MATCH", + .desc = "Number Packet Header Matches", + .code = 0x004c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_pkt_match), + .umasks = icx_unc_m2m_pkt_match, + }, + { .name = "UNC_M2M_PREFCAM_CIS_DROPS", + .desc = "UNC_M2M_PREFCAM_CIS_DROPS (experimental)", + .code = 0x0073, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_PREFCAM_CYCLES_FULL", + .desc = "Prefetch CAM Cycles Full", + .code = 0x006b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_cycles_ne), /* shared */ + .umasks = icx_unc_m2m_prefcam_cycles_ne, + }, + { .name = "UNC_M2M_PREFCAM_CYCLES_NE", + .desc = "Prefetch CAM Cycles Not Empty", + .code = 0x006c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_cycles_ne), + .umasks = icx_unc_m2m_prefcam_cycles_ne, + }, + { .name = "UNC_M2M_PREFCAM_DEALLOCS", + .desc = "Prefetch CAM Deallocs", + .code = 0x006e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_deallocs), + .umasks = icx_unc_m2m_prefcam_deallocs, + }, + { .name = "UNC_M2M_PREFCAM_DEMAND_DROPS", + .desc = "Data Prefetches Dropped", + .code = 0x006f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_inserts), /* shared */ + .umasks = icx_unc_m2m_prefcam_inserts, + }, + { .name = "UNC_M2M_PREFCAM_DEMAND_MERGE", + .desc = "Demands Merged with CAMed Prefetches", + .code = 0x0074, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_demand_merge), + .umasks = icx_unc_m2m_prefcam_demand_merge, + }, + { .name = "UNC_M2M_PREFCAM_DEMAND_NO_MERGE", + .desc = "Demands Not Merged with CAMed Prefetches", + .code = 0x0075, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_demand_no_merge), + .umasks = icx_unc_m2m_prefcam_demand_no_merge, + }, + { .name = "UNC_M2M_PREFCAM_DROP_REASONS_CH0", + .desc = "Data Prefetches Dropped Ch0 - Reasons", + .code = 0x0070, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_drop_reasons_ch1), /* shared */ + .umasks = icx_unc_m2m_prefcam_drop_reasons_ch1, + }, + { .name = "UNC_M2M_PREFCAM_DROP_REASONS_CH1", + .desc = "Data Prefetches Dropped Ch1 - Reasons", + .code = 0x0071, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_drop_reasons_ch1), + .umasks = icx_unc_m2m_prefcam_drop_reasons_ch1, + }, + { .name = "UNC_M2M_PREFCAM_DROP_REASONS_CH2", + .desc = "Data Prefetches Dropped Ch2 - Reasons", + .code = 0x0072, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_drop_reasons_ch2), + .umasks = icx_unc_m2m_prefcam_drop_reasons_ch2, + }, + { .name = "UNC_M2M_PREFCAM_INSERTS", + .desc = "Prefetch CAM Inserts", + .code = 0x006d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_inserts), + .umasks = icx_unc_m2m_prefcam_inserts, + }, + { .name = "UNC_M2M_PREFCAM_OCCUPANCY", + .desc = "Prefetch CAM Occupancy", + .code = 0x006a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_resp_miss), /* shared */ + .umasks = icx_unc_m2m_prefcam_resp_miss, + }, + { .name = "UNC_M2M_PREFCAM_RESP_MISS", + .desc = "TBD", + .code = 0x0076, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_resp_miss), + .umasks = icx_unc_m2m_prefcam_resp_miss, + }, + { .name = "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + .desc = "UNC_M2M_PREFCAM_RxC_CYCLES_NE (experimental)", + .code = 0x0079, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_PREFCAM_RxC_DEALLOCS", + .desc = "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + .code = 0x007a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_prefcam_rxc_deallocs), + .umasks = icx_unc_m2m_prefcam_rxc_deallocs, + }, + { .name = "UNC_M2M_PREFCAM_RxC_INSERTS", + .desc = "UNC_M2M_PREFCAM_RxC_INSERTS (experimental)", + .code = 0x0078, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RING_BOUNCES_HORZ", + .desc = "Messages that bounced on the Horizontal Ring.", + .code = 0x00ac, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ring_bounces_horz), + .umasks = icx_unc_m2m_ring_bounces_horz, + }, + { .name = "UNC_M2M_RING_BOUNCES_VERT", + .desc = "Messages that bounced on the Vertical Ring.", + .code = 0x00aa, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ring_sink_starved_vert), /* shared */ + .umasks = icx_unc_m2m_ring_sink_starved_vert, + }, + { .name = "UNC_M2M_RING_SINK_STARVED_HORZ", + .desc = "Sink Starvation on Horizontal Ring", + .code = 0x00ad, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ring_sink_starved_horz), + .umasks = icx_unc_m2m_ring_sink_starved_horz, + }, + { .name = "UNC_M2M_RING_SINK_STARVED_VERT", + .desc = "Sink Starvation on Vertical Ring", + .code = 0x00ab, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_ring_sink_starved_vert), + .umasks = icx_unc_m2m_ring_sink_starved_vert, + }, + { .name = "UNC_M2M_RING_SRC_THRTL", + .desc = "Source Throttle (experimental)", + .code = 0x00ae, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RPQ_NO_REG_CRD", + .desc = "M2M to iMC RPQ Cycles w/Credits - Regular", + .code = 0x0043, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rpq_no_spec_crd), /* shared */ + .umasks = icx_unc_m2m_rpq_no_spec_crd, + }, + { .name = "UNC_M2M_RPQ_NO_REG_CRD_PMM", + .desc = "M2M->iMC RPQ Cycles w/Credits - PMM", + .code = 0x004f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wpq_no_reg_crd), /* shared */ + .umasks = icx_unc_m2m_wpq_no_reg_crd, + }, + { .name = "UNC_M2M_RPQ_NO_SPEC_CRD", + .desc = "M2M to iMC RPQ Cycles w/Credits - Special", + .code = 0x0044, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rpq_no_spec_crd), + .umasks = icx_unc_m2m_rpq_no_spec_crd, + }, + { .name = "UNC_M2M_RxC_AD_CYCLES_FULL", + .desc = "AD Ingress (from CMS) Full (experimental)", + .code = 0x0004, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_AD_CYCLES_NE", + .desc = "AD Ingress (from CMS) Not Empty (experimental)", + .code = 0x0003, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_AD_INSERTS", + .desc = "AD Ingress (from CMS) Allocations (experimental)", + .code = 0x0001, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_AD_OCCUPANCY", + .desc = "AD Ingress (from CMS) Occupancy (experimental)", + .code = 0x0002, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + .desc = "AD Ingress (from CMS) Occupancy - Prefetches (experimental)", + .code = 0x0077, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_AK_WR_CMP", + .desc = "AK Egress (to CMS) Allocations (experimental)", + .code = 0x005c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_BL_CYCLES_FULL", + .desc = "BL Ingress (from CMS) Full (experimental)", + .code = 0x0008, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_BL_CYCLES_NE", + .desc = "BL Ingress (from CMS) Not Empty (experimental)", + .code = 0x0007, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_BL_INSERTS", + .desc = "BL Ingress (from CMS) Allocations (experimental)", + .code = 0x0005, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxC_BL_OCCUPANCY", + .desc = "BL Ingress (from CMS) Occupancy (experimental)", + .code = 0x0006, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxR_BUSY_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e5, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_ads_used), /* shared */ + .umasks = icx_unc_m2m_txr_horz_ads_used, + }, + { .name = "UNC_M2M_RxR_BYPASS", + .desc = "Transgress Ingress Bypass", + .code = 0x00e2, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rxr_inserts), /* shared */ + .umasks = icx_unc_m2m_rxr_inserts, + }, + { .name = "UNC_M2M_RxR_CRD_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e3, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rxr_crd_starved), + .umasks = icx_unc_m2m_rxr_crd_starved, + }, + { .name = "UNC_M2M_RxR_CRD_STARVED_1", + .desc = "Transgress Injection Starvation (experimental)", + .code = 0x00e4, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_RxR_INSERTS", + .desc = "Transgress Ingress Allocations", + .code = 0x00e1, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rxr_inserts), + .umasks = icx_unc_m2m_rxr_inserts, + }, + { .name = "UNC_M2M_RxR_OCCUPANCY", + .desc = "Transgress Ingress Occupancy", + .code = 0x00e0, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_rxr_occupancy), + .umasks = icx_unc_m2m_rxr_occupancy, + }, + { .name = "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + .desc = "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS (experimental)", + .code = 0x0033, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + .desc = "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS (experimental)", + .code = 0x0034, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS", + .desc = "Retry - Mem Mirroring Mode (experimental)", + .code = 0x0035, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS", + .desc = "Retry - Mem Mirroring Mode (experimental)", + .code = 0x0036, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_RD_ACCEPTS", + .desc = "Scoreboard Accepts (experimental)", + .code = 0x002f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_RD_REJECTS", + .desc = "Scoreboard Rejects (experimental)", + .code = 0x0030, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_WR_ACCEPTS", + .desc = "Scoreboard Accepts (experimental)", + .code = 0x0031, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_SCOREBOARD_WR_REJECTS", + .desc = "Scoreboard Rejects (experimental)", + .code = 0x0032, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d0, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall0_no_txr_horz_crd_ad_ag0), + .umasks = icx_unc_m2m_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d2, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag0), /* shared */ + .umasks = icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d4, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag0), + .umasks = icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d6, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag1), + .umasks = icx_unc_m2m_stall0_no_txr_horz_crd_bl_ag1, + }, + { .name = "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d1, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1), /* shared */ + .umasks = icx_unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d3, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1), + .umasks = icx_unc_m2m_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d5, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1), /* shared */ + .umasks = icx_unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d7, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1), + .umasks = icx_unc_m2m_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M2M_TAG_HIT", + .desc = "Tag Hit", + .code = 0x002c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_tag_hit), + .umasks = icx_unc_m2m_tag_hit, + }, + { .name = "UNC_M2M_TAG_MISS", + .desc = "Tag Miss (experimental)", + .code = 0x0061, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TGR_AD_CREDITS", + .desc = "Number AD Ingress Credits (experimental)", + .code = 0x0041, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TGR_BL_CREDITS", + .desc = "Number BL Ingress Credits (experimental)", + .code = 0x0042, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TRACKER_FULL", + .desc = "Tracker Cycles Full", + .code = 0x0045, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_tracker_inserts), /* shared */ + .umasks = icx_unc_m2m_tracker_inserts, + }, + { .name = "UNC_M2M_TRACKER_INSERTS", + .desc = "Tracker Inserts", + .code = 0x0049, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_tracker_inserts), + .umasks = icx_unc_m2m_tracker_inserts, + }, + { .name = "UNC_M2M_TRACKER_NE", + .desc = "Tracker Cycles Not Empty", + .code = 0x0046, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_tracker_occupancy), /* shared */ + .umasks = icx_unc_m2m_tracker_occupancy, + }, + { .name = "UNC_M2M_TRACKER_OCCUPANCY", + .desc = "Tracker Occupancy", + .code = 0x0047, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_tracker_occupancy), + .umasks = icx_unc_m2m_tracker_occupancy, + }, + { .name = "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + .desc = "AD Egress (to CMS) Credit Acquired (experimental)", + .code = 0x000d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + .desc = "AD Egress (to CMS) Credits Occupancy (experimental)", + .code = 0x000e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_CYCLES_FULL", + .desc = "AD Egress (to CMS) Full (experimental)", + .code = 0x000c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_CYCLES_NE", + .desc = "AD Egress (to CMS) Not Empty (experimental)", + .code = 0x000b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_INSERTS", + .desc = "AD Egress (to CMS) Allocations (experimental)", + .code = 0x0009, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + .desc = "Cycles with No AD Egress (to CMS) Credits (experimental)", + .code = 0x000f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + .desc = "Cycles Stalled with No AD Egress (to CMS) Credits (experimental)", + .code = 0x0010, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AD_OCCUPANCY", + .desc = "AD Egress (to CMS) Occupancy (experimental)", + .code = 0x000a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AK", + .desc = "Outbound Ring Transactions on AK", + .code = 0x0039, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak), + .umasks = icx_unc_m2m_txc_ak, + }, + { .name = "UNC_M2M_TxC_AKC_CREDITS", + .desc = "AKC Credits (experimental)", + .code = 0x005f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2M_TxC_AK_CREDITS_ACQUIRED", + .desc = "AK Egress (to CMS) Credit Acquired", + .code = 0x001d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_no_credit_cycles), /* shared */ + .umasks = icx_unc_m2m_txc_ak_no_credit_cycles, + }, + { .name = "UNC_M2M_TxC_AK_CYCLES_FULL", + .desc = "AK Egress (to CMS) Full", + .code = 0x0014, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_cycles_full), + .umasks = icx_unc_m2m_txc_ak_cycles_full, + }, + { .name = "UNC_M2M_TxC_AK_CYCLES_NE", + .desc = "AK Egress (to CMS) Not Empty", + .code = 0x0013, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_occupancy), /* shared */ + .umasks = icx_unc_m2m_txc_ak_occupancy, + }, + { .name = "UNC_M2M_TxC_AK_INSERTS", + .desc = "AK Egress (to CMS) Allocations", + .code = 0x0011, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_inserts), + .umasks = icx_unc_m2m_txc_ak_inserts, + }, + { .name = "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES", + .desc = "Cycles with No AK Egress (to CMS) Credits", + .code = 0x001f, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_no_credit_cycles), + .umasks = icx_unc_m2m_txc_ak_no_credit_cycles, + }, + { .name = "UNC_M2M_TxC_AK_NO_CREDIT_STALLED", + .desc = "Cycles Stalled with No AK Egress (to CMS) Credits", + .code = 0x0020, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_credits_acquired), /* shared */ + .umasks = icx_unc_m2m_txc_bl_credits_acquired, + }, + { .name = "UNC_M2M_TxC_AK_OCCUPANCY", + .desc = "AK Egress (to CMS) Occupancy", + .code = 0x0012, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_ak_occupancy), + .umasks = icx_unc_m2m_txc_ak_occupancy, + }, + { .name = "UNC_M2M_TxC_BL", + .desc = "Outbound DRS Ring Transactions to Cache", + .code = 0x0040, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl), + .umasks = icx_unc_m2m_txc_bl, + }, + { .name = "UNC_M2M_TxC_BL_CREDITS_ACQUIRED", + .desc = "BL Egress (to CMS) Credit Acquired", + .code = 0x0019, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_credits_acquired), + .umasks = icx_unc_m2m_txc_bl_credits_acquired, + }, + { .name = "UNC_M2M_TxC_BL_CYCLES_FULL", + .desc = "BL Egress (to CMS) Full", + .code = 0x0018, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_cycles_ne), /* shared */ + .umasks = icx_unc_m2m_txc_bl_cycles_ne, + }, + { .name = "UNC_M2M_TxC_BL_CYCLES_NE", + .desc = "BL Egress (to CMS) Not Empty", + .code = 0x0017, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_cycles_ne), + .umasks = icx_unc_m2m_txc_bl_cycles_ne, + }, + { .name = "UNC_M2M_TxC_BL_INSERTS", + .desc = "BL Egress (to CMS) Allocations", + .code = 0x0015, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_inserts), + .umasks = icx_unc_m2m_txc_bl_inserts, + }, + { .name = "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES", + .desc = "Cycles with No BL Egress (to CMS) Credits", + .code = 0x001b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_no_credit_stalled), /* shared */ + .umasks = icx_unc_m2m_txc_bl_no_credit_stalled, + }, + { .name = "UNC_M2M_TxC_BL_NO_CREDIT_STALLED", + .desc = "Cycles Stalled with No BL Egress (to CMS) Credits", + .code = 0x001c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txc_bl_no_credit_stalled), + .umasks = icx_unc_m2m_txc_bl_no_credit_stalled, + }, + { .name = "UNC_M2M_TxR_HORZ_ADS_USED", + .desc = "CMS Horizontal ADS Used", + .code = 0x00a6, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_ads_used), + .umasks = icx_unc_m2m_txr_horz_ads_used, + }, + { .name = "UNC_M2M_TxR_HORZ_BYPASS", + .desc = "CMS Horizontal Bypass Used", + .code = 0x00a7, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_cycles_full), /* shared */ + .umasks = icx_unc_m2m_txr_horz_cycles_full, + }, + { .name = "UNC_M2M_TxR_HORZ_CYCLES_FULL", + .desc = "Cycles CMS Horizontal Egress Queue is Full", + .code = 0x00a2, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_cycles_full), + .umasks = icx_unc_m2m_txr_horz_cycles_full, + }, + { .name = "UNC_M2M_TxR_HORZ_CYCLES_NE", + .desc = "Cycles CMS Horizontal Egress Queue is Not Empty", + .code = 0x00a3, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_inserts), /* shared */ + .umasks = icx_unc_m2m_txr_horz_inserts, + }, + { .name = "UNC_M2M_TxR_HORZ_INSERTS", + .desc = "CMS Horizontal Egress Inserts", + .code = 0x00a1, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_inserts), + .umasks = icx_unc_m2m_txr_horz_inserts, + }, + { .name = "UNC_M2M_TxR_HORZ_NACK", + .desc = "CMS Horizontal Egress NACKs", + .code = 0x00a4, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_occupancy), /* shared */ + .umasks = icx_unc_m2m_txr_horz_occupancy, + }, + { .name = "UNC_M2M_TxR_HORZ_OCCUPANCY", + .desc = "CMS Horizontal Egress Occupancy", + .code = 0x00a0, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_occupancy), + .umasks = icx_unc_m2m_txr_horz_occupancy, + }, + { .name = "UNC_M2M_TxR_HORZ_STARVED", + .desc = "CMS Horizontal Egress Injection Starvation", + .code = 0x00a5, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_horz_starved), + .umasks = icx_unc_m2m_txr_horz_starved, + }, + { .name = "UNC_M2M_TxR_VERT_ADS_USED", + .desc = "CMS Vertical ADS Used", + .code = 0x009c, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_ads_used), + .umasks = icx_unc_m2m_txr_vert_ads_used, + }, + { .name = "UNC_M2M_TxR_VERT_BYPASS", + .desc = "CMS Vertical ADS Used", + .code = 0x009d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_bypass), + .umasks = icx_unc_m2m_txr_vert_bypass, + }, + { .name = "UNC_M2M_TxR_VERT_BYPASS_1", + .desc = "CMS Vertical ADS Used", + .code = 0x009e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_cycles_full1), /* shared */ + .umasks = icx_unc_m2m_txr_vert_cycles_full1, + }, + { .name = "UNC_M2M_TxR_VERT_CYCLES_FULL0", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0094, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_cycles_ne0), /* shared */ + .umasks = icx_unc_m2m_txr_vert_cycles_ne0, + }, + { .name = "UNC_M2M_TxR_VERT_CYCLES_FULL1", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0095, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_cycles_full1), + .umasks = icx_unc_m2m_txr_vert_cycles_full1, + }, + { .name = "UNC_M2M_TxR_VERT_CYCLES_NE0", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0096, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_cycles_ne0), + .umasks = icx_unc_m2m_txr_vert_cycles_ne0, + }, + { .name = "UNC_M2M_TxR_VERT_CYCLES_NE1", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0097, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_inserts1), /* shared */ + .umasks = icx_unc_m2m_txr_vert_inserts1, + }, + { .name = "UNC_M2M_TxR_VERT_INSERTS0", + .desc = "CMS Vert Egress Allocations", + .code = 0x0092, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_occupancy0), /* shared */ + .umasks = icx_unc_m2m_txr_vert_occupancy0, + }, + { .name = "UNC_M2M_TxR_VERT_INSERTS1", + .desc = "CMS Vert Egress Allocations", + .code = 0x0093, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_inserts1), + .umasks = icx_unc_m2m_txr_vert_inserts1, + }, + { .name = "UNC_M2M_TxR_VERT_NACK0", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0098, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_starved0), /* shared */ + .umasks = icx_unc_m2m_txr_vert_starved0, + }, + { .name = "UNC_M2M_TxR_VERT_NACK1", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0099, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_occupancy1), /* shared */ + .umasks = icx_unc_m2m_txr_vert_occupancy1, + }, + { .name = "UNC_M2M_TxR_VERT_OCCUPANCY0", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0090, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_occupancy0), + .umasks = icx_unc_m2m_txr_vert_occupancy0, + }, + { .name = "UNC_M2M_TxR_VERT_OCCUPANCY1", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0091, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_occupancy1), + .umasks = icx_unc_m2m_txr_vert_occupancy1, + }, + { .name = "UNC_M2M_TxR_VERT_STARVED0", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_starved0), + .umasks = icx_unc_m2m_txr_vert_starved0, + }, + { .name = "UNC_M2M_TxR_VERT_STARVED1", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_txr_vert_starved1), + .umasks = icx_unc_m2m_txr_vert_starved1, + }, + { .name = "UNC_M2M_VERT_RING_AD_IN_USE", + .desc = "Vertical AD Ring In Use", + .code = 0x00b0, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m2m_vert_ring_akc_in_use, + }, + { .name = "UNC_M2M_VERT_RING_AKC_IN_USE", + .desc = "Vertical AKC Ring In Use", + .code = 0x00b4, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_akc_in_use), + .umasks = icx_unc_m2m_vert_ring_akc_in_use, + }, + { .name = "UNC_M2M_VERT_RING_AK_IN_USE", + .desc = "Vertical AK Ring In Use", + .code = 0x00b1, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m2m_vert_ring_bl_in_use, + }, + { .name = "UNC_M2M_VERT_RING_BL_IN_USE", + .desc = "Vertical BL Ring in Use", + .code = 0x00b2, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_bl_in_use), + .umasks = icx_unc_m2m_vert_ring_bl_in_use, + }, + { .name = "UNC_M2M_VERT_RING_IV_IN_USE", + .desc = "Vertical IV Ring in Use", + .code = 0x00b3, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_iv_in_use), + .umasks = icx_unc_m2m_vert_ring_iv_in_use, + }, + { .name = "UNC_M2M_VERT_RING_TGC_IN_USE", + .desc = "Vertical TGC Ring In Use", + .code = 0x00b5, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_vert_ring_tgc_in_use), + .umasks = icx_unc_m2m_vert_ring_tgc_in_use, + }, + { .name = "UNC_M2M_WPQ_FLUSH", + .desc = "WPQ Flush", + .code = 0x0058, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_inserts), /* shared */ + .umasks = icx_unc_m2m_wr_tracker_inserts, + }, + { .name = "UNC_M2M_WPQ_NO_REG_CRD", + .desc = "M2M->iMC WPQ Cycles w/Credits - Regular", + .code = 0x004d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wpq_no_reg_crd), + .umasks = icx_unc_m2m_wpq_no_reg_crd, + }, + { .name = "UNC_M2M_WPQ_NO_REG_CRD_PMM", + .desc = "M2M->iMC WPQ Cycles w/Credits - PMM", + .code = 0x0051, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wpq_no_spec_crd), /* shared */ + .umasks = icx_unc_m2m_wpq_no_spec_crd, + }, + { .name = "UNC_M2M_WPQ_NO_SPEC_CRD", + .desc = "M2M->iMC WPQ Cycles w/Credits - Special", + .code = 0x004e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wpq_no_spec_crd), + .umasks = icx_unc_m2m_wpq_no_spec_crd, + }, + { .name = "UNC_M2M_WR_TRACKER_FULL", + .desc = "Write Tracker Cycles Full", + .code = 0x004a, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_full), + .umasks = icx_unc_m2m_wr_tracker_full, + }, + { .name = "UNC_M2M_WR_TRACKER_INSERTS", + .desc = "Write Tracker Inserts", + .code = 0x0056, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_inserts), + .umasks = icx_unc_m2m_wr_tracker_inserts, + }, + { .name = "UNC_M2M_WR_TRACKER_NE", + .desc = "Write Tracker Cycles Not Empty", + .code = 0x004b, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_occupancy), /* shared */ + .umasks = icx_unc_m2m_wr_tracker_occupancy, + }, + { .name = "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS", + .desc = "Write Tracker Non-Posted Inserts", + .code = 0x0063, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_nonposted_occupancy), /* shared */ + .umasks = icx_unc_m2m_wr_tracker_nonposted_occupancy, + }, + { .name = "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY", + .desc = "Write Tracker Non-Posted Occupancy", + .code = 0x0062, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_nonposted_occupancy), + .umasks = icx_unc_m2m_wr_tracker_nonposted_occupancy, + }, + { .name = "UNC_M2M_WR_TRACKER_OCCUPANCY", + .desc = "Write Tracker Occupancy", + .code = 0x0055, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_occupancy), + .umasks = icx_unc_m2m_wr_tracker_occupancy, + }, + { .name = "UNC_M2M_WR_TRACKER_POSTED_INSERTS", + .desc = "Write Tracker Posted Inserts", + .code = 0x005e, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_posted_occupancy), /* shared */ + .umasks = icx_unc_m2m_wr_tracker_posted_occupancy, + }, + { .name = "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY", + .desc = "Write Tracker Posted Occupancy", + .code = 0x005d, + .modmsk = ICX_UNC_M2M_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2m_wr_tracker_posted_occupancy), + .umasks = icx_unc_m2m_wr_tracker_posted_occupancy, + }, +}; +/* 175 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_m2pcie_events.h b/src/libpfm4/lib/events/intel_icx_unc_m2pcie_events.h new file mode 100644 index 000000000..cf5e806cb --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_m2pcie_events.h @@ -0,0 +1,2969 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_m2pcie (IcelakeX Uncore M2PCIE) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_m2p_ag0_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag0_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag0_bl_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag0_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag1_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag1_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag1_bl_crd_acquired0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ag1_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_distress_asserted[]={ + { .uname = "DPT_LOCAL", + .udesc = "DPT Local (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_NONLOCAL", + .udesc = "DPT Remote (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_IV", + .udesc = "DPT Stalled - IV (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_NOCRD", + .udesc = "DPT Stalled - No Credit (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HORZ", + .udesc = "Horizontal (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_LOCAL", + .udesc = "PMM Local (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_NONLOCAL", + .udesc = "PMM Remote (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VERT", + .udesc = "Vertical (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_egress_ordering[]={ + { .uname = "IV_SNOOPGO_DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_SNOOPGO_UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_horz_ring_akc_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_horz_ring_bl_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_horz_ring_iv_in_use[]={ + { .uname = "LEFT", + .udesc = "Left (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT", + .udesc = "Right (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_iio_credits_acquired[]={ + { .uname = "DRS_0", + .udesc = "DRS (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_1", + .udesc = "DRS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_0", + .udesc = "NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_1", + .udesc = "NCB (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_0", + .udesc = "NCS (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_1", + .udesc = "NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_iio_credits_reject[]={ + { .uname = "DRS", + .udesc = "DRS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB", + .udesc = "NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_iio_credits_used[]={ + { .uname = "DRS_0", + .udesc = "DRS to CMS Port 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DRS_1", + .udesc = "DRS to CMS Port 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_0", + .udesc = "NCB to CMS Port 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_1", + .udesc = "NCB to CMS Port 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_0", + .udesc = "NCS to CMS Port 0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_1", + .udesc = "NCS to CMS Port 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_p2p_ded_returned_0[]={ + { .uname = "MS2IOSF0_NCB", + .udesc = "M2IOSF0 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF0_NCS", + .udesc = "M2IOSF0 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF1_NCB", + .udesc = "M2IOSF1 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF1_NCS", + .udesc = "M2IOSF1 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF2_NCB", + .udesc = "M2IOSF2 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF2_NCS", + .udesc = "M2IOSF2 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF3_NCB", + .udesc = "M2IOSF3 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF3_NCS", + .udesc = "M2IOSF3 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_p2p_ded_returned_1[]={ + { .uname = "MS2IOSF4_NCB", + .udesc = "M2IOSF4 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF4_NCS", + .udesc = "M2IOSF4 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF5_NCB", + .udesc = "M2IOSF5 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MS2IOSF5_NCS", + .udesc = "M2IOSF5 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_shar_p2p_crd_returned[]={ + { .uname = "AGENT_0", + .udesc = "Agent0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_1", + .udesc = "Agent1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_2", + .udesc = "Agent2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_3", + .udesc = "Agent3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_4", + .udesc = "Agent4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_5", + .udesc = "Agent5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_shar_p2p_crd_taken_0[]={ + { .uname = "M2IOSF0_NCB", + .udesc = "M2IOSF0 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF0_NCS", + .udesc = "M2IOSF0 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF1_NCB", + .udesc = "M2IOSF1 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF1_NCS", + .udesc = "M2IOSF1 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF2_NCB", + .udesc = "M2IOSF2 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF2_NCS", + .udesc = "M2IOSF2 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF3_NCB", + .udesc = "M2IOSF3 - NCB (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF3_NCS", + .udesc = "M2IOSF3 - NCS (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_shar_p2p_crd_taken_1[]={ + { .uname = "M2IOSF4_NCB", + .udesc = "M2IOSF4 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF4_NCS", + .udesc = "M2IOSF4 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF5_NCB", + .udesc = "M2IOSF5 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF5_NCS", + .udesc = "M2IOSF5 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_shar_p2p_crd_wait_0[]={ + { .uname = "M2IOSF0_NCB", + .udesc = "M2IOSF0 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF0_NCS", + .udesc = "M2IOSF0 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF1_NCB", + .udesc = "M2IOSF1 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF1_NCS", + .udesc = "M2IOSF1 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF2_NCB", + .udesc = "M2IOSF2 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF2_NCS", + .udesc = "M2IOSF2 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF3_NCB", + .udesc = "M2IOSF3 - NCB (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF3_NCS", + .udesc = "M2IOSF3 - NCS (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_local_shar_p2p_crd_wait_1[]={ + { .uname = "M2IOSF4_NCB", + .udesc = "M2IOSF4 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF4_NCS", + .udesc = "M2IOSF4 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF5_NCB", + .udesc = "M2IOSF5 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "M2IOSF5_NCS", + .udesc = "M2IOSF5 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_misc_external[]={ + { .uname = "MBE_INST0", + .udesc = "Number of cycles MBE is high for MS2IDI0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MBE_INST1", + .udesc = "Number of cycles MBE is high for MS2IDI1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_p2p_crd_occupancy[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "LOCAL_NCB", + .udesc = "Local NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_NCS", + .udesc = "Local NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_NCB", + .udesc = "Remote NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_NCS", + .udesc = "Remote NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_p2p_shar_received[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "LOCAL_NCB", + .udesc = "Local NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_NCS", + .udesc = "Local NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_NCB", + .udesc = "Remote NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REMOTE_NCS", + .udesc = "Remote NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_p2p_ded_returned[]={ + { .uname = "UPI0_NCB", + .udesc = "UPI0 - NCB (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI0_NCS", + .udesc = "UPI0 - NCS (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCB", + .udesc = "UPI1 - NCB (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCS", + .udesc = "UPI1 - NCS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCB", + .udesc = "UPI2 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCS", + .udesc = "UPI2 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_p2p_shar_returned[]={ + { .uname = "AGENT_0", + .udesc = "Agent0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_1", + .udesc = "Agent1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_2", + .udesc = "Agent2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_shar_p2p_crd_returned[]={ + { .uname = "AGENT_0", + .udesc = "Agent0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_1", + .udesc = "Agent1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AGENT_2", + .udesc = "Agent2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_shar_p2p_crd_taken_0[]={ + { .uname = "UPI0_DRS", + .udesc = "UPI0 - DRS (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI0_NCB", + .udesc = "UPI0 - NCB (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI0_NCS", + .udesc = "UPI0 - NCS (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_DRS", + .udesc = "UPI1 - DRS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCB", + .udesc = "UPI1 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCS", + .udesc = "UPI1 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_shar_p2p_crd_taken_1[]={ + { .uname = "UPI2_DRS", + .udesc = "UPI2 - DRS (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCB", + .udesc = "UPI2 - NCB (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCS", + .udesc = "UPI2 - NCS (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_shar_p2p_crd_wait_0[]={ + { .uname = "UPI0_DRS", + .udesc = "UPI0 - DRS (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI0_NCB", + .udesc = "UPI0 - NCB (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI0_NCS", + .udesc = "UPI0 - NCS (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_DRS", + .udesc = "UPI1 - DRS (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCB", + .udesc = "UPI1 - NCB (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI1_NCS", + .udesc = "UPI1 - NCS (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_remote_shar_p2p_crd_wait_1[]={ + { .uname = "UPI2_DRS", + .udesc = "UPI2 - DRS (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCB", + .udesc = "UPI2 - NCB (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI2_NCS", + .udesc = "UPI2 - NCS (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ring_bounces_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ring_sink_starved_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "Acknowledgements to Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_ring_sink_starved_vert[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "Acknowledgements to core (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "Data Responses to core (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "Snoops of processor's cache. (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_rxc_inserts[]={ + { .uname = "ALL", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "CHA_IDI", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHA_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CHA_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UPI_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_rxr_crd_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IFV", + .udesc = "IFV - Credited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_rxr_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_rxr_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_stall0_no_txr_horz_crd_ad_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag1[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txc_credits[]={ + { .uname = "PMM", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PRQ", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txc_cycles_full[]={ + { .uname = "AD_0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_1", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_1", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_BLOCK_0", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_BLOCK_1", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txc_cycles_ne[]={ + { .uname = "AD_0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_1", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_1", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_DISTRESS_0", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_DISTRESS_1", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txc_inserts[]={ + { .uname = "AD_0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_1", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_CRD_0", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_CRD_1", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_1", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_horz_ads_used[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_horz_cycles_full[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_horz_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_horz_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_horz_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_ads_used[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_bypass[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG1", + .udesc = "IV - Agent 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_cycles_full1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_cycles_ne0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_inserts1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_occupancy0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_occupancy1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_starved0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_txr_vert_starved1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGC", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_vert_ring_akc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_vert_ring_bl_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_vert_ring_iv_in_use[]={ + { .uname = "DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m2p_vert_ring_tgc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_m2pcie_pe[]={ + { .name = "UNC_M2P_AG0_AD_CRD_ACQUIRED0", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0080, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2p_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M2P_AG0_AD_CRD_ACQUIRED1", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0081, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2p_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M2P_AG0_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0082, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_ad_crd_occupancy0), + .umasks = icx_unc_m2p_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M2P_AG0_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0083, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_ad_crd_occupancy1), + .umasks = icx_unc_m2p_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M2P_AG0_BL_CRD_ACQUIRED0", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0088, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_bl_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2p_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M2P_AG0_BL_CRD_ACQUIRED1", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0089, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2p_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M2P_AG0_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008a, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_bl_crd_occupancy0), + .umasks = icx_unc_m2p_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M2P_AG0_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008b, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag0_bl_crd_occupancy1), + .umasks = icx_unc_m2p_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M2P_AG1_AD_CRD_ACQUIRED0", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0084, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m2p_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M2P_AG1_AD_CRD_ACQUIRED1", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0085, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2p_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M2P_AG1_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0086, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_ad_crd_occupancy0), + .umasks = icx_unc_m2p_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M2P_AG1_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0087, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_ad_crd_occupancy1), + .umasks = icx_unc_m2p_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M2P_AG1_BL_CRD_ACQUIRED0", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008c, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_bl_crd_acquired0), + .umasks = icx_unc_m2p_ag1_bl_crd_acquired0, + }, + { .name = "UNC_M2P_AG1_BL_CRD_ACQUIRED1", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008d, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m2p_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M2P_AG1_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008e, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall0_no_txr_horz_crd_ad_ag0), /* shared */ + .umasks = icx_unc_m2p_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M2P_AG1_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008f, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ag1_bl_crd_occupancy1), + .umasks = icx_unc_m2p_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M2P_CLOCKTICKS", + .desc = "Clockticks of the mesh to PCI (M2P)", + .code = 0x0001, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2P_CMS_CLOCKTICKS", + .desc = "CMS Clockticks", + .code = 0x00c0, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2P_DISTRESS_ASSERTED", + .desc = "Distress signal asserted", + .code = 0x00af, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_distress_asserted), + .umasks = icx_unc_m2p_distress_asserted, + }, + { .name = "UNC_M2P_EGRESS_ORDERING", + .desc = "Egress Blocking due to Ordering requirements", + .code = 0x00ba, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_egress_ordering), + .umasks = icx_unc_m2p_egress_ordering, + }, + { .name = "UNC_M2P_HORZ_RING_AD_IN_USE", + .desc = "Horizontal AD Ring In Use", + .code = 0x00b6, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_horz_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m2p_horz_ring_akc_in_use, + }, + { .name = "UNC_M2P_HORZ_RING_AKC_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00bb, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_horz_ring_akc_in_use), + .umasks = icx_unc_m2p_horz_ring_akc_in_use, + }, + { .name = "UNC_M2P_HORZ_RING_AK_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00b7, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_horz_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m2p_horz_ring_bl_in_use, + }, + { .name = "UNC_M2P_HORZ_RING_BL_IN_USE", + .desc = "Horizontal BL Ring in Use", + .code = 0x00b8, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_horz_ring_bl_in_use), + .umasks = icx_unc_m2p_horz_ring_bl_in_use, + }, + { .name = "UNC_M2P_HORZ_RING_IV_IN_USE", + .desc = "Horizontal IV Ring in Use", + .code = 0x00b9, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_horz_ring_iv_in_use), + .umasks = icx_unc_m2p_horz_ring_iv_in_use, + }, + { .name = "UNC_M2P_IIO_CREDITS_ACQUIRED", + .desc = "M2PCIe IIO Credit Acquired", + .code = 0x0033, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_iio_credits_acquired), + .umasks = icx_unc_m2p_iio_credits_acquired, + }, + { .name = "UNC_M2P_IIO_CREDITS_REJECT", + .desc = "M2PCIe IIO Failed to Acquire a Credit", + .code = 0x0034, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_iio_credits_reject), + .umasks = icx_unc_m2p_iio_credits_reject, + }, + { .name = "UNC_M2P_IIO_CREDITS_USED", + .desc = "M2PCIe IIO Credits in Use", + .code = 0x0032, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_iio_credits_used), + .umasks = icx_unc_m2p_iio_credits_used, + }, + { .name = "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0", + .desc = "Local Dedicated P2P Credit Taken - 0", + .code = 0x0046, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_taken_0), /* shared */ + .umasks = icx_unc_m2p_local_shar_p2p_crd_taken_0, + }, + { .name = "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1", + .desc = "Local Dedicated P2P Credit Taken - 1", + .code = 0x0047, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_taken_1), /* shared */ + .umasks = icx_unc_m2p_local_shar_p2p_crd_taken_1, + }, + { .name = "UNC_M2P_LOCAL_P2P_DED_RETURNED_0", + .desc = "Local P2P Dedicated Credits Returned - 0", + .code = 0x0019, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_p2p_ded_returned_0), + .umasks = icx_unc_m2p_local_p2p_ded_returned_0, + }, + { .name = "UNC_M2P_LOCAL_P2P_DED_RETURNED_1", + .desc = "Local P2P Dedicated Credits Returned - 1", + .code = 0x001a, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_p2p_ded_returned_1), + .umasks = icx_unc_m2p_local_p2p_ded_returned_1, + }, + { .name = "UNC_M2P_LOCAL_P2P_SHAR_RETURNED", + .desc = "Local P2P Shared Credits Returned", + .code = 0x0017, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_p2p_shar_returned), /* shared */ + .umasks = icx_unc_m2p_remote_p2p_shar_returned, + }, + { .name = "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED", + .desc = "Local Shared P2P Credit Returned to credit ring", + .code = 0x0044, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_returned), + .umasks = icx_unc_m2p_local_shar_p2p_crd_returned, + }, + { .name = "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0", + .desc = "Local Shared P2P Credit Taken - 0", + .code = 0x0040, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_taken_0), + .umasks = icx_unc_m2p_local_shar_p2p_crd_taken_0, + }, + { .name = "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1", + .desc = "Local Shared P2P Credit Taken - 1", + .code = 0x0041, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_taken_1), + .umasks = icx_unc_m2p_local_shar_p2p_crd_taken_1, + }, + { .name = "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0", + .desc = "Waiting on Local Shared P2P Credit - 0", + .code = 0x004a, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_wait_0), + .umasks = icx_unc_m2p_local_shar_p2p_crd_wait_0, + }, + { .name = "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1", + .desc = "Waiting on Local Shared P2P Credit - 1", + .code = 0x004b, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_local_shar_p2p_crd_wait_1), + .umasks = icx_unc_m2p_local_shar_p2p_crd_wait_1, + }, + { .name = "UNC_M2P_MISC_EXTERNAL", + .desc = "Miscellaneous Events (mostly from MS2IDI)", + .code = 0x00e6, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_misc_external), + .umasks = icx_unc_m2p_misc_external, + }, + { .name = "UNC_M2P_P2P_CRD_OCCUPANCY", + .desc = "P2P Credit Occupancy", + .code = 0x0014, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_p2p_crd_occupancy), + .umasks = icx_unc_m2p_p2p_crd_occupancy, + }, + { .name = "UNC_M2P_P2P_DED_RECEIVED", + .desc = "Dedicated Credits Received", + .code = 0x0016, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_p2p_shar_received), /* shared */ + .umasks = icx_unc_m2p_p2p_shar_received, + }, + { .name = "UNC_M2P_P2P_SHAR_RECEIVED", + .desc = "Shared Credits Received", + .code = 0x0015, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_p2p_shar_received), + .umasks = icx_unc_m2p_p2p_shar_received, + }, + { .name = "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0", + .desc = "Remote Dedicated P2P Credit Taken - 0", + .code = 0x0048, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_taken_0), /* shared */ + .umasks = icx_unc_m2p_remote_shar_p2p_crd_taken_0, + }, + { .name = "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1", + .desc = "Remote Dedicated P2P Credit Taken - 1", + .code = 0x0049, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_taken_1), /* shared */ + .umasks = icx_unc_m2p_remote_shar_p2p_crd_taken_1, + }, + { .name = "UNC_M2P_REMOTE_P2P_DED_RETURNED", + .desc = "Remote P2P Dedicated Credits Returned", + .code = 0x001b, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_p2p_ded_returned), + .umasks = icx_unc_m2p_remote_p2p_ded_returned, + }, + { .name = "UNC_M2P_REMOTE_P2P_SHAR_RETURNED", + .desc = "Remote P2P Shared Credits Returned", + .code = 0x0018, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_p2p_shar_returned), + .umasks = icx_unc_m2p_remote_p2p_shar_returned, + }, + { .name = "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED", + .desc = "Remote Shared P2P Credit Returned to credit ring", + .code = 0x0045, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_returned), + .umasks = icx_unc_m2p_remote_shar_p2p_crd_returned, + }, + { .name = "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0", + .desc = "Remote Shared P2P Credit Taken - 0", + .code = 0x0042, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_taken_0), + .umasks = icx_unc_m2p_remote_shar_p2p_crd_taken_0, + }, + { .name = "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1", + .desc = "Remote Shared P2P Credit Taken - 1", + .code = 0x0043, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_taken_1), + .umasks = icx_unc_m2p_remote_shar_p2p_crd_taken_1, + }, + { .name = "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0", + .desc = "Waiting on Remote Shared P2P Credit - 0", + .code = 0x004c, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_wait_0), + .umasks = icx_unc_m2p_remote_shar_p2p_crd_wait_0, + }, + { .name = "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1", + .desc = "Waiting on Remote Shared P2P Credit - 1", + .code = 0x004d, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_remote_shar_p2p_crd_wait_1), + .umasks = icx_unc_m2p_remote_shar_p2p_crd_wait_1, + }, + { .name = "UNC_M2P_RING_BOUNCES_HORZ", + .desc = "Messages that bounced on the Horizontal Ring.", + .code = 0x00ac, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ring_bounces_horz), + .umasks = icx_unc_m2p_ring_bounces_horz, + }, + { .name = "UNC_M2P_RING_BOUNCES_VERT", + .desc = "Messages that bounced on the Vertical Ring.", + .code = 0x00aa, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ring_sink_starved_vert), /* shared */ + .umasks = icx_unc_m2p_ring_sink_starved_vert, + }, + { .name = "UNC_M2P_RING_SINK_STARVED_HORZ", + .desc = "Sink Starvation on Horizontal Ring", + .code = 0x00ad, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ring_sink_starved_horz), + .umasks = icx_unc_m2p_ring_sink_starved_horz, + }, + { .name = "UNC_M2P_RING_SINK_STARVED_VERT", + .desc = "Sink Starvation on Vertical Ring", + .code = 0x00ab, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_ring_sink_starved_vert), + .umasks = icx_unc_m2p_ring_sink_starved_vert, + }, + { .name = "UNC_M2P_RING_SRC_THRTL", + .desc = "Source Throttle (experimental)", + .code = 0x00ae, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2P_RxC_CYCLES_NE", + .desc = "Ingress (from CMS) Queue Cycles Not Empty", + .code = 0x0010, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxc_inserts), /* shared */ + .umasks = icx_unc_m2p_rxc_inserts, + }, + { .name = "UNC_M2P_RxC_INSERTS", + .desc = "Ingress (from CMS) Queue Inserts", + .code = 0x0011, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxc_inserts), + .umasks = icx_unc_m2p_rxc_inserts, + }, + { .name = "UNC_M2P_RxR_BUSY_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e5, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_ads_used), /* shared */ + .umasks = icx_unc_m2p_txr_horz_ads_used, + }, + { .name = "UNC_M2P_RxR_BYPASS", + .desc = "Transgress Ingress Bypass", + .code = 0x00e2, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxr_inserts), /* shared */ + .umasks = icx_unc_m2p_rxr_inserts, + }, + { .name = "UNC_M2P_RxR_CRD_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e3, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxr_crd_starved), + .umasks = icx_unc_m2p_rxr_crd_starved, + }, + { .name = "UNC_M2P_RxR_CRD_STARVED_1", + .desc = "Transgress Injection Starvation (experimental)", + .code = 0x00e4, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M2P_RxR_INSERTS", + .desc = "Transgress Ingress Allocations", + .code = 0x00e1, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxr_inserts), + .umasks = icx_unc_m2p_rxr_inserts, + }, + { .name = "UNC_M2P_RxR_OCCUPANCY", + .desc = "Transgress Ingress Occupancy", + .code = 0x00e0, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_rxr_occupancy), + .umasks = icx_unc_m2p_rxr_occupancy, + }, + { .name = "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d0, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall0_no_txr_horz_crd_ad_ag0), + .umasks = icx_unc_m2p_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d2, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag0), /* shared */ + .umasks = icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d4, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag0), + .umasks = icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d6, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag1), + .umasks = icx_unc_m2p_stall0_no_txr_horz_crd_bl_ag1, + }, + { .name = "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d1, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1), /* shared */ + .umasks = icx_unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d3, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1), + .umasks = icx_unc_m2p_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d5, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1), /* shared */ + .umasks = icx_unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d7, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1), + .umasks = icx_unc_m2p_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M2P_TxC_CREDITS", + .desc = "UNC_M2P_TxC_CREDITS.PRQ", + .code = 0x002d, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txc_credits), + .umasks = icx_unc_m2p_txc_credits, + }, + { .name = "UNC_M2P_TxC_CYCLES_FULL", + .desc = "Egress (to CMS) Cycles Full", + .code = 0x0025, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txc_cycles_full), + .umasks = icx_unc_m2p_txc_cycles_full, + }, + { .name = "UNC_M2P_TxC_CYCLES_NE", + .desc = "Egress (to CMS) Cycles Not Empty", + .code = 0x0023, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txc_cycles_ne), + .umasks = icx_unc_m2p_txc_cycles_ne, + }, + { .name = "UNC_M2P_TxC_INSERTS", + .desc = "Egress (to CMS) Ingress", + .code = 0x0024, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txc_inserts), + .umasks = icx_unc_m2p_txc_inserts, + }, + { .name = "UNC_M2P_TxR_HORZ_ADS_USED", + .desc = "CMS Horizontal ADS Used", + .code = 0x00a6, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_ads_used), + .umasks = icx_unc_m2p_txr_horz_ads_used, + }, + { .name = "UNC_M2P_TxR_HORZ_BYPASS", + .desc = "CMS Horizontal Bypass Used", + .code = 0x00a7, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_cycles_full), /* shared */ + .umasks = icx_unc_m2p_txr_horz_cycles_full, + }, + { .name = "UNC_M2P_TxR_HORZ_CYCLES_FULL", + .desc = "Cycles CMS Horizontal Egress Queue is Full", + .code = 0x00a2, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_cycles_full), + .umasks = icx_unc_m2p_txr_horz_cycles_full, + }, + { .name = "UNC_M2P_TxR_HORZ_CYCLES_NE", + .desc = "Cycles CMS Horizontal Egress Queue is Not Empty", + .code = 0x00a3, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_inserts), /* shared */ + .umasks = icx_unc_m2p_txr_horz_inserts, + }, + { .name = "UNC_M2P_TxR_HORZ_INSERTS", + .desc = "CMS Horizontal Egress Inserts", + .code = 0x00a1, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_inserts), + .umasks = icx_unc_m2p_txr_horz_inserts, + }, + { .name = "UNC_M2P_TxR_HORZ_NACK", + .desc = "CMS Horizontal Egress NACKs", + .code = 0x00a4, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_occupancy), /* shared */ + .umasks = icx_unc_m2p_txr_horz_occupancy, + }, + { .name = "UNC_M2P_TxR_HORZ_OCCUPANCY", + .desc = "CMS Horizontal Egress Occupancy", + .code = 0x00a0, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_occupancy), + .umasks = icx_unc_m2p_txr_horz_occupancy, + }, + { .name = "UNC_M2P_TxR_HORZ_STARVED", + .desc = "CMS Horizontal Egress Injection Starvation", + .code = 0x00a5, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_horz_starved), + .umasks = icx_unc_m2p_txr_horz_starved, + }, + { .name = "UNC_M2P_TxR_VERT_ADS_USED", + .desc = "CMS Vertical ADS Used", + .code = 0x009c, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_ads_used), + .umasks = icx_unc_m2p_txr_vert_ads_used, + }, + { .name = "UNC_M2P_TxR_VERT_BYPASS", + .desc = "CMS Vertical ADS Used", + .code = 0x009d, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_bypass), + .umasks = icx_unc_m2p_txr_vert_bypass, + }, + { .name = "UNC_M2P_TxR_VERT_BYPASS_1", + .desc = "CMS Vertical ADS Used", + .code = 0x009e, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_cycles_full1), /* shared */ + .umasks = icx_unc_m2p_txr_vert_cycles_full1, + }, + { .name = "UNC_M2P_TxR_VERT_CYCLES_FULL0", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0094, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_cycles_ne0), /* shared */ + .umasks = icx_unc_m2p_txr_vert_cycles_ne0, + }, + { .name = "UNC_M2P_TxR_VERT_CYCLES_FULL1", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0095, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_cycles_full1), + .umasks = icx_unc_m2p_txr_vert_cycles_full1, + }, + { .name = "UNC_M2P_TxR_VERT_CYCLES_NE0", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0096, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_cycles_ne0), + .umasks = icx_unc_m2p_txr_vert_cycles_ne0, + }, + { .name = "UNC_M2P_TxR_VERT_CYCLES_NE1", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0097, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_inserts1), /* shared */ + .umasks = icx_unc_m2p_txr_vert_inserts1, + }, + { .name = "UNC_M2P_TxR_VERT_INSERTS0", + .desc = "CMS Vert Egress Allocations", + .code = 0x0092, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_occupancy0), /* shared */ + .umasks = icx_unc_m2p_txr_vert_occupancy0, + }, + { .name = "UNC_M2P_TxR_VERT_INSERTS1", + .desc = "CMS Vert Egress Allocations", + .code = 0x0093, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_inserts1), + .umasks = icx_unc_m2p_txr_vert_inserts1, + }, + { .name = "UNC_M2P_TxR_VERT_NACK0", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0098, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_starved0), /* shared */ + .umasks = icx_unc_m2p_txr_vert_starved0, + }, + { .name = "UNC_M2P_TxR_VERT_NACK1", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0099, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_occupancy1), /* shared */ + .umasks = icx_unc_m2p_txr_vert_occupancy1, + }, + { .name = "UNC_M2P_TxR_VERT_OCCUPANCY0", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0090, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_occupancy0), + .umasks = icx_unc_m2p_txr_vert_occupancy0, + }, + { .name = "UNC_M2P_TxR_VERT_OCCUPANCY1", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0091, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_occupancy1), + .umasks = icx_unc_m2p_txr_vert_occupancy1, + }, + { .name = "UNC_M2P_TxR_VERT_STARVED0", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009a, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_starved0), + .umasks = icx_unc_m2p_txr_vert_starved0, + }, + { .name = "UNC_M2P_TxR_VERT_STARVED1", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009b, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_txr_vert_starved1), + .umasks = icx_unc_m2p_txr_vert_starved1, + }, + { .name = "UNC_M2P_VERT_RING_AD_IN_USE", + .desc = "Vertical AD Ring In Use", + .code = 0x00b0, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m2p_vert_ring_akc_in_use, + }, + { .name = "UNC_M2P_VERT_RING_AKC_IN_USE", + .desc = "Vertical AKC Ring In Use", + .code = 0x00b4, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_akc_in_use), + .umasks = icx_unc_m2p_vert_ring_akc_in_use, + }, + { .name = "UNC_M2P_VERT_RING_AK_IN_USE", + .desc = "Vertical AK Ring In Use", + .code = 0x00b1, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m2p_vert_ring_bl_in_use, + }, + { .name = "UNC_M2P_VERT_RING_BL_IN_USE", + .desc = "Vertical BL Ring in Use", + .code = 0x00b2, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_bl_in_use), + .umasks = icx_unc_m2p_vert_ring_bl_in_use, + }, + { .name = "UNC_M2P_VERT_RING_IV_IN_USE", + .desc = "Vertical IV Ring in Use", + .code = 0x00b3, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_iv_in_use), + .umasks = icx_unc_m2p_vert_ring_iv_in_use, + }, + { .name = "UNC_M2P_VERT_RING_TGC_IN_USE", + .desc = "Vertical TGC Ring In Use", + .code = 0x00b5, + .modmsk = ICX_UNC_M2PCIE_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m2p_vert_ring_tgc_in_use), + .umasks = icx_unc_m2p_vert_ring_tgc_in_use, + }, +}; +/* 105 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_m3upi_events.h b/src/libpfm4/lib/events/intel_icx_unc_m3upi_events.h new file mode 100644 index 000000000..a332952bf --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_m3upi_events.h @@ -0,0 +1,3985 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_m3upi (IcelakeX Uncore M3UPI) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_m3upi_ag0_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag0_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag0_bl_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag0_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag1_ad_crd_occupancy0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag1_ad_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag1_bl_crd_acquired0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ag1_bl_crd_occupancy1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_cha_ad_credits_empty[]={ + { .uname = "REQ", + .udesc = "Requests (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Snoops (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VNA", + .udesc = "VNA Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB", + .udesc = "Writebacks (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_distress_asserted[]={ + { .uname = "DPT_LOCAL", + .udesc = "DPT Local (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_NONLOCAL", + .udesc = "DPT Remote (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_IV", + .udesc = "DPT Stalled - IV (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DPT_STALL_NOCRD", + .udesc = "DPT Stalled - No Credit (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "HORZ", + .udesc = "Horizontal (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_LOCAL", + .udesc = "PMM Local (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PMM_NONLOCAL", + .udesc = "PMM Remote (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VERT", + .udesc = "Vertical (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_egress_ordering[]={ + { .uname = "IV_SNOOPGO_DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_SNOOPGO_UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_horz_ring_akc_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_horz_ring_bl_in_use[]={ + { .uname = "LEFT_EVEN", + .udesc = "Left and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LEFT_ODD", + .udesc = "Left and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_EVEN", + .udesc = "Right and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT_ODD", + .udesc = "Right and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_horz_ring_iv_in_use[]={ + { .uname = "LEFT", + .udesc = "Left (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RIGHT", + .udesc = "Right (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_m2_bl_credits_empty[]={ + { .uname = "IIO1_NCB", + .udesc = "IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO2_NCB", + .udesc = "IIO2 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO3_NCB", + .udesc = "IIO3 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO4_NCB", + .udesc = "IIO4 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IIO5_NCB", + .udesc = "IIO5 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "All IIO targets for NCS are in single mask. ORs them together (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_SEL", + .udesc = "Selected M2p BL NCS credits (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UBOX_NCB", + .udesc = "IIO5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_misc_external[]={ + { .uname = "MBE_INST0", + .udesc = "Number of cycles MBE is high for MS2IDI0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MBE_INST1", + .udesc = "Number of cycles MBE is high for MS2IDI1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_multi_slot_rcvd[]={ + { .uname = "AD_SLOT0", + .udesc = "AD - Slot 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SLOT1", + .udesc = "AD - Slot 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SLOT2", + .udesc = "AD - Slot 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_SLOT0", + .udesc = "AK - Slot 0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_SLOT2", + .udesc = "AK - Slot 2 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_SLOT0", + .udesc = "BL - Slot 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ring_bounces_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ring_sink_starved_horz[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "Acknowledgements to Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "BL (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_ring_sink_starved_vert[]={ + { .uname = "AD", + .udesc = "AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "Acknowledgements to core (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL", + .udesc = "Data Responses to core (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "Snoops of processor's cache. (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_arb_lost_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_arb_misc[]={ + { .uname = "ADBL_PARALLEL_WIN_VN0", + .udesc = "AD, BL Parallel Win VN0 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ADBL_PARALLEL_WIN_VN1", + .udesc = "AD, BL Parallel Win VN1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_PARALLEL_WIN", + .udesc = "Max Parallel Win (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_PROG_AD_VN0", + .udesc = "No Progress on Pending AD VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_PROG_AD_VN1", + .udesc = "No Progress on Pending AD VN1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_PROG_BL_VN0", + .udesc = "No Progress on Pending BL VN0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_PROG_BL_VN1", + .udesc = "No Progress on Pending BL VN1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN01_PARALLEL_WIN", + .udesc = "VN0, VN1 Parallel Win (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_arb_nocrd_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_arb_noreq_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_bypassed[]={ + { .uname = "AD_S0_BL_ARB", + .udesc = "AD to Slot 0 on BL Arb (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_S0_IDLE", + .udesc = "AD to Slot 0 on Idle (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_S1_BL_SLOT", + .udesc = "AD + BL to Slot 1 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_S2_BL_SLOT", + .udesc = "AD + BL to Slot 2 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_crd_misc[]={ + { .uname = "ANY_BGF_FIFO", + .udesc = "Any In BGF FIFO (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ANY_BGF_PATH", + .udesc = "Any in BGF Path (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT1_FOR_D2K", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT2_FOR_D2K", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_NO_D2K_FOR_ARB", + .udesc = "No D2K For Arb (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NO_D2K_FOR_ARB", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_crd_occ[]={ + { .uname = "CONSUMED", + .udesc = "Credits Consumed (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "D2K_CRD", + .udesc = "D2K Credits (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLITS_IN_FIFO", + .udesc = "Packets in BGF FIFO (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLITS_IN_PATH", + .udesc = "Packets in BGF Path (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_FIFO", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_TOTAL", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxQ_CRD", + .udesc = "Transmit Credits (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VNA_IN_USE", + .udesc = "VNA In Use (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_cycles_ne_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_data_flits_not_sent[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO | INTEL_X86_DFL, + }, + { .uname = "NO_BGF", + .udesc = "No BGF Credits (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_TXQ", + .udesc = "No TxQ Credits (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TSV_HI", + .udesc = "TSV High (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VALID_FOR_FLIT", + .udesc = "Cycle valid for Flit (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_flits_gen_bl[]={ + { .uname = "P0_WAIT", + .udesc = "Wait on Pump 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_AT_LIMIT", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_BUSY", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_FIFO_FULL", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_HOLD_P0", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1P_TO_LIMBO", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1_WAIT", + .udesc = "Wait on Pump 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_flits_misc[]={ + { .uname = "S2REQ_IN_HOLDOFF", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S2REQ_IN_SERVICE", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S2REQ_RECEIVED", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S2REQ_WITHDRAWN", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_flits_slot_bl[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NEED_DATA", + .udesc = "Needs Data Flit (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P0_WAIT", + .udesc = "Wait on Pump 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1_NOT_REQ", + .udesc = "Don't Need Pump 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1_NOT_REQ_BUT_BUBBLE", + .udesc = "Don't Need Pump 1 - Bubble (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1_NOT_REQ_NOT_AVAIL", + .udesc = "Don't Need Pump 1 - Not Avail (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "P1_WAIT", + .udesc = "Wait on Pump 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_flit_gen_hdr1[]={ + { .uname = "ACCUM", + .udesc = "Accumulate (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ACCUM_READ", + .udesc = "Accumulate Ready (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ACCUM_WASTED", + .udesc = "Accumulate Wasted (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AHEAD_BLOCKED", + .udesc = "Run-Ahead - Blocked (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AHEAD_MSG1_AFTER", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AHEAD_MSG1_DURING", + .udesc = "Run-Ahead - Message (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AHEAD_MSG2_AFTER", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AHEAD_MSG2_SENT", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_flit_gen_hdr2[]={ + { .uname = "PAR", + .udesc = "Parallel Ok (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PAR_FLIT", + .udesc = "Parallel Flit Finished (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PAR_MSG", + .udesc = "Parallel Message (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RMSTALL", + .udesc = "Rate-matching Stall (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RMSTALL_NOMSG", + .udesc = "Rate-matching Stall - No Message (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_hdr_flits_sent[]={ + { .uname = "1_MSG", + .udesc = "One Message (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "1_MSG_VNX", + .udesc = "One Message in non-VNA (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "2_MSGS", + .udesc = "Two Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "3_MSGS", + .udesc = "Three Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOTS_1", + .udesc = "One Slot Taken (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOTS_2", + .udesc = "Two Slots Taken (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOTS_3", + .udesc = "All Slots Taken (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_hdr_flit_not_sent[]={ + { .uname = "ALL", + .udesc = "All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_BGF_CRD", + .udesc = "No BGF Credits (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_BGF_NO_MSG", + .udesc = "No BGF Credits + No Extra Message Slotted (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_TXQ_CRD", + .udesc = "No TxQ Credits (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NO_TXQ_NO_MSG", + .udesc = "No TxQ Credits + No Extra Message Slotted (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TSV_HI", + .udesc = "TSV High (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VALID_FOR_FLIT", + .udesc = "Cycle valid for Flit (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_held[]={ + { .uname = "CANT_SLOT_AD", + .udesc = "Can't Slot AD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CANT_SLOT_BL", + .udesc = "Can't Slot BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARALLEL_ATTEMPT", + .udesc = "Parallel Attempt (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PARALLEL_SUCCESS", + .udesc = "Parallel Success (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0", + .udesc = "VN0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1", + .udesc = "VN1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_inserts_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_occupancy_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_packing_miss_vn1[]={ + { .uname = "AD_REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCB", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_NCS", + .udesc = "NCS on BL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_RSP", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_WB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_vna_crd[]={ + { .uname = "ANY_IN_USE", + .udesc = "Any In Use (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORRECTED", + .udesc = "Corrected (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT1", + .udesc = "Level < 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT10", + .udesc = "Level < 10 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT4", + .udesc = "Level < 4 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LT5", + .udesc = "Level < 5 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxc_vna_crd_misc[]={ + { .uname = "REQ_ADBL_ALLOC_L5", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_VN01_ALLOC_LT10", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_JUST_AD", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_JUST_BL", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_ONLY", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_JUST_AD", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_JUST_BL", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_ONLY", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxr_crd_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IFV", + .udesc = "IFV - Credited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxr_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_rxr_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_stall0_no_txr_horz_crd_ad_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag0[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag1[]={ + { .uname = "TGR0", + .udesc = "For Transgress 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR1", + .udesc = "For Transgress 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR2", + .udesc = "For Transgress 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR3", + .udesc = "For Transgress 3 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR4", + .udesc = "For Transgress 4 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR5", + .udesc = "For Transgress 5 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR6", + .udesc = "For Transgress 6 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR7", + .udesc = "For Transgress 7 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1[]={ + { .uname = "TGR10", + .udesc = "For Transgress 10 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR8", + .udesc = "For Transgress 8 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGR9", + .udesc = "For Transgress 9 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_ad_flq_bypass[]={ + { .uname = "AD_SLOT0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SLOT1", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_SLOT2", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_EARLY_RSP", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_ad_flq_cycles_ne[]={ + { .uname = "VN0_REQ", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_SNP", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_REQ", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_SNP", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_ad_flq_inserts[]={ + { .uname = "VN0_REQ", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_SNP", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_REQ", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_SNP", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_ad_flq_occupancy[]={ + { .uname = "VN0_REQ", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_SNP", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_REQ", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_SNP", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_bl_arb_fail[]={ + { .uname = "VN0_NCB", + .udesc = "VN0 NCB Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_NCS", + .udesc = "VN0 NCS Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCB", + .udesc = "VN1 NCS Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCS", + .udesc = "VN1 NCB Messages (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_bl_flq_cycles_ne[]={ + { .uname = "VN0_REQ", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_SNP", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_REQ", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_SNP", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_bl_flq_inserts[]={ + { .uname = "VN0_NCB", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_NCS", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 NCS Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 NCB Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCB", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCS", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1_NCB Messages (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1_NCS Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_bl_flq_occupancy[]={ + { .uname = "VN0_NCB", + .udesc = "VN0 NCB Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_NCS", + .udesc = "VN0 NCS Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCB", + .udesc = "VN1_NCS Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCS", + .udesc = "VN1_NCB Messages (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txc_bl_wb_flq_occupancy[]={ + { .uname = "VN0_LOCAL", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_THROUGH", + .udesc = "VN0 WB Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WRPULL", + .udesc = "VN0 NCB Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_LOCAL", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_THROUGH", + .udesc = "VN1 WB Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WRPULL", + .udesc = "VN1_NCS Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_horz_ads_used[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_horz_cycles_full[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_horz_inserts[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_horz_occupancy[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x1100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_CRD", + .udesc = "AD - Credited (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x4400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_CRD", + .udesc = "BL - Credited (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_horz_starved[]={ + { .uname = "AD_ALL", + .udesc = "AD - All (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_UNCRD", + .udesc = "AD - Uncredited (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK", + .udesc = "AK (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_UNCRD", + .udesc = "AKC - Uncredited (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_ALL", + .udesc = "BL - All (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_UNCRD", + .udesc = "BL - Uncredited (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_ads_used[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_bypass[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG1", + .udesc = "IV - Agent 1 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_cycles_full1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_cycles_ne0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_inserts1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_occupancy0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV - Agent 0 (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_occupancy1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_starved0[]={ + { .uname = "AD_AG0", + .udesc = "AD - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_AG1", + .udesc = "AD - Agent 1 (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG0", + .udesc = "AK - Agent 0 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_AG1", + .udesc = "AK - Agent 1 (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG0", + .udesc = "BL - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_AG1", + .udesc = "BL - Agent 1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IV_AG0", + .udesc = "IV (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_txr_vert_starved1[]={ + { .uname = "AKC_AG0", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AKC_AG1", + .udesc = "AKC - Agent 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TGC", + .udesc = "AKC - Agent 0 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_upi_peer_ad_credits_empty[]={ + { .uname = "VN0_REQ", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_SNP", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_REQ", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_SNP", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VNA", + .udesc = "VNA (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_upi_peer_bl_credits_empty[]={ + { .uname = "VN0_NCS_NCB", + .udesc = "VN0 RSP Messages (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_RSP", + .udesc = "VN0 REQ Messages (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0_WB", + .udesc = "VN0 SNP Messages (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_NCS_NCB", + .udesc = "VN1 RSP Messages (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_RSP", + .udesc = "VN1 REQ Messages (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1_WB", + .udesc = "VN1 SNP Messages (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VNA", + .udesc = "VNA (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vert_ring_akc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vert_ring_bl_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vert_ring_iv_in_use[]={ + { .uname = "DN", + .udesc = "Down (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP", + .udesc = "Up (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vert_ring_tgc_in_use[]={ + { .uname = "DN_EVEN", + .udesc = "Down and Even (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DN_ODD", + .udesc = "Down and Odd (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_EVEN", + .udesc = "Up and Even (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "UP_ODD", + .udesc = "Up and Odd (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vn0_no_credits[]={ + { .uname = "NCB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_vn1_no_credits[]={ + { .uname = "NCB", + .udesc = "WB on BL (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "NCB on BL (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ", + .udesc = "REQ on AD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP", + .udesc = "RSP on AD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "SNP on AD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB", + .udesc = "RSP on BL (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_wb_occ_compare[]={ + { .uname = "BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x8200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0xa000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BOTHNONZERO_RT_GT_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x8100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BOTHNONZERO_RT_GT_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x9000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BOTHNONZERO_RT_LT_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x8400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BOTHNONZERO_RT_LT_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0xc000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_EQ_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_EQ_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_GT_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_GT_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_LT_LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RT_LT_LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_wb_pending[]={ + { .uname = "LOCALDEST_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCALDEST_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_AND_RT_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOCAL_AND_RT_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ROUTETHRU_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ROUTETHRU_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WAITING4PULL_VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WAITING4PULL_VN1", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_m3upi_xpt_pftch[]={ + { .uname = "ARB", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ARRIVED", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BYPASS", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLITTED", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOST_ARB", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOST_OLD", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LOST_QFULL", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_m3upi_pe[]={ + { .name = "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0080, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m3upi_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1", + .desc = "CMS Agent0 AD Credits Acquired", + .code = 0x0081, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m3upi_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0082, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_ad_crd_occupancy0), + .umasks = icx_unc_m3upi_ag0_ad_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent0 AD Credits Occupancy", + .code = 0x0083, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_ad_crd_occupancy1), + .umasks = icx_unc_m3upi_ag0_ad_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0088, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_bl_crd_occupancy0), /* shared */ + .umasks = icx_unc_m3upi_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1", + .desc = "CMS Agent0 BL Credits Acquired", + .code = 0x0089, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m3upi_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008a, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_bl_crd_occupancy0), + .umasks = icx_unc_m3upi_ag0_bl_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent0 BL Credits Occupancy", + .code = 0x008b, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag0_bl_crd_occupancy1), + .umasks = icx_unc_m3upi_ag0_bl_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0084, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_ad_crd_occupancy0), /* shared */ + .umasks = icx_unc_m3upi_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1", + .desc = "CMS Agent1 AD Credits Acquired", + .code = 0x0085, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_ad_crd_occupancy1), /* shared */ + .umasks = icx_unc_m3upi_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0086, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_ad_crd_occupancy0), + .umasks = icx_unc_m3upi_ag1_ad_crd_occupancy0, + }, + { .name = "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1", + .desc = "CMS Agent1 AD Credits Occupancy", + .code = 0x0087, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_ad_crd_occupancy1), + .umasks = icx_unc_m3upi_ag1_ad_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_bl_crd_acquired0), + .umasks = icx_unc_m3upi_ag1_bl_crd_acquired0, + }, + { .name = "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1", + .desc = "CMS Agent1 BL Credits Acquired", + .code = 0x008d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_bl_crd_occupancy1), /* shared */ + .umasks = icx_unc_m3upi_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall0_no_txr_horz_crd_ad_ag0), /* shared */ + .umasks = icx_unc_m3upi_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1", + .desc = "CMS Agent1 BL Credits Occupancy", + .code = 0x008f, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ag1_bl_crd_occupancy1), + .umasks = icx_unc_m3upi_ag1_bl_crd_occupancy1, + }, + { .name = "UNC_M3UPI_CHA_AD_CREDITS_EMPTY", + .desc = "CBox AD Credits Empty", + .code = 0x0022, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_cha_ad_credits_empty), + .umasks = icx_unc_m3upi_cha_ad_credits_empty, + }, + { .name = "UNC_M3UPI_CLOCKTICKS", + .desc = "Clockticks of the mesh to UPI (M3UPI)", + .code = 0x0001, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_CMS_CLOCKTICKS", + .desc = "CMS Clockticks (experimental)", + .code = 0x00c0, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_D2C_SENT", + .desc = "D2C Sent (experimental)", + .code = 0x002b, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_D2U_SENT", + .desc = "D2U Sent (experimental)", + .code = 0x002a, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_DISTRESS_ASSERTED", + .desc = "Distress signal asserted", + .code = 0x00af, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_distress_asserted), + .umasks = icx_unc_m3upi_distress_asserted, + }, + { .name = "UNC_M3UPI_EGRESS_ORDERING", + .desc = "Egress Blocking due to Ordering requirements", + .code = 0x00ba, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_egress_ordering), + .umasks = icx_unc_m3upi_egress_ordering, + }, + { .name = "UNC_M3UPI_HORZ_RING_AD_IN_USE", + .desc = "Horizontal AD Ring In Use", + .code = 0x00b6, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_horz_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m3upi_horz_ring_akc_in_use, + }, + { .name = "UNC_M3UPI_HORZ_RING_AKC_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00bb, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_horz_ring_akc_in_use), + .umasks = icx_unc_m3upi_horz_ring_akc_in_use, + }, + { .name = "UNC_M3UPI_HORZ_RING_AK_IN_USE", + .desc = "Horizontal AK Ring In Use", + .code = 0x00b7, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_horz_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m3upi_horz_ring_bl_in_use, + }, + { .name = "UNC_M3UPI_HORZ_RING_BL_IN_USE", + .desc = "Horizontal BL Ring in Use", + .code = 0x00b8, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_horz_ring_bl_in_use), + .umasks = icx_unc_m3upi_horz_ring_bl_in_use, + }, + { .name = "UNC_M3UPI_HORZ_RING_IV_IN_USE", + .desc = "Horizontal IV Ring in Use", + .code = 0x00b9, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_horz_ring_iv_in_use), + .umasks = icx_unc_m3upi_horz_ring_iv_in_use, + }, + { .name = "UNC_M3UPI_M2_BL_CREDITS_EMPTY", + .desc = "M2 BL Credits Empty", + .code = 0x0023, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_m2_bl_credits_empty), + .umasks = icx_unc_m3upi_m2_bl_credits_empty, + }, + { .name = "UNC_M3UPI_MISC_EXTERNAL", + .desc = "Miscellaneous Events (mostly from MS2IDI)", + .code = 0x00e6, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_misc_external), + .umasks = icx_unc_m3upi_misc_external, + }, + { .name = "UNC_M3UPI_MULTI_SLOT_RCVD", + .desc = "Multi Slot Flit Received", + .code = 0x003e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_multi_slot_rcvd), + .umasks = icx_unc_m3upi_multi_slot_rcvd, + }, + { .name = "UNC_M3UPI_RING_BOUNCES_HORZ", + .desc = "Messages that bounced on the Horizontal Ring.", + .code = 0x00ac, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ring_bounces_horz), + .umasks = icx_unc_m3upi_ring_bounces_horz, + }, + { .name = "UNC_M3UPI_RING_BOUNCES_VERT", + .desc = "Messages that bounced on the Vertical Ring.", + .code = 0x00aa, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ring_sink_starved_vert), /* shared */ + .umasks = icx_unc_m3upi_ring_sink_starved_vert, + }, + { .name = "UNC_M3UPI_RING_SINK_STARVED_HORZ", + .desc = "Sink Starvation on Horizontal Ring", + .code = 0x00ad, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ring_sink_starved_horz), + .umasks = icx_unc_m3upi_ring_sink_starved_horz, + }, + { .name = "UNC_M3UPI_RING_SINK_STARVED_VERT", + .desc = "Sink Starvation on Vertical Ring", + .code = 0x00ab, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_ring_sink_starved_vert), + .umasks = icx_unc_m3upi_ring_sink_starved_vert, + }, + { .name = "UNC_M3UPI_RING_SRC_THRTL", + .desc = "Source Throttle (experimental)", + .code = 0x00ae, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_RxC_ARB_LOST_VN0", + .desc = "Lost Arb for VN0", + .code = 0x004b, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_lost_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_arb_lost_vn1, + }, + { .name = "UNC_M3UPI_RxC_ARB_LOST_VN1", + .desc = "Lost Arb for VN1", + .code = 0x004c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_lost_vn1), + .umasks = icx_unc_m3upi_rxc_arb_lost_vn1, + }, + { .name = "UNC_M3UPI_RxC_ARB_MISC", + .desc = "Arb Miscellaneous", + .code = 0x004d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_misc), + .umasks = icx_unc_m3upi_rxc_arb_misc, + }, + { .name = "UNC_M3UPI_RxC_ARB_NOCRD_VN0", + .desc = "No Credits to Arb for VN0", + .code = 0x0047, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_nocrd_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_arb_nocrd_vn1, + }, + { .name = "UNC_M3UPI_RxC_ARB_NOCRD_VN1", + .desc = "No Credits to Arb for VN1", + .code = 0x0048, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_nocrd_vn1), + .umasks = icx_unc_m3upi_rxc_arb_nocrd_vn1, + }, + { .name = "UNC_M3UPI_RxC_ARB_NOREQ_VN0", + .desc = "Can't Arb for VN0", + .code = 0x0049, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_noreq_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_arb_noreq_vn1, + }, + { .name = "UNC_M3UPI_RxC_ARB_NOREQ_VN1", + .desc = "Can't Arb for VN1", + .code = 0x004a, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_arb_noreq_vn1), + .umasks = icx_unc_m3upi_rxc_arb_noreq_vn1, + }, + { .name = "UNC_M3UPI_RxC_BYPASSED", + .desc = "Ingress Queue Bypasses", + .code = 0x0040, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x7ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_bypassed), + .umasks = icx_unc_m3upi_rxc_bypassed, + }, + { .name = "UNC_M3UPI_RxC_CRD_MISC", + .desc = "Miscellaneous Credit Events", + .code = 0x005f, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_crd_misc), + .umasks = icx_unc_m3upi_rxc_crd_misc, + }, + { .name = "UNC_M3UPI_RxC_CRD_OCC", + .desc = "Credit Occupancy", + .code = 0x0060, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_crd_occ), + .umasks = icx_unc_m3upi_rxc_crd_occ, + }, + { .name = "UNC_M3UPI_RxC_CYCLES_NE_VN0", + .desc = "VN0 Ingress (from CMS) Queue - Cycles Not Empty", + .code = 0x0043, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_cycles_ne_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_cycles_ne_vn1, + }, + { .name = "UNC_M3UPI_RxC_CYCLES_NE_VN1", + .desc = "VN1 Ingress (from CMS) Queue - Cycles Not Empty", + .code = 0x0044, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_cycles_ne_vn1), + .umasks = icx_unc_m3upi_rxc_cycles_ne_vn1, + }, + { .name = "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT", + .desc = "Data Flit Not Sent", + .code = 0x0055, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_data_flits_not_sent), + .umasks = icx_unc_m3upi_rxc_data_flits_not_sent, + }, + { .name = "UNC_M3UPI_RxC_FLITS_GEN_BL", + .desc = "Generating BL Data Flit Sequence", + .code = 0x0057, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_flits_gen_bl), + .umasks = icx_unc_m3upi_rxc_flits_gen_bl, + }, + { .name = "UNC_M3UPI_RxC_FLITS_MISC", + .desc = "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + .code = 0x0058, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_flits_misc), + .umasks = icx_unc_m3upi_rxc_flits_misc, + }, + { .name = "UNC_M3UPI_RxC_FLITS_SLOT_BL", + .desc = "Slotting BL Message Into Header Flit", + .code = 0x0056, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_flits_slot_bl), + .umasks = icx_unc_m3upi_rxc_flits_slot_bl, + }, + { .name = "UNC_M3UPI_RxC_FLIT_GEN_HDR1", + .desc = "Flit Gen - Header 1", + .code = 0x0051, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_flit_gen_hdr1), + .umasks = icx_unc_m3upi_rxc_flit_gen_hdr1, + }, + { .name = "UNC_M3UPI_RxC_FLIT_GEN_HDR2", + .desc = "Flit Gen - Header 2", + .code = 0x0052, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_flit_gen_hdr2), + .umasks = icx_unc_m3upi_rxc_flit_gen_hdr2, + }, + { .name = "UNC_M3UPI_RxC_HDR_FLITS_SENT", + .desc = "Sent Header Flit", + .code = 0x0054, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_hdr_flits_sent), + .umasks = icx_unc_m3upi_rxc_hdr_flits_sent, + }, + { .name = "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT", + .desc = "Header Not Sent", + .code = 0x0053, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_hdr_flit_not_sent), + .umasks = icx_unc_m3upi_rxc_hdr_flit_not_sent, + }, + { .name = "UNC_M3UPI_RxC_HELD", + .desc = "Message Held", + .code = 0x0050, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x7ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_held), + .umasks = icx_unc_m3upi_rxc_held, + }, + { .name = "UNC_M3UPI_RxC_INSERTS_VN0", + .desc = "VN0 Ingress (from CMS) Queue - Inserts", + .code = 0x0041, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_inserts_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_inserts_vn1, + }, + { .name = "UNC_M3UPI_RxC_INSERTS_VN1", + .desc = "VN1 Ingress (from CMS) Queue - Inserts", + .code = 0x0042, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_inserts_vn1), + .umasks = icx_unc_m3upi_rxc_inserts_vn1, + }, + { .name = "UNC_M3UPI_RxC_OCCUPANCY_VN0", + .desc = "VN0 Ingress (from CMS) Queue - Occupancy", + .code = 0x0045, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_occupancy_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_occupancy_vn1, + }, + { .name = "UNC_M3UPI_RxC_OCCUPANCY_VN1", + .desc = "VN1 Ingress (from CMS) Queue - Occupancy", + .code = 0x0046, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_occupancy_vn1), + .umasks = icx_unc_m3upi_rxc_occupancy_vn1, + }, + { .name = "UNC_M3UPI_RxC_PACKING_MISS_VN0", + .desc = "VN0 message can't slot into flit", + .code = 0x004e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x7ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_packing_miss_vn1), /* shared */ + .umasks = icx_unc_m3upi_rxc_packing_miss_vn1, + }, + { .name = "UNC_M3UPI_RxC_PACKING_MISS_VN1", + .desc = "VN1 message can't slot into flit", + .code = 0x004f, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x7ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_packing_miss_vn1), + .umasks = icx_unc_m3upi_rxc_packing_miss_vn1, + }, + { .name = "UNC_M3UPI_RxC_VNA_CRD", + .desc = "Remote VNA Credits", + .code = 0x005a, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_vna_crd), + .umasks = icx_unc_m3upi_rxc_vna_crd, + }, + { .name = "UNC_M3UPI_RxC_VNA_CRD_MISC", + .desc = "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + .code = 0x0059, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxc_vna_crd_misc), + .umasks = icx_unc_m3upi_rxc_vna_crd_misc, + }, + { .name = "UNC_M3UPI_RxR_BUSY_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e5, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_ads_used), /* shared */ + .umasks = icx_unc_m3upi_txr_horz_ads_used, + }, + { .name = "UNC_M3UPI_RxR_BYPASS", + .desc = "Transgress Ingress Bypass", + .code = 0x00e2, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxr_inserts), /* shared */ + .umasks = icx_unc_m3upi_rxr_inserts, + }, + { .name = "UNC_M3UPI_RxR_CRD_STARVED", + .desc = "Transgress Injection Starvation", + .code = 0x00e3, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxr_crd_starved), + .umasks = icx_unc_m3upi_rxr_crd_starved, + }, + { .name = "UNC_M3UPI_RxR_CRD_STARVED_1", + .desc = "Transgress Injection Starvation (experimental)", + .code = 0x00e4, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_RxR_INSERTS", + .desc = "Transgress Ingress Allocations", + .code = 0x00e1, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxr_inserts), + .umasks = icx_unc_m3upi_rxr_inserts, + }, + { .name = "UNC_M3UPI_RxR_OCCUPANCY", + .desc = "Transgress Ingress Occupancy", + .code = 0x00e0, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_rxr_occupancy), + .umasks = icx_unc_m3upi_rxr_occupancy, + }, + { .name = "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d0, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall0_no_txr_horz_crd_ad_ag0), + .umasks = icx_unc_m3upi_stall0_no_txr_horz_crd_ad_ag0, + }, + { .name = "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d2, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag0), /* shared */ + .umasks = icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d4, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag0), + .umasks = icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag0, + }, + { .name = "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d6, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag1), + .umasks = icx_unc_m3upi_stall0_no_txr_horz_crd_bl_ag1, + }, + { .name = "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0", + .desc = "Stall on No AD Agent0 Transgress Credits", + .code = 0x00d1, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1), /* shared */ + .umasks = icx_unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1", + .desc = "Stall on No AD Agent1 Transgress Credits", + .code = 0x00d3, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1), + .umasks = icx_unc_m3upi_stall1_no_txr_horz_crd_ad_ag1_1, + }, + { .name = "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1", + .desc = "Stall on No BL Agent0 Transgress Credits", + .code = 0x00d5, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1), /* shared */ + .umasks = icx_unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1", + .desc = "Stall on No BL Agent1 Transgress Credits", + .code = 0x00d7, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1), + .umasks = icx_unc_m3upi_stall1_no_txr_horz_crd_bl_ag1_1, + }, + { .name = "UNC_M3UPI_TxC_AD_ARB_FAIL", + .desc = "Failed ARB for AD", + .code = 0x0030, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_ad_flq_cycles_ne), /* shared */ + .umasks = icx_unc_m3upi_txc_ad_flq_cycles_ne, + }, + { .name = "UNC_M3UPI_TxC_AD_FLQ_BYPASS", + .desc = "AD FlowQ Bypass", + .code = 0x002c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_ad_flq_bypass), + .umasks = icx_unc_m3upi_txc_ad_flq_bypass, + }, + { .name = "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE", + .desc = "AD Flow Q Not Empty", + .code = 0x0027, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_ad_flq_cycles_ne), + .umasks = icx_unc_m3upi_txc_ad_flq_cycles_ne, + }, + { .name = "UNC_M3UPI_TxC_AD_FLQ_INSERTS", + .desc = "AD Flow Q Inserts", + .code = 0x002d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_ad_flq_inserts), + .umasks = icx_unc_m3upi_txc_ad_flq_inserts, + }, + { .name = "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY", + .desc = "AD Flow Q Occupancy", + .code = 0x001c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x1ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_ad_flq_occupancy), + .umasks = icx_unc_m3upi_txc_ad_flq_occupancy, + }, + { .name = "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + .desc = "AK Flow Q Inserts (experimental)", + .code = 0x002f, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + .desc = "AK Flow Q Occupancy (experimental)", + .code = 0x001e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x1ull, + }, + { .name = "UNC_M3UPI_TxC_BL_ARB_FAIL", + .desc = "Failed ARB for BL", + .code = 0x0035, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_bl_arb_fail), + .umasks = icx_unc_m3upi_txc_bl_arb_fail, + }, + { .name = "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE", + .desc = "BL Flow Q Not Empty", + .code = 0x0028, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_bl_flq_cycles_ne), + .umasks = icx_unc_m3upi_txc_bl_flq_cycles_ne, + }, + { .name = "UNC_M3UPI_TxC_BL_FLQ_INSERTS", + .desc = "BL Flow Q Inserts", + .code = 0x002e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_bl_flq_inserts), + .umasks = icx_unc_m3upi_txc_bl_flq_inserts, + }, + { .name = "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY", + .desc = "BL Flow Q Occupancy", + .code = 0x001d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x1ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_bl_flq_occupancy), + .umasks = icx_unc_m3upi_txc_bl_flq_occupancy, + }, + { .name = "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY", + .desc = "BL Flow Q Occupancy", + .code = 0x001f, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0x1ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txc_bl_wb_flq_occupancy), + .umasks = icx_unc_m3upi_txc_bl_wb_flq_occupancy, + }, + { .name = "UNC_M3UPI_TxR_HORZ_ADS_USED", + .desc = "CMS Horizontal ADS Used", + .code = 0x00a6, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_ads_used), + .umasks = icx_unc_m3upi_txr_horz_ads_used, + }, + { .name = "UNC_M3UPI_TxR_HORZ_BYPASS", + .desc = "CMS Horizontal Bypass Used", + .code = 0x00a7, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_cycles_full), /* shared */ + .umasks = icx_unc_m3upi_txr_horz_cycles_full, + }, + { .name = "UNC_M3UPI_TxR_HORZ_CYCLES_FULL", + .desc = "Cycles CMS Horizontal Egress Queue is Full", + .code = 0x00a2, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_cycles_full), + .umasks = icx_unc_m3upi_txr_horz_cycles_full, + }, + { .name = "UNC_M3UPI_TxR_HORZ_CYCLES_NE", + .desc = "Cycles CMS Horizontal Egress Queue is Not Empty", + .code = 0x00a3, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_inserts), /* shared */ + .umasks = icx_unc_m3upi_txr_horz_inserts, + }, + { .name = "UNC_M3UPI_TxR_HORZ_INSERTS", + .desc = "CMS Horizontal Egress Inserts", + .code = 0x00a1, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_inserts), + .umasks = icx_unc_m3upi_txr_horz_inserts, + }, + { .name = "UNC_M3UPI_TxR_HORZ_NACK", + .desc = "CMS Horizontal Egress NACKs", + .code = 0x00a4, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_occupancy), /* shared */ + .umasks = icx_unc_m3upi_txr_horz_occupancy, + }, + { .name = "UNC_M3UPI_TxR_HORZ_OCCUPANCY", + .desc = "CMS Horizontal Egress Occupancy", + .code = 0x00a0, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_occupancy), + .umasks = icx_unc_m3upi_txr_horz_occupancy, + }, + { .name = "UNC_M3UPI_TxR_HORZ_STARVED", + .desc = "CMS Horizontal Egress Injection Starvation", + .code = 0x00a5, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_horz_starved), + .umasks = icx_unc_m3upi_txr_horz_starved, + }, + { .name = "UNC_M3UPI_TxR_VERT_ADS_USED", + .desc = "CMS Vertical ADS Used", + .code = 0x009c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_ads_used), + .umasks = icx_unc_m3upi_txr_vert_ads_used, + }, + { .name = "UNC_M3UPI_TxR_VERT_BYPASS", + .desc = "CMS Vertical ADS Used", + .code = 0x009d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_bypass), + .umasks = icx_unc_m3upi_txr_vert_bypass, + }, + { .name = "UNC_M3UPI_TxR_VERT_BYPASS_1", + .desc = "CMS Vertical ADS Used", + .code = 0x009e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_cycles_full1), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_cycles_full1, + }, + { .name = "UNC_M3UPI_TxR_VERT_CYCLES_FULL0", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0094, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_cycles_ne0), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_cycles_ne0, + }, + { .name = "UNC_M3UPI_TxR_VERT_CYCLES_FULL1", + .desc = "Cycles CMS Vertical Egress Queue Is Full", + .code = 0x0095, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_cycles_full1), + .umasks = icx_unc_m3upi_txr_vert_cycles_full1, + }, + { .name = "UNC_M3UPI_TxR_VERT_CYCLES_NE0", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0096, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_cycles_ne0), + .umasks = icx_unc_m3upi_txr_vert_cycles_ne0, + }, + { .name = "UNC_M3UPI_TxR_VERT_CYCLES_NE1", + .desc = "Cycles CMS Vertical Egress Queue Is Not Empty", + .code = 0x0097, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_inserts1), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_inserts1, + }, + { .name = "UNC_M3UPI_TxR_VERT_INSERTS0", + .desc = "CMS Vert Egress Allocations", + .code = 0x0092, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_occupancy0), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_occupancy0, + }, + { .name = "UNC_M3UPI_TxR_VERT_INSERTS1", + .desc = "CMS Vert Egress Allocations", + .code = 0x0093, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_inserts1), + .umasks = icx_unc_m3upi_txr_vert_inserts1, + }, + { .name = "UNC_M3UPI_TxR_VERT_NACK0", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0098, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_starved0), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_starved0, + }, + { .name = "UNC_M3UPI_TxR_VERT_NACK1", + .desc = "CMS Vertical Egress NACKs", + .code = 0x0099, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_occupancy1), /* shared */ + .umasks = icx_unc_m3upi_txr_vert_occupancy1, + }, + { .name = "UNC_M3UPI_TxR_VERT_OCCUPANCY0", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0090, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_occupancy0), + .umasks = icx_unc_m3upi_txr_vert_occupancy0, + }, + { .name = "UNC_M3UPI_TxR_VERT_OCCUPANCY1", + .desc = "CMS Vert Egress Occupancy", + .code = 0x0091, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_occupancy1), + .umasks = icx_unc_m3upi_txr_vert_occupancy1, + }, + { .name = "UNC_M3UPI_TxR_VERT_STARVED0", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009a, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_starved0), + .umasks = icx_unc_m3upi_txr_vert_starved0, + }, + { .name = "UNC_M3UPI_TxR_VERT_STARVED1", + .desc = "CMS Vertical Egress Injection Starvation", + .code = 0x009b, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_txr_vert_starved1), + .umasks = icx_unc_m3upi_txr_vert_starved1, + }, + { .name = "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY", + .desc = "UPI0 AD Credits Empty", + .code = 0x0020, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_upi_peer_ad_credits_empty), + .umasks = icx_unc_m3upi_upi_peer_ad_credits_empty, + }, + { .name = "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY", + .desc = "UPI0 BL Credits Empty", + .code = 0x0021, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_upi_peer_bl_credits_empty), + .umasks = icx_unc_m3upi_upi_peer_bl_credits_empty, + }, + { .name = "UNC_M3UPI_UPI_PREFETCH_SPAWN", + .desc = "FlowQ Generated Prefetch (experimental)", + .code = 0x0029, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_M3UPI_VERT_RING_AD_IN_USE", + .desc = "Vertical AD Ring In Use", + .code = 0x00b0, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_akc_in_use), /* shared */ + .umasks = icx_unc_m3upi_vert_ring_akc_in_use, + }, + { .name = "UNC_M3UPI_VERT_RING_AKC_IN_USE", + .desc = "Vertical AKC Ring In Use", + .code = 0x00b4, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_akc_in_use), + .umasks = icx_unc_m3upi_vert_ring_akc_in_use, + }, + { .name = "UNC_M3UPI_VERT_RING_AK_IN_USE", + .desc = "Vertical AK Ring In Use", + .code = 0x00b1, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_bl_in_use), /* shared */ + .umasks = icx_unc_m3upi_vert_ring_bl_in_use, + }, + { .name = "UNC_M3UPI_VERT_RING_BL_IN_USE", + .desc = "Vertical BL Ring in Use", + .code = 0x00b2, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_bl_in_use), + .umasks = icx_unc_m3upi_vert_ring_bl_in_use, + }, + { .name = "UNC_M3UPI_VERT_RING_IV_IN_USE", + .desc = "Vertical IV Ring in Use", + .code = 0x00b3, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_iv_in_use), + .umasks = icx_unc_m3upi_vert_ring_iv_in_use, + }, + { .name = "UNC_M3UPI_VERT_RING_TGC_IN_USE", + .desc = "Vertical TGC Ring In Use", + .code = 0x00b5, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vert_ring_tgc_in_use), + .umasks = icx_unc_m3upi_vert_ring_tgc_in_use, + }, + { .name = "UNC_M3UPI_VN0_CREDITS_USED", + .desc = "VN0 Credit Used", + .code = 0x005b, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vn0_no_credits), /* shared */ + .umasks = icx_unc_m3upi_vn0_no_credits, + }, + { .name = "UNC_M3UPI_VN0_NO_CREDITS", + .desc = "VN0 No Credits", + .code = 0x005d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vn0_no_credits), + .umasks = icx_unc_m3upi_vn0_no_credits, + }, + { .name = "UNC_M3UPI_VN1_CREDITS_USED", + .desc = "VN1 Credit Used", + .code = 0x005c, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vn1_no_credits), /* shared */ + .umasks = icx_unc_m3upi_vn1_no_credits, + }, + { .name = "UNC_M3UPI_VN1_NO_CREDITS", + .desc = "VN1 No Credits", + .code = 0x005e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_vn1_no_credits), + .umasks = icx_unc_m3upi_vn1_no_credits, + }, + { .name = "UNC_M3UPI_WB_OCC_COMPARE", + .desc = "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + .code = 0x007e, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_wb_occ_compare), + .umasks = icx_unc_m3upi_wb_occ_compare, + }, + { .name = "UNC_M3UPI_WB_PENDING", + .desc = "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + .code = 0x007d, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_wb_pending), + .umasks = icx_unc_m3upi_wb_pending, + }, + { .name = "UNC_M3UPI_XPT_PFTCH", + .desc = "UNC_M3UPI_XPT_PFTCH.ARRIVED", + .code = 0x0061, + .modmsk = ICX_UNC_M3UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_m3upi_xpt_pftch), + .umasks = icx_unc_m3upi_xpt_pftch, + }, +}; +/* 130 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_pcu_events.h b/src/libpfm4/lib/events/intel_icx_unc_pcu_events.h new file mode 100644 index 000000000..e85f09955 --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_pcu_events.h @@ -0,0 +1,196 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_pcu (IcelakeX Uncore PCU) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ + +static const intel_x86_umask_t icx_unc_p_power_state_occupancy[]={ + { .uname = "CORES_C0", + .udesc = "C0 and C1 (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORES_C3", + .udesc = "C3 (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "CORES_C6", + .udesc = "C6 and C7 (experimental)", + .ucode = 0xc000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_pcu_pe[]={ + { .name = "UNC_P_CLOCKTICKS", + .desc = "Clockticks of the power control unit (PCU)", + .code = 0x0000, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_CORE_TRANSITION_CYCLES", + .desc = "UNC_P_CORE_TRANSITION_CYCLES (experimental)", + .code = 0x0060, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_DEMOTIONS", + .desc = "UNC_P_DEMOTIONS (experimental)", + .code = 0x0030, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FIVR_PS_PS0_CYCLES", + .desc = "Phase Shed 0 Cycles (experimental)", + .code = 0x0075, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FIVR_PS_PS1_CYCLES", + .desc = "Phase Shed 1 Cycles (experimental)", + .code = 0x0076, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FIVR_PS_PS2_CYCLES", + .desc = "Phase Shed 2 Cycles (experimental)", + .code = 0x0077, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FIVR_PS_PS3_CYCLES", + .desc = "Phase Shed 3 Cycles (experimental)", + .code = 0x0078, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_CLIP_AVX256", + .desc = "AVX256 Frequency Clipping (experimental)", + .code = 0x0049, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_CLIP_AVX512", + .desc = "AVX512 Frequency Clipping (experimental)", + .code = 0x004a, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + .desc = "Thermal Strongest Upper Limit Cycles (experimental)", + .code = 0x0004, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_MAX_POWER_CYCLES", + .desc = "Power Strongest Upper Limit Cycles (experimental)", + .code = 0x0005, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_MIN_IO_P_CYCLES", + .desc = "IO P Limit Strongest Lower Limit Cycles (experimental)", + .code = 0x0073, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_FREQ_TRANS_CYCLES", + .desc = "Cycles spent changing Frequency (experimental)", + .code = 0x0074, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + .desc = "Memory Phase Shedding Cycles (experimental)", + .code = 0x002f, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PKG_RESIDENCY_C0_CYCLES", + .desc = "Package C State Residency - C0 (experimental)", + .code = 0x002a, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + .desc = "Package C State Residency - C2E (experimental)", + .code = 0x002b, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PKG_RESIDENCY_C3_CYCLES", + .desc = "Package C State Residency - C3 (experimental)", + .code = 0x002c, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PKG_RESIDENCY_C6_CYCLES", + .desc = "Package C State Residency - C6 (experimental)", + .code = 0x002d, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PMAX_THROTTLED_CYCLES", + .desc = "UNC_P_PMAX_THROTTLED_CYCLES (experimental)", + .code = 0x0006, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_POWER_STATE_OCCUPANCY", + .desc = "Number of cores in C-State", + .code = 0x0080, + .modmsk = ICX_UNC_PCU_OCC_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_p_power_state_occupancy), + .umasks = icx_unc_p_power_state_occupancy, + }, + { .name = "UNC_P_PROCHOT_EXTERNAL_CYCLES", + .desc = "External Prochot (experimental)", + .code = 0x000a, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_PROCHOT_INTERNAL_CYCLES", + .desc = "Internal Prochot (experimental)", + .code = 0x0009, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_TOTAL_TRANSITION_CYCLES", + .desc = "Total Core C State Transition Cycles (experimental)", + .code = 0x0072, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_P_VR_HOT_CYCLES", + .desc = "VR Hot (experimental)", + .code = 0x0042, + .modmsk = ICX_UNC_PCU_ATTRS, + .cntmsk = 0xfull, + }, +}; +/* 24 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_ubox_events.h b/src/libpfm4/lib/events/intel_icx_unc_ubox_events.h new file mode 100644 index 000000000..b112eac4c --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_ubox_events.h @@ -0,0 +1,256 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_ubox (IcelakeX Uncore UBOX) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ + +static const intel_x86_umask_t icx_unc_u_event_msg[]={ + { .uname = "DOORBELL_RCVD", + .udesc = "Doorbell (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "INT_PRIO", + .udesc = "Interrupt (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IPI_RCVD", + .udesc = "IPI (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "MSI_RCVD", + .udesc = "MSI (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VLW_RCVD", + .udesc = "VLW (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_u_m2u_misc1[]={ + { .uname = "RxC_CYCLES_NE_CBO_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RxC_CYCLES_NE_CBO_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RxC_CYCLES_NE_UPI_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RxC_CYCLES_NE_UPI_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_CBO_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_CBO_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_UPI_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_UPI_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_u_m2u_misc2[]={ + { .uname = "RxC_CYCLES_EMPTY_BL", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RxC_CYCLES_FULL_BL", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_VN0_NCB", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_CRD_OVF_VN0_NCS", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_EMPTY_AK", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_EMPTY_AKC", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_EMPTY_BL", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_FULL_BL", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_u_m2u_misc3[]={ + { .uname = "TxC_CYCLES_FULL_AK", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TxC_CYCLES_FULL_AKC", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_u_phold_cycles[]={ + { .uname = "ASSERT_TO_ACK", + .udesc = "Assert to ACK (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_DFL, + }, +}; + +static const intel_x86_umask_t icx_unc_u_racu_drng[]={ + { .uname = "PFTCH_BUF_EMPTY", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDRAND", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RDSEED", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_ubox_pe[]={ + { .name = "UNC_U_CLOCKTICKS", + .desc = "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + .code = 0x0000, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x1ull, + }, + { .name = "UNC_U_EVENT_MSG", + .desc = "Message Received", + .code = 0x0042, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_event_msg), + .umasks = icx_unc_u_event_msg, + }, + { .name = "UNC_U_LOCK_CYCLES", + .desc = "IDI Lock/SplitLock Cycles (experimental)", + .code = 0x0044, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + }, + { .name = "UNC_U_M2U_MISC1", + .desc = "TBD", + .code = 0x004d, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_m2u_misc1), + .umasks = icx_unc_u_m2u_misc1, + }, + { .name = "UNC_U_M2U_MISC2", + .desc = "TBD", + .code = 0x004e, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_m2u_misc2), + .umasks = icx_unc_u_m2u_misc2, + }, + { .name = "UNC_U_M2U_MISC3", + .desc = "TBD", + .code = 0x004f, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_m2u_misc3), + .umasks = icx_unc_u_m2u_misc3, + }, + { .name = "UNC_U_PHOLD_CYCLES", + .desc = "Cycles PHOLD Assert to Ack", + .code = 0x0045, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_phold_cycles), + .umasks = icx_unc_u_phold_cycles, + }, + { .name = "UNC_U_RACU_DRNG", + .desc = "TBD", + .code = 0x004c, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_u_racu_drng), + .umasks = icx_unc_u_racu_drng, + }, + { .name = "UNC_U_RACU_REQUESTS", + .desc = "RACU Request (experimental)", + .code = 0x0046, + .modmsk = ICX_UNC_UBO_ATTRS, + .cntmsk = 0x3ull, + }, +}; +/* 9 events available */ diff --git a/src/libpfm4/lib/events/intel_icx_unc_upi_events.h b/src/libpfm4/lib/events/intel_icx_unc_upi_events.h new file mode 100644 index 000000000..c60e49827 --- /dev/null +++ b/src/libpfm4/lib/events/intel_icx_unc_upi_events.h @@ -0,0 +1,754 @@ +/* + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * This file is part of libpfm, a performance monitoring support library for + * applications on Linux. + * + * PMU: icx_unc_upi (IcelakeX Uncore UPI) + * Based on Intel JSON event table version : 1.21 + * Based on Intel JSON event table published : 06/06/2023 + */ +static const intel_x86_umask_t icx_unc_upi_direct_attempts[]={ + { .uname = "D2C", + .udesc = "D2C (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "D2K", + .udesc = "D2K (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_flowq_no_vna_crd[]={ + { .uname = "AD_VNA_EQ0", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_VNA_EQ1", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AD_VNA_EQ2", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_VNA_EQ0", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_VNA_EQ1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_VNA_EQ2", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "AK_VNA_EQ3", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "BL_VNA_EQ0", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_m3_byp_blocked[]={ + { .uname = "BGF_CRD", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_AD_VNA_LE2", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_AK_VNA_LE3", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_BL_VNA_EQ0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GV_BLOCK", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_m3_rxq_blocked[]={ + { .uname = "BGF_CRD", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_AD_VNA_BTW_2_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_AD_VNA_LE2", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_AK_VNA_LE3", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_BL_VNA_BTW_0_THRESH", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "FLOWQ_BL_VNA_EQ0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "GV_BLOCK", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_req_slot2_from_m3[]={ + { .uname = "ACK", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN0", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VN1", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "VNA", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_rxl_flits[]={ + { .uname = "ALL_DATA", + .udesc = "All Data", + .ucode = 0x0f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_NULL", + .udesc = "Null FLITs received from any slot", + .ucode = 0x2700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA", + .udesc = "Data (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IDLE", + .udesc = "Null FLITs received from any slot (experimental)", + .ucode = 0x4700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCRD", + .udesc = "LLCRD Not Empty (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCTRL", + .udesc = "LLCTRL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NON_DATA", + .udesc = "All Non Data", + .ucode = 0x9700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NULL", + .udesc = "Slot NULL or LLCRD Empty (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PROTHDR", + .udesc = "Protocol Header (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT0", + .udesc = "Slot 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT1", + .udesc = "Slot 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT2", + .udesc = "Slot 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_rxl_inserts[]={ + { .uname = "SLOT0", + .udesc = "Slot 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT1", + .udesc = "Slot 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT2", + .udesc = "Slot 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_rxl_occupancy[]={ + { .uname = "SLOT0", + .udesc = "Slot 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT1", + .udesc = "Slot 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT2", + .udesc = "Slot 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_rxl_slot_bypass[]={ + { .uname = "S0_RXQ1", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S0_RXQ2", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S1_RXQ0", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S1_RXQ2", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S2_RXQ0", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "S2_RXQ1", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_txl0p_clk_active[]={ + { .uname = "CFG_CTL", + .udesc = "TBD (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DFX", + .udesc = "TBD (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RETRY", + .udesc = "TBD (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RXQ", + .udesc = "TBD (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RXQ_BYPASS", + .udesc = "TBD (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RXQ_CRED", + .udesc = "TBD (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SPARE", + .udesc = "TBD (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "TXQ", + .udesc = "TBD (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_txl_basic_hdr_match[]={ + { .uname = "NCB", + .udesc = "Non-Coherent Bypass (experimental)", + .ucode = 0x0e00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCB_OPC", + .udesc = "Non-Coherent Bypass, Match Opcode (experimental)", + .ucode = 0x100000e00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS", + .udesc = "Non-Coherent Standard (experimental)", + .ucode = 0x0f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NCS_OPC", + .udesc = "Non-Coherent Standard, Match Opcode (experimental)", + .ucode = 0x100000f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ", + .udesc = "Request (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "REQ_OPC", + .udesc = "Request, Match Opcode (experimental)", + .ucode = 0x100000800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPCNFLT", + .udesc = "Response - Conflict (experimental)", + .ucode = 0x10000aa00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSPI", + .udesc = "Response - Invalid (experimental)", + .ucode = 0x100002a00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP_DATA", + .udesc = "Response - Data (experimental)", + .ucode = 0x0c00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP_DATA_OPC", + .udesc = "Response - Data, Match Opcode (experimental)", + .ucode = 0x100000c00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP_NODATA", + .udesc = "Response - No Data (experimental)", + .ucode = 0x0a00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "RSP_NODATA_OPC", + .udesc = "Response - No Data, Match Opcode (experimental)", + .ucode = 0x100000a00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP", + .udesc = "Snoop (experimental)", + .ucode = 0x0900ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SNP_OPC", + .udesc = "Snoop, Match Opcode (experimental)", + .ucode = 0x100000900ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB", + .udesc = "Writeback (experimental)", + .ucode = 0x0d00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "WB_OPC", + .udesc = "Writeback, Match Opcode (experimental)", + .ucode = 0x100000d00ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_umask_t icx_unc_upi_txl_flits[]={ + { .uname = "ALL_DATA", + .udesc = "All Data", + .ucode = 0x0f00ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "ALL_NULL", + .udesc = "Null FLITs transmitted to any slot", + .ucode = 0x2700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "DATA", + .udesc = "Data (experimental)", + .ucode = 0x0800ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "IDLE", + .udesc = "Idle (experimental)", + .ucode = 0x4700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCRD", + .udesc = "LLCRD Not Empty (experimental)", + .ucode = 0x1000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "LLCTRL", + .udesc = "LLCTRL (experimental)", + .ucode = 0x4000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NON_DATA", + .udesc = "All Non Data", + .ucode = 0x9700ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "NULL", + .udesc = "Slot NULL or LLCRD Empty (experimental)", + .ucode = 0x2000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "PROTHDR", + .udesc = "Protocol Header (experimental)", + .ucode = 0x8000ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT0", + .udesc = "Slot 0 (experimental)", + .ucode = 0x0100ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT1", + .udesc = "Slot 1 (experimental)", + .ucode = 0x0200ull, + .uflags = INTEL_X86_NCOMBO, + }, + { .uname = "SLOT2", + .udesc = "Slot 2 (experimental)", + .ucode = 0x0400ull, + .uflags = INTEL_X86_NCOMBO, + }, +}; + +static const intel_x86_entry_t intel_icx_unc_upi_ll_pe[]={ + { .name = "UNC_UPI_CLOCKTICKS", + .desc = "Number of kfclks", + .code = 0x0001, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_DIRECT_ATTEMPTS", + .desc = "Direct packet attempts", + .code = 0x0012, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_direct_attempts), + .umasks = icx_unc_upi_direct_attempts, + }, + { .name = "UNC_UPI_FLOWQ_NO_VNA_CRD", + .desc = "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + .code = 0x0018, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_flowq_no_vna_crd), + .umasks = icx_unc_upi_flowq_no_vna_crd, + }, + { .name = "UNC_UPI_L1_POWER_CYCLES", + .desc = "Cycles in L1", + .code = 0x0021, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_M3_BYP_BLOCKED", + .desc = "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + .code = 0x0014, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_m3_byp_blocked), + .umasks = icx_unc_upi_m3_byp_blocked, + }, + { .name = "UNC_UPI_M3_CRD_RETURN_BLOCKED", + .desc = "UNC_UPI_M3_CRD_RETURN_BLOCKED (experimental)", + .code = 0x0016, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_M3_RXQ_BLOCKED", + .desc = "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + .code = 0x0015, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_m3_rxq_blocked), + .umasks = icx_unc_upi_m3_rxq_blocked, + }, + { .name = "UNC_UPI_PHY_INIT_CYCLES", + .desc = "Cycles where phy is not in L0, L0c, L0p, L1 (experimental)", + .code = 0x0020, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_POWER_L1_NACK", + .desc = "L1 Req Nack (experimental)", + .code = 0x0023, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_POWER_L1_REQ", + .desc = "L1 Req (same as L1 Ack). (experimental)", + .code = 0x0022, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_REQ_SLOT2_FROM_M3", + .desc = "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + .code = 0x0046, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_req_slot2_from_m3), + .umasks = icx_unc_upi_req_slot2_from_m3, + }, + { .name = "UNC_UPI_RxL0P_POWER_CYCLES", + .desc = "Cycles in L0p (experimental)", + .code = 0x0025, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL0_POWER_CYCLES", + .desc = "Cycles in L0 (experimental)", + .code = 0x0024, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_BASIC_HDR_MATCH", + .desc = "Matches on Receive path of a UPI Port", + .code = 0x0005, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_txl_basic_hdr_match), /* shared */ + .umasks = icx_unc_upi_txl_basic_hdr_match, + }, + { .name = "UNC_UPI_RxL_BYPASSED", + .desc = "RxQ Flit Buffer Bypassed", + .code = 0x0031, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_rxl_inserts), /* shared */ + .umasks = icx_unc_upi_rxl_inserts, + }, + { .name = "UNC_UPI_RxL_CRC_ERRORS", + .desc = "CRC Errors Detected (experimental)", + .code = 0x000b, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + .desc = "LLR Requests Sent (experimental)", + .code = 0x0008, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + .desc = "VN0 Credit Consumed (experimental)", + .code = 0x0039, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + .desc = "VN1 Credit Consumed (experimental)", + .code = 0x003a, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + .desc = "VNA Credit Consumed (experimental)", + .code = 0x0038, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_RxL_FLITS", + .desc = "Valid Flits Received", + .code = 0x0003, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_rxl_flits), + .umasks = icx_unc_upi_rxl_flits, + }, + { .name = "UNC_UPI_RxL_INSERTS", + .desc = "RxQ Flit Buffer Allocations", + .code = 0x0030, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_rxl_inserts), + .umasks = icx_unc_upi_rxl_inserts, + }, + { .name = "UNC_UPI_RxL_OCCUPANCY", + .desc = "RxQ Occupancy - All Packets", + .code = 0x0032, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_rxl_occupancy), + .umasks = icx_unc_upi_rxl_occupancy, + }, + { .name = "UNC_UPI_RxL_SLOT_BYPASS", + .desc = "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + .code = 0x0033, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_rxl_slot_bypass), + .umasks = icx_unc_upi_rxl_slot_bypass, + }, + { .name = "UNC_UPI_TxL0P_CLK_ACTIVE", + .desc = "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + .code = 0x002a, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_txl0p_clk_active), + .umasks = icx_unc_upi_txl0p_clk_active, + }, + { .name = "UNC_UPI_TxL0P_POWER_CYCLES", + .desc = "Cycles in L0p", + .code = 0x0027, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + .desc = "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER (experimental)", + .code = 0x0028, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + .desc = "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT (experimental)", + .code = 0x0029, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL0_POWER_CYCLES", + .desc = "Cycles in L0 (experimental)", + .code = 0x0026, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL_BASIC_HDR_MATCH", + .desc = "Matches on Transmit path of a UPI Port", + .code = 0x0004, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_txl_basic_hdr_match), + .umasks = icx_unc_upi_txl_basic_hdr_match, + }, + { .name = "UNC_UPI_TxL_BYPASSED", + .desc = "Tx Flit Buffer Bypassed (experimental)", + .code = 0x0041, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL_FLITS", + .desc = "Valid Flits Sent", + .code = 0x0002, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + .ngrp = 1, + .numasks= LIBPFM_ARRAY_SIZE(icx_unc_upi_txl_flits), + .umasks = icx_unc_upi_txl_flits, + }, + { .name = "UNC_UPI_TxL_INSERTS", + .desc = "Tx Flit Buffer Allocations (experimental)", + .code = 0x0040, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_TxL_OCCUPANCY", + .desc = "Tx Flit Buffer Occupancy (experimental)", + .code = 0x0042, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + .desc = "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01 (experimental)", + .code = 0x0045, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, + { .name = "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + .desc = "VNA Credits Pending Return - Occupancy (experimental)", + .code = 0x0044, + .modmsk = ICX_UNC_UPI_ATTRS, + .cntmsk = 0xfull, + }, +}; +/* 36 events available */ diff --git a/src/libpfm4/lib/pfmlib_amd64_rapl.c b/src/libpfm4/lib/pfmlib_amd64_rapl.c index 885704af7..a112405d5 100644 --- a/src/libpfm4/lib/pfmlib_amd64_rapl.c +++ b/src/libpfm4/lib/pfmlib_amd64_rapl.c @@ -53,9 +53,8 @@ pfm_amd64_rapl_detect(void *this) rev = pfm_amd64_cfg.revision; switch(rev) { case PFM_PMU_AMD64_FAM17H_ZEN2: - ret = PFM_SUCCESS; - break; case PFM_PMU_AMD64_FAM19H_ZEN3: + case PFM_PMU_AMD64_FAM19H_ZEN4: ret = PFM_SUCCESS; break; default: diff --git a/src/libpfm4/lib/pfmlib_common.c b/src/libpfm4/lib/pfmlib_common.c index f28175ae8..ce5c2e60d 100644 --- a/src/libpfm4/lib/pfmlib_common.c +++ b/src/libpfm4/lib/pfmlib_common.c @@ -118,6 +118,85 @@ static pfmlib_pmu_t *pfmlib_pmus[]= &intel_clx_support, &intel_icl_support, &intel_icx_support, + &intel_icx_unc_cha0_support, + &intel_icx_unc_cha1_support, + &intel_icx_unc_cha2_support, + &intel_icx_unc_cha3_support, + &intel_icx_unc_cha4_support, + &intel_icx_unc_cha5_support, + &intel_icx_unc_cha6_support, + &intel_icx_unc_cha7_support, + &intel_icx_unc_cha8_support, + &intel_icx_unc_cha9_support, + &intel_icx_unc_cha10_support, + &intel_icx_unc_cha11_support, + &intel_icx_unc_cha12_support, + &intel_icx_unc_cha13_support, + &intel_icx_unc_cha14_support, + &intel_icx_unc_cha15_support, + &intel_icx_unc_cha16_support, + &intel_icx_unc_cha17_support, + &intel_icx_unc_cha18_support, + &intel_icx_unc_cha19_support, + &intel_icx_unc_cha20_support, + &intel_icx_unc_cha21_support, + &intel_icx_unc_cha22_support, + &intel_icx_unc_cha23_support, + &intel_icx_unc_cha24_support, + &intel_icx_unc_cha25_support, + &intel_icx_unc_cha26_support, + &intel_icx_unc_cha27_support, + &intel_icx_unc_cha28_support, + &intel_icx_unc_cha29_support, + &intel_icx_unc_cha30_support, + &intel_icx_unc_cha31_support, + &intel_icx_unc_cha32_support, + &intel_icx_unc_cha33_support, + &intel_icx_unc_cha34_support, + &intel_icx_unc_cha35_support, + &intel_icx_unc_cha36_support, + &intel_icx_unc_cha37_support, + &intel_icx_unc_cha38_support, + &intel_icx_unc_cha39_support, + &intel_icx_unc_imc0_support, + &intel_icx_unc_imc1_support, + &intel_icx_unc_imc2_support, + &intel_icx_unc_imc3_support, + &intel_icx_unc_imc4_support, + &intel_icx_unc_imc5_support, + &intel_icx_unc_imc6_support, + &intel_icx_unc_imc7_support, + &intel_icx_unc_imc8_support, + &intel_icx_unc_imc9_support, + &intel_icx_unc_imc10_support, + &intel_icx_unc_imc11_support, + &intel_icx_unc_m2m0_support, + &intel_icx_unc_m2m1_support, + &intel_icx_unc_iio0_support, + &intel_icx_unc_iio1_support, + &intel_icx_unc_iio2_support, + &intel_icx_unc_iio3_support, + &intel_icx_unc_iio4_support, + &intel_icx_unc_iio5_support, + &intel_icx_unc_irp0_support, + &intel_icx_unc_irp1_support, + &intel_icx_unc_irp2_support, + &intel_icx_unc_irp3_support, + &intel_icx_unc_irp4_support, + &intel_icx_unc_irp5_support, + &intel_icx_unc_pcu_support, + &intel_icx_unc_upi0_support, + &intel_icx_unc_upi1_support, + &intel_icx_unc_upi2_support, + &intel_icx_unc_upi3_support, + &intel_icx_unc_m3upi0_support, + &intel_icx_unc_m3upi1_support, + &intel_icx_unc_m3upi2_support, + &intel_icx_unc_m3upi3_support, + &intel_icx_unc_ubox_support, + &intel_icx_unc_m2pcie0_support, + &intel_icx_unc_m2pcie1_support, + &intel_icx_unc_m2pcie2_support, &intel_spr_support, &intel_emr_support, &intel_rapl_support, diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_cha.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_cha.c new file mode 100644 index 000000000..e304237c3 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_cha.c @@ -0,0 +1,155 @@ +/* + * pfmlib_intel_icx_unc_cha.c : Intel ICX CHA-Box uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_cha_events.h" + +static void +display_cha(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + pfm_snbep_unc_reg_t f; + + __pfm_vbprintf("[UNC_CHA=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d tid_en=%d umask_ext=0x%x] %s\n", + reg->val, + reg->icx_cha.unc_event, + reg->icx_cha.unc_umask, + reg->icx_cha.unc_en, + reg->icx_cha.unc_inv, + reg->icx_cha.unc_edge, + reg->icx_cha.unc_thres, + reg->icx_cha.unc_tid, + reg->icx_cha.unc_umask_ext, + pe[e->event].name); + + if (e->count == 1) + return; + + f.val = e->codes[1]; + + __pfm_vbprintf("[UNC_CHA_FILTER0=0x%"PRIx64" thread_id=%d source=0x%x state=0x%x]\n", + f.val, + f.skx_cha_filt0.tid, + f.skx_cha_filt0.sid, + f.skx_cha_filt0.state); + + if (e->count == 2) + return; + + f.val = e->codes[2]; + + __pfm_vbprintf("[UNC_CHA_FILTER1=0x%"PRIx64" rem=%d loc=%d all_opc=%d nm=%d" + " not_nm=%d opc0=0x%x opc1=0x%x nc=%d isoc=%d]\n", + f.val, + f.skx_cha_filt1.rem, + f.skx_cha_filt1.loc, + f.skx_cha_filt1.all_opc, + f.skx_cha_filt1.nm, + f.skx_cha_filt1.not_nm, + f.skx_cha_filt1.opc0, + f.skx_cha_filt1.opc1, + f.skx_cha_filt1.nc, + f.skx_cha_filt1.isoc); +} + +#define DEFINE_CHA(n) \ +pfmlib_pmu_t intel_icx_unc_cha##n##_support = {\ + .desc = "Intel IcelakeX CHA"#n" uncore",\ + .name = "icx_unc_cha"#n,\ + .perf_name = "uncore_cha_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_CHA##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_cha_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_cha_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_cha,\ +} + +DEFINE_CHA(0); +DEFINE_CHA(1); +DEFINE_CHA(2); +DEFINE_CHA(3); +DEFINE_CHA(4); +DEFINE_CHA(5); +DEFINE_CHA(6); +DEFINE_CHA(7); +DEFINE_CHA(8); +DEFINE_CHA(9); +DEFINE_CHA(10); +DEFINE_CHA(11); +DEFINE_CHA(12); +DEFINE_CHA(13); +DEFINE_CHA(14); +DEFINE_CHA(15); +DEFINE_CHA(16); +DEFINE_CHA(17); +DEFINE_CHA(18); +DEFINE_CHA(19); +DEFINE_CHA(20); +DEFINE_CHA(21); +DEFINE_CHA(22); +DEFINE_CHA(23); +DEFINE_CHA(24); +DEFINE_CHA(25); +DEFINE_CHA(26); +DEFINE_CHA(27); +DEFINE_CHA(28); +DEFINE_CHA(29); +DEFINE_CHA(30); +DEFINE_CHA(31); +DEFINE_CHA(32); +DEFINE_CHA(33); +DEFINE_CHA(34); +DEFINE_CHA(35); +DEFINE_CHA(36); +DEFINE_CHA(37); +DEFINE_CHA(38); +DEFINE_CHA(39); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_iio.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_iio.c new file mode 100644 index 000000000..99006bb55 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_iio.c @@ -0,0 +1,91 @@ +/* + * pfmlib_intel_icx_unc_iio.c : Intel ICX IIO-Box uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of iiorge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERIIONTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_iio_events.h" + +static void +display_iio(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_IIO=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d fc_mask=%d ch_mask=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + reg->iio.unc_fcmsk, + reg->iio.unc_chmsk, + pe[e->event].name); +} + +#define DEFINE_IIO(n) \ +pfmlib_pmu_t intel_icx_unc_iio##n##_support = {\ + .desc = "Intel IcelakeX IIO"#n" uncore",\ + .name = "icx_unc_iio"#n,\ + .perf_name = "uncore_iio_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_IIO##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_iio_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_iio_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_iio,\ +} + +DEFINE_IIO(0); +DEFINE_IIO(1); +DEFINE_IIO(2); +DEFINE_IIO(3); +DEFINE_IIO(4); +DEFINE_IIO(5); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_imc.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_imc.c new file mode 100644 index 000000000..25c81cf1e --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_imc.c @@ -0,0 +1,95 @@ +/* + * pfmlib_intel_icx_unc_imc.c : Intel ICX IMC-Box uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of imcrge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERIMCNTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_imc_events.h" + +static void +display_imc(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_IMC=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +#define DEFINE_IMC(n) \ +pfmlib_pmu_t intel_icx_unc_imc##n##_support = {\ + .desc = "Intel IcelakeX CHA"#n" uncore",\ + .name = "icx_unc_imc"#n,\ + .perf_name = "uncore_imc_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_IMC##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_imc_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_imc_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_imc,\ +} + +DEFINE_IMC(0); +DEFINE_IMC(1); +DEFINE_IMC(2); +DEFINE_IMC(3); +DEFINE_IMC(4); +DEFINE_IMC(5); +DEFINE_IMC(6); +DEFINE_IMC(7); +DEFINE_IMC(8); +DEFINE_IMC(9); +DEFINE_IMC(10); +DEFINE_IMC(11); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_irp.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_irp.c new file mode 100644 index 000000000..b80e7a8c9 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_irp.c @@ -0,0 +1,89 @@ +/* + * pfmlib_intel_icx_unc_irp.c : Intel ICX IRP uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of irprge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERIRPNTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_irp_events.h" + +static void +display_irp(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_IRP=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d fc_mask=%d ch_mask=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +#define DEFINE_IRP(n) \ +pfmlib_pmu_t intel_icx_unc_irp##n##_support = {\ + .desc = "Intel IcelakeX IRP"#n" uncore",\ + .name = "icx_unc_irp"#n,\ + .perf_name = "uncore_irp_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_IRP##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_irp_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_irp_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_irp,\ +} + +DEFINE_IRP(0); +DEFINE_IRP(1); +DEFINE_IRP(2); +DEFINE_IRP(3); +DEFINE_IRP(4); +DEFINE_IRP(5); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_m2m.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_m2m.c new file mode 100644 index 000000000..f9d36c810 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_m2m.c @@ -0,0 +1,85 @@ +/* + * pfmlib_intel_icx_unc_m2m.c : Intel ICX M2M uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of m2mrge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERM2MNTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_m2m_events.h" + +static void +display_m2m(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_M2M=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d ext_umask0x%x] %s\n", + reg->val, + reg->icx_m2m.unc_event, + reg->icx_m2m.unc_umask, + reg->icx_m2m.unc_en, + reg->icx_m2m.unc_inv, + reg->icx_m2m.unc_edge, + reg->icx_m2m.unc_thres, + pe[e->event].name); +} + +#define DEFINE_M2M(n) \ +pfmlib_pmu_t intel_icx_unc_m2m##n##_support = {\ + .desc = "Intel IcelakeX M2M"#n" uncore",\ + .name = "icx_unc_m2m"#n,\ + .perf_name = "uncore_m2m_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_M2M##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_m2m_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_m2m_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_m2m,\ +} + +DEFINE_M2M(0); +DEFINE_M2M(1); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_m2pcie.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_m2pcie.c new file mode 100644 index 000000000..2e67120bd --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_m2pcie.c @@ -0,0 +1,86 @@ +/* + * pfmlib_intel_icx_unc_m2pcie.c : Intel ICX M2PCIE uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of m2pcierge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERM2PCIENTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_m2pcie_events.h" + +static void +display_m2pcie(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_M2PCIE=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +#define DEFINE_M2PCIE(n) \ +pfmlib_pmu_t intel_icx_unc_m2pcie##n##_support = {\ + .desc = "Intel IcelakeX M2PCIE"#n" uncore",\ + .name = "icx_unc_m2pcie"#n,\ + .perf_name = "uncore_m2pcie_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_M2PCIE##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_m2pcie_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_m2pcie_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_m2pcie,\ +} + +DEFINE_M2PCIE(0); +DEFINE_M2PCIE(1); +DEFINE_M2PCIE(2); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_m3upi.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_m3upi.c new file mode 100644 index 000000000..742e77104 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_m3upi.c @@ -0,0 +1,87 @@ +/* + * pfmlib_intel_icx_unc_m3upi.c : Intel ICX M3UPI uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of m3upirge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERM3UPINTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_m3upi_events.h" + +static void +display_m3upi(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_M3UPI=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +#define DEFINE_M3UPI(n) \ +pfmlib_pmu_t intel_icx_unc_m3upi##n##_support = {\ + .desc = "Intel IcelakeX M3UPI"#n" uncore",\ + .name = "icx_unc_m3upi"#n,\ + .perf_name = "uncore_m3upi_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_M3UPI##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_m3upi_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_m3upi_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_m3upi,\ +} + +DEFINE_M3UPI(0); +DEFINE_M3UPI(1); +DEFINE_M3UPI(2); +DEFINE_M3UPI(3); diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_pcu.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_pcu.c new file mode 100644 index 000000000..ac1444bac --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_pcu.c @@ -0,0 +1,85 @@ +/* + * pfmlib_intel_icx_unc_pcu.c : Intel ICX PCU uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of pcurge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERPCUNTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_pcu_events.h" + +static void +display_pcu(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_PCU=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d tid_en=%d occ_inv=%d occ_edge=%d] %s\n", + reg->val, + reg->icx_pcu.unc_event, + reg->icx_pcu.unc_umask, + reg->icx_pcu.unc_en, + reg->icx_pcu.unc_inv, + reg->icx_pcu.unc_edge, + reg->icx_pcu.unc_thres, + reg->icx_pcu.unc_tid_en, + reg->icx_pcu.unc_occ_inv, + reg->icx_pcu.unc_occ_edge, + pe[e->event].name); +} + +pfmlib_pmu_t intel_icx_unc_pcu_support = { + .desc = "Intel IcelakeX PCU uncore", + .name = "icx_unc_pcu", + .perf_name = "uncore_pcu", + .pmu = PFM_PMU_INTEL_ICX_UNC_PCU, + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_pcu_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 4, + .num_fixed_cntrs = 0, + .max_encoding = 2, + .pe = intel_icx_unc_pcu_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK | INTEL_PMU_FL_UNC_OCC + | PFMLIB_PMU_FL_NO_SMPL, + .pmu_detect = pfm_intel_icx_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, + .can_auto_encode = pfm_intel_snbep_unc_can_auto_encode, + .display_reg = display_pcu, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_ubox.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_ubox.c new file mode 100644 index 000000000..c2034ff6f --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_ubox.c @@ -0,0 +1,81 @@ +/* + * pfmlib_intel_icx_unc_ubox.c : Intel ICX UBOX uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of uboxrge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERUBOXNTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_ubox_events.h" + +static void +display_ubox(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_UBOX=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +pfmlib_pmu_t intel_icx_unc_ubox_support = { + .desc = "Intel IcelakeX UBOX uncore", + .name = "icx_unc_ubox", + .perf_name = "uncore_ubox", + .pmu = PFM_PMU_INTEL_ICX_UNC_UBOX, + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_ubox_pe), + .type = PFM_PMU_TYPE_UNCORE, + .num_cntrs = 4, + .num_fixed_cntrs = 0, + .max_encoding = 2, + .pe = intel_icx_unc_ubox_pe, + .atdesc = snbep_unc_mods, + .flags = PFMLIB_PMU_FL_RAW_UMASK, + .pmu_detect = pfm_intel_icx_unc_detect, + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding, + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding), + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), + .get_event_first = pfm_intel_x86_get_event_first, + .get_event_next = pfm_intel_x86_get_event_next, + .event_is_valid = pfm_intel_x86_event_is_valid, + .validate_table = pfm_intel_x86_validate_table, + .get_event_info = pfm_intel_x86_get_event_info, + .get_event_attr_info = pfm_intel_x86_get_event_attr_info, + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs), + .get_event_nattrs = pfm_intel_x86_get_event_nattrs, + .can_auto_encode = pfm_intel_x86_can_auto_encode, + .display_reg = display_ubox, +}; diff --git a/src/libpfm4/lib/pfmlib_intel_icx_unc_upi.c b/src/libpfm4/lib/pfmlib_intel_icx_unc_upi.c new file mode 100644 index 000000000..be4994c37 --- /dev/null +++ b/src/libpfm4/lib/pfmlib_intel_icx_unc_upi.c @@ -0,0 +1,87 @@ +/* + * pfmlib_intel_icx_unc_upi.c : Intel ICX UPI uncore PMU + * + * Copyright (c) 2023 Google LLC + * Contributed by Stephane Eranian + * + * Permission is hereby granted, free of upirge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, + * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERUPINTABILITY, FITNESS FOR A + * PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF + * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include + +/* private headers */ +#include "pfmlib_priv.h" +#include "pfmlib_intel_x86_priv.h" +#include "pfmlib_intel_snbep_unc_priv.h" +#include "events/intel_icx_unc_upi_events.h" + +static void +display_upi(void *this, pfmlib_event_desc_t *e, void *val) +{ + const intel_x86_entry_t *pe = this_pe(this); + pfm_snbep_unc_reg_t *reg = val; + + __pfm_vbprintf("[UNC_UPI=0x%"PRIx64" event=0x%x umask=0x%x en=%d " + "inv=%d edge=%d thres=%d] %s\n", + reg->val, + reg->com.unc_event, + reg->com.unc_umask, + reg->com.unc_en, + reg->com.unc_inv, + reg->com.unc_edge, + reg->com.unc_thres, + pe[e->event].name); +} + +#define DEFINE_UPI(n) \ +pfmlib_pmu_t intel_icx_unc_upi##n##_support = {\ + .desc = "Intel IcelakeX UPI"#n" uncore",\ + .name = "icx_unc_upi"#n,\ + .perf_name = "uncore_upi_"#n,\ + .pmu = PFM_PMU_INTEL_ICX_UNC_UPI##n,\ + .pme_count = LIBPFM_ARRAY_SIZE(intel_icx_unc_upi_ll_pe),\ + .type = PFM_PMU_TYPE_UNCORE,\ + .num_cntrs = 4,\ + .num_fixed_cntrs = 0,\ + .max_encoding = 2,\ + .pe = intel_icx_unc_upi_ll_pe,\ + .atdesc = snbep_unc_mods,\ + .flags = PFMLIB_PMU_FL_RAW_UMASK,\ + .pmu_detect = pfm_intel_icx_unc_detect,\ + .get_event_encoding[PFM_OS_NONE] = pfm_intel_snbep_unc_get_encoding,\ + PFMLIB_ENCODE_PERF(pfm_intel_snbep_unc_get_perf_encoding),\ + PFMLIB_OS_DETECT(pfm_intel_x86_perf_detect), \ + .get_event_first = pfm_intel_x86_get_event_first,\ + .get_event_next = pfm_intel_x86_get_event_next,\ + .event_is_valid = pfm_intel_x86_event_is_valid,\ + .validate_table = pfm_intel_x86_validate_table,\ + .get_event_info = pfm_intel_x86_get_event_info,\ + .get_event_attr_info = pfm_intel_x86_get_event_attr_info,\ + PFMLIB_VALID_PERF_PATTRS(pfm_intel_snbep_unc_perf_validate_pattrs),\ + .get_event_nattrs = pfm_intel_x86_get_event_nattrs,\ + .can_auto_encode = pfm_intel_x86_can_auto_encode, \ + .display_reg = display_upi,\ +} + +DEFINE_UPI(0); +DEFINE_UPI(1); +DEFINE_UPI(2); +DEFINE_UPI(3); diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc.c b/src/libpfm4/lib/pfmlib_intel_snbep_unc.c index acaccbc80..5e3affe6b 100644 --- a/src/libpfm4/lib/pfmlib_intel_snbep_unc.c +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc.c @@ -54,6 +54,9 @@ const pfmlib_attr_desc_t snbep_unc_mods[]={ PFM_ATTR_B("rmem", "remote memory cacheable"), /* not_nm filter1 (skx) */ PFM_ATTR_I("dnid", "destination node id [0-15]"), /* SKX:UPI */ PFM_ATTR_I("rcsnid", "destination RCS Node id [0-15]"), /* SKX:UPI */ + PFM_ATTR_I("t", "threshold in range [0-63]"), /* threshold */ + PFM_ATTR_B("occ_i", "occupancy event invert"), /* invert occupancy event */ + PFM_ATTR_B("occ_e", "occupancy event edge "), /* edge occupancy event */ PFM_ATTR_NULL }; @@ -198,6 +201,27 @@ pfm_intel_skx_unc_detect(void *this) return PFM_SUCCESS; } +int +pfm_intel_icx_unc_detect(void *this) +{ + int ret; + + ret = pfm_intel_x86_detect(); + if (ret != PFM_SUCCESS) + + if (pfm_intel_x86_cfg.family != 6) + return PFM_ERR_NOTSUPP; + + switch(pfm_intel_x86_cfg.model) { + case 106: /* Icelake X */ + break; + default: + return PFM_ERR_NOTSUPP; + } + return PFM_SUCCESS; +} + + static void display_com(void *this, pfmlib_event_desc_t *e, void *val) @@ -541,6 +565,13 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) reg.pcu.unc_thres = ival; umodmsk |= _SNBEP_UNC_ATTR_T5; break; + case SNBEP_UNC_ATTR_T6: /* counter-mask */ + /* already forced, cannot overwrite */ + if (ival > 63) + return PFM_ERR_ATTR_VAL; + reg.com.unc_thres = ival; + umodmsk |= _SNBEP_UNC_ATTR_T6; + break; case SNBEP_UNC_ATTR_TF: /* thread id */ if (ival > 1) { DPRINT("invalid thread id, must be < 1"); @@ -649,6 +680,14 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) filters[0].skx_upi_filt.rcsnid = ival; filters[0].skx_upi_filt.en_rcsnid = 1; break; + case SNBEP_UNC_ATTR_OCC_I: /* occ_i */ + reg.icx_pcu.unc_occ_inv = !!ival; + umodmsk |= _SNBEP_UNC_ATTR_OCC_I; + break; + case SNBEP_UNC_ATTR_OCC_E: /* occ_e */ + reg.icx_pcu.unc_occ_edge = !!ival; + umodmsk |= _SNBEP_UNC_ATTR_OCC_E; + break; default: DPRINT("event %s invalid attribute %d\n", pe[e->event].name, a->idx); return PFM_ERR_ATTR; @@ -843,6 +882,15 @@ pfm_intel_snbep_unc_get_encoding(void *this, pfmlib_event_desc_t *e) case SNBEP_UNC_ATTR_RCSNID: evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, filters[0].skx_upi_filt.rcsnid); break; + case SNBEP_UNC_ATTR_T6: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.icx_pcu.unc_thres); + break; + case SNBEP_UNC_ATTR_OCC_I: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.icx_pcu.unc_occ_inv); + break; + case SNBEP_UNC_ATTR_OCC_E: + evt_strcat(e->fstr, ":%s=%lu", snbep_unc_mods[idx].name, reg.icx_pcu.unc_occ_edge); + break; default: DPRINT("unknown attribute %d for event %s\n", idx, pe[e->event].name); return PFM_ERR_ATTR; diff --git a/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h b/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h index a3c33f305..737d20394 100644 --- a/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h +++ b/src/libpfm4/lib/pfmlib_intel_snbep_unc_priv.h @@ -53,6 +53,9 @@ #define SNBEP_UNC_ATTR_RMEM 18 /* not near memory cacheable skx */ #define SNBEP_UNC_ATTR_DNID 19 /* destination node id */ #define SNBEP_UNC_ATTR_RCSNID 20 /* RCS node id */ +#define SNBEP_UNC_ATTR_T6 21 /* threshold (cmask) 6-bit */ +#define SNBEP_UNC_ATTR_OCC_I 22 /* occupancy invert */ +#define SNBEP_UNC_ATTR_OCC_E 23 /* occupancy edge */ #define _SNBEP_UNC_ATTR_I (1 << SNBEP_UNC_ATTR_I) #define _SNBEP_UNC_ATTR_E (1 << SNBEP_UNC_ATTR_E) @@ -75,6 +78,9 @@ #define _SNBEP_UNC_ATTR_RMEM (1 << SNBEP_UNC_ATTR_RMEM) #define _SNBEP_UNC_ATTR_DNID (1 << SNBEP_UNC_ATTR_DNID) #define _SNBEP_UNC_ATTR_RCSNID (1 << SNBEP_UNC_ATTR_RCSNID) +#define _SNBEP_UNC_ATTR_T6 (1 << SNBEP_UNC_ATTR_T6) +#define _SNBEP_UNC_ATTR_OCC_I (1 << SNBEP_UNC_ATTR_OCC_I) +#define _SNBEP_UNC_ATTR_OCC_E (1 << SNBEP_UNC_ATTR_OCC_E) #define SNBEP_UNC_IRP_ATTRS \ (_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) @@ -134,6 +140,12 @@ #define SKX_UNC_PCU_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) +#define ICX_UNC_PCU_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T6) + +#define ICX_UNC_PCU_OCC_ATTRS \ + (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T6|_SNBEP_UNC_ATTR_OCC_I|_SNBEP_UNC_ATTR_OCC_E) + #define SNBEP_UNC_PCU_BAND_ATTRS \ (SNBEP_UNC_PCU_ATTRS | _SNBEP_UNC_ATTR_FF) @@ -215,6 +227,8 @@ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_CHA_ATTRS SKX_UNC_CHA_ATTRS + #define SKX_UNC_CHA_FILT1_ATTRS \ (SKX_UNC_CHA_ATTRS |\ _SNBEP_UNC_ATTR_LOC |\ @@ -229,30 +243,48 @@ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_IIO_ATTRS \ + (_SNBEP_UNC_ATTR_I |\ + _SNBEP_UNC_ATTR_E |\ + _SNBEP_UNC_ATTR_T8) + #define SKX_UNC_IMC_ATTRS \ (_SNBEP_UNC_ATTR_I |\ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_IMC_ATTRS SKX_UNC_IMC_ATTRS +#define ICX_UNC_M2PCIE_ATTRS SKX_UNC_IMC_ATTRS + #define SKX_UNC_IRP_ATTRS \ (_SNBEP_UNC_ATTR_I |\ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_IRP_ATTRS SKX_UNC_IRP_ATTRS + #define SKX_UNC_M2M_ATTRS \ (_SNBEP_UNC_ATTR_I |\ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_M2M_ATTRS SKX_UNC_M2M_ATTRS + #define SKX_UNC_M3UPI_ATTRS \ (_SNBEP_UNC_ATTR_I |\ _SNBEP_UNC_ATTR_E |\ _SNBEP_UNC_ATTR_T8) +#define ICX_UNC_M3UPI_ATTRS SKX_UNC_M3UPI_ATTRS + #define SKX_UNC_UBO_ATTRS SNBEP_UNC_UBO_ATTRS +#define ICX_UNC_UBO_ATTRS SNBEP_UNC_UBO_ATTRS #define SKX_UNC_UPI_ATTRS \ (_SNBEP_UNC_ATTR_I|_SNBEP_UNC_ATTR_E|_SNBEP_UNC_ATTR_T8) + +#define ICX_UNC_UPI_ATTRS SKX_UNC_UPI_ATTRS + #define SKX_UNC_UPI_OPC_ATTRS \ (SKX_UNC_UPI_ATTRS |\ _SNBEP_UNC_ATTR_DNID| _SNBEP_UNC_ATTR_RCSNID) @@ -298,6 +330,49 @@ typedef union { unsigned long unc_thres:8; /* counter mask */ unsigned long unc_res3:32; /* reserved */ } cha; /* covers skx cha */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit mask */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detect */ + unsigned long unc_tid:1; /* tid filter enable */ + unsigned long unc_ov:1; /* overflow enable */ + unsigned long unc_res2:1; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:8; /* counter mask */ + unsigned long unc_umask_ext:26; /* extended umask */ + unsigned long unc_res3:9; /* reserved */ + } icx_cha; /* covers icx cha */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit mask */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_res2:3; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:8; /* counter mask */ + unsigned long unc_umask2:8; /* extended unit mask */ + unsigned long unc_res3:24; /* reserved */ + } icx_m2m; /* covers icx m2m */ + struct { + unsigned long unc_event:8; /* event code */ + unsigned long unc_umask:8; /* unit mask */ + unsigned long unc_res1:1; /* reserved */ + unsigned long unc_rst:1; /* reset */ + unsigned long unc_edge:1; /* edge detec */ + unsigned long unc_tid_en:1; /* tid enable */ + unsigned long unc_res2:2; /* reserved */ + unsigned long unc_en:1; /* enable */ + unsigned long unc_inv:1; /* invert counter mask */ + unsigned long unc_thres:6; /* counter mask */ + unsigned long unc_occ_inv:1; /* occupancy event invert */ + unsigned long unc_occ_edge:1; /* occupancy event edge */ + unsigned long unc_res3:24; /* reserved */ + } icx_pcu; /* covers icx pcu */ struct { unsigned long unc_event:8; /* event code */ unsigned long unc_umask:8; /* unit mask */ @@ -495,6 +570,7 @@ extern int pfm_intel_knl_unc_detect(void *this); extern int pfm_intel_knm_unc_detect(void *this); extern int pfm_intel_bdx_unc_detect(void *this); extern int pfm_intel_skx_unc_detect(void *this); +extern int pfm_intel_icx_unc_detect(void *this); extern int pfm_intel_snbep_unc_get_perf_encoding(void *this, pfmlib_event_desc_t *e); extern int pfm_intel_snbep_unc_can_auto_encode(void *this, int pidx, int uidx); extern int pfm_intel_snbep_unc_get_event_attr_info(void *this, int pidx, int attr_idx, pfmlib_event_attr_info_t *info); diff --git a/src/libpfm4/lib/pfmlib_intel_x86_priv.h b/src/libpfm4/lib/pfmlib_intel_x86_priv.h index 28e099d51..3f2a226b5 100644 --- a/src/libpfm4/lib/pfmlib_intel_x86_priv.h +++ b/src/libpfm4/lib/pfmlib_intel_x86_priv.h @@ -309,7 +309,9 @@ static inline int intel_x86_uflag(void *this, int idx, int attr, int flag) { const intel_x86_entry_t *pe = this_pe(this); - return !!(pe[idx].umasks[attr].uflags & flag); + if (pe[idx].numasks) + return !!(pe[idx].umasks[attr].uflags & flag); + return 0; } static inline unsigned int diff --git a/src/libpfm4/lib/pfmlib_priv.h b/src/libpfm4/lib/pfmlib_priv.h index d91923596..af78b31ac 100644 --- a/src/libpfm4/lib/pfmlib_priv.h +++ b/src/libpfm4/lib/pfmlib_priv.h @@ -305,6 +305,85 @@ extern pfmlib_pmu_t intel_skx_support; extern pfmlib_pmu_t intel_clx_support; extern pfmlib_pmu_t intel_icl_support; extern pfmlib_pmu_t intel_icx_support; +extern pfmlib_pmu_t intel_icx_unc_cha0_support; +extern pfmlib_pmu_t intel_icx_unc_cha1_support; +extern pfmlib_pmu_t intel_icx_unc_cha2_support; +extern pfmlib_pmu_t intel_icx_unc_cha3_support; +extern pfmlib_pmu_t intel_icx_unc_cha4_support; +extern pfmlib_pmu_t intel_icx_unc_cha5_support; +extern pfmlib_pmu_t intel_icx_unc_cha6_support; +extern pfmlib_pmu_t intel_icx_unc_cha7_support; +extern pfmlib_pmu_t intel_icx_unc_cha8_support; +extern pfmlib_pmu_t intel_icx_unc_cha9_support; +extern pfmlib_pmu_t intel_icx_unc_cha10_support; +extern pfmlib_pmu_t intel_icx_unc_cha11_support; +extern pfmlib_pmu_t intel_icx_unc_cha12_support; +extern pfmlib_pmu_t intel_icx_unc_cha13_support; +extern pfmlib_pmu_t intel_icx_unc_cha14_support; +extern pfmlib_pmu_t intel_icx_unc_cha15_support; +extern pfmlib_pmu_t intel_icx_unc_cha16_support; +extern pfmlib_pmu_t intel_icx_unc_cha17_support; +extern pfmlib_pmu_t intel_icx_unc_cha18_support; +extern pfmlib_pmu_t intel_icx_unc_cha19_support; +extern pfmlib_pmu_t intel_icx_unc_cha20_support; +extern pfmlib_pmu_t intel_icx_unc_cha21_support; +extern pfmlib_pmu_t intel_icx_unc_cha22_support; +extern pfmlib_pmu_t intel_icx_unc_cha23_support; +extern pfmlib_pmu_t intel_icx_unc_cha24_support; +extern pfmlib_pmu_t intel_icx_unc_cha25_support; +extern pfmlib_pmu_t intel_icx_unc_cha26_support; +extern pfmlib_pmu_t intel_icx_unc_cha27_support; +extern pfmlib_pmu_t intel_icx_unc_cha28_support; +extern pfmlib_pmu_t intel_icx_unc_cha29_support; +extern pfmlib_pmu_t intel_icx_unc_cha30_support; +extern pfmlib_pmu_t intel_icx_unc_cha31_support; +extern pfmlib_pmu_t intel_icx_unc_cha32_support; +extern pfmlib_pmu_t intel_icx_unc_cha33_support; +extern pfmlib_pmu_t intel_icx_unc_cha34_support; +extern pfmlib_pmu_t intel_icx_unc_cha35_support; +extern pfmlib_pmu_t intel_icx_unc_cha36_support; +extern pfmlib_pmu_t intel_icx_unc_cha37_support; +extern pfmlib_pmu_t intel_icx_unc_cha38_support; +extern pfmlib_pmu_t intel_icx_unc_cha39_support; +extern pfmlib_pmu_t intel_icx_unc_imc0_support; +extern pfmlib_pmu_t intel_icx_unc_imc1_support; +extern pfmlib_pmu_t intel_icx_unc_imc2_support; +extern pfmlib_pmu_t intel_icx_unc_imc3_support; +extern pfmlib_pmu_t intel_icx_unc_imc4_support; +extern pfmlib_pmu_t intel_icx_unc_imc5_support; +extern pfmlib_pmu_t intel_icx_unc_imc6_support; +extern pfmlib_pmu_t intel_icx_unc_imc7_support; +extern pfmlib_pmu_t intel_icx_unc_imc8_support; +extern pfmlib_pmu_t intel_icx_unc_imc9_support; +extern pfmlib_pmu_t intel_icx_unc_imc10_support; +extern pfmlib_pmu_t intel_icx_unc_imc11_support; +extern pfmlib_pmu_t intel_icx_unc_m2m0_support; +extern pfmlib_pmu_t intel_icx_unc_m2m1_support; +extern pfmlib_pmu_t intel_icx_unc_iio0_support; +extern pfmlib_pmu_t intel_icx_unc_iio1_support; +extern pfmlib_pmu_t intel_icx_unc_iio2_support; +extern pfmlib_pmu_t intel_icx_unc_iio3_support; +extern pfmlib_pmu_t intel_icx_unc_iio4_support; +extern pfmlib_pmu_t intel_icx_unc_iio5_support; +extern pfmlib_pmu_t intel_icx_unc_irp0_support; +extern pfmlib_pmu_t intel_icx_unc_irp1_support; +extern pfmlib_pmu_t intel_icx_unc_irp2_support; +extern pfmlib_pmu_t intel_icx_unc_irp3_support; +extern pfmlib_pmu_t intel_icx_unc_irp4_support; +extern pfmlib_pmu_t intel_icx_unc_irp5_support; +extern pfmlib_pmu_t intel_icx_unc_pcu_support; +extern pfmlib_pmu_t intel_icx_unc_upi0_support; +extern pfmlib_pmu_t intel_icx_unc_upi1_support; +extern pfmlib_pmu_t intel_icx_unc_upi2_support; +extern pfmlib_pmu_t intel_icx_unc_upi3_support; +extern pfmlib_pmu_t intel_icx_unc_m3upi0_support; +extern pfmlib_pmu_t intel_icx_unc_m3upi1_support; +extern pfmlib_pmu_t intel_icx_unc_m3upi2_support; +extern pfmlib_pmu_t intel_icx_unc_m3upi3_support; +extern pfmlib_pmu_t intel_icx_unc_ubox_support; +extern pfmlib_pmu_t intel_icx_unc_m2pcie0_support; +extern pfmlib_pmu_t intel_icx_unc_m2pcie1_support; +extern pfmlib_pmu_t intel_icx_unc_m2pcie2_support; extern pfmlib_pmu_t intel_spr_support; extern pfmlib_pmu_t intel_emr_support; extern pfmlib_pmu_t intel_rapl_support; diff --git a/src/libpfm4/tests/validate_x86.c b/src/libpfm4/tests/validate_x86.c index 6fa5dae43..adb7464dd 100644 --- a/src/libpfm4/tests/validate_x86.c +++ b/src/libpfm4/tests/validate_x86.c @@ -8302,6 +8302,486 @@ static const test_event_t x86_test_events[]={ .codes[0] = 0x15301b0, .fstr = "emr::ARITH:FPDIV_ACTIVE:k=1:u=1:e=0:i=0:c=1:intx=0:intxcp=0", }, + { SRC_LINE, + .name = "icx_unc_cha0::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha0::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha1::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha1::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha2::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha2::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha3::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha3::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha4::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha4::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha5::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha5::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha6::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha6::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha7::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha7::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha8::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha8::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha9::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha9::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha10::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha10::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha11::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha11::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha12::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha12::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha13::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha13::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha14::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha14::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha15::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha15::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha16::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha16::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha17::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha17::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha18::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha18::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha19::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha19::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha20::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha20::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha21::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha21::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha22::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha22::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha23::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha23::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha24::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha24::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha25::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha25::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha26::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha26::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha27::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha27::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha28::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha28::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha29::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha29::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha30::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha30::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha31::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha31::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha32::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha32::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha33::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha33::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha34::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha34::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha35::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha35::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha36::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha36::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha37::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha37::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha38::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha38::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha39::UNC_CHA_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_cha39::UNC_CHA_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha2::UNC_CHA_TOR_INSERTS:IO_MISS_PCIRDCUR", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xc8f3fe00000435ull, + .fstr = "icx_unc_cha2::UNC_CHA_TOR_INSERTS:IO_MISS_PCIRDCUR:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_cha4::UNC_CHA_TOR_INSERTS:IO_MISS_PCIRDCUR:t=16:i", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xc8f3fe10800435ull, + .fstr = "icx_unc_cha4::UNC_CHA_TOR_INSERTS:IO_MISS_PCIRDCUR:e=0:i=1:t=16", + }, + { SRC_LINE, + .name = "icx_unc_iio0::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio0::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio1::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio1::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio2::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio2::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio3::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio3::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio4::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio4::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio5::UNC_IIO_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_iio5::UNC_IIO_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio1::UNC_IIO_DATA_REQ_BY_CPU:MEM_READ_PART0", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x70010000004c0ull, + .fstr = "icx_unc_iio1::UNC_IIO_DATA_REQ_BY_CPU:MEM_READ_PART0:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_iio2::UNC_IIO_DATA_REQ_OF_CPU:MEM_READ_PART5", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x7020000000483ull, + .fstr = "icx_unc_iio2::UNC_IIO_DATA_REQ_OF_CPU:MEM_READ_PART5:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_irp1::UNC_I_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x01, + .fstr = "icx_unc_irp1::UNC_I_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_m2m0::UNC_M2M_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x00, + .fstr = "icx_unc_m2m0::UNC_M2M_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_m2m1::UNC_M2M_DIRECTORY_UPDATE", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x12e, + .fstr = "icx_unc_m2m1::UNC_M2M_DIRECTORY_UPDATE:ANY:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_pcu::UNC_P_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x0, + .fstr = "icx_unc_pcu::UNC_P_CLOCKTICKS:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_pcu::UNC_P_CLOCKTICKS:occ_i:occ_e", + .ret = PFM_ERR_ATTR, + }, + { SRC_LINE, + .name = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xc080, + .fstr = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=0:t=0:occ_i=0:occ_e=0", + }, + { SRC_LINE, + .name = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:occ_i", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x4000c080, + .fstr = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=0:i=1:t=0:occ_i=1:occ_e=0", + }, + { SRC_LINE, + .name = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:occ_e", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x8000c080, + .fstr = "icx_unc_pcu::UNC_P_POWER_STATE_OCCUPANCY:CORES_C6:e=1:i=0:t=0:occ_i=0:occ_e=1", + }, + { + .name = "icx_unc_upi0::UNC_UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_upi0::UNC_UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_upi1::UNC_UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_upi1::UNC_UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_upi2::UNC_UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_upi2::UNC_UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_upi3::UNC_UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_upi3::UNC_UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_upi0::UNC_UPI_RxL_FLITS:ALL_DATA", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xf03, + .fstr = "icx_unc_upi0::UNC_UPI_RxL_FLITS:ALL_DATA:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_upi0::UNC_UPI_TxL_FLITS:ALL_DATA", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0xf02, + .fstr = "icx_unc_upi0::UNC_UPI_TxL_FLITS:ALL_DATA:e=0:i=0:t=0", + }, + { SRC_LINE, + .name = "icx_unc_m3upi0::UNC_M3UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_m3upi0::UNC_M3UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_m3upi1::UNC_M3UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_m3upi1::UNC_M3UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_m3upi2::UNC_M3UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_m3upi2::UNC_M3UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_m3upi3::UNC_M3UPI_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x1, + .fstr = "icx_unc_m3upi3::UNC_M3UPI_CLOCKTICKS:e=0:i=0:t=0" + }, + { SRC_LINE, + .name = "icx_unc_ubox::UNC_U_CLOCKTICKS", + .ret = PFM_SUCCESS, + .count = 1, + .codes[0] = 0x0, + .fstr = "icx_unc_ubox::UNC_U_CLOCKTICKS:e=0:i=0:t=0" + }, }; #define NUM_TEST_EVENTS (int)(sizeof(x86_test_events)/sizeof(test_event_t))