diff --git a/arch/arm/include/armv6-m/irq.h b/arch/arm/include/armv6-m/irq.h index 9a0426a2dfb29..81f88d809cf02 100644 --- a/arch/arm/include/armv6-m/irq.h +++ b/arch/arm/include/armv6-m/irq.h @@ -129,6 +129,8 @@ #define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */ #define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */ +#define up_irq_is_disabled(flags) ((flags) != 0) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h index cb8f14831cf66..874e5b494cde6 100644 --- a/arch/arm/include/armv7-a/irq.h +++ b/arch/arm/include/armv7-a/irq.h @@ -212,6 +212,45 @@ /* Bits 12-29: Reserved */ #define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ +/* PSR bits */ + +#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ +#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) +# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ +# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ +# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ +# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ +# define PSR_MODE_MON (22 << PSR_MODE_SHIFT) /* Monitor mode */ +# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ +# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hyp mode */ +# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ +# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ + +#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ +#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ +#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) +# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ +# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ +# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ +#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ +#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ +#define PSR_GE_MASK (15 << PSR_GE_SHIFT) + /* Bits 20-23: Reserved. RAZ/SBZP */ +#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ +#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ +#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) +#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ +#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ +#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ +#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ +#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ + +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE +# define up_irq_is_disabled(flags) (((flags) & PSR_F_BIT) != 0) +#else +# define up_irq_is_disabled(flags) (((flags) & PSR_I_BIT) != 0) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index 1c78a60140e54..c2a2002c78624 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -190,6 +190,12 @@ #define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */ #define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */ +#ifdef CONFIG_ARMV7M_USEBASEPRI +# define up_irq_is_disabled(flags) ((flags) == NVIC_SYSH_DISABLE_PRIORITY) +#else +# define up_irq_is_disabled(flags) ((flags) != 0) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h index a19070b79abd8..1e92c7f901052 100644 --- a/arch/arm/include/armv7-r/irq.h +++ b/arch/arm/include/armv7-r/irq.h @@ -212,6 +212,45 @@ /* Bits 12-29: Reserved */ #define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ +/* PSR bits */ + +#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ +#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) +# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ +# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ +# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ +# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ +# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ +# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ +# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ + +#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ +#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ +#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) +# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ +# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ +# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ +#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ +#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */ +#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT) +#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ +#define PSR_GE_MASK (15 << PSR_GE_SHIFT) + /* Bits 20-23: Reserved. RAZ/SBZP */ +#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ +#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ +#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) +#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ +#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ +#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ +#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ +#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ + +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE +# define up_irq_is_disabled(flags) (((flags) & PSR_F_BIT) != 0) +#else +# define up_irq_is_disabled(flags) (((flags) & PSR_I_BIT) != 0) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/include/armv8-m/irq.h b/arch/arm/include/armv8-m/irq.h index 60c43a6149d7e..92d7cc52979ae 100644 --- a/arch/arm/include/armv8-m/irq.h +++ b/arch/arm/include/armv8-m/irq.h @@ -201,6 +201,12 @@ #define CONTROL_SPSEL (1 << 1) /* Bit 1: Stack-pointer select */ #define CONTROL_NPRIV (1 << 0) /* Bit 0: Not privileged */ +#ifdef CONFIG_ARMV8M_USEBASEPRI +# define up_irq_is_disabled(flags) ((flags) == NVIC_SYSH_DISABLE_PRIORITY) +#else +# define up_irq_is_disabled(flags) ((flags) != 0) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/include/armv8-r/irq.h b/arch/arm/include/armv8-r/irq.h index 25cd71c3f3e41..971197b628d3f 100644 --- a/arch/arm/include/armv8-r/irq.h +++ b/arch/arm/include/armv8-r/irq.h @@ -212,6 +212,45 @@ /* Bits 12-29: Reserved */ #define MPIDR_U (1 << 30) /* Bit 30: Multiprocessing Extensions. */ +/* PSR bits */ + +#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ +#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) +# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ +# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ +# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ +# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ +# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ +# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hypervisor mode */ +# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ +# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ + +#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ +#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ +#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) +# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ +# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ +# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ +#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ +#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */ +#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT) +#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ +#define PSR_GE_MASK (15 << PSR_GE_SHIFT) + /* Bits 20-23: Reserved. RAZ/SBZP */ +#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ +#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ +#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) +#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ +#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ +#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ +#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ +#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ + +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE +# define up_irq_is_disabled(flags) (((flags) & PSR_F_BIT) != 0) +#else +# define up_irq_is_disabled(flags) (((flags) & PSR_I_BIT) != 0) +#endif /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/arm.h b/arch/arm/src/armv7-a/arm.h index 8683a318a806d..7553b8e8e5515 100644 --- a/arch/arm/src/armv7-a/arm.h +++ b/arch/arm/src/armv7-a/arm.h @@ -35,39 +35,6 @@ /* ARMv7-A ******************************************************************/ -/* PSR bits */ - -#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ -#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) -# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ -# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ -# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ -# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ -# define PSR_MODE_MON (22 << PSR_MODE_SHIFT) /* Monitor mode */ -# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ -# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hyp mode */ -# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ -# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ - -#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ -#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ -#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) -# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ -# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ -# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ -#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ -#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ -#define PSR_GE_MASK (15 << PSR_GE_SHIFT) - /* Bits 20-23: Reserved. RAZ/SBZP */ -#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ -#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ -#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) -#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ -#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ -#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ -#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ -#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ - /**************************************************************************** * Inline Functions ****************************************************************************/ diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index a469f9af52d61..c295eea0fd162 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -24,7 +24,7 @@ #include -#include "arm.h" +#include #include "cp15.h" #include "sctlr.h" #include "mmu.h" diff --git a/arch/arm/src/armv7-r/arm.h b/arch/arm/src/armv7-r/arm.h index 9eb24883d0062..cd47fa1f23c71 100644 --- a/arch/arm/src/armv7-r/arm.h +++ b/arch/arm/src/armv7-r/arm.h @@ -42,39 +42,6 @@ /* ARMv7-R ******************************************************************/ -/* PSR bits */ - -#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ -#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) -# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ -# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ -# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ -# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ -# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ -# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ -# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ - -#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ -#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ -#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) -# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ -# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ -# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ -#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ -#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */ -#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT) -#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ -#define PSR_GE_MASK (15 << PSR_GE_SHIFT) - /* Bits 20-23: Reserved. RAZ/SBZP */ -#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ -#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ -#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) -#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ -#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ -#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ -#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ -#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ - /**************************************************************************** * Inline Functions ****************************************************************************/ diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index cd298688dc91d..ab821d988e2bc 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -24,7 +24,7 @@ #include -#include "arm.h" +#include #include "cp15.h" #include "sctlr.h" #include "arm_internal.h" diff --git a/arch/arm/src/armv8-r/arm.h b/arch/arm/src/armv8-r/arm.h index 041ba84a99546..227ca0ddef8f8 100644 --- a/arch/arm/src/armv8-r/arm.h +++ b/arch/arm/src/armv8-r/arm.h @@ -51,40 +51,6 @@ /* ARMv8-R ******************************************************************/ -/* PSR bits */ - -#define PSR_MODE_SHIFT (0) /* Bits 0-4: Mode fields */ -#define PSR_MODE_MASK (31 << PSR_MODE_SHIFT) -# define PSR_MODE_USR (16 << PSR_MODE_SHIFT) /* User mode */ -# define PSR_MODE_FIQ (17 << PSR_MODE_SHIFT) /* FIQ mode */ -# define PSR_MODE_IRQ (18 << PSR_MODE_SHIFT) /* IRQ mode */ -# define PSR_MODE_SVC (19 << PSR_MODE_SHIFT) /* Supervisor mode */ -# define PSR_MODE_ABT (23 << PSR_MODE_SHIFT) /* Abort mode */ -# define PSR_MODE_HYP (26 << PSR_MODE_SHIFT) /* Hypervisor mode */ -# define PSR_MODE_UND (27 << PSR_MODE_SHIFT) /* Undefined mode */ -# define PSR_MODE_SYS (31 << PSR_MODE_SHIFT) /* System mode */ - -#define PSR_T_BIT (1 << 5) /* Bit 5: Thumb execution state bit */ -#define PSR_MASK_SHIFT (6) /* Bits 6-8: Mask Bits */ -#define PSR_MASK_MASK (7 << PSR_GE_SHIFT) -# define PSR_F_BIT (1 << 6) /* Bit 6: FIQ mask bit */ -# define PSR_I_BIT (1 << 7) /* Bit 7: IRQ mask bit */ -# define PSR_A_BIT (1 << 8) /* Bit 8: Asynchronous abort mask */ -#define PSR_E_BIT (1 << 9) /* Bit 9: Endianness execution state bit */ -#define PSR_IT27_SHIFT (10) /* Bits 10-15: If-Then execution state bits IT[2:7] */ -#define PSR_IT27_MASK (0x3f << PSR_IT27_SHIFT) -#define PSR_GE_SHIFT (16) /* Bits 16-19: Greater than or Equal flags */ -#define PSR_GE_MASK (15 << PSR_GE_SHIFT) - /* Bits 20-23: Reserved. RAZ/SBZP */ -#define PSR_J_BIT (1 << 24) /* Bit 24: Jazelle state bit */ -#define PSR_IT01_SHIFT (25) /* Bits 25-26: If-Then execution state bits IT[0:1] */ -#define PSR_IT01_MASK (3 << PSR_IT01_SHIFT) -#define PSR_Q_BIT (1 << 27) /* Bit 27: Cumulative saturation bit */ -#define PSR_V_BIT (1 << 28) /* Bit 28: Overflow condition flag */ -#define PSR_C_BIT (1 << 29) /* Bit 29: Carry condition flag */ -#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */ -#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */ - /**************************************************************************** * Inline Functions ****************************************************************************/ diff --git a/arch/arm/src/armv8-r/arm_head.S b/arch/arm/src/armv8-r/arm_head.S index 16819dc32c824..81f9e247d2668 100644 --- a/arch/arm/src/armv8-r/arm_head.S +++ b/arch/arm/src/armv8-r/arm_head.S @@ -24,7 +24,7 @@ #include -#include "arm.h" +#include #include "cp15.h" #include "cp15_cacheops.h" #include "sctlr.h" diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h index 79cca7308bfc5..5e4e8bbb53334 100644 --- a/arch/arm64/include/irq.h +++ b/arch/arm64/include/irq.h @@ -39,6 +39,7 @@ /* Include NuttX-specific IRQ definitions */ #include +#include /* Include chip-specific IRQ definitions (including IRQ numbers) */ @@ -220,6 +221,29 @@ #define XCPTCONTEXT_REGS (XCPTCONTEXT_GP_REGS + XCPTCONTEXT_FPU_REGS) #define XCPTCONTEXT_SIZE (8 * XCPTCONTEXT_REGS) +#define DAIFSET_FIQ_BIT BIT(0) +#define DAIFSET_IRQ_BIT BIT(1) +#define DAIFSET_ABT_BIT BIT(2) +#define DAIFSET_DBG_BIT BIT(3) + +#define DAIFCLR_FIQ_BIT BIT(0) +#define DAIFCLR_IRQ_BIT BIT(1) +#define DAIFCLR_ABT_BIT BIT(2) +#define DAIFCLR_DBG_BIT BIT(3) + +#define DAIF_FIQ_BIT BIT(6) +#define DAIF_IRQ_BIT BIT(7) +#define DAIF_ABT_BIT BIT(8) +#define DAIF_DBG_BIT BIT(9) + +#define DAIF_MASK (0xf << 6) + +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE +# define up_irq_is_disabled(flags) (((flags) & DAIF_FIQ_BIT) != 0) +#else +# define up_irq_is_disabled(flags) (((flags) & DAIF_IRQ_BIT) != 0) +#endif + #ifndef __ASSEMBLY__ #ifdef __cplusplus diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h index facf2da475ba9..a48a1bd36b891 100644 --- a/arch/arm64/src/common/arm64_arch.h +++ b/arch/arm64/src/common/arm64_arch.h @@ -52,23 +52,6 @@ #define BIT_MASK(n) (BIT(n) - 1) #define BIT64_MASK(n) (BIT64(n) - 1ULL) -#define DAIFSET_FIQ_BIT BIT(0) -#define DAIFSET_IRQ_BIT BIT(1) -#define DAIFSET_ABT_BIT BIT(2) -#define DAIFSET_DBG_BIT BIT(3) - -#define DAIFCLR_FIQ_BIT BIT(0) -#define DAIFCLR_IRQ_BIT BIT(1) -#define DAIFCLR_ABT_BIT BIT(2) -#define DAIFCLR_DBG_BIT BIT(3) - -#define DAIF_FIQ_BIT BIT(6) -#define DAIF_IRQ_BIT BIT(7) -#define DAIF_ABT_BIT BIT(8) -#define DAIF_DBG_BIT BIT(9) - -#define DAIF_MASK (0xf << 6) - /* Arm® Architecture Registers Armv8, for Armv8-A architecture profile * ( DDI 0595, ID121321 ), defined: * diff --git a/arch/arm64/src/common/arm64_head.S b/arch/arm64/src/common/arm64_head.S index 53ceeb93c4b97..5d56fbc3c3402 100644 --- a/arch/arm64/src/common/arm64_head.S +++ b/arch/arm64/src/common/arm64_head.S @@ -26,6 +26,7 @@ #include #include +#include #include "arm64_arch.h" #include "arm64_internal.h" #include "arm64_macro.inc" diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index cb12637720baa..67f444985b4cf 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -555,6 +555,8 @@ # define REG_FS11 REG_F27 #endif +#define up_irq_is_disabled(flags) (((flags) & STATUS_IE) != 0) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index f5c71856b6236..2c7399c36f936 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -156,6 +156,8 @@ #define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) +#define up_irq_is_disabled(flags) (((flags) & XCHAL_IRQ_LEVEL) != 0) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 7909f58cd74ef..ee112c0a74a63 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -366,6 +366,27 @@ inline_function irqstate_t enter_critical_section_nonirq(void) } else { + /* CHECK IRQ + * + * After the OS starts, in the thread context, + * we must ensure that the interrupt is not masked + * when first enters the critical section. + * Otherwise, at this time when another CPU issues a pause + * interrupt to the current CPU, it can lead to a deadlock. + * + * During the vela os startup phase, interrupts are masked until + * the interrupt initialization function (irq_initialize) is called. + * Before invoking the interrupt initialization function, + * umm_initialize will call enter_critical_section, + * during which time interrupts are masked. + * Therefore, we need to use OSINIT_IDLELOOP + * as a condition for judgment at this point. + */ + +#ifdef up_irq_is_disabled + DEBUGASSERT(is_idle_task(rtcb) || !up_irq_is_disabled(ret)); +#endif + /* If we get here with irqcount == 0, then we know that the * current task running on this CPU is not in a critical * section. However other tasks on other CPUs may be in a