From 60c1d7db5eb5788c77f9a72330206d0e127ef5b0 Mon Sep 17 00:00:00 2001 From: Daniel Sudzilouski Date: Thu, 11 Jan 2024 15:57:03 -0500 Subject: [PATCH] ari integrated test file works --- src/asm/ari_2.s | 72 +++++++++---------- src/asm/out/storeload_2.memh | 23 ++++-- src/asm/storeload_2.s | 31 ++++++-- src/asm/test/ari_2.result | 4 +- src/asm/test/storeload_2.result | 10 +-- .../src/cpu/rv32i_multicycle_core.sv | 4 +- 6 files changed, 87 insertions(+), 57 deletions(-) diff --git a/src/asm/ari_2.s b/src/asm/ari_2.s index 034a929..3c8d9de 100644 --- a/src/asm/ari_2.s +++ b/src/asm/ari_2.s @@ -72,39 +72,39 @@ nop trap: beq x0, x0, trap -|---------------------------------------| -| Register File State | -|---------------------------------------| -| x00, zero = 0x00000000 ( 0)| -| x01, ra = 0xffffffff ( -1)| -| x02, sp = 0x00000023 ( 35)| -| x03, gp = 0x00000067 ( 103)| -| x04, tp = 0x00000033 ( 51)| -| x05, t0 = 0x00000001 ( 1)| -| x06, t1 = 0xffffff00 ( -256)| -| x07, t2 = 0x00000019 ( 25)| -| x08, s0 = 0xffffff93 ( -109)| -| x09, s1 = 0x00000093 ( 147)| -| x10, a0 = 0xffff9313 ( -27885)| -| x11, a1 = 0x00009313 ( 37651)| -| x12, a2 = 0x00000000 ( 0)| -| x13, a3 = 0xffffffff ( -1)| -| x14, a4 = 0x00000067 ( 103)| -| x15, a5 = 0x00000023 ( 35)| -| x16, a6 = 0x00000004 ( 4)| -| x17, a7 = 0x00000230 ( 560)| -| x18, s2 = 0x00000006 ( 6)| -| x19, s3 = 0xfffffff0 ( -16)| -| x20, s4 = 0x00000001 ( 1)| -| x21, s5 = 0x000000d4 ( 212)| -| x22, s6 = 0x008000d8 ( 8388824)| -| x23, s7 = 0x0a455000 ( 172314624)| -| x24, s8 = 0x93130104 (-1827471100)| -| x25, s9 = 0x00000104 ( 260)| -| x26, s10 = 0x00000045 ( 69)| -| x27, s11 = 0x0000000c ( 12)| -| x28, t3 = 0x00000064 ( 100)| -| x29, t4 = 0x000001a4 ( 420)| -| x30, t5 = 0x00000045 ( 69)| -| x31, t6 = 0x00809313 ( 8426259)| -|---------------------------------------| \ No newline at end of file +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x02, sp = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x03, gp = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x04, tp = 0x00000033 ( 51)| +#TESTASSERTOUTPUT| x05, t0 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x06, t1 = 0xffffff00 ( -256)| +#TESTASSERTOUTPUT| x07, t2 = 0x00000019 ( 25)| +#TESTASSERTOUTPUT| x08, s0 = 0xffffff93 ( -109)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000093 ( 147)| +#TESTASSERTOUTPUT| x10, a0 = 0xffff9313 ( -27885)| +#TESTASSERTOUTPUT| x11, a1 = 0x00009313 ( 37651)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x13, a3 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x14, a4 = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000004 ( 4)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000230 ( 560)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000006 ( 6)| +#TESTASSERTOUTPUT| x19, s3 = 0xfffffff0 ( -16)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x21, s5 = 0x000000d4 ( 212)| +#TESTASSERTOUTPUT| x22, s6 = 0x008000d8 ( 8388824)| +#TESTASSERTOUTPUT| x23, s7 = 0x0a455000 ( 172314624)| +#TESTASSERTOUTPUT| x24, s8 = 0x93130104 (-1827471100)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000104 ( 260)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000045 ( 69)| +#TESTASSERTOUTPUT| x27, s11 = 0x0000000c ( 12)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000064 ( 100)| +#TESTASSERTOUTPUT| x29, t4 = 0x000001a4 ( 420)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000045 ( 69)| +#TESTASSERTOUTPUT| x31, t6 = 0x00809313 ( 8426259)| +#TESTASSERTOUTPUT|---------------------------------------| \ No newline at end of file diff --git a/src/asm/out/storeload_2.memh b/src/asm/out/storeload_2.memh index 266a694..87463c7 100644 --- a/src/asm/out/storeload_2.memh +++ b/src/asm/out/storeload_2.memh @@ -1,8 +1,19 @@ 0ff00093 // PC=0x0 line=1: addi x1, x0, 255 # x01 = 255 (32'b00000000000000000000000011111111) 40000113 // PC=0x4 line=2: addi x2, x0, 1024 # x02 = 1024 -00112023 // PC=0x8 line=3: sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) -00010183 // PC=0xc line=4: lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) -00011203 // PC=0x10 line=5: lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) -00012283 // PC=0x14 line=6: lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) -00014303 // PC=0x18 line=7: lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) -00015383 // PC=0x1c line=8: lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) +00112023 // PC=0x8 line=3: sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) +00010183 // PC=0xc line=4: lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) +00011203 // PC=0x10 line=5: lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) +00012283 // PC=0x14 line=6: lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) +00014303 // PC=0x18 line=7: lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) +00015383 // PC=0x1c line=8: lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) +fff00513 // PC=0x20 line=11: addi x10, x0, -1 # x10 = -1 (32'b11111111111111111111111111111111) +40400593 // PC=0x24 line=12: addi x11, x0, 1028 # x11 = 1028 +00000613 // PC=0x28 line=15: addi x12, x0, 0 # x12 = 0 (32'b00000000000000000000000000000000) +00000693 // PC=0x2c line=16: addi x13, x0, 0 # x13 = 0 (32'b00000000000000000000000000000000) +00000713 // PC=0x30 line=17: addi x14, x0, 0 # x14 = 0 (32'b00000000000000000000000000000000) +00a5a023 // PC=0x34 line=20: sw x10, 0(x11) # (MEM:1028) = -1 (32'b11111111111111111111111111111111) +00a59223 // PC=0x38 line=21: sh x10, 4(x11) # (MEM:1032) = 65535 (32'b00000000000000001111111111111111) +00a58423 // PC=0x3c line=22: sb x10, 8(x11) # (MEM:1036) = 255 (32'b00000000000000000000000011111111) +0005a603 // PC=0x40 line=25: lw x12, 0(x11) # x12 = -1 (32'b11111111111111111111111111111111) +0045a683 // PC=0x44 line=26: lw x13, 4(x11) # x13 = -1 (32'b11111111111111111111111111111111) +0085a703 // PC=0x48 line=27: lw x14, 8(x11) # x14 = -1 (32'b11111111111111111111111111111111) diff --git a/src/asm/storeload_2.s b/src/asm/storeload_2.s index 43c0c4b..25bbaf0 100644 --- a/src/asm/storeload_2.s +++ b/src/asm/storeload_2.s @@ -1,11 +1,30 @@ addi x1, x0, 255 # x01 = 255 (32'b00000000000000000000000011111111) addi x2, x0, 1024 # x02 = 1024 -sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) -lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) -lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) -lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) -lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) -lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) +sw x1, 0(x2) # (MEM:1024) = 255 (32'b00000000000000000000000011111111) +lb x3, 0(x2) # x03 = -1 (32'b11111111111111111111111111111111) +lh x4, 0(x2) # x04 = 255 (32'b00000000000000000000000011111111) +lw x5, 0(x2) # x05 = 255 (32'b00000000000000000000000011111111) +lbu x6, 0(x2) # x06 = 255 (32'b00000000000000000000000011111111) +lhu x7, 0(x2) # x07 = 255 (32'b00000000000000000000000011111111) + +# test partial stores +addi x10, x0, -1 # x10 = -1 (32'b11111111111111111111111111111111) +addi x11, x0, 1028 # x11 = 1028 + +# zero out the memory +addi x12, x0, 0 # x12 = 0 (32'b00000000000000000000000000000000) +addi x13, x0, 0 # x13 = 0 (32'b00000000000000000000000000000000) +addi x14, x0, 0 # x14 = 0 (32'b00000000000000000000000000000000) + +# store partial +sw x10, 0(x11) # (MEM:1028) = -1 (32'b11111111111111111111111111111111) +sh x10, 4(x11) # (MEM:1032) = 65535 (32'b00000000000000001111111111111111) +sb x10, 8(x11) # (MEM:1036) = 255 (32'b00000000000000000000000011111111) + +# read full +lw x12, 0(x11) # x12 = -1 (32'b11111111111111111111111111111111) +lw x13, 4(x11) # x13 = -1 (32'b11111111111111111111111111111111) +lw x14, 8(x11) # x14 = -1 (32'b11111111111111111111111111111111) #TESTASSERTOUTPUT|---------------------------------------| diff --git a/src/asm/test/ari_2.result b/src/asm/test/ari_2.result index ba0d8d3..b48284b 100644 --- a/src/asm/test/ari_2.result +++ b/src/asm/test/ari_2.result @@ -24,9 +24,9 @@ FST info: dumpfile rv32_simulator.fst opened for output. #TESTASSERTOUTPUT| x06, t1 = 0xffffff00 ( -256)| #TESTASSERTOUTPUT| x07, t2 = 0x00000019 ( 25)| #TESTASSERTOUTPUT| x08, s0 = 0xffffff93 ( -109)| -#TESTASSERTOUTPUT| x09, s1 = 0x93130104 (-1827471100)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000093 ( 147)| #TESTASSERTOUTPUT| x10, a0 = 0xffff9313 ( -27885)| -#TESTASSERTOUTPUT| x11, a1 = 0x93130104 (-1827471100)| +#TESTASSERTOUTPUT| x11, a1 = 0x00009313 ( 37651)| #TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x13, a3 = 0xffffffff ( -1)| #TESTASSERTOUTPUT| x14, a4 = 0x00000067 ( 103)| diff --git a/src/asm/test/storeload_2.result b/src/asm/test/storeload_2.result index c17f983..f211c9d 100644 --- a/src/asm/test/storeload_2.result +++ b/src/asm/test/storeload_2.result @@ -25,11 +25,11 @@ Ran 10000 cycles, finishing. #TESTASSERTOUTPUT| x07, t2 = 0x000000ff ( 255)| #TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x11, a1 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x13, a3 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x14, a4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x10, a0 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x11, a1 = 0x00000404 ( 1028)| +#TESTASSERTOUTPUT| x12, a2 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x13, a3 = 0xxxxxffff ( X)| +#TESTASSERTOUTPUT| x14, a4 = 0xxxxxxxff ( X)| #TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)| diff --git a/src/components/src/cpu/rv32i_multicycle_core.sv b/src/components/src/cpu/rv32i_multicycle_core.sv index f3ffea5..fdd843d 100644 --- a/src/components/src/cpu/rv32i_multicycle_core.sv +++ b/src/components/src/cpu/rv32i_multicycle_core.sv @@ -125,8 +125,8 @@ module rv32i_multicycle_core( 3'b000: mem_data_extended = {{24{mem_data[7]}}, mem_data[7:0]}; // load byte, sign extend 7:0 3'b001: mem_data_extended = {{16{mem_data[15]}}, mem_data[15:0]}; // load byte, sign extend 15:0 3'b010: mem_data_extended = mem_data; // load word, 31:0 - 3'b100: mem_data_extended = mem_data; // load byte unsigned, 7:0 (memory already masks read for us) - 3'b101: mem_data_extended = mem_data; // load half unsigned, 15:0 (memory already masks read for us) + 3'b100: mem_data_extended = {24'b0, mem_data[7:0]}; // load byte unsigned, 7:0 + 3'b101: mem_data_extended = {16'b0, mem_data[15:0]}; // load byte unsigned, 15:0 endcase end