From 5316c4e645828569e670a59be22833c2624d5a75 Mon Sep 17 00:00:00 2001 From: Daniel Sudzilouski Date: Tue, 9 Jan 2024 14:51:38 -0500 Subject: [PATCH] regression tests look good --- src/asm/irtypes.s | 24 +++++++++---------- src/asm/itypes.s | 44 +++++++++++++++++------------------ src/asm/test/irtypes.result | 40 +++++++++++++++++++++++++++++++ src/asm/test/storeload.result | 40 +++++++++++++++++++++++++++++++ src/asm/validate.js | 13 ++++++++--- src/components/Makefile | 2 +- 6 files changed, 125 insertions(+), 38 deletions(-) create mode 100644 src/asm/test/irtypes.result create mode 100644 src/asm/test/storeload.result diff --git a/src/asm/irtypes.s b/src/asm/irtypes.s index 98cf016..6d6c27f 100644 --- a/src/asm/irtypes.s +++ b/src/asm/irtypes.s @@ -20,7 +20,7 @@ sra x19, x6, x16 # x19 = -16 slt x20, x1, x2 # x20 = 1 sltu x21, x1, x2 # x20 = 0 #TESTASSERTOUTPUT|---------------------------------------| -#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT| Register File State :) | #TESTASSERTOUTPUT|---------------------------------------| #TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| #TESTASSERTOUTPUT| x01, ra = 0xffffffff ( -1)| @@ -44,14 +44,14 @@ sltu x21, x1, x2 # x20 = 0 #TESTASSERTOUTPUT| x19, s3 = 0xfffffff0 ( -16)| #TESTASSERTOUTPUT| x20, s4 = 0x00000001 ( 1)| #TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| -#TESTASSERTOUTPUT| x22, s6 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x23, s7 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x24, s8 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x25, s9 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x26, s10 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x27, s11 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x28, t3 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x29, t4 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x30, t5 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x31, t6 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT|---------------------------------------| \ No newline at end of file +#TESTASSERTIGNORE| x22, s6 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x23, s7 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x24, s8 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x25, s9 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x26, s10 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x27, s11 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x28, t3 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x29, t4 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x30, t5 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x31, t6 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE|---------------------------------------| \ No newline at end of file diff --git a/src/asm/itypes.s b/src/asm/itypes.s index 479fb42..4edaa7c 100644 --- a/src/asm/itypes.s +++ b/src/asm/itypes.s @@ -22,25 +22,25 @@ andi x9, x8, 100 #TESTASSERTOUTPUT| x08, s0 = 0x000007fc ( 2044)| #TESTASSERTOUTPUT| x09, s1 = 0x00000064 ( 100)| #TESTASSERTOUTPUT| x10, a0 = 0xfffffff0 ( -16)| -#TESTASSERTOUTPUT| x11, a1 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x12, a2 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x13, a3 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x14, a4 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x15, a5 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x16, a6 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x17, a7 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x18, s2 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x19, s3 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x20, s4 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x21, s5 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x22, s6 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x23, s7 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x24, s8 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x25, s9 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x26, s10 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x27, s11 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x28, t3 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x29, t4 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x30, t5 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT| x31, t6 = 0xxxxxxxxx ( x)| -#TESTASSERTOUTPUT|---------------------------------------| \ No newline at end of file +#TESTASSERTIGNORE| x11, a1 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x12, a2 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x13, a3 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x14, a4 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x15, a5 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x16, a6 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x17, a7 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x18, s2 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x19, s3 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x20, s4 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x21, s5 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x22, s6 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x23, s7 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x24, s8 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x25, s9 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x26, s10 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x27, s11 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x28, t3 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x29, t4 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x30, t5 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE| x31, t6 = 0xxxxxxxxx ( x)| +#TESTASSERTIGNORE|---------------------------------------| \ No newline at end of file diff --git a/src/asm/test/irtypes.result b/src/asm/test/irtypes.result new file mode 100644 index 0000000..68fc770 --- /dev/null +++ b/src/asm/test/irtypes.result @@ -0,0 +1,40 @@ +WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/irtypes.memh): Not enough words in the file for the requested range [0:1023]. +Running simulation of memory ../asm/out/irtypes.memh for up to 100 cycles. Waves will be stored to rv32_simulator.fst. +FST info: dumpfile rv32_simulator.fst opened for output. +Ran 100 cycles, finishing. +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x02, sp = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x03, gp = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x04, tp = 0x00000033 ( 51)| +#TESTASSERTOUTPUT| x05, t0 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x06, t1 = 0xffffff00 ( -256)| +#TESTASSERTOUTPUT| x07, t2 = 0x00000019 ( 25)| +#TESTASSERTOUTPUT| x08, s0 = 0xfffffffc ( -4)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x11, a1 = 0xfffffffe ( -2)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x13, a3 = 0xffffffff ( -1)| +#TESTASSERTOUTPUT| x14, a4 = 0x00000067 ( 103)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000023 ( 35)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000004 ( 4)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000230 ( 560)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000006 ( 6)| +#TESTASSERTOUTPUT| x19, s3 = 0xfffffff0 ( -16)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000001 ( 1)| +#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT|---------------------------------------| diff --git a/src/asm/test/storeload.result b/src/asm/test/storeload.result new file mode 100644 index 0000000..beb21b1 --- /dev/null +++ b/src/asm/test/storeload.result @@ -0,0 +1,40 @@ +WARNING: ./tests/provided/bytewise_distributed_ram.sv:58: $readmemh(../asm/out/storeload.memh): Not enough words in the file for the requested range [0:1023]. +Running simulation of memory ../asm/out/storeload.memh for up to 100 cycles. Waves will be stored to rv32_simulator.fst. +FST info: dumpfile rv32_simulator.fst opened for output. +Ran 100 cycles, finishing. +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| Register File State :) | +#TESTASSERTOUTPUT|---------------------------------------| +#TESTASSERTOUTPUT| x00, zero = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x01, ra = 0xffffff9c ( -100)| +#TESTASSERTOUTPUT| x02, sp = 0x00000400 ( 1024)| +#TESTASSERTOUTPUT| x03, gp = 0xffffff9c ( -100)| +#TESTASSERTOUTPUT| x04, tp = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x05, t0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x06, t1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x07, t2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x08, s0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x09, s1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x10, a0 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x11, a1 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x12, a2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x13, a3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x14, a4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x15, a5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x16, a6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x17, a7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x18, s2 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x19, s3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x20, s4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x21, s5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x22, s6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x23, s7 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x24, s8 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x25, s9 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x26, s10 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x27, s11 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x28, t3 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x29, t4 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x30, t5 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT| x31, t6 = 0x00000000 ( 0)| +#TESTASSERTOUTPUT|---------------------------------------| diff --git a/src/asm/validate.js b/src/asm/validate.js index e813026..a284c69 100644 --- a/src/asm/validate.js +++ b/src/asm/validate.js @@ -13,18 +13,25 @@ let expected = fs.readFileSync( path.resolve(__dirname, expected_file), { encoding: 'utf8', flag: 'r' }) .toString() .split("\n") - .filter(line => line.includes("TESTASSERTOUTPUT")); + .filter(line => line.includes("TESTASSERTOUTPUT") || line.includes("TESTASSERTIGNORE")); let actual = fs.readFileSync( path.resolve(__dirname, actual_file), { encoding: 'utf8', flag: 'r' }) .toString() .split("\n") - .filter(line => line.includes("TESTASSERTOUTPUT")); + .filter(line => line.includes("TESTASSERTOUTPUT") || line.includes("TESTASSERTIGNORE")); for(let i = 0; i < expected.length; i++) { console.log(expected[i]) console.log(actual[i]); - if(expected[i] != actual[i]) { + if(expected[i].includes("TESTASSERTIGNORE")) { + // pass + } + else if(i == actual.length) { + console.error("[ERROR] FAILED TO ASSERT REGISTER FILE STATE NOT ENOUGH LINES!!!!!!!"); + } + else if(expected[i] != actual[i]) { + console.error("[ERROR] FAILED TO ASSERT REGISTER FILE STATE !!!!!!!"); process.exit(1); } diff --git a/src/components/Makefile b/src/components/Makefile index ddb4a5b..44a6a4b 100644 --- a/src/components/Makefile +++ b/src/components/Makefile @@ -103,7 +103,7 @@ rv32_simulator: tests/provided/rv32_simulator.sv src/**/*.sv # Validates that the simulator output is as expected %.validate: %.result - node ../asm/validate.js test/$< $(basename $<).s + node ../asm/validate.js $(basename $<).s test/$< test_rv32_all: itypes.validate irtypes.validate storeload.validate