A four-issue, out of order RISC-V processor core for computer organization 2023 fall in THU CST.
Three integer dispatch queues and one store-load dispatch queue.
Support RV32I, with Exception Flow and Sv32 Page Table.
The best test case yields an IPC (Instructions Per Cycle) of 2.3.
A more detailed README and architectural design documents will be supplemented later.
PS: Its name tree-diagram comes from a supercomputer in a anime とある魔術の禁書目録.