-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathI8080InstrInfo.td
285 lines (245 loc) · 9.38 KB
/
I8080InstrInfo.td
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
//===-- I8080InstrInfo.td - Target Description for I8080 -----------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the I8080 instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
include "I8080InstrFormats.td"
//===============================
// ALU_r Instructions
// Format: 0b(xxxxx)(sss)
// Where: x => Opcode
// s => Register ID
//===============================
// ADD (Reg): 0b10000SSS
def ADD_r : I8080ALU_rInst<0b10000, "add", add>;
// //==========================
// // R Type Instructions
// //==========================
// def ADD : RTypeInstr<0b0000, "add",
// [(set i32:$dr, (add i32:$sr1, i32:$sr2))]> {
// let isAdd = 1;
// }
// def NAND: RTypeInstr<0b0001, "nand",
// [(set (i32 GRRegs:$dr), (xor (xor (i32 GRRegs:$sr1), (xor (i32 GRRegs:$sr1), (i32 GRRegs:$sr2))), (xor (i32 GRRegs:$sr2), (xor (i32 GRRegs:$sr1), (i32 GRRegs:$sr2)))))]>;
// //=========================
// // I Type Instruction
// //==========================
// def ADDI : ITypeInstr<0b0010, (outs GRRegs:$dst), (ins GRRegs:$src1, I8080imm20:$imm),
// "addi", "$dst, $src1, $imm",
// [(set (i32 GRRegs:$dst), (add (i32 GRRegs:$src1), I8080imm20:$imm))]> {
// bits<4> dst;
// bits<4> src1;
// bits<20> imm;
// let Inst{27-24} = src1;
// let Inst{23-20} = dst;
// let Inst{19-0} = imm;
// }
// def LW: ITypeInstr<0b0011, (outs GRRegs:$dst), (ins I8080imm20:$off20, GRRegs:$base),
// "lw", "$dst, ${off20}(${base})",
// [(set (i32 GRRegs:$dst), (load (add (i32 GRRegs:$base), I8080imm20:$off20)))]> {
// bits<4> dst;
// bits<4> base;
// bits<20> off20;
// let Inst{23-20} = dst;
// let Inst{27-24} = base;
// let Inst{19-0} = off20;
// }
// def SW: ITypeInstr<0b0100, (outs GRRegs:$src1), (ins I8080imm20:$offset, GRRegs:$base),
// "sw", "$src1, ${offset}(${base})",
// [(store i32:$src1, (add (i32 GRRegs:$base), I8080imm20:$offset))]> {
// bits<4> src1;
// bits<4> base;
// bits<20> offset;
// let Inst{27-24} = base;
// let Inst{23-20} = src1;
// let Inst{19-0} = offset;
// }
// def GOTO: ITypeInstr<0b0101, (outs), (ins I8080imm20:$offset),
// "goto", "$offset",
// [(brind I8080imm20:$offset)]> {
// bits<20> offset;
// let Inst{27-24} = 0;
// let Inst{23-20} = 0;
// let Inst{19-0} = offset;
// let isBranch = 1;
// let isTerminator = 1;
// }
// def JALR: ITypeInstr<0b0101, (outs GRRegs:$dr), (ins GRRegs:$sr1),
// "jalr", "$dr, $sr1",
// []> {
// bits<4> dr;
// bits<4> sr1;
// let Inst{27-24} = dr;
// let Inst{23-20} = sr1;
// let Inst{19-0} = 0;
// let isBranch = 1;
// let isTerminator = 1;
// }
// def HALT : InstI8080<(outs), (ins), 0b0111, "halt", "", []> {
// let Inst{27-0} = 0;
// let isTerminator = 1;
// let hasSideEffects = 1;
// }
// def SKPE : SKPTypeInstr<0b1000, 0b0000, "skpe", []>;
// def SKPLT : SKPTypeInstr<0b1000, 0b0001, "skplt", []>;
// def LEA: ITypeInstr<0b1001, (outs GRRegs:$dr), (ins I8080imm20:$offset),
// "lea", "$dr, $offset",
// [(set i32:$dr, (add pc, I8080imm20:$offset))]> {
// bits<4> dr;
// bits<20> offset;
// let Inst{27-24} = dr;
// let Inst{23-20} = 0;
// let Inst{19-0} = offset;
// let isAdd = 1;
// }
// def BEQ: ITypeInstr<0b0100, (outs SRCRegs:$src1), (ins SRCRegs:$src2, i32imm:$pcoffset),
// "BEQ $src1, $src2, $pcoffset",
// [(BR_CC, i32:$src1, i32:$src2, I8080imm20:$pcoffset))]> { // pcoffset?? (add $pc, offset, 1???)
// bits<4> src1;
// bits<4> src2;
// bits<20> pcoffset;
// let Inst{27-24} = src1;
// let Inst{23-20} = src2;
// let Inst{19-0} = pcoffset;
// }
//===----------------------------------------------------------------------===//
// ALU Instructions
//===----------------------------------------------------------------------===//
// multiclass BinOp<bits<4> opcode, string opstr, SDNode opnode> {
// def rr : ALUInst<opcode, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
// !strconcat(opstr, " $dst, $src1, $src2"),
// [(set i16:$dst, (opnode i16:$src1, i16:$src2))]> {
// bits<4> dst;
// bits<4> src1;
// bits<4> src2;
// let Inst{5} = 0;
// let Inst{7-6} = 0b00;
// let Inst{11-9} = dst;
// let Inst{8-6} = src1;
// let Inst{2-0} = src2;
// }
// def ri : ALUInst<opcode, (outs GRRegs:$dst), (ins GRRegs:$src1, i16imm:$imm),
// !strconcat(opstr, " $dst, $src1, $imm"),
// [(set i16:$dst, (opnode i16:$src1, I8080imm5:$imm))]> {
// bits<3> dst;
// bits<3> src1;
// bits<5> imm;
// let Inst{5} = 1;
// let Inst{11-9} = dst;
// let Inst{8-6} = src1;
// let Inst{4-0} = imm;
// }
// }
// defm ADD : BinOp<0b0001, "add", add>;
// defm AND : BinOp<0b0101, "and", and>;
//===----------------------------------------------------------------------===//
// Load/Store Instructions
//===----------------------------------------------------------------------===//
// def LD : InstI8080<(outs GRRegs:$val), (ins memsrc:$addr),
// "ld $val, $addr",
// [(set i16:$val, (load addr:$addr))]> {
// bits<3> val;
// bits<9> addr;
// let Inst{15-12} = 0b0010;
// let Inst{11-9} = val;
// let Inst{8-0} = addr;
// }
//def ST : InstI8080<(outs), (ins GRRegs:$val, memsrc:$addr),
// "st $val, $addr",
// [(store i16:$val, addr:$addr)] {
// bits<3> val;
// bits<9> addr;
// let Inst{15-12} = 0b0011;
// let Inst{11-9} = val;
// let Inst{8-0} = addr;
// }
// def LDR : InstI8080<(outs GRRegs:$val), (ins GRRegs:$src1, i16imm:$imm),
// "ldr $val, $src1, $imm",
// [(set i16:$val, (load (add addr:$src1, addr:$imm)))]> {
// bits<3> val;
// bits<3> src1; //Base Register
// bits<6> addr;
// let Inst{15-12} = 0b0110;
// let Inst{11-9} = val;
// let Inst{8-6} = src1;
// let Inst{5-0} = addr;
// }
// def STR : InstI8080<(outs GRRegs:$val), (ins GRRegs:$src1, i16imm:$imm),
// "str $val, $src1, $imm",
// [(store i16:$val, (add addr:$src1, addr:$imm))]> {
// bits<3> val;
// bits<3> src1; //Base Register
// bits<6> addr;
// let Inst{15-12} = 0b0110;
// let Inst{11-9} = val;
// let Inst{8-6} = src1;
// let Inst{5-0} = addr;
// }
// def LDI : InstI8080<(outs GRRegs:$val), (ins memsrc:$addr),
// "ldi $val, $addr",
// [(set i16:$val, (load (load addr:$addr)))]> {
// bits<3> val;
// bits<9> addr;
// let Inst{15-12} = 0b0010;
// let Inst{11-9} = val;
// let Inst{8-0} = addr;
// }
//===----------------------------------------------------------------------===//
// Return Instructions
//===----------------------------------------------------------------------===//
// let isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [LR] in {
// def RET : InstI8080<(outs), (ins variable_ops),
// "bx lr", [(I8080RetFlag)]> {
// let Inst{27-0} = 0b0001001011111111111100011110;
// }
// }
//===----------------------------------------------------------------------===//
// Call Instructions
//===----------------------------------------------------------------------===//
// JSR
// let isCall = 1, Defs = [LR], Uses = [SP] in {
// def BL : BranchInst<0b1011, (outs), (ins GRRegs:$addr),
// "bl $addr",
// [(lc3_call i16:$addr)]> {
// bits<4> addr;
// let Inst{31-28} = 0b1110;
// let Inst{3-0} = addr;
// }
// }
// def : Pattern<(i32 (load_sym tglobaladdr:$addr)), [(MOVi32 $addr)]>;
//===----------------------------------------------------------------------===//
//Branch Instructions
//===----------------------------------------------------------------------===//
// let isTerminator = 1, isBranch = 1, isBarrier = 1 in {
// def B : InstI8080<(outs), (ins b_target:$dst),
// "brnzp $dst", [(br bb:$dst)]> {
// bits<9> dst;
// bits<3> cc;
// let Inst{15-12} = 0b0000;
// let Inst{11-9} = 0b111;
// let Inst{8-0} = dst;
// }
// }
//let isTerminator = 1, isBranch = 1, Uses = [CPSR] in {
// def Bcc : InstI8080<(outs), (ins cc_val:$cc, b_target:$dst),
// "br$cc, $dst", []> {
// }
//}
//===----------------------------------------------------------------------===//
// Pseudo Instructions
//===----------------------------------------------------------------------===//
// let Defs = [R7], Uses = [R7] in {
// def ADJCALLSTACKDOWN : I8080PseudoInst<(outs), (ins i16imm:$amt),
// "# ADJCALLSTACKDOWN $amt",
// [(callseq_start timm:$amt)]>;
// def ADJCALLSTACKUP : I8080PseudoInst<(outs), (ins i16imm:$amt1, i16imm:$amt2),
// "# ADJCALLSTACKUP $amt1",
// [(callseq_end timm:$amt1, timm:$amt2)]>;
// }