SYZYGY is an FPGA expansion standard for medium to high speed interfaces. Learn more and check out the specifications here: https://syzygyfpga.io/
All 12 I/O pins broken out to a 0.1" header. All 4 TX/RX lanes and ref clock broken out to SMA connections
kicad-src: KiCad v6 source files
production:
- Gerbers: [project]_gerbers.zip
- Schematic: [project].pdf
- Board render: [project].png
