Input and output size of Vivado HLS generated model #985
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Hi @Stefanvanaardt , I am in your same situation. Did you find a solution for interpreting the vhdl signals in Vivado and for creating a testbench? Thank you, Gio |
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Good day,
I have a model of the following shape:
This is correctly reflected in the parameters.h file:
first input dense layer:
and output layer:
When building the model and importing to Vivado, the input layer (looking at "...solution/imp/vhdl/myproject.vhd") is now of the size (1535 downto 0):
input_2_V : IN STD_LOGIC_VECTOR (1535 downto 0);
and output consists of multiple outputs of size (5 downto 0) as well as individual output bits.
so the combined output size is the above (1535 downto 0)
There are also additional input and outputs created. I am not sure why there are two types of IO created and the size relation of the two:
The intended data in which the model was created and tested was for 256 bits to be input to the network and 256 bits again be output from the network.
The above has resulted in input and output sizes of 4096 bits as well, this leads me to believe it is related to the reuse factor or something similar which I am not understanding.
So I failing to understand the input and output shape of the HDL model and the method to control this.
If anyone could assist I would be very grateful.
If it helps, I have the following configuration:
Strategy: Resource - to allow for large network size
BramFactor: 1000000000
IOType: io_parallel
Kind regards,
Stefan
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