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tile_type_RIOI.json
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{
"pips": {
"RIOI.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY1_OFDLY0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP0_0"
},
"RIOI.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY0_OFDLY0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP0_1"
},
"RIOI.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY1_OFDLY1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP1_0"
},
"RIOI.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY0_OFDLY1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP1_1"
},
"RIOI.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ODELAY1_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP2_0"
},
"RIOI.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ODELAY0_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP2_1"
},
"RIOI.IOI_BYP3_0->IOI_IMUX_RC0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR0_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_0"
},
"RIOI.IOI_BYP3_1->IOI_IMUX_RC3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE3_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP3_1"
},
"RIOI.IOI_BYP4_0->IOI_IMUX_RC1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR1_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CLR2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_0"
},
"RIOI.IOI_BYP4_1->IOI_IMUX_RC2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IMUX_RC2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_RCLK_DIV_CE2_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP4_1"
},
"RIOI.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY1_OFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP5_0"
},
"RIOI.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_ODELAY0_OFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP5_1"
},
"RIOI.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY1_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP6_0"
},
"RIOI.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_IDELAY0_CINVCTRL",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP6_1"
},
"RIOI.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_IDELAY1_IFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP7_0"
},
"RIOI.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "RIOI_IDELAY0_IFDLY2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_BYP7_1"
},
"RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC1_CLKDIV",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "IOI_CLK0_0"
},
"RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "IOI_ILOGIC1_CLKDIVP",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
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},
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},
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