Reset active by default on Nexys A7

[davidmallasen]

On the Nexys A7, @luispimo realized that the jtag_trst_ni is connected to switch 0, so than reset is active by default.

x-heep/hw/fpga/constraints/nexys/pin_assign.xdc

Line 24 in 2c6d7d8

set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS33} [get_ports {jtag_trst_ni}]; #IO_L24N_T3_RS0_15 Sch=sw[0]

This can be confusing unless you read the pin assign, so we could either fix this by mapping this reset to a button (high by default) or at least by documenting this in the RunOnFPGA.

[davideschiavone]

We may want to invert the polarity in the wrapper so that by default is not active, or indeed assign it to a button.

Feel free to suggest and make a modification