diff --git a/data/registers/rtc_v3.json b/data/registers/rtc_v3.json index 11fd6565ca..37e848a27f 100644 --- a/data/registers/rtc_v3.json +++ b/data/registers/rtc_v3.json @@ -528,6 +528,16 @@ "fieldset/ICSR": { "description": "Initialization control and status register", "fields": [ + { + "name": "ALRWF", + "description": "Alarm write enabled", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, { "name": "WUTWF", "description": "Wakeup timer write enabled", diff --git a/data/registers/rtc_v3l5.json b/data/registers/rtc_v3l5.json index 74fa2624e8..506c5a25c3 100644 --- a/data/registers/rtc_v3l5.json +++ b/data/registers/rtc_v3l5.json @@ -512,6 +512,16 @@ "fieldset/ICSR": { "description": "Initialization control and status register", "fields": [ + { + "name": "ALRWF", + "description": "Alarm write enabled", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, { "name": "WUTWF", "description": "Wakeup timer write flag", diff --git a/data/registers/rtc_v3u5.json b/data/registers/rtc_v3u5.json index 144f1eacb8..735ff793de 100644 --- a/data/registers/rtc_v3u5.json +++ b/data/registers/rtc_v3u5.json @@ -557,6 +557,16 @@ "fieldset/ICSR": { "description": "Initialization control and status register", "fields": [ + { + "name": "ALRWF", + "description": "Alarm write enabled", + "bit_offset": 0, + "bit_size": 1, + "array": { + "len": 2, + "stride": 1 + } + }, { "name": "WUTWF", "description": "Wakeup timer write enabled", diff --git a/stm32-metapac/src/peripherals/rtc_v3.rs b/stm32-metapac/src/peripherals/rtc_v3.rs index e1546a28e6..c3dee4288d 100644 --- a/stm32-metapac/src/peripherals/rtc_v3.rs +++ b/stm32-metapac/src/peripherals/rtc_v3.rs @@ -1072,6 +1072,21 @@ pub mod regs { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Icsr(pub u32); impl Icsr { + #[doc = "Alarm write enabled"] + #[inline(always)] + pub const fn alrwf(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Alarm write enabled"] + #[inline(always)] + pub fn set_alrwf(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } #[doc = "Wakeup timer write enabled"] #[inline(always)] pub const fn wutwf(&self) -> bool { @@ -1181,6 +1196,7 @@ pub mod regs { impl core::fmt::Debug for Icsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Icsr") + .field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)]) .field("wutwf", &self.wutwf()) .field("shpf", &self.shpf()) .field("inits", &self.inits()) @@ -1198,6 +1214,7 @@ pub mod regs { fn format(&self, f: defmt::Formatter) { #[derive(defmt :: Format)] struct Icsr { + alrwf: [bool; 2usize], wutwf: bool, shpf: bool, inits: bool, @@ -1209,6 +1226,7 @@ pub mod regs { recalpf: super::vals::Recalpf, } let proxy = Icsr { + alrwf: [self.alrwf(0usize), self.alrwf(1usize)], wutwf: self.wutwf(), shpf: self.shpf(), inits: self.inits(), diff --git a/stm32-metapac/src/peripherals/rtc_v3l5.rs b/stm32-metapac/src/peripherals/rtc_v3l5.rs index 35f1618499..6bef4d95dc 100644 --- a/stm32-metapac/src/peripherals/rtc_v3l5.rs +++ b/stm32-metapac/src/peripherals/rtc_v3l5.rs @@ -1013,6 +1013,21 @@ pub mod regs { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Icsr(pub u32); impl Icsr { + #[doc = "Alarm write enabled"] + #[inline(always)] + pub const fn alrwf(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Alarm write enabled"] + #[inline(always)] + pub fn set_alrwf(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } #[doc = "Wakeup timer write flag"] #[inline(always)] pub const fn wutwf(&self) -> bool { @@ -1100,6 +1115,7 @@ pub mod regs { impl core::fmt::Debug for Icsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Icsr") + .field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)]) .field("wutwf", &self.wutwf()) .field("shpf", &self.shpf()) .field("inits", &self.inits()) @@ -1115,6 +1131,7 @@ pub mod regs { fn format(&self, f: defmt::Formatter) { #[derive(defmt :: Format)] struct Icsr { + alrwf: [bool; 2usize], wutwf: bool, shpf: bool, inits: bool, @@ -1124,6 +1141,7 @@ pub mod regs { recalpf: super::vals::Recalpf, } let proxy = Icsr { + alrwf: [self.alrwf(0usize), self.alrwf(1usize)], wutwf: self.wutwf(), shpf: self.shpf(), inits: self.inits(), diff --git a/stm32-metapac/src/peripherals/rtc_v3u5.rs b/stm32-metapac/src/peripherals/rtc_v3u5.rs index 825a34ea75..9b6b226249 100644 --- a/stm32-metapac/src/peripherals/rtc_v3u5.rs +++ b/stm32-metapac/src/peripherals/rtc_v3u5.rs @@ -1105,6 +1105,21 @@ pub mod regs { #[derive(Copy, Clone, Eq, PartialEq)] pub struct Icsr(pub u32); impl Icsr { + #[doc = "Alarm write enabled"] + #[inline(always)] + pub const fn alrwf(&self, n: usize) -> bool { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + let val = (self.0 >> offs) & 0x01; + val != 0 + } + #[doc = "Alarm write enabled"] + #[inline(always)] + pub fn set_alrwf(&mut self, n: usize, val: bool) { + assert!(n < 2usize); + let offs = 0usize + n * 1usize; + self.0 = (self.0 & !(0x01 << offs)) | (((val as u32) & 0x01) << offs); + } #[doc = "Wakeup timer write enabled"] #[inline(always)] pub const fn wutwf(&self) -> bool { @@ -1214,6 +1229,7 @@ pub mod regs { impl core::fmt::Debug for Icsr { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("Icsr") + .field("alrwf", &[self.alrwf(0usize), self.alrwf(1usize)]) .field("wutwf", &self.wutwf()) .field("shpf", &self.shpf()) .field("inits", &self.inits()) @@ -1231,6 +1247,7 @@ pub mod regs { fn format(&self, f: defmt::Formatter) { #[derive(defmt :: Format)] struct Icsr { + alrwf: [bool; 2usize], wutwf: bool, shpf: bool, inits: bool, @@ -1242,6 +1259,7 @@ pub mod regs { recalpf: super::vals::Recalpf, } let proxy = Icsr { + alrwf: [self.alrwf(0usize), self.alrwf(1usize)], wutwf: self.wutwf(), shpf: self.shpf(), inits: self.inits(), diff --git a/stm32-metapac/src/registers/rtc_v3.rs b/stm32-metapac/src/registers/rtc_v3.rs index 6cf91a5ef8..f34c4a1eef 100644 --- a/stm32-metapac/src/registers/rtc_v3.rs +++ b/stm32-metapac/src/registers/rtc_v3.rs @@ -1245,6 +1245,27 @@ pub(crate) static REGISTERS: IR = IR { ), bit_size: 32, fields: &[ + Field { + name: "alrwf", + description: Some( + "Alarm write enabled", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: Some( + Array::Regular( + RegularArray { + len: 2, + stride: 1, + }, + ), + ), + enumm: None, + }, Field { name: "wutwf", description: Some( diff --git a/stm32-metapac/src/registers/rtc_v3l5.rs b/stm32-metapac/src/registers/rtc_v3l5.rs index fadcb33882..1a076e68c3 100644 --- a/stm32-metapac/src/registers/rtc_v3l5.rs +++ b/stm32-metapac/src/registers/rtc_v3l5.rs @@ -1216,6 +1216,27 @@ pub(crate) static REGISTERS: IR = IR { ), bit_size: 32, fields: &[ + Field { + name: "alrwf", + description: Some( + "Alarm write enabled", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: Some( + Array::Regular( + RegularArray { + len: 2, + stride: 1, + }, + ), + ), + enumm: None, + }, Field { name: "wutwf", description: Some( diff --git a/stm32-metapac/src/registers/rtc_v3u5.rs b/stm32-metapac/src/registers/rtc_v3u5.rs index 884b0eae07..03d33f3fe2 100644 --- a/stm32-metapac/src/registers/rtc_v3u5.rs +++ b/stm32-metapac/src/registers/rtc_v3u5.rs @@ -1317,6 +1317,27 @@ pub(crate) static REGISTERS: IR = IR { ), bit_size: 32, fields: &[ + Field { + name: "alrwf", + description: Some( + "Alarm write enabled", + ), + bit_offset: BitOffset::Regular( + RegularBitOffset { + offset: 0, + }, + ), + bit_size: 1, + array: Some( + Array::Regular( + RegularArray { + len: 2, + stride: 1, + }, + ), + ), + enumm: None, + }, Field { name: "wutwf", description: Some(