diff --git a/embassy-stm32/src/rcc/g0.rs b/embassy-stm32/src/rcc/g0.rs
index 5da33720c8..f55b182906 100644
--- a/embassy-stm32/src/rcc/g0.rs
+++ b/embassy-stm32/src/rcc/g0.rs
@@ -1,8 +1,8 @@
 use crate::pac::flash::vals::Latency;
 pub use crate::pac::pwr::vals::Vos as VoltageRange;
 pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
-    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
+    Hpre as AHBPrescaler, Hsidiv as HsiSysDiv, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
+    Pllr as PllRDiv, Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
 use crate::pac::{FLASH, PWR, RCC};
 use crate::time::Hertz;
@@ -28,6 +28,12 @@ pub struct Hse {
     pub mode: HseMode,
 }
 
+#[derive(Clone, Copy, Eq, PartialEq)]
+pub struct Hsi {
+    /// Division factor for HSISYS clock. Default is 1.
+    pub sys_div: HsiSysDiv,
+}
+
 /// PLL Configuration
 ///
 /// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
@@ -58,8 +64,8 @@ pub struct Pll {
 #[non_exhaustive]
 #[derive(Clone, Copy)]
 pub struct Config {
-    /// HSI Enable
-    pub hsi: bool,
+    /// HSI Configuration
+    pub hsi: Option<Hsi>,
 
     /// HSE Configuration
     pub hse: Option<Hse>,
@@ -94,7 +100,9 @@ impl Default for Config {
     #[inline]
     fn default() -> Config {
         Config {
-            hsi: true,
+            hsi: Some(Hsi {
+                sys_div: HsiSysDiv::DIV1,
+            }),
             hse: None,
             sys: Sysclk::HSI,
             #[cfg(crs)]
@@ -119,7 +127,12 @@ pub struct PllFreq {
 
 pub(crate) unsafe fn init(config: Config) {
     // Turn on the HSI
-    RCC.cr().modify(|w| w.set_hsion(true));
+    RCC.cr().modify(|w| {
+        w.set_hsion(true);
+        if let Some(hsi) = config.hsi {
+            w.set_hsidiv(hsi.sys_div);
+        }
+    });
     while !RCC.cr().read().hsirdy() {}
 
     // Use the HSI clock as system clock during the actual clock setup
@@ -127,9 +140,9 @@ pub(crate) unsafe fn init(config: Config) {
     while RCC.cfgr().read().sws() != Sysclk::HSI {}
 
     // Configure HSI
-    let hsi = match config.hsi {
-        false => None,
-        true => Some(HSI_FREQ),
+    let (hsi, hsisys) = match config.hsi {
+        None => (None, None),
+        Some(hsi) => (Some(HSI_FREQ), Some(HSI_FREQ / hsi.sys_div)),
     };
 
     // Configure HSE
@@ -222,7 +235,7 @@ pub(crate) unsafe fn init(config: Config) {
         .unwrap_or_default();
 
     let sys = match config.sys {
-        Sysclk::HSI => unwrap!(hsi),
+        Sysclk::HSI => unwrap!(hsisys),
         Sysclk::HSE => unwrap!(hse),
         Sysclk::PLL1_R => unwrap!(pll.pll_r),
         _ => unreachable!(),
@@ -264,7 +277,7 @@ pub(crate) unsafe fn init(config: Config) {
     while RCC.cfgr().read().sws() != config.sys {}
 
     // Disable HSI if not used
-    if !config.hsi {
+    if config.hsi.is_none() {
         RCC.cr().modify(|w| w.set_hsion(false));
     }
 
diff --git a/examples/stm32g0/src/bin/hf_timer.rs b/examples/stm32g0/src/bin/hf_timer.rs
index 3ea06cdee1..dfb6e0edcb 100644
--- a/examples/stm32g0/src/bin/hf_timer.rs
+++ b/examples/stm32g0/src/bin/hf_timer.rs
@@ -16,7 +16,9 @@ async fn main(_spawner: Spawner) {
     let mut config = PeripheralConfig::default();
     {
         use embassy_stm32::rcc::*;
-        config.rcc.hsi = true;
+        config.rcc.hsi = Some(Hsi {
+            sys_div: HsiSysDiv::DIV1,
+        });
         config.rcc.pll = Some(Pll {
             source: PllSource::HSI,
             prediv: PllPreDiv::DIV1,
diff --git a/tests/stm32/src/common.rs b/tests/stm32/src/common.rs
index 935a41ed2d..829f2cff00 100644
--- a/tests/stm32/src/common.rs
+++ b/tests/stm32/src/common.rs
@@ -284,7 +284,9 @@ pub fn config() -> Config {
 
     #[cfg(feature = "stm32g071rb")]
     {
-        config.rcc.hsi = true;
+        config.rcc.hsi = Some(Hsi {
+            sys_div: HsiSysDiv::DIV1,
+        });
         config.rcc.pll = Some(Pll {
             source: PllSource::HSI,
             prediv: PllPreDiv::DIV1,