README.md

cache_hw_models

• This repo contains implementation of 3 types of caches implemented and verified in Verilog HDL.

• Direct-mapped, 2 way associative, 4 way associative.

• "dm_cache" folder contains Direct-Mapped, Write-Allocate and Write-Back Cache.

• "tw_associative" folder contains Two-Way Associative, Write-Allocate, Write-Back Cache with LRU Replacement Policy.

• "fw_associative" folder contains Four-Way Associative, Write-Allocate, Write-Back Cache with LRU Replacement Policy.

tools used

for verilog simulation and testing

> Icarus Verilog

Debug

> gtkwave

Lint

> verilator