From da124686f6c8a011f1238dcccd9a7d011385b0d2 Mon Sep 17 00:00:00 2001
From: Mohamed Gaber <donn@efabless.com>
Date: Tue, 23 Jan 2024 15:17:03 +0300
Subject: [PATCH] Update submodule, fix logic bug, revert colab-env merge
 mishap

---
 nix/colab-env.nix           | 12 ++++++------
 openlane/config/__main__.py |  2 +-
 test/steps/all              |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/nix/colab-env.nix b/nix/colab-env.nix
index dda36d230..0eab616da 100644
--- a/nix/colab-env.nix
+++ b/nix/colab-env.nix
@@ -14,10 +14,10 @@
 {
   system,
   openlane,
-  tkinter,
+  python3,
+  symlinkJoin,
 }:
-with pkgs;
-  symlinkJoin {
-    name = "openlane-colab-env";
-    paths = openlane.includedTools ++ [python3.pkgs.tkinter];
-  }
+symlinkJoin {
+  name = "openlane-colab-env";
+  paths = openlane.includedTools;
+}
diff --git a/openlane/config/__main__.py b/openlane/config/__main__.py
index 7e2ee2bff..2ca5ce204 100644
--- a/openlane/config/__main__.py
+++ b/openlane/config/__main__.py
@@ -112,7 +112,7 @@ def create_config(
                 exit(1)
     source_rtl_key = "VERILOG_FILES"
     if not functools.reduce(
-        lambda acc, x: acc and (x.endswith(".sv") or x.endswith(".v")), source_rtl
+        lambda acc, x: acc and (x.endswith(".sv") or x.endswith(".v")), source_rtl, True
     ):
         print(
             "Only Verilog/SystemVerilog files are supported by create-config.",
diff --git a/test/steps/all b/test/steps/all
index cedaedd09..45eec695e 160000
--- a/test/steps/all
+++ b/test/steps/all
@@ -1 +1 @@
-Subproject commit cedaedd092cdc07a5f2d74a36b4e499d0df26c41
+Subproject commit 45eec695efc091ee76301ef8e0c61e736fcfaf42