Constructs unsupported for synthesis

[mo-hosni]

The declaration of regs as

reg x = 1'b1;

such as in

caravel_mgmt_soc_litex/verilog/rtl/mgmt_core.v

Line 150 in 3222bd5

reg [31:0] mgmtsoc_vexriscv = 32'd268435456;

isn't supported in ASIC synthesis. This is equivalent to

reg mgmtsoc_vexriscv;
initial 
    mgmtsoc_vexriscv = 32'd268435456;

So, the initial part is ignored by synthesis tools such as DC. This didn't cause an issue with yosys but I don't think it is correct.
A simple fix would be converting the reg to a wire so it's an assign statement which is synthesizable.
I did that for the mgmtsoc_vexriscv to get the GL from DC to work. But still, this error is in the HDL in around 1800 different lines.

[mo-hosni]

@jeffdi