From 1c54133d5f559cdeb74f9bc3d160232aedac4f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Mallas=C3=A9n=20Quintana?= Date: Fri, 16 Aug 2024 12:20:15 +0200 Subject: [PATCH] Fix SV formatting Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> --- hw/int/add/full_adder.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/int/add/full_adder.sv b/hw/int/add/full_adder.sv index a0416a6..8db3f07 100644 --- a/hw/int/add/full_adder.sv +++ b/hw/int/add/full_adder.sv @@ -12,7 +12,7 @@ // Delay: O(1) module full_adder ( - input logic x, // First operand + input logic x, // First operand input logic y, // Second operand input logic cin, // Carry-in bit output logic s, // Output sum