diff --git a/data/Chipsea/CS32F030x.svd b/data/Chipsea/CS32F030x.svd
new file mode 100644
index 0000000..681b3b5
--- /dev/null
+++ b/data/Chipsea/CS32F030x.svd
@@ -0,0 +1,13901 @@
+
+
+ CS32F030x
+ 1.0
+ CS32F030x
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ CRC
+ cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DATA
+ Data register bits
+ 0
+ 32
+
+
+
+
+ FREDATA
+ FREDATA
+ free data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FREDATA
+ Free Data register
+ bits
+ 0
+ 8
+
+
+
+
+ CTR
+ CTR
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RST
+ reset bit
+ 0
+ 1
+
+
+ DINREVMOD
+ Input data Reverse mode selection
+ 5
+ 2
+
+
+ DOREVEN
+ Output data Reverse enable
+ 7
+ 1
+
+
+
+
+ INITCFG
+ INITCFG
+ CRC initial value configuration register
+ 0xC
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ INITCFG
+ CRC initial value configuration bits
+ 0
+ 32
+
+
+
+
+
+
+ GPIOF
+ General-purpose I/Os
+ GPIO
+ 0x48001400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ GPIOE
+ 0x48001000
+
+
+ GPIOD
+ 0x48000C00
+
+
+ GPIOC
+ 0x48000800
+
+
+ GPIOB
+ 0x48000400
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SBMODE
+ Single-wire bidirectional mode
+ 15
+ 1
+
+
+ SBOEN
+ Single-wire bidirectional output
+ enable
+ 14
+ 1
+
+
+ CRCEN
+ CRC calculation enable
+ 13
+ 1
+
+
+ NXTCRC
+ Next CRC transfer
+ 12
+ 1
+
+
+ CRC16
+ 16-bit CRC enable
+ 11
+ 1
+
+
+ ROM
+ Receive only mode
+ 10
+ 1
+
+
+ SWNSSM
+ software NSS mode
+ 9
+ 1
+
+
+ NVSWNSSM
+ NSS value in software NSS mode
+ 8
+ 1
+
+
+ LSBF
+ LSB first
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ CRSEL
+ Communication rate selection
+ 3
+ 3
+
+
+ SPIM
+ SPI mode
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0700
+
+
+ DMARXEN
+ DMA enable for receive
+ 0
+ 1
+
+
+ DMATXEN
+ DMA enable for transmit
+ 1
+ 1
+
+
+ NSSOEN
+ NSS output enable
+ 2
+ 1
+
+
+ NSSPM
+ NSS pulse mode
+ 3
+ 1
+
+
+ TIEN
+ SPI TI mode enable
+ 4
+ 1
+
+
+ ERRINTEN
+ Enable bit for error interrupt
+ 5
+ 1
+
+
+ RXNEINTEN
+ Enable bit for receive Buffer Not
+ Empty Interrupt
+ 6
+ 1
+
+
+ TXEINTEN
+ Enable bit for transmit Buffer
+ Empty Interrupt
+ 7
+ 1
+
+
+ DLEN
+ Data length
+ 8
+ 4
+
+
+ RXNE8
+ RXNE generate condition selection
+ 12
+ 1
+
+
+ DMARXODD
+ Number of data to receive
+ with DMA is odd
+ 13
+ 1
+
+
+ DMATXODD
+ Number of data to transmit
+ with DMA is odd
+ 14
+ 1
+
+
+
+
+ STS
+ STS
+ SPI status
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ I2SCSF
+ I2S Channel side flag
+ 2
+ 1
+ read-only
+
+
+ TXUFERR
+ Transmitter data underflow error
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error
+ 4
+ 1
+ read-write
+
+
+ MMERR
+ Multi-master error
+ 5
+ 1
+ read-only
+
+
+ RXOFERR
+ Receiver data overflow error
+ 6
+ 1
+ read-only
+
+
+ BUSY
+ Busy
+ 7
+ 1
+ read-only
+
+
+ NWERR
+ Error of SPI NSS or I2S WS
+ 8
+ 1
+ read-only
+
+
+ RXFIFOS
+ Receive FIFO status
+ 9
+ 2
+ read-only
+
+
+ TXFIFOS
+ Transmit FIFO status
+ 11
+ 2
+ read-only
+
+
+
+
+ DATA
+ DATA
+ Transfer data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Transfer data register
+ 0
+ 16
+
+
+
+
+ CRCPOLYR
+ CRCPOLYR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLYR
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2S_CTR
+ I2S_CTR
+ I2S control register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMS
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOM
+ I2S operation mode
+ 8
+ 2
+
+
+ PCMLONG
+ PCM long frame synchronization
+ 7
+ 1
+
+
+ I2SSTDS
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPIS
+ clock polarity of Inactive state
+ 3
+ 1
+
+
+ I2SDL
+ I2S data length
+ 1
+ 2
+
+
+ I2SCL
+ I2S Channel length
+ 0
+ 1
+
+
+
+
+ I2S_PDIV
+ I2S_PDIV
+ I2S pre-divider register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOEN
+ MCK output enable
+ 9
+ 1
+
+
+ PDIVPS
+ Parity selection of pre-divider
+ 8
+ 1
+
+
+ I2SPDIV
+ I2S pre-divider
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ PMU
+ Power management unit
+ PMU
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTR
+ CTR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBTWEN
+ VBAT domain write enable
+ 8
+ 1
+
+
+ LVDSEL
+ low vlotage detector
+ threshold Selection
+ 5
+ 3
+
+
+ LVDEN
+ low vlotage detector Enable
+ 4
+ 1
+
+
+ CLRPWDF
+ Clear power down flag
+ 3
+ 1
+
+
+ CLRWUPF
+ Clear wakup flag
+ 2
+ 1
+
+
+ DSMODE
+ Deepsleep Mode or
+ Power down selection
+ 1
+ 1
+
+
+ LDOLM
+ LDO low power Control
+ 0
+ 1
+
+
+
+
+ CS
+ CS
+ control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ WUPEN2
+ WKUP pin2 Enable
+ 9
+ 1
+ read-write
+
+
+ WUPEN1
+ WKUP pin1 Enable
+ 8
+ 1
+ read-write
+
+
+ VREFRDY
+ VREFINT reference voltage ready
+ 3
+ 1
+ read-only
+
+
+ LVDO
+ low vlotage detector Output
+ 2
+ 1
+ read-only
+
+
+ PWDF
+ power down flag
+ 1
+ 1
+ read-only
+
+
+ WUPF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ I2CEN
+ I2C enable
+ 0
+ 1
+ read-write
+
+
+ TXISIE
+ Enable bit for TX interrupt
+ 1
+ 1
+ read-write
+
+
+ RXNEIE
+ Enable bit for RX interrupt
+ 2
+ 1
+ read-write
+
+
+ ADRMIE
+ Enable bit for Address match
+ interrupt
+ 3
+ 1
+ read-write
+
+
+ NACKRIE
+ Enable bit for Not acknowledge
+ received interrupt
+ 4
+ 1
+ read-write
+
+
+ STOPDIE
+ Enable bit for STOP detection
+ interrupt
+ 5
+ 1
+ read-write
+
+
+ CMPIE
+ Enable bit for Transfer complete
+ interrupt
+ 6
+ 1
+ read-write
+
+
+ ERRDIE
+ Enable bit for Error detection
+ interrupt
+ 7
+ 1
+ read-write
+
+
+ DFCFG
+ Digital filter configuration
+ 8
+ 4
+ read-write
+
+
+ AFDIS
+ Analog filter Disable
+ 12
+ 1
+ read-write
+
+
+ SWRST
+ Software reset
+ 13
+ 1
+ write-only
+
+
+ TXDMAREQEN
+ Enable bit for Transmission
+ DMA requests
+ 14
+ 1
+ read-write
+
+
+ RXDMAREQEN
+ Enable bit for Reception
+ DMA requests
+ 15
+ 1
+ read-write
+
+
+ SLVRC
+ Slave response control
+ 16
+ 1
+ read-write
+
+
+ DISSTRETCH
+ Disable clock stretching
+ 17
+ 1
+ read-write
+
+
+ WKUPEN
+ Enable bit for Stop mode Wakeup
+ 18
+ 1
+ read-write
+
+
+ GCEN
+ Enable bit for General call
+ 19
+ 1
+ read-write
+
+
+ SMBHAEN
+ Enable bit for SMBus Host address
+ 20
+ 1
+ read-write
+
+
+ SMBDDAEN
+ Enable bit for SMBus Device
+ Default address
+ 21
+ 1
+ read-write
+
+
+ SMBAEN
+ SMBUS alert enable
+ 22
+ 1
+ read-write
+
+
+ PECMEN
+ PEC mode enable
+ 23
+ 1
+ read-write
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECCTR
+ PEC byte control
+ 26
+ 1
+
+
+ TENDSEL
+ Tranfer end mode selection
+ (master mode)
+ 25
+ 1
+
+
+ RELOADM
+ Bytes number reload mode
+ 24
+ 1
+
+
+ BNUM
+ Bytes number
+ 16
+ 8
+
+
+ NACKGEN
+ Generate a NACK on I2C bus
+ (slave mode)
+ 15
+ 1
+
+
+ STOPGEN
+ Generate a Stop on I2C bus
+ (master mode)
+ 14
+ 1
+
+
+ STARTGEN
+ Generate a Start on I2C bus
+ 13
+ 1
+
+
+ HEAD10AR
+ 10-bit address header only
+ read direction (master receiver mode)
+ 12
+ 1
+
+
+ ADRFMT
+ Addressing format (master mode)
+ 11
+ 1
+
+
+ TDIR
+ Direction of Transfer (master
+ mode)
+ 10
+ 1
+
+
+ MTADR8
+ Master transfer address
+ bit 9:8 on I2C bus
+ 8
+ 2
+
+
+ MTADR1
+ Master transfer address
+ bit 7:1 on I2C bus
+ 1
+ 7
+
+
+ MTADR0
+ Master transfer address
+ bit 0 on I2C bus
+ 0
+ 1
+
+
+
+
+ SADR1
+ SADR1
+ I2C slave address 1 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR1_0
+ Slave Address 1
+ 0
+ 1
+
+
+ SADR1_1
+ Slave Address 1
+ 1
+ 7
+
+
+ SADR1_8
+ Slave Address 1
+ 8
+ 2
+
+
+ SADR1MODE
+ Slave Address 1 10-bit mode
+ 10
+ 1
+
+
+ SADR1EN
+ Slave Address 1 enable
+ 15
+ 1
+
+
+
+
+ SADR2
+ SADR2
+ I2C slave address 2 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR2
+ Slave Address 2
+ 1
+ 7
+
+
+ SADR2MSK
+ Slave Address 2 masks
+ 8
+ 3
+
+
+ SADR2EN
+ Slave Address 2 enable
+ 15
+ 1
+
+
+
+
+ TMR
+ TMR
+ I2C timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLLT
+ Master mode SCL low time
+ 0
+ 8
+
+
+ SCLHT
+ Master mode SCL high time
+ 8
+ 8
+
+
+ SDAHT
+ SDA hold time
+ 16
+ 4
+
+
+ SDAST
+ SDA setup time
+ 20
+ 4
+
+
+ TPDIV
+ Timing pre-divider
+ 28
+ 4
+
+
+
+
+ OVRT
+ OVRT
+ I2C overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMA
+ Bus overtime A
+ 0
+ 12
+
+
+ IDLEDEN
+ Idle clock overtime
+ detection
+ 12
+ 1
+
+
+ TIMAEN
+ timer A enable
+ 15
+ 1
+
+
+ TIMB
+ Bus overtime B
+ 16
+ 12
+
+
+ TIMBEN
+ timer B enable
+ 31
+ 1
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ MSLVA
+ Matched Slave Address
+ 17
+ 7
+ read-only
+
+
+ DIRF
+ Slave Transfer direction
+ flag
+ 16
+ 1
+ read-only
+
+
+ BUSYF
+ Bus busy flag
+ 15
+ 1
+ read-only
+
+
+ SMBAF
+ SMBus alert flag
+ 13
+ 1
+ read-only
+
+
+ OVRTF
+ Overtime or tLOW detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERRF
+ PEC Error flag
+ 11
+ 1
+ read-only
+
+
+ OVRF
+ Slave Overflow/Underflow flag
+ 10
+ 1
+ read-only
+
+
+ ARBLOF
+ Arbitration lost flag
+ 9
+ 1
+ read-only
+
+
+ BUSERRF
+ Bus error flag
+ 8
+ 1
+ read-only
+
+
+ RLDF
+ Reload flag
+ 7
+ 1
+ read-only
+
+
+ CMPF
+ Master mode Transfer Complete
+ flag
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ NACK received flag
+ 4
+ 1
+ read-only
+
+
+ ADRF
+ Slave mode Address matched
+ flag
+ 3
+ 1
+ read-only
+
+
+ RXNEF
+ Data register not empty in
+ receiving mode
+ 2
+ 1
+ read-only
+
+
+ TXINTF
+ Transmit interrupt flag
+ 1
+ 1
+ read-write
+
+
+ TXEF
+ Data register empty flag in
+ transmitting mode
+ 0
+ 1
+ read-write
+
+
+
+
+ STSC
+ STSC
+ Status clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SMBAFC
+ SMBus alert flag clear
+ 13
+ 1
+
+
+ OVRTFC
+ Overtime detection flag
+ clear
+ 12
+ 1
+
+
+ PECERRFC
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRFC
+ Slave Overflow/Underflow
+ flag clear
+ 10
+ 1
+
+
+ ARLOFC
+ Arbitration Lost flag
+ clear
+ 9
+ 1
+
+
+ BUSERRFC
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPFC
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKFC
+ NACK received flag clear
+ 4
+ 1
+
+
+ ADRFC
+ Slave mode Address matched
+ flag clear
+ 3
+ 1
+
+
+
+
+ PECCODE
+ PECCODE
+ I2C received PEC code register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PECCODE
+ Received PEC code
+ 0
+ 8
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXBUF
+ Receive buffer register
+ 0
+ 8
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXBUF
+ Transmit buffer register
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ FWDT
+ Free Watchdog Timer
+ FWDT
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code(write only,
+ read 0x0000)
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ Pre-divider register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDIV
+ Pre-divider
+ 0
+ 3
+
+
+
+
+ UVAL
+ UVAL
+ Update register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ UVAL
+ Watchdog counter update
+ value
+ 0
+ 12
+
+
+
+
+ STS
+ STS
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DRF
+ FWDT divider refresh flag
+ 0
+ 1
+
+
+ UVRF
+ FWDT update value refresh
+ flag
+ 1
+ 1
+
+
+ WRF
+ FWDT window refresh flag
+ 2
+ 1
+
+
+
+
+ WINVAL
+ WINVAL
+ Window value register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WINVAL
+ FWDT window value
+ 0
+ 12
+
+
+
+
+
+
+ WWDT
+ Window Watchdog Timer
+ WWDT
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDT
+ Window Watchdog Timer interrupt
+ 0
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WWDTEN
+ Window watchdog timer enable
+ 7
+ 1
+
+
+ CVAL
+ Counter Value
+ 0
+ 7
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ RMDIE
+ Reminder interrupt enable
+ 9
+ 1
+
+
+ PDIV
+ Pre-divider
+ 7
+ 2
+
+
+ WVAL
+ window value
+ 0
+ 7
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RMDIF
+ Reminder interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ TIM1
+ Advanced-timers
+ TIM
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_UP_TRG_COM
+ TIM1 Break, Update, Trigger and Commutation
+ 13
+
+
+ TIM1_CC
+ TIM1 Capture Compare interrupt
+ 14
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO4
+ Idle value output of
+ channel 4
+ 14
+ 1
+
+
+ IVO3N
+ Idle value output of channel
+ 3 complementary
+ 13
+ 1
+
+
+ IVO3
+ Idle value output of channel 3
+ 12
+ 1
+
+
+ IVO2N
+ Idle value output of channel 2
+ complementary
+ 11
+ 1
+
+
+ IVO2
+ Idle value output of channel 2
+ 10
+ 1
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of
+ channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of
+ channel
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event interrupt
+ 5
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channe l communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel 2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH4CCG
+ Channel 4 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 3 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 2 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ CH2ICPDIV
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ IC1PCS
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3NCCEN
+ Channel 3 complementary capture compare
+ enable
+ 10
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2NCCEN
+ Channel 2 complementary capture compare
+ enable
+ 6
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update repetition register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ Counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL
+ Channel 2 capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL
+ Channel 3 capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL
+ Channel 4 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ channel output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ General-purpose-timers
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ CH4CCG
+ Channel 1 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 1 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 1 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode
+ selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value
+ preload enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ IC2PSC
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ channel 3 and channel 4 configuration register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4NCCP
+ Channel 4 complementary capture compare
+ Polarity
+ 15
+ 1
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL_H
+ High Counter update value (TIM2
+ only)
+ 16
+ 16
+
+
+ UVAL_L
+ Low Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL_H
+ Channel 1 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH1CCVAL_L
+ Channel 1 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL_H
+ Channel 2 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH2CCVAL_L
+ Channel 2 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL_H
+ Channel 3 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH3CCVAL_L
+ Channel 3 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL_L
+ Channel 4 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH4CCVAL_H
+ Channel 4 low capture compare value
+ 0
+ 16
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM14
+ General-purpose-timers
+ TIM
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM14
+ TIM14 global interrupt
+ 19
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ capture/compare mode register (input
+ mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ REMAP
+ REMAP
+ remap register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1IS
+ Channel 1 input selection
+ 0
+ 2
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LVD
+ LVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ INTEN
+ INTEN
+ Interrupt enable register
+ 0x0
+ 0x20
+ read-write
+ 0x0F940000
+
+
+ INTEN0
+ Interrupt enable for line 0
+ 0
+ 1
+
+
+ INTEN1
+ Interrupt enable for line 1
+ 1
+ 1
+
+
+ INTEN2
+ Interrupt enable for line 2
+ 2
+ 1
+
+
+ INTEN3
+ Interrupt enable for line 3
+ 3
+ 1
+
+
+ INTEN4
+ Interrupt enable for line 4
+ 4
+ 1
+
+
+ INTEN5
+ Interrupt enable for line 5
+ 5
+ 1
+
+
+ INTEN6
+ Interrupt enable for line 6
+ 6
+ 1
+
+
+ INTEN7
+ Interrupt enable for line 7
+ 7
+ 1
+
+
+ INTEN8
+ Interrupt enable for line 8
+ 8
+ 1
+
+
+ INTEN9
+ Interrupt enable for line 9
+ 9
+ 1
+
+
+ INTEN10
+ Interrupt enable for line 10
+ 10
+ 1
+
+
+ INTEN11
+ Interrupt enable for line 11
+ 11
+ 1
+
+
+ INTEN12
+ Interrupt enable for line 12
+ 12
+ 1
+
+
+ INTEN13
+ Interrupt enable for line 13
+ 13
+ 1
+
+
+ INTEN14
+ Interrupt enable for line 14
+ 14
+ 1
+
+
+ INTEN15
+ Interrupt enable for line 15
+ 15
+ 1
+
+
+ INTEN16
+ Interrupt enable for line 16
+ 16
+ 1
+
+
+ INTEN17
+ Interrupt enable for line 17
+ 17
+ 1
+
+
+ INTEN18
+ Interrupt enable for line 18
+ 18
+ 1
+
+
+ INTEN19
+ Interrupt enable for line 19
+ 19
+ 1
+
+
+ INTEN20
+ Interrupt enable for line 20
+ 20
+ 1
+
+
+ INTEN21
+ Interrupt enable for line 21
+ 21
+ 1
+
+
+ INTEN22
+ Interrupt enable for line 22
+ 22
+ 1
+
+
+ INTEN23
+ Interrupt enable for line 23
+ 23
+ 1
+
+
+ INTEN24
+ Interrupt enable for line 24
+ 24
+ 1
+
+
+ INTEN25
+ Interrupt enable for line 25
+ 25
+ 1
+
+
+ INTEN26
+ Interrupt enable for line 26
+ 26
+ 1
+
+
+ INTEN27
+ Interrupt enable for line 27
+ 27
+ 1
+
+
+
+
+ EVTEN
+ EVTEN
+ Event enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVTEN0
+ Event enable for line 0
+ 0
+ 1
+
+
+ EVTEN1
+ Event enable for line 1
+ 1
+ 1
+
+
+ EVTEN2
+ Event enable for line 2
+ 2
+ 1
+
+
+ EVTEN3
+ Event enable for line 3
+ 3
+ 1
+
+
+ EVTEN4
+ Event enable for line 4
+ 4
+ 1
+
+
+ EVTEN5
+ Event enable for line 5
+ 5
+ 1
+
+
+ EVTEN6
+ Event enable for line 6
+ 6
+ 1
+
+
+ EVTEN7
+ Event enable for line 7
+ 7
+ 1
+
+
+ EVTEN8
+ Event enable for line 8
+ 8
+ 1
+
+
+ EVTEN9
+ Event enable for line 9
+ 9
+ 1
+
+
+ EVTEN10
+ Event enable for line 10
+ 10
+ 1
+
+
+ EVTEN11
+ Event enable for line 11
+ 11
+ 1
+
+
+ EVTEN12
+ Event enable for line 12
+ 12
+ 1
+
+
+ EVTEN13
+ Event enable for line 13
+ 13
+ 1
+
+
+ EVTEN14
+ Event enable for line 14
+ 14
+ 1
+
+
+ EVTEN15
+ Event enable for line 15
+ 15
+ 1
+
+
+ EVTEN16
+ Event enable for line 16
+ 16
+ 1
+
+
+ EVTEN17
+ Event enable for line 17
+ 17
+ 1
+
+
+ EVTEN18
+ Event enable for line 18
+ 18
+ 1
+
+
+ EVTEN19
+ Event enable for line 19
+ 19
+ 1
+
+
+ EVTEN20
+ Event enable for line 20
+ 20
+ 1
+
+
+ EVTEN21
+ Event enable for line 21
+ 21
+ 1
+
+
+ EVTEN22
+ Event enable for line 22
+ 22
+ 1
+
+
+ EVTEN23
+ Event enable for line 23
+ 23
+ 1
+
+
+ EVTEN24
+ Event enable for line 24
+ 24
+ 1
+
+
+ EVTEN25
+ Event enable for line 25
+ 25
+ 1
+
+
+ EVTEN26
+ Event enable for line 26
+ 26
+ 1
+
+
+ EVTEN27
+ Event enable for line 27
+ 27
+ 1
+
+
+
+
+ RTEN
+ RTEN
+ Rising edge trigger enable register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTEN0
+ Rising edge trigger enable for line 0
+ 0
+ 1
+
+
+ RTEN1
+ Rising edge trigger enable for line 1
+ 1
+ 1
+
+
+ RTEN2
+ Rising edge trigger enable for line 2
+ 2
+ 1
+
+
+ RTEN3
+ Rising edge trigger enable for line 3
+ 3
+ 1
+
+
+ RTEN4
+ Rising edge trigger enable for line 4
+ 4
+ 1
+
+
+ RTEN5
+ Rising edge trigger enable for line 5
+ 5
+ 1
+
+
+ RTEN6
+ Rising edge trigger enable for line 6
+ 6
+ 1
+
+
+ RTEN7
+ Rising edge trigger enable for line 7
+ 7
+ 1
+
+
+ RTEN8
+ Rising edge trigger enable for line 8
+ 8
+ 1
+
+
+ RTEN9
+ Rising edge trigger enable for line 9
+ 9
+ 1
+
+
+ RTEN10
+ Rising edge trigger enable for line 10
+ 10
+ 1
+
+
+ RTEN11
+ Rising edge trigger enable for line 11
+ 11
+ 1
+
+
+ RTEN12
+ Rising edge trigger enable for line 12
+ 12
+ 1
+
+
+ RTEN13
+ Rising edge trigger enable for line 13
+ 13
+ 1
+
+
+ RTEN14
+ Rising edge trigger enable for line 14
+ 14
+ 1
+
+
+ RTEN15
+ Rising edge trigger enable for line 15
+ 15
+ 1
+
+
+ RTEN16
+ Rising edge trigger enable for line 16
+ 16
+ 1
+
+
+ RTEN17
+ Rising edge trigger enable for line 17
+ 17
+ 1
+
+
+ RTEN19
+ Rising edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ FTEN
+ FTEN
+ Falling edge trigger enable register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FTEN0
+ Falling edge trigger enable for line 0
+ 0
+ 1
+
+
+ FTEN1
+ Falling edge trigger enable for line 1
+ 1
+ 1
+
+
+ FTEN2
+ Falling edge trigger enable for line 2
+ 2
+ 1
+
+
+ FTEN3
+ Falling edge trigger enable for line 3
+ 3
+ 1
+
+
+ FTEN4
+ Falling edge trigger enable for line 4
+ 4
+ 1
+
+
+ FTEN5
+ Falling edge trigger enable for line 5
+ 5
+ 1
+
+
+ FTEN6
+ Falling edge trigger enable for line 6
+ 6
+ 1
+
+
+ FTEN7
+ Falling edge trigger enable for line 7
+ 7
+ 1
+
+
+ FTEN8
+ Falling edge trigger enable for line 8
+ 8
+ 1
+
+
+ FTEN9
+ Falling edge trigger enable for line 9
+ 9
+ 1
+
+
+ FTEN10
+ Falling edge trigger enable for line 10
+ 10
+ 1
+
+
+ FTEN11
+ Falling edge trigger enable for line 11
+ 11
+ 1
+
+
+ FTEN12
+ Falling edge trigger enable for line 12
+ 12
+ 1
+
+
+ FTEN13
+ Falling edge trigger enable for line 13
+ 13
+ 1
+
+
+ FTEN14
+ Falling edge trigger enable for line 14
+ 14
+ 1
+
+
+ FTEN15
+ Falling edge trigger enable for line 15
+ 15
+ 1
+
+
+ FTEN16
+ Falling edge trigger enable for line 16
+ 16
+ 1
+
+
+ FTEN17
+ Falling edge trigger enable for line 17
+ 17
+ 1
+
+
+ FTEN19
+ Falling edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ SWTIEN
+ SWTIEN
+ Software trigger interrupt/event
+ enable register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWTIEN0
+ Software trigger interrupt/event for
+ line 0
+ 0
+ 1
+
+
+ SWTIEN1
+ Software trigger interrupt/event for
+ line 1
+ 1
+ 1
+
+
+ SWTIEN2
+ Software trigger interrupt/event for
+ line 2
+ 2
+ 1
+
+
+ SWTIEN3
+ Software trigger interrupt/event for
+ line 3
+ 3
+ 1
+
+
+ SWTIEN4
+ Software trigger interrupt/event for
+ line 4
+ 4
+ 1
+
+
+ SWTIEN5
+ Software trigger interrupt/event for
+ line 5
+ 5
+ 1
+
+
+ SWTIEN6
+ Software trigger interrupt/event for
+ line 6
+ 6
+ 1
+
+
+ SWTIEN7
+ Software trigger interrupt/event for
+ line 7
+ 7
+ 1
+
+
+ SWTIEN8
+ Software trigger interrupt/event for
+ line 8
+ 8
+ 1
+
+
+ SWTIEN9
+ Software trigger interrupt/event for
+ line 9
+ 9
+ 1
+
+
+ SWTIEN10
+ Software trigger interrupt/event for
+ line 10
+ 10
+ 1
+
+
+ SWTIEN11
+ Software trigger interrupt/event for
+ line 11
+ 11
+ 1
+
+
+ SWTIEN12
+ Software trigger interrupt/event for
+ line 12
+ 12
+ 1
+
+
+ SWTIEN13
+ Software trigger interrupt/event for
+ line 13
+ 13
+ 1
+
+
+ SWTIEN14
+ Software trigger interrupt/event for
+ line 14
+ 14
+ 1
+
+
+ SWTIEN15
+ Software trigger interrupt/event for
+ line 15
+ 15
+ 1
+
+
+ SWTIEN16
+ Software trigger interrupt/event for
+ line 16
+ 16
+ 1
+
+
+ SWTIEN17
+ Software trigger interrupt/event for
+ line 17
+ 17
+ 1
+
+
+ SWTIEN19
+ Software trigger interrupt/event for
+ line 19
+ 19
+ 1
+
+
+
+
+ PDF
+ PDF
+ Pending flag register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDF0
+ Pending interrupt flag for line 0
+ 0
+ 1
+
+
+ PDF1
+ Pending interrupt flag for line 1
+ 1
+ 1
+
+
+ PDF2
+ Pending interrupt flag for line 2
+ 2
+ 1
+
+
+ PDF3
+ Pending interrupt flag for line 3
+ 3
+ 1
+
+
+ PDF4
+ Pending interrupt flag for line 4
+ 4
+ 1
+
+
+ PDF5
+ Pending interrupt flag for line 5
+ 5
+ 1
+
+
+ PDF6
+ Pending interrupt flag for line 6
+ 6
+ 1
+
+
+ PDF7
+ Pending interrupt flag for line 7
+ 7
+ 1
+
+
+ PDF8
+ Pending interrupt flag for line 8
+ 8
+ 1
+
+
+ PDF9
+ Pending interrupt flag for line 9
+ 9
+ 1
+
+
+ PDF10
+ Pending interrupt flag for line 10
+ 10
+ 1
+
+
+ PDF11
+ Pending interrupt flag for line 11
+ 11
+ 1
+
+
+ PDF12
+ Pending interrupt flag for line 12
+ 12
+ 1
+
+
+ PDF13
+ Pending interrupt flag for line 13
+ 13
+ 1
+
+
+ PDF14
+ Pending interrupt flag for line 14
+ 14
+ 1
+
+
+ PDF15
+ Pending interrupt flag for line 15
+ 15
+ 1
+
+
+ PDF16
+ Pending interrupt flag for line 16
+ 16
+ 1
+
+
+ PDF17
+ Pending interrupt flag for line 17
+ 17
+ 1
+
+
+ PDF19
+ Pending interrupt flag for line 19
+ 19
+ 1
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_00
+ PRI_00
+ 6
+ 2
+
+
+ PRI_01
+ PRI_01
+ 14
+ 2
+
+
+ PRI_02
+ PRI_02
+ 22
+ 2
+
+
+ PRI_03
+ PRI_03
+ 30
+ 2
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_40
+ PRI_40
+ 6
+ 2
+
+
+ PRI_41
+ PRI_41
+ 14
+ 2
+
+
+ PRI_42
+ PRI_42
+ 22
+ 2
+
+
+ PRI_43
+ PRI_43
+ 30
+ 2
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_80
+ PRI_80
+ 6
+ 2
+
+
+ PRI_81
+ PRI_81
+ 14
+ 2
+
+
+ PRI_82
+ PRI_82
+ 22
+ 2
+
+
+ PRI_83
+ PRI_83
+ 30
+ 2
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_120
+ PRI_120
+ 6
+ 2
+
+
+ PRI_121
+ PRI_121
+ 14
+ 2
+
+
+ PRI_122
+ PRI_122
+ 22
+ 2
+
+
+ PRI_123
+ PRI_123
+ 30
+ 2
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_160
+ PRI_160
+ 6
+ 2
+
+
+ PRI_161
+ PRI_161
+ 14
+ 2
+
+
+ PRI_162
+ PRI_162
+ 22
+ 2
+
+
+ PRI_163
+ PRI_163
+ 30
+ 2
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_200
+ PRI_200
+ 6
+ 2
+
+
+ PRI_201
+ PRI_201
+ 14
+ 2
+
+
+ PRI_202
+ PRI_202
+ 22
+ 2
+
+
+ PRI_203
+ PRI_203
+ 30
+ 2
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_240
+ PRI_240
+ 6
+ 2
+
+
+ PRI_241
+ PRI_241
+ 14
+ 2
+
+
+ PRI_242
+ PRI_242
+ 22
+ 2
+
+
+ PRI_243
+ PRI_243
+ 30
+ 2
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_280
+ PRI_280
+ 6
+ 2
+
+
+ PRI_281
+ PRI_281
+ 14
+ 2
+
+
+ PRI_282
+ PRI_282
+ 22
+ 2
+
+
+ PRI_283
+ PRI_283
+ 30
+ 2
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA channel 1 interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA channel 2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_5
+ DMA channel 4 and 5 interrupts
+ 11
+
+
+
+ STS
+ STS
+ DMA interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF1
+ Global interrupt flag of Channel 1
+ 0
+ 1
+
+
+ CMPIF1
+ Transfer complete flag of Channel 1
+ 1
+ 1
+
+
+ HLFIF1
+ Half transfer flag of Channel 1
+ 2
+ 1
+
+
+ TEIF1
+ Transfer error flag of Channel 1
+ 3
+ 1
+
+
+ GIF2
+ Global interrupt flag of Channel 2
+ 4
+ 1
+
+
+ CMPIF2
+ Transfer complete flag of Channel 2
+ 5
+ 1
+
+
+ HTIF2
+ Half transfer flag of Channel 2
+ 6
+ 1
+
+
+ TEIF2
+ Transfer error flag of Channel 2
+ 7
+ 1
+
+
+ GIF3
+ Global interrupt flag of Channel 3
+ 8
+ 1
+
+
+ CMPIF3
+ Transfer complete flag of Channel 3
+ 9
+ 1
+
+
+ HLFIF3
+ Half transfer flag of Channel 3
+ 10
+ 1
+
+
+ ERRIF3
+ Transfer error flag of Channel 3
+ 11
+ 1
+
+
+ GIF4
+ Global interrupt flag of Channel 4
+ 12
+ 1
+
+
+ CMPIF4
+ Transfer complete flag of Channel 4
+ 13
+ 1
+
+
+ HLFIF4
+ Half transfer flag of Channel 4
+ 14
+ 1
+
+
+ ERRIF4
+ Transfer error flag of Channel 4
+ 15
+ 1
+
+
+ GIF5
+ Global interrupt flag of Channel 5
+ 16
+ 1
+
+
+ CMPIF5
+ Transfer complete flag of Channel 5
+ 17
+ 1
+
+
+ HLFIF5
+ Half transfer flag of Channel 5
+ 18
+ 1
+
+
+ ERRIF5
+ Transfer error flag of Channel 5
+ 19
+ 1
+
+
+ GIF6
+ Global interrupt flag of Channel 6
+ 20
+ 1
+
+
+ CMPIF6
+ Transfer complete flag of Channel 6
+ 21
+ 1
+
+
+ HLFIF6
+ Half transfer flag of Channel 6
+ 22
+ 1
+
+
+ ERRIF6
+ Transfer error flag of Channel 6
+ 23
+ 1
+
+
+ GIF7
+ Global interrupt flag of Channel 7
+ 24
+ 1
+
+
+ CMPIF7
+ Transfer complete flag of Channel 7
+ 25
+ 1
+
+
+ HLFIF7
+ Half transfer flag of Channel 7
+ 26
+ 1
+
+
+ ERRIF7
+ Transfer error flag of Channel 7
+ 27
+ 1
+
+
+
+
+ INTFC
+ INTFC
+ DMA interrupt status clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Global interrupt flag clear of
+ Channel 1
+ 0
+ 1
+
+
+ CGIF2
+ Global interrupt flag clear of
+ Channel 2
+ 4
+ 1
+
+
+ CGIF3
+ Global interrupt flag clear of
+ Channel 3
+ 8
+ 1
+
+
+ CGIF4
+ Global interrupt flag clear of
+ Channel 4
+ 12
+ 1
+
+
+ CGIF5
+ Global interrupt flag clear of
+ Channel 5
+ 16
+ 1
+
+
+ CGIF6
+ Global interrupt flag clear of
+ Channel 6
+ 20
+ 1
+
+
+ CGIF7
+ Global interrupt flag clear of
+ Channel 7
+ 24
+ 1
+
+
+ CMPIFC1
+ Transfer complete flag clear of
+ Channel 1
+ 1
+ 1
+
+
+ CMPIFC2
+ Transfer complete flag clear of
+ Channel 2
+ 5
+ 1
+
+
+ CMPIFC3
+ Transfer complete flag clear of
+ Channel 3
+ 9
+ 1
+
+
+ CMPIFC4
+ Transfer complete flag clear of
+ Channel 4
+ 13
+ 1
+
+
+ CMPIFC5
+ Transfer complete flag clear of
+ Channel 5
+ 17
+ 1
+
+
+ CMPIFC6
+ Transfer complete flag clear of
+ Channel 6
+ 21
+ 1
+
+
+ CMPIFC7
+ Transfer complete flag clear of
+ Channel 7
+ 25
+ 1
+
+
+ HLFIFC1
+ Half transfer flag clear of
+ Channel 1
+ 2
+ 1
+
+
+ HLFIFC2
+ Half transfer flag clear of
+ Channel 2
+ 6
+ 1
+
+
+ HLFIFC3
+ Half transfer flag clear of
+ Channel 3
+ 10
+ 1
+
+
+ HLFIFC4
+ Half transfer flag clear of
+ Channel 4
+ 14
+ 1
+
+
+ HLFIFC5
+ Half transfer flag clear of
+ Channel 5
+ 18
+ 1
+
+
+ HLFIFC6
+ Half transfer flag clear of
+ Channel 6
+ 22
+ 1
+
+
+ HLFIFC7
+ Half transfer flag clear of
+ Channel 7
+ 26
+ 1
+
+
+ ERRIFC1
+ Transfer error flag clear of
+ Channel 1
+ 3
+ 1
+
+
+ ERRIFC2
+ Transfer error flag clear of
+ Channel 2
+ 7
+ 1
+
+
+ ERRIFC3
+ Transfer error flag clear of
+ Channel 3
+ 11
+ 1
+
+
+ ERRIFC4
+ Transfer error flag clear of
+ Channel 4
+ 15
+ 1
+
+
+ ERRIFC5
+ Transfer error flag clear of
+ Channel 5
+ 19
+ 1
+
+
+ ERRIFC6
+ Transfer error flag clear of
+ Channel 6
+ 23
+ 1
+
+
+ ERRIFC7
+ Transfer error flag clear of
+ Channel 7
+ 27
+ 1
+
+
+
+
+ CH1CTR
+ CH1CTR
+ DMA channel 1 controller register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CEN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH1NUM
+ CH1NUM
+ Transfer data number register of DMA
+ channel 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH1PA
+ CH1PA
+ Peripheral address register of
+ DMA channel 1
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH1MA
+ CH1MA
+ Memory address register of
+ DMA channel 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH2CTR
+ CH2CTR
+ DMA channel 2 controller register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH2NUM
+ CH2NUM
+ Transfer data number register of
+ DMA channel 2
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH2PA
+ CH2PA
+ Peripheral address register of
+ DMA channel 2
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH2MA
+ CH2MA
+ Memory address register of DMA
+ channel 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH3CTR
+ CH3CTR
+ DMA channel 3 controller register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH3NUM
+ CH3NUM
+ Transfer data number register of
+ DMA channel 3
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH3PA
+ CH3PA
+ Peripheral address register of
+ DMA channel 3
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH3MA
+ CH3MA
+ Memory address register of
+ DMA channel 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH4CTR
+ CH4CTR
+ DMA channel 4 controller register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH4NUM
+ CH4NUM
+ Transfer data number register of
+ DMA channel 4
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH4PA
+ CH4PA
+ Peripheral address register of
+ DMA channel 4
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH4MA
+ CH4MA
+ Memory address register of
+ DMA channel 4
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH5CTR
+ CH5CTR
+ DMA channel 5 controller register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH5NUM
+ CH5NUM
+ Transfer data number register of
+ DMA channel 5
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH5PA
+ CH5PA
+ Peripheral address register of
+ DMA channel 5
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH5MA
+ CH5MA
+ Memory address register of
+ DMA channel 5
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH6CTR
+ CH6CTR
+ DMA channel 6 controller register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH6NUM
+ CH6NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH6PA
+ CH6PA
+ Peripheral address register of
+ DMA channel 6
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH6MA
+ CH6MA
+ Memory address register of
+ DMA channel 6
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH7CTR
+ CH7CTR
+ DMA channel 7 controller register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH7NUM
+ CH7NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH7PA
+ CH7PA
+ Peripheral address register of
+ DMA channel 7
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH7MA
+ CH7MA
+ Memory address register of
+ DMA channel 7
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ RCU
+ Reset and clock unit
+ RCU
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCU
+ RCU global interrupt
+ 4
+
+
+
+ CTR
+ CTR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ HRCEN
+ HRC Enable
+ 0
+ 1
+ read-write
+
+
+ HRCSTAB
+ HRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ HRCTRIM
+ HRC Triming
+ 3
+ 5
+ read-write
+
+
+ HRCCALIB
+ HRC Internal 8MHz RC calibration
+ 8
+ 8
+ read-only
+
+
+ HXTEN
+ HXT Enable
+ 16
+ 1
+ read-write
+
+
+ HXTSTAB
+ HXT Stabilization flag
+ 17
+ 1
+ read-only
+
+
+ HXTBPS
+ HXT Bypass Enable
+ 18
+ 1
+ read-write
+
+
+ HXTME
+ HXT Monitor Enable
+ 19
+ 1
+ read-write
+
+
+ HXTDRV
+ HXT Drive capability Selection
+ 21
+ 2
+ read-write
+
+
+ PLLEN
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ PLLSTAB
+ PLL Stabilization flag
+ 25
+ 1
+ read-only
+
+
+
+
+ CFG
+ CFG
+ Clock configuration register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SYSSW
+ System clock switch Control
+ 0
+ 2
+ read-write
+
+
+ SYSSS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ HCLKPDIV
+ HCLK Pre-divider
+ 4
+ 4
+ read-write
+
+
+ PCLKPDIV
+ PCLK Pre-divider
+ 8
+ 3
+ read-write
+
+
+ ADCPDIV
+ ADC Clock Pre-divider
+ 14
+ 1
+ read-write
+
+
+ PLLSEL
+ PLL source Selction
+ 15
+ 2
+ read-write
+
+
+ PLLHXTPDIV
+ PLL source HXT pre-divdier
+ 17
+ 1
+ read-write
+
+
+ PLLMUF
+ PLL clock multiplication factor
+ 18
+ 4
+ read-write
+
+
+ CKOSEL
+ CLKOUT Source Selection
+ 24
+ 4
+ read-write
+
+
+ CKOPDIV
+ CLKOUT Pre-divider
+ 28
+ 3
+ read-write
+
+
+ CKOPLLND
+ PLL clock not divided for CLKOUT
+ 31
+ 1
+ read-write
+
+
+
+
+ INTR
+ INTR
+ Clock interrupt register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LRCSTABIF
+ LRC stabilization interrupt flag
+ 0
+ 1
+ read-only
+
+
+ LXTSTABIF
+ LXT stabilization interrupt flag
+ 1
+ 1
+ read-only
+
+
+ HRCSTABIF
+ HRC stabilization interrupt flag
+ 2
+ 1
+ read-only
+
+
+ HXTSTABIF
+ HXT stabilization interrupt flag
+ 3
+ 1
+ read-only
+
+
+ PLLSTABIF
+ PLL stabilization interrupt flag
+ 4
+ 1
+ read-only
+
+
+ HRC14STABIF
+ HRC14 stabilization interrupt flag
+ 5
+ 1
+ read-only
+
+
+ CKFAILIF
+ HXT clock fail interrupt flag
+ 7
+ 1
+ read-only
+
+
+ LRCSTABIE
+ LRC stabilization interrupt enable
+ 8
+ 1
+ read-write
+
+
+ LXTSTABIE
+ LXT stabilization interrupt enable
+ 9
+ 1
+ read-write
+
+
+ HRCSTABIE
+ HRC stabilization Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ HXTSTABIE
+ HXT stabilization Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ PLLSTABIE
+ PLL stabilization Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ HRC14STABIE
+ HRC14 stabilization Interrupt Enable
+ 13
+ 1
+ read-write
+
+
+ LRCSTABIC
+ LRC stabilization Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ LXTSTABIC
+ LXT stabilization Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ HRCSTABIC
+ HRC stabilization Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ HXTSTABIC
+ HXT stabilization Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ PLLSTABIC
+ PLL stabilization Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ HRC14STABIC
+ HRC14 stabilization Interrupt Clear
+ 21
+ 1
+ write-only
+
+
+ CKFAILIC
+ HXT Clock Fail Interrupt Clear
+ 23
+ 1
+ write-only
+
+
+
+
+ APB2RST
+ APB2RST
+ APB2 reset register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGRST
+ SYSCFG reset
+ 0
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ TIM16RST
+ TIM16 timer reset
+ 17
+ 1
+
+
+ TIM17RST
+ TIM17 timer reset
+ 18
+ 1
+
+
+ DBGRST
+ Debug MCU reset
+ 22
+ 1
+
+
+
+
+ APB1RST
+ APB1RST
+ APB1 reset register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM14RST
+ Timer 14 reset
+ 8
+ 1
+
+
+ WWDTRST
+ WWDT reset
+ 11
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ PMURST
+ PMU reset
+ 28
+ 1
+
+
+
+
+ AHBEN
+ AHBEN
+ AHB Clock enable register
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ DMAEN
+ enable bit for DMA clock
+ 0
+ 1
+
+
+ RMCEN
+ enable bit for SRAM clock
+ 2
+ 1
+
+
+ FMCEN
+ enable bit for FMC clock
+ 4
+ 1
+
+
+ CRCEN
+ enable bit for CRC clock
+ 6
+ 1
+
+
+ PAEN
+ enable bit for GPIO port A clock
+ 17
+ 1
+
+
+ PBEN
+ enable bit for GPIO port B clock
+ 18
+ 1
+
+
+ PCEN
+ enable bit for GPIO port C clock
+ 19
+ 1
+
+
+ PDEN
+ enable bit for GPIO port D clock
+ 20
+ 1
+
+
+ PEEN
+ enable bit for GPIO port E clock
+ 21
+ 1
+
+
+ PFEN
+ enable bit for GPIO port F clock
+ 22
+ 1
+
+
+
+
+ APB2EN
+ APB2EN
+ APB peripheral clock enable register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGEN
+ enable bit for SYSCFG clock
+ 0
+ 1
+
+
+ ADCEN
+ enable bit for ADC clock
+ 9
+ 1
+
+
+ TIM1EN
+ enable bit for TIM1 clock
+ 11
+ 1
+
+
+ SPI1EN
+ enable bit for SPI1 clock
+ 12
+ 1
+
+
+ USART1EN
+ enable bit for USART1 clock
+ 14
+ 1
+
+
+ TIM16EN
+ enable bit for TIM16 clock
+ 17
+ 1
+
+
+ TIM17EN
+ enable bit for TIM17 clock
+ 18
+ 1
+
+
+ DBGEN
+ enable bit for DBG clock
+ 22
+ 1
+
+
+
+
+ APB1EN
+ APB1EN
+ APB peripheral clock enable register 1
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2EN
+ Tenable bit for TIM2 clock
+ 0
+ 1
+
+
+ TIM3EN
+ enable bit for TIM3 clock
+ 1
+ 1
+
+
+ TIM14EN
+ enable bit for TIM14 clock
+ 8
+ 1
+
+
+ WWDTEN
+ enable bit for WWDT clock
+ 11
+ 1
+
+
+ I2C1EN
+ enable bit for I2C1 clock
+ 21
+ 1
+
+
+ PMUEN
+ enable bit for PMU clock
+ 28
+ 1
+
+
+
+
+ VBDC
+ VBDC
+ VBAT domain control register
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ LXTEN
+ LXT Enable
+ 0
+ 1
+ read-write
+
+
+ LXTSTAB
+ LXT Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ LXTBYP
+ LXT bypass
+ 2
+ 1
+ read-write
+
+
+ LXTDRV
+ LXT oscillator drive capability
+ 3
+ 3
+ read-write
+
+
+ RTCSRC
+ RTC clock source selection
+ 8
+ 2
+ read-write
+
+
+ RTCCLKEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ VBTRST
+ VBAT domain software reset
+ 16
+ 1
+ read-write
+
+
+
+
+ STS
+ STS
+ status register
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LRCEN
+ LRC enable
+ 0
+ 1
+ read-write
+
+
+ LRCSTAB
+ LRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ REGERRRSTF
+ register error flag
+ 22
+ 1
+ read-only
+
+
+ V15RSTF
+ Reset flag from the 1.5V domain
+ 23
+ 1
+ read-only
+
+
+ CRSTF
+ Clear reset flag
+ 24
+ 1
+ read-write
+
+
+ OBURSTF
+ Option byte update reset
+ flag
+ 25
+ 1
+ read-write
+
+
+ NRSTF
+ reset flag of pin nRST
+ 26
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ SWRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ FWDTRSTF
+ FWDT reset flag
+ 29
+ 1
+ read-write
+
+
+ WWDTRSTF
+ WWDT reset flag
+ 30
+ 1
+ read-write
+
+
+ LPERSTF
+ Low-power mode enter-reset flag
+ 31
+ 1
+ read-write
+
+
+
+
+ AHBRST
+ AHBRST
+ AHB reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PARST
+ GPIO port A reset
+ 17
+ 1
+
+
+ PBRST
+ GPIO port B reset
+ 18
+ 1
+
+
+ PCRST
+ GPIO port C reset
+ 19
+ 1
+
+
+ PDRST
+ GPIO port D reset
+ 20
+ 1
+
+
+ PERST
+ GPIO port E reset
+ 21
+ 1
+
+
+ PFRST
+ GPIO port F reset
+ 22
+ 1
+
+
+
+
+ CFG2
+ CFG2
+ Clock configuration register 2
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PLLPDIV
+ PLL pre-divider factor
+ 0
+ 4
+
+
+
+
+ CFG3
+ CFG3
+ Clock configuration register 3
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ USART1SEL
+ Selection of USART1 Clock
+ 0
+ 2
+
+
+ I2C1SEL
+ Selection of I2C1 Clock
+ 4
+ 1
+
+
+ ADCSEL
+ Selection of ADC Clock
+ 8
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Clock control register 2
+ 0x34
+ 0x20
+ 0x00000080
+
+
+ HRC14EN
+ HRC14 enable
+ 0
+ 1
+ read-write
+
+
+ HRC14STAB
+ HRC14 Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ ADCDISHRC14
+ ADC control HRC14 opening disable
+ 2
+ 1
+ read-write
+
+
+ HRC14TRIM
+ HRC14 Triming
+ 3
+ 5
+ read-write
+
+
+ HRC14CALIB
+ HRC14 calibration
+ 8
+ 8
+ read-only
+
+
+
+
+
+
+ SYSCFG
+ System configuration
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ RMAPCFG
+ RMAPCFG
+ SYSCFG remap configuration
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C_FMPEN_PA10
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 23
+ 1
+
+
+ I2C_FMPEN_PA9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 22
+ 1
+
+
+ I2C_FMPEN_PB9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 19
+ 1
+
+
+ I2C_FMPEN_PB8
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 18
+ 1
+
+
+ I2C_FMPEN_PB7
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 17
+ 1
+
+
+ I2C_FMPEN_PB6
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 16
+ 1
+
+
+ TIM17_DMA_CHRMAP
+ TIM17 DMA channel remapping
+ 12
+ 1
+
+
+ TIM16_DMA_CHRMAP
+ TIM16 DMA channel remapping
+ 11
+ 1
+
+
+ USART1_RX_DMA_CHRMAP
+ USART1 RX DMA channel remapping
+ 10
+ 1
+
+
+ USART1_TX_DMA_CHRMAP
+ USART1 TX DMA channel remapping
+ 9
+ 1
+
+
+ ADC_DMA_CHRMAP
+ ADC DMA channel remapping
+ 8
+ 1
+
+
+ MEM_RMAP
+ Memory remapping selection
+ 0
+ 2
+
+
+
+
+ EXTISRC1
+ EXTISRC1
+ external interrupt source selection register 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL3
+ External interrupt source selection 3
+ 12
+ 4
+
+
+ EXTI_SEL2
+ External interrupt source selection 2
+ 8
+ 4
+
+
+ EXTI_SEL1
+ External interrupt source selection 1
+ 4
+ 4
+
+
+ EXTI_SEL0
+ External interrupt source selection 0
+ 0
+ 4
+
+
+
+
+ EXTISRC2
+ EXTISRC2
+ external interrupt source selection register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL7
+ External interrupt source selection 7
+ 12
+ 4
+
+
+ EXTI_SEL6
+ External interrupt source selection 6
+ 8
+ 4
+
+
+ EXTI_SEL5
+ External interrupt source selection 5
+ 4
+ 4
+
+
+ EXTI_SEL4
+ External interrupt source selection 4
+ 0
+ 4
+
+
+
+
+ EXTISRC3
+ EXTISRC3
+ external interrupt source selection register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL11
+ External interrupt source selection 11
+ 12
+ 4
+
+
+ EXTI_SEL10
+ External interrupt source selection 10
+ 8
+ 4
+
+
+ EXTI_SEL9
+ External interrupt source selection 9
+ 4
+ 4
+
+
+ EXTI_SEL8
+ External interrupt source selection 8
+ 0
+ 4
+
+
+
+
+ EXTISRC4
+ EXTISRC4
+ external interrupt source selection register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL15
+ External interrupt source selection 15
+ 12
+ 4
+
+
+ EXTI_SEL14
+ External interrupt source selection 14
+ 8
+ 4
+
+
+ EXTI_SEL13
+ External interrupt source selection 13
+ 4
+ 4
+
+
+ EXTI_SEL12
+ External interrupt source selection 12
+ 0
+ 4
+
+
+
+
+ ERRLOCK
+ ERRLOCK
+ error and timer break lock
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ SRAM_PRTY_ERR
+ SRAM parity error flag
+ 8
+ 1
+
+
+ PVD_TIMBRK_LOCK
+ PVD output lock to tim
+ break enable
+ 2
+ 1
+
+
+ SRAM_PRTY_TIMBRK_LOCK
+ SRAM parity lock to
+ tim break
+ 1
+ 1
+
+
+ LOCKUP_TIMBRK_LOCK
+ Cortex-M0 LOCKUP lock to tim
+ break enable
+ 0
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ STAT
+ STAT
+ ADC status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVT
+ analog watchdog event flag
+ 7
+ 1
+
+
+ DOVR
+ ADC data overrun flag
+ 4
+ 1
+
+
+ EOCG
+ End of conversion group flag
+ 3
+ 1
+
+
+ EOCH
+ End of channel conversion flag
+ 2
+ 1
+
+
+ EOSP
+ End of sampling phase flag
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization
+ 0
+ 1
+
+
+
+
+ INTEN
+ INTEN
+ ADC interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVTIE
+ analog watchdog event interrupt
+ enable
+ 7
+ 1
+
+
+ DATOVR
+ ADC data overrun interrupt enable
+ 4
+ 1
+
+
+ EOGIE
+ End of conversion group interrupt
+ enable
+ 3
+ 1
+
+
+ EOC
+ End of channel conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSMPL
+ End of sampling phase interrupt
+ enable
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ CTR
+ CTR
+ ADC general control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALB
+ ADC calibration control
+ 31
+ 1
+
+
+ ADSTOP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADSTRT
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADCOFF
+ ADC power off command
+ 1
+ 1
+
+
+ ADCON
+ ADC power on command
+ 0
+ 1
+
+
+
+
+ CFG
+ CFG
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDGCHAN
+ Analog watchdog monitor channel
+ selection
+ 26
+ 5
+
+
+ WDGEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ WDGCHMODE
+ Analog watchdog channel monitor
+ mode
+ 22
+ 1
+
+
+ DISCONT
+ Discontinuous conversion mode
+ 16
+ 1
+
+
+ ATSTDBY
+ auto standby mode
+ 15
+ 1
+
+
+ PAUSE
+ conversion pause mode
+ 14
+ 1
+
+
+ GCONT
+ Group conversion Single/continuous
+ mode
+ 13
+ 1
+
+
+ DOVRWRT
+ Coversion data overrun overwriten
+ mode
+ 12
+ 1
+
+
+ TRGMODE
+ Coverstion Trigger mode selection
+ 10
+ 2
+
+
+ HTRGSEL
+ Hardware trigger source selection
+ 6
+ 3
+
+
+ DATALG
+ Coversion data format alignment
+ 5
+ 1
+
+
+ DATRES
+ Coversion data reselution
+ 3
+ 2
+
+
+ CGDIR
+ Coveration group sequence
+ direction
+ 2
+ 1
+
+
+ DMAMODE
+ Direct memory access
+ single/circle mode
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CLK
+ CLK
+ clock source register
+ 0x10
+ 0x20
+ read-write
+ 0x00008000
+
+
+ CKSRC
+ ADC clock source selection
+ 30
+ 2
+
+
+
+
+ SMPLR
+ SMPLR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPLT
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ WDTH
+ WDTH
+ Analog watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ HITH
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LOTH
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHANSEL
+ CHANSEL
+ conversion channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHANSEL18
+ conversion channel selection x
+ 18
+ 1
+
+
+ CHANSEL17
+ conversion channel selection x
+ 17
+ 1
+
+
+ CHANSEL16
+ conversion channel selection x
+ 16
+ 1
+
+
+ CHANSEL15
+ conversion channel selection x
+ 15
+ 1
+
+
+ CHANSEL14
+ conversion channel selection x
+ 14
+ 1
+
+
+ CHANSEL13
+ conversion channel selection x
+ 13
+ 1
+
+
+ CHANSEL12
+ conversion channel selection x
+ 12
+ 1
+
+
+ CHANSEL11
+ conversion channel selection x
+ 11
+ 1
+
+
+ CHANSEL10
+ conversion channel selection x
+ 10
+ 1
+
+
+ CHANSEL9
+ conversion channel selection x
+ 9
+ 1
+
+
+ CHANSEL8
+ conversion channel selection x
+ 8
+ 1
+
+
+ CHANSEL7
+ conversion channel selection x
+ 7
+ 1
+
+
+ CHANSEL6
+ conversion channel selection x
+ 6
+ 1
+
+
+ CHANSEL5
+ conversion channel selection x
+ 5
+ 1
+
+
+ CHANSEL4
+ conversion channel selection x
+ 4
+ 1
+
+
+ CHANSEL3
+ conversion channel selection x
+ 3
+ 1
+
+
+ CHANSEL2
+ conversion channel selection x
+ 2
+ 1
+
+
+ CHANSEL1
+ conversion channel selection x
+ 1
+ 1
+
+
+ CHANSEL0
+ conversion channel selection x
+ 0
+ 1
+
+
+
+
+ OUTDAT
+ OUTDAT
+ conversion output data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OUTDAT
+ conversion output data
+ 0
+ 16
+
+
+
+
+ INNCHEN
+ INNCHEN
+ internal conversion channel enable
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBATMEN
+ VBAT monitor enable
+ 24
+ 1
+
+
+ TPSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VREFINTEN
+ VREFINT enable
+ 22
+ 1
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTCIE
+ Enable bit for Block transmit
+ complete interrupt
+ 27
+ 1
+
+
+ OVRTIE
+ Enable bit for Receiver overtime
+ interrupt
+ 26
+ 1
+
+
+ PRETDE
+ Pre-active time for Driver
+ Enable
+ 21
+ 5
+
+
+ POSTDE
+ Pos-active time for Driver
+ Enable
+ 16
+ 5
+
+
+ OVRS
+ Oversampling selection
+ 15
+ 1
+
+
+ CMIE
+ Enable bit for Character
+ match interrupt
+ 14
+ 1
+
+
+ RXMSKEN
+ Reception mask mode enable
+ 13
+ 1
+
+
+ DL
+ Data length
+ 12
+ 1
+
+
+ RXWKUPS
+ Receiver wakeup selection
+ 11
+ 1
+
+
+ PEN
+ Parity enable
+ 10
+ 1
+
+
+ ODDS
+ Odd parity selection
+ 9
+ 1
+
+
+ PERRIE
+ Enable bit for parity err
+ interrupt
+ 8
+ 1
+
+
+ TXEIE
+ Enable bit for transmit empty
+ interrupt
+ 7
+ 1
+
+
+ TCIE
+ Enable bit for transmit
+ complete interrupt
+ 6
+ 1
+
+
+ RXNEIE
+ Enable bit for RXNE interrupt
+ 5
+ 1
+
+
+ IDLEIE
+ Enable bit for IDLE interrupt
+ 4
+ 1
+
+
+ TEN
+ Transmitter enable
+ 3
+ 1
+
+
+ REN
+ Receiver enable
+ 2
+ 1
+
+
+ WKUPSTOP
+ Wakeup mcu from stop mode enable
+ 1
+ 1
+
+
+ UEN
+ USART enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ UADR_4
+ USART Address
+ 28
+ 4
+
+
+ UADR_0
+ USART Address
+ 24
+ 4
+
+
+ ROTEN
+ Receiver overtime enable
+ 23
+ 1
+
+
+ ABRSEL
+ Auto baud rate mode selection
+ 21
+ 2
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBF
+ MSB first
+ 19
+ 1
+
+
+ DINV
+ Data bit inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin inversion
+ 16
+ 1
+
+
+ TXRXSWAP
+ TX/RX pins swap enable
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOPLEN
+ STOP bits length
+ 12
+ 2
+
+
+ CKEN
+ CK pin enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ CKLEN
+ LCK length
+ 8
+ 1
+
+
+ LBDIE
+ Enable bit for LIN break frame
+ detection interrupt
+ 6
+ 1
+
+
+ LINBRK11
+ 11-bit break frame detection
+ 5
+ 1
+
+
+ ADRM7
+ 4bit/7bit Address Detection selection
+ 4
+ 1
+
+
+
+
+ CTR3
+ CTR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPIE
+ Enable bit for Wakeup from
+ Stop mode interrupt
+ 22
+ 1
+
+
+ WKUPMTHD
+ Wakeup from Stop mode method
+ 20
+ 2
+
+
+ SCANUM
+ Number of Smartcard auto-retry times
+ 17
+ 3
+
+
+ DEPS
+ DE polarity selection
+ 15
+ 1
+
+
+ DEN
+ DE enable
+ 14
+ 1
+
+
+ DRMRE
+ DMA request mask on Reception
+ Error
+ 13
+ 1
+
+
+ NORXOF
+ No Receive Overflow detection
+ 12
+ 1
+
+
+ SPMS
+ Sample method selection
+ 11
+ 1
+
+
+ CTSIE
+ Enable bit for CTS interrupt
+ 10
+ 1
+
+
+ CTSEN
+ CTS enable
+ 9
+ 1
+
+
+ RTSEN
+ RTS enable
+ 8
+ 1
+
+
+ TXDMA
+ Transmit with DMA
+ 7
+ 1
+
+
+ RXDMA
+ Receive with DMA
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ SCNACK
+ Smartcard transmit NACK in parity error
+ 4
+ 1
+
+
+ HDEN
+ Half-duplex enable
+ 3
+ 1
+
+
+ IRMS
+ IrDA mode selection
+ 2
+ 1
+
+
+ IRDAEN
+ IrDA mode enable
+ 1
+ 1
+
+
+ ERRIE
+ Enable bit for Error interrupt
+ 0
+ 1
+
+
+
+
+ BRT
+ BRT
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ INTDIV
+ DIV INT value
+ 4
+ 12
+
+
+ FRADIV
+ DIV Fraction value
+ 0
+ 4
+
+
+
+
+ GTPDIV
+ GTPDIV
+ Guard time and pre-divider
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GUDT
+ Guard time value
+ 8
+ 8
+
+
+ PDIV
+ Pre-divider value
+ 0
+ 8
+
+
+
+
+ RXOVR
+ RXOVR
+ Receiver overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ NUMBLK
+ Unit number of block
+ 24
+ 8
+
+
+ RXOVR
+ Receiver overtime value
+ 0
+ 24
+
+
+
+
+ SWTR
+ SWTR
+ Software Trigger register
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXESET
+ TXE set trigger
+ 4
+ 1
+
+
+ RXNECLR
+ RXNE clear trigger
+ 3
+ 1
+
+
+ RXMSKT
+ Reception mask mode trigger
+ 2
+ 1
+
+
+ BRKFST
+ Break frame send trigger
+ 1
+ 1
+
+
+ ABRT
+ Auto baud rate trigger
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ Interrupt and status register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ RENACTF
+ REN active flag
+ 22
+ 1
+
+
+ TENACTF
+ TEN active flag
+ 21
+ 1
+
+
+ WKUPF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RXMSKF
+ Reception mask mode flag
+ 19
+ 1
+
+
+ BRKSF
+ Break frame send flag
+ 18
+ 1
+
+
+ CMF
+ Character match flag
+ 17
+ 1
+
+
+ BUSY
+ Busy flag
+ 16
+ 1
+
+
+ ABRTF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABRTERRF
+ Auto baud rate error flag
+ 14
+ 1
+
+
+ ENDBLKF
+ End of block flag
+ 12
+ 1
+
+
+ ROTF
+ Receiver overtime flag
+ 11
+ 1
+
+
+ CTSF
+ CTS flag
+ 10
+ 1
+
+
+ CTSIF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LINBKF
+ LIN break frame detection flag
+ 8
+ 1
+
+
+ TXE
+ transmit buffer empty flag
+ 7
+ 1
+
+
+ TCF
+ Transmission complete flag
+ 6
+ 1
+
+
+ RXNE
+ receiver buffer not empty
+ flag
+ 5
+ 1
+
+
+ IDLEF
+ Idle frame detected flag
+ 4
+ 1
+
+
+ OVRERRF
+ Reception overflow error
+ flag
+ 3
+ 1
+
+
+ NF
+ Noise flag
+ 2
+ 1
+
+
+ FERRF
+ Frame error flag
+ 1
+ 1
+
+
+ PERRF
+ Parity error flag
+ 0
+ 1
+
+
+
+
+ IFCLR
+ IFCLR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPFC
+ Wakeup from Stop mode flag
+ clear
+ 20
+ 1
+
+
+ CMFC
+ Character match flag clear
+ 17
+ 1
+
+
+ ENDBLKFC
+ End of block flag clear
+ 12
+ 1
+
+
+ ROTFC
+ Receiver overtime flag clear
+ 11
+ 1
+
+
+ CTSFC
+ CTS flag clear
+ 9
+ 1
+
+
+ LINBKFC
+ LIN break frame detection flag
+ clear
+ 8
+ 1
+
+
+ TCFC
+ Transmission complete flag
+ clear
+ 6
+ 1
+
+
+ IDLEFC
+ Idle frame detected flag
+ clear
+ 4
+ 1
+
+
+ OVRERRC
+ Overrun error flag clear
+ 3
+ 1
+
+
+ STARTNFC
+ Start bit Noise detected
+ flag clear
+ 2
+ 1
+
+
+ FERRC
+ Frame error flag clear
+ 1
+ 1
+
+
+ PERRC
+ Parity error flag clear
+ 0
+ 1
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RXBUF
+ Receive buffer
+ 0
+ 9
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXBUF
+ Transmit buffer
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 2
+
+
+
+ TIME
+ TIME
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MINTEN
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD format
+ 8
+ 4
+
+
+ SECTEN
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DATE
+ DATE
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YTEN
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YUNT
+ Year units in BCD format
+ 16
+ 4
+
+
+ WUNT
+ Week day units
+ 13
+ 3
+
+
+ MTEN
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MUNT
+ Month units in BCD format
+ 8
+ 4
+
+
+ DTEN
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DUNT
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CTR
+ CTR
+ control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ TRESEL
+ Time recording edge select
+ 3
+ 1
+ read-write
+
+
+ OPCLKEN
+ outside precise clock detection enable
+ 4
+ 1
+ read-write
+
+
+ DAR
+ direct access registers
+ 5
+ 1
+ read-write
+
+
+ FMT12
+ 12/24 format
+ 6
+ 1
+ read-write
+
+
+ ALRE
+ Alarm enable
+ 8
+ 1
+ read-write
+
+
+ TRE
+ Time recording enable
+ 11
+ 1
+ read-write
+
+
+ ALRIE
+ Alarm interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TRIE
+ Time recording interrupt enable
+ 15
+ 1
+ read-write
+
+
+ INC1H
+ increase 1 hour
+ 16
+ 1
+ write-only
+
+
+ DEC1H
+ decrease 1 hour
+ 17
+ 1
+ write-only
+
+
+ SAVEF
+ saving time flag
+ 18
+ 1
+ read-write
+
+
+ CALSRC
+ Calibration output source
+ 19
+ 1
+ read-write
+
+
+ APOL
+ Alarm Output polarity
+ 20
+ 1
+ read-write
+
+
+ OUTSRC
+ Output source
+ 21
+ 2
+ read-write
+
+
+ CALOE
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+
+
+ STS
+ STS
+ status register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ ALRWAF
+ Alarm write access flag
+ 0
+ 1
+ read-only
+
+
+ SHF_BUSY
+ Shift busy
+ 3
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization flag
+ 5
+ 1
+ read-write
+
+
+ INITF
+ Initialization mode endter flag
+ 6
+ 1
+ read-only
+
+
+ INITE
+ Initialization mode enbale
+ 7
+ 1
+ read-write
+
+
+ ALRF
+ Alarm flag
+ 8
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TAMP1F
+ RTC_INBREAK1 detection flag
+ 13
+ 1
+ read-write
+
+
+ TAMP2F
+ RTC_INBREAK2 detection flag
+ 14
+ 1
+ read-write
+
+
+ CALBSY
+ Calibration busy
+ 16
+ 1
+ read-only
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ PDIV1
+ first pre-divider factor
+ 16
+ 7
+
+
+ PDIV2
+ second pre-divider factor
+ 0
+ 15
+
+
+
+
+ ACFG1
+ ACFG1
+ alarm config1 register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDBYP
+ week/date bypass
+ 31
+ 1
+
+
+ WDSEL
+ week/date selection
+ 30
+ 1
+
+
+ DTEN
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DUNT
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ HORBYP
+ hours bypass
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MINBYP
+ minutes bypass
+ 15
+ 1
+
+
+ MINTEN
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ SECBYP
+ seconds bypass
+ 7
+ 1
+
+
+ SECTEN
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ CCODE
+ CCODE
+ control code register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code
+ 0
+ 8
+
+
+
+
+ SSEC
+ SSEC
+ subsecond register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSEC
+ subsecond
+ 0
+ 16
+
+
+
+
+ ADJ
+ ADJ
+ adjustment register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ INC1S
+ increase one second
+ 31
+ 1
+
+
+ SSEC_ADJ
+ subsecond adjustment
+ 0
+ 15
+
+
+
+
+ TR2
+ TR2
+ recording2 register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MINTEN
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ SECTEN
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ TR1
+ TR1
+ recording1 register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WEEKUNT
+ Week units
+ 13
+ 3
+
+
+ MTEN
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MUNT
+ Month units in BCD format
+ 8
+ 4
+
+
+ DTEN
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DUNT
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TR3
+ TR3
+ recording3 register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSEC
+ Subsecond
+ 0
+ 16
+
+
+
+
+ 1SCAL
+ 1SCAL
+ 1Hz clock calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ INSCLK
+ Insert RTC clock
+ 15
+ 1
+
+
+ WIN8S
+ 8-second calibration window
+ 14
+ 1
+
+
+ WIN16S
+ 16-second calibration window
+ 13
+ 1
+
+
+ SWACLK
+ swallow RTC clock
+ 0
+ 9
+
+
+
+
+ MF
+ MF
+ multiplex function register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PC15CFG
+ PC15 config
+ 23
+ 1
+
+
+ PC15DATA
+ PC15 output data
+ 22
+ 1
+
+
+ PC14CFG
+ PC14 config
+ 21
+ 1
+
+
+ PC14DATA
+ PC14 output data
+ 20
+ 1
+
+
+ PC13CFG
+ PC13 config
+ 19
+ 1
+
+
+ PC13DATA
+ RTC_ALARM output type/PC13 output
+ data
+ 18
+ 1
+
+
+ INBRKPUDIS
+ RTC_INBREAKx pull-up disable
+ 15
+ 1
+
+
+ INBRKPRCH
+ RTC_INBREAKx precharge duration
+ 13
+ 2
+
+
+ INBRKFLT
+ RTC_INBREAKx filter count
+ 11
+ 2
+
+
+ INBRKFREQ
+ Inbreak sampling frequency
+ 8
+ 3
+
+
+ INBRKTR
+ Activate timestamp on inbreak detection
+ event
+ 7
+ 1
+
+
+ INBRK2TRG
+ Active level for RTC_INBREAK2
+ input
+ 4
+ 1
+
+
+ INBRK2E
+ RTC_INBREAK2 input detection
+ enable
+ 3
+ 1
+
+
+ INBRKIE
+ Inbreak interrupt enable
+ 2
+ 1
+
+
+ INBRK1TRG
+ Active level for RTC_INBREAK1
+ input
+ 1
+ 1
+
+
+ INBRK1E
+ Active level for RTC_INBREAK1
+ input
+ 0
+ 1
+
+
+
+
+ ACFG2
+ ACFG2
+ alarm config2 register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SSECBYP
+ Subsecond bypass
+ 24
+ 4
+
+
+ SSEC
+ Subsecond
+ 0
+ 15
+
+
+
+
+ AO0
+ AO0
+ always on registers 0
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO1
+ AO1
+ RTC always on registers 1
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO2
+ AO2
+ RTC always on registers 2
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO3
+ AO3
+ RTC always on registers 3
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO4
+ AO4
+ RTC always on registers 4
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+
+
+ TIM15
+ General-purpose-timers
+ TIM
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM15
+ TIM15 global interrupt
+ 20
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of channel
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger
+ DMA request
+ 14
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1
+ DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event
+ interrupt
+ 5
+ 1
+
+
+ CH1INTEN
+ Enable bit for channel 1
+ interrupt
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channel communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH1CCG
+ Channel 1 capture compare event
+ generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration register
+ (output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM16
+ 0x40014400
+
+ TIM16
+ TIM16 global interrupt
+ 21
+
+
+
+ TIM17
+ 0x40014800
+
+ TIM17
+ TIM17 global interrupt
+ 22
+
+
+
+ TIM6
+ General-purpose-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt
+ 17
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+
+
+ FMC
+ FLASH Memory Control
+ FMC
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 3
+
+
+
+ WCR
+ WCR
+ Flash access control register
+ 0x0
+ 0x20
+ 0x00000030
+
+
+ WCNT
+ FMC wait conuter
+ 0
+ 3
+ read-write
+
+
+ WE
+ FMC wait enable
+ 4
+ 1
+ read-write
+
+
+ WS
+ FMC wait status
+ 5
+ 1
+ read-only
+
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code
+ 0
+ 32
+
+
+
+
+ OBCCODE
+ OBCCODE
+ Option Byte Control code register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OBCCODE
+ Option Byte Control code
+ 0
+ 32
+
+
+
+
+ STS
+ STS
+ status register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ ENDF
+ End of operation
+ 5
+ 1
+ read-write
+
+
+ WPERR
+ Erase/Program protection error
+ 4
+ 1
+ read-write
+
+
+ PGERR
+ Program error
+ 2
+ 1
+ read-write
+
+
+ BUSY
+ Busy
+ 0
+ 1
+ read-only
+
+
+
+
+ CTR
+ CTR
+ FMC control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ OBUPDATE
+ Update option byte
+ 13
+ 1
+
+
+ ENDIE
+ End of operation interrupt
+ enable
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ OBWEN
+ Option byte erase/program enable
+ 9
+ 1
+
+
+ LOCK
+ LOCK
+ 7
+ 1
+
+
+ START
+ Start of erase
+ 6
+ 1
+
+
+ OBERS
+ Option byte erase command
+ 5
+ 1
+
+
+ OBPG
+ Option byte programm command
+ 4
+ 1
+
+
+ CHIPERS
+ Main flash CHIP ERASE
+ 2
+ 1
+
+
+ PERS
+ Flash page erase
+ 1
+ 1
+
+
+ PG
+ Main flash program
+ 0
+ 1
+
+
+
+
+ ERSADR
+ ERSADR
+ Flash erase address register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ERSADR
+ Flash erase address
+ 0
+ 32
+
+
+
+
+ OBSTS
+ OBSTS
+ Option byte status register
+ 0x1C
+ 0x20
+ read-only
+ 0x03FFFFF2
+
+
+ DATA1
+ DATA1
+ 24
+ 8
+
+
+ DATA0
+ DATA0
+ 16
+ 8
+
+
+ VDDA_DET
+ VDDA_DET
+ 13
+ 1
+
+
+ nBOOT1
+ nBOOT1
+ 12
+ 1
+
+
+ nRST_PWD
+ nRST_PWD
+ 10
+ 1
+
+
+ nRST_DSM
+ nRST_DSM
+ 9
+ 1
+
+
+ FWDT_AO
+ FWDT_AO
+ 8
+ 1
+
+
+ RPROT
+ RPROT
+ 1
+ 2
+
+
+ OBERR
+ Option byte error
+ 0
+ 1
+
+
+
+
+ WPSTS
+ WPSTS
+ Write protection status register
+ 0x20
+ 0x20
+ read-only
+ 0xFFFFFFFF
+
+
+ WPROT0
+ Write protect byte 0
+ 0
+ 8
+
+
+ WPROT1
+ Write protect byte 1
+ 8
+ 8
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBG
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ID
+ ID
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision identifier
+ 16
+ 16
+
+
+
+
+ LPWCFG
+ LPWCFG
+ Debug support for low power
+ configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DSM_DBGEN
+ Debug Deep Sleep Mode
+ 1
+ 1
+
+
+ PWD_DBGEN
+ Debug Down Power Mode
+ 2
+ 1
+
+
+
+
+ APB1CFG
+ APB1CFG
+ Debug support for apb1 peripherals
+ configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM2_DBG_PAUSE
+ TIM2 counter paused when system is
+ in debug mode
+ 0
+ 1
+
+
+ TIM3_DBG_PAUSE
+ TIM3 counter paused when system is
+ in debug mode
+ 1
+ 1
+
+
+ TIM6_DBG_PAUSE
+ TIM6 counter paused when system
+ is in debug mode
+ 4
+ 1
+
+
+ TIM14_DBG_PAUSE
+ TIM14 counter when system is in
+ debug mode
+ 8
+ 1
+
+
+ RTC_DBG_PAUSE
+ RTC paused when system is in
+ debug mode
+ 10
+ 1
+
+
+ WWDT_DBG_PAUSE
+ window watchdog paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ FWDT_DBG_PAUSE
+ Free watchdog paused when system
+ is in debug mode
+ 12
+ 1
+
+
+ I2C1_SMBUS_DBG_PAUSE
+ SMBUS timeout counter paused when
+ system is in debug mode
+ 21
+ 1
+
+
+
+
+ APB2CFG
+ APB2CFG
+ Debug support for apb2 peripherals
+ configuration register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM1_DBG_PAUSE
+ TIM1 counter paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ TIM15_DBG_PAUSE
+ TIM15 counter paused when system
+ is in debug mode
+ 16
+ 1
+
+
+ TIM16_DBG_PAUSE
+ TIM16 counter paused when system is
+ in debug mode
+ 17
+ 1
+
+
+ TIM17_DBG_PAUSE
+ TIM17 counter paused when system is
+ in debug mode
+ 18
+ 1
+
+
+
+
+
+
+
diff --git a/data/Chipsea/CS32F031x.svd b/data/Chipsea/CS32F031x.svd
new file mode 100644
index 0000000..ff144d5
--- /dev/null
+++ b/data/Chipsea/CS32F031x.svd
@@ -0,0 +1,13964 @@
+
+
+ CS32F031x
+ 1.0
+ CS32F031x
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ CRC
+ cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DATA
+ Data register bits
+ 0
+ 32
+
+
+
+
+ FREDATA
+ FREDATA
+ free data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FREDATA
+ Free Data register
+ bits
+ 0
+ 8
+
+
+
+
+ CTR
+ CTR
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RST
+ reset bit
+ 0
+ 1
+
+
+ DINREVMOD
+ Input data Reverse mode selection
+ 5
+ 2
+
+
+ DOREVEN
+ Output data Reverse enable
+ 7
+ 1
+
+
+
+
+ INITCFG
+ INITCFG
+ CRC initial value configuration register
+ 0xC
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ INITCFG
+ CRC initial value configuration bits
+ 0
+ 32
+
+
+
+
+
+
+ GPIOF
+ General-purpose I/Os
+ GPIO
+ 0x48001400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ GPIOE
+ 0x48001000
+
+
+ GPIOD
+ 0x48000C00
+
+
+ GPIOC
+ 0x48000800
+
+
+ GPIOB
+ 0x48000400
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SBMODE
+ Single-wire bidirectional mode
+ 15
+ 1
+
+
+ SBOEN
+ Single-wire bidirectional output
+ enable
+ 14
+ 1
+
+
+ CRCEN
+ CRC calculation enable
+ 13
+ 1
+
+
+ NXTCRC
+ Next CRC transfer
+ 12
+ 1
+
+
+ CRC16
+ 16-bit CRC enable
+ 11
+ 1
+
+
+ ROM
+ Receive only mode
+ 10
+ 1
+
+
+ SWNSSM
+ software NSS mode
+ 9
+ 1
+
+
+ NVSWNSSM
+ NSS value in software NSS mode
+ 8
+ 1
+
+
+ LSBF
+ LSB first
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ CRSEL
+ Communication rate selection
+ 3
+ 3
+
+
+ SPIM
+ SPI mode
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0700
+
+
+ DMARXEN
+ DMA enable for receive
+ 0
+ 1
+
+
+ DMATXEN
+ DMA enable for transmit
+ 1
+ 1
+
+
+ NSSOEN
+ NSS output enable
+ 2
+ 1
+
+
+ NSSPM
+ NSS pulse mode
+ 3
+ 1
+
+
+ TIEN
+ SPI TI mode enable
+ 4
+ 1
+
+
+ ERRINTEN
+ Enable bit for error interrupt
+ 5
+ 1
+
+
+ RXNEINTEN
+ Enable bit for receive Buffer Not
+ Empty Interrupt
+ 6
+ 1
+
+
+ TXEINTEN
+ Enable bit for transmit Buffer
+ Empty Interrupt
+ 7
+ 1
+
+
+ DLEN
+ Data length
+ 8
+ 4
+
+
+ RXNE8
+ RXNE generate condition selection
+ 12
+ 1
+
+
+ DMARXODD
+ Number of data to receive
+ with DMA is odd
+ 13
+ 1
+
+
+ DMATXODD
+ Number of data to transmit
+ with DMA is odd
+ 14
+ 1
+
+
+
+
+ STS
+ STS
+ SPI status
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ I2SCSF
+ I2S Channel side flag
+ 2
+ 1
+ read-only
+
+
+ TXUFERR
+ Transmitter data underflow error
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error
+ 4
+ 1
+ read-write
+
+
+ MMERR
+ Multi-master error
+ 5
+ 1
+ read-only
+
+
+ RXOFERR
+ Receiver data overflow error
+ 6
+ 1
+ read-only
+
+
+ BUSY
+ Busy
+ 7
+ 1
+ read-only
+
+
+ NWERR
+ Error of SPI NSS or I2S WS
+ 8
+ 1
+ read-only
+
+
+ RXFIFOS
+ Receive FIFO status
+ 9
+ 2
+ read-only
+
+
+ TXFIFOS
+ Transmit FIFO status
+ 11
+ 2
+ read-only
+
+
+
+
+ DATA
+ DATA
+ Transfer data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Transfer data register
+ 0
+ 16
+
+
+
+
+ CRCPOLYR
+ CRCPOLYR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLYR
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2S_CTR
+ I2S_CTR
+ I2S control register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMS
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOM
+ I2S operation mode
+ 8
+ 2
+
+
+ PCMLONG
+ PCM long frame synchronization
+ 7
+ 1
+
+
+ I2SSTDS
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPIS
+ clock polarity of Inactive state
+ 3
+ 1
+
+
+ I2SDL
+ I2S data length
+ 1
+ 2
+
+
+ I2SCL
+ I2S Channel length
+ 0
+ 1
+
+
+
+
+ I2S_PDIV
+ I2S_PDIV
+ I2S pre-divider register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOEN
+ MCK output enable
+ 9
+ 1
+
+
+ PDIVPS
+ Parity selection of pre-divider
+ 8
+ 1
+
+
+ I2SPDIV
+ I2S pre-divider
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ PMU
+ Power management unit
+ PMU
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTR
+ CTR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBTWEN
+ VBAT domain write enable
+ 8
+ 1
+
+
+ LVDSEL
+ low vlotage detector
+ threshold Selection
+ 5
+ 3
+
+
+ LVDEN
+ low vlotage detector Enable
+ 4
+ 1
+
+
+ CLRPWDF
+ Clear power down flag
+ 3
+ 1
+
+
+ CLRWUPF
+ Clear wakup flag
+ 2
+ 1
+
+
+ DSMODE
+ Deepsleep Mode or
+ Power down selection
+ 1
+ 1
+
+
+ LDOLM
+ LDO low power Control
+ 0
+ 1
+
+
+
+
+ CS
+ CS
+ control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ WUPEN2
+ WKUP pin2 Enable
+ 9
+ 1
+ read-write
+
+
+ WUPEN1
+ WKUP pin1 Enable
+ 8
+ 1
+ read-write
+
+
+ VREFRDY
+ VREFINT reference voltage ready
+ 3
+ 1
+ read-only
+
+
+ LVDO
+ low vlotage detector Output
+ 2
+ 1
+ read-only
+
+
+ PWDF
+ power down flag
+ 1
+ 1
+ read-only
+
+
+ WUPF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ I2CEN
+ I2C enable
+ 0
+ 1
+ read-write
+
+
+ TXISIE
+ Enable bit for TX interrupt
+ 1
+ 1
+ read-write
+
+
+ RXNEIE
+ Enable bit for RX interrupt
+ 2
+ 1
+ read-write
+
+
+ ADRMIE
+ Enable bit for Address match
+ interrupt
+ 3
+ 1
+ read-write
+
+
+ NACKRIE
+ Enable bit for Not acknowledge
+ received interrupt
+ 4
+ 1
+ read-write
+
+
+ STOPDIE
+ Enable bit for STOP detection
+ interrupt
+ 5
+ 1
+ read-write
+
+
+ CMPIE
+ Enable bit for Transfer complete
+ interrupt
+ 6
+ 1
+ read-write
+
+
+ ERRDIE
+ Enable bit for Error detection
+ interrupt
+ 7
+ 1
+ read-write
+
+
+ DFCFG
+ Digital filter configuration
+ 8
+ 4
+ read-write
+
+
+ AFDIS
+ Analog filter Disable
+ 12
+ 1
+ read-write
+
+
+ SWRST
+ Software reset
+ 13
+ 1
+ write-only
+
+
+ TXDMAREQEN
+ Enable bit for Transmission
+ DMA requests
+ 14
+ 1
+ read-write
+
+
+ RXDMAREQEN
+ Enable bit for Reception
+ DMA requests
+ 15
+ 1
+ read-write
+
+
+ SLVRC
+ Slave response control
+ 16
+ 1
+ read-write
+
+
+ DISSTRETCH
+ Disable clock stretching
+ 17
+ 1
+ read-write
+
+
+ WKUPEN
+ Enable bit for Stop mode Wakeup
+ 18
+ 1
+ read-write
+
+
+ GCEN
+ Enable bit for General call
+ 19
+ 1
+ read-write
+
+
+ SMBHAEN
+ Enable bit for SMBus Host address
+ 20
+ 1
+ read-write
+
+
+ SMBDDAEN
+ Enable bit for SMBus Device
+ Default address
+ 21
+ 1
+ read-write
+
+
+ SMBAEN
+ SMBUS alert enable
+ 22
+ 1
+ read-write
+
+
+ PECMEN
+ PEC mode enable
+ 23
+ 1
+ read-write
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECCTR
+ PEC byte control
+ 26
+ 1
+
+
+ TENDSEL
+ Tranfer end mode selection
+ (master mode)
+ 25
+ 1
+
+
+ RELOADM
+ Bytes number reload mode
+ 24
+ 1
+
+
+ BNUM
+ Bytes number
+ 16
+ 8
+
+
+ NACKGEN
+ Generate a NACK on I2C bus
+ (slave mode)
+ 15
+ 1
+
+
+ STOPGEN
+ Generate a Stop on I2C bus
+ (master mode)
+ 14
+ 1
+
+
+ STARTGEN
+ Generate a Start on I2C bus
+ 13
+ 1
+
+
+ HEAD10AR
+ 10-bit address header only
+ read direction (master receiver mode)
+ 12
+ 1
+
+
+ ADRFMT
+ Addressing format (master mode)
+ 11
+ 1
+
+
+ TDIR
+ Direction of Transfer (master
+ mode)
+ 10
+ 1
+
+
+ MTADR8
+ Master transfer address
+ bit 9:8 on I2C bus
+ 8
+ 2
+
+
+ MTADR1
+ Master transfer address
+ bit 7:1 on I2C bus
+ 1
+ 7
+
+
+ MTADR0
+ Master transfer address
+ bit 0 on I2C bus
+ 0
+ 1
+
+
+
+
+ SADR1
+ SADR1
+ I2C slave address 1 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR1_0
+ Slave Address 1
+ 0
+ 1
+
+
+ SADR1_1
+ Slave Address 1
+ 1
+ 7
+
+
+ SADR1_8
+ Slave Address 1
+ 8
+ 2
+
+
+ SADR1MODE
+ Slave Address 1 10-bit mode
+ 10
+ 1
+
+
+ SADR1EN
+ Slave Address 1 enable
+ 15
+ 1
+
+
+
+
+ SADR2
+ SADR2
+ I2C slave address 2 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR2
+ Slave Address 2
+ 1
+ 7
+
+
+ SADR2MSK
+ Slave Address 2 masks
+ 8
+ 3
+
+
+ SADR2EN
+ Slave Address 2 enable
+ 15
+ 1
+
+
+
+
+ TMR
+ TMR
+ I2C timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLLT
+ Master mode SCL low time
+ 0
+ 8
+
+
+ SCLHT
+ Master mode SCL high time
+ 8
+ 8
+
+
+ SDAHT
+ SDA hold time
+ 16
+ 4
+
+
+ SDAST
+ SDA setup time
+ 20
+ 4
+
+
+ TPDIV
+ Timing pre-divider
+ 28
+ 4
+
+
+
+
+ OVRT
+ OVRT
+ I2C overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMA
+ Bus overtime A
+ 0
+ 12
+
+
+ IDLEDEN
+ Idle clock overtime
+ detection
+ 12
+ 1
+
+
+ TIMAEN
+ timer A enable
+ 15
+ 1
+
+
+ TIMB
+ Bus overtime B
+ 16
+ 12
+
+
+ TIMBEN
+ timer B enable
+ 31
+ 1
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ MSLVA
+ Matched Slave Address
+ 17
+ 7
+ read-only
+
+
+ DIRF
+ Slave Transfer direction
+ flag
+ 16
+ 1
+ read-only
+
+
+ BUSYF
+ Bus busy flag
+ 15
+ 1
+ read-only
+
+
+ SMBAF
+ SMBus alert flag
+ 13
+ 1
+ read-only
+
+
+ OVRTF
+ Overtime or tLOW detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERRF
+ PEC Error flag
+ 11
+ 1
+ read-only
+
+
+ OVRF
+ Slave Overflow/Underflow flag
+ 10
+ 1
+ read-only
+
+
+ ARBLOF
+ Arbitration lost flag
+ 9
+ 1
+ read-only
+
+
+ BUSERRF
+ Bus error flag
+ 8
+ 1
+ read-only
+
+
+ RLDF
+ Reload flag
+ 7
+ 1
+ read-only
+
+
+ CMPF
+ Master mode Transfer Complete
+ flag
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ NACK received flag
+ 4
+ 1
+ read-only
+
+
+ ADRF
+ Slave mode Address matched
+ flag
+ 3
+ 1
+ read-only
+
+
+ RXNEF
+ Data register not empty in
+ receiving mode
+ 2
+ 1
+ read-only
+
+
+ TXINTF
+ Transmit interrupt flag
+ 1
+ 1
+ read-write
+
+
+ TXEF
+ Data register empty flag in
+ transmitting mode
+ 0
+ 1
+ read-write
+
+
+
+
+ STSC
+ STSC
+ Status clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SMBAFC
+ SMBus alert flag clear
+ 13
+ 1
+
+
+ OVRTFC
+ Overtime detection flag
+ clear
+ 12
+ 1
+
+
+ PECERRFC
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRFC
+ Slave Overflow/Underflow
+ flag clear
+ 10
+ 1
+
+
+ ARLOFC
+ Arbitration Lost flag
+ clear
+ 9
+ 1
+
+
+ BUSERRFC
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPFC
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKFC
+ NACK received flag clear
+ 4
+ 1
+
+
+ ADRFC
+ Slave mode Address matched
+ flag clear
+ 3
+ 1
+
+
+
+
+ PECCODE
+ PECCODE
+ I2C received PEC code register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PECCODE
+ Received PEC code
+ 0
+ 8
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXBUF
+ Receive buffer register
+ 0
+ 8
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXBUF
+ Transmit buffer register
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ FWDT
+ Free Watchdog Timer
+ FWDT
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code(write only,
+ read 0x0000)
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ Pre-divider register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDIV
+ Pre-divider
+ 0
+ 3
+
+
+
+
+ UVAL
+ UVAL
+ Update register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ UVAL
+ Watchdog counter update
+ value
+ 0
+ 12
+
+
+
+
+ STS
+ STS
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DRF
+ FWDT divider refresh flag
+ 0
+ 1
+
+
+ UVRF
+ FWDT update value refresh
+ flag
+ 1
+ 1
+
+
+ WRF
+ FWDT window refresh flag
+ 2
+ 1
+
+
+
+
+ WINVAL
+ WINVAL
+ Window value register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WINVAL
+ FWDT window value
+ 0
+ 12
+
+
+
+
+
+
+ WWDT
+ Window Watchdog Timer
+ WWDT
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDT
+ Window Watchdog Timer interrupt
+ 0
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WWDTEN
+ Window watchdog timer enable
+ 7
+ 1
+
+
+ CVAL
+ Counter Value
+ 0
+ 7
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ RMDIE
+ Reminder interrupt enable
+ 9
+ 1
+
+
+ PDIV
+ Pre-divider
+ 7
+ 2
+
+
+ WVAL
+ window value
+ 0
+ 7
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RMDIF
+ Reminder interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ TIM1
+ Advanced-timers
+ TIM
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_UP_TRG_COM
+ TIM1 Break, Update, Trigger and Commutation
+ 13
+
+
+ TIM1_CC
+ TIM1 Capture Compare interrupt
+ 14
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO4
+ Idle value output of
+ channel 4
+ 14
+ 1
+
+
+ IVO3N
+ Idle value output of channel
+ 3 complementary
+ 13
+ 1
+
+
+ IVO3
+ Idle value output of channel 3
+ 12
+ 1
+
+
+ IVO2N
+ Idle value output of channel 2
+ complementary
+ 11
+ 1
+
+
+ IVO2
+ Idle value output of channel 2
+ 10
+ 1
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of
+ channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of
+ channel
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event interrupt
+ 5
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channe l communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel 2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH4CCG
+ Channel 4 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 3 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 2 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ CH2ICPDIV
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ IC1PCS
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3NCCEN
+ Channel 3 complementary capture compare
+ enable
+ 10
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2NCCEN
+ Channel 2 complementary capture compare
+ enable
+ 6
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update repetition register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ Counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL
+ Channel 2 capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL
+ Channel 3 capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL
+ Channel 4 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ channel output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM2
+ General-purpose-timers
+ TIM
+ 0x40000000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM2
+ TIM2 global interrupt
+ 15
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ CH4CCG
+ Channel 1 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 1 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 1 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode
+ selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value
+ preload enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ IC2PSC
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ channel 3 and channel 4 configuration register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4NCCP
+ Channel 4 complementary capture compare
+ Polarity
+ 15
+ 1
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL_H
+ High Counter update value (TIM2
+ only)
+ 16
+ 16
+
+
+ UVAL_L
+ Low Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL_H
+ Channel 1 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH1CCVAL_L
+ Channel 1 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL_H
+ Channel 2 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH2CCVAL_L
+ Channel 2 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL_H
+ Channel 3 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH3CCVAL_L
+ Channel 3 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL_L
+ Channel 4 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH4CCVAL_H
+ Channel 4 low capture compare value
+ 0
+ 16
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ 0x40000400
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ TIM14
+ General-purpose-timers
+ TIM
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM14
+ TIM14 global interrupt
+ 19
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ capture/compare mode register (input
+ mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ REMAP
+ REMAP
+ remap register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1IS
+ Channel 1 input selection
+ 0
+ 2
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LVD
+ LVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ INTEN
+ INTEN
+ Interrupt enable register
+ 0x0
+ 0x20
+ read-write
+ 0x0F940000
+
+
+ INTEN0
+ Interrupt enable for line 0
+ 0
+ 1
+
+
+ INTEN1
+ Interrupt enable for line 1
+ 1
+ 1
+
+
+ INTEN2
+ Interrupt enable for line 2
+ 2
+ 1
+
+
+ INTEN3
+ Interrupt enable for line 3
+ 3
+ 1
+
+
+ INTEN4
+ Interrupt enable for line 4
+ 4
+ 1
+
+
+ INTEN5
+ Interrupt enable for line 5
+ 5
+ 1
+
+
+ INTEN6
+ Interrupt enable for line 6
+ 6
+ 1
+
+
+ INTEN7
+ Interrupt enable for line 7
+ 7
+ 1
+
+
+ INTEN8
+ Interrupt enable for line 8
+ 8
+ 1
+
+
+ INTEN9
+ Interrupt enable for line 9
+ 9
+ 1
+
+
+ INTEN10
+ Interrupt enable for line 10
+ 10
+ 1
+
+
+ INTEN11
+ Interrupt enable for line 11
+ 11
+ 1
+
+
+ INTEN12
+ Interrupt enable for line 12
+ 12
+ 1
+
+
+ INTEN13
+ Interrupt enable for line 13
+ 13
+ 1
+
+
+ INTEN14
+ Interrupt enable for line 14
+ 14
+ 1
+
+
+ INTEN15
+ Interrupt enable for line 15
+ 15
+ 1
+
+
+ INTEN16
+ Interrupt enable for line 16
+ 16
+ 1
+
+
+ INTEN17
+ Interrupt enable for line 17
+ 17
+ 1
+
+
+ INTEN18
+ Interrupt enable for line 18
+ 18
+ 1
+
+
+ INTEN19
+ Interrupt enable for line 19
+ 19
+ 1
+
+
+ INTEN20
+ Interrupt enable for line 20
+ 20
+ 1
+
+
+ INTEN21
+ Interrupt enable for line 21
+ 21
+ 1
+
+
+ INTEN22
+ Interrupt enable for line 22
+ 22
+ 1
+
+
+ INTEN23
+ Interrupt enable for line 23
+ 23
+ 1
+
+
+ INTEN24
+ Interrupt enable for line 24
+ 24
+ 1
+
+
+ INTEN25
+ Interrupt enable for line 25
+ 25
+ 1
+
+
+ INTEN26
+ Interrupt enable for line 26
+ 26
+ 1
+
+
+ INTEN27
+ Interrupt enable for line 27
+ 27
+ 1
+
+
+
+
+ EVTEN
+ EVTEN
+ Event enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVTEN0
+ Event enable for line 0
+ 0
+ 1
+
+
+ EVTEN1
+ Event enable for line 1
+ 1
+ 1
+
+
+ EVTEN2
+ Event enable for line 2
+ 2
+ 1
+
+
+ EVTEN3
+ Event enable for line 3
+ 3
+ 1
+
+
+ EVTEN4
+ Event enable for line 4
+ 4
+ 1
+
+
+ EVTEN5
+ Event enable for line 5
+ 5
+ 1
+
+
+ EVTEN6
+ Event enable for line 6
+ 6
+ 1
+
+
+ EVTEN7
+ Event enable for line 7
+ 7
+ 1
+
+
+ EVTEN8
+ Event enable for line 8
+ 8
+ 1
+
+
+ EVTEN9
+ Event enable for line 9
+ 9
+ 1
+
+
+ EVTEN10
+ Event enable for line 10
+ 10
+ 1
+
+
+ EVTEN11
+ Event enable for line 11
+ 11
+ 1
+
+
+ EVTEN12
+ Event enable for line 12
+ 12
+ 1
+
+
+ EVTEN13
+ Event enable for line 13
+ 13
+ 1
+
+
+ EVTEN14
+ Event enable for line 14
+ 14
+ 1
+
+
+ EVTEN15
+ Event enable for line 15
+ 15
+ 1
+
+
+ EVTEN16
+ Event enable for line 16
+ 16
+ 1
+
+
+ EVTEN17
+ Event enable for line 17
+ 17
+ 1
+
+
+ EVTEN18
+ Event enable for line 18
+ 18
+ 1
+
+
+ EVTEN19
+ Event enable for line 19
+ 19
+ 1
+
+
+ EVTEN20
+ Event enable for line 20
+ 20
+ 1
+
+
+ EVTEN21
+ Event enable for line 21
+ 21
+ 1
+
+
+ EVTEN22
+ Event enable for line 22
+ 22
+ 1
+
+
+ EVTEN23
+ Event enable for line 23
+ 23
+ 1
+
+
+ EVTEN24
+ Event enable for line 24
+ 24
+ 1
+
+
+ EVTEN25
+ Event enable for line 25
+ 25
+ 1
+
+
+ EVTEN26
+ Event enable for line 26
+ 26
+ 1
+
+
+ EVTEN27
+ Event enable for line 27
+ 27
+ 1
+
+
+
+
+ RTEN
+ RTEN
+ Rising edge trigger enable register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTEN0
+ Rising edge trigger enable for line 0
+ 0
+ 1
+
+
+ RTEN1
+ Rising edge trigger enable for line 1
+ 1
+ 1
+
+
+ RTEN2
+ Rising edge trigger enable for line 2
+ 2
+ 1
+
+
+ RTEN3
+ Rising edge trigger enable for line 3
+ 3
+ 1
+
+
+ RTEN4
+ Rising edge trigger enable for line 4
+ 4
+ 1
+
+
+ RTEN5
+ Rising edge trigger enable for line 5
+ 5
+ 1
+
+
+ RTEN6
+ Rising edge trigger enable for line 6
+ 6
+ 1
+
+
+ RTEN7
+ Rising edge trigger enable for line 7
+ 7
+ 1
+
+
+ RTEN8
+ Rising edge trigger enable for line 8
+ 8
+ 1
+
+
+ RTEN9
+ Rising edge trigger enable for line 9
+ 9
+ 1
+
+
+ RTEN10
+ Rising edge trigger enable for line 10
+ 10
+ 1
+
+
+ RTEN11
+ Rising edge trigger enable for line 11
+ 11
+ 1
+
+
+ RTEN12
+ Rising edge trigger enable for line 12
+ 12
+ 1
+
+
+ RTEN13
+ Rising edge trigger enable for line 13
+ 13
+ 1
+
+
+ RTEN14
+ Rising edge trigger enable for line 14
+ 14
+ 1
+
+
+ RTEN15
+ Rising edge trigger enable for line 15
+ 15
+ 1
+
+
+ RTEN16
+ Rising edge trigger enable for line 16
+ 16
+ 1
+
+
+ RTEN17
+ Rising edge trigger enable for line 17
+ 17
+ 1
+
+
+ RTEN19
+ Rising edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ FTEN
+ FTEN
+ Falling edge trigger enable register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FTEN0
+ Falling edge trigger enable for line 0
+ 0
+ 1
+
+
+ FTEN1
+ Falling edge trigger enable for line 1
+ 1
+ 1
+
+
+ FTEN2
+ Falling edge trigger enable for line 2
+ 2
+ 1
+
+
+ FTEN3
+ Falling edge trigger enable for line 3
+ 3
+ 1
+
+
+ FTEN4
+ Falling edge trigger enable for line 4
+ 4
+ 1
+
+
+ FTEN5
+ Falling edge trigger enable for line 5
+ 5
+ 1
+
+
+ FTEN6
+ Falling edge trigger enable for line 6
+ 6
+ 1
+
+
+ FTEN7
+ Falling edge trigger enable for line 7
+ 7
+ 1
+
+
+ FTEN8
+ Falling edge trigger enable for line 8
+ 8
+ 1
+
+
+ FTEN9
+ Falling edge trigger enable for line 9
+ 9
+ 1
+
+
+ FTEN10
+ Falling edge trigger enable for line 10
+ 10
+ 1
+
+
+ FTEN11
+ Falling edge trigger enable for line 11
+ 11
+ 1
+
+
+ FTEN12
+ Falling edge trigger enable for line 12
+ 12
+ 1
+
+
+ FTEN13
+ Falling edge trigger enable for line 13
+ 13
+ 1
+
+
+ FTEN14
+ Falling edge trigger enable for line 14
+ 14
+ 1
+
+
+ FTEN15
+ Falling edge trigger enable for line 15
+ 15
+ 1
+
+
+ FTEN16
+ Falling edge trigger enable for line 16
+ 16
+ 1
+
+
+ FTEN17
+ Falling edge trigger enable for line 17
+ 17
+ 1
+
+
+ FTEN19
+ Falling edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ SWTIEN
+ SWTIEN
+ Software trigger interrupt/event
+ enable register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWTIEN0
+ Software trigger interrupt/event for
+ line 0
+ 0
+ 1
+
+
+ SWTIEN1
+ Software trigger interrupt/event for
+ line 1
+ 1
+ 1
+
+
+ SWTIEN2
+ Software trigger interrupt/event for
+ line 2
+ 2
+ 1
+
+
+ SWTIEN3
+ Software trigger interrupt/event for
+ line 3
+ 3
+ 1
+
+
+ SWTIEN4
+ Software trigger interrupt/event for
+ line 4
+ 4
+ 1
+
+
+ SWTIEN5
+ Software trigger interrupt/event for
+ line 5
+ 5
+ 1
+
+
+ SWTIEN6
+ Software trigger interrupt/event for
+ line 6
+ 6
+ 1
+
+
+ SWTIEN7
+ Software trigger interrupt/event for
+ line 7
+ 7
+ 1
+
+
+ SWTIEN8
+ Software trigger interrupt/event for
+ line 8
+ 8
+ 1
+
+
+ SWTIEN9
+ Software trigger interrupt/event for
+ line 9
+ 9
+ 1
+
+
+ SWTIEN10
+ Software trigger interrupt/event for
+ line 10
+ 10
+ 1
+
+
+ SWTIEN11
+ Software trigger interrupt/event for
+ line 11
+ 11
+ 1
+
+
+ SWTIEN12
+ Software trigger interrupt/event for
+ line 12
+ 12
+ 1
+
+
+ SWTIEN13
+ Software trigger interrupt/event for
+ line 13
+ 13
+ 1
+
+
+ SWTIEN14
+ Software trigger interrupt/event for
+ line 14
+ 14
+ 1
+
+
+ SWTIEN15
+ Software trigger interrupt/event for
+ line 15
+ 15
+ 1
+
+
+ SWTIEN16
+ Software trigger interrupt/event for
+ line 16
+ 16
+ 1
+
+
+ SWTIEN17
+ Software trigger interrupt/event for
+ line 17
+ 17
+ 1
+
+
+ SWTIEN19
+ Software trigger interrupt/event for
+ line 19
+ 19
+ 1
+
+
+
+
+ PDF
+ PDF
+ Pending flag register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDF0
+ Pending interrupt flag for line 0
+ 0
+ 1
+
+
+ PDF1
+ Pending interrupt flag for line 1
+ 1
+ 1
+
+
+ PDF2
+ Pending interrupt flag for line 2
+ 2
+ 1
+
+
+ PDF3
+ Pending interrupt flag for line 3
+ 3
+ 1
+
+
+ PDF4
+ Pending interrupt flag for line 4
+ 4
+ 1
+
+
+ PDF5
+ Pending interrupt flag for line 5
+ 5
+ 1
+
+
+ PDF6
+ Pending interrupt flag for line 6
+ 6
+ 1
+
+
+ PDF7
+ Pending interrupt flag for line 7
+ 7
+ 1
+
+
+ PDF8
+ Pending interrupt flag for line 8
+ 8
+ 1
+
+
+ PDF9
+ Pending interrupt flag for line 9
+ 9
+ 1
+
+
+ PDF10
+ Pending interrupt flag for line 10
+ 10
+ 1
+
+
+ PDF11
+ Pending interrupt flag for line 11
+ 11
+ 1
+
+
+ PDF12
+ Pending interrupt flag for line 12
+ 12
+ 1
+
+
+ PDF13
+ Pending interrupt flag for line 13
+ 13
+ 1
+
+
+ PDF14
+ Pending interrupt flag for line 14
+ 14
+ 1
+
+
+ PDF15
+ Pending interrupt flag for line 15
+ 15
+ 1
+
+
+ PDF16
+ Pending interrupt flag for line 16
+ 16
+ 1
+
+
+ PDF17
+ Pending interrupt flag for line 17
+ 17
+ 1
+
+
+ PDF19
+ Pending interrupt flag for line 19
+ 19
+ 1
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_00
+ PRI_00
+ 6
+ 2
+
+
+ PRI_01
+ PRI_01
+ 14
+ 2
+
+
+ PRI_02
+ PRI_02
+ 22
+ 2
+
+
+ PRI_03
+ PRI_03
+ 30
+ 2
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_40
+ PRI_40
+ 6
+ 2
+
+
+ PRI_41
+ PRI_41
+ 14
+ 2
+
+
+ PRI_42
+ PRI_42
+ 22
+ 2
+
+
+ PRI_43
+ PRI_43
+ 30
+ 2
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_80
+ PRI_80
+ 6
+ 2
+
+
+ PRI_81
+ PRI_81
+ 14
+ 2
+
+
+ PRI_82
+ PRI_82
+ 22
+ 2
+
+
+ PRI_83
+ PRI_83
+ 30
+ 2
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_120
+ PRI_120
+ 6
+ 2
+
+
+ PRI_121
+ PRI_121
+ 14
+ 2
+
+
+ PRI_122
+ PRI_122
+ 22
+ 2
+
+
+ PRI_123
+ PRI_123
+ 30
+ 2
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_160
+ PRI_160
+ 6
+ 2
+
+
+ PRI_161
+ PRI_161
+ 14
+ 2
+
+
+ PRI_162
+ PRI_162
+ 22
+ 2
+
+
+ PRI_163
+ PRI_163
+ 30
+ 2
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_200
+ PRI_200
+ 6
+ 2
+
+
+ PRI_201
+ PRI_201
+ 14
+ 2
+
+
+ PRI_202
+ PRI_202
+ 22
+ 2
+
+
+ PRI_203
+ PRI_203
+ 30
+ 2
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_240
+ PRI_240
+ 6
+ 2
+
+
+ PRI_241
+ PRI_241
+ 14
+ 2
+
+
+ PRI_242
+ PRI_242
+ 22
+ 2
+
+
+ PRI_243
+ PRI_243
+ 30
+ 2
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_280
+ PRI_280
+ 6
+ 2
+
+
+ PRI_281
+ PRI_281
+ 14
+ 2
+
+
+ PRI_282
+ PRI_282
+ 22
+ 2
+
+
+ PRI_283
+ PRI_283
+ 30
+ 2
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA channel 1 interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA channel 2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_5
+ DMA channel 4 and 5 interrupts
+ 11
+
+
+
+ STS
+ STS
+ DMA interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF1
+ Global interrupt flag of Channel 1
+ 0
+ 1
+
+
+ CMPIF1
+ Transfer complete flag of Channel 1
+ 1
+ 1
+
+
+ HLFIF1
+ Half transfer flag of Channel 1
+ 2
+ 1
+
+
+ TEIF1
+ Transfer error flag of Channel 1
+ 3
+ 1
+
+
+ GIF2
+ Global interrupt flag of Channel 2
+ 4
+ 1
+
+
+ CMPIF2
+ Transfer complete flag of Channel 2
+ 5
+ 1
+
+
+ HTIF2
+ Half transfer flag of Channel 2
+ 6
+ 1
+
+
+ TEIF2
+ Transfer error flag of Channel 2
+ 7
+ 1
+
+
+ GIF3
+ Global interrupt flag of Channel 3
+ 8
+ 1
+
+
+ CMPIF3
+ Transfer complete flag of Channel 3
+ 9
+ 1
+
+
+ HLFIF3
+ Half transfer flag of Channel 3
+ 10
+ 1
+
+
+ ERRIF3
+ Transfer error flag of Channel 3
+ 11
+ 1
+
+
+ GIF4
+ Global interrupt flag of Channel 4
+ 12
+ 1
+
+
+ CMPIF4
+ Transfer complete flag of Channel 4
+ 13
+ 1
+
+
+ HLFIF4
+ Half transfer flag of Channel 4
+ 14
+ 1
+
+
+ ERRIF4
+ Transfer error flag of Channel 4
+ 15
+ 1
+
+
+ GIF5
+ Global interrupt flag of Channel 5
+ 16
+ 1
+
+
+ CMPIF5
+ Transfer complete flag of Channel 5
+ 17
+ 1
+
+
+ HLFIF5
+ Half transfer flag of Channel 5
+ 18
+ 1
+
+
+ ERRIF5
+ Transfer error flag of Channel 5
+ 19
+ 1
+
+
+ GIF6
+ Global interrupt flag of Channel 6
+ 20
+ 1
+
+
+ CMPIF6
+ Transfer complete flag of Channel 6
+ 21
+ 1
+
+
+ HLFIF6
+ Half transfer flag of Channel 6
+ 22
+ 1
+
+
+ ERRIF6
+ Transfer error flag of Channel 6
+ 23
+ 1
+
+
+ GIF7
+ Global interrupt flag of Channel 7
+ 24
+ 1
+
+
+ CMPIF7
+ Transfer complete flag of Channel 7
+ 25
+ 1
+
+
+ HLFIF7
+ Half transfer flag of Channel 7
+ 26
+ 1
+
+
+ ERRIF7
+ Transfer error flag of Channel 7
+ 27
+ 1
+
+
+
+
+ INTFC
+ INTFC
+ DMA interrupt status clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Global interrupt flag clear of
+ Channel 1
+ 0
+ 1
+
+
+ CGIF2
+ Global interrupt flag clear of
+ Channel 2
+ 4
+ 1
+
+
+ CGIF3
+ Global interrupt flag clear of
+ Channel 3
+ 8
+ 1
+
+
+ CGIF4
+ Global interrupt flag clear of
+ Channel 4
+ 12
+ 1
+
+
+ CGIF5
+ Global interrupt flag clear of
+ Channel 5
+ 16
+ 1
+
+
+ CGIF6
+ Global interrupt flag clear of
+ Channel 6
+ 20
+ 1
+
+
+ CGIF7
+ Global interrupt flag clear of
+ Channel 7
+ 24
+ 1
+
+
+ CMPIFC1
+ Transfer complete flag clear of
+ Channel 1
+ 1
+ 1
+
+
+ CMPIFC2
+ Transfer complete flag clear of
+ Channel 2
+ 5
+ 1
+
+
+ CMPIFC3
+ Transfer complete flag clear of
+ Channel 3
+ 9
+ 1
+
+
+ CMPIFC4
+ Transfer complete flag clear of
+ Channel 4
+ 13
+ 1
+
+
+ CMPIFC5
+ Transfer complete flag clear of
+ Channel 5
+ 17
+ 1
+
+
+ CMPIFC6
+ Transfer complete flag clear of
+ Channel 6
+ 21
+ 1
+
+
+ CMPIFC7
+ Transfer complete flag clear of
+ Channel 7
+ 25
+ 1
+
+
+ HLFIFC1
+ Half transfer flag clear of
+ Channel 1
+ 2
+ 1
+
+
+ HLFIFC2
+ Half transfer flag clear of
+ Channel 2
+ 6
+ 1
+
+
+ HLFIFC3
+ Half transfer flag clear of
+ Channel 3
+ 10
+ 1
+
+
+ HLFIFC4
+ Half transfer flag clear of
+ Channel 4
+ 14
+ 1
+
+
+ HLFIFC5
+ Half transfer flag clear of
+ Channel 5
+ 18
+ 1
+
+
+ HLFIFC6
+ Half transfer flag clear of
+ Channel 6
+ 22
+ 1
+
+
+ HLFIFC7
+ Half transfer flag clear of
+ Channel 7
+ 26
+ 1
+
+
+ ERRIFC1
+ Transfer error flag clear of
+ Channel 1
+ 3
+ 1
+
+
+ ERRIFC2
+ Transfer error flag clear of
+ Channel 2
+ 7
+ 1
+
+
+ ERRIFC3
+ Transfer error flag clear of
+ Channel 3
+ 11
+ 1
+
+
+ ERRIFC4
+ Transfer error flag clear of
+ Channel 4
+ 15
+ 1
+
+
+ ERRIFC5
+ Transfer error flag clear of
+ Channel 5
+ 19
+ 1
+
+
+ ERRIFC6
+ Transfer error flag clear of
+ Channel 6
+ 23
+ 1
+
+
+ ERRIFC7
+ Transfer error flag clear of
+ Channel 7
+ 27
+ 1
+
+
+
+
+ CH1CTR
+ CH1CTR
+ DMA channel 1 controller register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CEN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH1NUM
+ CH1NUM
+ Transfer data number register of DMA
+ channel 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH1PA
+ CH1PA
+ Peripheral address register of
+ DMA channel 1
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH1MA
+ CH1MA
+ Memory address register of
+ DMA channel 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH2CTR
+ CH2CTR
+ DMA channel 2 controller register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH2NUM
+ CH2NUM
+ Transfer data number register of
+ DMA channel 2
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH2PA
+ CH2PA
+ Peripheral address register of
+ DMA channel 2
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH2MA
+ CH2MA
+ Memory address register of DMA
+ channel 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH3CTR
+ CH3CTR
+ DMA channel 3 controller register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH3NUM
+ CH3NUM
+ Transfer data number register of
+ DMA channel 3
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH3PA
+ CH3PA
+ Peripheral address register of
+ DMA channel 3
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH3MA
+ CH3MA
+ Memory address register of
+ DMA channel 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH4CTR
+ CH4CTR
+ DMA channel 4 controller register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH4NUM
+ CH4NUM
+ Transfer data number register of
+ DMA channel 4
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH4PA
+ CH4PA
+ Peripheral address register of
+ DMA channel 4
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH4MA
+ CH4MA
+ Memory address register of
+ DMA channel 4
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH5CTR
+ CH5CTR
+ DMA channel 5 controller register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH5NUM
+ CH5NUM
+ Transfer data number register of
+ DMA channel 5
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH5PA
+ CH5PA
+ Peripheral address register of
+ DMA channel 5
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH5MA
+ CH5MA
+ Memory address register of
+ DMA channel 5
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH6CTR
+ CH6CTR
+ DMA channel 6 controller register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH6NUM
+ CH6NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH6PA
+ CH6PA
+ Peripheral address register of
+ DMA channel 6
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH6MA
+ CH6MA
+ Memory address register of
+ DMA channel 6
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH7CTR
+ CH7CTR
+ DMA channel 7 controller register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH7NUM
+ CH7NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH7PA
+ CH7PA
+ Peripheral address register of
+ DMA channel 7
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH7MA
+ CH7MA
+ Memory address register of
+ DMA channel 7
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ RCU
+ Reset and clock unit
+ RCU
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCU
+ RCU global interrupt
+ 4
+
+
+
+ CTR
+ CTR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ HRCEN
+ HRC Enable
+ 0
+ 1
+ read-write
+
+
+ HRCSTAB
+ HRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ HRCTRIM
+ HRC Triming
+ 3
+ 5
+ read-write
+
+
+ HRCCALIB
+ HRC Internal 8MHz RC calibration
+ 8
+ 8
+ read-only
+
+
+ HXTEN
+ HXT Enable
+ 16
+ 1
+ read-write
+
+
+ HXTSTAB
+ HXT Stabilization flag
+ 17
+ 1
+ read-only
+
+
+ HXTBPS
+ HXT Bypass Enable
+ 18
+ 1
+ read-write
+
+
+ HXTME
+ HXT Monitor Enable
+ 19
+ 1
+ read-write
+
+
+ HXTDRV
+ HXT Drive capability Selection
+ 21
+ 2
+ read-write
+
+
+ PLLEN
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ PLLSTAB
+ PLL Stabilization flag
+ 25
+ 1
+ read-only
+
+
+
+
+ CFG
+ CFG
+ Clock configuration register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SYSSW
+ System clock switch Control
+ 0
+ 2
+ read-write
+
+
+ SYSSS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ HCLKPDIV
+ HCLK Pre-divider
+ 4
+ 4
+ read-write
+
+
+ PCLKPDIV
+ PCLK Pre-divider
+ 8
+ 3
+ read-write
+
+
+ ADCPDIV
+ ADC Clock Pre-divider
+ 14
+ 1
+ read-write
+
+
+ PLLSEL
+ PLL source Selction
+ 15
+ 2
+ read-write
+
+
+ PLLHXTPDIV
+ PLL source HXT pre-divdier
+ 17
+ 1
+ read-write
+
+
+ PLLMUF
+ PLL clock multiplication factor
+ 18
+ 4
+ read-write
+
+
+ CKOSEL
+ CLKOUT Source Selection
+ 24
+ 4
+ read-write
+
+
+ CKOPDIV
+ CLKOUT Pre-divider
+ 28
+ 3
+ read-write
+
+
+ CKOPLLND
+ PLL clock not divided for CLKOUT
+ 31
+ 1
+ read-write
+
+
+
+
+ INTR
+ INTR
+ Clock interrupt register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LRCSTABIF
+ LRC stabilization interrupt flag
+ 0
+ 1
+ read-only
+
+
+ LXTSTABIF
+ LXT stabilization interrupt flag
+ 1
+ 1
+ read-only
+
+
+ HRCSTABIF
+ HRC stabilization interrupt flag
+ 2
+ 1
+ read-only
+
+
+ HXTSTABIF
+ HXT stabilization interrupt flag
+ 3
+ 1
+ read-only
+
+
+ PLLSTABIF
+ PLL stabilization interrupt flag
+ 4
+ 1
+ read-only
+
+
+ HRC14STABIF
+ HRC14 stabilization interrupt flag
+ 5
+ 1
+ read-only
+
+
+ CKFAILIF
+ HXT clock fail interrupt flag
+ 7
+ 1
+ read-only
+
+
+ LRCSTABIE
+ LRC stabilization interrupt enable
+ 8
+ 1
+ read-write
+
+
+ LXTSTABIE
+ LXT stabilization interrupt enable
+ 9
+ 1
+ read-write
+
+
+ HRCSTABIE
+ HRC stabilization Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ HXTSTABIE
+ HXT stabilization Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ PLLSTABIE
+ PLL stabilization Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ HRC14STABIE
+ HRC14 stabilization Interrupt Enable
+ 13
+ 1
+ read-write
+
+
+ LRCSTABIC
+ LRC stabilization Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ LXTSTABIC
+ LXT stabilization Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ HRCSTABIC
+ HRC stabilization Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ HXTSTABIC
+ HXT stabilization Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ PLLSTABIC
+ PLL stabilization Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ HRC14STABIC
+ HRC14 stabilization Interrupt Clear
+ 21
+ 1
+ write-only
+
+
+ CKFAILIC
+ HXT Clock Fail Interrupt Clear
+ 23
+ 1
+ write-only
+
+
+
+
+ APB2RST
+ APB2RST
+ APB2 reset register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGRST
+ SYSCFG reset
+ 0
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ TIM16RST
+ TIM16 timer reset
+ 17
+ 1
+
+
+ TIM17RST
+ TIM17 timer reset
+ 18
+ 1
+
+
+ DBGRST
+ Debug MCU reset
+ 22
+ 1
+
+
+
+
+ APB1RST
+ APB1RST
+ APB1 reset register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM14RST
+ Timer 14 reset
+ 8
+ 1
+
+
+ WWDTRST
+ WWDT reset
+ 11
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ PMURST
+ PMU reset
+ 28
+ 1
+
+
+
+
+ AHBEN
+ AHBEN
+ AHB Clock enable register
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ DMAEN
+ enable bit for DMA clock
+ 0
+ 1
+
+
+ RMCEN
+ enable bit for SRAM clock
+ 2
+ 1
+
+
+ FMCEN
+ enable bit for FMC clock
+ 4
+ 1
+
+
+ CRCEN
+ enable bit for CRC clock
+ 6
+ 1
+
+
+ PAEN
+ enable bit for GPIO port A clock
+ 17
+ 1
+
+
+ PBEN
+ enable bit for GPIO port B clock
+ 18
+ 1
+
+
+ PCEN
+ enable bit for GPIO port C clock
+ 19
+ 1
+
+
+ PDEN
+ enable bit for GPIO port D clock
+ 20
+ 1
+
+
+ PEEN
+ enable bit for GPIO port E clock
+ 21
+ 1
+
+
+ PFEN
+ enable bit for GPIO port F clock
+ 22
+ 1
+
+
+
+
+ APB2EN
+ APB2EN
+ APB peripheral clock enable register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGEN
+ enable bit for SYSCFG clock
+ 0
+ 1
+
+
+ ADCEN
+ enable bit for ADC clock
+ 9
+ 1
+
+
+ TIM1EN
+ enable bit for TIM1 clock
+ 11
+ 1
+
+
+ SPI1EN
+ enable bit for SPI1 clock
+ 12
+ 1
+
+
+ USART1EN
+ enable bit for USART1 clock
+ 14
+ 1
+
+
+ TIM16EN
+ enable bit for TIM16 clock
+ 17
+ 1
+
+
+ TIM17EN
+ enable bit for TIM17 clock
+ 18
+ 1
+
+
+ DBGEN
+ enable bit for DBG clock
+ 22
+ 1
+
+
+
+
+ APB1EN
+ APB1EN
+ APB peripheral clock enable register 1
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2EN
+ Tenable bit for TIM2 clock
+ 0
+ 1
+
+
+ TIM3EN
+ enable bit for TIM3 clock
+ 1
+ 1
+
+
+ TIM14EN
+ enable bit for TIM14 clock
+ 8
+ 1
+
+
+ WWDTEN
+ enable bit for WWDT clock
+ 11
+ 1
+
+
+ I2C1EN
+ enable bit for I2C1 clock
+ 21
+ 1
+
+
+ PMUEN
+ enable bit for PMU clock
+ 28
+ 1
+
+
+
+
+ VBDC
+ VBDC
+ VBAT domain control register
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ LXTEN
+ LXT Enable
+ 0
+ 1
+ read-write
+
+
+ LXTSTAB
+ LXT Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ LXTBYP
+ LXT bypass
+ 2
+ 1
+ read-write
+
+
+ LXTDRV
+ LXT oscillator drive capability
+ 3
+ 3
+ read-write
+
+
+ RTCSRC
+ RTC clock source selection
+ 8
+ 2
+ read-write
+
+
+ RTCCLKEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ VBTRST
+ VBAT domain software reset
+ 16
+ 1
+ read-write
+
+
+
+
+ STS
+ STS
+ status register
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LRCEN
+ LRC enable
+ 0
+ 1
+ read-write
+
+
+ LRCSTAB
+ LRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ REGERRRSTF
+ register error flag
+ 22
+ 1
+ read-only
+
+
+ V15RSTF
+ Reset flag from the 1.5V domain
+ 23
+ 1
+ read-only
+
+
+ CRSTF
+ Clear reset flag
+ 24
+ 1
+ read-write
+
+
+ OBURSTF
+ Option byte update reset
+ flag
+ 25
+ 1
+ read-write
+
+
+ NRSTF
+ reset flag of pin nRST
+ 26
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ SWRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ FWDTRSTF
+ FWDT reset flag
+ 29
+ 1
+ read-write
+
+
+ WWDTRSTF
+ WWDT reset flag
+ 30
+ 1
+ read-write
+
+
+ LPERSTF
+ Low-power mode enter-reset flag
+ 31
+ 1
+ read-write
+
+
+
+
+ AHBRST
+ AHBRST
+ AHB reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PARST
+ GPIO port A reset
+ 17
+ 1
+
+
+ PBRST
+ GPIO port B reset
+ 18
+ 1
+
+
+ PCRST
+ GPIO port C reset
+ 19
+ 1
+
+
+ PDRST
+ GPIO port D reset
+ 20
+ 1
+
+
+ PERST
+ GPIO port E reset
+ 21
+ 1
+
+
+ PFRST
+ GPIO port F reset
+ 22
+ 1
+
+
+
+
+ CFG2
+ CFG2
+ Clock configuration register 2
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PLLPDIV
+ PLL pre-divider factor
+ 0
+ 4
+
+
+
+
+ CFG3
+ CFG3
+ Clock configuration register 3
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ USART1SEL
+ Selection of USART1 Clock
+ 0
+ 2
+
+
+ I2C1SEL
+ Selection of I2C1 Clock
+ 4
+ 1
+
+
+ ADCSEL
+ Selection of ADC Clock
+ 8
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Clock control register 2
+ 0x34
+ 0x20
+ 0x00000080
+
+
+ HRC14EN
+ HRC14 enable
+ 0
+ 1
+ read-write
+
+
+ HRC14STAB
+ HRC14 Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ ADCDISHRC14
+ ADC control HRC14 opening disable
+ 2
+ 1
+ read-write
+
+
+ HRC14TRIM
+ HRC14 Triming
+ 3
+ 5
+ read-write
+
+
+ HRC14CALIB
+ HRC14 calibration
+ 8
+ 8
+ read-only
+
+
+
+
+
+
+ SYSCFG
+ System configuration
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ RMAPCFG
+ RMAPCFG
+ SYSCFG remap configuration
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C_FMPEN_PA10
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 23
+ 1
+
+
+ I2C_FMPEN_PA9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 22
+ 1
+
+
+ I2C_FMPEN_PB9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 19
+ 1
+
+
+ I2C_FMPEN_PB8
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 18
+ 1
+
+
+ I2C_FMPEN_PB7
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 17
+ 1
+
+
+ I2C_FMPEN_PB6
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 16
+ 1
+
+
+ TIM17_DMA_CHRMAP
+ TIM17 DMA channel remapping
+ 12
+ 1
+
+
+ TIM16_DMA_CHRMAP
+ TIM16 DMA channel remapping
+ 11
+ 1
+
+
+ USART1_RX_DMA_CHRMAP
+ USART1 RX DMA channel remapping
+ 10
+ 1
+
+
+ USART1_TX_DMA_CHRMAP
+ USART1 TX DMA channel remapping
+ 9
+ 1
+
+
+ ADC_DMA_CHRMAP
+ ADC DMA channel remapping
+ 8
+ 1
+
+
+ MEM_RMAP
+ Memory remapping selection
+ 0
+ 2
+
+
+
+
+ EXTISRC1
+ EXTISRC1
+ external interrupt source selection register 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL3
+ External interrupt source selection 3
+ 12
+ 4
+
+
+ EXTI_SEL2
+ External interrupt source selection 2
+ 8
+ 4
+
+
+ EXTI_SEL1
+ External interrupt source selection 1
+ 4
+ 4
+
+
+ EXTI_SEL0
+ External interrupt source selection 0
+ 0
+ 4
+
+
+
+
+ EXTISRC2
+ EXTISRC2
+ external interrupt source selection register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL7
+ External interrupt source selection 7
+ 12
+ 4
+
+
+ EXTI_SEL6
+ External interrupt source selection 6
+ 8
+ 4
+
+
+ EXTI_SEL5
+ External interrupt source selection 5
+ 4
+ 4
+
+
+ EXTI_SEL4
+ External interrupt source selection 4
+ 0
+ 4
+
+
+
+
+ EXTISRC3
+ EXTISRC3
+ external interrupt source selection register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL11
+ External interrupt source selection 11
+ 12
+ 4
+
+
+ EXTI_SEL10
+ External interrupt source selection 10
+ 8
+ 4
+
+
+ EXTI_SEL9
+ External interrupt source selection 9
+ 4
+ 4
+
+
+ EXTI_SEL8
+ External interrupt source selection 8
+ 0
+ 4
+
+
+
+
+ EXTISRC4
+ EXTISRC4
+ external interrupt source selection register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL15
+ External interrupt source selection 15
+ 12
+ 4
+
+
+ EXTI_SEL14
+ External interrupt source selection 14
+ 8
+ 4
+
+
+ EXTI_SEL13
+ External interrupt source selection 13
+ 4
+ 4
+
+
+ EXTI_SEL12
+ External interrupt source selection 12
+ 0
+ 4
+
+
+
+
+ ERRLOCK
+ ERRLOCK
+ error and timer break lock
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ SRAM_PRTY_ERR
+ SRAM parity error flag
+ 8
+ 1
+
+
+ PVD_TIMBRK_LOCK
+ PVD output lock to tim
+ break enable
+ 2
+ 1
+
+
+ SRAM_PRTY_TIMBRK_LOCK
+ SRAM parity lock to
+ tim break
+ 1
+ 1
+
+
+ LOCKUP_TIMBRK_LOCK
+ Cortex-M0 LOCKUP lock to tim
+ break enable
+ 0
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ STAT
+ STAT
+ ADC status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVT
+ analog watchdog event flag
+ 7
+ 1
+
+
+ DOVR
+ ADC data overrun flag
+ 4
+ 1
+
+
+ EOCG
+ End of conversion group flag
+ 3
+ 1
+
+
+ EOCH
+ End of channel conversion flag
+ 2
+ 1
+
+
+ EOSP
+ End of sampling phase flag
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization
+ 0
+ 1
+
+
+
+
+ INTEN
+ INTEN
+ ADC interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVTIE
+ analog watchdog event interrupt
+ enable
+ 7
+ 1
+
+
+ DATOVR
+ ADC data overrun interrupt enable
+ 4
+ 1
+
+
+ EOGIE
+ End of conversion group interrupt
+ enable
+ 3
+ 1
+
+
+ EOC
+ End of channel conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSMPL
+ End of sampling phase interrupt
+ enable
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ CTR
+ CTR
+ ADC general control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALB
+ ADC calibration control
+ 31
+ 1
+
+
+ ADSTOP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADSTRT
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADCOFF
+ ADC power off command
+ 1
+ 1
+
+
+ ADCON
+ ADC power on command
+ 0
+ 1
+
+
+
+
+ CFG
+ CFG
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDGCHAN
+ Analog watchdog monitor channel
+ selection
+ 26
+ 5
+
+
+ WDGEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ WDGCHMODE
+ Analog watchdog channel monitor
+ mode
+ 22
+ 1
+
+
+ DISCONT
+ Discontinuous conversion mode
+ 16
+ 1
+
+
+ ATSTDBY
+ auto standby mode
+ 15
+ 1
+
+
+ PAUSE
+ conversion pause mode
+ 14
+ 1
+
+
+ GCONT
+ Group conversion Single/continuous
+ mode
+ 13
+ 1
+
+
+ DOVRWRT
+ Coversion data overrun overwriten
+ mode
+ 12
+ 1
+
+
+ TRGMODE
+ Coverstion Trigger mode selection
+ 10
+ 2
+
+
+ HTRGSEL
+ Hardware trigger source selection
+ 6
+ 3
+
+
+ DATALG
+ Coversion data format alignment
+ 5
+ 1
+
+
+ DATRES
+ Coversion data reselution
+ 3
+ 2
+
+
+ CGDIR
+ Coveration group sequence
+ direction
+ 2
+ 1
+
+
+ DMAMODE
+ Direct memory access
+ single/circle mode
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CLK
+ CLK
+ clock source register
+ 0x10
+ 0x20
+ read-write
+ 0x00008000
+
+
+ CKSRC
+ ADC clock source selection
+ 30
+ 2
+
+
+
+
+ SMPLR
+ SMPLR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPLT
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ WDTH
+ WDTH
+ Analog watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ HITH
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LOTH
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHANSEL
+ CHANSEL
+ conversion channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHANSEL18
+ conversion channel selection x
+ 18
+ 1
+
+
+ CHANSEL17
+ conversion channel selection x
+ 17
+ 1
+
+
+ CHANSEL16
+ conversion channel selection x
+ 16
+ 1
+
+
+ CHANSEL15
+ conversion channel selection x
+ 15
+ 1
+
+
+ CHANSEL14
+ conversion channel selection x
+ 14
+ 1
+
+
+ CHANSEL13
+ conversion channel selection x
+ 13
+ 1
+
+
+ CHANSEL12
+ conversion channel selection x
+ 12
+ 1
+
+
+ CHANSEL11
+ conversion channel selection x
+ 11
+ 1
+
+
+ CHANSEL10
+ conversion channel selection x
+ 10
+ 1
+
+
+ CHANSEL9
+ conversion channel selection x
+ 9
+ 1
+
+
+ CHANSEL8
+ conversion channel selection x
+ 8
+ 1
+
+
+ CHANSEL7
+ conversion channel selection x
+ 7
+ 1
+
+
+ CHANSEL6
+ conversion channel selection x
+ 6
+ 1
+
+
+ CHANSEL5
+ conversion channel selection x
+ 5
+ 1
+
+
+ CHANSEL4
+ conversion channel selection x
+ 4
+ 1
+
+
+ CHANSEL3
+ conversion channel selection x
+ 3
+ 1
+
+
+ CHANSEL2
+ conversion channel selection x
+ 2
+ 1
+
+
+ CHANSEL1
+ conversion channel selection x
+ 1
+ 1
+
+
+ CHANSEL0
+ conversion channel selection x
+ 0
+ 1
+
+
+
+
+ OUTDAT
+ OUTDAT
+ conversion output data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OUTDAT
+ conversion output data
+ 0
+ 16
+
+
+
+
+ INNCHEN
+ INNCHEN
+ internal conversion channel enable
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBATMEN
+ VBAT monitor enable
+ 24
+ 1
+
+
+ TPSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VREFINTEN
+ VREFINT enable
+ 22
+ 1
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTCIE
+ Enable bit for Block transmit
+ complete interrupt
+ 27
+ 1
+
+
+ OVRTIE
+ Enable bit for Receiver overtime
+ interrupt
+ 26
+ 1
+
+
+ PRETDE
+ Pre-active time for Driver
+ Enable
+ 21
+ 5
+
+
+ POSTDE
+ Pos-active time for Driver
+ Enable
+ 16
+ 5
+
+
+ OVRS
+ Oversampling selection
+ 15
+ 1
+
+
+ CMIE
+ Enable bit for Character
+ match interrupt
+ 14
+ 1
+
+
+ RXMSKEN
+ Reception mask mode enable
+ 13
+ 1
+
+
+ DL
+ Data length
+ 12
+ 1
+
+
+ RXWKUPS
+ Receiver wakeup selection
+ 11
+ 1
+
+
+ PEN
+ Parity enable
+ 10
+ 1
+
+
+ ODDS
+ Odd parity selection
+ 9
+ 1
+
+
+ PERRIE
+ Enable bit for parity err
+ interrupt
+ 8
+ 1
+
+
+ TXEIE
+ Enable bit for transmit empty
+ interrupt
+ 7
+ 1
+
+
+ TCIE
+ Enable bit for transmit
+ complete interrupt
+ 6
+ 1
+
+
+ RXNEIE
+ Enable bit for RXNE interrupt
+ 5
+ 1
+
+
+ IDLEIE
+ Enable bit for IDLE interrupt
+ 4
+ 1
+
+
+ TEN
+ Transmitter enable
+ 3
+ 1
+
+
+ REN
+ Receiver enable
+ 2
+ 1
+
+
+ WKUPSTOP
+ Wakeup mcu from stop mode enable
+ 1
+ 1
+
+
+ UEN
+ USART enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ UADR_4
+ USART Address
+ 28
+ 4
+
+
+ UADR_0
+ USART Address
+ 24
+ 4
+
+
+ ROTEN
+ Receiver overtime enable
+ 23
+ 1
+
+
+ ABRSEL
+ Auto baud rate mode selection
+ 21
+ 2
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBF
+ MSB first
+ 19
+ 1
+
+
+ DINV
+ Data bit inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin inversion
+ 16
+ 1
+
+
+ TXRXSWAP
+ TX/RX pins swap enable
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOPLEN
+ STOP bits length
+ 12
+ 2
+
+
+ CKEN
+ CK pin enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ CKLEN
+ LCK length
+ 8
+ 1
+
+
+ LBDIE
+ Enable bit for LIN break frame
+ detection interrupt
+ 6
+ 1
+
+
+ LINBRK11
+ 11-bit break frame detection
+ 5
+ 1
+
+
+ ADRM7
+ 4bit/7bit Address Detection selection
+ 4
+ 1
+
+
+
+
+ CTR3
+ CTR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPIE
+ Enable bit for Wakeup from
+ Stop mode interrupt
+ 22
+ 1
+
+
+ WKUPMTHD
+ Wakeup from Stop mode method
+ 20
+ 2
+
+
+ SCANUM
+ Number of Smartcard auto-retry times
+ 17
+ 3
+
+
+ DEPS
+ DE polarity selection
+ 15
+ 1
+
+
+ DEN
+ DE enable
+ 14
+ 1
+
+
+ DRMRE
+ DMA request mask on Reception
+ Error
+ 13
+ 1
+
+
+ NORXOF
+ No Receive Overflow detection
+ 12
+ 1
+
+
+ SPMS
+ Sample method selection
+ 11
+ 1
+
+
+ CTSIE
+ Enable bit for CTS interrupt
+ 10
+ 1
+
+
+ CTSEN
+ CTS enable
+ 9
+ 1
+
+
+ RTSEN
+ RTS enable
+ 8
+ 1
+
+
+ TXDMA
+ Transmit with DMA
+ 7
+ 1
+
+
+ RXDMA
+ Receive with DMA
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ SCNACK
+ Smartcard transmit NACK in parity error
+ 4
+ 1
+
+
+ HDEN
+ Half-duplex enable
+ 3
+ 1
+
+
+ IRMS
+ IrDA mode selection
+ 2
+ 1
+
+
+ IRDAEN
+ IrDA mode enable
+ 1
+ 1
+
+
+ ERRIE
+ Enable bit for Error interrupt
+ 0
+ 1
+
+
+
+
+ BRT
+ BRT
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ INTDIV
+ DIV INT value
+ 4
+ 12
+
+
+ FRADIV
+ DIV Fraction value
+ 0
+ 4
+
+
+
+
+ GTPDIV
+ GTPDIV
+ Guard time and pre-divider
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GUDT
+ Guard time value
+ 8
+ 8
+
+
+ PDIV
+ Pre-divider value
+ 0
+ 8
+
+
+
+
+ RXOVR
+ RXOVR
+ Receiver overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ NUMBLK
+ Unit number of block
+ 24
+ 8
+
+
+ RXOVR
+ Receiver overtime value
+ 0
+ 24
+
+
+
+
+ SWTR
+ SWTR
+ Software Trigger register
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXESET
+ TXE set trigger
+ 4
+ 1
+
+
+ RXNECLR
+ RXNE clear trigger
+ 3
+ 1
+
+
+ RXMSKT
+ Reception mask mode trigger
+ 2
+ 1
+
+
+ BRKFST
+ Break frame send trigger
+ 1
+ 1
+
+
+ ABRT
+ Auto baud rate trigger
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ Interrupt and status register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ RENACTF
+ REN active flag
+ 22
+ 1
+
+
+ TENACTF
+ TEN active flag
+ 21
+ 1
+
+
+ WKUPF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RXMSKF
+ Reception mask mode flag
+ 19
+ 1
+
+
+ BRKSF
+ Break frame send flag
+ 18
+ 1
+
+
+ CMF
+ Character match flag
+ 17
+ 1
+
+
+ BUSY
+ Busy flag
+ 16
+ 1
+
+
+ ABRTF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABRTERRF
+ Auto baud rate error flag
+ 14
+ 1
+
+
+ ENDBLKF
+ End of block flag
+ 12
+ 1
+
+
+ ROTF
+ Receiver overtime flag
+ 11
+ 1
+
+
+ CTSF
+ CTS flag
+ 10
+ 1
+
+
+ CTSIF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LINBKF
+ LIN break frame detection flag
+ 8
+ 1
+
+
+ TXE
+ transmit buffer empty flag
+ 7
+ 1
+
+
+ TCF
+ Transmission complete flag
+ 6
+ 1
+
+
+ RXNE
+ receiver buffer not empty
+ flag
+ 5
+ 1
+
+
+ IDLEF
+ Idle frame detected flag
+ 4
+ 1
+
+
+ OVRERRF
+ Reception overflow error
+ flag
+ 3
+ 1
+
+
+ NF
+ Noise flag
+ 2
+ 1
+
+
+ FERRF
+ Frame error flag
+ 1
+ 1
+
+
+ PERRF
+ Parity error flag
+ 0
+ 1
+
+
+
+
+ IFCLR
+ IFCLR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPFC
+ Wakeup from Stop mode flag
+ clear
+ 20
+ 1
+
+
+ CMFC
+ Character match flag clear
+ 17
+ 1
+
+
+ ENDBLKFC
+ End of block flag clear
+ 12
+ 1
+
+
+ ROTFC
+ Receiver overtime flag clear
+ 11
+ 1
+
+
+ CTSFC
+ CTS flag clear
+ 9
+ 1
+
+
+ LINBKFC
+ LIN break frame detection flag
+ clear
+ 8
+ 1
+
+
+ TCFC
+ Transmission complete flag
+ clear
+ 6
+ 1
+
+
+ IDLEFC
+ Idle frame detected flag
+ clear
+ 4
+ 1
+
+
+ OVRERRC
+ Overrun error flag clear
+ 3
+ 1
+
+
+ STARTNFC
+ Start bit Noise detected
+ flag clear
+ 2
+ 1
+
+
+ FERRC
+ Frame error flag clear
+ 1
+ 1
+
+
+ PERRC
+ Parity error flag clear
+ 0
+ 1
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RXBUF
+ Receive buffer
+ 0
+ 9
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXBUF
+ Transmit buffer
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ USART3
+ 0x40004800
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ USART4
+ 0x40004C00
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ USART5
+ 0x40005000
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ USART6
+ 0x40011400
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ USART7
+ 0x40011800
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ USART8
+ 0x40011C00
+
+ USART3_8
+ USART3_8 global interrupt
+ 29
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ RTC global interrupt
+ 2
+
+
+
+ TIME
+ TIME
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MINTEN
+ Minute tens in BCD format
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD format
+ 8
+ 4
+
+
+ SECTEN
+ Second tens in BCD format
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD format
+ 0
+ 4
+
+
+
+
+ DATE
+ DATE
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YTEN
+ Year tens in BCD format
+ 20
+ 4
+
+
+ YUNT
+ Year units in BCD format
+ 16
+ 4
+
+
+ WUNT
+ Week day units
+ 13
+ 3
+
+
+ MTEN
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MUNT
+ Month units in BCD format
+ 8
+ 4
+
+
+ DTEN
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DUNT
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ CTR
+ CTR
+ control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ TRESEL
+ Time recording edge select
+ 3
+ 1
+ read-write
+
+
+ OPCLKEN
+ outside precise clock detection enable
+ 4
+ 1
+ read-write
+
+
+ DAR
+ direct access registers
+ 5
+ 1
+ read-write
+
+
+ FMT12
+ 12/24 format
+ 6
+ 1
+ read-write
+
+
+ ALRE
+ Alarm enable
+ 8
+ 1
+ read-write
+
+
+ TRE
+ Time recording enable
+ 11
+ 1
+ read-write
+
+
+ ALRIE
+ Alarm interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TRIE
+ Time recording interrupt enable
+ 15
+ 1
+ read-write
+
+
+ INC1H
+ increase 1 hour
+ 16
+ 1
+ write-only
+
+
+ DEC1H
+ decrease 1 hour
+ 17
+ 1
+ write-only
+
+
+ SAVEF
+ saving time flag
+ 18
+ 1
+ read-write
+
+
+ CALSRC
+ Calibration output source
+ 19
+ 1
+ read-write
+
+
+ APOL
+ Alarm Output polarity
+ 20
+ 1
+ read-write
+
+
+ OUTSRC
+ Output source
+ 21
+ 2
+ read-write
+
+
+ CALOE
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+
+
+ STS
+ STS
+ status register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ ALRWAF
+ Alarm write access flag
+ 0
+ 1
+ read-only
+
+
+ SHF_BUSY
+ Shift busy
+ 3
+ 1
+ read-write
+
+
+ INITS
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ RSF
+ Registers synchronization flag
+ 5
+ 1
+ read-write
+
+
+ INITF
+ Initialization mode endter flag
+ 6
+ 1
+ read-only
+
+
+ INITE
+ Initialization mode enbale
+ 7
+ 1
+ read-write
+
+
+ ALRF
+ Alarm flag
+ 8
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ TSOVF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TAMP1F
+ RTC_INBREAK1 detection flag
+ 13
+ 1
+ read-write
+
+
+ TAMP2F
+ RTC_INBREAK2 detection flag
+ 14
+ 1
+ read-write
+
+
+ CALBSY
+ Calibration busy
+ 16
+ 1
+ read-only
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ PDIV1
+ first pre-divider factor
+ 16
+ 7
+
+
+ PDIV2
+ second pre-divider factor
+ 0
+ 15
+
+
+
+
+ ACFG1
+ ACFG1
+ alarm config1 register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDBYP
+ week/date bypass
+ 31
+ 1
+
+
+ WDSEL
+ week/date selection
+ 30
+ 1
+
+
+ DTEN
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DUNT
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ HORBYP
+ hours bypass
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MINBYP
+ minutes bypass
+ 15
+ 1
+
+
+ MINTEN
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ SECBYP
+ seconds bypass
+ 7
+ 1
+
+
+ SECTEN
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ CCODE
+ CCODE
+ control code register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code
+ 0
+ 8
+
+
+
+
+ SSEC
+ SSEC
+ subsecond register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSEC
+ subsecond
+ 0
+ 16
+
+
+
+
+ ADJ
+ ADJ
+ adjustment register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ INC1S
+ increase one second
+ 31
+ 1
+
+
+ SSEC_ADJ
+ subsecond adjustment
+ 0
+ 15
+
+
+
+
+ TR2
+ TR2
+ recording2 register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HORTEN
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HORUNT
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MINTEN
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MINUNT
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ SECTEN
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SECUNT
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ TR1
+ TR1
+ recording1 register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WEEKUNT
+ Week units
+ 13
+ 3
+
+
+ MTEN
+ Month tens in BCD format
+ 12
+ 1
+
+
+ MUNT
+ Month units in BCD format
+ 8
+ 4
+
+
+ DTEN
+ Date tens in BCD format
+ 4
+ 2
+
+
+ DUNT
+ Date units in BCD format
+ 0
+ 4
+
+
+
+
+ TR3
+ TR3
+ recording3 register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSEC
+ Subsecond
+ 0
+ 16
+
+
+
+
+ 1SCAL
+ 1SCAL
+ 1Hz clock calibration register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ INSCLK
+ Insert RTC clock
+ 15
+ 1
+
+
+ WIN8S
+ 8-second calibration window
+ 14
+ 1
+
+
+ WIN16S
+ 16-second calibration window
+ 13
+ 1
+
+
+ SWACLK
+ swallow RTC clock
+ 0
+ 9
+
+
+
+
+ MF
+ MF
+ multiplex function register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PC15CFG
+ PC15 config
+ 23
+ 1
+
+
+ PC15DATA
+ PC15 output data
+ 22
+ 1
+
+
+ PC14CFG
+ PC14 config
+ 21
+ 1
+
+
+ PC14DATA
+ PC14 output data
+ 20
+ 1
+
+
+ PC13CFG
+ PC13 config
+ 19
+ 1
+
+
+ PC13DATA
+ RTC_ALARM output type/PC13 output
+ data
+ 18
+ 1
+
+
+ INBRKPUDIS
+ RTC_INBREAKx pull-up disable
+ 15
+ 1
+
+
+ INBRKPRCH
+ RTC_INBREAKx precharge duration
+ 13
+ 2
+
+
+ INBRKFLT
+ RTC_INBREAKx filter count
+ 11
+ 2
+
+
+ INBRKFREQ
+ Inbreak sampling frequency
+ 8
+ 3
+
+
+ INBRKTR
+ Activate timestamp on inbreak detection
+ event
+ 7
+ 1
+
+
+ INBRK2TRG
+ Active level for RTC_INBREAK2
+ input
+ 4
+ 1
+
+
+ INBRK2E
+ RTC_INBREAK2 input detection
+ enable
+ 3
+ 1
+
+
+ INBRKIE
+ Inbreak interrupt enable
+ 2
+ 1
+
+
+ INBRK1TRG
+ Active level for RTC_INBREAK1
+ input
+ 1
+ 1
+
+
+ INBRK1E
+ Active level for RTC_INBREAK1
+ input
+ 0
+ 1
+
+
+
+
+ ACFG2
+ ACFG2
+ alarm config2 register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SSECBYP
+ Subsecond bypass
+ 24
+ 4
+
+
+ SSEC
+ Subsecond
+ 0
+ 15
+
+
+
+
+ AO0
+ AO0
+ always on registers 0
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO1
+ AO1
+ RTC always on registers 1
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO2
+ AO2
+ RTC always on registers 2
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO3
+ AO3
+ RTC always on registers 3
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+ AO4
+ AO4
+ RTC always on registers 4
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ AO
+ AO
+ 0
+ 32
+
+
+
+
+
+
+ TIM15
+ General-purpose-timers
+ TIM
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM15
+ TIM15 global interrupt
+ 20
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of channel
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger
+ DMA request
+ 14
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1
+ DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event
+ interrupt
+ 5
+ 1
+
+
+ CH1INTEN
+ Enable bit for channel 1
+ interrupt
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channel communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH1CCG
+ Channel 1 capture compare event
+ generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration register
+ (output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM16
+ 0x40014400
+
+ TIM16
+ TIM16 global interrupt
+ 21
+
+
+
+ TIM17
+ 0x40014800
+
+ TIM17
+ TIM17 global interrupt
+ 22
+
+
+
+ TIM6
+ General-purpose-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt
+ 17
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+
+
+ FMC
+ FLASH Memory Control
+ FMC
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 3
+
+
+
+ WCR
+ WCR
+ Flash access control register
+ 0x0
+ 0x20
+ 0x00000030
+
+
+ WCNT
+ FMC wait conuter
+ 0
+ 3
+ read-write
+
+
+ WE
+ FMC wait enable
+ 4
+ 1
+ read-write
+
+
+ WS
+ FMC wait status
+ 5
+ 1
+ read-only
+
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code
+ 0
+ 32
+
+
+
+
+ OBCCODE
+ OBCCODE
+ Option Byte Control code register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OBCCODE
+ Option Byte Control code
+ 0
+ 32
+
+
+
+
+ STS
+ STS
+ status register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ ENDF
+ End of operation
+ 5
+ 1
+ read-write
+
+
+ WPERR
+ Erase/Program protection error
+ 4
+ 1
+ read-write
+
+
+ PGERR
+ Program error
+ 2
+ 1
+ read-write
+
+
+ BUSY
+ Busy
+ 0
+ 1
+ read-only
+
+
+
+
+ CTR
+ CTR
+ FMC control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ OBUPDATE
+ Update option byte
+ 13
+ 1
+
+
+ ENDIE
+ End of operation interrupt
+ enable
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ OBWEN
+ Option byte erase/program enable
+ 9
+ 1
+
+
+ LOCK
+ LOCK
+ 7
+ 1
+
+
+ START
+ Start of erase
+ 6
+ 1
+
+
+ OBERS
+ Option byte erase command
+ 5
+ 1
+
+
+ OBPG
+ Option byte programm command
+ 4
+ 1
+
+
+ CHIPERS
+ Main flash CHIP ERASE
+ 2
+ 1
+
+
+ PERS
+ Flash page erase
+ 1
+ 1
+
+
+ PG
+ Main flash program
+ 0
+ 1
+
+
+
+
+ ERSADR
+ ERSADR
+ Flash erase address register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ERSADR
+ Flash erase address
+ 0
+ 32
+
+
+
+
+ OBSTS
+ OBSTS
+ Option byte status register
+ 0x1C
+ 0x20
+ read-only
+ 0x03FFFFF2
+
+
+ DATA1
+ DATA1
+ 24
+ 8
+
+
+ DATA0
+ DATA0
+ 16
+ 8
+
+
+ VDDA_DET
+ VDDA_DET
+ 13
+ 1
+
+
+ nBOOT1
+ nBOOT1
+ 12
+ 1
+
+
+ nRST_PWD
+ nRST_PWD
+ 10
+ 1
+
+
+ nRST_DSM
+ nRST_DSM
+ 9
+ 1
+
+
+ FWDT_AO
+ FWDT_AO
+ 8
+ 1
+
+
+ RPROT
+ RPROT
+ 1
+ 2
+
+
+ OBERR
+ Option byte error
+ 0
+ 1
+
+
+
+
+ WPSTS
+ WPSTS
+ Write protection status register
+ 0x20
+ 0x20
+ read-only
+ 0xFFFFFFFF
+
+
+ WPROT0
+ Write protect byte 0
+ 0
+ 8
+
+
+ WPROT1
+ Write protect byte 1
+ 8
+ 8
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBG
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ID
+ ID
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision identifier
+ 16
+ 16
+
+
+
+
+ LPWCFG
+ LPWCFG
+ Debug support for low power
+ configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DSM_DBGEN
+ Debug Deep Sleep Mode
+ 1
+ 1
+
+
+ PWD_DBGEN
+ Debug Down Power Mode
+ 2
+ 1
+
+
+
+
+ APB1CFG
+ APB1CFG
+ Debug support for apb1 peripherals
+ configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM2_DBG_PAUSE
+ TIM2 counter paused when system is
+ in debug mode
+ 0
+ 1
+
+
+ TIM3_DBG_PAUSE
+ TIM3 counter paused when system is
+ in debug mode
+ 1
+ 1
+
+
+ TIM6_DBG_PAUSE
+ TIM6 counter paused when system
+ is in debug mode
+ 4
+ 1
+
+
+ TIM14_DBG_PAUSE
+ TIM14 counter when system is in
+ debug mode
+ 8
+ 1
+
+
+ RTC_DBG_PAUSE
+ RTC paused when system is in
+ debug mode
+ 10
+ 1
+
+
+ WWDT_DBG_PAUSE
+ window watchdog paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ FWDT_DBG_PAUSE
+ Free watchdog paused when system
+ is in debug mode
+ 12
+ 1
+
+
+ I2C1_SMBUS_DBG_PAUSE
+ SMBUS timeout counter paused when
+ system is in debug mode
+ 21
+ 1
+
+
+
+
+ APB2CFG
+ APB2CFG
+ Debug support for apb2 peripherals
+ configuration register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM1_DBG_PAUSE
+ TIM1 counter paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ TIM15_DBG_PAUSE
+ TIM15 counter paused when system
+ is in debug mode
+ 16
+ 1
+
+
+ TIM16_DBG_PAUSE
+ TIM16 counter paused when system is
+ in debug mode
+ 17
+ 1
+
+
+ TIM17_DBG_PAUSE
+ TIM17 counter paused when system is
+ in debug mode
+ 18
+ 1
+
+
+
+
+
+
+
diff --git a/data/Chipsea/CS32F036x.svd b/data/Chipsea/CS32F036x.svd
new file mode 100644
index 0000000..21c036a
--- /dev/null
+++ b/data/Chipsea/CS32F036x.svd
@@ -0,0 +1,13017 @@
+
+
+ CS32F036x
+ 1.0
+ CS32F036x
+
+
+ 8
+
+ 32
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ CRC
+ cyclic redundancy check calculation
+ unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DATA
+ Data register bits
+ 0
+ 32
+
+
+
+
+ FREDATA
+ FREDATA
+ free data register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FREDATA
+ Free Data register
+ bits
+ 0
+ 8
+
+
+
+
+ CTR
+ CTR
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RST
+ reset bit
+ 0
+ 1
+
+
+ DINREVMOD
+ Input data Reverse mode selection
+ 5
+ 2
+
+
+ DOREVEN
+ Output data Reverse enable
+ 7
+ 1
+
+
+
+
+ INITCFG
+ INITCFG
+ CRC initial value configuration register
+ 0xC
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ INITCFG
+ CRC initial value configuration bits
+ 0
+ 32
+
+
+
+
+
+
+ GPIOF
+ General-purpose I/Os
+ GPIO
+ 0x48001400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ GPIOD
+ 0x48000C00
+
+
+ GPIOC
+ 0x48000800
+
+
+ GPIOB
+ 0x48000400
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ PFR
+ PFR
+ GPIO port function register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ FUNC15
+ Port i function (j = 0..15)
+ 30
+ 2
+
+
+ FUNC14
+ Port i function (j = 0..15)
+ 28
+ 2
+
+
+ FUNC13
+ Port i function (j = 0..15)
+ 26
+ 2
+
+
+ FUNC12
+ Port i function (j = 0..15)
+ 24
+ 2
+
+
+ FUNC11
+ Port i function (j = 0..15)
+ 22
+ 2
+
+
+ FUNC10
+ Port i function (j = 0..15)
+ 20
+ 2
+
+
+ FUNC9
+ Port i function (j = 0..15)
+ 18
+ 2
+
+
+ FUNC8
+ Port i function (j = 0..15)
+ 16
+ 2
+
+
+ FUNC7
+ Port i function (j = 0..15)
+ 14
+ 2
+
+
+ FUNC6
+ Port i function (j = 0..15)
+ 12
+ 2
+
+
+ FUNC5
+ Port i function (j = 0..15)
+ 10
+ 2
+
+
+ FUNC4
+ Port i function (j = 0..15)
+ 8
+ 2
+
+
+ FUNC3
+ Port i function (j = 0..15)
+ 6
+ 2
+
+
+ FUNC2
+ Port i function (j = 0..15)
+ 4
+ 2
+
+
+ FUNC1
+ Port i function (j = 0..15)
+ 2
+ 2
+
+
+ FUNC0
+ Port i function (j = 0..15)
+ 0
+ 2
+
+
+
+
+ PODENR
+ PODENR
+ GPIO port output open-drain enable
+ register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ODEN15
+ Port i output open-drain enable
+ 15
+ 15
+ 1
+
+
+ ODEN14
+ Port i output open-drain enable
+ 14
+ 14
+ 1
+
+
+ ODEN13
+ Port i output open-drain enable
+ 13
+ 13
+ 1
+
+
+ ODEN12
+ Port i output open-drain enable
+ 12
+ 12
+ 1
+
+
+ ODEN11
+ Port i output open-drain enable
+ 11
+ 11
+ 1
+
+
+ ODEN10
+ Port i output open-drain enable
+ 10
+ 10
+ 1
+
+
+ ODEN9
+ Port i output open-drain enable
+ 9
+ 9
+ 1
+
+
+ ODEN8
+ Port i output open-drain enable
+ 8
+ 8
+ 1
+
+
+ ODEN7
+ Port i output open-drain enable
+ 7
+ 7
+ 1
+
+
+ ODEN6
+ Port i output open-drain enable
+ 6
+ 6
+ 1
+
+
+ ODEN5
+ Port i output open-drain enable
+ 5
+ 5
+ 1
+
+
+ ODEN4
+ Port i output open-drain enable
+ 4
+ 4
+ 1
+
+
+ ODEN3
+ Port i output open-drain enable
+ 3
+ 3
+ 1
+
+
+ ODEN2
+ Port i output open-drain enable
+ 2
+ 2
+ 1
+
+
+ ODEN1
+ Port i output open-drain enable
+ 1
+ 1
+ 1
+
+
+ ODEN0
+ Port i output open-drain enable
+ 0
+ 0
+ 1
+
+
+
+
+ POSR
+ POSR
+ GPIO port output speed
+ register
+ 0x8
+ 0x20
+ read-write
+ 0x0C000000
+
+
+ OS15
+ Port i output speed (i=
+ 0..15)
+ 30
+ 2
+
+
+ OS14
+ Port i output speed (i=
+ 0..15)
+ 28
+ 2
+
+
+ OS13
+ Port i output speed (i=
+ 0..15)
+ 26
+ 2
+
+
+ OS12
+ Port i output speed (i=
+ 0..15)
+ 24
+ 2
+
+
+ OS11
+ Port i output speed (i=
+ 0..15)
+ 22
+ 2
+
+
+ OS10
+ Port i output speed (i=
+ 0..15)
+ 20
+ 2
+
+
+ OS9
+ Port i output speed (i=
+ 0..15)
+ 18
+ 2
+
+
+ OS8
+ Port i output speed (i=
+ 0..15)
+ 16
+ 2
+
+
+ OS7
+ Port i output speed (i=
+ 0..15)
+ 14
+ 2
+
+
+ OS6
+ Port i output speed (i=
+ 0..15)
+ 12
+ 2
+
+
+ OS5
+ Port i output speed (i=
+ 0..15)
+ 10
+ 2
+
+
+ OS4
+ Port i output speed (i=
+ 0..15)
+ 8
+ 2
+
+
+ OS3
+ Port i output speed (i=
+ 0..15)
+ 6
+ 2
+
+
+ OS2
+ Port i output speed (i=
+ 0..15)
+ 4
+ 2
+
+
+ OS1
+ Port i output speed (i=
+ 0..15)
+ 2
+ 2
+
+
+ OS0
+ Port i output speed (i=
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUPDR
+ PUPDR
+ GPIO port pull-up/pull-down
+ register
+ 0xC
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUPDR15
+ Port i configuration bits (i =
+ 0..15)
+ 30
+ 2
+
+
+ PUPDR14
+ Port i configuration bits (i =
+ 0..15)
+ 28
+ 2
+
+
+ PUPDR13
+ Port i configuration bits (i =
+ 0..15)
+ 26
+ 2
+
+
+ PUPDR12
+ Port i configuration bits (i =
+ 0..15)
+ 24
+ 2
+
+
+ PUPDR11
+ Port i configuration bits (i =
+ 0..15)
+ 22
+ 2
+
+
+ PUPDR10
+ Port i configuration bits (i =
+ 0..15)
+ 20
+ 2
+
+
+ PUPDR9
+ Port i configuration bits (i =
+ 0..15)
+ 18
+ 2
+
+
+ PUPDR8
+ Port i configuration bits (i =
+ 0..15)
+ 16
+ 2
+
+
+ PUPDR7
+ Port i configuration bits (i =
+ 0..15)
+ 14
+ 2
+
+
+ PUPDR6
+ Port i configuration bits (i =
+ 0..15)
+ 12
+ 2
+
+
+ PUPDR5
+ Port i configuration bits (i =
+ 0..15)
+ 10
+ 2
+
+
+ PUPDR4
+ Port i configuration bits (i =
+ 0..15)
+ 8
+ 2
+
+
+ PUPDR3
+ Port i configuration bits (i =
+ 0..15)
+ 6
+ 2
+
+
+ PUPDR2
+ Port i configuration bits (i =
+ 0..15)
+ 4
+ 2
+
+
+ PUPDR1
+ Port i configuration bits (i =
+ 0..15)
+ 2
+ 2
+
+
+ PUPDR0
+ Port i configuration bits (i =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ DI
+ DI
+ GPIO port data input register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DI15
+ Port i data input j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DI14
+ Port i data input j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DI13
+ Port i data input j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DI12
+ Port i data input j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DI11
+ Port i data input j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DI10
+ Port i data input j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DI9
+ Port i data input j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DI8
+ Port i data input j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DI7
+ Port i data input j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DI6
+ Port i data input j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DI5
+ Port i data input j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DI4
+ Port i data input j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DI3
+ Port i data input j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DI2
+ Port i data input j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DI1
+ Port i data input j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DI0
+ Port i data input j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ DO
+ DO
+ GPIO port data output register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DO15
+ Port i data output j (j =
+ 0..15)
+ 15
+ 1
+
+
+ DO14
+ Port i data output j (j =
+ 0..15)
+ 14
+ 1
+
+
+ DO13
+ Port i data output j (j =
+ 0..15)
+ 13
+ 1
+
+
+ DO12
+ Port i data output j (j =
+ 0..15)
+ 12
+ 1
+
+
+ DO11
+ Port i data output j (j =
+ 0..15)
+ 11
+ 1
+
+
+ DO10
+ Port i data output j (j =
+ 0..15)
+ 10
+ 1
+
+
+ DO9
+ Port i data output j (j =
+ 0..15)
+ 9
+ 1
+
+
+ DO8
+ Port i data output j (j =
+ 0..15)
+ 8
+ 1
+
+
+ DO7
+ Port i data output j (j =
+ 0..15)
+ 7
+ 1
+
+
+ DO6
+ Port i data output j (j =
+ 0..15)
+ 6
+ 1
+
+
+ DO5
+ Port i data output j (j =
+ 0..15)
+ 5
+ 1
+
+
+ DO4
+ Port i data output j (j =
+ 0..15)
+ 4
+ 1
+
+
+ DO3
+ Port i data output j (j =
+ 0..15)
+ 3
+ 1
+
+
+ DO2
+ Port i data output j (j =
+ 0..15)
+ 2
+ 1
+
+
+ DO1
+ Port i data output j (j =
+ 0..15)
+ 1
+ 1
+
+
+ DO0
+ Port i data output j (j =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ SCR
+ SCR
+ GPIO port set/clear register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BC15
+ Port i bit clear j (i =
+ 0..15)
+ 31
+ 1
+
+
+ BC14
+ Port i bit clear j (i =
+ 0..15)
+ 30
+ 1
+
+
+ BC13
+ Port i bit clear j (i =
+ 0..15)
+ 29
+ 1
+
+
+ BC12
+ Port i bit clear j (i =
+ 0..15)
+ 28
+ 1
+
+
+ BC11
+ Port i bit clear j (i =
+ 0..15)
+ 27
+ 1
+
+
+ BC10
+ Port i bit clear j (i =
+ 0..15)
+ 26
+ 1
+
+
+ BC9
+ Port i bit clear j (i =
+ 0..15)
+ 25
+ 1
+
+
+ BC8
+ Port i bit clear j (i =
+ 0..15)
+ 24
+ 1
+
+
+ BC7
+ Port i bit clear j (i =
+ 0..15)
+ 23
+ 1
+
+
+ BC6
+ Port i bit clear j (i =
+ 0..15)
+ 22
+ 1
+
+
+ BC5
+ Port i bit clear j (i =
+ 0..15)
+ 21
+ 1
+
+
+ BC4
+ Port i bit clear j (i =
+ 0..15)
+ 20
+ 1
+
+
+ BC3
+ Port i bit clear j (i =
+ 0..15)
+ 19
+ 1
+
+
+ BC2
+ Port i bit clear j (i =
+ 0..15)
+ 18
+ 1
+
+
+ BC1
+ Port i bit clear j (i =
+ 0..15)
+ 17
+ 1
+
+
+ BC0
+ Port i bit clear j (i =
+ 0..15)
+ 16
+ 1
+
+
+ BS15
+ Port i bit set j (i =
+ 0..15)
+ 15
+ 1
+
+
+ BS14
+ Port i bit set j (i =
+ 0..15)
+ 14
+ 1
+
+
+ BS13
+ Port i bit set j (i =
+ 0..15)
+ 13
+ 1
+
+
+ BS12
+ Port i bit set j (i =
+ 0..15)
+ 12
+ 1
+
+
+ BS11
+ Port i bit set j (i =
+ 0..15)
+ 11
+ 1
+
+
+ BS10
+ Port i bit set j (i =
+ 0..15)
+ 10
+ 1
+
+
+ BS9
+ Port i bit set j (i =
+ 0..15)
+ 9
+ 1
+
+
+ BS8
+ Port i bit set j (i =
+ 0..15)
+ 8
+ 1
+
+
+ BS7
+ Port i bit set j (i =
+ 0..15)
+ 7
+ 1
+
+
+ BS6
+ Port i bit set j (i =
+ 0..15)
+ 6
+ 1
+
+
+ BS5
+ Port i bit set j (i =
+ 0..15)
+ 5
+ 1
+
+
+ BS4
+ Port i bit set j (i =
+ 0..15)
+ 4
+ 1
+
+
+ BS3
+ Port i bit set j (i =
+ 0..15)
+ 3
+ 1
+
+
+ BS2
+ Port i bit set j (i =
+ 0..15)
+ 2
+ 1
+
+
+ BS1
+ Port i bit set j (i =
+ 0..15)
+ 1
+ 1
+
+
+ BS0
+ Port i bit set j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port lock register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LOCKK
+ Lock sequence key
+ 16
+ 1
+
+
+ LOCK15
+ Port i lock j (i =
+ 0..15)
+ 15
+ 1
+
+
+ LOCK14
+ Port i lock j (i =
+ 0..15)
+ 14
+ 1
+
+
+ LOCK13
+ Port i lock j (i =
+ 0..15)
+ 13
+ 1
+
+
+ LOCK12
+ Port i lock j (i =
+ 0..15)
+ 12
+ 1
+
+
+ LOCK11
+ Port i lock j (i =
+ 0..15)
+ 11
+ 1
+
+
+ LOCK10
+ Port i lock j (i =
+ 0..15)
+ 10
+ 1
+
+
+ LOCK9
+ Port i lock j (i =
+ 0..15)
+ 9
+ 1
+
+
+ LOCK8
+ Port i lock j (i =
+ 0..15)
+ 8
+ 1
+
+
+ LOCK7
+ Port i lock j (i =
+ 0..15)
+ 7
+ 1
+
+
+ LOCK6
+ Port i lock j (i =
+ 0..15)
+ 6
+ 1
+
+
+ LOCK5
+ Port i lock j (i =
+ 0..15)
+ 5
+ 1
+
+
+ LOCK4
+ Port i lock j (i =
+ 0..15)
+ 4
+ 1
+
+
+ LOCK3
+ Port i lock j (i =
+ 0..15)
+ 3
+ 1
+
+
+ LOCK2
+ Port i lock j (i =
+ 0..15)
+ 2
+ 1
+
+
+ LOCK1
+ Port i lock j (i =
+ 0..15)
+ 1
+ 1
+
+
+ LOCK0
+ Port i lock j (i =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ MFSELL
+ MFSELL
+ GPIO multi-function selection low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELL7
+ Port i multi-function selection j
+ (i = 0..7)
+ 28
+ 4
+
+
+ MFSELL6
+ Port i multi-function selection j
+ (i = 0..7)
+ 24
+ 4
+
+
+ MFSELL5
+ Port i multi-function selection j
+ (i = 0..7)
+ 20
+ 4
+
+
+ MFSELL4
+ Port i multi-function selection j
+ (i = 0..7)
+ 16
+ 4
+
+
+ MFSELL3
+ Port i multi-function selection j
+ (i = 0..7)
+ 12
+ 4
+
+
+ MFSELL2
+ Port i multi-function selection j
+ (i = 0..7)
+ 8
+ 4
+
+
+ MFSELL1
+ Port i multi-function selection j
+ (i = 0..7)
+ 4
+ 4
+
+
+ MFSELL0
+ Port i multi-function selection j
+ (i = 0..7)
+ 0
+ 4
+
+
+
+
+ MFSELH
+ MFSELH
+ GPIO multi-function selection high
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MFSELH15
+ Port i multi-function selection j
+ (i = 8..15)
+ 28
+ 4
+
+
+ MFSELH14
+ Port i multi-function selection j
+ (i = 8..15)
+ 24
+ 4
+
+
+ MFSELH13
+ Port i multi-function selection j
+ (i = 8..15)
+ 20
+ 4
+
+
+ MFSELH12
+ Port i multi-function selection j
+ (i = 8..15)
+ 16
+ 4
+
+
+ MFSELH11
+ Port i multi-function selection j
+ (i = 8..15)
+ 12
+ 4
+
+
+ MFSELH10
+ Port i multi-function selection j
+ (i = 8..15)
+ 8
+ 4
+
+
+ MFSELH9
+ Port i multi-function selection j
+ (i = 8..15)
+ 4
+ 4
+
+
+ MFSELH8
+ Port i multi-function selection j
+ (i = 8..15)
+ 0
+ 4
+
+
+
+
+ CLRR
+ CLRR
+ GPIO port clear register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ BCLR0
+ Port i bit clear j
+ 0
+ 1
+
+
+ BCLR1
+ Port i bit clear j
+ 1
+ 1
+
+
+ BCLR2
+ Port i bit clear j
+ 2
+ 1
+
+
+ BCLR3
+ Port i bit clear j
+ 3
+ 1
+
+
+ BCLR4
+ Port i bit clear j
+ 4
+ 1
+
+
+ BCLR5
+ Port i bit clear j
+ 5
+ 1
+
+
+ BCLR6
+ Port i bit clear j
+ 6
+ 1
+
+
+ BCLR7
+ Port i bit clear j
+ 7
+ 1
+
+
+ BCLR8
+ Port i bit clear j
+ 8
+ 1
+
+
+ BCLR9
+ Port i bit clear j
+ 9
+ 1
+
+
+ BCLR10
+ Port i bit clear j
+ 10
+ 1
+
+
+ BCLR11
+ Port i bit clear j
+ 11
+ 1
+
+
+ BCLR12
+ Port i bit clear j
+ 12
+ 1
+
+
+ BCLR13
+ Port i bit clear j
+ 13
+ 1
+
+
+ BCLR14
+ Port i bit clear j
+ 14
+ 1
+
+
+ BCLR15
+ Port i bit clear j
+ 15
+ 1
+
+
+
+
+
+
+ SPI1
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ SPI1_global_interrupt
+ 25
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SBMODE
+ Single-wire bidirectional mode
+ 15
+ 1
+
+
+ SBOEN
+ Single-wire bidirectional output
+ enable
+ 14
+ 1
+
+
+ CRCEN
+ CRC calculation enable
+ 13
+ 1
+
+
+ NXTCRC
+ Next CRC transfer
+ 12
+ 1
+
+
+ CRC16
+ 16-bit CRC enable
+ 11
+ 1
+
+
+ ROM
+ Receive only mode
+ 10
+ 1
+
+
+ SWNSSM
+ software NSS mode
+ 9
+ 1
+
+
+ NVSWNSSM
+ NSS value in software NSS mode
+ 8
+ 1
+
+
+ LSBF
+ LSB first
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ CRSEL
+ Communication rate selection
+ 3
+ 3
+
+
+ SPIM
+ SPI mode
+ 2
+ 1
+
+
+ CPOL
+ Clock polarity
+ 1
+ 1
+
+
+ CPHA
+ Clock phase
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0700
+
+
+ DMARXEN
+ DMA enable for receive
+ 0
+ 1
+
+
+ DMATXEN
+ DMA enable for transmit
+ 1
+ 1
+
+
+ NSSOEN
+ NSS output enable
+ 2
+ 1
+
+
+ NSSPM
+ NSS pulse mode
+ 3
+ 1
+
+
+ TIEN
+ SPI TI mode enable
+ 4
+ 1
+
+
+ ERRINTEN
+ Enable bit for error interrupt
+ 5
+ 1
+
+
+ RXNEINTEN
+ Enable bit for receive Buffer Not
+ Empty Interrupt
+ 6
+ 1
+
+
+ TXEINTEN
+ Enable bit for transmit Buffer
+ Empty Interrupt
+ 7
+ 1
+
+
+ DLEN
+ Data length
+ 8
+ 4
+
+
+ RXNE8
+ RXNE generate condition selection
+ 12
+ 1
+
+
+ DMARXODD
+ Number of data to receive
+ with DMA is odd
+ 13
+ 1
+
+
+ DMATXODD
+ Number of data to transmit
+ with DMA is odd
+ 14
+ 1
+
+
+
+
+ STS
+ STS
+ SPI status
+ 0x8
+ 0x20
+ 0x0002
+
+
+ RXNE
+ Receive buffer not empty
+ 0
+ 1
+ read-only
+
+
+ TXE
+ Transmit buffer empty
+ 1
+ 1
+ read-only
+
+
+ I2SCSF
+ I2S Channel side flag
+ 2
+ 1
+ read-only
+
+
+ TXUFERR
+ Transmitter data underflow error
+ 3
+ 1
+ read-only
+
+
+ CRCERR
+ CRC error
+ 4
+ 1
+ read-write
+
+
+ MMERR
+ Multi-master error
+ 5
+ 1
+ read-only
+
+
+ RXOFERR
+ Receiver data overflow error
+ 6
+ 1
+ read-only
+
+
+ BUSY
+ Busy
+ 7
+ 1
+ read-only
+
+
+ NWERR
+ Error of SPI NSS or I2S WS
+ 8
+ 1
+ read-only
+
+
+ RXFIFOS
+ Receive FIFO status
+ 9
+ 2
+ read-only
+
+
+ TXFIFOS
+ Transmit FIFO status
+ 11
+ 2
+ read-only
+
+
+
+
+ DATA
+ DATA
+ Transfer data register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Transfer data register
+ 0
+ 16
+
+
+
+
+ CRCPOLYR
+ CRCPOLYR
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLYR
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ Rx CRC register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2S_CTR
+ I2S_CTR
+ I2S control register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SMS
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOM
+ I2S operation mode
+ 8
+ 2
+
+
+ PCMLONG
+ PCM long frame synchronization
+ 7
+ 1
+
+
+ I2SSTDS
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPIS
+ clock polarity of Inactive state
+ 3
+ 1
+
+
+ I2SDL
+ I2S data length
+ 1
+ 2
+
+
+ I2SCL
+ I2S Channel length
+ 0
+ 1
+
+
+
+
+ I2S_PDIV
+ I2S_PDIV
+ I2S pre-divider register
+ 0x20
+ 0x20
+ read-write
+ 0x00000010
+
+
+ MCKOEN
+ MCK output enable
+ 9
+ 1
+
+
+ PDIVPS
+ Parity selection of pre-divider
+ 8
+ 1
+
+
+ I2SPDIV
+ I2S pre-divider
+ 0
+ 8
+
+
+
+
+
+
+ SPI2
+ 0x40003800
+
+ SPI2
+ SPI2 global interrupt
+ 26
+
+
+
+ PMU
+ Power management unit
+ PMU
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTR
+ CTR
+ control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBTWEN
+ VBAT domain write enable
+ 8
+ 1
+
+
+ LVDSEL
+ low vlotage detector
+ threshold Selection
+ 5
+ 3
+
+
+ LVDEN
+ low vlotage detector Enable
+ 4
+ 1
+
+
+ CLRPWDF
+ Clear power down flag
+ 3
+ 1
+
+
+ CLRWUPF
+ Clear wakup flag
+ 2
+ 1
+
+
+ DSMODE
+ Deepsleep Mode or
+ Power down selection
+ 1
+ 1
+
+
+ LDOLM
+ LDO low power Control
+ 0
+ 1
+
+
+
+
+ CS
+ CS
+ control/status register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ WUPEN2
+ WKUP pin2 Enable
+ 9
+ 1
+ read-write
+
+
+ WUPEN1
+ WKUP pin1 Enable
+ 8
+ 1
+ read-write
+
+
+ VREFRDY
+ VREFINT reference voltage ready
+ 3
+ 1
+ read-only
+
+
+ LVDO
+ low vlotage detector Output
+ 2
+ 1
+ read-only
+
+
+ PWDF
+ power down flag
+ 1
+ 1
+ read-only
+
+
+ WUPF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+
+
+
+
+ I2C1
+ Inter-integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C1
+ I2C1 global interrupt
+ 23
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ 0x00000000
+
+
+ I2CEN
+ I2C enable
+ 0
+ 1
+ read-write
+
+
+ TXISIE
+ Enable bit for TX interrupt
+ 1
+ 1
+ read-write
+
+
+ RXNEIE
+ Enable bit for RX interrupt
+ 2
+ 1
+ read-write
+
+
+ ADRMIE
+ Enable bit for Address match
+ interrupt
+ 3
+ 1
+ read-write
+
+
+ NACKRIE
+ Enable bit for Not acknowledge
+ received interrupt
+ 4
+ 1
+ read-write
+
+
+ STOPDIE
+ Enable bit for STOP detection
+ interrupt
+ 5
+ 1
+ read-write
+
+
+ CMPIE
+ Enable bit for Transfer complete
+ interrupt
+ 6
+ 1
+ read-write
+
+
+ ERRDIE
+ Enable bit for Error detection
+ interrupt
+ 7
+ 1
+ read-write
+
+
+ DFCFG
+ Digital filter configuration
+ 8
+ 4
+ read-write
+
+
+ AFDIS
+ Analog filter Disable
+ 12
+ 1
+ read-write
+
+
+ SWRST
+ Software reset
+ 13
+ 1
+ write-only
+
+
+ TXDMAREQEN
+ Enable bit for Transmission
+ DMA requests
+ 14
+ 1
+ read-write
+
+
+ RXDMAREQEN
+ Enable bit for Reception
+ DMA requests
+ 15
+ 1
+ read-write
+
+
+ SLVRC
+ Slave response control
+ 16
+ 1
+ read-write
+
+
+ DISSTRETCH
+ Disable clock stretching
+ 17
+ 1
+ read-write
+
+
+ WKUPEN
+ Enable bit for Stop mode Wakeup
+ 18
+ 1
+ read-write
+
+
+ GCEN
+ Enable bit for General call
+ 19
+ 1
+ read-write
+
+
+ SMBHAEN
+ Enable bit for SMBus Host address
+ 20
+ 1
+ read-write
+
+
+ SMBDDAEN
+ Enable bit for SMBus Device
+ Default address
+ 21
+ 1
+ read-write
+
+
+ SMBAEN
+ SMBUS alert enable
+ 22
+ 1
+ read-write
+
+
+ PECMEN
+ PEC mode enable
+ 23
+ 1
+ read-write
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PECCTR
+ PEC byte control
+ 26
+ 1
+
+
+ TENDSEL
+ Tranfer end mode selection
+ (master mode)
+ 25
+ 1
+
+
+ RELOADM
+ Bytes number reload mode
+ 24
+ 1
+
+
+ BNUM
+ Bytes number
+ 16
+ 8
+
+
+ NACKGEN
+ Generate a NACK on I2C bus
+ (slave mode)
+ 15
+ 1
+
+
+ STOPGEN
+ Generate a Stop on I2C bus
+ (master mode)
+ 14
+ 1
+
+
+ STARTGEN
+ Generate a Start on I2C bus
+ 13
+ 1
+
+
+ HEAD10AR
+ 10-bit address header only
+ read direction (master receiver mode)
+ 12
+ 1
+
+
+ ADRFMT
+ Addressing format (master mode)
+ 11
+ 1
+
+
+ TDIR
+ Direction of Transfer (master
+ mode)
+ 10
+ 1
+
+
+ MTADR8
+ Master transfer address
+ bit 9:8 on I2C bus
+ 8
+ 2
+
+
+ MTADR1
+ Master transfer address
+ bit 7:1 on I2C bus
+ 1
+ 7
+
+
+ MTADR0
+ Master transfer address
+ bit 0 on I2C bus
+ 0
+ 1
+
+
+
+
+ SADR1
+ SADR1
+ I2C slave address 1 register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR1_0
+ Slave Address 1
+ 0
+ 1
+
+
+ SADR1_1
+ Slave Address 1
+ 1
+ 7
+
+
+ SADR1_8
+ Slave Address 1
+ 8
+ 2
+
+
+ SADR1MODE
+ Slave Address 1 10-bit mode
+ 10
+ 1
+
+
+ SADR1EN
+ Slave Address 1 enable
+ 15
+ 1
+
+
+
+
+ SADR2
+ SADR2
+ I2C slave address 2 register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SADR2
+ Slave Address 2
+ 1
+ 7
+
+
+ SADR2MSK
+ Slave Address 2 masks
+ 8
+ 3
+
+
+ SADR2EN
+ Slave Address 2 enable
+ 15
+ 1
+
+
+
+
+ TMR
+ TMR
+ I2C timing register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SCLLT
+ Master mode SCL low time
+ 0
+ 8
+
+
+ SCLHT
+ Master mode SCL high time
+ 8
+ 8
+
+
+ SDAHT
+ SDA hold time
+ 16
+ 4
+
+
+ SDAST
+ SDA setup time
+ 20
+ 4
+
+
+ TPDIV
+ Timing pre-divider
+ 28
+ 4
+
+
+
+
+ OVRT
+ OVRT
+ I2C overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMA
+ Bus overtime A
+ 0
+ 12
+
+
+ IDLEDEN
+ Idle clock overtime
+ detection
+ 12
+ 1
+
+
+ TIMAEN
+ timer A enable
+ 15
+ 1
+
+
+ TIMB
+ Bus overtime B
+ 16
+ 12
+
+
+ TIMBEN
+ timer B enable
+ 31
+ 1
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x18
+ 0x20
+ 0x00000001
+
+
+ MSLVA
+ Matched Slave Address
+ 17
+ 7
+ read-only
+
+
+ DIRF
+ Slave Transfer direction
+ flag
+ 16
+ 1
+ read-only
+
+
+ BUSYF
+ Bus busy flag
+ 15
+ 1
+ read-only
+
+
+ SMBAF
+ SMBus alert flag
+ 13
+ 1
+ read-only
+
+
+ OVRTF
+ Overtime or tLOW detection
+ flag
+ 12
+ 1
+ read-only
+
+
+ PECERRF
+ PEC Error flag
+ 11
+ 1
+ read-only
+
+
+ OVRF
+ Slave Overflow/Underflow flag
+ 10
+ 1
+ read-only
+
+
+ ARBLOF
+ Arbitration lost flag
+ 9
+ 1
+ read-only
+
+
+ BUSERRF
+ Bus error flag
+ 8
+ 1
+ read-only
+
+
+ RLDF
+ Reload flag
+ 7
+ 1
+ read-only
+
+
+ CMPF
+ Master mode Transfer Complete
+ flag
+ 6
+ 1
+ read-only
+
+
+ STOPF
+ Stop detection flag
+ 5
+ 1
+ read-only
+
+
+ NACKF
+ NACK received flag
+ 4
+ 1
+ read-only
+
+
+ ADRF
+ Slave mode Address matched
+ flag
+ 3
+ 1
+ read-only
+
+
+ RXNEF
+ Data register not empty in
+ receiving mode
+ 2
+ 1
+ read-only
+
+
+ TXINTF
+ Transmit interrupt flag
+ 1
+ 1
+ read-write
+
+
+ TXEF
+ Data register empty flag in
+ transmitting mode
+ 0
+ 1
+ read-write
+
+
+
+
+ STSC
+ STSC
+ Status clear register
+ 0x1C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ SMBAFC
+ SMBus alert flag clear
+ 13
+ 1
+
+
+ OVRTFC
+ Overtime detection flag
+ clear
+ 12
+ 1
+
+
+ PECERRFC
+ PEC Error flag clear
+ 11
+ 1
+
+
+ OVRFC
+ Slave Overflow/Underflow
+ flag clear
+ 10
+ 1
+
+
+ ARLOFC
+ Arbitration Lost flag
+ clear
+ 9
+ 1
+
+
+ BUSERRFC
+ Bus error flag clear
+ 8
+ 1
+
+
+ STOPFC
+ Stop detection flag clear
+ 5
+ 1
+
+
+ NACKFC
+ NACK received flag clear
+ 4
+ 1
+
+
+ ADRFC
+ Slave mode Address matched
+ flag clear
+ 3
+ 1
+
+
+
+
+ PECCODE
+ PECCODE
+ I2C received PEC code register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PECCODE
+ Received PEC code
+ 0
+ 8
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RXBUF
+ Receive buffer register
+ 0
+ 8
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TXBUF
+ Transmit buffer register
+ 0
+ 8
+
+
+
+
+
+
+ I2C2
+ 0x40005800
+
+ I2C2
+ I2C2 global interrupt
+ 24
+
+
+
+ FWDT
+ Free Watchdog Timer
+ FWDT
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x0
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code(write only,
+ read 0x0000)
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ Pre-divider register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDIV
+ Pre-divider
+ 0
+ 3
+
+
+
+
+ UVAL
+ UVAL
+ Update register
+ 0x8
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ UVAL
+ Watchdog counter update
+ value
+ 0
+ 12
+
+
+
+
+ STS
+ STS
+ Status register
+ 0xC
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DRF
+ FWDT divider refresh flag
+ 0
+ 1
+
+
+ UVRF
+ FWDT update value refresh
+ flag
+ 1
+ 1
+
+
+ WRF
+ FWDT window refresh flag
+ 2
+ 1
+
+
+
+
+ WINVAL
+ WINVAL
+ Window value register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WINVAL
+ FWDT window value
+ 0
+ 12
+
+
+
+
+
+
+ WWDT
+ Window Watchdog Timer
+ WWDT
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDT
+ Window Watchdog Timer interrupt
+ 0
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WWDTEN
+ Window watchdog timer enable
+ 7
+ 1
+
+
+ CVAL
+ Counter Value
+ 0
+ 7
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ RMDIE
+ Reminder interrupt enable
+ 9
+ 1
+
+
+ PDIV
+ Pre-divider
+ 7
+ 2
+
+
+ WVAL
+ window value
+ 0
+ 7
+
+
+
+
+ STS
+ STS
+ Status register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RMDIF
+ Reminder interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+ TIM1
+ Advanced-timers
+ TIM
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM1_BRK_UP_TRG_COM
+ TIM1 Break, Update, Trigger and Commutation
+ 13
+
+
+ TIM1_CC
+ TIM1 Capture Compare interrupt
+ 14
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO4
+ Idle value output of
+ channel 4
+ 14
+ 1
+
+
+ IVO3N
+ Idle value output of channel
+ 3 complementary
+ 13
+ 1
+
+
+ IVO3
+ Idle value output of channel 3
+ 12
+ 1
+
+
+ IVO2N
+ Idle value output of channel 2
+ complementary
+ 11
+ 1
+
+
+ IVO2
+ Idle value output of channel 2
+ 10
+ 1
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of
+ channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of
+ channel
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event interrupt
+ 5
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channe l communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel 2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH4CCG
+ Channel 4 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 3 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 2 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ CH2ICPDIV
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ IC1PCS
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3NCCEN
+ Channel 3 complementary capture compare
+ enable
+ 10
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2NCCEN
+ Channel 2 complementary capture compare
+ enable
+ 6
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update repetition register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ Counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL
+ Channel 2 capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL
+ Channel 3 capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL
+ Channel 4 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ channel output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM3
+ General-purpose-timers
+ TIM
+ 0x40000400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM3
+ TIM3 global interrupt
+ 16
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ CPS
+ Count pattern selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI1XOR
+ XOR input for TI1
+ 7
+ 1
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETRINV
+ ETR invert
+ 15
+ 1
+
+
+ ECMODE2
+ External clock mode 2 enable
+ 14
+ 1
+
+
+ ETPDIV
+ External trigger pre-divide
+ 12
+ 2
+
+
+ ETFLT
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRIGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMCFG
+ Slave mode configuration
+ 0
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger DMA request
+ 14
+ 1
+
+
+ COMDEN
+ Enable bit for COM event DMA request
+ 13
+ 1
+
+
+ CH4DEN
+ Enable bit for channel 4 DMA request
+ 12
+ 1
+
+
+ CH3DEN
+ Enable bit for channel 3 DMA request
+ 11
+ 1
+
+
+ CH2DEN
+ Enable bit for channel 2 DMA request
+ 10
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1 DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update DMA request
+ 8
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ CH4INTEN
+ Channel 4 capture compare interrupt flag
+ 4
+ 1
+
+
+ CH3INTEN
+ Channel 3 capture compare interrupt flag
+ 3
+ 1
+
+
+ CH2INTEN
+ Channel2 capture compare interrupt flag
+ 2
+ 1
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4ICOF
+ Channel 4 input capture overflow
+ 12
+ 1
+
+
+ CH3ICOF
+ Channel 3 input capture overflow
+ 11
+ 1
+
+
+ CH2ICOF
+ Channel 2 input capture overflow
+ 10
+ 1
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CH4CCIF
+ Channel 4 capture compare interrupt
+ flag
+ 4
+ 1
+
+
+ CH3CCIF
+ Channel 3 capture compare interrupt
+ flag
+ 3
+ 1
+
+
+ CH2CCIF
+ Channel2 capture compare interrupt
+ flag
+ 2
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ CH4CCG
+ Channel 1 capture
+ compare event generation
+ 4
+ 1
+
+
+ CH3CCG
+ Channel 1 capture
+ compare event generation
+ 3
+ 1
+
+
+ CH2CCG
+ Channel 1 capture
+ compare event generation
+ 2
+ 1
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2OCCEN
+ Channel 2 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH2OCMSEL
+ Channel 2 output compare mode
+ selection
+ 12
+ 3
+
+
+ CH2OCVPEN
+ Channel 2 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH2OCFEN
+ Channel 2 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1OCCEN
+ Channel 1 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode
+ selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value
+ preload enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2ICFLT
+ Channel 2 input capture filter
+ 12
+ 4
+
+
+ IC2PSC
+ Channel 2 input capture pre-divide
+ 10
+ 2
+
+
+ CH2FS
+ Channel 2 function selection
+ 8
+ 2
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Output
+ CH34CFGR_Output
+ channel 3 and channel 4 configuration register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4OCCEN
+ Channel 4 output compare clear
+ enable
+ 15
+ 1
+
+
+ CH4OCMSEL
+ Channel 4 output compare mode selection
+ 12
+ 3
+
+
+ CH4OCVPEN
+ Channel 4 output compare value preload
+ enable
+ 11
+ 1
+
+
+ CH4OCFEN
+ Channel 4 output compare fast
+ enable
+ 10
+ 1
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3OCCEN
+ Channel 3 output compare clear
+ enable
+ 7
+ 1
+
+
+ CH3OCMSEL
+ Channel 3 output compare mode selection
+ 4
+ 3
+
+
+ CH3OCVPEN
+ Channel 3 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH3OCFEN
+ Channel 3 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH34CFGR_Input
+ CH34CFGR_Input
+ channel 3 and channel 4 configuration register (input
+ mode)
+ CH34CFGR_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4ICFLT
+ Channel 4 input capture filter
+ 12
+ 4
+
+
+ CH4ICPDIV
+ Channel 4 input capture pre-divide
+ 10
+ 2
+
+
+ CH4FS
+ Channel 4 function
+ selection
+ 8
+ 2
+
+
+ CH3ICFLT
+ Channel 3 input capture filter
+ 4
+ 4
+
+
+ CH3ICPDIV
+ Channel 3 input capture pre-divide
+ 2
+ 2
+
+
+ CH3FS
+ Channel 3 function
+ selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH4NCCP
+ Channel 4 complementary capture compare
+ Polarity
+ 15
+ 1
+
+
+ CH4CCP
+ Channel 4 capture compare
+ Polarity
+ 13
+ 1
+
+
+ CH4CCEN
+ Channel 4 capture compare
+ enable
+ 12
+ 1
+
+
+ CH3NCCP
+ Channel 3 complementary capture compare
+ Polarity
+ 11
+ 1
+
+
+ CH3CCP
+ Channel 3 capture compare
+ Polarity
+ 9
+ 1
+
+
+ CH3CCEN
+ Channel 3 capture compare
+ enable
+ 8
+ 1
+
+
+ CH2NCCP
+ Channel 2 complementary capture compare
+ Polarity
+ 7
+ 1
+
+
+ CH2CCP
+ Channel 2 capture compare
+ Polarity
+ 5
+ 1
+
+
+ CH2CCEN
+ Channel 2 capture compare
+ enable
+ 4
+ 1
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT_H
+ High counter value (TIM2
+ only)
+ 16
+ 16
+
+
+ CNT_L
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL_H
+ High Counter update value (TIM2
+ only)
+ 16
+ 16
+
+
+ UVAL_L
+ Low Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL_H
+ Channel 1 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH1CCVAL_L
+ Channel 1 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH2CCVAL
+ CH2CCVAL
+ channel 2 capture compare value register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2CCVAL_H
+ Channel 2 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH2CCVAL_L
+ Channel 2 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH3CCVAL
+ CH3CCVAL
+ channel 3 capture compare value register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3CCVAL_H
+ Channel 3 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH3CCVAL_L
+ Channel 3 low capture compare value
+ 0
+ 16
+
+
+
+
+ CH4CCVAL
+ CH4CCVAL
+ channel 4 capture compare value register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH4CCVAL_L
+ Channel 4 high capture compare value (TIM2
+ only)
+ 16
+ 16
+
+
+ CH4CCVAL_H
+ Channel 4 low capture compare value
+ 0
+ 16
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM14
+ General-purpose-timers
+ TIM
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM14
+ TIM14 global interrupt
+ 19
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1INTEN
+ Channel1 capture compare interrupt flag
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ CH1CCIF
+ Channel1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CH1CCG
+ Channel 1 capture
+ compare event generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration
+ register(output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ capture/compare mode register (input
+ mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare
+ Polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider value
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ Channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ REMAP
+ REMAP
+ remap register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1IS
+ Channel 1 input selection
+ 0
+ 2
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LVD
+ LVD through EXTI line detection
+ 1
+
+
+ EXTI0_1
+ EXTI Line[1:0] interrupts
+ 5
+
+
+ EXTI2_3
+ EXTI Line[3:2] interrupts
+ 6
+
+
+ EXTI4_15
+ EXTI Line15 and EXTI4 interrupts
+ 7
+
+
+
+ INTEN
+ INTEN
+ Interrupt enable register
+ 0x0
+ 0x20
+ read-write
+ 0x0F940000
+
+
+ INTEN0
+ Interrupt enable for line 0
+ 0
+ 1
+
+
+ INTEN1
+ Interrupt enable for line 1
+ 1
+ 1
+
+
+ INTEN2
+ Interrupt enable for line 2
+ 2
+ 1
+
+
+ INTEN3
+ Interrupt enable for line 3
+ 3
+ 1
+
+
+ INTEN4
+ Interrupt enable for line 4
+ 4
+ 1
+
+
+ INTEN5
+ Interrupt enable for line 5
+ 5
+ 1
+
+
+ INTEN6
+ Interrupt enable for line 6
+ 6
+ 1
+
+
+ INTEN7
+ Interrupt enable for line 7
+ 7
+ 1
+
+
+ INTEN8
+ Interrupt enable for line 8
+ 8
+ 1
+
+
+ INTEN9
+ Interrupt enable for line 9
+ 9
+ 1
+
+
+ INTEN10
+ Interrupt enable for line 10
+ 10
+ 1
+
+
+ INTEN11
+ Interrupt enable for line 11
+ 11
+ 1
+
+
+ INTEN12
+ Interrupt enable for line 12
+ 12
+ 1
+
+
+ INTEN13
+ Interrupt enable for line 13
+ 13
+ 1
+
+
+ INTEN14
+ Interrupt enable for line 14
+ 14
+ 1
+
+
+ INTEN15
+ Interrupt enable for line 15
+ 15
+ 1
+
+
+ INTEN16
+ Interrupt enable for line 16
+ 16
+ 1
+
+
+ INTEN17
+ Interrupt enable for line 17
+ 17
+ 1
+
+
+ INTEN18
+ Interrupt enable for line 18
+ 18
+ 1
+
+
+ INTEN19
+ Interrupt enable for line 19
+ 19
+ 1
+
+
+ INTEN20
+ Interrupt enable for line 20
+ 20
+ 1
+
+
+ INTEN21
+ Interrupt enable for line 21
+ 21
+ 1
+
+
+ INTEN22
+ Interrupt enable for line 22
+ 22
+ 1
+
+
+ INTEN23
+ Interrupt enable for line 23
+ 23
+ 1
+
+
+ INTEN24
+ Interrupt enable for line 24
+ 24
+ 1
+
+
+ INTEN25
+ Interrupt enable for line 25
+ 25
+ 1
+
+
+ INTEN26
+ Interrupt enable for line 26
+ 26
+ 1
+
+
+ INTEN27
+ Interrupt enable for line 27
+ 27
+ 1
+
+
+
+
+ EVTEN
+ EVTEN
+ Event enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVTEN0
+ Event enable for line 0
+ 0
+ 1
+
+
+ EVTEN1
+ Event enable for line 1
+ 1
+ 1
+
+
+ EVTEN2
+ Event enable for line 2
+ 2
+ 1
+
+
+ EVTEN3
+ Event enable for line 3
+ 3
+ 1
+
+
+ EVTEN4
+ Event enable for line 4
+ 4
+ 1
+
+
+ EVTEN5
+ Event enable for line 5
+ 5
+ 1
+
+
+ EVTEN6
+ Event enable for line 6
+ 6
+ 1
+
+
+ EVTEN7
+ Event enable for line 7
+ 7
+ 1
+
+
+ EVTEN8
+ Event enable for line 8
+ 8
+ 1
+
+
+ EVTEN9
+ Event enable for line 9
+ 9
+ 1
+
+
+ EVTEN10
+ Event enable for line 10
+ 10
+ 1
+
+
+ EVTEN11
+ Event enable for line 11
+ 11
+ 1
+
+
+ EVTEN12
+ Event enable for line 12
+ 12
+ 1
+
+
+ EVTEN13
+ Event enable for line 13
+ 13
+ 1
+
+
+ EVTEN14
+ Event enable for line 14
+ 14
+ 1
+
+
+ EVTEN15
+ Event enable for line 15
+ 15
+ 1
+
+
+ EVTEN16
+ Event enable for line 16
+ 16
+ 1
+
+
+ EVTEN17
+ Event enable for line 17
+ 17
+ 1
+
+
+ EVTEN18
+ Event enable for line 18
+ 18
+ 1
+
+
+ EVTEN19
+ Event enable for line 19
+ 19
+ 1
+
+
+ EVTEN20
+ Event enable for line 20
+ 20
+ 1
+
+
+ EVTEN21
+ Event enable for line 21
+ 21
+ 1
+
+
+ EVTEN22
+ Event enable for line 22
+ 22
+ 1
+
+
+ EVTEN23
+ Event enable for line 23
+ 23
+ 1
+
+
+ EVTEN24
+ Event enable for line 24
+ 24
+ 1
+
+
+ EVTEN25
+ Event enable for line 25
+ 25
+ 1
+
+
+ EVTEN26
+ Event enable for line 26
+ 26
+ 1
+
+
+ EVTEN27
+ Event enable for line 27
+ 27
+ 1
+
+
+
+
+ RTEN
+ RTEN
+ Rising edge trigger enable register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTEN0
+ Rising edge trigger enable for line 0
+ 0
+ 1
+
+
+ RTEN1
+ Rising edge trigger enable for line 1
+ 1
+ 1
+
+
+ RTEN2
+ Rising edge trigger enable for line 2
+ 2
+ 1
+
+
+ RTEN3
+ Rising edge trigger enable for line 3
+ 3
+ 1
+
+
+ RTEN4
+ Rising edge trigger enable for line 4
+ 4
+ 1
+
+
+ RTEN5
+ Rising edge trigger enable for line 5
+ 5
+ 1
+
+
+ RTEN6
+ Rising edge trigger enable for line 6
+ 6
+ 1
+
+
+ RTEN7
+ Rising edge trigger enable for line 7
+ 7
+ 1
+
+
+ RTEN8
+ Rising edge trigger enable for line 8
+ 8
+ 1
+
+
+ RTEN9
+ Rising edge trigger enable for line 9
+ 9
+ 1
+
+
+ RTEN10
+ Rising edge trigger enable for line 10
+ 10
+ 1
+
+
+ RTEN11
+ Rising edge trigger enable for line 11
+ 11
+ 1
+
+
+ RTEN12
+ Rising edge trigger enable for line 12
+ 12
+ 1
+
+
+ RTEN13
+ Rising edge trigger enable for line 13
+ 13
+ 1
+
+
+ RTEN14
+ Rising edge trigger enable for line 14
+ 14
+ 1
+
+
+ RTEN15
+ Rising edge trigger enable for line 15
+ 15
+ 1
+
+
+ RTEN16
+ Rising edge trigger enable for line 16
+ 16
+ 1
+
+
+ RTEN17
+ Rising edge trigger enable for line 17
+ 17
+ 1
+
+
+ RTEN19
+ Rising edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ FTEN
+ FTEN
+ Falling edge trigger enable register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FTEN0
+ Falling edge trigger enable for line 0
+ 0
+ 1
+
+
+ FTEN1
+ Falling edge trigger enable for line 1
+ 1
+ 1
+
+
+ FTEN2
+ Falling edge trigger enable for line 2
+ 2
+ 1
+
+
+ FTEN3
+ Falling edge trigger enable for line 3
+ 3
+ 1
+
+
+ FTEN4
+ Falling edge trigger enable for line 4
+ 4
+ 1
+
+
+ FTEN5
+ Falling edge trigger enable for line 5
+ 5
+ 1
+
+
+ FTEN6
+ Falling edge trigger enable for line 6
+ 6
+ 1
+
+
+ FTEN7
+ Falling edge trigger enable for line 7
+ 7
+ 1
+
+
+ FTEN8
+ Falling edge trigger enable for line 8
+ 8
+ 1
+
+
+ FTEN9
+ Falling edge trigger enable for line 9
+ 9
+ 1
+
+
+ FTEN10
+ Falling edge trigger enable for line 10
+ 10
+ 1
+
+
+ FTEN11
+ Falling edge trigger enable for line 11
+ 11
+ 1
+
+
+ FTEN12
+ Falling edge trigger enable for line 12
+ 12
+ 1
+
+
+ FTEN13
+ Falling edge trigger enable for line 13
+ 13
+ 1
+
+
+ FTEN14
+ Falling edge trigger enable for line 14
+ 14
+ 1
+
+
+ FTEN15
+ Falling edge trigger enable for line 15
+ 15
+ 1
+
+
+ FTEN16
+ Falling edge trigger enable for line 16
+ 16
+ 1
+
+
+ FTEN17
+ Falling edge trigger enable for line 17
+ 17
+ 1
+
+
+ FTEN19
+ Falling edge trigger enable for line 19
+ 19
+ 1
+
+
+
+
+ SWTIEN
+ SWTIEN
+ Software trigger interrupt/event
+ enable register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWTIEN0
+ Software trigger interrupt/event for
+ line 0
+ 0
+ 1
+
+
+ SWTIEN1
+ Software trigger interrupt/event for
+ line 1
+ 1
+ 1
+
+
+ SWTIEN2
+ Software trigger interrupt/event for
+ line 2
+ 2
+ 1
+
+
+ SWTIEN3
+ Software trigger interrupt/event for
+ line 3
+ 3
+ 1
+
+
+ SWTIEN4
+ Software trigger interrupt/event for
+ line 4
+ 4
+ 1
+
+
+ SWTIEN5
+ Software trigger interrupt/event for
+ line 5
+ 5
+ 1
+
+
+ SWTIEN6
+ Software trigger interrupt/event for
+ line 6
+ 6
+ 1
+
+
+ SWTIEN7
+ Software trigger interrupt/event for
+ line 7
+ 7
+ 1
+
+
+ SWTIEN8
+ Software trigger interrupt/event for
+ line 8
+ 8
+ 1
+
+
+ SWTIEN9
+ Software trigger interrupt/event for
+ line 9
+ 9
+ 1
+
+
+ SWTIEN10
+ Software trigger interrupt/event for
+ line 10
+ 10
+ 1
+
+
+ SWTIEN11
+ Software trigger interrupt/event for
+ line 11
+ 11
+ 1
+
+
+ SWTIEN12
+ Software trigger interrupt/event for
+ line 12
+ 12
+ 1
+
+
+ SWTIEN13
+ Software trigger interrupt/event for
+ line 13
+ 13
+ 1
+
+
+ SWTIEN14
+ Software trigger interrupt/event for
+ line 14
+ 14
+ 1
+
+
+ SWTIEN15
+ Software trigger interrupt/event for
+ line 15
+ 15
+ 1
+
+
+ SWTIEN16
+ Software trigger interrupt/event for
+ line 16
+ 16
+ 1
+
+
+ SWTIEN17
+ Software trigger interrupt/event for
+ line 17
+ 17
+ 1
+
+
+ SWTIEN19
+ Software trigger interrupt/event for
+ line 19
+ 19
+ 1
+
+
+
+
+ PDF
+ PDF
+ Pending flag register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PDF0
+ Pending interrupt flag for line 0
+ 0
+ 1
+
+
+ PDF1
+ Pending interrupt flag for line 1
+ 1
+ 1
+
+
+ PDF2
+ Pending interrupt flag for line 2
+ 2
+ 1
+
+
+ PDF3
+ Pending interrupt flag for line 3
+ 3
+ 1
+
+
+ PDF4
+ Pending interrupt flag for line 4
+ 4
+ 1
+
+
+ PDF5
+ Pending interrupt flag for line 5
+ 5
+ 1
+
+
+ PDF6
+ Pending interrupt flag for line 6
+ 6
+ 1
+
+
+ PDF7
+ Pending interrupt flag for line 7
+ 7
+ 1
+
+
+ PDF8
+ Pending interrupt flag for line 8
+ 8
+ 1
+
+
+ PDF9
+ Pending interrupt flag for line 9
+ 9
+ 1
+
+
+ PDF10
+ Pending interrupt flag for line 10
+ 10
+ 1
+
+
+ PDF11
+ Pending interrupt flag for line 11
+ 11
+ 1
+
+
+ PDF12
+ Pending interrupt flag for line 12
+ 12
+ 1
+
+
+ PDF13
+ Pending interrupt flag for line 13
+ 13
+ 1
+
+
+ PDF14
+ Pending interrupt flag for line 14
+ 14
+ 1
+
+
+ PDF15
+ Pending interrupt flag for line 15
+ 15
+ 1
+
+
+ PDF16
+ Pending interrupt flag for line 16
+ 16
+ 1
+
+
+ PDF17
+ Pending interrupt flag for line 17
+ 17
+ 1
+
+
+ PDF19
+ Pending interrupt flag for line 19
+ 19
+ 1
+
+
+
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0x33D
+ registers
+
+
+
+ ISER
+ ISER
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER
+ ICER
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR
+ ISPR
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR
+ ICPR
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_00
+ PRI_00
+ 6
+ 2
+
+
+ PRI_01
+ PRI_01
+ 14
+ 2
+
+
+ PRI_02
+ PRI_02
+ 22
+ 2
+
+
+ PRI_03
+ PRI_03
+ 30
+ 2
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x304
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_40
+ PRI_40
+ 6
+ 2
+
+
+ PRI_41
+ PRI_41
+ 14
+ 2
+
+
+ PRI_42
+ PRI_42
+ 22
+ 2
+
+
+ PRI_43
+ PRI_43
+ 30
+ 2
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_80
+ PRI_80
+ 6
+ 2
+
+
+ PRI_81
+ PRI_81
+ 14
+ 2
+
+
+ PRI_82
+ PRI_82
+ 22
+ 2
+
+
+ PRI_83
+ PRI_83
+ 30
+ 2
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x30C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_120
+ PRI_120
+ 6
+ 2
+
+
+ PRI_121
+ PRI_121
+ 14
+ 2
+
+
+ PRI_122
+ PRI_122
+ 22
+ 2
+
+
+ PRI_123
+ PRI_123
+ 30
+ 2
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x310
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_160
+ PRI_160
+ 6
+ 2
+
+
+ PRI_161
+ PRI_161
+ 14
+ 2
+
+
+ PRI_162
+ PRI_162
+ 22
+ 2
+
+
+ PRI_163
+ PRI_163
+ 30
+ 2
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x314
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_200
+ PRI_200
+ 6
+ 2
+
+
+ PRI_201
+ PRI_201
+ 14
+ 2
+
+
+ PRI_202
+ PRI_202
+ 22
+ 2
+
+
+ PRI_203
+ PRI_203
+ 30
+ 2
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x318
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_240
+ PRI_240
+ 6
+ 2
+
+
+ PRI_241
+ PRI_241
+ 14
+ 2
+
+
+ PRI_242
+ PRI_242
+ 22
+ 2
+
+
+ PRI_243
+ PRI_243
+ 30
+ 2
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x31C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PRI_280
+ PRI_280
+ 6
+ 2
+
+
+ PRI_281
+ PRI_281
+ 14
+ 2
+
+
+ PRI_282
+ PRI_282
+ 22
+ 2
+
+
+ PRI_283
+ PRI_283
+ 30
+ 2
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA1_Channel1
+ DMA channel 1 interrupt
+ 9
+
+
+ DMA1_Channel2_3
+ DMA channel 2 and 3 interrupts
+ 10
+
+
+ DMA1_Channel4_5
+ DMA channel 4 and 5 interrupts
+ 11
+
+
+
+ STS
+ STS
+ DMA interrupt status register
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF1
+ Global interrupt flag of Channel 1
+ 0
+ 1
+
+
+ CMPIF1
+ Transfer complete flag of Channel 1
+ 1
+ 1
+
+
+ HLFIF1
+ Half transfer flag of Channel 1
+ 2
+ 1
+
+
+ TEIF1
+ Transfer error flag of Channel 1
+ 3
+ 1
+
+
+ GIF2
+ Global interrupt flag of Channel 2
+ 4
+ 1
+
+
+ CMPIF2
+ Transfer complete flag of Channel 2
+ 5
+ 1
+
+
+ HTIF2
+ Half transfer flag of Channel 2
+ 6
+ 1
+
+
+ TEIF2
+ Transfer error flag of Channel 2
+ 7
+ 1
+
+
+ GIF3
+ Global interrupt flag of Channel 3
+ 8
+ 1
+
+
+ CMPIF3
+ Transfer complete flag of Channel 3
+ 9
+ 1
+
+
+ HLFIF3
+ Half transfer flag of Channel 3
+ 10
+ 1
+
+
+ ERRIF3
+ Transfer error flag of Channel 3
+ 11
+ 1
+
+
+ GIF4
+ Global interrupt flag of Channel 4
+ 12
+ 1
+
+
+ CMPIF4
+ Transfer complete flag of Channel 4
+ 13
+ 1
+
+
+ HLFIF4
+ Half transfer flag of Channel 4
+ 14
+ 1
+
+
+ ERRIF4
+ Transfer error flag of Channel 4
+ 15
+ 1
+
+
+ GIF5
+ Global interrupt flag of Channel 5
+ 16
+ 1
+
+
+ CMPIF5
+ Transfer complete flag of Channel 5
+ 17
+ 1
+
+
+ HLFIF5
+ Half transfer flag of Channel 5
+ 18
+ 1
+
+
+ ERRIF5
+ Transfer error flag of Channel 5
+ 19
+ 1
+
+
+ GIF6
+ Global interrupt flag of Channel 6
+ 20
+ 1
+
+
+ CMPIF6
+ Transfer complete flag of Channel 6
+ 21
+ 1
+
+
+ HLFIF6
+ Half transfer flag of Channel 6
+ 22
+ 1
+
+
+ ERRIF6
+ Transfer error flag of Channel 6
+ 23
+ 1
+
+
+ GIF7
+ Global interrupt flag of Channel 7
+ 24
+ 1
+
+
+ CMPIF7
+ Transfer complete flag of Channel 7
+ 25
+ 1
+
+
+ HLFIF7
+ Half transfer flag of Channel 7
+ 26
+ 1
+
+
+ ERRIF7
+ Transfer error flag of Channel 7
+ 27
+ 1
+
+
+
+
+ INTFC
+ INTFC
+ DMA interrupt status clear register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CGIF1
+ Global interrupt flag clear of
+ Channel 1
+ 0
+ 1
+
+
+ CGIF2
+ Global interrupt flag clear of
+ Channel 2
+ 4
+ 1
+
+
+ CGIF3
+ Global interrupt flag clear of
+ Channel 3
+ 8
+ 1
+
+
+ CGIF4
+ Global interrupt flag clear of
+ Channel 4
+ 12
+ 1
+
+
+ CGIF5
+ Global interrupt flag clear of
+ Channel 5
+ 16
+ 1
+
+
+ CGIF6
+ Global interrupt flag clear of
+ Channel 6
+ 20
+ 1
+
+
+ CGIF7
+ Global interrupt flag clear of
+ Channel 7
+ 24
+ 1
+
+
+ CMPIFC1
+ Transfer complete flag clear of
+ Channel 1
+ 1
+ 1
+
+
+ CMPIFC2
+ Transfer complete flag clear of
+ Channel 2
+ 5
+ 1
+
+
+ CMPIFC3
+ Transfer complete flag clear of
+ Channel 3
+ 9
+ 1
+
+
+ CMPIFC4
+ Transfer complete flag clear of
+ Channel 4
+ 13
+ 1
+
+
+ CMPIFC5
+ Transfer complete flag clear of
+ Channel 5
+ 17
+ 1
+
+
+ CMPIFC6
+ Transfer complete flag clear of
+ Channel 6
+ 21
+ 1
+
+
+ CMPIFC7
+ Transfer complete flag clear of
+ Channel 7
+ 25
+ 1
+
+
+ HLFIFC1
+ Half transfer flag clear of
+ Channel 1
+ 2
+ 1
+
+
+ HLFIFC2
+ Half transfer flag clear of
+ Channel 2
+ 6
+ 1
+
+
+ HLFIFC3
+ Half transfer flag clear of
+ Channel 3
+ 10
+ 1
+
+
+ HLFIFC4
+ Half transfer flag clear of
+ Channel 4
+ 14
+ 1
+
+
+ HLFIFC5
+ Half transfer flag clear of
+ Channel 5
+ 18
+ 1
+
+
+ HLFIFC6
+ Half transfer flag clear of
+ Channel 6
+ 22
+ 1
+
+
+ HLFIFC7
+ Half transfer flag clear of
+ Channel 7
+ 26
+ 1
+
+
+ ERRIFC1
+ Transfer error flag clear of
+ Channel 1
+ 3
+ 1
+
+
+ ERRIFC2
+ Transfer error flag clear of
+ Channel 2
+ 7
+ 1
+
+
+ ERRIFC3
+ Transfer error flag clear of
+ Channel 3
+ 11
+ 1
+
+
+ ERRIFC4
+ Transfer error flag clear of
+ Channel 4
+ 15
+ 1
+
+
+ ERRIFC5
+ Transfer error flag clear of
+ Channel 5
+ 19
+ 1
+
+
+ ERRIFC6
+ Transfer error flag clear of
+ Channel 6
+ 23
+ 1
+
+
+ ERRIFC7
+ Transfer error flag clear of
+ Channel 7
+ 27
+ 1
+
+
+
+
+ CH1CTR
+ CH1CTR
+ DMA channel 1 controller register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CEN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH1NUM
+ CH1NUM
+ Transfer data number register of DMA
+ channel 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH1PA
+ CH1PA
+ Peripheral address register of
+ DMA channel 1
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH1MA
+ CH1MA
+ Memory address register of
+ DMA channel 1
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH2CTR
+ CH2CTR
+ DMA channel 2 controller register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH2NUM
+ CH2NUM
+ Transfer data number register of
+ DMA channel 2
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH2PA
+ CH2PA
+ Peripheral address register of
+ DMA channel 2
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH2MA
+ CH2MA
+ Memory address register of DMA
+ channel 2
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH3CTR
+ CH3CTR
+ DMA channel 3 controller register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH3NUM
+ CH3NUM
+ Transfer data number register of
+ DMA channel 3
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH3PA
+ CH3PA
+ Peripheral address register of
+ DMA channel 3
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH3MA
+ CH3MA
+ Memory address register of
+ DMA channel 3
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH4CTR
+ CH4CTR
+ DMA channel 4 controller register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH4NUM
+ CH4NUM
+ Transfer data number register of
+ DMA channel 4
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH4PA
+ CH4PA
+ Peripheral address register of
+ DMA channel 4
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH4MA
+ CH4MA
+ Memory address register of
+ DMA channel 4
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH5CTR
+ CH5CTR
+ DMA channel 5 controller register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH5NUM
+ CH5NUM
+ Transfer data number register of
+ DMA channel 5
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH5PA
+ CH5PA
+ Peripheral address register of
+ DMA channel 5
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH5MA
+ CH5MA
+ Memory address register of
+ DMA channel 5
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH6CTR
+ CH6CTR
+ DMA channel 6 controller register
+ 0x6C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH6NUM
+ CH6NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x70
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH6PA
+ CH6PA
+ Peripheral address register of
+ DMA channel 6
+ 0x74
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH6MA
+ CH6MA
+ Memory address register of
+ DMA channel 6
+ 0x78
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH7CTR
+ CH7CTR
+ DMA channel 7 controller register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EN
+ Channel enable
+ 0
+ 1
+
+
+ CMPIE
+ Enable bit for Transfer
+ complete interrupt
+ 1
+ 1
+
+
+ HLFIE
+ Enable bit for Half
+ transfer interrupt
+ 2
+ 1
+
+
+ ERRIE
+ Enable bit for Transfer
+ error interrupt
+ 3
+ 1
+
+
+ DIR
+ Direction of transfer
+ 4
+ 1
+
+
+ CIRM
+ Circular mode
+ 5
+ 1
+
+
+ PAGM
+ Peripheral address generation mode
+ 6
+ 1
+
+
+ MAGM
+ Memory address generation mode
+ 7
+ 1
+
+
+ PWDH
+ Peripheral width
+ 8
+ 2
+
+
+ MWDH
+ Memory width
+ 10
+ 2
+
+
+ PRIL
+ Priority level of Channel
+ 12
+ 2
+
+
+ M2MM
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH7NUM
+ CH7NUM
+ Transfer data number register of
+ DMA channel 7
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ NUM
+ transfer data number
+ 0
+ 16
+
+
+
+
+ CH7PA
+ CH7PA
+ Peripheral address register of
+ DMA channel 7
+ 0x88
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADR
+ Peripheral address
+ 0
+ 32
+
+
+
+
+ CH7MA
+ CH7MA
+ Memory address register of
+ DMA channel 7
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADR
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ RCU
+ Reset and clock unit
+ RCU
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCU
+ RCU global interrupt
+ 4
+
+
+
+ CTR
+ CTR
+ Clock control register
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ HRCEN
+ HRC Enable
+ 0
+ 1
+ read-write
+
+
+ HRCSTAB
+ HRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ HRCTRIM
+ HRC Triming
+ 3
+ 5
+ read-write
+
+
+ HRCCALIB
+ HRC Internal 8MHz RC calibration
+ 8
+ 8
+ read-only
+
+
+ HXTEN
+ HXT Enable
+ 16
+ 1
+ read-write
+
+
+ HXTSTAB
+ HXT Stabilization flag
+ 17
+ 1
+ read-only
+
+
+ HXTBPS
+ HXT Bypass Enable
+ 18
+ 1
+ read-write
+
+
+ HXTME
+ HXT Monitor Enable
+ 19
+ 1
+ read-write
+
+
+ HXTDRV
+ HXT Drive capability Selection
+ 21
+ 2
+ read-write
+
+
+ PLLEN
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ PLLSTAB
+ PLL Stabilization flag
+ 25
+ 1
+ read-only
+
+
+
+
+ CFG
+ CFG
+ Clock configuration register
+ 0x4
+ 0x20
+ 0x00000000
+
+
+ SYSSW
+ System clock switch Control
+ 0
+ 2
+ read-write
+
+
+ SYSSS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ HCLKPDIV
+ HCLK Pre-divider
+ 4
+ 4
+ read-write
+
+
+ PCLKPDIV
+ PCLK Pre-divider
+ 8
+ 3
+ read-write
+
+
+ ADCPDIV
+ ADC Clock Pre-divider
+ 14
+ 1
+ read-write
+
+
+ PLLSEL
+ PLL source Selction
+ 15
+ 2
+ read-write
+
+
+ PLLHXTPDIV
+ PLL source HXT pre-divdier
+ 17
+ 1
+ read-write
+
+
+ PLLMUF
+ PLL clock multiplication factor
+ 18
+ 4
+ read-write
+
+
+ CKOSEL
+ CLKOUT Source Selection
+ 24
+ 4
+ read-write
+
+
+ CKOPDIV
+ CLKOUT Pre-divider
+ 28
+ 3
+ read-write
+
+
+ CKOPLLND
+ PLL clock not divided for CLKOUT
+ 31
+ 1
+ read-write
+
+
+
+
+ INTR
+ INTR
+ Clock interrupt register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ LRCSTABIF
+ LRC stabilization interrupt flag
+ 0
+ 1
+ read-only
+
+
+ LXTSTABIF
+ LXT stabilization interrupt flag
+ 1
+ 1
+ read-only
+
+
+ HRCSTABIF
+ HRC stabilization interrupt flag
+ 2
+ 1
+ read-only
+
+
+ HXTSTABIF
+ HXT stabilization interrupt flag
+ 3
+ 1
+ read-only
+
+
+ PLLSTABIF
+ PLL stabilization interrupt flag
+ 4
+ 1
+ read-only
+
+
+ HRC14STABIF
+ HRC14 stabilization interrupt flag
+ 5
+ 1
+ read-only
+
+
+ CKFAILIF
+ HXT clock fail interrupt flag
+ 7
+ 1
+ read-only
+
+
+ LRCSTABIE
+ LRC stabilization interrupt enable
+ 8
+ 1
+ read-write
+
+
+ LXTSTABIE
+ LXT stabilization interrupt enable
+ 9
+ 1
+ read-write
+
+
+ HRCSTABIE
+ HRC stabilization Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ HXTSTABIE
+ HXT stabilization Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ PLLSTABIE
+ PLL stabilization Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ HRC14STABIE
+ HRC14 stabilization Interrupt Enable
+ 13
+ 1
+ read-write
+
+
+ LRCSTABIC
+ LRC stabilization Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ LXTSTABIC
+ LXT stabilization Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ HRCSTABIC
+ HRC stabilization Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ HXTSTABIC
+ HXT stabilization Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ PLLSTABIC
+ PLL stabilization Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ HRC14STABIC
+ HRC14 stabilization Interrupt Clear
+ 21
+ 1
+ write-only
+
+
+ CKFAILIC
+ HXT Clock Fail Interrupt Clear
+ 23
+ 1
+ write-only
+
+
+
+
+ APB2RST
+ APB2RST
+ APB2 reset register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGRST
+ SYSCFG reset
+ 0
+ 1
+
+
+ ADCRST
+ ADC interface reset
+ 9
+ 1
+
+
+ TIM1RST
+ TIM1 timer reset
+ 11
+ 1
+
+
+ SPI1RST
+ SPI 1 reset
+ 12
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 14
+ 1
+
+
+ TIM16RST
+ TIM16 timer reset
+ 17
+ 1
+
+
+ TIM17RST
+ TIM17 timer reset
+ 18
+ 1
+
+
+ DBGRST
+ Debug MCU reset
+ 22
+ 1
+
+
+
+
+ APB1RST
+ APB1RST
+ APB1 reset register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2RST
+ Timer 2 reset
+ 0
+ 1
+
+
+ TIM3RST
+ Timer 3 reset
+ 1
+ 1
+
+
+ TIM14RST
+ Timer 14 reset
+ 8
+ 1
+
+
+ WWDTRST
+ WWDT reset
+ 11
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 21
+ 1
+
+
+ PMURST
+ PMU reset
+ 28
+ 1
+
+
+
+
+ AHBEN
+ AHBEN
+ AHB Clock enable register
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ DMAEN
+ enable bit for DMA clock
+ 0
+ 1
+
+
+ RMCEN
+ enable bit for SRAM clock
+ 2
+ 1
+
+
+ FMCEN
+ enable bit for FMC clock
+ 4
+ 1
+
+
+ CRCEN
+ enable bit for CRC clock
+ 6
+ 1
+
+
+ PAEN
+ enable bit for GPIO port A clock
+ 17
+ 1
+
+
+ PBEN
+ enable bit for GPIO port B clock
+ 18
+ 1
+
+
+ PCEN
+ enable bit for GPIO port C clock
+ 19
+ 1
+
+
+ PDEN
+ enable bit for GPIO port D clock
+ 20
+ 1
+
+
+ PEEN
+ enable bit for GPIO port E clock
+ 21
+ 1
+
+
+ PFEN
+ enable bit for GPIO port F clock
+ 22
+ 1
+
+
+
+
+ APB2EN
+ APB2EN
+ APB peripheral clock enable register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SYSCFGEN
+ enable bit for SYSCFG clock
+ 0
+ 1
+
+
+ ADCEN
+ enable bit for ADC clock
+ 9
+ 1
+
+
+ TIM1EN
+ enable bit for TIM1 clock
+ 11
+ 1
+
+
+ SPI1EN
+ enable bit for SPI1 clock
+ 12
+ 1
+
+
+ USART1EN
+ enable bit for USART1 clock
+ 14
+ 1
+
+
+ TIM16EN
+ enable bit for TIM16 clock
+ 17
+ 1
+
+
+ TIM17EN
+ enable bit for TIM17 clock
+ 18
+ 1
+
+
+ DBGEN
+ enable bit for DBG clock
+ 22
+ 1
+
+
+
+
+ APB1EN
+ APB1EN
+ APB peripheral clock enable register 1
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIM2EN
+ Tenable bit for TIM2 clock
+ 0
+ 1
+
+
+ TIM3EN
+ enable bit for TIM3 clock
+ 1
+ 1
+
+
+ TIM14EN
+ enable bit for TIM14 clock
+ 8
+ 1
+
+
+ WWDTEN
+ enable bit for WWDT clock
+ 11
+ 1
+
+
+ I2C1EN
+ enable bit for I2C1 clock
+ 21
+ 1
+
+
+ PMUEN
+ enable bit for PMU clock
+ 28
+ 1
+
+
+
+
+ VBDC
+ VBDC
+ VBAT domain control register
+ 0x20
+ 0x20
+ 0x00000000
+
+
+ LXTEN
+ LXT Enable
+ 0
+ 1
+ read-write
+
+
+ LXTSTAB
+ LXT Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ LXTBYP
+ LXT bypass
+ 2
+ 1
+ read-write
+
+
+ LXTDRV
+ LXT oscillator drive capability
+ 3
+ 3
+ read-write
+
+
+ RTCSRC
+ RTC clock source selection
+ 8
+ 2
+ read-write
+
+
+ RTCCLKEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ VBTRST
+ VBAT domain software reset
+ 16
+ 1
+ read-write
+
+
+
+
+ STS
+ STS
+ status register
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LRCEN
+ LRC enable
+ 0
+ 1
+ read-write
+
+
+ LRCSTAB
+ LRC Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ REGERRRSTF
+ register error flag
+ 22
+ 1
+ read-only
+
+
+ V15RSTF
+ Reset flag from the 1.5V domain
+ 23
+ 1
+ read-only
+
+
+ CRSTF
+ Clear reset flag
+ 24
+ 1
+ read-write
+
+
+ OBURSTF
+ Option byte update reset
+ flag
+ 25
+ 1
+ read-write
+
+
+ NRSTF
+ reset flag of pin nRST
+ 26
+ 1
+ read-write
+
+
+ PORRSTF
+ POR/PDR reset flag
+ 27
+ 1
+ read-write
+
+
+ SWRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ FWDTRSTF
+ FWDT reset flag
+ 29
+ 1
+ read-write
+
+
+ WWDTRSTF
+ WWDT reset flag
+ 30
+ 1
+ read-write
+
+
+ LPERSTF
+ Low-power mode enter-reset flag
+ 31
+ 1
+ read-write
+
+
+
+
+ AHBRST
+ AHBRST
+ AHB reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PARST
+ GPIO port A reset
+ 17
+ 1
+
+
+ PBRST
+ GPIO port B reset
+ 18
+ 1
+
+
+ PCRST
+ GPIO port C reset
+ 19
+ 1
+
+
+ PDRST
+ GPIO port D reset
+ 20
+ 1
+
+
+ PERST
+ GPIO port E reset
+ 21
+ 1
+
+
+ PFRST
+ GPIO port F reset
+ 22
+ 1
+
+
+
+
+ CFG2
+ CFG2
+ Clock configuration register 2
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PLLPDIV
+ PLL pre-divider factor
+ 0
+ 4
+
+
+
+
+ CFG3
+ CFG3
+ Clock configuration register 3
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ USART1SEL
+ Selection of USART1 Clock
+ 0
+ 2
+
+
+ I2C1SEL
+ Selection of I2C1 Clock
+ 4
+ 1
+
+
+ ADCSEL
+ Selection of ADC Clock
+ 8
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Clock control register 2
+ 0x34
+ 0x20
+ 0x00000080
+
+
+ HRC14EN
+ HRC14 enable
+ 0
+ 1
+ read-write
+
+
+ HRC14STAB
+ HRC14 Stabilization flag
+ 1
+ 1
+ read-only
+
+
+ ADCDISHRC14
+ ADC control HRC14 opening disable
+ 2
+ 1
+ read-write
+
+
+ HRC14TRIM
+ HRC14 Triming
+ 3
+ 5
+ read-write
+
+
+ HRC14CALIB
+ HRC14 calibration
+ 8
+ 8
+ read-only
+
+
+
+
+
+
+ SYSCFG
+ System configuration
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ RMAPCFG
+ RMAPCFG
+ SYSCFG remap configuration
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ I2C_FMPEN_PA10
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 23
+ 1
+
+
+ I2C_FMPEN_PA9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 22
+ 1
+
+
+ I2C_FMPEN_PB9
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 19
+ 1
+
+
+ I2C_FMPEN_PB8
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 18
+ 1
+
+
+ I2C_FMPEN_PB7
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 17
+ 1
+
+
+ I2C_FMPEN_PB6
+ Fast Mode Plus (FM+) driving capability
+ activation bits.
+ 16
+ 1
+
+
+ TIM17_DMA_CHRMAP
+ TIM17 DMA channel remapping
+ 12
+ 1
+
+
+ TIM16_DMA_CHRMAP
+ TIM16 DMA channel remapping
+ 11
+ 1
+
+
+ USART1_RX_DMA_CHRMAP
+ USART1 RX DMA channel remapping
+ 10
+ 1
+
+
+ USART1_TX_DMA_CHRMAP
+ USART1 TX DMA channel remapping
+ 9
+ 1
+
+
+ ADC_DMA_CHRMAP
+ ADC DMA channel remapping
+ 8
+ 1
+
+
+ MEM_RMAP
+ Memory remapping selection
+ 0
+ 2
+
+
+
+
+ EXTISRC1
+ EXTISRC1
+ external interrupt source selection register 1
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL3
+ External interrupt source selection 3
+ 12
+ 4
+
+
+ EXTI_SEL2
+ External interrupt source selection 2
+ 8
+ 4
+
+
+ EXTI_SEL1
+ External interrupt source selection 1
+ 4
+ 4
+
+
+ EXTI_SEL0
+ External interrupt source selection 0
+ 0
+ 4
+
+
+
+
+ EXTISRC2
+ EXTISRC2
+ external interrupt source selection register
+ 2
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL7
+ External interrupt source selection 7
+ 12
+ 4
+
+
+ EXTI_SEL6
+ External interrupt source selection 6
+ 8
+ 4
+
+
+ EXTI_SEL5
+ External interrupt source selection 5
+ 4
+ 4
+
+
+ EXTI_SEL4
+ External interrupt source selection 4
+ 0
+ 4
+
+
+
+
+ EXTISRC3
+ EXTISRC3
+ external interrupt source selection register
+ 3
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL11
+ External interrupt source selection 11
+ 12
+ 4
+
+
+ EXTI_SEL10
+ External interrupt source selection 10
+ 8
+ 4
+
+
+ EXTI_SEL9
+ External interrupt source selection 9
+ 4
+ 4
+
+
+ EXTI_SEL8
+ External interrupt source selection 8
+ 0
+ 4
+
+
+
+
+ EXTISRC4
+ EXTISRC4
+ external interrupt source selection register
+ 4
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ EXTI_SEL15
+ External interrupt source selection 15
+ 12
+ 4
+
+
+ EXTI_SEL14
+ External interrupt source selection 14
+ 8
+ 4
+
+
+ EXTI_SEL13
+ External interrupt source selection 13
+ 4
+ 4
+
+
+ EXTI_SEL12
+ External interrupt source selection 12
+ 0
+ 4
+
+
+
+
+ ERRLOCK
+ ERRLOCK
+ error and timer break lock
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ SRAM_PRTY_ERR
+ SRAM parity error flag
+ 8
+ 1
+
+
+ PVD_TIMBRK_LOCK
+ PVD output lock to tim
+ break enable
+ 2
+ 1
+
+
+ SRAM_PRTY_TIMBRK_LOCK
+ SRAM parity lock to
+ tim break
+ 1
+ 1
+
+
+ LOCKUP_TIMBRK_LOCK
+ Cortex-M0 LOCKUP lock to tim
+ break enable
+ 0
+ 1
+
+
+
+
+
+
+ ADC
+ Analog-to-digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_COMP
+ ADC and comparator 1 and 2
+ 12
+
+
+
+ STAT
+ STAT
+ ADC status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVT
+ analog watchdog event flag
+ 7
+ 1
+
+
+ DOVR
+ ADC data overrun flag
+ 4
+ 1
+
+
+ EOCG
+ End of conversion group flag
+ 3
+ 1
+
+
+ EOCH
+ End of channel conversion flag
+ 2
+ 1
+
+
+ EOSP
+ End of sampling phase flag
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization
+ 0
+ 1
+
+
+
+
+ INTEN
+ INTEN
+ ADC interrupt enable register
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDEVTIE
+ analog watchdog event interrupt
+ enable
+ 7
+ 1
+
+
+ DATOVR
+ ADC data overrun interrupt enable
+ 4
+ 1
+
+
+ EOGIE
+ End of conversion group interrupt
+ enable
+ 3
+ 1
+
+
+ EOC
+ End of channel conversion interrupt
+ enable
+ 2
+ 1
+
+
+ EOSMPL
+ End of sampling phase interrupt
+ enable
+ 1
+ 1
+
+
+ EOI
+ End of ADC initialization interrupt
+ enable
+ 0
+ 1
+
+
+
+
+ CTR
+ CTR
+ ADC general control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CALB
+ ADC calibration control
+ 31
+ 1
+
+
+ ADSTOP
+ ADC stop conversion
+ command
+ 4
+ 1
+
+
+ ADSTRT
+ ADC start conversion
+ command
+ 2
+ 1
+
+
+ ADCOFF
+ ADC power off command
+ 1
+ 1
+
+
+ ADCON
+ ADC power on command
+ 0
+ 1
+
+
+
+
+ CFG
+ CFG
+ configuration register 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDGCHAN
+ Analog watchdog monitor channel
+ selection
+ 26
+ 5
+
+
+ WDGEN
+ Analog watchdog enable
+ 23
+ 1
+
+
+ WDGCHMODE
+ Analog watchdog channel monitor
+ mode
+ 22
+ 1
+
+
+ DISCONT
+ Discontinuous conversion mode
+ 16
+ 1
+
+
+ ATSTDBY
+ auto standby mode
+ 15
+ 1
+
+
+ PAUSE
+ conversion pause mode
+ 14
+ 1
+
+
+ GCONT
+ Group conversion Single/continuous
+ mode
+ 13
+ 1
+
+
+ DOVRWRT
+ Coversion data overrun overwriten
+ mode
+ 12
+ 1
+
+
+ TRGMODE
+ Coverstion Trigger mode selection
+ 10
+ 2
+
+
+ HTRGSEL
+ Hardware trigger source selection
+ 6
+ 3
+
+
+ DATALG
+ Coversion data format alignment
+ 5
+ 1
+
+
+ DATRES
+ Coversion data reselution
+ 3
+ 2
+
+
+ CGDIR
+ Coveration group sequence
+ direction
+ 2
+ 1
+
+
+ DMAMODE
+ Direct memory access
+ single/circle mode
+ 1
+ 1
+
+
+ DMAEN
+ Direct memory access
+ enable
+ 0
+ 1
+
+
+
+
+ CLK
+ CLK
+ clock source register
+ 0x10
+ 0x20
+ read-write
+ 0x00008000
+
+
+ CKSRC
+ ADC clock source selection
+ 30
+ 2
+
+
+
+
+ SMPLR
+ SMPLR
+ sampling time register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SMPLT
+ Sampling time selection
+ 0
+ 3
+
+
+
+
+ WDTH
+ WDTH
+ Analog watchdog threshold register
+ 0x20
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ HITH
+ Analog watchdog higher
+ threshold
+ 16
+ 12
+
+
+ LOTH
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ CHANSEL
+ CHANSEL
+ conversion channel selection register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHANSEL18
+ conversion channel selection x
+ 18
+ 1
+
+
+ CHANSEL17
+ conversion channel selection x
+ 17
+ 1
+
+
+ CHANSEL16
+ conversion channel selection x
+ 16
+ 1
+
+
+ CHANSEL15
+ conversion channel selection x
+ 15
+ 1
+
+
+ CHANSEL14
+ conversion channel selection x
+ 14
+ 1
+
+
+ CHANSEL13
+ conversion channel selection x
+ 13
+ 1
+
+
+ CHANSEL12
+ conversion channel selection x
+ 12
+ 1
+
+
+ CHANSEL11
+ conversion channel selection x
+ 11
+ 1
+
+
+ CHANSEL10
+ conversion channel selection x
+ 10
+ 1
+
+
+ CHANSEL9
+ conversion channel selection x
+ 9
+ 1
+
+
+ CHANSEL8
+ conversion channel selection x
+ 8
+ 1
+
+
+ CHANSEL7
+ conversion channel selection x
+ 7
+ 1
+
+
+ CHANSEL6
+ conversion channel selection x
+ 6
+ 1
+
+
+ CHANSEL5
+ conversion channel selection x
+ 5
+ 1
+
+
+ CHANSEL4
+ conversion channel selection x
+ 4
+ 1
+
+
+ CHANSEL3
+ conversion channel selection x
+ 3
+ 1
+
+
+ CHANSEL2
+ conversion channel selection x
+ 2
+ 1
+
+
+ CHANSEL1
+ conversion channel selection x
+ 1
+ 1
+
+
+ CHANSEL0
+ conversion channel selection x
+ 0
+ 1
+
+
+
+
+ OUTDAT
+ OUTDAT
+ conversion output data register
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OUTDAT
+ conversion output data
+ 0
+ 16
+
+
+
+
+ INNCHEN
+ INNCHEN
+ internal conversion channel enable
+ register
+ 0x308
+ 0x20
+ read-write
+ 0x00000000
+
+
+ VBATMEN
+ VBAT monitor enable
+ 24
+ 1
+
+
+ TPSEN
+ Temperature sensor enable
+ 23
+ 1
+
+
+ VREFINTEN
+ VREFINT enable
+ 22
+ 1
+
+
+
+
+
+
+ USART1
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART1
+ USART1 global interrupt
+ 27
+
+
+
+ CTR1
+ CTR1
+ Control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BTCIE
+ Enable bit for Block transmit
+ complete interrupt
+ 27
+ 1
+
+
+ OVRTIE
+ Enable bit for Receiver overtime
+ interrupt
+ 26
+ 1
+
+
+ PRETDE
+ Pre-active time for Driver
+ Enable
+ 21
+ 5
+
+
+ POSTDE
+ Pos-active time for Driver
+ Enable
+ 16
+ 5
+
+
+ OVRS
+ Oversampling selection
+ 15
+ 1
+
+
+ CMIE
+ Enable bit for Character
+ match interrupt
+ 14
+ 1
+
+
+ RXMSKEN
+ Reception mask mode enable
+ 13
+ 1
+
+
+ DL
+ Data length
+ 12
+ 1
+
+
+ RXWKUPS
+ Receiver wakeup selection
+ 11
+ 1
+
+
+ PEN
+ Parity enable
+ 10
+ 1
+
+
+ ODDS
+ Odd parity selection
+ 9
+ 1
+
+
+ PERRIE
+ Enable bit for parity err
+ interrupt
+ 8
+ 1
+
+
+ TXEIE
+ Enable bit for transmit empty
+ interrupt
+ 7
+ 1
+
+
+ TCIE
+ Enable bit for transmit
+ complete interrupt
+ 6
+ 1
+
+
+ RXNEIE
+ Enable bit for RXNE interrupt
+ 5
+ 1
+
+
+ IDLEIE
+ Enable bit for IDLE interrupt
+ 4
+ 1
+
+
+ TEN
+ Transmitter enable
+ 3
+ 1
+
+
+ REN
+ Receiver enable
+ 2
+ 1
+
+
+ WKUPSTOP
+ Wakeup mcu from stop mode enable
+ 1
+ 1
+
+
+ UEN
+ USART enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ Control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ UADR_4
+ USART Address
+ 28
+ 4
+
+
+ UADR_0
+ USART Address
+ 24
+ 4
+
+
+ ROTEN
+ Receiver overtime enable
+ 23
+ 1
+
+
+ ABRSEL
+ Auto baud rate mode selection
+ 21
+ 2
+
+
+ ABREN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBF
+ MSB first
+ 19
+ 1
+
+
+ DINV
+ Data bit inversion
+ 18
+ 1
+
+
+ TXINV
+ TX pin inversion
+ 17
+ 1
+
+
+ RXINV
+ RX pin inversion
+ 16
+ 1
+
+
+ TXRXSWAP
+ TX/RX pins swap enable
+ 15
+ 1
+
+
+ LINEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STOPLEN
+ STOP bits length
+ 12
+ 2
+
+
+ CKEN
+ CK pin enable
+ 11
+ 1
+
+
+ CPOL
+ Clock polarity
+ 10
+ 1
+
+
+ CPHA
+ Clock phase
+ 9
+ 1
+
+
+ CKLEN
+ LCK length
+ 8
+ 1
+
+
+ LBDIE
+ Enable bit for LIN break frame
+ detection interrupt
+ 6
+ 1
+
+
+ LINBRK11
+ 11-bit break frame detection
+ 5
+ 1
+
+
+ ADRM7
+ 4bit/7bit Address Detection selection
+ 4
+ 1
+
+
+
+
+ CTR3
+ CTR3
+ Control register 3
+ 0x8
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPIE
+ Enable bit for Wakeup from
+ Stop mode interrupt
+ 22
+ 1
+
+
+ WKUPMTHD
+ Wakeup from Stop mode method
+ 20
+ 2
+
+
+ SCANUM
+ Number of Smartcard auto-retry times
+ 17
+ 3
+
+
+ DEPS
+ DE polarity selection
+ 15
+ 1
+
+
+ DEN
+ DE enable
+ 14
+ 1
+
+
+ DRMRE
+ DMA request mask on Reception
+ Error
+ 13
+ 1
+
+
+ NORXOF
+ No Receive Overflow detection
+ 12
+ 1
+
+
+ SPMS
+ Sample method selection
+ 11
+ 1
+
+
+ CTSIE
+ Enable bit for CTS interrupt
+ 10
+ 1
+
+
+ CTSEN
+ CTS enable
+ 9
+ 1
+
+
+ RTSEN
+ RTS enable
+ 8
+ 1
+
+
+ TXDMA
+ Transmit with DMA
+ 7
+ 1
+
+
+ RXDMA
+ Receive with DMA
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ SCNACK
+ Smartcard transmit NACK in parity error
+ 4
+ 1
+
+
+ HDEN
+ Half-duplex enable
+ 3
+ 1
+
+
+ IRMS
+ IrDA mode selection
+ 2
+ 1
+
+
+ IRDAEN
+ IrDA mode enable
+ 1
+ 1
+
+
+ ERRIE
+ Enable bit for Error interrupt
+ 0
+ 1
+
+
+
+
+ BRT
+ BRT
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ INTDIV
+ DIV INT value
+ 4
+ 12
+
+
+ FRADIV
+ DIV Fraction value
+ 0
+ 4
+
+
+
+
+ GTPDIV
+ GTPDIV
+ Guard time and pre-divider
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ GUDT
+ Guard time value
+ 8
+ 8
+
+
+ PDIV
+ Pre-divider value
+ 0
+ 8
+
+
+
+
+ RXOVR
+ RXOVR
+ Receiver overtime register
+ 0x14
+ 0x20
+ read-write
+ 0x0000
+
+
+ NUMBLK
+ Unit number of block
+ 24
+ 8
+
+
+ RXOVR
+ Receiver overtime value
+ 0
+ 24
+
+
+
+
+ SWTR
+ SWTR
+ Software Trigger register
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXESET
+ TXE set trigger
+ 4
+ 1
+
+
+ RXNECLR
+ RXNE clear trigger
+ 3
+ 1
+
+
+ RXMSKT
+ Reception mask mode trigger
+ 2
+ 1
+
+
+ BRKFST
+ Break frame send trigger
+ 1
+ 1
+
+
+ ABRT
+ Auto baud rate trigger
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ Interrupt and status register
+ 0x1C
+ 0x20
+ read-only
+ 0x00C0
+
+
+ RENACTF
+ REN active flag
+ 22
+ 1
+
+
+ TENACTF
+ TEN active flag
+ 21
+ 1
+
+
+ WKUPF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RXMSKF
+ Reception mask mode flag
+ 19
+ 1
+
+
+ BRKSF
+ Break frame send flag
+ 18
+ 1
+
+
+ CMF
+ Character match flag
+ 17
+ 1
+
+
+ BUSY
+ Busy flag
+ 16
+ 1
+
+
+ ABRTF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABRTERRF
+ Auto baud rate error flag
+ 14
+ 1
+
+
+ ENDBLKF
+ End of block flag
+ 12
+ 1
+
+
+ ROTF
+ Receiver overtime flag
+ 11
+ 1
+
+
+ CTSF
+ CTS flag
+ 10
+ 1
+
+
+ CTSIF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LINBKF
+ LIN break frame detection flag
+ 8
+ 1
+
+
+ TXE
+ transmit buffer empty flag
+ 7
+ 1
+
+
+ TCF
+ Transmission complete flag
+ 6
+ 1
+
+
+ RXNE
+ receiver buffer not empty
+ flag
+ 5
+ 1
+
+
+ IDLEF
+ Idle frame detected flag
+ 4
+ 1
+
+
+ OVRERRF
+ Reception overflow error
+ flag
+ 3
+ 1
+
+
+ NF
+ Noise flag
+ 2
+ 1
+
+
+ FERRF
+ Frame error flag
+ 1
+ 1
+
+
+ PERRF
+ Parity error flag
+ 0
+ 1
+
+
+
+
+ IFCLR
+ IFCLR
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ WKUPFC
+ Wakeup from Stop mode flag
+ clear
+ 20
+ 1
+
+
+ CMFC
+ Character match flag clear
+ 17
+ 1
+
+
+ ENDBLKFC
+ End of block flag clear
+ 12
+ 1
+
+
+ ROTFC
+ Receiver overtime flag clear
+ 11
+ 1
+
+
+ CTSFC
+ CTS flag clear
+ 9
+ 1
+
+
+ LINBKFC
+ LIN break frame detection flag
+ clear
+ 8
+ 1
+
+
+ TCFC
+ Transmission complete flag
+ clear
+ 6
+ 1
+
+
+ IDLEFC
+ Idle frame detected flag
+ clear
+ 4
+ 1
+
+
+ OVRERRC
+ Overrun error flag clear
+ 3
+ 1
+
+
+ STARTNFC
+ Start bit Noise detected
+ flag clear
+ 2
+ 1
+
+
+ FERRC
+ Frame error flag clear
+ 1
+ 1
+
+
+ PERRC
+ Parity error flag clear
+ 0
+ 1
+
+
+
+
+ RXBUF
+ RXBUF
+ Receive buffer register
+ 0x24
+ 0x20
+ read-only
+ 0x0000
+
+
+ RXBUF
+ Receive buffer
+ 0
+ 9
+
+
+
+
+ TXBUF
+ TXBUF
+ Transmit buffer register
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXBUF
+ Transmit buffer
+ 0
+ 9
+
+
+
+
+
+
+ USART2
+ 0x40004400
+
+ USART2
+ USART2 global interrupt
+ 28
+
+
+
+ TIM15
+ General-purpose-timers
+ TIM
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM15
+ TIM15 global interrupt
+ 20
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ IVO1N
+ Idle value output of channel 1
+ complementary
+ 9
+ 1
+
+
+ IVO1
+ Idle value output of channel 1
+ 8
+ 1
+
+
+ CHDMARS
+ DMA request source of channel
+ 3
+ 1
+
+
+ CHPUS
+ Preload update source of channel
+ 2
+ 1
+
+
+ CHPSEN
+ Preload shadow enable of channel
+ 0
+ 1
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ TDREN
+ Enable bit for trigger
+ DMA request
+ 14
+ 1
+
+
+ CH1DEN
+ Enable bit for channel 1
+ DMA request
+ 9
+ 1
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ BRKINTEN
+ Enable bit for break interrupt
+ 7
+ 1
+
+
+ TINTEN
+ Enable bit for trigger interrupt
+ 6
+ 1
+
+
+ COMINTEN
+ Enable bit for COM event
+ interrupt
+ 5
+ 1
+
+
+ CH1INTEN
+ Enable bit for channel 1
+ interrupt
+ 1
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1ICOF
+ Channel 1 input capture overflow
+ 9
+ 1
+
+
+ BRKIF
+ Interrupt flag of break
+ 7
+ 1
+
+
+ TRIGIF
+ Interrupt flag of trigger
+ 6
+ 1
+
+
+ CHCOMIF
+ channel communication event
+ interrupt flag
+ 5
+ 1
+
+
+ CH1CCIF
+ Channel 1 capture compare interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKEG
+ Break event generation
+ 7
+ 1
+
+
+ TRIGEG
+ Trigger event generation
+ 6
+ 1
+
+
+ COMEG
+ COM event generation
+ 5
+ 1
+
+
+ CH1CCG
+ Channel 1 capture compare event
+ generation
+ 1
+ 1
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CH12CFGR_Output
+ CH12CFGR_Output
+ channel 1 and channel 2 configuration register
+ (output mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1OCMSEL
+ Channel 1 output compare mode selection
+ 4
+ 3
+
+
+ CH1OCVPEN
+ Channel 1 output compare value preload
+ enable
+ 3
+ 1
+
+
+ CH1OCFEN
+ Channel 1 output compare fast
+ enable
+ 2
+ 1
+
+
+ CH1FS
+ Channel 1 function
+ selection
+ 0
+ 2
+
+
+
+
+ CH12CFGR_Input
+ CH12CFGR_Input
+ channel 1 and channel 2 configuration register
+ (input mode)
+ CH12CFGR_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1ICFLT
+ Channel 1 input capture filter
+ 4
+ 4
+
+
+ CH1ICPDIV
+ Channel 1 input capture pre-divide
+ 2
+ 2
+
+
+ CH1FS
+ Channel 1 function selection
+ 0
+ 2
+
+
+
+
+ CCCTR
+ CCCTR
+ channel capture compare control
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NCCP
+ Channel 1 complementary capture compare
+ Polarity
+ 3
+ 1
+
+
+ CH1NCCEN
+ Channel 1 complementary capture compare
+ enable
+ 2
+ 1
+
+
+ CH1CCP
+ Channel 1 capture compare polarity
+ 1
+ 1
+
+
+ CH1CCEN
+ Channel 1 capture compare enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+ UVALREP
+ UVALREP
+ counter update register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALREP
+ counter update repetition value
+ 0
+ 8
+
+
+
+
+ CH1CCVAL
+ CH1CCVAL
+ channel 1 capture compare value register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CCVAL
+ channel 1 capture compare value
+ 0
+ 16
+
+
+
+
+ CHOPR
+ CHOPR
+ output protect register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHOPEN
+ Channel output pad enable
+ 15
+ 1
+
+
+ CHOPAEN
+ Channel output pad auto enable
+ 14
+ 1
+
+
+ BRKPOL
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ RUNOS
+ Run mode off-state control
+ 11
+ 1
+
+
+ IDLEOS
+ Idle mode off-state control
+ 10
+ 1
+
+
+ LCKLV
+ Lock level control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time configuration
+ 0
+ 8
+
+
+
+
+ DMAACR
+ DMAACR
+ DMA access configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATL
+ DMA transfer length
+ 8
+ 5
+
+
+ DMASA
+ DMA start address
+ 0
+ 5
+
+
+
+
+ DMAIR
+ DMAIR
+ DMA access interface register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMAI
+ DMA access interface
+ 0
+ 16
+
+
+
+
+
+
+ TIM16
+ 0x40014400
+
+ TIM16
+ TIM16 global interrupt
+ 21
+
+
+
+ TIM17
+ 0x40014800
+
+ TIM17
+ TIM17 global interrupt
+ 22
+
+
+
+ TIM6
+ General-purpose-timers
+ TIM
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIM6
+ TIM6 global interrupt
+ 17
+
+
+
+ CTR1
+ CTR1
+ control register 1
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ UVALSEN
+ UVAL shadow enable
+ 7
+ 1
+
+
+ SPEN
+ Single pulse enable
+ 3
+ 1
+
+
+ URSEL
+ Update request selection
+ 2
+ 1
+
+
+ UPD
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTR2
+ CTR2
+ control register 2
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMTOC
+ Master mode trigger out control
+ 4
+ 3
+
+
+
+
+ DIEN
+ DIEN
+ DMA and interrupt enable register
+ 0xC
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPDEN
+ Enable bit for update
+ DMA request
+ 8
+ 1
+
+
+ UPINTEN
+ Enable bit for update interrupt
+ 0
+ 1
+
+
+
+
+ STS
+ STS
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPIF
+ Interrupt flag of update
+ 0
+ 1
+
+
+
+
+ SWEGR
+ SWEGR
+ software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UEG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter
+ 0
+ 16
+
+
+
+
+ PDIV
+ PDIV
+ pre-divider
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PDIV
+ pre-divider
+ 0
+ 16
+
+
+
+
+ UVAL
+ UVAL
+ counter update register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ UVAL
+ Counter update value
+ 0
+ 16
+
+
+
+
+
+
+ FMC
+ FLASH Memory Control
+ FMC
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FLASH
+ Flash global interrupt
+ 3
+
+
+
+ WCR
+ WCR
+ Flash access control register
+ 0x0
+ 0x20
+ 0x00000030
+
+
+ WCNT
+ FMC wait conuter
+ 0
+ 3
+ read-write
+
+
+ WE
+ FMC wait enable
+ 4
+ 1
+ read-write
+
+
+ WS
+ FMC wait status
+ 5
+ 1
+ read-only
+
+
+
+
+ CCODE
+ CCODE
+ Control code register
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CCODE
+ Control code
+ 0
+ 32
+
+
+
+
+ OBCCODE
+ OBCCODE
+ Option Byte Control code register
+ 0x8
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OBCCODE
+ Option Byte Control code
+ 0
+ 32
+
+
+
+
+ STS
+ STS
+ status register
+ 0xC
+ 0x20
+ 0x00000000
+
+
+ ENDF
+ End of operation
+ 5
+ 1
+ read-write
+
+
+ WPERR
+ Erase/Program protection error
+ 4
+ 1
+ read-write
+
+
+ PGERR
+ Program error
+ 2
+ 1
+ read-write
+
+
+ BUSY
+ Busy
+ 0
+ 1
+ read-only
+
+
+
+
+ CTR
+ CTR
+ FMC control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ OBUPDATE
+ Update option byte
+ 13
+ 1
+
+
+ ENDIE
+ End of operation interrupt
+ enable
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 10
+ 1
+
+
+ OBWEN
+ Option byte erase/program enable
+ 9
+ 1
+
+
+ LOCK
+ LOCK
+ 7
+ 1
+
+
+ START
+ Start of erase
+ 6
+ 1
+
+
+ OBERS
+ Option byte erase command
+ 5
+ 1
+
+
+ OBPG
+ Option byte programm command
+ 4
+ 1
+
+
+ CHIPERS
+ Main flash CHIP ERASE
+ 2
+ 1
+
+
+ PERS
+ Flash page erase
+ 1
+ 1
+
+
+ PG
+ Main flash program
+ 0
+ 1
+
+
+
+
+ ERSADR
+ ERSADR
+ Flash erase address register
+ 0x14
+ 0x20
+ write-only
+ 0x00000000
+
+
+ ERSADR
+ Flash erase address
+ 0
+ 32
+
+
+
+
+ OBSTS
+ OBSTS
+ Option byte status register
+ 0x1C
+ 0x20
+ read-only
+ 0x03FFFFF2
+
+
+ DATA1
+ DATA1
+ 24
+ 8
+
+
+ DATA0
+ DATA0
+ 16
+ 8
+
+
+ VDDA_DET
+ VDDA_DET
+ 13
+ 1
+
+
+ nBOOT1
+ nBOOT1
+ 12
+ 1
+
+
+ nRST_PWD
+ nRST_PWD
+ 10
+ 1
+
+
+ nRST_DSM
+ nRST_DSM
+ 9
+ 1
+
+
+ FWDT_AO
+ FWDT_AO
+ 8
+ 1
+
+
+ RPROT
+ RPROT
+ 1
+ 2
+
+
+ OBERR
+ Option byte error
+ 0
+ 1
+
+
+
+
+ WPSTS
+ WPSTS
+ Write protection status register
+ 0x20
+ 0x20
+ read-only
+ 0xFFFFFFFF
+
+
+ WPROT0
+ Write protect byte 0
+ 0
+ 8
+
+
+ WPROT1
+ Write protect byte 1
+ 8
+ 8
+
+
+
+
+
+
+ DBG
+ Debug support
+ DBG
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ID
+ ID
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ DEV_ID
+ Device Identifier
+ 0
+ 12
+
+
+ REV_ID
+ Revision identifier
+ 16
+ 16
+
+
+
+
+ LPWCFG
+ LPWCFG
+ Debug support for low power
+ configuration register
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ DSM_DBGEN
+ Debug Deep Sleep Mode
+ 1
+ 1
+
+
+ PWD_DBGEN
+ Debug Down Power Mode
+ 2
+ 1
+
+
+
+
+ APB1CFG
+ APB1CFG
+ Debug support for apb1 peripherals
+ configuration register
+ 0x8
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM2_DBG_PAUSE
+ TIM2 counter paused when system is
+ in debug mode
+ 0
+ 1
+
+
+ TIM3_DBG_PAUSE
+ TIM3 counter paused when system is
+ in debug mode
+ 1
+ 1
+
+
+ TIM6_DBG_PAUSE
+ TIM6 counter paused when system
+ is in debug mode
+ 4
+ 1
+
+
+ TIM14_DBG_PAUSE
+ TIM14 counter when system is in
+ debug mode
+ 8
+ 1
+
+
+ RTC_DBG_PAUSE
+ RTC paused when system is in
+ debug mode
+ 10
+ 1
+
+
+ WWDT_DBG_PAUSE
+ window watchdog paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ FWDT_DBG_PAUSE
+ Free watchdog paused when system
+ is in debug mode
+ 12
+ 1
+
+
+ I2C1_SMBUS_DBG_PAUSE
+ SMBUS timeout counter paused when
+ system is in debug mode
+ 21
+ 1
+
+
+
+
+ APB2CFG
+ APB2CFG
+ Debug support for apb2 peripherals
+ configuration register
+ 0xC
+ 0x20
+ read-write
+ 0x0
+
+
+ TIM1_DBG_PAUSE
+ TIM1 counter paused when system
+ is in debug mode
+ 11
+ 1
+
+
+ TIM15_DBG_PAUSE
+ TIM15 counter paused when system
+ is in debug mode
+ 16
+ 1
+
+
+ TIM16_DBG_PAUSE
+ TIM16 counter paused when system is
+ in debug mode
+ 17
+ 1
+
+
+ TIM17_DBG_PAUSE
+ TIM17 counter paused when system is
+ in debug mode
+ 18
+ 1
+
+
+
+
+
+
+
diff --git a/data/Chipsea/CS32F103xB.svd b/data/Chipsea/CS32F103xB.svd
new file mode 100644
index 0000000..0730188
--- /dev/null
+++ b/data/Chipsea/CS32F103xB.svd
@@ -0,0 +1,70 @@
+
+
Chipsea Ltd.
+
Chipsea
+
CS32F103xB
+
ARMCM3
+
1.2
+
ARM 32-bit Cortex-M3 Microcontroller based device, CPU clock up to 80MHz, etc.
+
+ ARM Limited (ARM) is supplying this software for use with Cortex-M\n
+ processor based microcontroller, but can be equally used for other\n
+ suitable processor architectures. This file can be freely distributed.\n
+ Modifications to this file shall be clearly marked.\n
+ \n
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+
+
+
CM3
+
r1p0
+
little
+
true
+
false
+
3
+
false
+
+
8
+
32
+
+
32
+
read-write
+
0x00000000
+
0xFFFFFFFF
+
+
+
RCU
1.0
Add your description
RCU
0x40021000
32
read-write
0
0x00000400
registers
RCU
RCU global interrupt
5
RCU_CTR
RCU¿ØÖƼĴæÆ÷
0x0
32
read-write
0x00000083
0xFFFFFFFF
PLLSTAB
PLLSTAB
25
1
read-only
PLLEN
PLLEN
24
1
read-write
HXTME
HXTME
19
1
read-write
HXTBPS
HXTBPS
18
1
read-write
HXTSTAB
HXTSTAB
17
1
read-only
HXTEN
HXTEN
16
1
read-write
HRCCALIB
HRCCALIB
8
8
read-only
HRCTRIM
HRCTRIM
3
5
read-write
HRCSTAB
HRCSTAB
1
1
read-only
HRCEN
HRCEN
0
1
read-write
RCU_CFG
RCUÅäÖüĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CKOSEL
CKOSEL
24
3
read-write
USBPDIV
USBPDIV
22
1
read-write
PLLMUF
PLLMUF
18
4
read-write
PLLHXTPDIV
PLLHXTPDIV
17
1
read-write
PLLSEL
PLLSEL
16
1
read-write
ADCPDIV
ADCPDIV
14
2
read-write
HPCLKPDIV
HPCLKPDIV
11
3
read-write
PCLKPDIV
PCLKPDIV
8
3
read-write
HCLKPDIV
HCLKPDIV
4
4
read-write
SYSSS
SYSSS
2
2
read-only
SYSSW
SYSSW
0
2
read-write
RCU_INTR
RCUÖжϼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
CKFAILIC
CKFAILIC
23
1
read-clear by writing 1
PLLSTABIC
PLLSTABIC
20
1
read-clear by writing 1
HXTSTABIC
HXTSTABIC
19
1
read-clear by writing 1
HRCSTABIC
HRCSTABIC
18
1
read-clear by writing 1
LXTSTABIC
LXTSTABIC
17
1
read-clear by writing 1
LRCSTABIC
LRCSTABIC
16
1
read-clear by writing 1
PLLSTABIE
PLLSTABIE
12
1
read-write
HXTSTABIE
HXTSTABIE
11
1
read-write
HRCSTABIE
HRCSTABIE
10
1
read-write
LXTSTABIE
LXTSTABIE
9
1
read-write
LRCSTABIE
LRCSTABIE
8
1
read-write
CKFAILIF
CKFAILIF
7
1
read-only
PLLSTABIF
PLLSTABIF
4
1
read-only
HXTSTABIF
HXTSTABIF
3
1
read-only
HRCSTABIF
HRCSTABIF
2
1
read-only
LXTSTABIF
LXTSTABIF
1
1
read-only
LRCSTABIF
LRCSTABIF
0
1
read-only
RCU_APB2RST
RCU APB2¸´Î»¼Ä´æÆ÷
0xc
32
read-write
0x00000000
0xFFFFFFFF
UASRT1RST
UASRT1RST
14
1
read-write
TIM8RST
TIM8RST
13
1
read-write
SPI1RST
SPI1RST
12
1
read-write
TIM1RST
TIM1RST
11
1
read-write
ADC2RST
ADC2RST
10
1
read-write
ADC1RST
ADC1RST
9
1
read-write
PERST
PERST
6
1
read-write
PDRST
PDRST
5
1
read-write
PCRST
PCRST
4
1
read-write
PBRST
PBRST
3
1
read-write
PARST
PARST
2
1
read-write
AFIORST
AFIORST
0
1
read-write
RCU_APB1RST
RCU APB1¸´Î»¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
PMURST
PMURST
28
1
read-write
BKPRST
BKPRST
27
1
read-write
CANRST
CANRST
25
1
read-write
USBRST
USBRST
23
1
read-write
I2C2RST
I2C2RST
22
1
read-write
I2C1RST
I2C1RST
21
1
read-write
USART3RST
USART3RST
18
1
read-write
USART2RST
USART2RST
17
1
read-write
SPI2RST
SPI2RST
14
1
read-write
WWDTRST
WWDTRST
11
1
read-write
TIM4RST
TIM4RST
2
1
read-write
TIM3RST
TIM3RST
1
1
read-write
TIM2RST
TIM2RST
0
1
read-write
RCU_AHBEN
RCU AHBʱÖÓʹÄܼĴæÆ÷
0x14
32
read-write
0x00000014
0xFFFFFFFF
CRCEN
CRCEN
6
1
read-write
FMCEN
FMCEN
4
1
read-write
RMCEN
RMCEN
2
1
read-write
DMAEN
DMAEN
0
1
read-write
RCU_APB2EN
RCU APB2ʱÖÓʹÄܼĴæÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
USART1EN
USART1EN
14
1
read-write
SPI1EN
SPI1EN
12
1
read-write
TIM1EN
TIM1EN
11
1
read-write
ADC2EN
ADC2EN
10
1
read-write
ADC1EN
ADC1EN
9
1
read-write
PFEN
PFEN
6
1
read-write
PDEN
PDEN
5
1
read-write
PCEN
PCEN
4
1
read-write
PBEN
PBEN
3
1
read-write
PAEN
PAEN
2
1
read-write
AFIOEN
AFIOEN
0
1
read-write
RCU_APB1EN
RCU APB1ʱÖÓʹÄܼĴæÆ÷
0x1C
32
read-write
0x00000000
0xFFFFFFFF
PMUEN
PMUEN
28
1
read-only
BKPEN
BKPEN
27
1
read-write
CANEN
CANEN
25
1
read-write
USBEN
USBEN
23
1
read-write
I2C2EN
I2C2EN
22
1
read-write
I2C1EN
I2C1EN
21
1
read-write
USART3EN
USART3EN
18
1
read-write
USART2EN
USART2EN
17
1
read-write
SPI2EN
SPI2EN
14
1
read-write
WWDTEN
WWDTEN
11
1
read-write
TIM4EN
TIM4EN
2
1
read-write
TIM3EN
TIM3EN
1
1
read-write
TIM2EN
TIM2EN
0
1
read-write
RCU_VBDC
RCU±¸·ÝÓò¿ØÖƼĴæÆ÷
0x20
32
read-write
0x00000000
0xFFFFFFFF
VBTRST
VBTRST
16
1
read-write
RTCCLKEN
RTCCLKEN
15
1
read-write
RTCSRC
RTCSRC
8
2
read-write
LXTBYP
LXTBYP
2
1
read-write
LXTSTAB
LXTSTAB
1
1
read-write
LXTEN
LXTEN
0
1
read-write
RCU_STS
ADC״̬¼Ä´æÆ÷
0x24
32
read-write
0x0C000000
0xFFFFFFFF
LPERSTF
LPERSTF
31
1
read-write
WWDTRSTF
WWDTRSTF
30
1
read-write
FWDTRSTF
FWDTRSTF
29
1
read-write
SWRSTF
SWRSTF
28
1
read-write
PORRSTF
PORRSTF
27
1
read-write
NRSTF
NRSTF
26
1
read-write
CRSTF
CRSTF
24
1
read-write
LRCSTAB
LRCSTAB
1
1
read-write
LRCEN
LRCEN
0
1
read-write
GPIOA
1.0
Add your description
GPIOA
0x40010800
32
read-write
0
0x00000400
registers
CFGL
GPIOÅäÖõͼĴæÆ÷
0x0
32
read-write
0x44444444
0xFFFFFFFF
CFG7
CFG7
30
2
read-write
FUNC7
FUNC7
28
2
read-write
CFG6
CFG6
26
2
read-write
FUNC6
FUNC6
24
2
read-write
CFG5
CFG5
22
2
read-write
FUNC5
FUNC5
20
2
read-write
CFG4
CFG4
18
2
read-write
FUNC4
FUNC4
16
2
read-write
CFG3
CFG3
14
2
read-write
FUNC3
FUNC3
12
2
read-write
CFG2
CFG2
10
2
read-write
FUNC2
FUNC2
8
2
read-write
CFG1
CFG1
6
2
read-write
FUNC1
FUNC1
4
2
read-write
CFG0
CFG0
2
2
read-write
FUNC0
FUNC0
0
2
read-write
CFGH
GPIOÅäÖø߼ĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CFG15
CFG15
30
2
read-write
FUNC15
FUNC15
28
2
read-write
CFG14
CFG14
26
2
read-write
FUNC14
FUNC14
24
2
read-write
CFG13
CFG13
22
2
read-write
FUNC13
FUNC13
20
2
read-write
CFG12
CFG12
18
2
read-write
FUNC12
FUNC12
16
2
read-write
CFG11
CFG11
14
2
read-write
FUNC11
FUNC11
12
2
read-write
CFG10
CFG10
10
2
read-write
FUNC10
FUNC10
8
2
read-write
CFG9
CFG9
6
2
read-write
FUNC9
FUNC9
4
2
read-write
CFG8
CFG8
2
2
read-write
FUNC8
FUNC8
0
2
read-write
DI
¶Ë¿ÚÊäÈëÊý¾Ý¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
DI15
DI15
15
1
read-only
DI14
DI14
14
1
read-only
DI13
DI13
13
1
read-only
DI12
DI12
12
1
read-only
DI11
DI11
11
1
read-only
DI10
DI10
10
1
read-only
DI9
DI9
9
1
read-only
DI8
DI8
8
1
read-only
DI7
DI7
7
1
read-only
DI6
DI6
6
1
read-only
DI5
DI5
5
1
read-only
DI4
DI4
4
1
read-only
DI3
DI3
3
1
read-only
DI2
DI2
2
1
read-only
DI1
DI1
1
1
read-only
DI0
DI0
0
1
read-only
DO
¶Ë¿ÚÊä³öÊý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DO15
DO15
15
1
read-write
DO14
DO14
14
1
read-write
DO13
DO13
13
1
read-write
DO12
DO12
12
1
read-write
DO11
DO11
11
1
read-write
DO10
DO10
10
1
read-write
DO9
DO9
9
1
read-write
DO8
DO8
8
1
read-write
DO7
DO7
7
1
read-write
DO6
DO6
6
1
read-write
DO5
DO5
5
1
read-write
DO4
DO4
4
1
read-write
DO3
DO3
3
1
read-write
DO2
DO2
2
1
read-write
DO1
DO1
1
1
read-write
DO0
DO0
0
1
read-write
SCR
¶Ë¿ÚλÉèÖÃ/Çå³ý¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
BC15
BC15
31
1
write-only
BC14
BC14
30
1
write-only
BC13
BC13
29
1
write-only
BC12
BC12
28
1
write-only
BC11
BC11
27
1
write-only
BC10
BC10
26
1
write-only
BC9
BC9
25
1
write-only
BC8
BC8
24
1
write-only
BC7
BC7
23
1
write-only
BC6
BC6
22
1
write-only
BC5
BC5
21
1
write-only
BC4
BC4
20
1
write-only
BC3
BC3
19
1
write-only
BC2
BC2
18
1
write-only
BC1
BC1
17
1
write-only
BC0
BC0
16
1
write-only
BS15
BS15
15
1
write-only
BS14
BS14
14
1
write-only
BS13
BS13
13
1
write-only
BS12
BS12
12
1
write-only
BS11
BS11
11
1
write-only
BS10
BS10
10
1
write-only
BS9
BS9
9
1
write-only
BS8
BS8
8
1
write-only
BS7
BS7
7
1
write-only
BS6
BS6
6
1
write-only
BS5
BS5
5
1
write-only
BS4
BS4
4
1
write-only
BS3
BS3
3
1
write-only
BS2
BS2
2
1
write-only
BS1
BS1
1
1
write-only
BS0
BS0
0
1
write-only
CLRR
¶Ë¿ÚλÇå³ý¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
BCLR15
BCLR15
15
1
write-only
BCLR14
BCLR14
14
1
write-only
BCLR13
BCLR13
13
1
write-only
BCLR12
BCLR12
12
1
write-only
BCLR11
BCLR11
11
1
write-only
BCLR10
BCLR10
10
1
write-only
BCLR9
BCLR9
9
1
write-only
BCLR8
BCLR8
8
1
write-only
BCLR7
BCLR7
7
1
write-only
BCLR6
BCLR6
6
1
write-only
BCLR5
BCLR5
5
1
write-only
BCLR4
BCLR4
4
1
write-only
BCLR3
BCLR3
3
1
write-only
BCLR2
BCLR2
2
1
write-only
BCLR1
BCLR1
1
1
write-only
BCLR0
BCLR0
0
1
write-only
LOCK
¶Ë¿ÚÅäÖÃËø¶¨¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
LOCK15
LOCK15
15
1
read-write
LOCK14
LOCK14
14
1
read-write
LOCK13
LOCK13
13
1
read-write
LOCK12
LOCK12
12
1
read-write
LOCK11
LOCK11
11
1
read-write
LOCK10
LOCK10
10
1
read-write
LOCK9
LOCK9
9
1
read-write
LOCK8
LOCK8
8
1
read-write
LOCK7
LOCK7
7
1
read-write
LOCK6
LOCK6
6
1
read-write
LOCK5
LOCK5
5
1
read-write
LOCK4
LOCK4
4
1
read-write
LOCK3
LOCK3
3
1
read-write
LOCK2
LOCK2
2
1
read-write
LOCK1
LOCK1
1
1
read-write
LOCK0
LOCK0
0
1
read-write
GPIOB
1.0
Add your description
GPIOB
0x40010C00
32
read-write
0
0x00000400
registers
CFGL
GPIOÅäÖõͼĴæÆ÷
0x0
32
read-write
0x44444444
0xFFFFFFFF
CFG7
CFG7
30
2
read-write
FUNC7
FUNC7
28
2
read-write
CFG6
CFG6
26
2
read-write
FUNC6
FUNC6
24
2
read-write
CFG5
CFG5
22
2
read-write
FUNC5
FUNC5
20
2
read-write
CFG4
CFG4
18
2
read-write
FUNC4
FUNC4
16
2
read-write
CFG3
CFG3
14
2
read-write
FUNC3
FUNC3
12
2
read-write
CFG2
CFG2
10
2
read-write
FUNC2
FUNC2
8
2
read-write
CFG1
CFG1
6
2
read-write
FUNC1
FUNC1
4
2
read-write
CFG0
CFG0
2
2
read-write
FUNC0
FUNC0
0
2
read-write
CFGH
GPIOÅäÖø߼ĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CFG15
CFG15
30
2
read-write
FUNC15
FUNC15
28
2
read-write
CFG14
CFG14
26
2
read-write
FUNC14
FUNC14
24
2
read-write
CFG13
CFG13
22
2
read-write
FUNC13
FUNC13
20
2
read-write
CFG12
CFG12
18
2
read-write
FUNC12
FUNC12
16
2
read-write
CFG11
CFG11
14
2
read-write
FUNC11
FUNC11
12
2
read-write
CFG10
CFG10
10
2
read-write
FUNC10
FUNC10
8
2
read-write
CFG9
CFG9
6
2
read-write
FUNC9
FUNC9
4
2
read-write
CFG8
CFG8
2
2
read-write
FUNC8
FUNC8
0
2
read-write
DI
¶Ë¿ÚÊäÈëÊý¾Ý¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
DI15
DI15
15
1
read-only
DI14
DI14
14
1
read-only
DI13
DI13
13
1
read-only
DI12
DI12
12
1
read-only
DI11
DI11
11
1
read-only
DI10
DI10
10
1
read-only
DI9
DI9
9
1
read-only
DI8
DI8
8
1
read-only
DI7
DI7
7
1
read-only
DI6
DI6
6
1
read-only
DI5
DI5
5
1
read-only
DI4
DI4
4
1
read-only
DI3
DI3
3
1
read-only
DI2
DI2
2
1
read-only
DI1
DI1
1
1
read-only
DI0
DI0
0
1
read-only
DO
¶Ë¿ÚÊä³öÊý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DO15
DO15
15
1
read-write
DO14
DO14
14
1
read-write
DO13
DO13
13
1
read-write
DO12
DO12
12
1
read-write
DO11
DO11
11
1
read-write
DO10
DO10
10
1
read-write
DO9
DO9
9
1
read-write
DO8
DO8
8
1
read-write
DO7
DO7
7
1
read-write
DO6
DO6
6
1
read-write
DO5
DO5
5
1
read-write
DO4
DO4
4
1
read-write
DO3
DO3
3
1
read-write
DO2
DO2
2
1
read-write
DO1
DO1
1
1
read-write
DO0
DO0
0
1
read-write
SCR
¶Ë¿ÚλÉèÖÃ/Çå³ý¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
BC15
BC15
31
1
write-only
BC14
BC14
30
1
write-only
BC13
BC13
29
1
write-only
BC12
BC12
28
1
write-only
BC11
BC11
27
1
write-only
BC10
BC10
26
1
write-only
BC9
BC9
25
1
write-only
BC8
BC8
24
1
write-only
BC7
BC7
23
1
write-only
BC6
BC6
22
1
write-only
BC5
BC5
21
1
write-only
BC4
BC4
20
1
write-only
BC3
BC3
19
1
write-only
BC2
BC2
18
1
write-only
BC1
BC1
17
1
write-only
BC0
BC0
16
1
write-only
BS15
BS15
15
1
write-only
BS14
BS14
14
1
write-only
BS13
BS13
13
1
write-only
BS12
BS12
12
1
write-only
BS11
BS11
11
1
write-only
BS10
BS10
10
1
write-only
BS9
BS9
9
1
write-only
BS8
BS8
8
1
write-only
BS7
BS7
7
1
write-only
BS6
BS6
6
1
write-only
BS5
BS5
5
1
write-only
BS4
BS4
4
1
write-only
BS3
BS3
3
1
write-only
BS2
BS2
2
1
write-only
BS1
BS1
1
1
write-only
BS0
BS0
0
1
write-only
CLRR
¶Ë¿ÚλÇå³ý¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
BCLR15
BCLR15
15
1
write-only
BCLR14
BCLR14
14
1
write-only
BCLR13
BCLR13
13
1
write-only
BCLR12
BCLR12
12
1
write-only
BCLR11
BCLR11
11
1
write-only
BCLR10
BCLR10
10
1
write-only
BCLR9
BCLR9
9
1
write-only
BCLR8
BCLR8
8
1
write-only
BCLR7
BCLR7
7
1
write-only
BCLR6
BCLR6
6
1
write-only
BCLR5
BCLR5
5
1
write-only
BCLR4
BCLR4
4
1
write-only
BCLR3
BCLR3
3
1
write-only
BCLR2
BCLR2
2
1
write-only
BCLR1
BCLR1
1
1
write-only
BCLR0
BCLR0
0
1
write-only
LOCK
¶Ë¿ÚÅäÖÃËø¶¨¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
LOCK15
LOCK15
15
1
read-write
LOCK14
LOCK14
14
1
read-write
LOCK13
LOCK13
13
1
read-write
LOCK12
LOCK12
12
1
read-write
LOCK11
LOCK11
11
1
read-write
LOCK10
LOCK10
10
1
read-write
LOCK9
LOCK9
9
1
read-write
LOCK8
LOCK8
8
1
read-write
LOCK7
LOCK7
7
1
read-write
LOCK6
LOCK6
6
1
read-write
LOCK5
LOCK5
5
1
read-write
LOCK4
LOCK4
4
1
read-write
LOCK3
LOCK3
3
1
read-write
LOCK2
LOCK2
2
1
read-write
LOCK1
LOCK1
1
1
read-write
LOCK0
LOCK0
0
1
read-write
GPIOC
1.0
Add your description
GPIOC
0x40011000
32
read-write
0
0x00000400
registers
CFGL
GPIOÅäÖõͼĴæÆ÷
0x0
32
read-write
0x44444444
0xFFFFFFFF
CFG7
CFG7
30
2
read-write
FUNC7
FUNC7
28
2
read-write
CFG6
CFG6
26
2
read-write
FUNC6
FUNC6
24
2
read-write
CFG5
CFG5
22
2
read-write
FUNC5
FUNC5
20
2
read-write
CFG4
CFG4
18
2
read-write
FUNC4
FUNC4
16
2
read-write
CFG3
CFG3
14
2
read-write
FUNC3
FUNC3
12
2
read-write
CFG2
CFG2
10
2
read-write
FUNC2
FUNC2
8
2
read-write
CFG1
CFG1
6
2
read-write
FUNC1
FUNC1
4
2
read-write
CFG0
CFG0
2
2
read-write
FUNC0
FUNC0
0
2
read-write
CFGH
GPIOÅäÖø߼ĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CFG15
CFG15
30
2
read-write
FUNC15
FUNC15
28
2
read-write
CFG14
CFG14
26
2
read-write
FUNC14
FUNC14
24
2
read-write
CFG13
CFG13
22
2
read-write
FUNC13
FUNC13
20
2
read-write
CFG12
CFG12
18
2
read-write
FUNC12
FUNC12
16
2
read-write
CFG11
CFG11
14
2
read-write
FUNC11
FUNC11
12
2
read-write
CFG10
CFG10
10
2
read-write
FUNC10
FUNC10
8
2
read-write
CFG9
CFG9
6
2
read-write
FUNC9
FUNC9
4
2
read-write
CFG8
CFG8
2
2
read-write
FUNC8
FUNC8
0
2
read-write
DI
¶Ë¿ÚÊäÈëÊý¾Ý¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
DI15
DI15
15
1
read-only
DI14
DI14
14
1
read-only
DI13
DI13
13
1
read-only
DI12
DI12
12
1
read-only
DI11
DI11
11
1
read-only
DI10
DI10
10
1
read-only
DI9
DI9
9
1
read-only
DI8
DI8
8
1
read-only
DI7
DI7
7
1
read-only
DI6
DI6
6
1
read-only
DI5
DI5
5
1
read-only
DI4
DI4
4
1
read-only
DI3
DI3
3
1
read-only
DI2
DI2
2
1
read-only
DI1
DI1
1
1
read-only
DI0
DI0
0
1
read-only
DO
¶Ë¿ÚÊä³öÊý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DO15
DO15
15
1
read-write
DO14
DO14
14
1
read-write
DO13
DO13
13
1
read-write
DO12
DO12
12
1
read-write
DO11
DO11
11
1
read-write
DO10
DO10
10
1
read-write
DO9
DO9
9
1
read-write
DO8
DO8
8
1
read-write
DO7
DO7
7
1
read-write
DO6
DO6
6
1
read-write
DO5
DO5
5
1
read-write
DO4
DO4
4
1
read-write
DO3
DO3
3
1
read-write
DO2
DO2
2
1
read-write
DO1
DO1
1
1
read-write
DO0
DO0
0
1
read-write
SCR
¶Ë¿ÚλÉèÖÃ/Çå³ý¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
BC15
BC15
31
1
write-only
BC14
BC14
30
1
write-only
BC13
BC13
29
1
write-only
BC12
BC12
28
1
write-only
BC11
BC11
27
1
write-only
BC10
BC10
26
1
write-only
BC9
BC9
25
1
write-only
BC8
BC8
24
1
write-only
BC7
BC7
23
1
write-only
BC6
BC6
22
1
write-only
BC5
BC5
21
1
write-only
BC4
BC4
20
1
write-only
BC3
BC3
19
1
write-only
BC2
BC2
18
1
write-only
BC1
BC1
17
1
write-only
BC0
BC0
16
1
write-only
BS15
BS15
15
1
write-only
BS14
BS14
14
1
write-only
BS13
BS13
13
1
write-only
BS12
BS12
12
1
write-only
BS11
BS11
11
1
write-only
BS10
BS10
10
1
write-only
BS9
BS9
9
1
write-only
BS8
BS8
8
1
write-only
BS7
BS7
7
1
write-only
BS6
BS6
6
1
write-only
BS5
BS5
5
1
write-only
BS4
BS4
4
1
write-only
BS3
BS3
3
1
write-only
BS2
BS2
2
1
write-only
BS1
BS1
1
1
write-only
BS0
BS0
0
1
write-only
CLRR
¶Ë¿ÚλÇå³ý¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
BCLR15
BCLR15
15
1
write-only
BCLR14
BCLR14
14
1
write-only
BCLR13
BCLR13
13
1
write-only
BCLR12
BCLR12
12
1
write-only
BCLR11
BCLR11
11
1
write-only
BCLR10
BCLR10
10
1
write-only
BCLR9
BCLR9
9
1
write-only
BCLR8
BCLR8
8
1
write-only
BCLR7
BCLR7
7
1
write-only
BCLR6
BCLR6
6
1
write-only
BCLR5
BCLR5
5
1
write-only
BCLR4
BCLR4
4
1
write-only
BCLR3
BCLR3
3
1
write-only
BCLR2
BCLR2
2
1
write-only
BCLR1
BCLR1
1
1
write-only
BCLR0
BCLR0
0
1
write-only
LOCK
¶Ë¿ÚÅäÖÃËø¶¨¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
LOCK15
LOCK15
15
1
read-write
LOCK14
LOCK14
14
1
read-write
LOCK13
LOCK13
13
1
read-write
LOCK12
LOCK12
12
1
read-write
LOCK11
LOCK11
11
1
read-write
LOCK10
LOCK10
10
1
read-write
LOCK9
LOCK9
9
1
read-write
LOCK8
LOCK8
8
1
read-write
LOCK7
LOCK7
7
1
read-write
LOCK6
LOCK6
6
1
read-write
LOCK5
LOCK5
5
1
read-write
LOCK4
LOCK4
4
1
read-write
LOCK3
LOCK3
3
1
read-write
LOCK2
LOCK2
2
1
read-write
LOCK1
LOCK1
1
1
read-write
LOCK0
LOCK0
0
1
read-write
GPIOD
1.0
Add your description
GPIOD
0x40011400
32
read-write
0
0x00000400
registers
CFGL
GPIOÅäÖõͼĴæÆ÷
0x0
32
read-write
0x44444444
0xFFFFFFFF
CFG7
CFG7
30
2
read-write
FUNC7
FUNC7
28
2
read-write
CFG6
CFG6
26
2
read-write
FUNC6
FUNC6
24
2
read-write
CFG5
CFG5
22
2
read-write
FUNC5
FUNC5
20
2
read-write
CFG4
CFG4
18
2
read-write
FUNC4
FUNC4
16
2
read-write
CFG3
CFG3
14
2
read-write
FUNC3
FUNC3
12
2
read-write
CFG2
CFG2
10
2
read-write
FUNC2
FUNC2
8
2
read-write
CFG1
CFG1
6
2
read-write
FUNC1
FUNC1
4
2
read-write
CFG0
CFG0
2
2
read-write
FUNC0
FUNC0
0
2
read-write
CFGH
GPIOÅäÖø߼ĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CFG15
CFG15
30
2
read-write
FUNC15
FUNC15
28
2
read-write
CFG14
CFG14
26
2
read-write
FUNC14
FUNC14
24
2
read-write
CFG13
CFG13
22
2
read-write
FUNC13
FUNC13
20
2
read-write
CFG12
CFG12
18
2
read-write
FUNC12
FUNC12
16
2
read-write
CFG11
CFG11
14
2
read-write
FUNC11
FUNC11
12
2
read-write
CFG10
CFG10
10
2
read-write
FUNC10
FUNC10
8
2
read-write
CFG9
CFG9
6
2
read-write
FUNC9
FUNC9
4
2
read-write
CFG8
CFG8
2
2
read-write
FUNC8
FUNC8
0
2
read-write
DI
¶Ë¿ÚÊäÈëÊý¾Ý¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
DI15
DI15
15
1
read-only
DI14
DI14
14
1
read-only
DI13
DI13
13
1
read-only
DI12
DI12
12
1
read-only
DI11
DI11
11
1
read-only
DI10
DI10
10
1
read-only
DI9
DI9
9
1
read-only
DI8
DI8
8
1
read-only
DI7
DI7
7
1
read-only
DI6
DI6
6
1
read-only
DI5
DI5
5
1
read-only
DI4
DI4
4
1
read-only
DI3
DI3
3
1
read-only
DI2
DI2
2
1
read-only
DI1
DI1
1
1
read-only
DI0
DI0
0
1
read-only
DO
¶Ë¿ÚÊä³öÊý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DO15
DO15
15
1
read-write
DO14
DO14
14
1
read-write
DO13
DO13
13
1
read-write
DO12
DO12
12
1
read-write
DO11
DO11
11
1
read-write
DO10
DO10
10
1
read-write
DO9
DO9
9
1
read-write
DO8
DO8
8
1
read-write
DO7
DO7
7
1
read-write
DO6
DO6
6
1
read-write
DO5
DO5
5
1
read-write
DO4
DO4
4
1
read-write
DO3
DO3
3
1
read-write
DO2
DO2
2
1
read-write
DO1
DO1
1
1
read-write
DO0
DO0
0
1
read-write
SCR
¶Ë¿ÚλÉèÖÃ/Çå³ý¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
BC15
BC15
31
1
write-only
BC14
BC14
30
1
write-only
BC13
BC13
29
1
write-only
BC12
BC12
28
1
write-only
BC11
BC11
27
1
write-only
BC10
BC10
26
1
write-only
BC9
BC9
25
1
write-only
BC8
BC8
24
1
write-only
BC7
BC7
23
1
write-only
BC6
BC6
22
1
write-only
BC5
BC5
21
1
write-only
BC4
BC4
20
1
write-only
BC3
BC3
19
1
write-only
BC2
BC2
18
1
write-only
BC1
BC1
17
1
write-only
BC0
BC0
16
1
write-only
BS15
BS15
15
1
write-only
BS14
BS14
14
1
write-only
BS13
BS13
13
1
write-only
BS12
BS12
12
1
write-only
BS11
BS11
11
1
write-only
BS10
BS10
10
1
write-only
BS9
BS9
9
1
write-only
BS8
BS8
8
1
write-only
BS7
BS7
7
1
write-only
BS6
BS6
6
1
write-only
BS5
BS5
5
1
write-only
BS4
BS4
4
1
write-only
BS3
BS3
3
1
write-only
BS2
BS2
2
1
write-only
BS1
BS1
1
1
write-only
BS0
BS0
0
1
write-only
CLRR
¶Ë¿ÚλÇå³ý¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
BCLR15
BCLR15
15
1
write-only
BCLR14
BCLR14
14
1
write-only
BCLR13
BCLR13
13
1
write-only
BCLR12
BCLR12
12
1
write-only
BCLR11
BCLR11
11
1
write-only
BCLR10
BCLR10
10
1
write-only
BCLR9
BCLR9
9
1
write-only
BCLR8
BCLR8
8
1
write-only
BCLR7
BCLR7
7
1
write-only
BCLR6
BCLR6
6
1
write-only
BCLR5
BCLR5
5
1
write-only
BCLR4
BCLR4
4
1
write-only
BCLR3
BCLR3
3
1
write-only
BCLR2
BCLR2
2
1
write-only
BCLR1
BCLR1
1
1
write-only
BCLR0
BCLR0
0
1
write-only
LOCK
¶Ë¿ÚÅäÖÃËø¶¨¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
LOCK15
LOCK15
15
1
read-write
LOCK14
LOCK14
14
1
read-write
LOCK13
LOCK13
13
1
read-write
LOCK12
LOCK12
12
1
read-write
LOCK11
LOCK11
11
1
read-write
LOCK10
LOCK10
10
1
read-write
LOCK9
LOCK9
9
1
read-write
LOCK8
LOCK8
8
1
read-write
LOCK7
LOCK7
7
1
read-write
LOCK6
LOCK6
6
1
read-write
LOCK5
LOCK5
5
1
read-write
LOCK4
LOCK4
4
1
read-write
LOCK3
LOCK3
3
1
read-write
LOCK2
LOCK2
2
1
read-write
LOCK1
LOCK1
1
1
read-write
LOCK0
LOCK0
0
1
read-write
GPIOE
1.0
Add your description
GPIOE
0x40011800
32
read-write
0
0x00000400
registers
CFGL
GPIOÅäÖõͼĴæÆ÷
0x0
32
read-write
0x44444444
0xFFFFFFFF
CFG7
CFG7
30
2
read-write
FUNC7
FUNC7
28
2
read-write
CFG6
CFG6
26
2
read-write
FUNC6
FUNC6
24
2
read-write
CFG5
CFG5
22
2
read-write
FUNC5
FUNC5
20
2
read-write
CFG4
CFG4
18
2
read-write
FUNC4
FUNC4
16
2
read-write
CFG3
CFG3
14
2
read-write
FUNC3
FUNC3
12
2
read-write
CFG2
CFG2
10
2
read-write
FUNC2
FUNC2
8
2
read-write
CFG1
CFG1
6
2
read-write
FUNC1
FUNC1
4
2
read-write
CFG0
CFG0
2
2
read-write
FUNC0
FUNC0
0
2
read-write
CFGH
GPIOÅäÖø߼ĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CFG15
CFG15
30
2
read-write
FUNC15
FUNC15
28
2
read-write
CFG14
CFG14
26
2
read-write
FUNC14
FUNC14
24
2
read-write
CFG13
CFG13
22
2
read-write
FUNC13
FUNC13
20
2
read-write
CFG12
CFG12
18
2
read-write
FUNC12
FUNC12
16
2
read-write
CFG11
CFG11
14
2
read-write
FUNC11
FUNC11
12
2
read-write
CFG10
CFG10
10
2
read-write
FUNC10
FUNC10
8
2
read-write
CFG9
CFG9
6
2
read-write
FUNC9
FUNC9
4
2
read-write
CFG8
CFG8
2
2
read-write
FUNC8
FUNC8
0
2
read-write
DI
¶Ë¿ÚÊäÈëÊý¾Ý¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
DI15
DI15
15
1
read-only
DI14
DI14
14
1
read-only
DI13
DI13
13
1
read-only
DI12
DI12
12
1
read-only
DI11
DI11
11
1
read-only
DI10
DI10
10
1
read-only
DI9
DI9
9
1
read-only
DI8
DI8
8
1
read-only
DI7
DI7
7
1
read-only
DI6
DI6
6
1
read-only
DI5
DI5
5
1
read-only
DI4
DI4
4
1
read-only
DI3
DI3
3
1
read-only
DI2
DI2
2
1
read-only
DI1
DI1
1
1
read-only
DI0
DI0
0
1
read-only
DO
¶Ë¿ÚÊä³öÊý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DO15
DO15
15
1
read-write
DO14
DO14
14
1
read-write
DO13
DO13
13
1
read-write
DO12
DO12
12
1
read-write
DO11
DO11
11
1
read-write
DO10
DO10
10
1
read-write
DO9
DO9
9
1
read-write
DO8
DO8
8
1
read-write
DO7
DO7
7
1
read-write
DO6
DO6
6
1
read-write
DO5
DO5
5
1
read-write
DO4
DO4
4
1
read-write
DO3
DO3
3
1
read-write
DO2
DO2
2
1
read-write
DO1
DO1
1
1
read-write
DO0
DO0
0
1
read-write
SCR
¶Ë¿ÚλÉèÖÃ/Çå³ý¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
BC15
BC15
31
1
write-only
BC14
BC14
30
1
write-only
BC13
BC13
29
1
write-only
BC12
BC12
28
1
write-only
BC11
BC11
27
1
write-only
BC10
BC10
26
1
write-only
BC9
BC9
25
1
write-only
BC8
BC8
24
1
write-only
BC7
BC7
23
1
write-only
BC6
BC6
22
1
write-only
BC5
BC5
21
1
write-only
BC4
BC4
20
1
write-only
BC3
BC3
19
1
write-only
BC2
BC2
18
1
write-only
BC1
BC1
17
1
write-only
BC0
BC0
16
1
write-only
BS15
BS15
15
1
write-only
BS14
BS14
14
1
write-only
BS13
BS13
13
1
write-only
BS12
BS12
12
1
write-only
BS11
BS11
11
1
write-only
BS10
BS10
10
1
write-only
BS9
BS9
9
1
write-only
BS8
BS8
8
1
write-only
BS7
BS7
7
1
write-only
BS6
BS6
6
1
write-only
BS5
BS5
5
1
write-only
BS4
BS4
4
1
write-only
BS3
BS3
3
1
write-only
BS2
BS2
2
1
write-only
BS1
BS1
1
1
write-only
BS0
BS0
0
1
write-only
CLRR
¶Ë¿ÚλÇå³ý¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
BCLR15
BCLR15
15
1
write-only
BCLR14
BCLR14
14
1
write-only
BCLR13
BCLR13
13
1
write-only
BCLR12
BCLR12
12
1
write-only
BCLR11
BCLR11
11
1
write-only
BCLR10
BCLR10
10
1
write-only
BCLR9
BCLR9
9
1
write-only
BCLR8
BCLR8
8
1
write-only
BCLR7
BCLR7
7
1
write-only
BCLR6
BCLR6
6
1
write-only
BCLR5
BCLR5
5
1
write-only
BCLR4
BCLR4
4
1
write-only
BCLR3
BCLR3
3
1
write-only
BCLR2
BCLR2
2
1
write-only
BCLR1
BCLR1
1
1
write-only
BCLR0
BCLR0
0
1
write-only
LOCK
¶Ë¿ÚÅäÖÃËø¶¨¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
LOCK15
LOCK15
15
1
read-write
LOCK14
LOCK14
14
1
read-write
LOCK13
LOCK13
13
1
read-write
LOCK12
LOCK12
12
1
read-write
LOCK11
LOCK11
11
1
read-write
LOCK10
LOCK10
10
1
read-write
LOCK9
LOCK9
9
1
read-write
LOCK8
LOCK8
8
1
read-write
LOCK7
LOCK7
7
1
read-write
LOCK6
LOCK6
6
1
read-write
LOCK5
LOCK5
5
1
read-write
LOCK4
LOCK4
4
1
read-write
LOCK3
LOCK3
3
1
read-write
LOCK2
LOCK2
2
1
read-write
LOCK1
LOCK1
1
1
read-write
LOCK0
LOCK0
0
1
read-write
CAN1
1.0
Add your description
CAN
0x40006400
32
read-write
0
0x00000400
registers
CAN1_TX
CAN1 TX interrupts
19
CAN1_RX0
CAN1 RX0 interrupts
20
CAN1_RX1
CAN1 RX1 interrupts
21
CAN1_SCE
CAN1 SCE interrupt
22
MCTR
CANÖ÷¿ØÖƼĴæÆ÷
0x0
32
read-write
0x00010002
0xFFFFFFFF
DBGW
DBGW
16
1
read-write
SOFTRST
SOFTRST
15
1
read-write
TTCEN
TTCEN
7
1
read-write
AUTOFFM
AUTOFFM
6
1
read-write
AUTOATV
AUTOATV
5
1
read-write
NAUTORT
NAUTORT
4
1
read-write
RFOWRM
RFOWRM
3
1
read-write
TXFP
TXFP
2
1
read-write
SLEEP
SLEEP
1
1
read-write
INRQ
INRQ
0
1
read-write
MSTS
CANÖ÷״̬¼Ä´æÆ÷
0x4
32
read-write
0x00000C02
0xFFFFFFFF
RPS
RPS
11
1
read-write
LSAMP
LSAMP
10
1
read-write
RXM
RXM
9
1
read-write
TXM
TXM
8
1
read-write
SEI
SEI
4
1
read-write
WKUI
WKUI
3
1
read-write
ERI
ERI
2
1
read-write
SLEEPF
SLEEPF
1
1
read-write
INITF
INITF
0
1
read-write
TXSTS
CAN·¢ËÍ״̬¼Ä´æÆ÷
0x8
32
read-write
0x1C000000
0xFFFFFFFF
LOWM2
LOWM2
31
1
read-only
LOWM1
LOWM1
30
1
read-only
LOWM0
LOWM0
29
1
read-only
TXME2
TXME2
28
1
read-only
TXME1
TXME1
27
1
read-only
TXME0
TXME0
26
1
read-only
MNUM
MNUM
24
2
read-only
MATXRQ2
MATXRQ2
23
1
read-set
MTXERR2
MTXERR2
19
1
read-clear by writing 1
MAL2
MAL2
18
1
read-clear by writing 1
MTXSU2
MTXSU2
17
1
read-clear by writing 1
MRQCP2
MRQCP2
16
1
read-clear by writing 1
MATXRQ1
MATXRQ1
15
1
read-set
MTXERR1
MTXERR1
11
1
read-clear by writing 1
MAL1
MAL1
10
1
read-clear by writing 1
MTXSU1
MTXSU1
9
1
read-clear by writing 1
MRQCP1
MRQCP1
8
1
read-clear by writing 1
MATXRQ0
MATXRQ0
7
1
read-clear by writing 1
MTXERR0
MTXERR0
3
1
read-clear by writing 1
MAL0
MAL0
2
1
read-clear by writing 1
MTXSU0
MTXSU0
1
1
read-clear by writing 1
MRQCP0
MRQCP0
0
1
read-clear by writing 1
RXFF0
CAN½ÓÊÕFIFO0¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
RFOM0
RFOM0
5
1
read-set
FIFOOVR0
FIFOOVR0
4
1
read-clear by writing 1
FIFOF0
FIFOF0
3
1
read-clear by writing 1
FIFOMP0
FIFOMP0
0
2
read-only
RXFF1
CAN½ÓÊÕFIFO1¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
RFOM1
RFOM1
5
1
read-set
FIFOOVR1
FIFOOVR1
4
1
read-clear by writing 1
FIFOF1
FIFOF1
3
1
read-clear by writing 1
FIFOMP1
FIFOMP1
0
2
read-only
INTR
CANÖжÏʹÄܼĴæÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
SLEEPIE
SLEEPIE
17
1
read-write
WKUPIE
WKUPIE
16
1
read-write
ERRIE
ERRIE
15
1
read-write
LENIE
LENIE
11
1
read-write
BOFIE
BOFIE
10
1
read-write
EPSSIE
EPSSIE
9
1
read-write
EWIE
EWIE
8
1
read-write
FFOVRIE1
FFOVRIE1
7
1
read-write
FFUIE1
FFUIE1
6
1
read-write
FFMPIE1
FFMPIE1
5
1
read-write
FFOVRIE0
FFOVRIE0
4
1
read-write
FFUIE0
FFUIE0
3
1
read-write
FFMPIE0
FFMPIE0
1
1
read-write
TXEIE
TXEIE
0
1
read-write
ERRSTS
CAN´íÎó״̬¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
RFC
RFC
24
8
read-only
TEC
TEC
16
8
read-only
LEC
LEC
4
3
read-write
BOFF
BOFF
2
1
read-only
ERRPF
ERRPF
1
1
read-only
ERRWF
ERRWF
0
1
read-only
BTM
CANʱÐò¼Ä´æÆ÷
0x1C
32
read-write
0x01230000
0xFFFFFFFF
SLEM
SLEM
31
1
read-write
LPBM
LPBM
30
1
read-write
RBCTW
RBCTW
24
2
read-write
TS2
TS2
20
3
read-write
TS1
TS1
16
4
read-write
BRPDIV
BRPDIV
0
10
read-write
TXMI0
·¢ËÍÓÊÏä±êʶ·û¼Ä´æÆ÷0
0x180
32
read-write
0x00000000
0xFFFFFFFF
STD_EXTID
STD_EXTID
21
11
read-write
EXTID
EXTID
3
18
read-write
SESEL
SESEL
2
1
read-write
RTRQ
RTRQ
1
1
read-write
TRQ
TRQ
0
1
read-write
TXMI1
·¢ËÍÓÊÏä±êʶ·û¼Ä´æÆ÷1
0x190
32
read-write
0x00000000
0xFFFFFFFF
STD_EXTID
STD_EXTID
21
11
read-write
EXTID
EXTID
3
18
read-write
SESEL
SESEL
2
1
read-write
RTRQ
RTRQ
1
1
read-write
TRQ
TRQ
0
1
read-write
TXMI2
·¢ËÍÓÊÏä±êʶ·û¼Ä´æÆ÷2
0x1A0
32
read-write
0x00000000
0xFFFFFFFF
STD_EXTID
STD_EXTID
21
11
read-write
EXTID
EXTID
3
18
read-write
SESEL
SESEL
2
1
read-write
RTRQ
RTRQ
1
1
read-write
TRQ
TRQ
0
1
read-write
TXLT0
·¢ËÍÓÊÏäÊý¾Ý³¤¶ÈºÍʱ¼ä´Á¼Ä´æÆ÷0
0x184
32
read-write
0x00000000
0xFFFFFFFF
TIMES
TIMES
16
16
read-write
TTS
TTS
8
1
read-write
TDL
TDL
0
4
read-write
TXLT1
·¢ËÍÓÊÏäÊý¾Ý³¤¶ÈºÍʱ¼ä´Á¼Ä´æÆ÷1
0x194
32
read-write
0x00000000
0xFFFFFFFF
TIMES
TIMES
16
16
read-write
TTS
TTS
8
1
read-write
TDL
TDL
0
4
read-write
TXLT2
·¢ËÍÓÊÏäÊý¾Ý³¤¶ÈºÍʱ¼ä´Á¼Ä´æÆ÷2
0x1A4
32
read-write
0x00000000
0xFFFFFFFF
TIMES
TIMES
16
16
read-write
TTS
TTS
8
1
read-write
TDL
TDL
0
4
read-write
TXDL0
·¢ËÍÓÊÏäµÍ×Ö½ÚÊý¾Ý¼Ä´æÆ÷0
0x188
32
read-write
0x00000000
0xFFFFFFFF
DATA3
DATA3
24
8
read-write
DATA2
DATA2
16
8
read-write
DATA1
DATA1
8
8
read-write
DATA0
DATA0
0
8
read-write
TXDL1
·¢ËÍÓÊÏäµÍ×Ö½ÚÊý¾Ý¼Ä´æÆ÷1
0x198
32
read-write
0x00000000
0xFFFFFFFF
DATA3
DATA3
24
8
read-write
DATA2
DATA2
16
8
read-write
DATA1
DATA1
8
8
read-write
DATA0
DATA0
0
8
read-write
TXDL2
·¢ËÍÓÊÏäµÍ×Ö½ÚÊý¾Ý¼Ä´æÆ÷2
0x1A8
32
read-write
0x00000000
0xFFFFFFFF
DATA3
DATA3
24
8
read-write
DATA2
DATA2
16
8
read-write
DATA1
DATA1
8
8
read-write
DATA0
DATA0
0
8
read-write
TXDH0
·¢ËÍÓÊÏä¸ß×Ö½ÚÊý¾Ý¼Ä´æÆ÷0
0x18C
32
read-write
0x00000000
0xFFFFFFFF
DATA7
DATA7
24
8
read-write
DATA6
DATA6
16
8
read-write
DATA5
DATA5
8
8
read-write
DATA4
DATA4
0
8
read-write
TXDH1
·¢ËÍÓÊÏä¸ß×Ö½ÚÊý¾Ý¼Ä´æÆ÷1
0x19C
32
read-write
0x00000000
0xFFFFFFFF
DATA7
DATA7
24
8
read-write
DATA6
DATA6
16
8
read-write
DATA5
DATA5
8
8
read-write
DATA4
DATA4
0
8
read-write
TXDH2
·¢ËÍÓÊÏä¸ß×Ö½ÚÊý¾Ý¼Ä´æÆ÷2
0x1AC
32
read-write
0x00000000
0xFFFFFFFF
DATA7
DATA7
24
8
read-write
DATA6
DATA6
16
8
read-write
DATA5
DATA5
8
8
read-write
DATA4
DATA4
0
8
read-write
RFFID0
½ÓÊÕFIFOÓÊÏä±êʶ¼Ä´æÆ÷0
0x1B0
32
read-write
0x00000000
0xFFFFFFFF
STD_EXTID
STD_EXTID
24
8
read-write
EXTID
EXTID
16
8
read-write
SESEL
SESEL
8
8
read-write
RTRQ
RTRQ
0
8
read-write
RFFID1
½ÓÊÕFIFOÓÊÏä±êʶ¼Ä´æÆ÷1
0x1C0
32
read-write
0x00000000
0xFFFFFFFF
STD_EXTID
STD_EXTID
24
8
read-write
EXTID
EXTID
16
8
read-write
SESEL
SESEL
8
8
read-write
RTRQ
RTRQ
0
8
read-write
RXLT0
½ÓÊÕFIFOÓÊÏäÊý¾Ý³¤¶ÈºÍʱ¼ä´Á¼Ä´æÆ÷0
0x1B4
32
read-write
0x00000000
0xFFFFFFFF
TIMES
TIMES
16
16
read-only
ICCTR
ICCTR
8
8
read-only
RDL
RDL
0
4
read-only
RXLT1
½ÓÊÕFIFOÓÊÏäÊý¾Ý³¤¶ÈºÍʱ¼ä´Á¼Ä´æÆ÷1
0x1C4
32
read-write
0x00000000
0xFFFFFFFF
TIMES
TIMES
16
16
read-only
ICCTR
ICCTR
8
8
read-only
RDL
RDL
0
4
read-only
RXDL0
½ÓÊÕFIFOÓÊÏäµÍ×ֽڼĴæÆ÷0
0x1B8
32
read-write
0x00000000
0xFFFFFFFF
DATA3
DATA3
24
8
read-only
DATA2
DATA2
16
8
read-only
DATA1
DATA1
8
8
read-only
DATA0
DATA0
0
8
read-only
RXDL1
½ÓÊÕFIFOÓÊÏäµÍ×ֽڼĴæÆ÷1
0x1C8
32
read-write
0x00000000
0xFFFFFFFF
DATA3
DATA3
24
8
read-only
DATA2
DATA2
16
8
read-only
DATA1
DATA1
8
8
read-only
DATA0
DATA0
0
8
read-only
RXDH0
½ÓÊÕFIFOÓÊÏä¸ß×ֽڼĴæÆ÷0
0x1BC
32
read-write
0x00000000
0xFFFFFFFF
DATA7
DATA7
24
8
read-only
DATA6
DATA6
16
8
read-only
DATA5
DATA5
8
8
read-only
DATA4
DATA4
0
8
read-only
RXDH1
½ÓÊÕFIFOÓÊÏä¸ß×ֽڼĴæÆ÷1
0x1CC
32
read-write
0x00000000
0xFFFFFFFF
DATA7
DATA7
24
8
read-only
DATA6
DATA6
16
8
read-only
DATA5
DATA5
8
8
read-only
DATA4
DATA4
0
8
read-only
FLTM
¹ýÂËÆ÷Ö÷¼Ä´æÆ÷
0x200
32
read-write
0x2A1C0E01
0xFFFFFFFF
FWKM
FWKM
0
1
read-write
FMOD
¹ýÂËÆ÷ģʽ¼Ä´æÆ÷
0x204
32
read-write
0x00000000
0xFFFFFFFF
FM13
FM13
13
1
read-write
FM12
FM12
12
1
read-write
FM11
FM11
11
1
read-write
FM10
FM10
10
1
read-write
FM9
FM9
9
1
read-write
FM8
FM8
8
1
read-write
FM7
FM7
7
1
read-write
FM6
FM6
6
1
read-write
FM5
FM5
5
1
read-write
FM4
FM4
4
1
read-write
FM3
FM3
3
1
read-write
FM2
FM2
2
1
read-write
FM1
FM1
1
1
read-write
FM0
FM0
0
1
read-write
FBW
¹ýÂËÆ÷λ¿í¼Ä´æÆ÷
0x20C
32
read-write
0x00000000
0xFFFFFFFF
FBC13
FBC13
13
1
read-write
FBC12
FBC12
12
1
read-write
FBC11
FBC11
11
1
read-write
FBC10
FBC10
10
1
read-write
FBC9
FBC9
9
1
read-write
FBC8
FBC8
8
1
read-write
FBC7
FBC7
7
1
read-write
FBC6
FBC6
6
1
read-write
FBC5
FBC5
5
1
read-write
FBC4
FBC4
4
1
read-write
FBC3
FBC3
3
1
read-write
FBC2
FBC2
2
1
read-write
FBC1
FBC1
1
1
read-write
FBC0
FBC0
0
1
read-write
FLTFA
¹ýÂËÆ÷FIFO¹ØÁª¼Ä´æÆ÷
0x214
32
read-write
0x00000000
0xFFFFFFFF
FFA13
FFA13
13
1
read-write
FFA12
FFA12
12
1
read-write
FFA11
FFA11
11
1
read-write
FFA10
FFA10
10
1
read-write
FFA9
FFA9
9
1
read-write
FFA8
FFA8
8
1
read-write
FFA7
FFA7
7
1
read-write
FFA6
FFA6
6
1
read-write
FFA5
FFA5
5
1
read-write
FFA4
FFA4
4
1
read-write
FFA3
FFA3
3
1
read-write
FFA2
FFA2
2
1
read-write
FFA1
FFA1
1
1
read-write
FFA0
FFA0
0
1
read-write
FAS
¹ýÂËÆ÷¼¤»î¼Ä´æÆ÷
0x21C
32
read-write
0x00000000
0xFFFFFFFF
FAS13
FAS13
13
1
read-write
FAS12
FAS12
12
1
read-write
FAS11
FAS11
11
1
read-write
FAS10
FAS10
10
1
read-write
FAS9
FAS9
9
1
read-write
FAS8
FAS8
8
1
read-write
FAS7
FAS7
7
1
read-write
FAS6
FAS6
6
1
read-write
FAS5
FAS5
5
1
read-write
FAS4
FAS4
4
1
read-write
FAS3
FAS3
3
1
read-write
FAS2
FAS2
2
1
read-write
FAS1
FAS1
1
1
read-write
FAS0
FAS0
0
1
read-write
F0B1
Filter bank 0 register 1
0x240
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F0B2
Filter bank 0 register 2
0x244
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F1B1
Filter bank 1 register 1
0x248
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F1B2
Filter bank 1 register 2
0x24C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F2B1
Filter bank 2 register 1
0x250
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F2B2
Filter bank 2 register 2
0x254
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F3B1
Filter bank 3 register 1
0x258
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F3B2
Filter bank 3 register 2
0x25C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F4B1
Filter bank 4 register 1
0x260
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F4B2
Filter bank 4 register 2
0x264
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F5B1
Filter bank 5 register 1
0x268
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F5B2
Filter bank 5 register 2
0x26C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F6B1
Filter bank 6 register 1
0x270
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F6B2
Filter bank 6 register 2
0x274
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F7B1
Filter bank 7 register 1
0x278
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F7B2
Filter bank 7 register 2
0x27C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F8B1
Filter bank 8 register 1
0x280
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F8B2
Filter bank 8 register 2
0x284
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F9B1
Filter bank 9 register 1
0x288
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F9B2
Filter bank 9 register 2
0x28C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F10B1
Filter bank 10 register 1
0x290
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F10B2
Filter bank 10 register 2
0x294
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F11B1
Filter bank 11 register 1
0x298
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F11B2
Filter bank 11 register 2
0x29C
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F12B1
Filter bank 12 register 1
0x2A0
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
F12B2
Filter bank 12 register 2
0x2A4
32
read-write
0x00000000
0xFFFFFFFF
FB13_0
FB13_0
0
14
read-write
TIM1
1.0
Add your description
TIM
0x40012C00
32
read-write
0
0x00000400
registers
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global interrupt
24
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10 global interrupt
25
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation interrupts and
+ TIM11 global interrupt
26
TIM1_CC
TIM1 Capture Compare interrupt
27
CTR1
TIM1 control register 1
0x0
32
read-write
0x00000000
0xFFFFFFFF
CKDIV
CKDIV
8
2
read-write
UVALSEN
UVALSEN
7
1
read-write
CPS
CPS
5
2
read-write
DIR
DIR
4
1
read-write
SPEN
SPEN
3
1
read-write
URSEL
URSEL
2
1
read-write
UPD
UPD
1
1
read-write
CEN
CEN
0
1
read-write
CTR2
TIM1 control register 2
0x4
32
read-write
0x00000000
0xFFFFFFFF
IVO4
IVO4
14
1
read-write
IVO3N
IVO3N
13
1
read-write
IVO3
IVO3
12
1
read-write
IVO2N
IVO2N
11
1
read-write
IVO2
IVO2
10
1
read-write
IVO1N
IVO1N
9
1
read-write
IVO1
IVO1
8
1
read-write
TI1XOR
TI1XOR
7
1
read-write
MMTOC
MMTOC
4
3
read-write
CHDMARS
CHDMARS
3
1
read-write
CHPUS
CHPUS
2
1
read-write
CHPSEN
CHPSEN
0
1
read-write
SMCFG
TIM1 slave mode configuration register
0x8
32
read-write
0x00000000
0xFFFFFFFF
ETRINV
ETRINV
15
1
read-write
ECMODE2
ECMODE2
14
1
read-write
ETPDIV
ETPDIV
12
2
read-write
ETFLT
ETFLT
8
4
read-write
MSM
MSM
7
1
read-write
TRIGS
TRIGS
4
3
read-write
SMCFG
SMCFG
0
3
read-write
DIEN
DMA/interrupt register
0xc
32
read-write
0x00000000
0xFFFFFFFF
TDREN
TDREN
14
1
read-write
COMDEN
COMDEN
13
1
read-write
CH4DEN
CH4DEN
12
1
read-write
CH3DEN
CH3DEN
11
1
read-write
CH2DEN
CH2DEN
10
1
read-write
CH1DEN
CH1DEN
9
1
read-write
UPDEN
UPDEN
8
1
read-write
BRKINTEN
BRKINTEN
7
1
read-write
TINTEN
TINTEN
6
1
read-write
COMINTEN
COMINTEN
5
1
read-write
CH4INTEN
CH4INTEN
4
1
read-write
CH3INTEN
CH3INTEN
3
1
read-write
CH2INTEN
CH2INTEN
2
1
read-write
CH1INTEN
CH1INTEN
1
1
read-write
UPINTEN
UPINTEN
0
1
read-write
STS
TIM1 status register
0x10
32
read-write
0x00000000
0xFFFFFFFF
CH4ICOF
CH4ICOF
12
1
read-write
CH3ICOF
CH3ICOF
11
1
read-write
CH2ICOF
CH2ICOF
10
1
read-write
CH1ICOF
CH1ICOF
9
1
read-write
BRKIF
BRKIF
7
1
read-write
TRIGIF
TRIGIF
6
1
read-write
CHCOMIF
CHCOMIF
5
1
read-write
CH4CCIF
CH4CCIF
4
1
read-write
CH3CCIF
CH3CCIF
3
1
read-write
CH2CCIF
CH2CCIF
2
1
read-write
CH1CCIF
CH1CCIF
1
1
read-write
UPIF
UPIF
0
1
read-write
SWEGR
TIM1 software event generation register
0x14
32
read-write
0x00000000
0xFFFFFFFF
BRKEG
BRKEG
7
1
read-write
TRIGEG
TRIGEG
6
1
read-write
COMEG
COMEG
5
1
read-write
CH4CCG
CH4CCG
4
1
read-write
CH3CCG
CH3CCG
3
1
read-write
CH2CCG
CH2CCG
2
1
read-write
CH1CCG
CH1CCG
1
1
read-write
UEG
UEG
0
1
read-write
CH12CFG_OUTPUT
TIM1 channel 1 and channel 2 output configuration register
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2OCCEN
CH2OCCEN
15
1
read-write
CH2OCMSEL
CH2OCMSEL
12
3
read-write
CH2OCVPEN
CH2OCVPEN
11
1
read-write
CH2OCFEN
CH2OCFEN
10
1
read-write
CH2FS
CH2FS
8
2
read-write
CH1OCCEN
CH1OCCEN
7
1
read-write
CH1OCMSEL
CH1OCMSEL
4
3
read-write
CH1OCVPEN
CH1OCVPEN
3
1
read-write
CH1OCFEN
CH1OCFEN
2
1
read-write
CH1FS
CH1FS
0
2
read-write
CH12CFG_INPUT
TIM1 channel 1 and channel 2 input configuration register
CH12CFG_OUTPUT
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2ICFLT
CH2ICFLT
12
4
read-write
CH2ICPDIV
CH2ICPDIV
10
2
read-write
CH2FS
CH2FS
8
2
read-write
CH1ICFLT
CH1ICFLT
4
4
read-write
CH1ICPDIV
CH1ICPDIV
2
2
read-write
CH1FS
CH1FS
0
2
read-write
CH34CFG_OUTPUT
TIM1 channel 3 and channel 4 output configuration register
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4OCCEN
CH4OCCEN
15
1
read-write
CH4OCMSEL
CH4OCMSEL
12
3
read-write
CH4OCVPEN
CH4OCVPEN
11
1
read-write
CH4OCFEN
CH4OCFEN
10
1
read-write
CH4FS
CH4FS
8
2
read-write
CH3OCCEN
CH3OCCEN
7
1
read-write
CH3OCMSEL
CH3OCMSEL
4
3
read-write
CH3OCVPEN
CH3OCVPEN
3
1
read-write
CH3OCFEN
CH3OCFEN
2
1
read-write
CH3FS
CH3FS
0
2
read-write
CH34CFG_INPUT
TIM1 channel 3 and channel 4 input configuration register
CH34CFG_OUTPUT
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4ICFLT
CH4ICFLT
12
4
read-write
CH4ICPDIV
CH4ICPDIV
10
2
read-write
CH4FS
CH4FS
8
2
read-write
CH3ICFLT
CH3ICFLT
4
4
read-write
CH3ICPDIV
CH3ICPDIV
2
2
read-write
CH3FS
CH3FS
0
2
read-write
CCCTR
TIM1 channel capture compare control register
0x20
32
read-write
0x00000000
0xFFFFFFFF
CH4CCP
CH4CCP
13
1
read-write
CH4CCEN
CH4CCEN
12
1
read-write
CH3NCCP
CH3NCCP
11
1
read-write
CH3NCCEN
CH3NCCEN
10
1
read-write
CH3CCP
CH3CCP
9
1
read-write
CH3CCEN
CH3CCEN
8
1
read-write
CH2NCCP
CH2NCCP
7
1
read-write
CH2NCCEN
CH2NCCEN
6
1
read-write
CH2CCP
CH2CCP
5
1
read-write
CH2CCEN
CH2CCEN
4
1
read-write
CH1NCCP
CH1NCCP
3
1
read-write
CH1NCCEN
CH1NCCEN
2
1
read-write
CH1CCP
CH1CCP
1
1
read-write
CH1CCEN
CH1CCEN
0
1
read-write
CNT
TIM1 counter
0x24
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
PDIV
TIM1 pre-divider
0x28
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
16
read-write
UVAL
TIM1 counter update register
0x2c
32
read-write
0x00000000
0xFFFFFFFF
UVAL
UVAL
0
16
read-write
UVALREP
TIM1 counter update repetition register
0x30
32
read-write
0x00000000
0xFFFFFFFF
UVALREP
UVALREP
0
8
read-write
CH1CCVAL
TIM1 channel 1 capture compare value register
0x34
32
read-write
0x00000000
0xFFFFFFFF
CH1CCVAL
CH1CCVAL
0
16
read-write
CH2CCVAL
TIM1 channel 2 capture compare value register
0x38
32
read-write
0x00000000
0xFFFFFFFF
CH2CCVAL
CH2CCVAL
0
16
read-write
CH3CCVAL
TIM1 channel 3 capture compare value register
0x3c
32
read-write
0x00000000
0xFFFFFFFF
CH3CCVAL
CH3CCVAL
0
16
read-write
CH4CCVAL
TIM1 channel 4 capture compare value register
0x40
32
read-write
0x00000000
0xFFFFFFFF
CH4CCVAL
CH4CCVAL
0
16
read-write
CHOPR
TIM1 channel output protect register
0x44
32
read-write
0x00000000
0xFFFFFFFF
CHOPEN
CHOPEN
15
1
read-write
CHOPAEN
CHOPAEN
14
1
read-write
BRKPOL
BRKPOL
13
1
read-write
BRKEN
BRKEN
12
1
read-write
RUNOS
RUNOS
11
1
read-write
IDLEOS
IDLEOS
10
1
read-write
LCKLV
LCKLV
8
2
read-write
DTCFG
DTCFG
0
8
read-write
DMAACR
TIM1 DMA access configuration register
0x48
32
read-write
0x00000000
0xFFFFFFFF
DMATL
DMATL
8
5
read-write
DMASA
DMASA
0
5
read-write
DMAIR
TIM1 DMA access interface register
0x4c
32
read-write
0x00000000
0xFFFFFFFF
DMAI
DMAI
0
16
read-write
TIM2
1.0
Add your description
TIM
0x40000000
32
read-write
0
0x00000400
registers
TIM2
TIM2 global interrupt
28
CTR1
TIM2¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x00000000
0xFFFFFFFF
CKDIV
CKDIV
8
2
read-write
UVALSEN
UVALSEN
7
1
read-write
CPS
CPS
5
2
read-write
DIR
DIR
4
1
read-write
SPEN
SPEN
3
1
read-write
URSEL
URSEL
2
1
read-write
UPD
UPD
1
1
read-write
CEN
CEN
0
1
read-write
CTR2
TIM2¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x00000000
0xFFFFFFFF
TI1XOR
TI1XOR
7
1
read-write
MMTOC
MMTOC
4
3
read-write
CHDMARS
CHDMARS
3
1
read-write
SMCFG
TIM2´ÓģʽÅäÖüĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
ETRINV
ETRINV
15
1
read-write
ECMODE2
ECMODE2
14
1
read-write
ETPDIV
ETPDIV
12
2
read-write
ETFLT
ETFLT
8
4
read-write
MSM
MSM
7
1
read-write
TRIGS
TRIGS
4
3
read-write
SMCFG
SMCFG
0
3
read-write
DIEN
DMAºÍÖжÏÇëÇóʹÄܼĴæÆ÷
0xc
32
read-write
0x00000000
0xFFFFFFFF
TDREN
TDREN
14
1
read-write
CH4DEN
CH4DEN
12
1
read-write
CH3DEN
CH3DEN
11
1
read-write
CH2DEN
CH2DEN
10
1
read-write
CH1DEN
CH1DEN
9
1
read-write
UPDEN
UPDEN
8
1
read-write
TINTEN
TINTEN
6
1
read-write
CH4INTEN
CH4INTEN
4
1
read-write
CH3INTEN
CH3INTEN
3
1
read-write
CH2INTEN
CH2INTEN
2
1
read-write
CH1INTEN
CH1INTEN
1
1
read-write
UPINTEN
UPINTEN
0
1
read-write
STS
TIM2 ״̬¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
CH4ICOF
CH4ICOF
12
1
read-write
CH3ICOF
CH3ICOF
11
1
read-write
CH2ICOF
CH2ICOF
10
1
read-write
CH1ICOF
CH1ICOF
9
1
read-write
TRIGIF
TRIGIF
6
1
read-write
CH4CCIF
CH4CCIF
4
1
read-write
CH3CCIF
CH3CCIF
3
1
read-write
CH2CCIF
CH2CCIF
2
1
read-write
CH1CCIF
CH1CCIF
1
1
read-write
UPIF
UPIF
0
1
read-write
SWEGR
TIM2 Èí¼þʼþÉú³É¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
TRIGEG
TRIGEG
6
1
read-write
CH4CCG
CH4CCG
4
1
read-write
CH3CCG
CH3CCG
3
1
read-write
CH2CCG
CH2CCG
2
1
read-write
CH1CCG
CH1CCG
1
1
read-write
UEG
UEG
0
1
read-write
CH12CFG_OUTPUT
TIM2 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2OCCEN
CH2OCCEN
15
1
read-write
CH2OCMSEL
CH2OCMSEL
12
3
read-write
CH2OCVPEN
CH2OCVPEN
11
1
read-write
CH2OCFEN
CH2OCFEN
10
1
read-write
CH2FS
CH2FS
8
2
read-write
CH1OCCEN
CH1OCCEN
7
1
read-write
CH1OCMSEL
CH1OCMSEL
4
3
read-write
CH1OCVPEN
CH1OCVPEN
3
1
read-write
CH1OCFEN
CH1OCFEN
2
1
read-write
CH1FS
CH1FS
0
2
read-write
CH12CFG_INPUT
TIM2 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
CH12CFG_OUTPUT
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2ICFLT
CH2ICFLT
12
4
read-write
CH2ICPDIV
CH2ICPDIV
10
2
read-write
CH2FS
CH2FS
8
2
read-write
CH1ICFLT
CH1ICFLT
4
4
read-write
CH1ICPDIV
CH1ICPDIV
2
2
read-write
CH1FS
CH1FS
0
2
read-write
CH34CFG_OUTPUT
TIM2 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4OCCEN
CH4OCCEN
15
1
read-write
CH4OCMSEL
CH4OCMSEL
12
3
read-write
CH4OCVPEN
CH4OCVPEN
11
1
read-write
CH4OCFEN
CH4OCFEN
10
1
read-write
CH4FS
CH4FS
8
2
read-write
CH3OCCEN
CH3OCCEN
7
1
read-write
CH3OCMSEL
CH3OCMSEL
4
3
read-write
CH3OCVPEN
CH3OCVPEN
3
1
read-write
CH3OCFEN
CH3OCFEN
2
1
read-write
CH3FS
CH3FS
0
2
read-write
CH34CFG_INPUT
TIM2 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
CH34CFG_OUTPUT
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4ICFLT
CH4ICFLT
12
4
read-write
CH4ICPDIV
CH4ICPDIV
10
2
read-write
CH4FS
CH4FS
8
2
read-write
CH3ICFLT
CH3ICFLT
4
4
read-write
CH3ICPDIV
CH3ICPDIV
2
2
read-write
CH3FS
CH3FS
0
2
read-write
CCCTR
TIM2ͨµÀ²¶»ñ±È½Ï¿ØÖƼĴæÆ÷
0x20
32
read-write
0x00000000
0xFFFFFFFF
CH4CCP
CH4CCP
13
1
read-write
CH4CCEN
CH4CCEN
12
1
read-write
CH3CCP
CH3CCP
9
1
read-write
CH3CCEN
CH3CCEN
8
1
read-write
CH2CCP
CH2CCP
5
1
read-write
CH2CCEN
CH2CCEN
4
1
read-write
CH1CCP
CH1CCP
1
1
read-write
CH1CCEN
CH1CCEN
0
1
read-write
CNT
TIM2¼ÆÊýÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
PDIV
TIM2Ô¤·ÖƵ
0x28
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
16
read-write
UVAL
TIM2¼ÆÊýÆ÷¸üмĴæÆ÷
0x2c
32
read-write
0x00000000
0xFFFFFFFF
UVAL
UVAL
0
16
read-write
CH1CCVAL
TIM2ͨµÀ1²¶»ñ±È½Ï¼Ä´æÆ÷
0x34
32
read-write
0x00000000
0xFFFFFFFF
CH1CCVAL
CH1CCVAL
0
16
read-write
CH2CCVAL
TIM2ͨµÀ2²¶»ñ±È½Ï¼Ä´æÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
CH2CCVAL
CH2CCVAL
0
16
read-write
CH3CCVAL
TIM2ͨµÀ3²¶»ñ±È½Ï¼Ä´æÆ÷
0x3c
32
read-write
0x00000000
0xFFFFFFFF
CH3CCVAL
CH3CCVAL
0
16
read-write
CH4CCVAL
TIM2ͨµÀ4²¶»ñ±È½Ï¼Ä´æÆ÷
0x40
32
read-write
0x00000000
0xFFFFFFFF
CH4CCVAL
CH4CCVAL
0
16
read-write
DMAACR
TIM2 DMA¶ÁдÅäÖüĴæÆ÷
0x48
32
read-write
0x00000000
0xFFFFFFFF
DMATL
DMATL
8
5
read-write
DMASA
DMASA
0
5
read-write
DMAIR
TIM2 DMA½Ó¿Ú¼Ä´æÆ÷
0x4c
32
read-write
0x00000000
0xFFFFFFFF
DMAI
DMAI
0
16
read-write
TIM3
1.0
Add your description
TIM
0x40000400
32
read-write
0
0x00000400
registers
TIM3
TIM3 global interrupt
29
CTR1
TIM3¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x00000000
0xFFFFFFFF
CKDIV
CKDIV
8
2
read-write
UVALSEN
UVALSEN
7
1
read-write
CPS
CPS
5
2
read-write
DIR
DIR
4
1
read-write
SPEN
SPEN
3
1
read-write
URSEL
URSEL
2
1
read-write
UPD
UPD
1
1
read-write
CEN
CEN
0
1
read-write
CTR2
TIM3¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x00000000
0xFFFFFFFF
TI1XOR
TI1XOR
7
1
read-write
MMTOC
MMTOC
4
3
read-write
CHDMARS
CHDMARS
3
1
read-write
SMCFG
TIM3´ÓģʽÅäÖüĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
ETRINV
ETRINV
15
1
read-write
ECMODE2
ECMODE2
14
1
read-write
ETPDIV
ETPDIV
12
2
read-write
ETFLT
ETFLT
8
4
read-write
MSM
MSM
7
1
read-write
TRIGS
TRIGS
4
3
read-write
SMCFG
SMCFG
0
3
read-write
DIEN
DMAºÍÖжÏÇëÇóʹÄܼĴæÆ÷
0xc
32
read-write
0x00000000
0xFFFFFFFF
TDREN
TDREN
14
1
read-write
CH4DEN
CH4DEN
12
1
read-write
CH3DEN
CH3DEN
11
1
read-write
CH2DEN
CH2DEN
10
1
read-write
CH1DEN
CH1DEN
9
1
read-write
UPDEN
UPDEN
8
1
read-write
TINTEN
TINTEN
6
1
read-write
CH4INTEN
CH4INTEN
4
1
read-write
CH3INTEN
CH3INTEN
3
1
read-write
CH2INTEN
CH2INTEN
2
1
read-write
CH1INTEN
CH1INTEN
1
1
read-write
UPINTEN
UPINTEN
0
1
read-write
STS
TIM3 ״̬¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
CH4ICOF
CH4ICOF
12
1
read-write
CH3ICOF
CH3ICOF
11
1
read-write
CH2ICOF
CH2ICOF
10
1
read-write
CH1ICOF
CH1ICOF
9
1
read-write
TRIGIF
TRIGIF
6
1
read-write
CH4CCIF
CH4CCIF
4
1
read-write
CH3CCIF
CH3CCIF
3
1
read-write
CH2CCIF
CH2CCIF
2
1
read-write
CH1CCIF
CH1CCIF
1
1
read-write
UPIF
UPIF
0
1
read-write
SWEGR
TIM3 Èí¼þʼþÉú³É¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
TRIGEG
TRIGEG
6
1
read-write
CH4CCG
CH4CCG
4
1
read-write
CH3CCG
CH3CCG
3
1
read-write
CH2CCG
CH2CCG
2
1
read-write
CH1CCG
CH1CCG
1
1
read-write
UEG
UEG
0
1
read-write
CH12CFG_OUTPUT
TIM3 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2OCCEN
CH2OCCEN
15
1
read-write
CH2OCMSEL
CH2OCMSEL
12
3
read-write
CH2OCVPEN
CH2OCVPEN
11
1
read-write
CH2OCFEN
CH2OCFEN
10
1
read-write
CH2FS
CH2FS
8
2
read-write
CH1OCCEN
CH1OCCEN
7
1
read-write
CH1OCMSEL
CH1OCMSEL
4
3
read-write
CH1OCVPEN
CH1OCVPEN
3
1
read-write
CH1OCFEN
CH1OCFEN
2
1
read-write
CH1FS
CH1FS
0
2
read-write
CH12CFG_INPUT
TIM3 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
CH12CFG_OUTPUT
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2ICFLT
CH2ICFLT
12
4
read-write
CH2ICPDIV
CH2ICPDIV
10
2
read-write
CH2FS
CH2FS
8
2
read-write
CH1ICFLT
CH1ICFLT
4
4
read-write
CH1ICPDIV
CH1ICPDIV
2
2
read-write
CH1FS
CH1FS
0
2
read-write
CH34CFG_OUTPUT
TIM3 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4OCCEN
CH4OCCEN
15
1
read-write
CH4OCMSEL
CH4OCMSEL
12
3
read-write
CH4OCVPEN
CH4OCVPEN
11
1
read-write
CH4OCFEN
CH4OCFEN
10
1
read-write
CH4FS
CH4FS
8
2
read-write
CH3OCCEN
CH3OCCEN
7
1
read-write
CH3OCMSEL
CH3OCMSEL
4
3
read-write
CH3OCVPEN
CH3OCVPEN
3
1
read-write
CH3OCFEN
CH3OCFEN
2
1
read-write
CH3FS
CH3FS
0
2
read-write
CH34CFG_INPUT
TIM3 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
CH34CFG_OUTPUT
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4ICFLT
CH4ICFLT
12
4
read-write
CH4ICPDIV
CH4ICPDIV
10
2
read-write
CH4FS
CH4FS
8
2
read-write
CH3ICFLT
CH3ICFLT
4
4
read-write
CH3ICPDIV
CH3ICPDIV
2
2
read-write
CH3FS
CH3FS
0
2
read-write
CCCTR
TIM3ͨµÀ²¶»ñ±È½Ï¿ØÖƼĴæÆ÷
0x20
32
read-write
0x00000000
0xFFFFFFFF
CH4CCP
CH4CCP
13
1
read-write
CH4CCEN
CH4CCEN
12
1
read-write
CH3CCP
CH3CCP
9
1
read-write
CH3CCEN
CH3CCEN
8
1
read-write
CH2CCP
CH2CCP
5
1
read-write
CH2CCEN
CH2CCEN
4
1
read-write
CH1CCP
CH1CCP
1
1
read-write
CH1CCEN
CH1CCEN
0
1
read-write
CNT
TIM3¼ÆÊýÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
PDIV
TIM3Ô¤·ÖƵ
0x28
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
16
read-write
UVAL
TIM3¼ÆÊýÆ÷¸üмĴæÆ÷
0x2c
32
read-write
0x00000000
0xFFFFFFFF
UVAL
UVAL
0
16
read-write
CH1CCVAL
TIM3ͨµÀ1²¶»ñ±È½Ï¼Ä´æÆ÷
0x34
32
read-write
0x00000000
0xFFFFFFFF
CH1CCVAL
CH1CCVAL
0
16
read-write
CH2CCVAL
TIM3ͨµÀ2²¶»ñ±È½Ï¼Ä´æÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
CH2CCVAL
CH2CCVAL
0
16
read-write
CH3CCVAL
TIM3ͨµÀ3²¶»ñ±È½Ï¼Ä´æÆ÷
0x3c
32
read-write
0x00000000
0xFFFFFFFF
CH3CCVAL
CH3CCVAL
0
16
read-write
CH4CCVAL
TIM3ͨµÀ4²¶»ñ±È½Ï¼Ä´æÆ÷
0x40
32
read-write
0x00000000
0xFFFFFFFF
CH4CCVAL
CH4CCVAL
0
16
read-write
DMAACR
TIM3 DMA¶ÁдÅäÖüĴæÆ÷
0x48
32
read-write
0x00000000
0xFFFFFFFF
DMATL
DMATL
8
5
read-write
DMASA
DMASA
0
5
read-write
DMAIR
TIM3 DMA½Ó¿Ú¼Ä´æÆ÷
0x4c
32
read-write
0x00000000
0xFFFFFFFF
DMAI
DMAI
0
16
read-write
TIM4
1.0
Add your description
TIM
0x40000800
32
read-write
0
0x00000400
registers
TIM4
TIM4 global interrupt
30
CTR1
TIM4¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x00000000
0xFFFFFFFF
CKDIV
CKDIV
8
2
read-write
UVALSEN
UVALSEN
7
1
read-write
CPS
CPS
5
2
read-write
DIR
DIR
4
1
read-write
SPEN
SPEN
3
1
read-write
URSEL
URSEL
2
1
read-write
UPD
UPD
1
1
read-write
CEN
CEN
0
1
read-write
CTR2
TIM4¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x00000000
0xFFFFFFFF
TI1XOR
TI1XOR
7
1
read-write
MMTOC
MMTOC
4
3
read-write
CHDMARS
CHDMARS
3
1
read-write
SMCFG
TIM4´ÓģʽÅäÖüĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
ETRINV
ETRINV
15
1
read-write
ECMODE2
ECMODE2
14
1
read-write
ETPDIV
ETPDIV
12
2
read-write
ETFLT
ETFLT
8
4
read-write
MSM
MSM
7
1
read-write
TRIGS
TRIGS
4
3
read-write
SMCFG
SMCFG
0
3
read-write
DIEN
DMAºÍÖжÏÇëÇóʹÄܼĴæÆ÷
0xc
32
read-write
0x00000000
0xFFFFFFFF
TDREN
TDREN
14
1
read-write
CH4DEN
CH4DEN
12
1
read-write
CH3DEN
CH3DEN
11
1
read-write
CH2DEN
CH2DEN
10
1
read-write
CH1DEN
CH1DEN
9
1
read-write
UPDEN
UPDEN
8
1
read-write
TINTEN
TINTEN
6
1
read-write
CH4INTEN
CH4INTEN
4
1
read-write
CH3INTEN
CH3INTEN
3
1
read-write
CH2INTEN
CH2INTEN
2
1
read-write
CH1INTEN
CH1INTEN
1
1
read-write
UPINTEN
UPINTEN
0
1
read-write
STS
TIM4 ״̬¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
CH4ICOF
CH4ICOF
12
1
read-write
CH3ICOF
CH3ICOF
11
1
read-write
CH2ICOF
CH2ICOF
10
1
read-write
CH1ICOF
CH1ICOF
9
1
read-write
TRIGIF
TRIGIF
6
1
read-write
CH4CCIF
CH4CCIF
4
1
read-write
CH3CCIF
CH3CCIF
3
1
read-write
CH2CCIF
CH2CCIF
2
1
read-write
CH1CCIF
CH1CCIF
1
1
read-write
UPIF
UPIF
0
1
read-write
SWEGR
TIM4 Èí¼þʼþÉú³É¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
TRIGEG
TRIGEG
6
1
read-write
CH4CCG
CH4CCG
4
1
read-write
CH3CCG
CH3CCG
3
1
read-write
CH2CCG
CH2CCG
2
1
read-write
CH1CCG
CH1CCG
1
1
read-write
UEG
UEG
0
1
read-write
CH12CFG_OUTPUT
TIM4 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2OCCEN
CH2OCCEN
15
1
read-write
CH2OCMSEL
CH2OCMSEL
12
3
read-write
CH2OCVPEN
CH2OCVPEN
11
1
read-write
CH2OCFEN
CH2OCFEN
10
1
read-write
CH2FS
CH2FS
8
2
read-write
CH1OCCEN
CH1OCCEN
7
1
read-write
CH1OCMSEL
CH1OCMSEL
4
3
read-write
CH1OCVPEN
CH1OCVPEN
3
1
read-write
CH1OCFEN
CH1OCFEN
2
1
read-write
CH1FS
CH1FS
0
2
read-write
CH12CFG_INPUT
TIM4 ͨµÀ1ºÍͨµÀ2ÅäÖüĴæÆ÷
CH12CFG_OUTPUT
0x18
32
read-write
0x00000000
0xFFFFFFFF
CH2ICFLT
CH2ICFLT
12
4
read-write
CH2ICPDIV
CH2ICPDIV
10
2
read-write
CH2FS
CH2FS
8
2
read-write
CH1ICFLT
CH1ICFLT
4
4
read-write
CH1ICPDIV
CH1ICPDIV
2
2
read-write
CH1FS
CH1FS
0
2
read-write
CH34CFG_OUTPUT
TIM4 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4OCCEN
CH4OCCEN
15
1
read-write
CH4OCMSEL
CH4OCMSEL
12
3
read-write
CH4OCVPEN
CH4OCVPEN
11
1
read-write
CH4OCFEN
CH4OCFEN
10
1
read-write
CH4FS
CH4FS
8
2
read-write
CH3OCCEN
CH3OCCEN
7
1
read-write
CH3OCMSEL
CH3OCMSEL
4
3
read-write
CH3OCVPEN
CH3OCVPEN
3
1
read-write
CH3OCFEN
CH3OCFEN
2
1
read-write
CH3FS
CH3FS
0
2
read-write
CH34CFG_INPUT
TIM4 ͨµÀ3ºÍͨµÀ4ÅäÖüĴæÆ÷
CH34CFG_OUTPUT
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CH4ICFLT
CH4ICFLT
12
4
read-write
CH4ICPDIV
CH4ICPDIV
10
2
read-write
CH4FS
CH4FS
8
2
read-write
CH3ICFLT
CH3ICFLT
4
4
read-write
CH3ICPDIV
CH3ICPDIV
2
2
read-write
CH3FS
CH3FS
0
2
read-write
CCCTR
TIM4ͨµÀ²¶»ñ±È½Ï¿ØÖƼĴæÆ÷
0x20
32
read-write
0x00000000
0xFFFFFFFF
CH4CCP
CH4CCP
13
1
read-write
CH4CCEN
CH4CCEN
12
1
read-write
CH3CCP
CH3CCP
9
1
read-write
CH3CCEN
CH3CCEN
8
1
read-write
CH2CCP
CH2CCP
5
1
read-write
CH2CCEN
CH2CCEN
4
1
read-write
CH1CCP
CH1CCP
1
1
read-write
CH1CCEN
CH1CCEN
0
1
read-write
CNT
TIM4¼ÆÊýÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
PDIV
TIM4Ô¤·ÖƵ
0x28
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
16
read-write
UVAL
TIM4¼ÆÊýÆ÷¸üмĴæÆ÷
0x2c
32
read-write
0x00000000
0xFFFFFFFF
UVAL
UVAL
0
16
read-write
CH1CCVAL
TIM4ͨµÀ1²¶»ñ±È½Ï¼Ä´æÆ÷
0x34
32
read-write
0x00000000
0xFFFFFFFF
CH1CCVAL
CH1CCVAL
0
16
read-write
CH2CCVAL
TIM4ͨµÀ2²¶»ñ±È½Ï¼Ä´æÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
CH2CCVAL
CH2CCVAL
0
16
read-write
CH3CCVAL
TIM4ͨµÀ3²¶»ñ±È½Ï¼Ä´æÆ÷
0x3c
32
read-write
0x00000000
0xFFFFFFFF
CH3CCVAL
CH3CCVAL
0
16
read-write
CH4CCVAL
TIM4ͨµÀ4²¶»ñ±È½Ï¼Ä´æÆ÷
0x40
32
read-write
0x00000000
0xFFFFFFFF
CH4CCVAL
CH4CCVAL
0
16
read-write
DMAACR
TIM4 DMA¶ÁдÅäÖüĴæÆ÷
0x48
32
read-write
0x00000000
0xFFFFFFFF
DMATL
DMATL
8
5
read-write
DMASA
DMASA
0
5
read-write
DMAIR
TIM4 DMA½Ó¿Ú¼Ä´æÆ÷
0x4c
32
read-write
0x00000000
0xFFFFFFFF
DMAI
DMAI
0
16
read-write
RTC
1.0
Add your description
RTC
0x40002800
32
read-write
0
0x00000400
registers
RTC
RTC global interrupt
3
RTCAlarm
RTC Alarms through EXTI line interrupt
41
ICTR
RTCÖжϿØÖƼĴæÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
OVRIE
OVRIE
2
1
read-write
ALRIE
ALRIE
1
1
read-write
SCIE
SCIE
0
1
read-write
STS
RTC״̬¼Ä´æÆ÷
0x4
32
read-write
0x00000020
0xFFFFFFFF
RTCOCF
RTCOCF
5
1
read-write
CMF
CMF
4
1
read-write
RSF
RSF
3
1
read-write
OVRF
OVRF
2
1
read-write
ALRF
ALRF
1
1
read-write
SCF
SCF
0
1
read-write
PDIVLH
RTCÔ¤·ÖƵװÔؼĴæÆ÷¸ßλ
0x8
32
read-write
0x00000000
0xFFFFFFFF
PDIVL
PDIVL
0
4
write-only
PDIVLL
RTCÔ¤·ÖƵװÔؼĴæÆ÷µÍλ
0xc
32
read-write
0x00000000
0xFFFFFFFF
PDIVL
PDIVL
0
16
write-only
PDIVH
RTCÔ¤·ÖƵֵ¼Ä´æÆ÷¸ßλ
0x10
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
4
read-only
PDIVL
RTCÔ¤·ÖƵֵ¼Ä´æÆ÷µÍλ
0x14
32
read-write
0x00008000
0xFFFFFFFF
PDIV
PDIV
0
16
read-only
CNTRH
RTC¼ÆÊýÆ÷Öµ¼Ä´æÆ÷¸ßλ
0x18
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
CNTRL
RTC¼ÆÊýÆ÷Öµ¼Ä´æÆ÷µÍλ
0x1c
32
read-write
0x00000000
0xFFFFFFFF
CNT
CNT
0
16
read-write
ALRH
RTCÄÖÖÓÖµ¼Ä´æÆ÷¸ßλ
0x20
32
read-write
0x0000FFFF
0xFFFFFFFF
ALR
ALR
0
16
write-only
ALRL
RTCÄÖÖÓÖµ¼Ä´æÆ÷µÍλ
0x24
32
read-write
0x0000FFFF
0xFFFFFFFF
ALR
ALR
0
16
write-only
BKP
1.0
Add your description
BKP
0x40006C00
32
read-write
0
0x00000400
registers
AO1
²»µôµç¼Ä´æÆ÷1
0x04
32
read-write
0x00000000
0xFFFFFFFF
AO1
AO1
0
16
read-write
AO2
²»µôµç¼Ä´æÆ÷2
0x08
32
read-write
0x00000000
0xFFFFFFFF
AO2
AO2
0
16
read-write
AO3
²»µôµç¼Ä´æÆ÷3
0x0c
32
read-write
0x00000000
0xFFFFFFFF
AO3
AO3
0
16
read-write
AO4
²»µôµç¼Ä´æÆ÷4
0x10
32
read-write
0x00000000
0xFFFFFFFF
AO4
AO4
0
16
read-write
AO5
²»µôµç¼Ä´æÆ÷5
0x14
32
read-write
0x00000000
0xFFFFFFFF
AO5
AO5
0
16
read-write
AO6
²»µôµç¼Ä´æÆ÷6
0x18
32
read-write
0x00000000
0xFFFFFFFF
AO6
AO6
0
16
read-write
AO7
²»µôµç¼Ä´æÆ÷7
0x1c
32
read-write
0x00000000
0xFFFFFFFF
AO7
AO7
0
16
read-write
AO8
²»µôµç¼Ä´æÆ÷8
0x20
32
read-write
0x00000000
0xFFFFFFFF
AO8
AO8
0
16
read-write
AO9
²»µôµç¼Ä´æÆ÷9
0x24
32
read-write
0x00000000
0xFFFFFFFF
AO9
AO9
0
16
read-write
AO10
²»µôµç¼Ä´æÆ÷10
0x28
32
read-write
0x00000000
0xFFFFFFFF
AO10
AO10
0
16
read-write
CCR
RTCʱÖÓУ׼¼Ä´æÆ÷
0x2c
32
read-write
0x00000000
0xFFFFFFFF
ALMSOS
ALMSOS
9
1
read-write
ALMSOEN
ALMSOEN
8
1
read-write
CALCO
CALCO
7
1
read-write
CALDATA
CALDATA
0
7
read-write
CTR
Backup¿ØÖƼĴæÆ÷
0x30
32
read-write
0x00000000
0xFFFFFFFF
TAMPPA
TAMPPA
1
1
read-write
TAMPPEN
TAMPPEN
0
1
read-write
CSR
BKP¿ØÖÆ״̬¼Ä´æÆ÷
0x34
32
read-write
0x00000000
0xFFFFFFFF
TAMPIF
TAMPIF
9
1
read-write
TAMPEF
TAMPEF
8
1
read-write
TAMPIE
TAMPIE
2
1
read-write
TAMPIFCLR
TAMPIFCLR
1
1
read-write
TAMPECLR
TAMPECLR
0
1
read-write
ADC1
1.0
Add your description
ADC
0x40012400
32
read-write
0
0x00000400
registers
ADC
ADC1 global interrupt
18
STS
ADC1״̬¼Ä´æÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
STRTF
STRTF
4
1
read-clear by writing 0
JSTRTF
JSTRTF
3
1
read-clear by writing 0
EOJCH
EOJCH
2
1
read-clear by writing 0
EOCH
EOCH
1
1
read-clear by writing 0
WDEVT
WDEVT
0
1
read-clear by writing 0
CTR1
ADC1¿ØÖƼĴæÆ÷1
0x4
32
read-write
0x00000000
0xFFFFFFFF
WDGEN
WDGEN
23
1
read-write
AWDJCHEN
AWDJCHEN
22
1
read-write
DMS
DMS
16
4
read-write
DISCCHCNT
DISCCHCNT
13
3
read-write
JDISCEN
JDISCEN
12
1
read-write
DISCEN
DISCEN
11
1
read-write
JAUTOC
JAUTOC
10
1
read-write
AWDSGLEN
AWDSGLEN
9
1
read-write
SCANMD
SCANMD
8
1
read-write
JEOCIE
JEOCIE
7
1
read-write
WDEVTIE
WDEVTIE
6
1
read-write
EOCIE
EOCIE
5
1
read-write
WDGCHAN
WDGCHAN
0
5
read-write
CTR
ADC1ͨÓÿØÖƼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
TSVRFEN
TSVRFEN
23
1
read-write
START
START
22
1
read-write
JSTART
JSTART
21
1
read-write
EXTTRG
EXTTRG
20
1
read-write
EVTS
EVTS
17
3
read-write
JEXTTRG
JEXTTRG
15
1
read-write
JEVTS
JEVTS
12
3
read-write
DALGN
DALGN
11
1
read-write
DMAEN
DMAEN
8
1
read-write
RSTCALB
RSTCALB
3
1
read-write
CALB
CALB
2
1
read-write
GCONT
GCONT
1
1
read-write
ADCON
ADCON
0
1
read-write
SMPR1
ADC1²ÉÑùʱ¼äÅäÖÃ1
0xc
32
read-write
0x00000000
0xFFFFFFFF
SMPLTx
SMPLTx
0
24
read-write
SMPR2
ADC1²ÉÑùʱ¼äÅäÖÃ2
0x10
32
read-write
0x00000000
0xFFFFFFFF
SMPLTx
SMPLTx
0
30
read-write
JOFT1
ADC1×¢ÈëͨµÀoffset¼Ä´æÆ÷1
0x14
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT2
ADC1×¢ÈëͨµÀoffset¼Ä´æÆ÷2
0x18
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT3
ADC1×¢ÈëͨµÀoffset¼Ä´æÆ÷3
0x1c
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT4
ADC1×¢ÈëͨµÀoffset¼Ä´æÆ÷4
0x20
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
WDTH
Ä£Äâ¿´ÃŹ·ãÐÖµ¼Ä´æÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
HITH
HITH
0
12
read-write
WDTL
Ä£Äâ¿´ÃŹ·ãÐÖµ¼Ä´æÆ÷
0x28
32
read-write
0x00000000
0xFFFFFFFF
LOTH
LOTH
0
12
read-write
SQR1
ADC1ÐòÁмĴæÆ÷1
0x2c
32
read-write
0x00000000
0xFFFFFFFF
SEQLEN
SEQLEN
20
4
read-write
CONVSQx
CONVSQx
0
20
read-write
SQR2
ADC1ÐòÁмĴæÆ÷2
0x30
32
read-write
0x00000000
0xFFFFFFFF
CONVSQx
CONVSQx
0
30
read-write
SQR3
ADC1ÐòÁмĴæÆ÷3
0x34
32
read-write
0x00000000
0xFFFFFFFF
CONVSQx
CONVSQx
0
30
read-write
JSQR
ADC1×¢ÈëÐòÁмĴæÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
JSEQLEN
JSEQLEN
20
2
read-write
JCONVSQx
JCONVSQx
0
20
read-write
JOUTDAT1
ADC1×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷1
0x3c
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT2
ADC1×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷2
0x40
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT3
ADC1×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷3
0x44
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT4
ADC1×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷4
0x48
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
OUTDAT
ADC1ת»»Êä³öÊý¾Ý¼Ä´æÆ÷
0x4c
32
read-write
0x00000000
0xFFFFFFFF
ADCC2OUTDAT
ADCC2OUTDAT
16
16
read-only
OUTDAT
OUTDAT
0
16
read-only
ADC2
1.0
Add your description
ADC
0x40012800
32
read-write
0
0x00000400
registers
ADC
ADC2 global interrupt
18
STS
ADC2״̬¼Ä´æÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
STRTF
STRTF
4
1
read-clear by writing 0
JSTRTF
JSTRTF
3
1
read-clear by writing 0
EOJCH
EOJCH
2
1
read-clear by writing 0
EOCH
EOCH
1
1
read-clear by writing 0
WDEVT
WDEVT
0
1
read-clear by writing 0
CTR1
ADC2¿ØÖƼĴæÆ÷1
0x4
32
read-write
0x00000000
0xFFFFFFFF
WDGEN
WDGEN
23
1
read-write
AWDJCHEN
AWDJCHEN
22
1
read-write
DMS
DMS
16
4
read-write
DISCCHCNT
DISCCHCNT
13
3
read-write
JDISCEN
JDISCEN
12
1
read-write
DISCEN
DISCEN
11
1
read-write
JAUTOC
JAUTOC
10
1
read-write
AWDSGLEN
AWDSGLEN
9
1
read-write
SCANMD
SCANMD
8
1
read-write
JEOCIE
JEOCIE
7
1
read-write
WDEVTIE
WDEVTIE
6
1
read-write
EOCIE
EOCIE
5
1
read-write
WDGCHAN
WDGCHAN
0
5
read-write
CTR
ADC2ͨÓÿØÖƼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
TSVRFEN
TSVRFEN
23
1
read-write
START
START
22
1
read-write
JSTART
JSTART
21
1
read-write
EXTTRG
EXTTRG
20
1
read-write
EVTS
EVTS
17
3
read-write
JEXTTRG
JEXTTRG
15
1
read-write
JEVTS
JEVTS
12
3
read-write
DALGN
DALGN
11
1
read-write
DMAEN
DMAEN
8
1
read-write
RSTCALB
RSTCALB
3
1
read-write
CALB
CALB
2
1
read-write
GCONT
GCONT
1
1
read-write
ADCON
ADCON
0
1
read-write
SMPR1
ADC2²ÉÑùʱ¼äÅäÖÃ1
0xc
32
read-write
0x00000000
0xFFFFFFFF
SMPLTx
SMPLTx
0
24
read-write
SMPR2
ADC2²ÉÑùʱ¼äÅäÖÃ2
0x10
32
read-write
0x00000000
0xFFFFFFFF
SMPLTx
SMPLTx
0
30
read-write
JOFT1
ADC2×¢ÈëͨµÀoffset¼Ä´æÆ÷1
0x14
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT2
ADC2×¢ÈëͨµÀoffset¼Ä´æÆ÷2
0x18
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT3
ADC2×¢ÈëͨµÀoffset¼Ä´æÆ÷3
0x1c
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
JOFT4
ADC2×¢ÈëͨµÀoffset¼Ä´æÆ÷4
0x20
32
read-write
0x00000000
0xFFFFFFFF
JOFT
JOFT
0
12
read-write
WDTH
Ä£Äâ¿´ÃŹ·ãÐÖµ¼Ä´æÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
HITH
HITH
0
12
read-write
WDTL
Ä£Äâ¿´ÃŹ·ãÐÖµ¼Ä´æÆ÷
0x28
32
read-write
0x00000000
0xFFFFFFFF
LOTH
LOTH
0
12
read-write
SQR1
ADC2ÐòÁмĴæÆ÷1
0x2c
32
read-write
0x00000000
0xFFFFFFFF
SEQLEN
SEQLEN
20
4
read-write
CONVSQx
CONVSQx
0
20
read-write
SQR2
ADC2ÐòÁмĴæÆ÷2
0x30
32
read-write
0x00000000
0xFFFFFFFF
CONVSQx
CONVSQx
0
30
read-write
SQR3
ADC2ÐòÁмĴæÆ÷3
0x34
32
read-write
0x00000000
0xFFFFFFFF
CONVSQx
CONVSQx
0
30
read-write
JSQR
ADC2×¢ÈëÐòÁмĴæÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
JSEQLEN
JSEQLEN
20
2
read-write
JCONVSQx
JCONVSQx
0
20
read-write
JOUTDAT1
ADC2×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷1
0x3c
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT2
ADC2×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷2
0x40
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT3
ADC2×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷3
0x44
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
JOUTDAT4
ADC2×¢ÈëͨµÀÊý¾Ý¼Ä´æÆ÷4
0x48
32
read-write
0x00000000
0xFFFFFFFF
JOUTDAT
JOUTDAT
0
16
read-write
OUTDAT
ADC2ת»»Êä³öÊý¾Ý¼Ä´æÆ÷
0x4c
32
read-write
0x00000000
0xFFFFFFFF
ADCC2OUTDAT
ADCC2OUTDAT
16
16
read-only
OUTDAT
OUTDAT
0
16
read-only
I2C1
1.0
Add your description
I2C
0x40005400
32
read-write
0
0x00000400
registers
I2C1_EV
I2C1 event interrupt
31
I2C1_ER
I2C1 error interrupt
32
CTR1
¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x0000
0xFFFFFFFF
SWREST
SWREST
15
1
read-write
SMBAEN
SMBAEN
13
1
read-write
PECK
PECK
12
1
read-write
APPOS
APPOS
11
1
read-write
ACKEN
ACKEN
10
1
read-write
STOPGEN
STOPGEN
9
1
read-write
STARTGEN
STARTGEN
8
1
read-write
DISSTRETCH
DISSTRETCH
7
1
read-write
GCEN
GCEN
6
1
read-write
PECMEN
PECMEN
5
1
read-write
ARPEN
ARPEN
4
1
read-write
SMBTPS
SMBTPS
3
1
read-write
SMBMD
SMBMD
1
1
read-write
I2CEN
I2CEN
0
1
read-write
CTR2
¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x0000
0xFFFFFFFF
DMALST
DMALST
12
1
read-write
DMAEN
DMAEN
11
1
read-write
BUFITEN
BUFITEN
10
1
read-write
EVTITEN
EVTITEN
9
1
read-write
ERRITEN
ERRITEN
8
1
read-write
CLKFREQ
CLKFREQ
0
6
read-write
SADR1
µØÖ·¼Ä´æÆ÷1
0x8
32
read-write
0x0000
0xFFFFFFFF
SADR1EN
SADR1EN
15
1
read-write
SADR9_8
SADR9_8
8
2
read-write
SADR7_1
SADR7_1
1
7
read-write
SADR0
SADR0
0
1
read-write
SADR2
µØÖ·¼Ä´æÆ÷2
0xC
32
read-write
0x0000
0xFFFFFFFF
SADR2
SADR2
1
7
read-write
SADR2EN
SADR2EN
0
1
read-write
DTR
Êý¾Ý¼Ä´æÆ÷
0x10
32
read-write
0x0000
0xFFFFFFFF
DTR
DTR
0
8
read-write
STR1
״̬¼Ä´æÆ÷1
0x14
32
read-write
0x0000
0xFFFFFFFF
SMBAF
SMBAF
15
1
read-clear by writing 0
OVRTF
OVRTF
14
1
read-clear by writing 0
PECERRF
PECERRF
12
1
read-clear by writing 0
OVRF
OVRF
11
1
read-clear by writing 0
ACKF
ACKF
10
1
read-clear by writing 0
ARBLOF
ARBLOF
9
1
read-clear by writing 0
BUSERRF
BUSERRF
8
1
read-clear by writing 0
TXEF
TXEF
7
1
read-only
RXNEF
RXNEF
6
1
read-only
STOPF
STOPF
4
1
read-only
ADD10ST
ADD10ST
3
1
read-only
BTFS
BTFS
2
1
read-only
ADDRF
ADDRF
1
1
read-only
SBF
SBF
0
1
read-only
STR2
״̬¼Ä´æÆ÷2
0x18
32
read-write
0x0000
0xFFFFFFFF
PECCODE
PECCODE
8
8
read-only
SDUALF
SDUALF
7
1
read-only
SMBHTF
SMBHTF
6
1
read-only
SMBDEFF
SMBDEFF
5
1
read-only
GCF
GCF
4
1
read-only
TRF
TRF
2
1
read-only
BUSYF
BUSYF
1
1
read-only
MSF
MSF
0
1
read-only
CCTR
ʱÖÓ¿ØÖƼĴæÆ÷
0x1C
32
read-write
0x0000
0xFFFFFFFF
FSC
FSC
15
1
read-write
FSDUTC
FSDUTC
14
1
read-write
CCTR
CCTR
0
12
read-write
MRTR
×î´óÉÏÉýʱ¼ä¿ØÖƼĴæÆ÷
0x20
32
read-write
0x0002
0xFFFFFFFF
MRT
MRT
0
6
read-write
I2C2
1.0
Add your description
I2C
0x40005800
32
read-write
0
0x00000400
registers
I2C2_EV
I2C2 event interrupt
33
I2C2_ER
I2C2 error interrupt
34
CTR1
¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x0000
0xFFFFFFFF
SWREST
SWREST
15
1
read-write
SMBAEN
SMBAEN
13
1
read-write
PECK
PECK
12
1
read-write
APPOS
APPOS
11
1
read-write
ACKEN
ACKEN
10
1
read-write
STOPGEN
STOPGEN
9
1
read-write
STARTGEN
STARTGEN
8
1
read-write
DISSTRETCH
DISSTRETCH
7
1
read-write
GCEN
GCEN
6
1
read-write
PECMEN
PECMEN
5
1
read-write
ARPEN
ARPEN
4
1
read-write
SMBTPS
SMBTPS
3
1
read-write
SMBMD
SMBMD
1
1
read-write
I2CEN
I2CEN
0
1
read-write
CTR2
¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x0000
0xFFFFFFFF
DMALST
DMALST
12
1
read-write
DMAEN
DMAEN
11
1
read-write
BUFITEN
BUFITEN
10
1
read-write
EVTITEN
EVTITEN
9
1
read-write
ERRITEN
ERRITEN
8
1
read-write
CLKFREQ
CLKFREQ
0
6
read-write
SADR1
µØÖ·¼Ä´æÆ÷1
0x8
32
read-write
0x0000
0xFFFFFFFF
SADR1EN
SADR1EN
15
1
read-write
SADR9_8
SADR9_8
8
2
read-write
SADR7_1
SADR7_1
1
7
read-write
SADR0
SADR0
0
1
read-write
SADR2
µØÖ·¼Ä´æÆ÷2
0xC
32
read-write
0x0000
0xFFFFFFFF
SADR2
SADR2
1
7
read-write
SADR2EN
SADR2EN
0
1
read-write
DTR
Êý¾Ý¼Ä´æÆ÷
0x10
32
read-write
0x0000
0xFFFFFFFF
DTR
DTR
0
8
read-write
STR1
״̬¼Ä´æÆ÷1
0x14
32
read-write
0x0000
0xFFFFFFFF
SMBAF
SMBAF
15
1
read-clear by writing 0
OVRTF
OVRTF
14
1
read-clear by writing 0
PECERRF
PECERRF
12
1
read-clear by writing 0
OVRF
OVRF
11
1
read-clear by writing 0
ACKF
ACKF
10
1
read-clear by writing 0
ARBLOF
ARBLOF
9
1
read-clear by writing 0
BUSERRF
BUSERRF
8
1
read-clear by writing 0
TXEF
TXEF
7
1
read-only
RXNEF
RXNEF
6
1
read-only
STOPF
STOPF
4
1
read-only
ADD10ST
ADD10ST
3
1
read-only
BTFS
BTFS
2
1
read-only
ADDRF
ADDRF
1
1
read-only
SBF
SBF
0
1
read-only
STR2
״̬¼Ä´æÆ÷2
0x18
32
read-write
0x0000
0xFFFFFFFF
PECCODE
PECCODE
8
8
read-only
SDUALF
SDUALF
7
1
read-only
SMBHTF
SMBHTF
6
1
read-only
SMBDEFF
SMBDEFF
5
1
read-only
GCF
GCF
4
1
read-only
TRF
TRF
2
1
read-only
BUSYF
BUSYF
1
1
read-only
MSF
MSF
0
1
read-only
CCTR
ʱÖÓ¿ØÖƼĴæÆ÷
0x1C
32
read-write
0x0000
0xFFFFFFFF
FSC
FSC
15
1
read-write
FSDUTC
FSDUTC
14
1
read-write
CCTR
CCTR
0
12
read-write
MRTR
×î´óÉÏÉýʱ¼ä¿ØÖƼĴæÆ÷
0x20
32
read-write
0x0002
0xFFFFFFFF
MRT
MRT
0
6
read-write
DMA1
1.0
Add your description
DMA
0x40020000
32
read-write
0
0x00000400
registers
DMA1_Channel1
DMA1 Channel1 global interrupt
11
DMA1_Channel2
DMA1 Channel2 global interrupt
12
DMA1_Channel3
DMA1 Channel3 global interrupt
13
DMA1_Channel4
DMA1 Channel4 global interrupt
14
DMA1_Channel5
DMA1 Channel5 global interrupt
15
DMA1_Channel6
DMA1 Channel6 global interrupt
16
DMA1_Channel7
DMA1 Channel7 global interrupt
17
STS
DMA ÖжÏ״̬¼Ä´æÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
ERRIF7
ERRIF7
27
1
read-only
HLFIF7
HLFIF7
26
1
read-only
CMPIF7
CMPIF7
25
1
read-only
GIF7
GIF7
24
1
read-only
ERRIF6
ERRIF6
23
1
read-only
HLFIF6
HLFIF6
22
1
read-only
CMPIF6
CMPIF6
21
1
read-only
GIF6
GIF6
20
1
read-only
ERRIF5
ERRIF5
19
1
read-only
HLFIF5
HLFIF5
18
1
read-only
CMPIF5
CMPIF5
17
1
read-only
GIF5
GIF5
16
1
read-only
ERRIF4
ERRIF4
15
1
read-only
HLFIF4
HLFIF4
14
1
read-only
CMPIF4
CMPIF4
13
1
read-only
GIF4
GIF4
12
1
read-only
ERRIF3
ERRIF3
11
1
read-only
HLFIF3
HLFIF3
10
1
read-only
CMPIF3
CMPIF3
9
1
read-only
GIF3
GIF3
8
1
read-only
ERRIF2
ERRIF2
7
1
read-only
HLFIF2
HLFIF2
6
1
read-only
CMPIF2
CMPIF2
5
1
read-only
GIF2
GIF2
4
1
read-only
ERRIF1
ERRIF1
3
1
read-only
HLFIF1
HLFIF1
2
1
read-only
CMPIF1
CMPIF1
1
1
read-only
GIF1
GIF1
0
1
read-only
INTFC
DMA ÖжϱêÖ¾Çå³ý¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
ERRIFC7
ERRIFC7
27
1
read-write
HLFIFC7
HLFIFC7
26
1
read-write
CMPIFC7
CMPIFC7
25
1
read-write
GIFC7
GIFC7
24
1
read-write
ERRIFC6
ERRIFC6
23
1
read-write
HLFIFC6
HLFIFC6
22
1
read-write
CMPIFC6
CMPIFC6
21
1
read-write
GIFC6
GIFC6
20
1
read-write
ERRIFC5
ERRIFC5
19
1
read-write
HLFIFC5
HLFIFC5
18
1
read-write
CMPIFC5
CMPIFC5
17
1
read-write
GIFC5
GIFC5
16
1
read-write
ERRIFC4
ERRIFC4
15
1
read-write
HLFIFC4
HLFIFC4
14
1
read-write
CMPIFC4
CMPIFC4
13
1
read-write
GIFC4
GIFC4
12
1
read-write
ERRIFC3
ERRIFC3
11
1
read-write
HLFIFC3
HLFIFC3
10
1
read-write
CMPIFC3
CMPIFC3
9
1
read-write
GIFC3
GIFC3
8
1
read-write
ERRIFC2
ERRIFC2
7
1
read-write
HLFIFC2
HLFIFC2
6
1
read-write
CMPIFC2
CMPIFC2
5
1
read-write
GIFC2
GIFC2
4
1
read-write
ERRIFC1
ERRIFC1
3
1
read-write
HLFIFC1
HLFIFC1
2
1
read-write
CMPIFC1
CMPIFC1
1
1
read-write
GIFC1
GIFC1
0
1
read-write
CH1CTR
DMA ͨµÀ 1 ¿ØÖƼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH1NUM
DMA ͨµÀ 1 ´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH1PA
DMA ͨµÀ 1ÍâÉèµØÖ·¼Ä´æÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH1MA
DMA ͨµÀ 1´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH2CTR
DMA ͨµÀ 2¿ØÖƼĴæÆ÷
0x1C
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH2NUM
DMA ͨµÀ 2 ´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x20
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH2PA
DMA ͨµÀ 2ÍâÉèµØÖ·¼Ä´æÆ÷
0x24
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH2MA
DMA ͨµÀ 2´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x28
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH3CTR
DMA ͨµÀ 3¿ØÖƼĴæÆ÷
0x30
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH3NUM
DMA ͨµÀ 3 ´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x34
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH3PA
DMA ͨµÀ 3ÍâÉèµØÖ·¼Ä´æÆ÷
0x38
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH3MA
DMA ͨµÀ 3´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x3C
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH4CTR
DMA ͨµÀ 4¿ØÖƼĴæÆ÷
0x44
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH4NUM
DMA ͨµÀ 4 ´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x48
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH4PA
DMA ͨµÀ 4ÍâÉèµØÖ·¼Ä´æÆ÷
0x4C
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH4MA
DMA ͨµÀ 4´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x50
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH5CTR
DMA ͨµÀ 5¿ØÖƼĴæÆ÷
0x58
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH5NUM
DMA ͨµÀ 5 ´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x5C
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH5PA
DMA ͨµÀ5ÍâÉèµØÖ·¼Ä´æÆ÷
0x60
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH5MA
DMA ͨµÀ 5´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x64
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH6CTR
DMA ͨµÀ 6¿ØÖƼĴæÆ÷
0x6C
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH6NUM
DMA ͨµÀ 6´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x70
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH6PA
DMA ͨµÀ6ÍâÉèµØÖ·¼Ä´æÆ÷
0x74
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH6MA
DMA ͨµÀ6´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x78
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
CH7CTR
DMA ͨµÀ7¿ØÖƼĴæÆ÷
0x80
32
read-write
0x00000000
0xFFFFFFFF
M2MM
M2MM
14
1
read-write
PRIL
PRIL
12
2
read-write
MWDH
MWDH
10
2
read-write
PWDH
PWDH
8
2
read-write
MAGM
MAGM
7
1
read-write
PAGM
PAGM
6
1
read-write
CIRM
CIRM
5
1
read-write
DIR
DIR
4
1
read-write
ERRIE
ERRIE
3
1
read-write
HLFIE
HLFIE
2
1
read-write
CMPIE
CMPIE
1
1
read-write
CEN
CEN
0
1
read-write
CH7NUM
DMA ͨµÀ 7´«ÊäÊý¾Ý¸öÊý¼Ä´æÆ÷
0x84
32
read-write
0x00000000
0xFFFFFFFF
NUM
NUM
0
16
read-write
CH7PA
DMA ͨµÀ7ÍâÉèµØÖ·¼Ä´æÆ÷
0x88
32
read-write
0x00000000
0xFFFFFFFF
PADR
PADR
0
32
read-write
CH7MA
DMA ͨµÀ7´æ´¢Æ÷µØÖ·¼Ä´æÆ÷
0x8C
32
read-write
0x00000000
0xFFFFFFFF
MADR
MADR
0
32
read-write
SPI1
1.0
Add your description
SPI
0x40013000
32
read-write
0
0x00000400
registers
SPI1
SPI1 global interrupt
35
CTR1
SPI1 ¿ØÖƼĴæÆ÷ 1
0x0
32
read-write
0x00000000
0xFFFFFFFF
SBMODE
SBMODE
15
1
read-write
SBOEN
SBOEN
14
1
read-write
CRCEN
CRCEN
13
1
read-write
NXTCRC
NXTCRC
12
1
read-write
DFLS
DFLS
11
1
read-write
ROM
ROM
10
1
read-write
SWNSSM
SWNSSM
9
1
read-write
NVSWNSSM
NVSWNSSM
8
1
read-write
LSBF
LSBF
7
1
read-write
SPIEN
SPIEN
6
1
read-write
CRSEL
CRSEL
3
3
read-write
SPIM
SPIM
2
1
read-write
CPOL
CPOL
1
1
read-write
CPHA
CPHA
0
1
read-write
CTR2
SPI1 ¿ØÖƼĴæÆ÷ 2
0x4
32
read-write
0x00000000
0xFFFFFFFF
TXEINTEN
TXEINTEN
7
1
read-write
RXNEINTEN
RXNEINTEN
6
1
read-write
ERRINTEN
ERRINTEN
5
1
read-write
NSSOEN
NSSOEN
2
1
read-write
DMATXEN
DMATXEN
1
1
read-write
DMARXEN
DMARXEN
0
1
read-write
STS
SPI1 ״̬¼Ä´æÆ÷
0x8
32
read-write
0x00000002
0xFFFFFFFF
BUSY
BUSY
7
1
read-write
RXOFERR
RXOFERR
6
1
read-write
MMERR
MMERR
5
1
read-write
CRCERR
CRCERR
4
1
read-write
TXE
TXE
1
1
read-write
RXNE
RXNE
0
1
read-write
DATA
SPI1 Êý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DATA
DATA
0
16
read-write
CRCPOLYR
SPI1 CRC ¶àÏîʽ¼Ä´æÆ÷
0x10
32
read-write
0x00000007
0xFFFFFFFF
CRCPR
CRCPR
0
16
read-write
RCRC
SPI1 Rx CRC ¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
RCR
RCR
0
16
read-only
TCRC
SPI1 Tx CRC ¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
TCR
TCR
0
16
read-only
SPI2
1.0
Add your description
SPI
0x40003800
32
read-write
0
0x00000400
registers
SPI2
SPI2 global interrupt
36
CTR1
SPI2 ¿ØÖƼĴæÆ÷ 1
0x0
32
read-write
0x00000000
0xFFFFFFFF
SBMODE
SBMODE
15
1
read-write
SBOEN
SBOEN
14
1
read-write
CRCEN
CRCEN
13
1
read-write
NXTCRC
NXTCRC
12
1
read-write
DFLS
DFLS
11
1
read-write
ROM
ROM
10
1
read-write
SWNSSM
SWNSSM
9
1
read-write
NVSWNSSM
NVSWNSSM
8
1
read-write
LSBF
LSBF
7
1
read-write
SPIEN
SPIEN
6
1
read-write
CRSEL
CRSEL
3
3
read-write
SPIM
SPIM
2
1
read-write
CPOL
CPOL
1
1
read-write
CPHA
CPHA
0
1
read-write
CTR2
SPI2 ¿ØÖƼĴæÆ÷ 2
0x4
32
read-write
0x00000000
0xFFFFFFFF
TXEINTEN
TXEINTEN
7
1
read-write
RXNEINTEN
RXNEINTEN
6
1
read-write
ERRINTEN
ERRINTEN
5
1
read-write
NSSOEN
NSSOEN
2
1
read-write
DMATXEN
DMATXEN
1
1
read-write
DMARXEN
DMARXEN
0
1
read-write
STS
SPI2 ״̬¼Ä´æÆ÷
0x8
32
read-write
0x00000002
0xFFFFFFFF
BUSY
BUSY
7
1
read-write
RXOFERR
RXOFERR
6
1
read-write
MMERR
MMERR
5
1
read-write
CRCERR
CRCERR
4
1
read-write
TXE
TXE
1
1
read-write
RXNE
RXNE
0
1
read-write
DATA
SPI2 Êý¾Ý¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
DATA
DATA
0
16
read-write
CRCPOLYR
SPI2 CRC ¶àÏîʽ¼Ä´æÆ÷
0x10
32
read-write
0x00000007
0xFFFFFFFF
CRCPR
CRCPR
0
16
read-write
RCRC
SPI2 Rx CRC ¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
RCR
RCR
0
16
read-only
TCRC
SPI2 Tx CRC ¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
TCR
TCR
0
16
read-only
USART1
1.0
Add your description
USART
0x40013800
32
read-write
0
0x00000400
registers
USART1
USART1 global interrupt
37
STS
USART1״̬¼Ä´æÆ÷
0x0
32
read-write
0x000000C0
0xFFFFFFFF
CTSF
CTSF
9
1
read-clear by writing 0
LINBKF
LINBKF
8
1
read-clear by writing 0
TXE
TXE
7
1
read-only
TCF
TCF
6
1
read-clear by writing 0
RXNE
RXNE
5
1
read-clear by writing 0
IDLEF
IDLEF
4
1
read-only
OVRERRF
OVRERRF
3
1
read-only
NF
NF
2
1
read-only
FERRF
FERRF
1
1
read-only
PERRF
PERRF
0
1
read-only
DATA
USART1Êý¾Ý¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
DATA
DATA
0
9
read-write
BRT
USART1²¨ÌØÂʼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
INTDIV
INTDIV
4
12
read-write
FRADIV
FRADIV
0
4
read-write
CTR1
USART1¿ØÖƼĴæÆ÷1
0xC
32
read-write
0x00000000
0xFFFFFFFF
UEN
UEN
13
1
read-write
FM
FM
12
1
read-write
WKUPS
WKUPS
11
1
read-write
PEN
PEN
10
1
read-write
ODDS
ODDS
9
1
read-write
PERRIE
PERRIE
8
1
read-write
TXEIE
TXEIE
7
1
read-write
TCIE
TCIE
6
1
read-write
RXNEIE
RXNEIE
5
1
read-write
IDLEIE
IDLEIE
4
1
read-write
TEN
TEN
3
1
read-write
REN
REN
2
1
read-write
WKEN
WKEN
1
1
read-write
BRKFEN
BRKFEN
0
1
read-write
CTR2
USART1¿ØÖƼĴæÆ÷2
0x10
32
read-write
0x00000000
0xFFFFFFFF
LINEN
LINEN
14
1
read-write
STOP
STOP
12
2
read-write
CKEN
CKEN
11
1
read-write
CPOL
CPOL
10
1
read-write
CPHA
CPHA
9
1
read-write
CKLEN
CKLEN
8
1
read-write
LBDIE
LBDIE
6
1
read-write
LINBRK11
LINBRK11
5
1
read-write
UADR
UADR
0
4
read-write
CTR3
USART1¿ØÖƼĴæÆ÷3
0x14
32
read-write
0x00000000
0xFFFFFFFF
CTSIE
CTSIE
10
1
read-write
CTSEN
CTSEN
9
1
read-write
RTSEN
RTSEN
8
1
read-write
TXDMA
TXDMA
7
1
read-write
RXDMA
RXDMA
6
1
read-write
SCEN
SCEN
5
1
read-write
SCNACK
SCNACK
4
1
read-write
HDEN
HDEN
3
1
read-write
IRMS
IRMS
2
1
read-write
IRDAEN
IRDAEN
1
1
read-write
ERRIE
ERRIE
0
1
read-write
GTPDIV
±£»¤Ê±¼äºÍÔ¤·ÖƵ¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
GUDT
GUDT
8
8
read-write
PDIV
PDIV
0
8
read-write
USART2
1.0
Add your description
USART
0x40004400
32
read-write
0
0x00000400
registers
USART2
USART2 global interrupt
38
STS
USART2״̬¼Ä´æÆ÷
0x0
32
read-write
0x000000C0
0xFFFFFFFF
CTSF
CTSF
9
1
read-clear by writing 0
LINBKF
LINBKF
8
1
read-clear by writing 0
TXE
TXE
7
1
read-only
TCF
TCF
6
1
read-clear by writing 0
RXNE
RXNE
5
1
read-clear by writing 0
IDLEF
IDLEF
4
1
read-only
OVRERRF
OVRERRF
3
1
read-only
NF
NF
2
1
read-only
FERRF
FERRF
1
1
read-only
PERRF
PERRF
0
1
read-only
DATA
USART2Êý¾Ý¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
DATA
DATA
0
9
read-write
BRT
USART2²¨ÌØÂʼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
INTDIV
INTDIV
4
12
read-write
FRADIV
FRADIV
0
4
read-write
CTR1
USART2¿ØÖƼĴæÆ÷1
0xC
32
read-write
0x00000000
0xFFFFFFFF
UEN
UEN
13
1
read-write
FM
FM
12
1
read-write
WKUPS
WKUPS
11
1
read-write
PEN
PEN
10
1
read-write
ODDS
ODDS
9
1
read-write
PERRIE
PERRIE
8
1
read-write
TXEIE
TXEIE
7
1
read-write
TCIE
TCIE
6
1
read-write
RXNEIE
RXNEIE
5
1
read-write
IDLEIE
IDLEIE
4
1
read-write
TEN
TEN
3
1
read-write
REN
REN
2
1
read-write
WKEN
WKEN
1
1
read-write
BRKFEN
BRKFEN
0
1
read-write
CTR2
USART2¿ØÖƼĴæÆ÷2
0x10
32
read-write
0x00000000
0xFFFFFFFF
LINEN
LINEN
14
1
read-write
STOP
STOP
12
2
read-write
CKEN
CKEN
11
1
read-write
CPOL
CPOL
10
1
read-write
CPHA
CPHA
9
1
read-write
CKLEN
CKLEN
8
1
read-write
LBDIE
LBDIE
6
1
read-write
LINBRK11
LINBRK11
5
1
read-write
UADR
UADR
0
4
read-write
CTR3
USART2¿ØÖƼĴæÆ÷3
0x14
32
read-write
0x00000000
0xFFFFFFFF
CTSIE
CTSIE
10
1
read-write
CTSEN
CTSEN
9
1
read-write
RTSEN
RTSEN
8
1
read-write
TXDMA
TXDMA
7
1
read-write
RXDMA
RXDMA
6
1
read-write
SCEN
SCEN
5
1
read-write
SCNACK
SCNACK
4
1
read-write
HDEN
HDEN
3
1
read-write
IRMS
IRMS
2
1
read-write
IRDAEN
IRDAEN
1
1
read-write
ERRIE
ERRIE
0
1
read-write
GTPDIV
±£»¤Ê±¼äºÍÔ¤·ÖƵ¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
GUDT
GUDT
8
8
read-write
PDIV
PDIV
0
8
read-write
USART3
1.0
Add your description
USART
0x40004800
32
read-write
0
0x00000400
registers
USART3
USART3 global interrupt
39
STS
USART3״̬¼Ä´æÆ÷
0x0
32
read-write
0x000000C0
0xFFFFFFFF
CTSF
CTSF
9
1
read-clear by writing 0
LINBKF
LINBKF
8
1
read-clear by writing 0
TXE
TXE
7
1
read-only
TCF
TCF
6
1
read-clear by writing 0
RXNE
RXNE
5
1
read-clear by writing 0
IDLEF
IDLEF
4
1
read-only
OVRERRF
OVRERRF
3
1
read-only
NF
NF
2
1
read-only
FERRF
FERRF
1
1
read-only
PERRF
PERRF
0
1
read-only
DATA
USART3Êý¾Ý¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
DATA
DATA
0
9
read-write
BRT
USART3²¨ÌØÂʼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
INTDIV
INTDIV
4
12
read-write
FRADIV
FRADIV
0
4
read-write
CTR1
USART3¿ØÖƼĴæÆ÷1
0xC
32
read-write
0x00000000
0xFFFFFFFF
UEN
UEN
13
1
read-write
FM
FM
12
1
read-write
WKUPS
WKUPS
11
1
read-write
PEN
PEN
10
1
read-write
ODDS
ODDS
9
1
read-write
PERRIE
PERRIE
8
1
read-write
TXEIE
TXEIE
7
1
read-write
TCIE
TCIE
6
1
read-write
RXNEIE
RXNEIE
5
1
read-write
IDLEIE
IDLEIE
4
1
read-write
TEN
TEN
3
1
read-write
REN
REN
2
1
read-write
WKEN
WKEN
1
1
read-write
BRKFEN
BRKFEN
0
1
read-write
CTR2
USART3¿ØÖƼĴæÆ÷2
0x10
32
read-write
0x00000000
0xFFFFFFFF
LINEN
LINEN
14
1
read-write
STOP
STOP
12
2
read-write
CKEN
CKEN
11
1
read-write
CPOL
CPOL
10
1
read-write
CPHA
CPHA
9
1
read-write
CKLEN
CKLEN
8
1
read-write
LBDIE
LBDIE
6
1
read-write
LINBRK11
LINBRK11
5
1
read-write
UADR
UADR
0
4
read-write
CTR3
USART3¿ØÖƼĴæÆ÷3
0x14
32
read-write
0x00000000
0xFFFFFFFF
CTSIE
CTSIE
10
1
read-write
CTSEN
CTSEN
9
1
read-write
RTSEN
RTSEN
8
1
read-write
TXDMA
TXDMA
7
1
read-write
RXDMA
RXDMA
6
1
read-write
SCEN
SCEN
5
1
read-write
SCNACK
SCNACK
4
1
read-write
HDEN
HDEN
3
1
read-write
IRMS
IRMS
2
1
read-write
IRDAEN
IRDAEN
1
1
read-write
ERRIE
ERRIE
0
1
read-write
GTPDIV
±£»¤Ê±¼äºÍÔ¤·ÖƵ¼Ä´æÆ÷
0x18
32
read-write
0x00000000
0xFFFFFFFF
GUDT
GUDT
8
8
read-write
PDIV
PDIV
0
8
read-write
EXTI
1.0
Add your description
EXTI
0x40010400
32
read-write
0
0x00000400
registers
TAMPER
Tamper interrupt
2
EXTI0
EXTI Line0 interrupt
6
EXTI1
EXTI Line1 interrupt
7
EXTI2
EXTI Line2 interrupt
8
EXTI3
EXTI Line3 interrupt
9
EXTI4
EXTI Line4 interrupt
10
EXTI9_5
EXTI Line[9:5] interrupts
23
EXTI15_10
EXTI Line[15:10] interrupts
40
INTEN
EXTIÖжÏʹÄܼĴæÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
INTEN18
INTEN18
18
1
read-write
INTEN17
INTEN17
17
1
read-write
INTEN16
INTEN16
16
1
read-write
INTEN15
INTEN15
15
1
read-write
INTEN14
INTEN14
14
1
read-write
INTEN13
INTEN13
13
1
read-write
INTEN12
INTEN12
12
1
read-write
INTEN11
INTEN11
11
1
read-write
INTEN10
INTEN10
10
1
read-write
INTEN9
INTEN9
9
1
read-write
INTEN8
INTEN8
8
1
read-write
INTEN7
INTEN7
7
1
read-write
INTEN6
INTEN6
6
1
read-write
INTEN5
INTEN5
5
1
read-write
INTEN4
INTEN4
4
1
read-write
INTEN3
INTEN3
3
1
read-write
INTEN2
INTEN2
2
1
read-write
INTEN1
INTEN1
1
1
read-write
INTEN0
INTEN0
0
1
read-write
EVTEN
EXTI ʼþʹÄܼĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
EVTEN18
EVTEN18
18
1
read-write
EVTEN17
EVTEN17
17
1
read-write
EVTEN16
EVTEN16
16
1
read-write
EVTEN15
EVTEN15
15
1
read-write
EVTEN14
EVTEN14
14
1
read-write
EVTEN13
EVTEN13
13
1
read-write
EVTEN12
EVTEN12
12
1
read-write
EVTEN11
EVTEN11
11
1
read-write
EVTEN10
EVTEN10
10
1
read-write
EVTEN9
EVTEN9
9
1
read-write
EVTEN8
EVTEN8
8
1
read-write
EVTEN7
EVTEN7
7
1
read-write
EVTEN6
EVTEN6
6
1
read-write
EVTEN5
EVTEN5
5
1
read-write
EVTEN4
EVTEN4
4
1
read-write
EVTEN3
EVTEN3
3
1
read-write
EVTEN2
EVTEN2
2
1
read-write
EVTEN1
EVTEN1
1
1
read-write
EVTEN0
EVTEN0
0
1
read-write
RTEN
EXTI ÉÏÉýÑØ´¥·¢Ê¹ÄܼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
RTEN18
RTEN18
18
1
read-write
RTEN17
RTEN17
17
1
read-write
RTEN16
RTEN16
16
1
read-write
RTEN15
RTEN15
15
1
read-write
RTEN14
RTEN14
14
1
read-write
RTEN13
RTEN13
13
1
read-write
RTEN12
RTEN12
12
1
read-write
RTEN11
RTEN11
11
1
read-write
RTEN10
RTEN10
10
1
read-write
RTEN9
RTEN9
9
1
read-write
RTEN8
RTEN8
8
1
read-write
RTEN7
RTEN7
7
1
read-write
RTEN6
RTEN6
6
1
read-write
RTEN5
RTEN5
5
1
read-write
RTEN4
RTEN4
4
1
read-write
RTEN3
RTEN3
3
1
read-write
RTEN2
RTEN2
2
1
read-write
RTEN1
RTEN1
1
1
read-write
RTEN0
RTEN0
0
1
read-write
FTEN
EXTI ÏÂÉýÑØ´¥·¢Ê¹ÄܼĴæÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
FTEN18
FTEN18
18
1
read-write
FTEN17
FTEN17
17
1
read-write
FTEN16
FTEN16
16
1
read-write
FTEN15
FTEN15
15
1
read-write
FTEN14
FTEN14
14
1
read-write
FTEN13
FTEN13
13
1
read-write
FTEN12
FTEN12
12
1
read-write
FTEN11
FTEN11
11
1
read-write
FTEN10
FTEN10
10
1
read-write
FTEN9
FTEN9
9
1
read-write
FTEN8
FTEN8
8
1
read-write
FTEN7
FTEN7
7
1
read-write
FTEN6
FTEN6
6
1
read-write
FTEN5
FTEN5
5
1
read-write
FTEN4
FTEN4
4
1
read-write
FTEN3
FTEN3
3
1
read-write
FTEN2
FTEN2
2
1
read-write
FTEN1
FTEN1
1
1
read-write
FTEN0
FTEN0
0
1
read-write
SWTIEN
EXTI Èí¼þ´¥·¢ÖжÏ/ʼþʹÄܼĴæÆ÷
0x10
32
read-write
0x00000000
0xFFFFFFFF
SWTIEN18
SWTIEN18
18
1
read-write
SWTIEN17
SWTIEN17
17
1
read-write
SWTIEN16
SWTIEN16
16
1
read-write
SWTIEN15
SWTIEN15
15
1
read-write
SWTIEN14
SWTIEN14
14
1
read-write
SWTIEN13
SWTIEN13
13
1
read-write
SWTIEN12
SWTIEN12
12
1
read-write
SWTIEN11
SWTIEN11
11
1
read-write
SWTIEN10
SWTIEN10
10
1
read-write
SWTIEN9
SWTIEN9
9
1
read-write
SWTIEN8
SWTIEN8
8
1
read-write
SWTIEN7
SWTIEN7
7
1
read-write
SWTIEN6
SWTIEN6
6
1
read-write
SWTIEN5
SWTIEN5
5
1
read-write
SWTIEN4
SWTIEN4
4
1
read-write
SWTIEN3
SWTIEN3
3
1
read-write
SWTIEN2
SWTIEN2
2
1
read-write
SWTIEN1
SWTIEN1
1
1
read-write
SWTIEN0
SWTIEN0
0
1
read-write
PDF
EXTI ÐüÆð¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
PDF18
PDF18
18
1
read-clear by writing 1
PDF17
PDF17
17
1
read-clear by writing 1
PDF16
PDF16
16
1
read-clear by writing 1
PDF15
PDF15
15
1
read-clear by writing 1
PDF14
PDF14
14
1
read-clear by writing 1
PDF13
PDF13
13
1
read-clear by writing 1
PDF12
PDF12
12
1
read-clear by writing 1
PDF11
PDF11
11
1
read-clear by writing 1
PDF10
PDF10
10
1
read-clear by writing 1
PDF9
PDF9
9
1
read-clear by writing 1
PDF8
PDF8
8
1
read-clear by writing 1
PDF7
PDF7
7
1
read-clear by writing 1
PDF6
PDF6
6
1
read-clear by writing 1
PDF5
PDF5
5
1
read-clear by writing 1
PDF4
PDF4
4
1
read-clear by writing 1
PDF3
PDF3
3
1
read-clear by writing 1
PDF2
PDF2
2
1
read-clear by writing 1
PDF1
PDF1
1
1
read-clear by writing 1
PDF0
PDF0
0
1
read-clear by writing 1
PMU
1.0
Add your description
PMU
0x40007000
32
read-write
0
0x00000400
registers
PVD
PVD through EXTI line detection
1
CTR
µçÔ´¿ØÖƼĴæÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
VBTWEN
VBTWEN
8
1
read-write
LVDSEL
LVDSEL
5
3
read-write
LVDEN
LVDEN
4
1
read-write
CLRPWDF
CLRPWDF
3
1
read-clear by writing 1
CLRWUPF
CLRWUPF
2
1
read-clear by writing 1
DSMODE
DSMODE
1
1
read-write
LDOLM
LDOLM
0
1
read-write
CS
µçÔ´¿ØÖÆ/״̬¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
WUPEN
WUPEN
8
1
read-write
LVDO
LVDO
2
1
read-only
PWDF
PWDF
1
1
read-only
WUPF
WUPF
0
1
read-only
FMC
1.0
Add your description
FMC
0x40022000
32
read-write
0
0x00000024
registers
FMC_WCR
FMCµÈ´ý¼Ä´æÆ÷
0x0
32
read-write
0x00000030
0xFFFFFFFF
WS
WS
5
1
read-only
WE
WE
4
1
read-write
HCAEN
HCAEN
3
1
read-write
WCNT
WCNT
0
3
read-write
FMC_CCODE
FMC¿ØÖÆÂë¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
CCODE
CCODE
0
32
write-only
FMC_OBCCODE
FMC´úÂëÑ¡Ïî×Ö½Ú¿ØÖÆÂë¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
OBCCODE
OBCCODE
0
32
write-only
FMC_STS
FMC״̬¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
ENDF
ENDF
5
1
read-write
WPERR
WPERR
4
1
read-write
PGERR
PGERR
2
1
read-write
BUSY
BUSY
0
1
read-only
FMC_CTR
FMC¿ØÖƼĴæÆ÷
0x10
32
read-write
0x00000080
0xFFFFFFFF
ENDIE
ENDIE
12
1
read-write
ERRIE
ERRIE
10
1
read-write
OBWEN
OBWEN
9
1
read-write
LOCK
LOCK
7
1
read-write
START
START
6
1
read-write
OBERS
OBERS
5
1
read-write
OBPG
OBPG
4
1
read-write
CHIPERS
CHIPERS
2
1
read-write
PERS
PERS
1
1
read-write
PG
PG
0
1
read-write
FMC_ERSADR
²Á³ýµØÖ·¼Ä´æÆ÷
0x14
32
read-write
0x00000000
0xFFFFFFFF
ERSADR
ERSADR
0
32
write-only
FMC_OBSTS
´úÂëÑ¡Ïî×Ö½Ú״̬¼Ä´æÆ÷
0x1C
32
read-write
0x03FFFFFC
0xFFFFFFFF
DATA1
DATA1
18
8
read-only
DATA0
DATA0
10
8
read-only
nRST_STDBY
nRST_STDBY
4
1
read-only
nRST_STOP
nRST_STOP
3
1
read-only
FWDT_AO
FWDT_AO
2
1
read-only
RPROT
RPROT
1
1
read-only
OBERR
OBERR
0
1
read-only
FMC_WRPR
ÉÁ´æд±£»¤×´Ì¬¼Ä´æÆ÷
0x20
32
read-write
0xFFFFFFFF
0xFFFFFFFF
WPROT3
WPROT3
24
8
read-only
WPROT2
WPROT2
16
8
read-only
WPROT1
WPROT1
8
8
read-only
WPROT0
WPROT0
0
8
read-only
FWDT
1.0
Add your description
FWDT
0x40003000
32
read-write
0
0x00000400
registers
FWDT_CCODE
FWDT¿ØÖÆÂë¼Ä´æÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
CCODE
CCODE
0
16
write-only
FWDT_PDIV
FWDTÔ¤·ÖƵ¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
PDIV
PDIV
0
3
read-write
FWDT_UVAL
FWDT¸üмĴæÆ÷
0x8
32
read-write
0x00000FFF
0xFFFFFFFF
UVAL
UVAL
0
12
read-write
FWDT_STS
FWDT״̬¼Ä´æÆ÷
0xC
32
read-write
0x00000000
0xFFFFFFFF
UVRF
UVRF
0
2
read-only
WWDT
1.0
Add your description
WWDT
0x40002C00
32
read-write
0
0x00000400
registers
WWDT
Window Watchdog interrupt
0
WWDT_CTR1
WWDT¿ØÖƼĴæÆ÷1
0x0
32
read-write
0x7F
0xFFFFFFFF
WWDTEN
WWDTEN
7
1
read-set
CVAL
CVAL
0
7
read-write
WWDT_CTR2
WWDT¿ØÖƼĴæÆ÷2
0x4
32
read-write
0x7F
0xFFFFFFFF
RMDIE
RMDIE
9
1
read-set
PDIV
PDIV
7
2
read-write
WVAL
WVAL
0
7
read-write
WWDT_STS
WWDT״̬¼Ä´æÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
RMDIF
RMDIF
0
1
read-clear by writing 0
DBG
1.0
Add your description
DBG
0xE0042000
32
read-write
0
0x00000008
registers
DBG_ID
΢¿ØÖÆÆ÷É豸IDÂë
0x0
32
read-write
0x00000410
0xFFFFFFFF
REV_ID
REV_ID
16
16
read-only
DEV_ID
DEV_ID
00
12
read-only
DBG_LPWCFG
µÍ¹¦ºÄµ÷ÊÔÖ§³ÖÅäÖüĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
I2C2_SMBUS_DBG_TMOUT
I2C2_SMBUS_DBG_TMOUT
16
1
read-write
I2C1_SMBUS_DBG_TMOUT
I2C1_SMBUS_DBG_TMOUT
15
1
read-write
CAN1_DBG_PAUSE
CAN1_DBG_PAUSE
14
1
read-write
TIM4_DBG_PAUSE
TIM4_DBG_PAUSE
13
1
read-write
TIM3_DBG_PAUSE
TIM3_DBG_PAUSE
12
1
read-write
TIM2_DBG_PAUSE
TIM2_DBG_PAUSE
11
1
read-write
TIM1_DBG_PAUSE
TIM1_DBG_PAUSE
10
1
read-write
WWDT_DBG_PAUSE
WWDT_DBG_PAUSE
9
1
read-write
FWDT_DBG_PAUSE
FWDT_DBG_PAUSE
8
1
read-write
TRACE_MD
TRACE_MD
6
2
read-write
TRACE_IOEN
TRACE_IOEN
5
1
read-write
STDBY_DBGEN
STDBY_DBGEN
2
1
read-write
STOP_DBGEN
STOP_DBGEN
1
1
read-write
SLEEP_DBGEN
SLEEP_DBGEN
0
1
read-write
CRC
1.0
Add your description
CRC
0x40023000
32
read-write
0
0x00000400
registers
DATA
Êý¾Ý¼Ä´æÆ÷
0x0
32
read-write
0xFFFFFFFF
0xFFFFFFFF
DATA
DATA
0
32
read-write
FREDATA
¶ÀÁ¢Êý¾Ý¼Ä´æÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
FREDATA
FREDATA
0
8
read-write
CRC_CTR
¿ØÖƼĴæÆ÷
0x8
32
read-write
0x00000000
0xFFFFFFFF
RST
RST
0
1
read-write
AFIO
1.0
Add your description
AFIO
0x40010000
32
read-write
0
0x00000400
registers
ECR
ʼþ¿ØÖƼĴæÆ÷
0x0
32
read-write
0x00000000
0xFFFFFFFF
EOEN
EOEN
7
1
read-write
EOPS
EOPS
4
3
read-write
EOPIN
EOPIN
0
4
read-write
MP
¸´Óù¦ÄÜÓ³ÉäºÍDebug¿ÚÅäÖüĴæÆ÷
0x4
32
read-write
0x00000000
0xFFFFFFFF
SWJ_CFG
SWJ_CFG
24
3
read-write
ADC2_ETRCRMP
ADC2_ETRCRMP
20
1
read-write
ADC2_ETJCRMP
ADC2_ETJCRMP
19
1
read-write
ADC1_ETRCRMP
ADC1_ETRCRMP
18
1
read-write
ADC1_ETJCRMP
ADC1_ETJCRMP
17
1
read-write
PTD01_MP
PTD01_MP
15
1
read-write
CAN_RMP
CAN_RMP
13
2
read-write
TIM4_RMP
TIM4_RMP
12
1
read-write
TIM3_RMP
TIM3_RMP
10
2
read-write
TIM2_RMP
TIM2_RMP
8
2
read-write
TIM1_RMP
TIM1_RMP
6
2
read-write
USART3_RMP
USART3_RMP
4
2
read-write
USART2_RMP
USART2_RMP
3
1
read-write
USART1_RMP
USART1_RMP
2
1
read-write
I2C1_RMP
I2C1_RMP
1
1
read-write
SPI1_RMP
SPI1_RMP
0
1
read-write
EXTCFG1
ÍⲿÖжÏÅäÖüĴæÆ÷1
0x8
32
read-write
0x00000000
0xFFFFFFFF
EXTI3
EXTI3
12
4
read-write
EXTI2
EXTI2
8
4
read-write
EXTI1
EXTI1
4
4
read-write
EXTI0
EXTI0
0
4
read-write
EXTCFG2
ÍⲿÖжÏÅäÖüĴæÆ÷2
0xC
32
read-write
0x00000000
0xFFFFFFFF
EXTI7
EXTI7
12
4
read-write
EXTI6
EXTI6
8
4
read-write
EXTI5
EXTI5
4
4
read-write
EXTI4
EXTI4
0
4
read-write
EXTCFG3
ÍⲿÖжÏÅäÖüĴæÆ÷3
0x10
32
read-write
0x00000000
0xFFFFFFFF
EXTI11
EXTI11
12
4
read-write
EXTI10
EXTI10
8
4
read-write
EXTI9
EXTI9
4
4
read-write
EXTI8
EXTI8
0
4
read-write
EXTCFG4
ÍⲿÖжÏÅäÖüĴæÆ÷4
0x14
32
read-write
0x00000000
0xFFFFFFFF
EXTI15
EXTI15
12
4
read-write
EXTI14
EXTI14
8
4
read-write
EXTI13
EXTI13
4
4
read-write
EXTI12
EXTI12
0
4
read-write
+
\ No newline at end of file