From f1a486ebf773d002a6aa8cb078ecb5ec78eaac06 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Tue, 28 Nov 2023 16:01:36 +0100 Subject: [PATCH 01/13] added sigma delta adc --- clash-cores/clash-cores.cabal | 1 + 1 file changed, 1 insertion(+) diff --git a/clash-cores/clash-cores.cabal b/clash-cores/clash-cores.cabal index 264156f5da..e951cbafb9 100644 --- a/clash-cores/clash-cores.cabal +++ b/clash-cores/clash-cores.cabal @@ -145,6 +145,7 @@ library Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO Clash.Cores.LatticeSemi.ECP5.IO Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO + Clash.Cores.SigmaDeltaADC ghc-options: -fexpose-all-unfoldings From d935dfd4c87f63ac591ac491a28a35123d54a43c Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Tue, 28 Nov 2023 16:03:34 +0100 Subject: [PATCH 02/13] added sigma delta adc --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 138 +++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 clash-cores/src/Clash/Cores/SigmaDeltaADC.hs diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs new file mode 100644 index 0000000000..594974e110 --- /dev/null +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -0,0 +1,138 @@ +module Clash.Cores.SigmaDeltaADC where + +import Clash.Prelude hiding (filter, truncate) + +-- Shared functions +-- Function to remove the LSBs from a BitVector +truncate :: (KnownNat n0, KnownNat n1) + => BitVector (n0 + n1) + -> BitVector n0 +truncate input = output + where + (output, lsb) = split input + +-- Remove the LSBs from sigma when the rollover is high +updateAccum ::(KnownNat n0, KnownNat n1) + => BitVector n0 -- The previous accum, the state + -> (BitVector (n0 + n1), Bool) -- The input, sigma and the rollover boolean + -> (BitVector n0, BitVector n0) -- The new accum and the output +updateAccum accum (sigma, rollover) + | rollover = (sigma', accum) + | otherwise = (accum, accum) + where + sigma' = truncate sigma + +-- Accumulator + +--The main function for the accumulator +{-# NOINLINE accumulator #-} +accumulator :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, n2 <= (n1 + n0)) + => SNat n0 -- The ADC width + -> SNat (n1 + n0) -- The accumulator width + -> Signal dom (BitVector n2) -- The input from the comparator + -> Signal dom (BitVector n0, Bool) -- The accumulator output and the accumulator ready +accumulator cw aw numOnes = bundle (accum, rollover) + where + accum = mealyB updateAccum 0 (sigma, rollover) + (sigma, rollover) = unbundle (counterT aw numOnes) + + + counterT :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) => SNat n0 -> Signal dom (BitVector n1) -> Signal dom (BitVector n0, Bool) + counterT aw numOnes = mealy counter (0, False, 0, 0) numOnes + + -- The counter for sigma, which counts up when the input from the comparator is high and resets when count is equal to zero + counter :: (KnownNat n0, KnownNat n1, n1 <= n0) + => (BitVector (n0 + 1), Bool, BitVector n1, BitVector (n0 - n1 + 1)) --The current state of sigma + -> BitVector n1 --The input, and count + -> ((BitVector (n0 + 1), Bool, BitVector n1, BitVector (n0 - n1 + 1 )), (BitVector n0, Bool)) --The updated sigma and + counter (sigma, rollover, num_ones, count) num_ones' = ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) + where + count' = count + 1 + rollover' = count == 0 + + new_state + | rollover = resize num_ones + | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) + | otherwise = maxBound + + + + + +-- Box avaraging filter +{-# NOINLINE filter #-} +filter :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) + => SNat n1 -- The amount of filter bits + -> Signal dom (BitVector n0) -- The input of the filter, width is equal to the adc width + -> Signal dom Bool -- Boolean to show when the accumulator is ready + -> Signal dom (BitVector n0, Bool) -- The filtered output and the sample_rdy +filter fw data_in sample = bundle(data_out, result_valid) + where + (accumulate, latch_result, result_valid) = mealyB pipeline (False, False, False) (sample, count) + count = traceSignal1 "Filter.count" (count' fw sample) + accum = traceSignal1 "Filter.Accum" (mealyB accumulatorf 0 (count, traceSignal1 "Filter.Data_in" data_in, traceSignal1 "Filter.Accumulate" accumulate)) + data_out = traceSignal1 "Filter.data_out" (mealyB updateAccum 0 (accum, latch_result)) + + -- The accumulator for the filter, it adds the input to accum when teh sample is ready + accumulatorf :: (KnownNat n0, KnownNat n1) + => BitVector (n0 + n1) -- state of accum + -> (BitVector n1, BitVector n0, Bool) -- The main counter input, the input data, boolean for when the sample is ready + -> (BitVector (n0 + n1), BitVector (n0 + n1)) -- new state, the output + accumulatorf accum (count, data_in, accumulate) + | count == 1 && accumulate = (extend data_in, accum) + | accumulate = (accum + extend data_in, accum) + | otherwise = (accum, accum) + + + -- Pipeline to sync all the signals + pipeline :: (KnownNat n0) + => (Bool, Bool, Bool) -- + -> (Bool, BitVector n0) + -> ((Bool, Bool, Bool), (Bool, Bool, Bool)) + pipeline (sample_d1, sample_d2, latch_result) (sample, count) = ((sample_d1', sample_d2', latch_result'), (accumulate, latch_result', latch_result)) + where + sample_d1' = sample + sample_d2' = sample_d1 + accumulate = sample_d1 && not sample_d2 + latch_result' = accumulate && (count == 1) + + + -- Count when the input sample is ready + count' :: (HiddenClockResetEnable dom, KnownNat n0) + => SNat n0 -- Filter width + -> Signal dom Bool -- Sample ready boolean + -> Signal dom (BitVector n0) -- counter output + count' fw sample = output + where + output = regEn 0 sample (output + 1) + +-- Function for the sigma delta ADC +{-# NOINLINE sigmaDeltaADC #-} +sigmaDeltaADC :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, KnownNat n3, CLog 2 (n3 + 1) <= (n1 + n0)) + => SNat n0 -- ADC width + -> SNat (n0 + n1) -- Accumnulator width + -> SNat n2 -- Filter width + -> Signal dom (BitVector n3) -- analog innput from the comparator + -> Signal dom (BitVector n3, BitVector n0, Bool) -- analog output to the RC network, digital out, sample ready +sigmaDeltaADC cw aw fw analog_cmp = bundle(delta, digital_out, sample_rdy) + where + delta = register 0 analog_cmp + (accum, accum_rdy) = unbundle(accumulator cw aw numOnes) + (digital_out, sample_rdy) = unbundle(filter fw accum accum_rdy) + + numOnes = traceSignal1 "adc.numOnes" (pack <$> (countOnes <$> delta)) + + countOnes :: (KnownNat n0) + => BitVector n0 + -> Index (n0 + 1) + countOnes analog_cmp = fromInteger (toInteger(popCount analog_cmp)) + + + + + + + + + + From 32bd5c17f0f01bb4980b09cd78cc1873f5885bde Mon Sep 17 00:00:00 2001 From: FloriaanB <148322329+FloraanB@users.noreply.github.com> Date: Wed, 29 Nov 2023 09:31:11 +0100 Subject: [PATCH 03/13] Removed lattice blackboxes --- clash-cores/clash-cores.cabal | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/clash-cores/clash-cores.cabal b/clash-cores/clash-cores.cabal index e951cbafb9..1f4c2b334e 100644 --- a/clash-cores/clash-cores.cabal +++ b/clash-cores/clash-cores.cabal @@ -141,10 +141,10 @@ library Clash.Cores.Xilinx.Xpm.Cdc.Single.Internal Clash.Cores.SPI Clash.Cores.UART - Clash.Cores.LatticeSemi.ICE40.IO - Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO - Clash.Cores.LatticeSemi.ECP5.IO - Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO + -- Clash.Cores.LatticeSemi.ICE40.IO + -- Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO + -- Clash.Cores.LatticeSemi.ECP5.IO + -- Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO Clash.Cores.SigmaDeltaADC ghc-options: From 6bf5a4ca7200666f8c5110d7bf213e045d322a27 Mon Sep 17 00:00:00 2001 From: FloriaanB <148322329+FloraanB@users.noreply.github.com> Date: Wed, 29 Nov 2023 10:38:41 +0100 Subject: [PATCH 04/13] Update clash-cores.cabal --- clash-cores/clash-cores.cabal | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/clash-cores/clash-cores.cabal b/clash-cores/clash-cores.cabal index 1f4c2b334e..e951cbafb9 100644 --- a/clash-cores/clash-cores.cabal +++ b/clash-cores/clash-cores.cabal @@ -141,10 +141,10 @@ library Clash.Cores.Xilinx.Xpm.Cdc.Single.Internal Clash.Cores.SPI Clash.Cores.UART - -- Clash.Cores.LatticeSemi.ICE40.IO - -- Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO - -- Clash.Cores.LatticeSemi.ECP5.IO - -- Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO + Clash.Cores.LatticeSemi.ICE40.IO + Clash.Cores.LatticeSemi.ICE40.Blackboxes.IO + Clash.Cores.LatticeSemi.ECP5.IO + Clash.Cores.LatticeSemi.ECP5.Blackboxes.IO Clash.Cores.SigmaDeltaADC ghc-options: From 6dccf80a5c1cb04152c589c98bcf6fc9537e1744 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Wed, 29 Nov 2023 14:50:14 +0100 Subject: [PATCH 05/13] Added documentation --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 334 +++++++++++++------ 1 file changed, 233 insertions(+), 101 deletions(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index 594974e110..ea8950f96c 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -1,132 +1,264 @@ -module Clash.Cores.SigmaDeltaADC where +module SigmaDeltaADC (sigmaDeltaADC) where import Clash.Prelude hiding (filter, truncate) +-- | Sigma Delta ADC configurable in the ADC width, OSR and filter depth + +-- The frequency for the ADC is equal to clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), +-- where clk is the operating frequency of the ADC +{-# NOINLINE sigmaDeltaADC #-} +sigmaDeltaADC :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, + KnownNat n2, KnownNat n3, CLog 2 (n3 + 1) <= (n1 + n0)) + => SNat n0 + -- ^ ADC width + -> SNat (n0 + n1) + -- ^ Accumulator width + -- Has to be larger or equal to the ADC width, the OSR is equal to 2^(AccumulatorWidth - ADCwidth) + + -> SNat n2 + -- ^ Filter depth + -- The depth of the decimation filter, the downsampling rate is equal to 2^FilterDepth + + -> Signal dom (BitVector n3) + -- ^ analog input from the comparator + -- For the design either lvds or an external comparator can be used + -- the input signal had to be connected to the positive input while + -- the output from a low pass RC-network connects to the negative input. + -- The input is a bitvector such that ddr or a deserialiser can be utilised + -- to get more bits per clock cycle for an increased sampling frequency. + -> Signal dom (BitVector n3, + BitVector n0, + Bool) + -- ^ parts of the tuple + -- + -- 1. feedback to the RC network: + -- The R and C of the low pass network need to be chosen such that: + -- RC inbetween 200 and 1000 x clk, where clk is the frequency of + -- output + -- + -- 2. the digital output of the ADC + -- + -- 3. Trigger for when the output is ready + +sigmaDeltaADC adcw accumw filterw analog_cmp = bundle(delta, digital_out, sample_rdy) + where + delta = register 0 analog_cmp + (accum, accum_rdy) = unbundle(accumulator adcw accumw numOnes) + (digital_out, sample_rdy) = unbundle(filter filterw accum accum_rdy) + numOnes = pack <$> (countOnes <$> delta) + + -- Shared functions -- Function to remove the LSBs from a BitVector truncate :: (KnownNat n0, KnownNat n1) => BitVector (n0 + n1) + -- ^ entire bitvector -> BitVector n0 + -- ^ bitvector without number of LSBs truncate input = output where - (output, lsb) = split input - --- Remove the LSBs from sigma when the rollover is high -updateAccum ::(KnownNat n0, KnownNat n1) - => BitVector n0 -- The previous accum, the state - -> (BitVector (n0 + n1), Bool) -- The input, sigma and the rollover boolean - -> (BitVector n0, BitVector n0) -- The new accum and the output -updateAccum accum (sigma, rollover) + (output, _) = split input + +-- Remove the LSBs from the accumulator output when the accumulator is ready +-- This is used for both the accumulator and the filter +truncateAccum ::(KnownNat n0, KnownNat n1) + => BitVector n0 + -- The previous accum + -> (BitVector (n0 + n1), Bool) + -- ^ parts of the tuple + -- + -- 1. Accumulator output + -- 2. Boolean for when the accumulator is ready + + -> (BitVector n0, BitVector n0) + + -- ^ parts of tuple + -- + -- 1. updated accum + -- 2. output accum + +truncateAccum accum (sigma, rollover) | rollover = (sigma', accum) - | otherwise = (accum, accum) + | otherwise = (accum, accum) where sigma' = truncate sigma + +-- Function to do a popcount from the input bit vector +countOnes :: (KnownNat n0) + => BitVector n0 + -- The bitvector to do a popcount on + -> Index (n0 + 1) + -- The result as an index +countOnes analog_cmp = fromInteger (toInteger(popCount analog_cmp)) + + -- Accumulator ---The main function for the accumulator +--The main function for the accumulator, all functions that start with accumulator are used for the accumulator {-# NOINLINE accumulator #-} accumulator :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, n2 <= (n1 + n0)) - => SNat n0 -- The ADC width - -> SNat (n1 + n0) -- The accumulator width - -> Signal dom (BitVector n2) -- The input from the comparator - -> Signal dom (BitVector n0, Bool) -- The accumulator output and the accumulator ready -accumulator cw aw numOnes = bundle (accum, rollover) + => SNat n0 + -- ^ The ADC width + -> SNat (n1 + n0) + -- ^ The accumulator width + -> Signal dom (BitVector n2) + -- ^ The amount of ones from the input + -> Signal dom (BitVector n0, Bool) + -- ^ Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter + -- +accumulator _ aw numOnes = bundle (accum, rollover) where - accum = mealyB updateAccum 0 (sigma, rollover) - (sigma, rollover) = unbundle (counterT aw numOnes) - - - counterT :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) => SNat n0 -> Signal dom (BitVector n1) -> Signal dom (BitVector n0, Bool) - counterT aw numOnes = mealy counter (0, False, 0, 0) numOnes - - -- The counter for sigma, which counts up when the input from the comparator is high and resets when count is equal to zero - counter :: (KnownNat n0, KnownNat n1, n1 <= n0) - => (BitVector (n0 + 1), Bool, BitVector n1, BitVector (n0 - n1 + 1)) --The current state of sigma - -> BitVector n1 --The input, and count - -> ((BitVector (n0 + 1), Bool, BitVector n1, BitVector (n0 - n1 + 1 )), (BitVector n0, Bool)) --The updated sigma and - counter (sigma, rollover, num_ones, count) num_ones' = ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) - where - count' = count + 1 - rollover' = count == 0 - - new_state - | rollover = resize num_ones - | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) - | otherwise = maxBound - - + accum = mealyB truncateAccum 0 (sigma, rollover) + (sigma, rollover) = unbundle (accumulatorCounterT aw numOnes) + + +accumulatorCounterT :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) + => SNat n0 + -- ^ the accumulator width + -> Signal dom (BitVector n1) + -- ^ The amount of ones from the input + -> Signal dom (BitVector n0, Bool) + -- ^ Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter +accumulatorCounterT _ numOnes = mealy accumulatorCounter (0, False, 0, 0) numOnes + +-- The counter for sigma, which counts counts the number of ones from the input and resets when count is equal to zero +accumulatorCounter :: (KnownNat n0, KnownNat n1, n1 <= n0) + => (BitVector (n0 + 1), + Bool, + BitVector n1, + BitVector (n0 - n1 + 1)) + -- ^ Parts of the Tuple + -- + -- 1. The previous sigma + -- 2. bool for when sigma is ready + -- 3. previous number of ones from the input + -- 4. previous value of the main counter + + -> BitVector n1 + -- number of ones from the input + + -> ((BitVector (n0 + 1), + Bool, + BitVector n1, + BitVector (n0 - n1 + 1 )), + (BitVector n0, + Bool)) + -- ^ Parts of the Tuple + -- + -- 1. The new sigma + -- 2. bool for when sigma is ready + -- 3. new number of ones from the input + -- 4. new value of the main counter + -- 5. The accumulator output + -- 6. Accumulator ready going to the filter + -- +accumulatorCounter (sigma, rollover, num_ones, count) num_ones' + = ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) + where + count' = count + 1 + rollover' = (count == 0) + new_state + | rollover = resize num_ones + | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) + | otherwise = maxBound -- Box avaraging filter +-- All functions that start with filter are used for the box averaging filter + {-# NOINLINE filter #-} filter :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) - => SNat n1 -- The amount of filter bits - -> Signal dom (BitVector n0) -- The input of the filter, width is equal to the adc width - -> Signal dom Bool -- Boolean to show when the accumulator is ready - -> Signal dom (BitVector n0, Bool) -- The filtered output and the sample_rdy -filter fw data_in sample = bundle(data_out, result_valid) - where - (accumulate, latch_result, result_valid) = mealyB pipeline (False, False, False) (sample, count) - count = traceSignal1 "Filter.count" (count' fw sample) - accum = traceSignal1 "Filter.Accum" (mealyB accumulatorf 0 (count, traceSignal1 "Filter.Data_in" data_in, traceSignal1 "Filter.Accumulate" accumulate)) - data_out = traceSignal1 "Filter.data_out" (mealyB updateAccum 0 (accum, latch_result)) - - -- The accumulator for the filter, it adds the input to accum when teh sample is ready - accumulatorf :: (KnownNat n0, KnownNat n1) - => BitVector (n0 + n1) -- state of accum - -> (BitVector n1, BitVector n0, Bool) -- The main counter input, the input data, boolean for when the sample is ready - -> (BitVector (n0 + n1), BitVector (n0 + n1)) -- new state, the output - accumulatorf accum (count, data_in, accumulate) - | count == 1 && accumulate = (extend data_in, accum) - | accumulate = (accum + extend data_in, accum) - | otherwise = (accum, accum) - - - -- Pipeline to sync all the signals - pipeline :: (KnownNat n0) - => (Bool, Bool, Bool) -- - -> (Bool, BitVector n0) - -> ((Bool, Bool, Bool), (Bool, Bool, Bool)) - pipeline (sample_d1, sample_d2, latch_result) (sample, count) = ((sample_d1', sample_d2', latch_result'), (accumulate, latch_result', latch_result)) - where - sample_d1' = sample - sample_d2' = sample_d1 - accumulate = sample_d1 && not sample_d2 - latch_result' = accumulate && (count == 1) - - - -- Count when the input sample is ready - count' :: (HiddenClockResetEnable dom, KnownNat n0) - => SNat n0 -- Filter width - -> Signal dom Bool -- Sample ready boolean - -> Signal dom (BitVector n0) -- counter output - count' fw sample = output - where - output = regEn 0 sample (output + 1) - --- Function for the sigma delta ADC -{-# NOINLINE sigmaDeltaADC #-} -sigmaDeltaADC :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, KnownNat n3, CLog 2 (n3 + 1) <= (n1 + n0)) - => SNat n0 -- ADC width - -> SNat (n0 + n1) -- Accumnulator width - -> SNat n2 -- Filter width - -> Signal dom (BitVector n3) -- analog innput from the comparator - -> Signal dom (BitVector n3, BitVector n0, Bool) -- analog output to the RC network, digital out, sample ready -sigmaDeltaADC cw aw fw analog_cmp = bundle(delta, digital_out, sample_rdy) - where - delta = register 0 analog_cmp - (accum, accum_rdy) = unbundle(accumulator cw aw numOnes) - (digital_out, sample_rdy) = unbundle(filter fw accum accum_rdy) + => SNat n1 + -- ^ Filter Depth + -> Signal dom (BitVector n0) + -- ^ The input of the filter, width is equal to the adc width - numOnes = traceSignal1 "adc.numOnes" (pack <$> (countOnes <$> delta)) + -> Signal dom Bool + -- ^ Boolean to show when the accumulator is ready - countOnes :: (KnownNat n0) - => BitVector n0 - -> Index (n0 + 1) - countOnes analog_cmp = fromInteger (toInteger(popCount analog_cmp)) + -> Signal dom (BitVector n0, Bool) + -- ^ Parts of the tuple + -- 1. The filtered output + -- 2. trigger when a new sample is ready +filter fw data_in accumRdy = bundle(data_out, result_valid) + where + (accumulate, latch_result, result_valid) = mealyB filterPipeline (False, False, False) (accumRdy, count) + count = filterCount fw accumRdy + accum = mealyB filterAccumulator 0 (count, data_in, accumulate) + data_out = mealyB truncateAccum 0 (accum, latch_result) + +-- The accumulator for the filter, it adds the input to accum when the sample from the accumulator is ready +filterAccumulator :: (KnownNat n0, KnownNat n1) + => BitVector (n0 + n1) + -- ^ previous count of the filter accumulator + -> (BitVector n1, BitVector n0, Bool) + -- ^ Parts of the Tuple: + -- 1. The filter counter + -- 2. Input data from a filter accumulator + -- 3. boolean for when the sample from the filter accumulator is ready + -- + -> (BitVector (n0 + n1), BitVector (n0 + n1)) + -- ^ Parts of the Tuple + -- 1. the new count of the accumulator + -- 2. the downsampled output of the filter and adc +filterAccumulator accum (count, data_in, accumulate) + | count == 1 && accumulate = (extend data_in, accum) + | accumulate = (accum + extend data_in, accum) + | otherwise = (accum, accum) + + +-- filterPipeline to sync all the signals +-- contains 3 registers to determine when the filter needs to accumulate. +-- this happens when the accumulator is ready +filterPipeline :: (KnownNat n0) + => (Bool, Bool, Bool) + -- ^ parts of the tuple + -- + -- 1. accum ready with 1 cycle of delay + -- 2. accum ready with 2 cycles of delay + -- 3. latch result with 1 cycle of delay + -> (Bool, BitVector n0) + -- ^ parts of tuple + -- input of the mealy machine + -- 1. accum ready + -- 2. the main counter + -- + -> ((Bool, Bool, Bool), (Bool, Bool, Bool)) + -- ^ parts of the tuple + -- + -- 1,2,3. input for all the registers + -- 4, boolean for when the filter need to accumulate + -- 5. boolean for when the filter accumulator of ready + -- 6. boolean for when the output for the adc is ready +filterPipeline (accumRdy_d1, accumRdy_d2, latch_result) (accumRdy, count) + = ((accumRdy_d1', accumRdy_d2', latch_result'), (accumulate, latch_result', latch_result)) + where + accumRdy_d1' = accumRdy + accumRdy_d2' = accumRdy_d1 + accumulate = accumRdy_d1 && not accumRdy_d2 + latch_result' = accumulate && (count == 1) + + +-- Count when the input sample is ready it counts till 2^(filterWidth) +filterCount :: (HiddenClockResetEnable dom, KnownNat n0) + => SNat n0 + -- Filter width + -> Signal dom Bool + -- Sample ready boolean + -> Signal dom (BitVector n0) + -- counter output +filterCount _ accumRdy = output + where + output = regEn 0 accumRdy (output + 1) From a86a4ecd1f3acd6227140bd43b356b04cbba1342 Mon Sep 17 00:00:00 2001 From: FloriaanB <148322329+FloraanB@users.noreply.github.com> Date: Wed, 29 Nov 2023 14:56:03 +0100 Subject: [PATCH 06/13] Changed module name --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index ea8950f96c..137bb9a9db 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -1,4 +1,4 @@ -module SigmaDeltaADC (sigmaDeltaADC) where +module Clash.Cores.SigmaDeltaADC (sigmaDeltaADC) where import Clash.Prelude hiding (filter, truncate) From 60bfc212f1d444a1fe34323bde73d850a252702c Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Fri, 1 Dec 2023 14:20:21 +0100 Subject: [PATCH 07/13] Fixed EOL errors --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 485 +++++++++---------- 1 file changed, 238 insertions(+), 247 deletions(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index ea8950f96c..7c2aac4532 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -4,267 +4,258 @@ import Clash.Prelude hiding (filter, truncate) -- | Sigma Delta ADC configurable in the ADC width, OSR and filter depth --- The frequency for the ADC is equal to clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), +-- | The frequency for the ADC is equal to clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), -- where clk is the operating frequency of the ADC {-# NOINLINE sigmaDeltaADC #-} -sigmaDeltaADC :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, - KnownNat n2, KnownNat n3, CLog 2 (n3 + 1) <= (n1 + n0)) - => SNat n0 - -- ^ ADC width - -> SNat (n0 + n1) - -- ^ Accumulator width - -- Has to be larger or equal to the ADC width, the OSR is equal to 2^(AccumulatorWidth - ADCwidth) - - -> SNat n2 - -- ^ Filter depth - -- The depth of the decimation filter, the downsampling rate is equal to 2^FilterDepth - - -> Signal dom (BitVector n3) - -- ^ analog input from the comparator - -- For the design either lvds or an external comparator can be used - -- the input signal had to be connected to the positive input while - -- the output from a low pass RC-network connects to the negative input. - -- The input is a bitvector such that ddr or a deserialiser can be utilised - -- to get more bits per clock cycle for an increased sampling frequency. - -> Signal dom (BitVector n3, - BitVector n0, - Bool) - -- ^ parts of the tuple - -- - -- 1. feedback to the RC network: - -- The R and C of the low pass network need to be chosen such that: - -- RC inbetween 200 and 1000 x clk, where clk is the frequency of - -- output - -- - -- 2. the digital output of the ADC - -- - -- 3. Trigger for when the output is ready - -sigmaDeltaADC adcw accumw filterw analog_cmp = bundle(delta, digital_out, sample_rdy) - where - delta = register 0 analog_cmp - (accum, accum_rdy) = unbundle(accumulator adcw accumw numOnes) - (digital_out, sample_rdy) = unbundle(filter filterw accum accum_rdy) - numOnes = pack <$> (countOnes <$> delta) - - --- Shared functions +sigmaDeltaADC :: + ( HiddenClockResetEnable dom, + KnownNat n0, + KnownNat n1, + KnownNat n2, + KnownNat n3, + CLog 2 (n3 + 1) <= (n1 + n0) + ) => + -- | ADC width + SNat n0 -> + -- | Accumulator width + -- Has to be larger or equal to the ADC width, the OSR is equal to 2^(AccumulatorWidth - ADCwidth) + SNat (n0 + n1) -> + -- | Filter depth + -- The depth of the decimation filter, the downsampling rate is equal to 2^FilterDepth + SNat n2 -> + -- | analog input from the comparator + -- For the design either lvds or an external comparator can be used + -- the input signal had to be connected to the positive input while + -- the output from a low pass RC-network connects to the negative input. + -- The input is a bitvector such that ddr or a deserialiser can be utilised + -- to get more bits per clock cycle for an increased sampling frequency. + Signal dom (BitVector n3) -> + -- | parts of the tuple + -- + -- 1. feedback to the RC network: + -- The R and C of the low pass network need to be chosen such that: + -- RC inbetween 200 and 1000 x clk, where clk is the frequency of + -- output + -- + -- 2. the digital output of the ADC + -- + -- 3. Trigger for when the output is ready + Signal + dom + ( BitVector n3, + BitVector n0, + Bool + ) +sigmaDeltaADC adcw accumw filterw analog_cmp = bundle (delta, digital_out, sample_rdy) + where + delta = register 0 analog_cmp + (accum, accum_rdy) = unbundle (accumulator adcw accumw numOnes) + (digital_out, sample_rdy) = unbundle (filter filterw accum accum_rdy) + numOnes = pack <$> (countOnes <$> delta) + +-- | Shared functions -- Function to remove the LSBs from a BitVector -truncate :: (KnownNat n0, KnownNat n1) - => BitVector (n0 + n1) - -- ^ entire bitvector - -> BitVector n0 - -- ^ bitvector without number of LSBs +truncate :: + (KnownNat n0, KnownNat n1) => + -- | entire bitvector + BitVector (n0 + n1) -> + -- | bitvector without number of LSBs + BitVector n0 truncate input = output - where - (output, _) = split input + where + (output, _) = split input --- Remove the LSBs from the accumulator output when the accumulator is ready +-- | Remove the LSBs from the accumulator output when the accumulator is ready -- This is used for both the accumulator and the filter -truncateAccum ::(KnownNat n0, KnownNat n1) - => BitVector n0 - -- The previous accum - -> (BitVector (n0 + n1), Bool) - -- ^ parts of the tuple - -- - -- 1. Accumulator output - -- 2. Boolean for when the accumulator is ready - - -> (BitVector n0, BitVector n0) - - -- ^ parts of tuple - -- - -- 1. updated accum - -- 2. output accum - +truncateAccum :: + (KnownNat n0, KnownNat n1) => + BitVector n0 -> + -- The previous accum + + -- | parts of the tuple + -- + -- 1. Accumulator output + -- 2. Boolean for when the accumulator is ready + (BitVector (n0 + n1), Bool) -> + -- | parts of tuple + -- + -- 1. updated accum + -- 2. output accum + (BitVector n0, BitVector n0) truncateAccum accum (sigma, rollover) - | rollover = (sigma', accum) - | otherwise = (accum, accum) - where - sigma' = truncate sigma - - --- Function to do a popcount from the input bit vector -countOnes :: (KnownNat n0) - => BitVector n0 - -- The bitvector to do a popcount on - -> Index (n0 + 1) - -- The result as an index -countOnes analog_cmp = fromInteger (toInteger(popCount analog_cmp)) - - --- Accumulator - ---The main function for the accumulator, all functions that start with accumulator are used for the accumulator + | rollover = (sigma', accum) + | otherwise = (accum, accum) + where + sigma' = truncate sigma + +-- | Function to do a popcount from the input bit vector +countOnes :: + (KnownNat n0) => +-- | The bitvector to do a popcount on + BitVector n0 -> +-- | The result as an index + Index (n0 + 1) +countOnes analog_cmp = fromInteger (toInteger (popCount analog_cmp)) + +-- |Accumulator +-- The main function for the accumulator, all functions that start with accumulator are used for the accumulator {-# NOINLINE accumulator #-} -accumulator :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, n2 <= (n1 + n0)) - => SNat n0 - -- ^ The ADC width - -> SNat (n1 + n0) - -- ^ The accumulator width - -> Signal dom (BitVector n2) - -- ^ The amount of ones from the input - -> Signal dom (BitVector n0, Bool) - -- ^ Parts of the Tuple - -- - -- 1. The accumulator output - -- 2. Accumulator ready going to the filter - -- +accumulator :: + (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, n2 <= (n1 + n0)) => + -- | The ADC width + SNat n0 -> + -- | The accumulator width + SNat (n1 + n0) -> + -- | The amount of ones from the input + Signal dom (BitVector n2) -> + -- | Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter + Signal dom (BitVector n0, Bool) accumulator _ aw numOnes = bundle (accum, rollover) - where - accum = mealyB truncateAccum 0 (sigma, rollover) - (sigma, rollover) = unbundle (accumulatorCounterT aw numOnes) - - -accumulatorCounterT :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) - => SNat n0 - -- ^ the accumulator width - -> Signal dom (BitVector n1) - -- ^ The amount of ones from the input - -> Signal dom (BitVector n0, Bool) - -- ^ Parts of the Tuple - -- - -- 1. The accumulator output - -- 2. Accumulator ready going to the filter + where + accum = mealyB truncateAccum 0 (sigma, rollover) + (sigma, rollover) = unbundle (accumulatorCounterT aw numOnes) + +accumulatorCounterT :: + (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) => + -- | the accumulator width + SNat n0 -> + -- | The amount of ones from the input + Signal dom (BitVector n1) -> + -- | Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter + Signal dom (BitVector n0, Bool) accumulatorCounterT _ numOnes = mealy accumulatorCounter (0, False, 0, 0) numOnes --- The counter for sigma, which counts counts the number of ones from the input and resets when count is equal to zero -accumulatorCounter :: (KnownNat n0, KnownNat n1, n1 <= n0) - => (BitVector (n0 + 1), - Bool, - BitVector n1, - BitVector (n0 - n1 + 1)) - -- ^ Parts of the Tuple - -- - -- 1. The previous sigma - -- 2. bool for when sigma is ready - -- 3. previous number of ones from the input - -- 4. previous value of the main counter - - -> BitVector n1 - -- number of ones from the input - - -> ((BitVector (n0 + 1), - Bool, - BitVector n1, - BitVector (n0 - n1 + 1 )), - (BitVector n0, - Bool)) - -- ^ Parts of the Tuple - -- - -- 1. The new sigma - -- 2. bool for when sigma is ready - -- 3. new number of ones from the input - -- 4. new value of the main counter - -- 5. The accumulator output - -- 6. Accumulator ready going to the filter - -- -accumulatorCounter (sigma, rollover, num_ones, count) num_ones' - = ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) - where - count' = count + 1 - rollover' = (count == 0) - - new_state - | rollover = resize num_ones - | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) - | otherwise = maxBound - - --- Box avaraging filter --- All functions that start with filter are used for the box averaging filter - +-- | The counter for sigma, which counts counts the number of ones from the input and resets when count is equal to zero +accumulatorCounter :: + (KnownNat n0, KnownNat n1, n1 <= n0) => + -- | Parts of the Tuple + -- + -- 1. The previous sigma + -- 2. bool for when sigma is ready + -- 3. previous number of ones from the input + -- 4. previous value of the main counter + ( BitVector (n0 + 1), + Bool, + BitVector n1, + BitVector (n0 - n1 + 1) + ) -> + -- | number of ones from the input + BitVector n1 -> + -- | Parts of the Tuple + -- + -- 1. The new sigma + -- 2. bool for when sigma is ready + -- 3. new number of ones from the input + -- 4. new value of the main counter + -- 5. The accumulator output + -- 6. Accumulator ready going to the filter + ( ( BitVector (n0 + 1), + Bool, + BitVector n1, + BitVector (n0 - n1 + 1) + ), + ( BitVector n0, + Bool + ) + ) +accumulatorCounter (sigma, rollover, num_ones, count) num_ones' = + ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) + where + count' = count + 1 + rollover' = (count == 0) + + new_state + | rollover = resize num_ones + | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) + | otherwise = maxBound + +-- | Box avaraging filter +-- | All functions that start with filter are used for the box averaging filter {-# NOINLINE filter #-} -filter :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) - => SNat n1 - -- ^ Filter Depth - -> Signal dom (BitVector n0) - -- ^ The input of the filter, width is equal to the adc width - - -> Signal dom Bool - -- ^ Boolean to show when the accumulator is ready - - -> Signal dom (BitVector n0, Bool) - -- ^ Parts of the tuple - -- 1. The filtered output - -- 2. trigger when a new sample is ready - -filter fw data_in accumRdy = bundle(data_out, result_valid) - where - (accumulate, latch_result, result_valid) = mealyB filterPipeline (False, False, False) (accumRdy, count) - count = filterCount fw accumRdy - accum = mealyB filterAccumulator 0 (count, data_in, accumulate) - data_out = mealyB truncateAccum 0 (accum, latch_result) - --- The accumulator for the filter, it adds the input to accum when the sample from the accumulator is ready -filterAccumulator :: (KnownNat n0, KnownNat n1) - => BitVector (n0 + n1) - -- ^ previous count of the filter accumulator - -> (BitVector n1, BitVector n0, Bool) - -- ^ Parts of the Tuple: - -- 1. The filter counter - -- 2. Input data from a filter accumulator - -- 3. boolean for when the sample from the filter accumulator is ready - -- - -> (BitVector (n0 + n1), BitVector (n0 + n1)) - -- ^ Parts of the Tuple - -- 1. the new count of the accumulator - -- 2. the downsampled output of the filter and adc +filter :: + (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) => + -- | Filter Depth + SNat n1 -> + -- | The input of the filter, width is equal to the adc width + Signal dom (BitVector n0) -> + -- | Boolean to show when the accumulator is ready + Signal dom Bool -> + -- | Parts of the tuple + -- 1. The filtered output + -- 2. trigger when a new sample is ready + Signal dom (BitVector n0, Bool) +filter fw data_in accumRdy = bundle (data_out, result_valid) + where + (accumulate, latch_result, result_valid) = mealyB filterPipeline (False, False, False) (accumRdy, count) + count = filterCount fw accumRdy + accum = mealyB filterAccumulator 0 (count, data_in, accumulate) + data_out = mealyB truncateAccum 0 (accum, latch_result) + +-- | The accumulator for the filter, it adds the input to accum when the sample from the accumulator is ready +filterAccumulator :: + (KnownNat n0, KnownNat n1) => + -- | previous count of the filter accumulator + BitVector (n0 + n1) -> + -- | Parts of the Tuple: + -- 1. The filter counter + -- 2. Input data from a filter accumulator + -- 3. boolean for when the sample from the filter accumulator is ready + (BitVector n1, BitVector n0, Bool) -> + -- | Parts of the Tuple + -- 1. the new count of the accumulator + -- 2. the downsampled output of the filter and adc + (BitVector (n0 + n1), BitVector (n0 + n1)) filterAccumulator accum (count, data_in, accumulate) - | count == 1 && accumulate = (extend data_in, accum) - | accumulate = (accum + extend data_in, accum) - | otherwise = (accum, accum) + | count == 1 && accumulate = (extend data_in, accum) + | accumulate = (accum + extend data_in, accum) + | otherwise = (accum, accum) - --- filterPipeline to sync all the signals +-- | FilterPipeline to sync all the signals -- contains 3 registers to determine when the filter needs to accumulate. -- this happens when the accumulator is ready -filterPipeline :: (KnownNat n0) - => (Bool, Bool, Bool) - -- ^ parts of the tuple - -- - -- 1. accum ready with 1 cycle of delay - -- 2. accum ready with 2 cycles of delay - -- 3. latch result with 1 cycle of delay - -> (Bool, BitVector n0) - -- ^ parts of tuple - -- input of the mealy machine - -- 1. accum ready - -- 2. the main counter - -- - -> ((Bool, Bool, Bool), (Bool, Bool, Bool)) - -- ^ parts of the tuple - -- - -- 1,2,3. input for all the registers - -- 4, boolean for when the filter need to accumulate - -- 5. boolean for when the filter accumulator of ready - -- 6. boolean for when the output for the adc is ready -filterPipeline (accumRdy_d1, accumRdy_d2, latch_result) (accumRdy, count) - = ((accumRdy_d1', accumRdy_d2', latch_result'), (accumulate, latch_result', latch_result)) - where - accumRdy_d1' = accumRdy - accumRdy_d2' = accumRdy_d1 - accumulate = accumRdy_d1 && not accumRdy_d2 - latch_result' = accumulate && (count == 1) - - --- Count when the input sample is ready it counts till 2^(filterWidth) -filterCount :: (HiddenClockResetEnable dom, KnownNat n0) - => SNat n0 - -- Filter width - -> Signal dom Bool - -- Sample ready boolean - -> Signal dom (BitVector n0) - -- counter output +filterPipeline :: + (KnownNat n0) => + -- | parts of the tuple + -- + -- 1. accum ready with 1 cycle of delay + -- 2. accum ready with 2 cycles of delay + -- 3. latch result with 1 cycle of delay + (Bool, Bool, Bool) -> + -- | parts of tuple + -- input of the mealy machine + -- 1. accum ready + -- 2. the main counter + (Bool, BitVector n0) -> + -- | parts of the tuple + -- + -- 1,2,3. input for all the registers + -- 4, boolean for when the filter need to accumulate + -- 5. boolean for when the filter accumulator of ready + -- 6. boolean for when the output for the adc is ready + ((Bool, Bool, Bool), (Bool, Bool, Bool)) +filterPipeline (accumRdy_d1, accumRdy_d2, latch_result) (accumRdy, count) = + ((accumRdy_d1', accumRdy_d2', latch_result'), (accumulate, latch_result', latch_result)) + where + accumRdy_d1' = accumRdy + accumRdy_d2' = accumRdy_d1 + accumulate = accumRdy_d1 && not accumRdy_d2 + latch_result' = accumulate && (count == 1) + +-- | Count when the input sample is ready it counts till 2^(filterWidth) +filterCount :: + (HiddenClockResetEnable dom, KnownNat n0) => + SNat n0 -> + -- | Filter width + Signal dom Bool -> + -- | Sample ready boolean + Signal dom (BitVector n0) + -- | Counter output filterCount _ accumRdy = output - where - output = regEn 0 accumRdy (output + 1) - - - - - - - - - + where + output = regEn 0 accumRdy (output + 1) From a19cefac9252b043d3547d8d4117239d8d8861f2 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Mon, 4 Dec 2023 11:56:21 +0100 Subject: [PATCH 08/13] Adjsuted Style --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 261 ----------------- .../Cores/LatticeSemi/ECP5/Blackboxes/IO.hs | 0 .../src/Clash/Cores/LatticeSemi/ECP5/IO.hs | 0 .../Cores/LatticeSemi/ICE40/Blackboxes/IO.hs | 0 .../src/Clash/Cores/LatticeSemi/ICE40/IO.hs | 0 clash-cores/{ => test}/src/Clash/Cores/SPI.hs | 0 .../test/src/Clash/Cores/SigmaDeltaADC.hs | 270 ++++++++++++++++++ .../{ => test}/src/Clash/Cores/UART.hs | 0 .../src/Clash/Cores/Xilinx/BlockRam.hs | 0 .../Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs | 0 .../Clash/Cores/Xilinx/BlockRam/Internal.hs | 0 .../src/Clash/Cores/Xilinx/DcFifo.hs | 0 .../Xilinx/DcFifo/Internal/BlackBoxes.hs | 0 .../Cores/Xilinx/DcFifo/Internal/Instances.hs | 0 .../Cores/Xilinx/DcFifo/Internal/Types.hs | 0 .../src/Clash/Cores/Xilinx/Floating.hs | 0 .../Cores/Xilinx/Floating/Annotations.hs | 0 .../Clash/Cores/Xilinx/Floating/BlackBoxes.hs | 0 .../Clash/Cores/Xilinx/Floating/Explicit.hs | 0 .../Clash/Cores/Xilinx/Floating/Internal.hs | 0 .../{ => test}/src/Clash/Cores/Xilinx/Ila.hs | 0 .../src/Clash/Cores/Xilinx/Ila/Internal.hs | 0 .../src/Clash/Cores/Xilinx/Internal.hs | 0 .../{ => test}/src/Clash/Cores/Xilinx/VIO.hs | 0 .../Cores/Xilinx/VIO/Internal/BlackBoxes.hs | 0 .../{ => test}/src/Clash/Cores/Xilinx/Xpm.hs | 0 .../src/Clash/Cores/Xilinx/Xpm/Cdc.hs | 0 .../Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs | 0 .../Xilinx/Xpm/Cdc/ArraySingle/Internal.hs | 0 .../src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs | 0 .../Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs | 0 .../Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs | 0 .../Xilinx/Xpm/Cdc/Handshake/Internal.hs | 0 .../src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs | 0 .../Cores/Xilinx/Xpm/Cdc/Single/Internal.hs | 0 35 files changed, 270 insertions(+), 261 deletions(-) delete mode 100644 clash-cores/src/Clash/Cores/SigmaDeltaADC.hs rename clash-cores/{ => test}/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/LatticeSemi/ECP5/IO.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/LatticeSemi/ICE40/IO.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/SPI.hs (100%) create mode 100644 clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs rename clash-cores/{ => test}/src/Clash/Cores/UART.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/BlockRam.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/BlockRam/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/DcFifo.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Floating.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Floating/Annotations.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Floating/Explicit.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Floating/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Ila.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Ila/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/VIO.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs (100%) rename clash-cores/{ => test}/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs (100%) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs deleted file mode 100644 index 9d4ff8b94a..0000000000 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ /dev/null @@ -1,261 +0,0 @@ -module Clash.Cores.SigmaDeltaADC (sigmaDeltaADC) where - -import Clash.Prelude hiding (filter, truncate) - --- | Sigma Delta ADC configurable in the ADC width, OSR and filter depth - --- | The frequency for the ADC is equal to clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), --- where clk is the operating frequency of the ADC -{-# NOINLINE sigmaDeltaADC #-} -sigmaDeltaADC :: - ( HiddenClockResetEnable dom, - KnownNat n0, - KnownNat n1, - KnownNat n2, - KnownNat n3, - CLog 2 (n3 + 1) <= (n1 + n0) - ) => - -- | ADC width - SNat n0 -> - -- | Accumulator width - -- Has to be larger or equal to the ADC width, the OSR is equal to 2^(AccumulatorWidth - ADCwidth) - SNat (n0 + n1) -> - -- | Filter depth - -- The depth of the decimation filter, the downsampling rate is equal to 2^FilterDepth - SNat n2 -> - -- | analog input from the comparator - -- For the design either lvds or an external comparator can be used - -- the input signal had to be connected to the positive input while - -- the output from a low pass RC-network connects to the negative input. - -- The input is a bitvector such that ddr or a deserialiser can be utilised - -- to get more bits per clock cycle for an increased sampling frequency. - Signal dom (BitVector n3) -> - -- | parts of the tuple - -- - -- 1. feedback to the RC network: - -- The R and C of the low pass network need to be chosen such that: - -- RC inbetween 200 and 1000 x clk, where clk is the frequency of - -- output - -- - -- 2. the digital output of the ADC - -- - -- 3. Trigger for when the output is ready - Signal - dom - ( BitVector n3, - BitVector n0, - Bool - ) -sigmaDeltaADC adcw accumw filterw analog_cmp = bundle (delta, digital_out, sample_rdy) - where - delta = register 0 analog_cmp - (accum, accum_rdy) = unbundle (accumulator adcw accumw numOnes) - (digital_out, sample_rdy) = unbundle (filter filterw accum accum_rdy) - numOnes = pack <$> (countOnes <$> delta) - --- | Shared functions --- Function to remove the LSBs from a BitVector -truncate :: - (KnownNat n0, KnownNat n1) => - -- | entire bitvector - BitVector (n0 + n1) -> - -- | bitvector without number of LSBs - BitVector n0 -truncate input = output - where - (output, _) = split input - --- | Remove the LSBs from the accumulator output when the accumulator is ready --- This is used for both the accumulator and the filter -truncateAccum :: - (KnownNat n0, KnownNat n1) => - BitVector n0 -> - -- The previous accum - - -- | parts of the tuple - -- - -- 1. Accumulator output - -- 2. Boolean for when the accumulator is ready - (BitVector (n0 + n1), Bool) -> - -- | parts of tuple - -- - -- 1. updated accum - -- 2. output accum - (BitVector n0, BitVector n0) -truncateAccum accum (sigma, rollover) - | rollover = (sigma', accum) - | otherwise = (accum, accum) - where - sigma' = truncate sigma - --- | Function to do a popcount from the input bit vector -countOnes :: - (KnownNat n0) => --- | The bitvector to do a popcount on - BitVector n0 -> --- | The result as an index - Index (n0 + 1) -countOnes analog_cmp = fromInteger (toInteger (popCount analog_cmp)) - --- |Accumulator --- The main function for the accumulator, all functions that start with accumulator are used for the accumulator -{-# NOINLINE accumulator #-} -accumulator :: - (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, KnownNat n2, n2 <= (n1 + n0)) => - -- | The ADC width - SNat n0 -> - -- | The accumulator width - SNat (n1 + n0) -> - -- | The amount of ones from the input - Signal dom (BitVector n2) -> - -- | Parts of the Tuple - -- - -- 1. The accumulator output - -- 2. Accumulator ready going to the filter - Signal dom (BitVector n0, Bool) -accumulator _ aw numOnes = bundle (accum, rollover) - where - accum = mealyB truncateAccum 0 (sigma, rollover) - (sigma, rollover) = unbundle (accumulatorCounterT aw numOnes) - -accumulatorCounterT :: - (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1, n1 <= n0) => - -- | the accumulator width - SNat n0 -> - -- | The amount of ones from the input - Signal dom (BitVector n1) -> - -- | Parts of the Tuple - -- - -- 1. The accumulator output - -- 2. Accumulator ready going to the filter - Signal dom (BitVector n0, Bool) -accumulatorCounterT _ numOnes = mealy accumulatorCounter (0, False, 0, 0) numOnes - --- | The counter for sigma, which counts counts the number of ones from the input and resets when count is equal to zero -accumulatorCounter :: - (KnownNat n0, KnownNat n1, n1 <= n0) => - -- | Parts of the Tuple - -- - -- 1. The previous sigma - -- 2. bool for when sigma is ready - -- 3. previous number of ones from the input - -- 4. previous value of the main counter - ( BitVector (n0 + 1), - Bool, - BitVector n1, - BitVector (n0 - n1 + 1) - ) -> - -- | number of ones from the input - BitVector n1 -> - -- | Parts of the Tuple - -- - -- 1. The new sigma - -- 2. bool for when sigma is ready - -- 3. new number of ones from the input - -- 4. new value of the main counter - -- 5. The accumulator output - -- 6. Accumulator ready going to the filter - ( ( BitVector (n0 + 1), - Bool, - BitVector n1, - BitVector (n0 - n1 + 1) - ), - ( BitVector n0, - Bool - ) - ) -accumulatorCounter (sigma, rollover, num_ones, count) num_ones' = - ((new_state, rollover', num_ones', count'), (resize sigma, rollover)) - where - count' = count + 1 - rollover' = (count == 0) - - new_state - | rollover = resize num_ones - | sigma /= maxBound = min (sigma + resize num_ones) (shiftR maxBound 1) - | otherwise = maxBound - --- | Box avaraging filter --- | All functions that start with filter are used for the box averaging filter -{-# NOINLINE filter #-} -filter :: - (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) => - -- | Filter Depth - SNat n1 -> - -- | The input of the filter, width is equal to the adc width - Signal dom (BitVector n0) -> - -- | Boolean to show when the accumulator is ready - Signal dom Bool -> - -- | Parts of the tuple - -- 1. The filtered output - -- 2. trigger when a new sample is ready - Signal dom (BitVector n0, Bool) -filter fw data_in accumRdy = bundle (data_out, result_valid) - where - (accumulate, latch_result, result_valid) = mealyB filterPipeline (False, False, False) (accumRdy, count) - count = filterCount fw accumRdy - accum = mealyB filterAccumulator 0 (count, data_in, accumulate) - data_out = mealyB truncateAccum 0 (accum, latch_result) - --- | The accumulator for the filter, it adds the input to accum when the sample from the accumulator is ready -filterAccumulator :: - (KnownNat n0, KnownNat n1) => - -- | previous count of the filter accumulator - BitVector (n0 + n1) -> - -- | Parts of the Tuple: - -- 1. The filter counter - -- 2. Input data from a filter accumulator - -- 3. boolean for when the sample from the filter accumulator is ready - (BitVector n1, BitVector n0, Bool) -> - -- | Parts of the Tuple - -- 1. the new count of the accumulator - -- 2. the downsampled output of the filter and adc - (BitVector (n0 + n1), BitVector (n0 + n1)) -filterAccumulator accum (count, data_in, accumulate) - | count == 1 && accumulate = (extend data_in, accum) - | accumulate = (accum + extend data_in, accum) - | otherwise = (accum, accum) - --- | FilterPipeline to sync all the signals --- contains 3 registers to determine when the filter needs to accumulate. --- this happens when the accumulator is ready -filterPipeline :: - (KnownNat n0) => - -- | parts of the tuple - -- - -- 1. accum ready with 1 cycle of delay - -- 2. accum ready with 2 cycles of delay - -- 3. latch result with 1 cycle of delay - (Bool, Bool, Bool) -> - -- | parts of tuple - -- input of the mealy machine - -- 1. accum ready - -- 2. the main counter - (Bool, BitVector n0) -> - -- | parts of the tuple - -- - -- 1,2,3. input for all the registers - -- 4, boolean for when the filter need to accumulate - -- 5. boolean for when the filter accumulator of ready - -- 6. boolean for when the output for the adc is ready - ((Bool, Bool, Bool), (Bool, Bool, Bool)) -filterPipeline (accumRdy_d1, accumRdy_d2, latch_result) (accumRdy, count) = - ((accumRdy_d1', accumRdy_d2', latch_result'), (accumulate, latch_result', latch_result)) - where - accumRdy_d1' = accumRdy - accumRdy_d2' = accumRdy_d1 - accumulate = accumRdy_d1 && not accumRdy_d2 - latch_result' = accumulate && (count == 1) - --- | Count when the input sample is ready it counts till 2^(filterWidth) -filterCount :: - (HiddenClockResetEnable dom, KnownNat n0) => - SNat n0 -> - -- | Filter width - Signal dom Bool -> - -- | Sample ready boolean - Signal dom (BitVector n0) - -- | Counter output -filterCount _ accumRdy = output - where - output = regEn 0 accumRdy (output + 1) diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs b/clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs similarity index 100% rename from clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs rename to clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs b/clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/IO.hs similarity index 100% rename from clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs rename to clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/IO.hs diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs b/clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs similarity index 100% rename from clash-cores/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs rename to clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs diff --git a/clash-cores/src/Clash/Cores/LatticeSemi/ICE40/IO.hs b/clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/IO.hs similarity index 100% rename from clash-cores/src/Clash/Cores/LatticeSemi/ICE40/IO.hs rename to clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/IO.hs diff --git a/clash-cores/src/Clash/Cores/SPI.hs b/clash-cores/test/src/Clash/Cores/SPI.hs similarity index 100% rename from clash-cores/src/Clash/Cores/SPI.hs rename to clash-cores/test/src/Clash/Cores/SPI.hs diff --git a/clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs new file mode 100644 index 0000000000..8fc7568312 --- /dev/null +++ b/clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs @@ -0,0 +1,270 @@ +module SigmaDeltaADC (sigmaDeltaADC) where + +import Clash.Prelude hiding (filter, truncate) + +-- | Shared functions +-- Function to remove the LSBs from a BitVector +truncate + :: (KnownNat n0, KnownNat n1) + => BitVector (n0 + n1) + -- ^ entire bitvector + -> BitVector n0 + -- ^ bitvector without number of LSBs +truncate input = output + where + (output, _) = split input + +-- | Remove the LSBs from the accumulator output when the accumulator is ready +-- This is used for both the accumulator and the filter +truncateAccum + :: (KnownNat n0, KnownNat n1) + => BitVector n0 + -- ^ The previous accum + -> (BitVector (n0 + n1), Bool) + -- ^ parts of the tuple + -- + -- 1. Accumulator output + -- 2. Boolean for when the accumulator is ready + -> (BitVector n0, BitVector n0) + -- ^ parts of tuple + -- + -- 1. updated accum + -- 2. output accum +truncateAccum accum (sigma, rollover) + | rollover = (sigma', accum) + | otherwise = (accum, accum) + where + sigma' = truncate sigma + +-- | Function to do a popcount from the input bit vector +countOnes + :: (KnownNat n0) + => BitVector n0 + -- ^ The bitvector to do a popcount on + -> Index (n0 + 1) + -- ^ The result as an index +countOnes analogCmp = toEnum (popCount analogCmp) + +-- |Accumulator +-- The main function for the accumulator, +-- all functions that start with accumulator are used for the accumulator +accumulator + :: ( HiddenClockResetEnable dom + , KnownNat n0 + , KnownNat n1 + , KnownNat n2 + , n2 <= (n1 + n0)) + => SNat n0 + -- ^ The ADC width + -> SNat (n1 + n0) + -- ^ The accumulator width + -> Signal dom (BitVector n2) + -- ^ The amount of ones from the input + -> (Signal dom (BitVector n0) + , Signal dom Bool) + -- ^ Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter +accumulator _ aw numOnes = (accum, rollover) + where + accum = mealyB truncateAccum 0 (sigma, rollover) + (sigma, rollover) = accumulatorCounterT aw numOnes + +accumulatorCounterT + :: ( HiddenClockResetEnable dom + , KnownNat n0 + , KnownNat n1 + , n1 <= n0) + => SNat n0 + -- ^ the accumulator width + -> Signal dom (BitVector n1) + -- ^ The amount of ones from the input + -> ( Signal dom (BitVector n0) + , Signal dom Bool) + -- ^ Parts of the Tuple + -- + -- 1. The accumulator output + -- 2. Accumulator ready going to the filter +accumulatorCounterT _ numOnes = mealyB accumulatorCounter (0, False, 0, 0) numOnes + +-- | The counter for sigma, which counts counts the number of ones from +-- the input and resets when count is equal to zero +accumulatorCounter + :: (KnownNat n0, KnownNat n1, n1 <= n0) + => ( BitVector (n0 + 1) + , Bool + , BitVector n1 + , BitVector (n0 - n1 + 1)) + -- ^ Parts of the Tuple + -- + -- 1. The previous sigma + -- 2. bool for when sigma is ready + -- 3. previous number of ones from the input + -- 4. previous value of the main counter-> BitVector n1 + -> BitVector n1 + -- ^ number of ones from the input + -> ( ( BitVector (n0 + 1) + , Bool + , BitVector n1 + , BitVector (n0 - n1 + 1)) + , ( BitVector n0 + , Bool) + ) + -- ^ Parts of the Tuple + -- + -- 1. The new sigma + -- 2. bool for when sigma is ready + -- 3. new number of ones from the input + -- 4. new value of the main counter + -- 5. The accumulator output + -- 6. Accumulator ready going to the filter +accumulatorCounter (sigma, rollover, numOnes, count) numOnes' = + ((newState, rollover', numOnes', count'), (resize sigma, rollover)) + where + count' = count + 1 + rollover' = (count == 0) + newState + | rollover = resize numOnes + | sigma /= maxBound = min (sigma + resize numOnes) (shiftR maxBound 1) + | otherwise = maxBound + +-- | Box avaraging filter +-- | All functions that start with filter are used for the box averaging filter +filter + :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) + => SNat n1 + -- ^ Filter Depth + -> Signal dom (BitVector n0) + -- ^ The input of the filter, width is equal to the adc width + -> Signal dom Bool + -- ^ Boolean to show when the accumulator is ready + -> ( Signal dom (BitVector n0) + , Signal dom Bool) + -- ^ Parts of the tuple + -- 1. The filtered output + -- 2. trigger when a new sample is ready +filter fw dataIn accumRdy = (dataOut, resultValid) + where + (accumulate, latchResult, resultValid) = + mealyB filterPipeline (False, False, False) (accumRdy, count) + count = filterCount fw accumRdy + accum = mealyB filterAccumulator 0 (count, dataIn, accumulate) + dataOut = mealyB truncateAccum 0 (accum, latchResult) + +-- | The accumulator for the filter, it adds the input to accum when +-- the sample from the accumulator is ready +filterAccumulator + :: (KnownNat n0, KnownNat n1) + => BitVector (n0 + n1) + -- ^ previous count of the filter accumulator + -> (BitVector n1, BitVector n0, Bool) + -- ^ Parts of the Tuple: + -- 1. The filter counter + -- 2. Input data from a filter accumulator + -- 3. boolean for when the sample from the filter accumulator is ready + -> (BitVector (n0 + n1), BitVector (n0 + n1)) + -- ^ Parts of the Tuple + -- 1. the new count of the accumulator + -- 2. the downsampled output of the filter and adc +filterAccumulator accum (count, dataIn, accumulate) + | count == 1 && accumulate = (extend dataIn, accum) + | accumulate = (accum + extend dataIn, accum) + | otherwise = (accum, accum) + +-- | FilterPipeline to sync all the signals +-- contains 3 registers to determine when the filter needs to accumulate. +-- this happens when the accumulator is ready +filterPipeline + :: (KnownNat n0) + => (Bool, Bool, Bool) + -- ^ parts of the tuple + -- + -- 1. accum ready with 1 cycle of delay + -- 2. accum ready with 2 cycles of delay + -- 3. latch result with 1 cycle of delay + -> (Bool, BitVector n0) + -- ^ parts of tuple + -- input of the mealy machine + -- 1. accum ready + -- 2. the main counter + -> ( (Bool, Bool, Bool), + (Bool, Bool, Bool)) + -- ^ parts of the tuple + -- + -- 1,2,3. input for all the registers + -- 4, boolean for when the filter need to accumulate + -- 5. boolean for when the filter accumulator of ready + -- 6. boolean for when the output for the adc is ready +filterPipeline (accumRdyD1, accumRdyD2, latchResult) (accumRdy, count) = + ( (accumRdyD1', accumRdyD2', latchResult') + , (accumulate, latchResult', latchResult)) + where + accumRdyD1' = accumRdy + accumRdyD2' = accumRdyD1 + accumulate = accumRdyD1 && not accumRdyD2 + latchResult' = accumulate && (count == 1) + +-- | Count when the input sample is ready it counts till 2^(filterWidth) +filterCount + :: (HiddenClockResetEnable dom, KnownNat n0) + => SNat n0 + -- ^ Filter width + -> Signal dom Bool + -- ^ Sample ready boolean + -> Signal dom (BitVector n0) + -- ^ Counter output +filterCount _ accumRdy = output + where + output = regEn 0 accumRdy (output + 1) + +-- | Sigma Delta ADC configurable in the ADC width, OSR and filter depth +-- +-- | The frequency for the ADC is equal to +-- clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), +-- where clk is the operating frequency of the ADC +sigmaDeltaADC + :: ( HiddenClockResetEnable dom + , KnownNat n0 + , KnownNat n1 + , KnownNat n2 + , KnownNat n3 + , CLog 2 (n3 + 1) <= (n1 + n0) + ) + => SNat n0 + -- ^ ADC width + -> SNat (n0 + n1) + -- ^ Accumulator width + -- Has to be larger or equal to the ADC width, + -- the OSR is equal to 2^(AccumulatorWidth - ADCwidth) + -> SNat n2 + -- ^ Filter depth + -- The depth of the decimation filter, + -- the downsampling rate is equal to 2^FilterDepth + -> Signal dom (BitVector n3) + -- ^ analog input from the comparator + -- For the design either lvds or an external comparator can be used + -- the input signal had to be connected to the positive input while + -- the output from a low pass RC-network connects to the negative input. + -- The input is a bitvector such that ddr or a deserialiser can be utilised + -- to get more bits per clock cycle for an increased sampling frequency. + -> ( Signal dom (BitVector n3) + , Signal dom (BitVector n0) + , Signal dom Bool + ) + -- ^ parts of the tuple + -- + -- 1. feedback to the RC network: + -- The R and C of the low pass network need to be chosen such that: + -- RC inbetween 200 and 1000 x clk, where clk is the frequency of + -- output + -- + -- 2. the digital output of the ADC + -- + -- 3. Trigger for when the output is ready +sigmaDeltaADC adcw accumw filterw analogCmp = (delta, digitalOut, sampleRdy) + where + delta = register 0 analogCmp + (accum, accumRdy) = accumulator adcw accumw numOnes + (digitalOut, sampleRdy) = filter filterw accum accumRdy + numOnes = pack <$> (countOnes <$> delta) diff --git a/clash-cores/src/Clash/Cores/UART.hs b/clash-cores/test/src/Clash/Cores/UART.hs similarity index 100% rename from clash-cores/src/Clash/Cores/UART.hs rename to clash-cores/test/src/Clash/Cores/UART.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs b/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/BlockRam.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs b/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs b/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/DcFifo.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs b/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs b/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs b/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Floating.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Floating.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Floating.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Annotations.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Floating/Annotations.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating/Explicit.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Explicit.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Floating/Explicit.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Floating/Explicit.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Floating/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Floating/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Floating/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Ila.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Ila.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Ila.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Ila.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Ila/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Ila/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Ila/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Ila/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/VIO.hs b/clash-cores/test/src/Clash/Cores/Xilinx/VIO.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/VIO.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/VIO.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs b/clash-cores/test/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs diff --git a/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs b/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs similarity index 100% rename from clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs rename to clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs From e0b303176ed0a9725535dd162f4e86ba6ab3a41f Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Mon, 4 Dec 2023 11:57:54 +0100 Subject: [PATCH 09/13] Moved src to clash-cores --- .../{test => }/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs | 0 clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ECP5/IO.hs | 0 .../{test => }/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs | 0 clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ICE40/IO.hs | 0 clash-cores/{test => }/src/Clash/Cores/SPI.hs | 0 clash-cores/{test => }/src/Clash/Cores/SigmaDeltaADC.hs | 0 clash-cores/{test => }/src/Clash/Cores/UART.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/BlockRam.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/BlockRam/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/DcFifo.hs | 0 .../src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs | 0 .../src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Floating/Annotations.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Floating/Explicit.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Floating/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Ila.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Ila/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/VIO.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs | 0 .../src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs | 0 .../src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs | 0 clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs | 0 .../{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs | 0 34 files changed, 0 insertions(+), 0 deletions(-) rename clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ECP5/IO.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/LatticeSemi/ICE40/IO.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/SPI.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/SigmaDeltaADC.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/UART.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/BlockRam.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/BlockRam/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/DcFifo.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating/Annotations.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating/Explicit.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Floating/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Ila.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Ila/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/VIO.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs (100%) rename clash-cores/{test => }/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs (100%) diff --git a/clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs rename to clash-cores/src/Clash/Cores/LatticeSemi/ECP5/Blackboxes/IO.hs diff --git a/clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/LatticeSemi/ECP5/IO.hs rename to clash-cores/src/Clash/Cores/LatticeSemi/ECP5/IO.hs diff --git a/clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs rename to clash-cores/src/Clash/Cores/LatticeSemi/ICE40/Blackboxes/IO.hs diff --git a/clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/IO.hs b/clash-cores/src/Clash/Cores/LatticeSemi/ICE40/IO.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/LatticeSemi/ICE40/IO.hs rename to clash-cores/src/Clash/Cores/LatticeSemi/ICE40/IO.hs diff --git a/clash-cores/test/src/Clash/Cores/SPI.hs b/clash-cores/src/Clash/Cores/SPI.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/SPI.hs rename to clash-cores/src/Clash/Cores/SPI.hs diff --git a/clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/SigmaDeltaADC.hs rename to clash-cores/src/Clash/Cores/SigmaDeltaADC.hs diff --git a/clash-cores/test/src/Clash/Cores/UART.hs b/clash-cores/src/Clash/Cores/UART.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/UART.hs rename to clash-cores/src/Clash/Cores/UART.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/BlockRam.hs rename to clash-cores/src/Clash/Cores/Xilinx/BlockRam.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs rename to clash-cores/src/Clash/Cores/Xilinx/BlockRam/BlackBoxes.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/BlockRam/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/BlockRam/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/DcFifo.hs rename to clash-cores/src/Clash/Cores/Xilinx/DcFifo.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs rename to clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/BlackBoxes.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs rename to clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Instances.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs b/clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs rename to clash-cores/src/Clash/Cores/Xilinx/DcFifo/Internal/Types.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Floating.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Floating.hs rename to clash-cores/src/Clash/Cores/Xilinx/Floating.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Annotations.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Floating/Annotations.hs rename to clash-cores/src/Clash/Cores/Xilinx/Floating/Annotations.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs rename to clash-cores/src/Clash/Cores/Xilinx/Floating/BlackBoxes.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Explicit.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating/Explicit.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Floating/Explicit.hs rename to clash-cores/src/Clash/Cores/Xilinx/Floating/Explicit.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Floating/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Floating/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Floating/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Floating/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Ila.hs b/clash-cores/src/Clash/Cores/Xilinx/Ila.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Ila.hs rename to clash-cores/src/Clash/Cores/Xilinx/Ila.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Ila/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Ila/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Ila/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Ila/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/VIO.hs b/clash-cores/src/Clash/Cores/Xilinx/VIO.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/VIO.hs rename to clash-cores/src/Clash/Cores/Xilinx/VIO.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs b/clash-cores/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs rename to clash-cores/src/Clash/Cores/Xilinx/VIO/Internal/BlackBoxes.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/ArraySingle/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Gray/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Handshake/Internal.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single.hs diff --git a/clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs b/clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs similarity index 100% rename from clash-cores/test/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs rename to clash-cores/src/Clash/Cores/Xilinx/Xpm/Cdc/Single/Internal.hs From da03db9420217f48b89cc92713c84f7d8dd27d1e Mon Sep 17 00:00:00 2001 From: FloriaanB <148322329+FloriaanB@users.noreply.github.com> Date: Mon, 4 Dec 2023 11:59:38 +0100 Subject: [PATCH 10/13] Update SigmaDeltaADC.hs --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index 8fc7568312..2241a57ee9 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -1,4 +1,4 @@ -module SigmaDeltaADC (sigmaDeltaADC) where +module Clash.Cores.SigmaDeltaADC (sigmaDeltaADC) where import Clash.Prelude hiding (filter, truncate) From e3d6728cb57de10c1c2216882acff974c4c40f35 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Wed, 6 Dec 2023 12:26:40 +0100 Subject: [PATCH 11/13] Changes popCount to popCountBV --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 44 ++++++++------------ 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index 8fc7568312..e6777fc8f8 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -1,6 +1,7 @@ -module SigmaDeltaADC (sigmaDeltaADC) where +module Clash.Cores.SigmaDeltaADC (sigmaDeltaADC) where import Clash.Prelude hiding (filter, truncate) +import Clash.Sized.Internal.BitVector -- | Shared functions -- Function to remove the LSBs from a BitVector @@ -16,7 +17,7 @@ truncate input = output -- | Remove the LSBs from the accumulator output when the accumulator is ready -- This is used for both the accumulator and the filter -truncateAccum +truncateAccum :: (KnownNat n0, KnownNat n1) => BitVector n0 -- ^ The previous accum @@ -36,25 +37,16 @@ truncateAccum accum (sigma, rollover) where sigma' = truncate sigma --- | Function to do a popcount from the input bit vector -countOnes - :: (KnownNat n0) - => BitVector n0 - -- ^ The bitvector to do a popcount on - -> Index (n0 + 1) - -- ^ The result as an index -countOnes analogCmp = toEnum (popCount analogCmp) - -- |Accumulator -- The main function for the accumulator, -- all functions that start with accumulator are used for the accumulator -accumulator +accumulator :: ( HiddenClockResetEnable dom , KnownNat n0 , KnownNat n1 , KnownNat n2 - , n2 <= (n1 + n0)) - => SNat n0 + , (n2) <= (n1 + n0)) + => SNat n0 -- ^ The ADC width -> SNat (n1 + n0) -- ^ The accumulator width @@ -88,7 +80,7 @@ accumulatorCounterT -- 2. Accumulator ready going to the filter accumulatorCounterT _ numOnes = mealyB accumulatorCounter (0, False, 0, 0) numOnes --- | The counter for sigma, which counts counts the number of ones from +-- | The counter for sigma, which counts counts the number of ones from -- the input and resets when count is equal to zero accumulatorCounter :: (KnownNat n0, KnownNat n1, n1 <= n0) @@ -101,7 +93,7 @@ accumulatorCounter -- 1. The previous sigma -- 2. bool for when sigma is ready -- 3. previous number of ones from the input - -- 4. previous value of the main counter-> BitVector n1 + -- 4. previous value of the main counter-> BitVector n1 -> BitVector n1 -- ^ number of ones from the input -> ( ( BitVector (n0 + 1) @@ -131,7 +123,7 @@ accumulatorCounter (sigma, rollover, numOnes, count) numOnes' = -- | Box avaraging filter -- | All functions that start with filter are used for the box averaging filter -filter +filter :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) => SNat n1 -- ^ Filter Depth @@ -146,13 +138,13 @@ filter -- 2. trigger when a new sample is ready filter fw dataIn accumRdy = (dataOut, resultValid) where - (accumulate, latchResult, resultValid) = + (accumulate, latchResult, resultValid) = mealyB filterPipeline (False, False, False) (accumRdy, count) count = filterCount fw accumRdy accum = mealyB filterAccumulator 0 (count, dataIn, accumulate) dataOut = mealyB truncateAccum 0 (accum, latchResult) --- | The accumulator for the filter, it adds the input to accum when +-- | The accumulator for the filter, it adds the input to accum when -- the sample from the accumulator is ready filterAccumulator :: (KnownNat n0, KnownNat n1) @@ -229,26 +221,26 @@ sigmaDeltaADC , KnownNat n1 , KnownNat n2 , KnownNat n3 - , CLog 2 (n3 + 1) <= (n1 + n0) - ) + , CLog 2 (n3 + 2) <= (n1 + n0) + ) => SNat n0 -- ^ ADC width -> SNat (n0 + n1) -- ^ Accumulator width - -- Has to be larger or equal to the ADC width, + -- Has to be larger or equal to the ADC width, -- the OSR is equal to 2^(AccumulatorWidth - ADCwidth) -> SNat n2 -- ^ Filter depth - -- The depth of the decimation filter, + -- The depth of the decimation filter, -- the downsampling rate is equal to 2^FilterDepth - -> Signal dom (BitVector n3) + -> Signal dom (BitVector (n3 + 1)) -- ^ analog input from the comparator -- For the design either lvds or an external comparator can be used -- the input signal had to be connected to the positive input while -- the output from a low pass RC-network connects to the negative input. -- The input is a bitvector such that ddr or a deserialiser can be utilised -- to get more bits per clock cycle for an increased sampling frequency. - -> ( Signal dom (BitVector n3) + -> ( Signal dom (BitVector (n3 + 1)) , Signal dom (BitVector n0) , Signal dom Bool ) @@ -267,4 +259,4 @@ sigmaDeltaADC adcw accumw filterw analogCmp = (delta, digitalOut, sampleRdy) delta = register 0 analogCmp (accum, accumRdy) = accumulator adcw accumw numOnes (digitalOut, sampleRdy) = filter filterw accum accumRdy - numOnes = pack <$> (countOnes <$> delta) + numOnes = pack <$> (popCountBV <$> delta) From 4315522ce35f7eb911485dc83c44aa70a252e8e5 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Thu, 18 Jan 2024 13:15:22 +0100 Subject: [PATCH 12/13] resolved some issues --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 333 ++++++++----------- 1 file changed, 133 insertions(+), 200 deletions(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index e6777fc8f8..2968cfe9ce 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -1,109 +1,74 @@ -module Clash.Cores.SigmaDeltaADC (sigmaDeltaADC) where +module SigmaDeltaADC where import Clash.Prelude hiding (filter, truncate) import Clash.Sized.Internal.BitVector --- | Shared functions --- Function to remove the LSBs from a BitVector -truncate - :: (KnownNat n0, KnownNat n1) - => BitVector (n0 + n1) - -- ^ entire bitvector - -> BitVector n0 - -- ^ bitvector without number of LSBs -truncate input = output - where - (output, _) = split input - -- | Remove the LSBs from the accumulator output when the accumulator is ready -- This is used for both the accumulator and the filter -truncateAccum - :: (KnownNat n0, KnownNat n1) - => BitVector n0 - -- ^ The previous accum - -> (BitVector (n0 + n1), Bool) - -- ^ parts of the tuple +truncateAccum :: + forall adcWdith accumExtra. + (KnownNat adcWdith, KnownNat accumExtra) => + -- | The previous accum + BitVector adcWdith -> + -- | parts of the tuple -- -- 1. Accumulator output -- 2. Boolean for when the accumulator is ready - -> (BitVector n0, BitVector n0) - -- ^ parts of tuple + (BitVector (adcWdith + accumExtra), Bool) -> + -- | parts of tuple -- -- 1. updated accum -- 2. output accum + (BitVector adcWdith, BitVector adcWdith) truncateAccum accum (sigma, rollover) - | rollover = (sigma', accum) + | rollover = (fst (split sigma), accum) | otherwise = (accum, accum) - where - sigma' = truncate sigma --- |Accumulator --- The main function for the accumulator, --- all functions that start with accumulator are used for the accumulator -accumulator - :: ( HiddenClockResetEnable dom - , KnownNat n0 - , KnownNat n1 - , KnownNat n2 - , (n2) <= (n1 + n0)) - => SNat n0 - -- ^ The ADC width - -> SNat (n1 + n0) - -- ^ The accumulator width - -> Signal dom (BitVector n2) - -- ^ The amount of ones from the input - -> (Signal dom (BitVector n0) - , Signal dom Bool) - -- ^ Parts of the Tuple - -- - -- 1. The accumulator output - -- 2. Accumulator ready going to the filter -accumulator _ aw numOnes = (accum, rollover) - where - accum = mealyB truncateAccum 0 (sigma, rollover) - (sigma, rollover) = accumulatorCounterT aw numOnes -accumulatorCounterT - :: ( HiddenClockResetEnable dom - , KnownNat n0 - , KnownNat n1 - , n1 <= n0) - => SNat n0 - -- ^ the accumulator width - -> Signal dom (BitVector n1) - -- ^ The amount of ones from the input - -> ( Signal dom (BitVector n0) - , Signal dom Bool) - -- ^ Parts of the Tuple +accumulator :: + forall adcWidth accumExtra inputWidth dom. + ( HiddenClockResetEnable dom, + KnownNat accumExtra, + KnownNat adcWidth, + KnownNat inputWidth, + inputWidth <= (adcWidth + accumExtra) + ) => + -- | The accumulator width + SNat (accumExtra + adcWidth) -> + -- | The amount of ones from the input + Signal dom (BitVector inputWidth) -> + -- | Parts of the Tuple -- -- 1. The accumulator output -- 2. Accumulator ready going to the filter -accumulatorCounterT _ numOnes = mealyB accumulatorCounter (0, False, 0, 0) numOnes + ( Signal dom (BitVector adcWidth), + Signal dom Bool + ) +accumulator _ numOnes = (accum, rollover) + where + accum = mealyB truncateAccum 0 (sigma, rollover) + (sigma, rollover) = + mealyB accumulatorCounter (accumInit , False, 0, 0) numOnes + accumInit = 0 :: BitVector (accumExtra + adcWidth + 1) -- | The counter for sigma, which counts counts the number of ones from -- the input and resets when count is equal to zero -accumulatorCounter - :: (KnownNat n0, KnownNat n1, n1 <= n0) - => ( BitVector (n0 + 1) - , Bool - , BitVector n1 - , BitVector (n0 - n1 + 1)) - -- ^ Parts of the Tuple +accumulatorCounter :: + (KnownNat sigmaWidth, KnownNat inputWidth, inputWidth <= sigmaWidth) => + -- | Parts of the Tuple -- -- 1. The previous sigma -- 2. bool for when sigma is ready -- 3. previous number of ones from the input -- 4. previous value of the main counter-> BitVector n1 - -> BitVector n1 - -- ^ number of ones from the input - -> ( ( BitVector (n0 + 1) - , Bool - , BitVector n1 - , BitVector (n0 - n1 + 1)) - , ( BitVector n0 - , Bool) - ) - -- ^ Parts of the Tuple + ( BitVector (sigmaWidth + 1), + Bool, + BitVector inputWidth, + Unsigned (sigmaWidth - inputWidth + 1) + ) -> + -- | number of ones from the input + BitVector inputWidth -> + -- | Parts of the Tuple -- -- 1. The new sigma -- 2. bool for when sigma is ready @@ -111,152 +76,120 @@ accumulatorCounter -- 4. new value of the main counter -- 5. The accumulator output -- 6. Accumulator ready going to the filter + ( ( BitVector (sigmaWidth + 1), + Bool, + BitVector inputWidth, + Unsigned (sigmaWidth - inputWidth + 1) + ), + ( BitVector sigmaWidth, + Bool + ) + ) accumulatorCounter (sigma, rollover, numOnes, count) numOnes' = - ((newState, rollover', numOnes', count'), (resize sigma, rollover)) - where - count' = count + 1 - rollover' = (count == 0) - newState - | rollover = resize numOnes - | sigma /= maxBound = min (sigma + resize numOnes) (shiftR maxBound 1) - | otherwise = maxBound + ((newState, rollover', numOnes', count'), (resize sigma, rollover)) + where + count' = count + 1 + rollover' = (count == 0) + newState + | rollover = resize numOnes + | sigma /= maxBound = min (sigma + resize numOnes) (shiftR maxBound 1) + | otherwise = maxBound -- | Box avaraging filter -- | All functions that start with filter are used for the box averaging filter -filter - :: (HiddenClockResetEnable dom, KnownNat n0, KnownNat n1) - => SNat n1 - -- ^ Filter Depth - -> Signal dom (BitVector n0) - -- ^ The input of the filter, width is equal to the adc width - -> Signal dom Bool - -- ^ Boolean to show when the accumulator is ready - -> ( Signal dom (BitVector n0) - , Signal dom Bool) - -- ^ Parts of the tuple +filter :: + forall dom adcWidth filterDepth . + (HiddenClockResetEnable dom, KnownNat adcWidth, KnownNat filterDepth) => + -- | Filter Depth + SNat filterDepth -> + -- | The input of the filter, width is equal to the adc width + Signal dom (BitVector adcWidth) -> + -- | Boolean to show when the accumulator is ready + Signal dom Bool -> + -- | Parts of the tuple -- 1. The filtered output -- 2. trigger when a new sample is ready -filter fw dataIn accumRdy = (dataOut, resultValid) - where - (accumulate, latchResult, resultValid) = - mealyB filterPipeline (False, False, False) (accumRdy, count) - count = filterCount fw accumRdy - accum = mealyB filterAccumulator 0 (count, dataIn, accumulate) - dataOut = mealyB truncateAccum 0 (accum, latchResult) + ( Signal dom (BitVector adcWidth), + Signal dom Bool + ) +filter _ dataIn accumRdy = (dataOut, resultValid) + where + count = regEn (0 :: Unsigned filterDepth) accumRdy (count + 1) + accum = mealyB filterAccumulator 0 (count, dataIn, accumulate) + dataOut = mealyB truncateAccum 0 (accum, latchResult) + accumRdyD1 = register False accumRdy + accumRdyD2 = register False accumRdyD1 + accumulate = accumRdyD1 .&&. (not <$> accumRdyD2) + latchResult = accumulate .&&. (count .==. 1) + resultValid = register False latchResult -- | The accumulator for the filter, it adds the input to accum when -- the sample from the accumulator is ready -filterAccumulator - :: (KnownNat n0, KnownNat n1) - => BitVector (n0 + n1) - -- ^ previous count of the filter accumulator - -> (BitVector n1, BitVector n0, Bool) - -- ^ Parts of the Tuple: +filterAccumulator :: + (KnownNat filterDepth, KnownNat adcWidth) => + -- | previous count of the filter accumulator + BitVector (filterDepth + adcWidth) -> + -- | Parts of the Tuple: -- 1. The filter counter -- 2. Input data from a filter accumulator -- 3. boolean for when the sample from the filter accumulator is ready - -> (BitVector (n0 + n1), BitVector (n0 + n1)) - -- ^ Parts of the Tuple + (Unsigned filterDepth, BitVector adcWidth, Bool) -> + -- | Parts of the Tuple -- 1. the new count of the accumulator -- 2. the downsampled output of the filter and adc + (BitVector (filterDepth + adcWidth), BitVector (filterDepth + adcWidth)) filterAccumulator accum (count, dataIn, accumulate) | count == 1 && accumulate = (extend dataIn, accum) | accumulate = (accum + extend dataIn, accum) | otherwise = (accum, accum) --- | FilterPipeline to sync all the signals --- contains 3 registers to determine when the filter needs to accumulate. --- this happens when the accumulator is ready -filterPipeline - :: (KnownNat n0) - => (Bool, Bool, Bool) - -- ^ parts of the tuple - -- - -- 1. accum ready with 1 cycle of delay - -- 2. accum ready with 2 cycles of delay - -- 3. latch result with 1 cycle of delay - -> (Bool, BitVector n0) - -- ^ parts of tuple - -- input of the mealy machine - -- 1. accum ready - -- 2. the main counter - -> ( (Bool, Bool, Bool), - (Bool, Bool, Bool)) - -- ^ parts of the tuple - -- - -- 1,2,3. input for all the registers - -- 4, boolean for when the filter need to accumulate - -- 5. boolean for when the filter accumulator of ready - -- 6. boolean for when the output for the adc is ready -filterPipeline (accumRdyD1, accumRdyD2, latchResult) (accumRdy, count) = - ( (accumRdyD1', accumRdyD2', latchResult') - , (accumulate, latchResult', latchResult)) - where - accumRdyD1' = accumRdy - accumRdyD2' = accumRdyD1 - accumulate = accumRdyD1 && not accumRdyD2 - latchResult' = accumulate && (count == 1) - --- | Count when the input sample is ready it counts till 2^(filterWidth) -filterCount - :: (HiddenClockResetEnable dom, KnownNat n0) - => SNat n0 - -- ^ Filter width - -> Signal dom Bool - -- ^ Sample ready boolean - -> Signal dom (BitVector n0) - -- ^ Counter output -filterCount _ accumRdy = output - where - output = regEn 0 accumRdy (output + 1) - -- | Sigma Delta ADC configurable in the ADC width, OSR and filter depth -- -- | The frequency for the ADC is equal to -- clk / 2^((AccumulatorWidth - BitsPerCycle - 1) + FilterDepth), -- where clk is the operating frequency of the ADC -sigmaDeltaADC - :: ( HiddenClockResetEnable dom - , KnownNat n0 - , KnownNat n1 - , KnownNat n2 - , KnownNat n3 - , CLog 2 (n3 + 2) <= (n1 + n0) - ) - => SNat n0 - -- ^ ADC width - -> SNat (n0 + n1) - -- ^ Accumulator width +-- +-- The R and C of the low pass network need to be chosen such that: +-- RC inbetween 200 and 1000 x clk, where clk is the frequency of +-- output +-- +-- For the design either lvds or an external comparator can be used +-- the input signal had to be connected to the positive input while +-- the output from a low pass RC-network connects to the negative input. +-- The input is a bitvector such that ddr or a deserialiser can be utilised +-- to get more bits per clock cycle for an increased sampling frequency. +sigmaDeltaADC :: + forall adcWidth accumExtra filterDepth inputWidth dom . + ( HiddenClockResetEnable dom, + KnownNat adcWidth, + KnownNat inputWidth, + CLog 2 (inputWidth + 2) <= (adcWidth + accumExtra) + ) => + -- | Accumulator width -- Has to be larger or equal to the ADC width, -- the OSR is equal to 2^(AccumulatorWidth - ADCwidth) - -> SNat n2 - -- ^ Filter depth + SNat (accumExtra + adcWidth) -> + -- | Filter depth -- The depth of the decimation filter, -- the downsampling rate is equal to 2^FilterDepth - -> Signal dom (BitVector (n3 + 1)) - -- ^ analog input from the comparator - -- For the design either lvds or an external comparator can be used - -- the input signal had to be connected to the positive input while - -- the output from a low pass RC-network connects to the negative input. - -- The input is a bitvector such that ddr or a deserialiser can be utilised - -- to get more bits per clock cycle for an increased sampling frequency. - -> ( Signal dom (BitVector (n3 + 1)) - , Signal dom (BitVector n0) - , Signal dom Bool - ) - -- ^ parts of the tuple - -- - -- 1. feedback to the RC network: - -- The R and C of the low pass network need to be chosen such that: - -- RC inbetween 200 and 1000 x clk, where clk is the frequency of - -- output - -- - -- 2. the digital output of the ADC - -- - -- 3. Trigger for when the output is ready -sigmaDeltaADC adcw accumw filterw analogCmp = (delta, digitalOut, sampleRdy) - where - delta = register 0 analogCmp - (accum, accumRdy) = accumulator adcw accumw numOnes - (digitalOut, sampleRdy) = filter filterw accum accumRdy - numOnes = pack <$> (popCountBV <$> delta) + SNat filterDepth -> + -- | analog input from the comparator + Signal dom (BitVector (inputWidth + 1)) -> + -- | parts of the tuple + -- + -- 1. feedback to the RC network: + -- + -- 2. the digital output of the ADC + -- + -- 3. Trigger for when the output is ready + ( Signal dom (BitVector (inputWidth + 1)), + Signal dom (BitVector adcWidth), + Signal dom Bool + ) +sigmaDeltaADC accumWidth@SNat filterDepth@SNat analogCmp + = (delta, digitalOut, sampleRdy) + where + delta = register 0 analogCmp + (accum, accumRdy) = accumulator accumWidth numOnes + (digitalOut, sampleRdy) = filter filterDepth accum accumRdy + numOnes = pack <$> (popCountBV <$> delta) From 0bc4ffc1ce3428406f8431be746d8cb9b3b8c141 Mon Sep 17 00:00:00 2001 From: FloriaanB Date: Thu, 18 Jan 2024 13:18:02 +0100 Subject: [PATCH 13/13] added forall statements --- clash-cores/src/Clash/Cores/SigmaDeltaADC.hs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs index 2968cfe9ce..fb698804bd 100644 --- a/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs +++ b/clash-cores/src/Clash/Cores/SigmaDeltaADC.hs @@ -54,6 +54,7 @@ accumulator _ numOnes = (accum, rollover) -- | The counter for sigma, which counts counts the number of ones from -- the input and resets when count is equal to zero accumulatorCounter :: + forall sigmaWidth inputWidth. (KnownNat sigmaWidth, KnownNat inputWidth, inputWidth <= sigmaWidth) => -- | Parts of the Tuple -- @@ -126,6 +127,7 @@ filter _ dataIn accumRdy = (dataOut, resultValid) -- | The accumulator for the filter, it adds the input to accum when -- the sample from the accumulator is ready filterAccumulator :: + forall filterDepth adcWdith. (KnownNat filterDepth, KnownNat adcWidth) => -- | previous count of the filter accumulator BitVector (filterDepth + adcWidth) -> @@ -173,7 +175,7 @@ sigmaDeltaADC :: -- The depth of the decimation filter, -- the downsampling rate is equal to 2^FilterDepth SNat filterDepth -> - -- | analog input from the comparator + -- | analog output from the comparator Signal dom (BitVector (inputWidth + 1)) -> -- | parts of the tuple --