From bf0694dc6eb12314cfc54d8e7fa586bab6f0bc79 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 4 Jan 2023 14:33:28 -0800 Subject: [PATCH 1/9] Assorted fixes for scala 2.13/chisel 3.5.5 --- src/main/scala/groundtest/TraceGen.scala | 13 ++++++++++ src/main/scala/rocket/HellaCache.scala | 2 +- src/main/scala/rocket/NBDcache.scala | 32 +++++++++++++++--------- src/main/scala/tilelink/Edges.scala | 32 ++++++++++++------------ src/main/scala/tilelink/ToAPB.scala | 4 +-- src/main/scala/unittest/UnitTest.scala | 3 ++- 6 files changed, 54 insertions(+), 32 deletions(-) diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 5a48857acd5..2160147968b 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -531,6 +531,19 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext io.mem.req.bits.signed := false.B io.mem.req.bits.cmd := reqCmd io.mem.req.bits.tag := reqTag + io.mem.req.bits.no_alloc := false.B + io.mem.req.bits.no_xcpt := false.B + io.mem.req.bits.mask := ~(0.U((numBitsInWord / 8).W)) + io.mem.req.bits.phys := false.B + io.mem.req.bits.dprv := PRV.M.U + io.mem.req.bits.dv := false.B + io.mem.keep_clock_enabled := true.B + + // The below signals don't matter because this uses the SimpleHellaIF + io.mem.s1_data.data := RegNext(io.mem.req.bits.data) + io.mem.s1_data.mask := RegNext(io.mem.req.bits.mask) + io.mem.s1_kill := false.B + io.mem.s2_kill := false.B // On cycle when request is actually sent, print it when (io.mem.req.fire) { diff --git a/src/main/scala/rocket/HellaCache.scala b/src/main/scala/rocket/HellaCache.scala index 314212eb95d..2c9acedd5fe 100644 --- a/src/main/scala/rocket/HellaCache.scala +++ b/src/main/scala/rocket/HellaCache.scala @@ -325,7 +325,7 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst || io.write.valid when (wen) { - tag_array.write(waddr, Vec(nWays, wdata), wmask) + tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(_.asTypeOf(chiselTypeOf(rstVal))) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index b49f8eff4fd..fadb2d6bd6f 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -50,13 +50,13 @@ class WritebackReq(params: TLBundleParameters)(implicit p: Parameters) extends L } class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val req = Flipped(Decoupled(new HellaCacheReq)) val resp = Decoupled(new HellaCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) val replay_next = Output(Bool()) - } + }) def beatOffset(addr: UInt) = addr.extract(beatOffBits - 1, wordOffBits) @@ -107,6 +107,8 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa io.resp.bits := req io.resp.bits.has_data := isRead(req.cmd) io.resp.bits.data := loadgen.data + io.resp.bits.data_raw := grant_word + io.resp.bits.data_word_bypass := loadgen.wordData io.resp.bits.store_data := req.data io.resp.bits.replay := true.B @@ -132,7 +134,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa } class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) @@ -152,7 +154,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach val replay = Decoupled(new ReplayInternal) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val probe_rdy = Output(Bool()) - } + }) val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(9) val state = RegInit(s_invalid) @@ -266,6 +268,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear) io.meta_write.bits.idx := req_idx + io.meta_write.bits.tag := io.tag io.meta_write.bits.data.coh := Mux(state === s_meta_clear, coh_on_clear, new_coh) io.meta_write.bits.data.tag := io.tag io.meta_write.bits.way_en := req.way_en @@ -288,6 +291,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach io.meta_read.valid := state === s_drain_rpq io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := io.tag + io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.replay.valid := state === s_drain_rpq && rpq.io.deq.valid io.replay.bits := rpq.io.deq.bits @@ -301,7 +305,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach } class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val req = Flipped(Decoupled(new MSHRReq)) val resp = Decoupled(new HellaCacheResp) val secondary_miss = Output(Bool()) @@ -319,7 +323,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu val probe_rdy = Output(Bool()) val fence_rdy = Output(Bool()) val replay_next = Output(Bool()) - } + }) // determine if the request is cacheable or not val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes) @@ -431,6 +435,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu val free_sdq = io.replay.fire && isWrite(io.replay.bits.cmd) io.replay.bits.data := sdq(RegEnable(replay_arb.io.out.bits.sdq_id, free_sdq)) + io.replay.bits.mask := 0.U io.replay <> replay_arb.io.out when (io.replay.valid || sdq_enq) { @@ -440,13 +445,13 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu } class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val req = Flipped(Decoupled(new WritebackReq(edge.bundle))) val meta_read = Decoupled(new L1MetaReadReq) val data_req = Decoupled(new L1DataReadReq) val data_resp = Input(Bits(encRowBits.W)) val release = Decoupled(new TLBundleC(edge.bundle)) - } + }) val req = Reg(new WritebackReq(edge.bundle)) val active = RegInit(false.B) @@ -490,6 +495,7 @@ class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach io.meta_read.valid := fire io.meta_read.bits.idx := req.idx io.meta_read.bits.tag := req.tag + io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.data_req.valid := fire io.data_req.bits.way_en := req.way_en @@ -516,7 +522,7 @@ class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach } class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val req = Flipped(Decoupled(new TLBundleB(edge.bundle))) val rep = Decoupled(new TLBundleC(edge.bundle)) val meta_read = Decoupled(new L1MetaReadReq) @@ -525,7 +531,7 @@ class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheMod val way_en = Input(Bits(nWays.W)) val mshr_rdy = Input(Bool()) val block_state = Input(new ClientMetadata()) - } + }) val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_mshr_resp :: s_release :: s_writeback_req :: s_writeback_resp :: @@ -553,10 +559,12 @@ class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheMod io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag + io.meta_read.bits.way_en := ~(0.U(nWays.W)) io.meta_write.valid := state === s_meta_write io.meta_write.bits.way_en := way_en io.meta_write.bits.idx := req_idx + io.meta_write.bits.tag := req_tag io.meta_write.bits.data.tag := req_tag io.meta_write.bits.data.coh := new_coh @@ -615,11 +623,11 @@ class ProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheMod } class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { - val io = new Bundle { + val io = IO(new Bundle { val read = Flipped(Decoupled(new L1DataReadReq)) val write = Flipped(Decoupled(new L1DataWriteReq)) val resp = Output(Vec(nWays, Bits(encRowBits.W))) - } + }) val waddr = io.write.bits.addr >> rowOffBits val raddr = io.read.bits.addr >> rowOffBits diff --git a/src/main/scala/tilelink/Edges.scala b/src/main/scala/tilelink/Edges.scala index fdad4edd3c5..46630104f26 100644 --- a/src/main/scala/tilelink/Edges.scala +++ b/src/main/scala/tilelink/Edges.scala @@ -238,36 +238,36 @@ class TLEdge( } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 - def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire()) + def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 - def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire()) + def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 - def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire()) + def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } - def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire()) + def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } - def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire()) + def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } - def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire()) + def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? @@ -306,18 +306,18 @@ class TLEdge( val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) - val a_inc = x.a.fire() && a_first && a_request - val b_inc = x.b.fire() && b_first && b_request - val c_inc = x.c.fire() && c_first && c_request - val d_inc = x.d.fire() && d_first && d_request - val e_inc = x.e.fire() && e_first && e_request + val a_inc = x.a.fire && a_first && a_request + val b_inc = x.b.fire && b_first && b_request + val c_inc = x.c.fire && c_first && c_request + val d_inc = x.d.fire && d_first && d_request + val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) - val a_dec = x.a.fire() && a_last && a_response - val b_dec = x.b.fire() && b_last && b_response - val c_dec = x.c.fire() && c_last && c_response - val d_dec = x.d.fire() && d_last && d_response - val e_dec = x.e.fire() && e_last && e_response + val a_dec = x.a.fire && a_last && a_response + val b_dec = x.b.fire && b_last && b_response + val c_dec = x.c.fire && c_last && c_response + val d_dec = x.d.fire && d_last && d_response + val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) diff --git a/src/main/scala/tilelink/ToAPB.scala b/src/main/scala/tilelink/ToAPB.scala index 485fe6b609c..44ffb3c33a9 100644 --- a/src/main/scala/tilelink/ToAPB.scala +++ b/src/main/scala/tilelink/ToAPB.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.amba.apb._ import freechips.rocketchip.amba._ import APBParameters._ -import chisel3.util.{RegEnable, Queue, log2Ceil, Cat} +import chisel3.util._ case class TLToAPBNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, APBImp)( dFn = { cp => @@ -63,7 +63,7 @@ class TLToAPB(val aFlow: Boolean = true)(implicit p: Parameters) extends LazyMod // data phase. Therefore, we must have enough space to save the data // phase result. Whenever we have a queued response, we can not allow // APB to present new responses, so we must quash the address phase. - val d = Wire(in.d) + val d = Wire(Decoupled(new TLBundleD(edgeIn.bundle))) in.d :<> Queue(d, 1, flow = true) // We need an irrevocable input for APB to stall diff --git a/src/main/scala/unittest/UnitTest.scala b/src/main/scala/unittest/UnitTest.scala index 41b970108da..0e0866bf505 100644 --- a/src/main/scala/unittest/UnitTest.scala +++ b/src/main/scala/unittest/UnitTest.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.unittest import chisel3._ import chisel3.util._ +import chisel3.experimental.{IO} import freechips.rocketchip.config._ import freechips.rocketchip.util._ @@ -17,7 +18,7 @@ trait HasUnitTestIO { } trait UnitTestLegacyModule extends HasUnitTestIO { - val io = new Bundle with UnitTestIO + val io = IO(new Bundle with UnitTestIO) } trait UnitTestModule extends Module with HasUnitTestIO { From 579a9402524f1b728ded345938d8d42917259d67 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 4 Jan 2023 17:03:40 -0800 Subject: [PATCH 2/9] Fix L2 TLB compile for chisel3.5.5 --- src/main/scala/rocket/PTW.scala | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 613b79943a8..717ef33a4e0 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -444,7 +444,13 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) - entry := r_pte + entry.ppn := r_pte.ppn + entry.d := r_pte.d + entry.a := r_pte.a + entry.u := r_pte.u + entry.x := r_pte.x + entry.w := r_pte.w + entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one @@ -493,9 +499,18 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( } val s2_pte = Wire(new PTE) - s2_pte := Mux1H(s2_hit_vec, s2_entry_vec) + val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) + s2_pte.ppn := s2_hit_entry.ppn + s2_pte.d := s2_hit_entry.d + s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) + s2_pte.u := s2_hit_entry.u + s2_pte.x := s2_hit_entry.x + s2_pte.w := s2_hit_entry.w + s2_pte.r := s2_hit_entry.r s2_pte.v := true.B + s2_pte.reserved_for_future := 0.U + s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") From 23951febafb8a4d8319ff7054db2f01462771ce7 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 6 Jan 2023 15:57:59 -0800 Subject: [PATCH 3/9] Fix chisel3 bump bug in ResetCatchAndSync --- src/main/scala/util/ResetCatchAndSync.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/util/ResetCatchAndSync.scala b/src/main/scala/util/ResetCatchAndSync.scala index 70fd447a1c3..82e0bef077d 100644 --- a/src/main/scala/util/ResetCatchAndSync.scala +++ b/src/main/scala/util/ResetCatchAndSync.scala @@ -23,7 +23,7 @@ class ResetCatchAndSync (sync: Int = 3) extends Module { // those flops) and on the output of the synchronizer circuit (to control // reset to any flops this circuit drives). - val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset) + val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool) withReset(post_psd_reset) { io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset, ~AsyncResetSynchronizerShiftReg(true.B, sync)) From 81d5f073b84532a9c6b230b2dc3dc14c7edeab07 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 7 Jan 2023 11:35:34 -0800 Subject: [PATCH 4/9] Fix remaining NBDcache chisel3 bugs --- src/main/scala/rocket/NBDcache.scala | 58 +++++++++++++++++++++------- 1 file changed, 44 insertions(+), 14 deletions(-) diff --git a/src/main/scala/rocket/NBDcache.scala b/src/main/scala/rocket/NBDcache.scala index fadb2d6bd6f..796fb68720e 100644 --- a/src/main/scala/rocket/NBDcache.scala +++ b/src/main/scala/rocket/NBDcache.scala @@ -6,11 +6,12 @@ package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.util.ImplicitConversions._ +import chisel3.experimental.dataview._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ -trait HasMissInfo extends HasL1HellaCacheParameters { +trait HasMissInfo extends Bundle with HasL1HellaCacheParameters { val tag_match = Bool() val old_meta = new L1Metadata val way_en = Bits(nWays.W) @@ -82,7 +83,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { - MuxLookup(req.cmd, Wire(new TLBundleA(edge.bundle)), Array( + MuxLookup(req.cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)), Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, @@ -95,7 +96,7 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle || !isAMO(req.cmd)) - Wire(new TLBundleA(edge.bundle)) + (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle || req.cmd =/= M_XSC) @@ -104,7 +105,15 @@ class IOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCa io.replay_next := (state === s_mem_ack) || io.resp.valid && !io.resp.ready io.resp.valid := (state === s_resp) - io.resp.bits := req + io.resp.bits.addr := req.addr + io.resp.bits.idx.foreach(_ := req.idx.get) + io.resp.bits.tag := req.tag + io.resp.bits.cmd := req.cmd + io.resp.bits.size := req.size + io.resp.bits.signed := req.signed + io.resp.bits.dprv := req.dprv + io.resp.bits.dv := req.dv + io.resp.bits.mask := req.mask io.resp.bits.has_data := isRead(req.cmd) io.resp.bits.data := loadgen.data io.resp.bits.data_raw := grant_word @@ -246,7 +255,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach } } - val grantackq = Module(new Queue(io.mem_finish.bits, 1)) + val grantackq = Module(new Queue(new TLBundleE(edge.bundle), 1)) val can_finish = state.isOneOf(s_invalid, s_refill_req) grantackq.io.enq.valid := refill_done && edge.isRequest(io.mem_grant.bits) grantackq.io.enq.bits := edge.GrantAck(io.mem_grant.bits) @@ -332,7 +341,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = io.req.valid && io.req.ready && cacheable && isWrite(io.req.bits.cmd) - val sdq = Mem(cfg.nSDQ, io.req.bits.data) + val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data } val idxMatch = Wire(Vec(cfg.nMSHRs, Bool())) @@ -346,6 +355,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new ReplayInternal, cfg.nMSHRs)) val alloc_arb = Module(new Arbiter(Bool(), cfg.nMSHRs)) + alloc_arb.io.in.foreach(_.bits := DontCare) var idx_match = false.B var pri_rdy = false.B @@ -365,7 +375,10 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu mshr.io.req_pri_val := alloc_arb.io.in(i).ready mshr.io.req_sec_val := io.req.valid && sdq_rdy && tag_match - mshr.io.req_bits := io.req.bits + mshr.io.req_bits.viewAsSupertype(new HellaCacheReqInternal) := io.req.bits.viewAsSupertype(new HellaCacheReqInternal) + mshr.io.req_bits.tag_match := io.req.bits.tag_match + mshr.io.req_bits.old_meta := io.req.bits.old_meta + mshr.io.req_bits.way_en := io.req.bits.way_en mshr.io.req_bits.sdq_id := sdq_alloc_id meta_read_arb.io.in(i) <> mshr.io.meta_read @@ -395,6 +408,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) + mmio_alloc_arb.io.in.foreach(_.bits := DontCare) val resp_arb = Module(new Arbiter(new HellaCacheResp, nIOMSHRs)) var mmio_rdy = false.B @@ -700,20 +714,20 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule io.cpu.req.ready := true.B val s1_valid = RegNext(io.cpu.req.fire, false.B) - val s1_req = Reg(io.cpu.req.bits) + val s1_req = Reg(new HellaCacheReq) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_replay = RegInit(false.B) val s1_clk_en = Reg(Bool()) val s1_sfence = s1_req.cmd === M_SFENCE val s2_valid = RegNext(s1_valid_masked && !s1_sfence, false.B) && !io.cpu.s2_xcpt.asUInt.orR - val s2_req = Reg(io.cpu.req.bits) + val s2_req = Reg(new HellaCacheReq) val s2_replay = RegNext(s1_replay, false.B) && s2_req.cmd =/= M_FLUSH_ALL val s2_recycle = Wire(Bool()) val s2_valid_masked = Wire(Bool()) val s3_valid = RegInit(false.B) - val s3_req = Reg(io.cpu.req.bits) + val s3_req = Reg(new HellaCacheReq) val s3_way = Reg(Bits()) val s1_recycled = RegEnable(s2_recycle, false.B, s1_clk_en) @@ -740,7 +754,9 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule dtlb.io.sfence.bits.rs2 := s1_req.size(1) dtlb.io.sfence.bits.addr := s1_req.addr dtlb.io.sfence.bits.asid := io.cpu.s1_data.data - + dtlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV + dtlb.io.sfence.bits.hg := s1_req.cmd == M_HFENCEG + when (io.cpu.req.valid) { s1_req := io.cpu.req.bits } @@ -794,6 +810,8 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule // tag read for new requests metaReadArb.io.in(4).valid := io.cpu.req.valid metaReadArb.io.in(4).bits.idx := io.cpu.req.bits.addr >> blockOffBits + metaReadArb.io.in(4).bits.tag := io.cpu.req.bits.addr >> untagBits + metaReadArb.io.in(4).bits.way_en := ~0.U(nWays.W) when (!metaReadArb.io.in(4).ready) { io.cpu.req.ready := false.B } // data read for new requests @@ -805,6 +823,8 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule // recycled requests metaReadArb.io.in(0).valid := s2_recycle metaReadArb.io.in(0).bits.idx := s2_req.addr >> blockOffBits + metaReadArb.io.in(0).bits.way_en := ~0.U(nWays.W) + metaReadArb.io.in(0).bits.tag := s2_req.tag readArb.io.in(0).valid := s2_recycle readArb.io.in(0).bits.addr := s2_req.addr readArb.io.in(0).bits.way_en := ~0.U(nWays.W) @@ -882,7 +902,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule // miss handling mshrs.io.req.valid := s2_valid_masked && !s2_hit && (isPrefetch(s2_req.cmd) || isRead(s2_req.cmd) || isWrite(s2_req.cmd)) - mshrs.io.req.bits := s2_req + mshrs.io.req.bits.viewAsSupertype(new Replay) := s2_req.viewAsSupertype(new HellaCacheReq) mshrs.io.req.bits.tag_match := s2_tag_match mshrs.io.req.bits.old_meta := Mux(s2_tag_match, L1Metadata(s2_repl_meta.tag, s2_hit_state), s2_repl_meta) mshrs.io.req.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) @@ -892,7 +912,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule // replays readArb.io.in(1).valid := mshrs.io.replay.valid - readArb.io.in(1).bits := mshrs.io.replay.bits + readArb.io.in(1).bits.addr := mshrs.io.replay.bits.addr readArb.io.in(1).bits.way_en := ~0.U(nWays.W) mshrs.io.replay.ready := readArb.io.in(1).ready s1_replay := mshrs.io.replay.valid && readArb.io.in(1).ready @@ -989,7 +1009,17 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule val cache_resp = Wire(Valid(new HellaCacheResp)) cache_resp.valid := (s2_replay || s2_valid_masked && s2_hit) && !s2_data_correctable - cache_resp.bits := s2_req + cache_resp.bits.addr := s2_req.addr + cache_resp.bits.idx.foreach(_ := s2_req.idx.get) + cache_resp.bits.tag := s2_req.tag + cache_resp.bits.cmd := s2_req.cmd + cache_resp.bits.size := s2_req.size + cache_resp.bits.signed := s2_req.signed + cache_resp.bits.dprv := s2_req.dprv + cache_resp.bits.dv := s2_req.dv + cache_resp.bits.data_word_bypass := loadgen.wordData + cache_resp.bits.data_raw := s2_data_word + cache_resp.bits.mask := s2_req.mask cache_resp.bits.has_data := isRead(s2_req.cmd) cache_resp.bits.data := loadgen.data | s2_sc_fail cache_resp.bits.store_data := s2_req.data From c143e6c90ebd314790af5984a6aacbb1a6360bad Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 11 Jan 2023 14:09:34 -0800 Subject: [PATCH 5/9] Remove memcpy from test suite (this isn't upstreamed) --- src/main/scala/system/RocketTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/system/RocketTestSuite.scala b/src/main/scala/system/RocketTestSuite.scala index e6406d1c494..ad683a8576e 100644 --- a/src/main/scala/system/RocketTestSuite.scala +++ b/src/main/scala/system/RocketTestSuite.scala @@ -175,7 +175,7 @@ object DefaultTestSuites { val rv64pi = List(rv64ui, rv64mi) val benchmarks = new BenchmarkTestSuite("rvi", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet( - "median", "multiply", "qsort", "rsort", "pmp", "towers", "vvadd", "dhrystone", "memcpy", "mt-matmul", "mt-memcpy")) + "median", "multiply", "qsort", "rsort", "pmp", "towers", "vvadd", "dhrystone", "mt-matmul")) val rv32udBenchmarks = new BenchmarkTestSuite("rvd", "$(RISCV)/riscv64-unknown-elf/share/riscv-tests/benchmarks", LinkedHashSet( "mm", "spmv", "mt-vvadd")) From d8375b2c287ed1ca094a77c1be2e1605e6456536 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 18 Jan 2023 12:54:17 -0800 Subject: [PATCH 6/9] Fix HellaQueue --- src/main/scala/util/HellaQueue.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/util/HellaQueue.scala b/src/main/scala/util/HellaQueue.scala index 39df57f9333..b05cde563de 100644 --- a/src/main/scala/util/HellaQueue.scala +++ b/src/main/scala/util/HellaQueue.scala @@ -47,6 +47,7 @@ class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module { val fq = Module(new HellaFlowQueue(entries)(data)) fq.io.enq <> io.enq io.deq <> Queue(fq.io.deq, 1, pipe = true) + io.count := fq.io.count } object HellaQueue { From a60a985b5126060f46f3743ef2c1eb3230b44923 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 19 Jan 2023 22:25:49 -0800 Subject: [PATCH 7/9] shamt is a rv32-only test --- src/main/scala/system/RocketTestSuite.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/system/RocketTestSuite.scala b/src/main/scala/system/RocketTestSuite.scala index ad683a8576e..5b763cf02a8 100644 --- a/src/main/scala/system/RocketTestSuite.scala +++ b/src/main/scala/system/RocketTestSuite.scala @@ -163,7 +163,7 @@ object DefaultTestSuites { val rv64siNames = rv32siNames val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_) - val rv64miNames = rv32miNames + "breakpoint" + "access" + "icache-alias" + val rv64miNames = rv32miNames - "shamt" + "breakpoint" + "access" + "icache-alias" val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_) val groundtestNames = LinkedHashSet("simple") From 53adf18d881ebc00190ae86c5f4d807aaca96e79 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 20 Jan 2023 11:08:09 -0800 Subject: [PATCH 8/9] icache-alias test is si-only --- src/main/scala/system/RocketTestSuite.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/system/RocketTestSuite.scala b/src/main/scala/system/RocketTestSuite.scala index 5b763cf02a8..d26c5fcfc75 100644 --- a/src/main/scala/system/RocketTestSuite.scala +++ b/src/main/scala/system/RocketTestSuite.scala @@ -160,10 +160,10 @@ object DefaultTestSuites { val rv64uzfh = new AssemblyTestSuite("rv64uzfh", rv64uzfhNames)(_) - val rv64siNames = rv32siNames + val rv64siNames = rv32siNames + "icache-alias" val rv64si = new AssemblyTestSuite("rv64si", rv64siNames)(_) - val rv64miNames = rv32miNames - "shamt" + "breakpoint" + "access" + "icache-alias" + val rv64miNames = rv32miNames - "shamt" + "breakpoint" + "access" val rv64mi = new AssemblyTestSuite("rv64mi", rv64miNames)(_) val groundtestNames = LinkedHashSet("simple") From 3b5fb3c043ccc2cea81ed7a44b295f4652d0ba02 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 30 Jan 2023 15:12:32 -0800 Subject: [PATCH 9/9] Fix match errors on rocket config fragments --- src/main/scala/subsystem/Configs.scala | 89 +++++++++++++++++++------- 1 file changed, 67 insertions(+), 22 deletions(-) diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 70059230515..b2303baa14a 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -227,26 +227,34 @@ class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => { class WithL1ICacheSets(sets: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - icache = tp.tileParams.icache.map(_.copy(nSets = sets))))} + icache = tp.tileParams.icache.map(_.copy(nSets = sets)))) + case t => t + } }) // This is the number of icache sets for all Rocket tiles class WithL1DCacheSets(sets: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - dcache = tp.tileParams.dcache.map(_.copy(nSets = sets))))} + dcache = tp.tileParams.dcache.map(_.copy(nSets = sets)))) + case t => t + } }) class WithL1ICacheWays(ways: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - icache = tp.tileParams.icache.map(_.copy(nWays = ways))))} + icache = tp.tileParams.icache.map(_.copy(nWays = ways)))) + case t => t + } }) class WithL1DCacheWays(ways: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - dcache = tp.tileParams.dcache.map(_.copy(nWays = ways))))} + dcache = tp.tileParams.dcache.map(_.copy(nWays = ways)))) + case t => t + } }) class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => { @@ -275,7 +283,9 @@ class WithIncoherentTiles extends Config((site, here, up) => { master = tp.crossingParams.master match { case x: TileMasterPortParams => x.copy(cork = Some(true)) case _ => throw new Exception("Unrecognized type for RocketCrossingParams.master") - }))} + })) + case t => t + } case BankedL2Key => up(BankedL2Key, site).copy( coherenceManager = CoherenceManagerWrapper.incoherentManager ) @@ -287,7 +297,9 @@ class WithRV32 extends Config((site, here, up) => { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy( fpu = tp.tileParams.core.fpu.map(_.copy(fLen = 32)), - mulDiv = Some(MulDivParams(mulUnroll = 8)))))} + mulDiv = Some(MulDivParams(mulUnroll = 8))))) + case t => t + } }) class WithFP16 extends Config((site, here, up) => { @@ -297,25 +309,32 @@ class WithFP16 extends Config((site, here, up) => { fpu = tp.tileParams.core.fpu.map(_.copy(minFLen = 16)) ) )) + case t => t } }) class WithNonblockingL1(nMSHRs: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - dcache = tp.tileParams.dcache.map(_.copy(nMSHRs = nMSHRs))))} + dcache = tp.tileParams.dcache.map(_.copy(nMSHRs = nMSHRs)))) + case t => t + } }) class WithNBreakpoints(hwbp: Int) extends Config ((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(nBreakpoints = hwbp)))} + core = tp.tileParams.core.copy(nBreakpoints = hwbp))) + case t => t + } }) class WithHypervisor(hext: Boolean = true) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useHypervisor = hext)))} + core = tp.tileParams.core.copy(useHypervisor = hext))) + case t => t + } }) class WithRoccExample extends Config((site, here, up) => { @@ -341,56 +360,74 @@ class WithRoccExample extends Config((site, here, up) => { class WithDefaultBtb extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - btb = Some(BTBParams())))} + btb = Some(BTBParams()))) + case t => t + } }) class WithFastMulDiv extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( core = tp.tileParams.core.copy(mulDiv = Some( - MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true)))))} + MulDivParams(mulUnroll = 8, mulEarlyOut = (site(XLen) > 32), divEarlyOut = true))))) + case t => t + } }) class WithoutMulDiv extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(mulDiv = None)))} + core = tp.tileParams.core.copy(mulDiv = None))) + case t => t + } }) class WithoutFPU extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(fpu = None)))} + core = tp.tileParams.core.copy(fpu = None))) + case t => t + } }) class WithFPUWithoutDivSqrt extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(fpu = tp.tileParams.core.fpu.map(_.copy(divSqrt = false)))))} + core = tp.tileParams.core.copy(fpu = tp.tileParams.core.fpu.map(_.copy(divSqrt = false))))) + case t => t + } }) class WithBitManip extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useBitManip = true)))} + core = tp.tileParams.core.copy(useBitManip = true))) + case t => t + } }) class WithBitManipCrypto extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useBitManipCrypto = true)))} + core = tp.tileParams.core.copy(useBitManipCrypto = true))) + case t => t + } }) class WithCryptoNIST extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useCryptoNIST = true)))} + core = tp.tileParams.core.copy(useCryptoNIST = true))) + case t => t + } }) class WithCryptoSM extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy( - core = tp.tileParams.core.copy(useCryptoSM = true)))} + core = tp.tileParams.core.copy(useCryptoSM = true))) + case t => t + } }) class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => { @@ -404,19 +441,25 @@ class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config(( class WithSynchronousRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - crossingType = SynchronousCrossing()))} + crossingType = SynchronousCrossing())) + case t => t + } }) class WithAsynchronousRocketTiles(depth: Int, sync: Int) extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - crossingType = AsynchronousCrossing()))} + crossingType = AsynchronousCrossing())) + case t => t + } }) class WithRationalRocketTiles extends Config((site, here, up) => { case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map { case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy( - crossingType = RationalCrossing()))} + crossingType = RationalCrossing())) + case t => t + } }) class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => { @@ -510,7 +553,9 @@ class WithScratchpadsOnly extends Config((site, here, up) => { dcache = tp.tileParams.dcache.map(_.copy( nSets = 256, // 16Kb scratchpad nWays = 1, - scratch = Some(0x80000000L)))))} + scratch = Some(0x80000000L))))) + case t => t + } }) /**