Need to define timing model data schema

[litghost]

Currently the FPGA interchange device database lacks timing model data. This new schema should cover defining timing models for both the routing graph (e.g. pip and wire delays) and BELs (setup/hold w.r.t. clock, launch from clock, combinatorial delays). This schema should accomidate multiple timing corners and multiple speed grades.

[mkurc-ant]

There is a draft PR open with a proposal and discussion around it: #38