From 4efcd73fb33ce79fbdcf4255957b96ed67f0e4b4 Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Mon, 28 Oct 2024 13:04:35 +0100 Subject: [PATCH 1/3] Cleanup block verfication codebase - Remove reduntant imports from RTL - Assign some hanging outputs to `unused_*` wires - Add explicit lint waivers for VeeR codebase - Add test-specific lint waivers for test wrappers - Build complex test design using multiple threads Signed-off-by: Robert Szczepanski --- design/el2_veer_wrapper.sv | 3 +- verification/block/common.mk | 10 ++- verification/block/config.vlt | 99 +++++++++++++++++++++ verification/block/dccm/Makefile | 8 +- verification/block/dccm/config.vlt | 7 ++ verification/block/dec_ib/Makefile | 8 +- verification/block/dec_ib/config.vlt | 3 + verification/block/dec_tl/Makefile | 8 +- verification/block/dec_tl/config.vlt | 5 ++ verification/block/dma/Makefile | 6 +- verification/block/dmi/Makefile | 8 +- verification/block/dmi/config.vlt | 5 ++ verification/block/exu_alu/Makefile | 8 +- verification/block/exu_alu/config.vlt | 5 ++ verification/block/exu_div/Makefile | 8 +- verification/block/exu_div/config.vlt | 5 ++ verification/block/exu_mul/Makefile | 8 +- verification/block/exu_mul/config.vlt | 5 ++ verification/block/iccm/Makefile | 8 +- verification/block/iccm/config.vlt | 7 ++ verification/block/ifu_compress/Makefile | 6 +- verification/block/lib_ahb_to_axi4/Makefile | 6 +- verification/block/lib_axi4_to_ahb/Makefile | 6 +- verification/block/lsu_tl/Makefile | 8 +- verification/block/lsu_tl/config.vlt | 5 ++ verification/block/pic/Makefile | 6 +- verification/block/pic_gw/Makefile | 6 +- verification/block/pmp/Makefile | 8 +- verification/block/pmp/config.vlt | 5 ++ verification/block/pmp_random/Makefile | 8 +- verification/block/pmp_random/config.vlt | 5 ++ 31 files changed, 228 insertions(+), 65 deletions(-) create mode 100644 verification/block/config.vlt create mode 100644 verification/block/dccm/config.vlt create mode 100644 verification/block/dec_ib/config.vlt create mode 100644 verification/block/dec_tl/config.vlt create mode 100644 verification/block/dmi/config.vlt create mode 100644 verification/block/exu_alu/config.vlt create mode 100644 verification/block/exu_div/config.vlt create mode 100644 verification/block/exu_mul/config.vlt create mode 100644 verification/block/iccm/config.vlt create mode 100644 verification/block/lsu_tl/config.vlt create mode 100644 verification/block/pmp/config.vlt create mode 100644 verification/block/pmp_random/config.vlt diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index b087ff6ca93..3db8932ef43 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -885,6 +885,7 @@ import el2_pkg::*; ); + logic unused_dmi_hard_reset; // JTAG/DMI instance dmi_wrapper dmi_wrapper ( // JTAG signals @@ -903,7 +904,7 @@ import el2_pkg::*; .reg_wr_addr (dmi_addr), // Write address to Processor .reg_en (dmi_en), // Write interface bit to Processor .reg_wr_en (dmi_wr_en), // Write enable to Processor - .dmi_hard_reset () + .dmi_hard_reset (unused_dmi_hard_reset) ); // DMI core/uncore mux diff --git a/verification/block/common.mk b/verification/block/common.mk index 293bc05b7fa..d860febdacf 100644 --- a/verification/block/common.mk +++ b/verification/block/common.mk @@ -40,15 +40,22 @@ endif ifeq ($(SIM), verilator) COMPILE_ARGS += --coverage-max-width 20000 COMPILE_ARGS += --timing - COMPILE_ARGS += -Wall -Wno-fatal + COMPILE_ARGS += -Wall + COMPILE_ARGS += $(CURDIR)/config.vlt EXTRA_ARGS += --trace --trace-structs EXTRA_ARGS += $(VERILATOR_COVERAGE) EXTRA_ARGS += -I$(CFGDIR) -Wno-DECLFILENAME + + # Include test specific Verilator config if it exists + ifneq ("$(wildcard $(TEST_DIR)/config.vlt)","") + COMPILE_ARGS += $(TEST_DIR)/config.vlt + endif else ifeq ($(SIM), vcs) EXTRA_ARGS += +incdir+$(CFGDIR) -assert svaext -cm line+cond+fsm+tgl+branch +vcs+lic+wait endif + COCOTB_HDL_TIMEUNIT = 1ns COCOTB_HDL_TIMEPRECISION = 10ps @@ -68,4 +75,3 @@ endif # Rules for generating VeeR config $(CFGDIR)/common_defines.vh: cd $(CURDIR) && $(CONFIG)/veer.config -fpga_optimize=0 $(EXTRA_CONFIG_OPTS) - diff --git a/verification/block/config.vlt b/verification/block/config.vlt new file mode 100644 index 00000000000..c243389869f --- /dev/null +++ b/verification/block/config.vlt @@ -0,0 +1,99 @@ +`verilator_config + +// Unnamed blocks do not influence logic +lint_off -rule GENUNNAMED + +// Unconnected IC memory output pins +lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_ic_mem.sv" + +// These require revisit to remove multiple definitions of variables with same names +lint_off -rule VARHIDDEN -file "*/axi4_to_ahb.sv" +lint_off -rule VARHIDDEN -file "*/el2_ifu_bp_ctl.sv" +lint_off -rule VARHIDDEN -file "*/el2_ifu_mem_ctl.sv" +lint_off -rule VARHIDDEN -file "*/el2_exu_alu_ctl.sv" +lint_off -rule VARHIDDEN -file "*/el2_pic_ctrl.sv" + +// Width related warning require explicit type casting +lint_off -rule WIDTHTRUNC -file "*/ahb_to_axi4.sv" +lint_off -rule WIDTHTRUNC -file "*/axi4_to_ahb.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dma_ctrl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_ifc_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_bp_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_aln_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dec_decode_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dec_tlu_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lib.sv" +lint_off -rule WIDTHTRUNC -file "*/beh_lib.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_bus_buffer.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dec_pmp_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_addrcheck.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_trigger.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_mem_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_exu.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_dbg.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_pic_ctrl.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_pmp.sv" +lint_off -rule WIDTHTRUNC -file "*/el2_mem_if.sv" + +lint_off -rule WIDTHEXPAND -file "*/el2_exu.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_pic_ctrl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_ifu_bp_ctl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_ifu_mem_ctl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_ifu_iccm_mem.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_lsu_addrcheck.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_lsu_bus_buffer.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_lsu_stbuf.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_ctl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_lsu_dccm_mem.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_exu_mul_ctl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_dec_tlu_ctl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_dma_ctrl.sv" +lint_off -rule WIDTHEXPAND -file "*/el2_dbg.sv" + +// Unused parameters are probably safe to remove from RTL +lint_off -rule UNUSEDPARAM -file "*/axi4_to_ahb.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_ifu.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_pic_ctrl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_dma_ctrl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_ifu_bp_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_ifu_mem_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_dec_tlu_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_lsu_dccm_mem.sv" + +// Gated clock, expected latch +lint_off -rule LATCH -file "*/beh_lib.sv" -lines 781 + +lint_off -rule BLKSEQ -file "*/beh_lib.sv" -lines 783 + +// The Verilator reports that `core_rst_l` is being used in sync and async nets, +// pointing to `rvdff` module as a source of the problem. Since the `rvdff` looks +// unrelated to `core_rst_l`, it requires a closer investigation. +lint_off -rule SYNCASYNCNET -file "*/el2_veer.sv" -lines 35 + +// Logic that might be not optimal for event based model used by Verilator +lint_off -rule UNOPTFLAT -file "*/axi4_to_ahb.sv" +lint_off -rule UNOPTFLAT -file "*/el2_ifu_ifc_ctl.sv" +lint_off -rule UNOPTFLAT -file "*/el2_dec_decode_ctl.sv" +lint_off -rule UNOPTFLAT -file "*/el2_exu_mul_ctl.sv" +lint_off -rule UNOPTFLAT -file "*/el2_exu_div_ctl.sv" +lint_off -rule UNOPTFLAT -file "*/el2_lsu.sv" +lint_off -rule UNOPTFLAT -file "*/el2_lsu_lsc_ctl.sv" +lint_off -rule UNOPTFLAT -file "*/el2_pic_ctrl.sv" + +// Warnings related to the generated `el2_param.vh` +lint_off -rule UNUSEDPARAM -file "*/el2_ifu_compress_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_dec_gpr_ctl.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_lsu_trigger.sv" +lint_off -rule UNUSEDPARAM -file "*/el2_lsu_clkdomain.sv" + +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_compress_ctl.sv" diff --git a/verification/block/dccm/Makefile b/verification/block/dccm/Makefile index c63493aef9b..d302cdd79b1 100644 --- a/verification/block/dccm/Makefile +++ b/verification/block/dccm/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -13,7 +13,7 @@ TOPLEVEL = el2_lsu_dccm_mem_wrapper VERILOG_SOURCES = \ $(SRCDIR)/lib/el2_mem_if.sv \ - $(CURDIR)/dccm/el2_lsu_dccm_mem_wrapper.sv \ + $(TEST_DIR)/el2_lsu_dccm_mem_wrapper.sv \ $(SRCDIR)/lsu/el2_lsu_dccm_mem.sv \ $(SRCDIR)/lib/mem_lib.sv @@ -21,4 +21,4 @@ VERILOG_SOURCES = \ # of simulation models EXTRA_ARGS += -UVERILATOR -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/dccm/config.vlt b/verification/block/dccm/config.vlt new file mode 100644 index 00000000000..17a51ba7795 --- /dev/null +++ b/verification/block/dccm/config.vlt @@ -0,0 +1,7 @@ +`verilator_config + +lint_off -rule PINCONNECTEMPTY -file "*/el2_lsu_dccm_mem_wrapper.sv" + +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_dccm_mem_wrapper.sv" + +lint_off -rule IMPORTSTAR -file "*/el2_mem_if.sv" diff --git a/verification/block/dec_ib/Makefile b/verification/block/dec_ib/Makefile index 91a5b12f290..8673ee193c3 100644 --- a/verification/block/dec_ib/Makefile +++ b/verification/block/dec_ib/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -11,7 +11,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_dec_ib_ctl_wrapper VERILOG_SOURCES = \ - $(CURDIR)/dec_ib/el2_dec_ib_ctl_wrapper.sv \ + $(TEST_DIR)/el2_dec_ib_ctl_wrapper.sv \ $(SRCDIR)/dec/el2_dec_ib_ctl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/dec_ib/config.vlt b/verification/block/dec_ib/config.vlt new file mode 100644 index 00000000000..31db5b367d3 --- /dev/null +++ b/verification/block/dec_ib/config.vlt @@ -0,0 +1,3 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_dec_ib_ctl_wrapper.sv" diff --git a/verification/block/dec_tl/Makefile b/verification/block/dec_tl/Makefile index 79c1bb7afd8..90ec53a070f 100644 --- a/verification/block/dec_tl/Makefile +++ b/verification/block/dec_tl/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -11,7 +11,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_dec_trigger_wrapper VERILOG_SOURCES = \ - $(CURDIR)/dec_tl/el2_dec_trigger_wrapper.sv \ + $(TEST_DIR)/el2_dec_trigger_wrapper.sv \ $(SRCDIR)/dec/el2_dec_trigger.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/dec_tl/config.vlt b/verification/block/dec_tl/config.vlt new file mode 100644 index 00000000000..2ba8c2e79b2 --- /dev/null +++ b/verification/block/dec_tl/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_dec_trigger_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/el2_dec_trigger_wrapper.sv" diff --git a/verification/block/dma/Makefile b/verification/block/dma/Makefile index c16ee90b984..f8bb8d6482d 100644 --- a/verification/block/dma/Makefile +++ b/verification/block/dma/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -14,4 +14,4 @@ TOPLEVEL = el2_dma_ctrl VERILOG_SOURCES = \ $(SRCDIR)/el2_dma_ctrl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/dmi/Makefile b/verification/block/dmi/Makefile index 31235148fbf..c7208aea6d4 100644 --- a/verification/block/dmi/Makefile +++ b/verification/block/dmi/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -11,11 +11,11 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = dmi_test_wrapper VERILOG_SOURCES = \ - $(CURDIR)/dmi/dmi_test_wrapper.sv \ + $(TEST_DIR)/dmi_test_wrapper.sv \ $(SRCDIR)/dmi/rvjtag_tap.v \ $(SRCDIR)/dmi/dmi_mux.v \ $(SRCDIR)/dmi/dmi_jtag_to_core_sync.v \ $(SRCDIR)/dmi/dmi_wrapper.v -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/dmi/config.vlt b/verification/block/dmi/config.vlt new file mode 100644 index 00000000000..983f0f5a6d3 --- /dev/null +++ b/verification/block/dmi/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/dmi_test_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/dmi_test_wrapper.sv" diff --git a/verification/block/exu_alu/Makefile b/verification/block/exu_alu/Makefile index b1a6398a7f0..4e19c07cb25 100644 --- a/verification/block/exu_alu/Makefile +++ b/verification/block/exu_alu/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -12,7 +12,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_exu_alu_ctl_wrapper VERILOG_SOURCES = \ - $(CURDIR)/exu_alu/el2_exu_alu_ctl_wrapper.sv \ + $(TEST_DIR)/el2_exu_alu_ctl_wrapper.sv \ $(SRCDIR)/exu/el2_exu_alu_ctl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/exu_alu/config.vlt b/verification/block/exu_alu/config.vlt new file mode 100644 index 00000000000..b694ee143f9 --- /dev/null +++ b/verification/block/exu_alu/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_exu_alu_ctl_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/el2_exu_alu_ctl_wrapper.sv" diff --git a/verification/block/exu_div/Makefile b/verification/block/exu_div/Makefile index 69f272fa37a..c99b798ab9e 100644 --- a/verification/block/exu_div/Makefile +++ b/verification/block/exu_div/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -12,7 +12,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_exu_div_ctl_wrapper VERILOG_SOURCES = \ - $(CURDIR)/exu_div/el2_exu_div_ctl_wrapper.sv \ + $(TEST_DIR)/el2_exu_div_ctl_wrapper.sv \ $(SRCDIR)/exu/el2_exu_div_ctl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/exu_div/config.vlt b/verification/block/exu_div/config.vlt new file mode 100644 index 00000000000..eedd8fd4519 --- /dev/null +++ b/verification/block/exu_div/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_exu_div_ctl_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/el2_exu_div_ctl_wrapper.sv" diff --git a/verification/block/exu_mul/Makefile b/verification/block/exu_mul/Makefile index 3ef7fa9b5fa..f563e24c338 100644 --- a/verification/block/exu_mul/Makefile +++ b/verification/block/exu_mul/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -12,7 +12,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_exu_mul_ctl_wrapper VERILOG_SOURCES = \ - $(CURDIR)/exu_mul/el2_exu_mul_ctl_wrapper.sv \ + $(TEST_DIR)/el2_exu_mul_ctl_wrapper.sv \ $(SRCDIR)/exu/el2_exu_mul_ctl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/exu_mul/config.vlt b/verification/block/exu_mul/config.vlt new file mode 100644 index 00000000000..e516fbe0007 --- /dev/null +++ b/verification/block/exu_mul/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_exu_mul_ctl_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/el2_exu_mul_ctl_wrapper.sv" diff --git a/verification/block/iccm/Makefile b/verification/block/iccm/Makefile index 0efbcfac1f3..81c66c5a591 100644 --- a/verification/block/iccm/Makefile +++ b/verification/block/iccm/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -13,7 +13,7 @@ TOPLEVEL = el2_ifu_iccm_mem_wrapper VERILOG_SOURCES = \ $(SRCDIR)/lib/el2_mem_if.sv \ - $(CURDIR)/iccm/el2_ifu_iccm_mem_wrapper.sv \ + $(TEST_DIR)/el2_ifu_iccm_mem_wrapper.sv \ $(SRCDIR)/ifu/el2_ifu_iccm_mem.sv \ $(SRCDIR)/lib/mem_lib.sv @@ -21,4 +21,4 @@ VERILOG_SOURCES = \ # of simulation models EXTRA_ARGS += -UVERILATOR -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/iccm/config.vlt b/verification/block/iccm/config.vlt new file mode 100644 index 00000000000..7ae02ce62d2 --- /dev/null +++ b/verification/block/iccm/config.vlt @@ -0,0 +1,7 @@ +`verilator_config + +lint_off -rule PINCONNECTEMPTY -file "*/el2_ifu_iccm_mem_wrapper.sv" + +lint_off -rule WIDTHTRUNC -file "*/el2_ifu_iccm_mem_wrapper.sv" + +lint_off -rule IMPORTSTAR -file "*/el2_mem_if.sv" diff --git a/verification/block/ifu_compress/Makefile b/verification/block/ifu_compress/Makefile index d2e37a9683c..ddd6981a459 100644 --- a/verification/block/ifu_compress/Makefile +++ b/verification/block/ifu_compress/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -13,4 +13,4 @@ TOPLEVEL = el2_ifu_compress_ctl VERILOG_SOURCES = \ $(SRCDIR)/ifu/el2_ifu_compress_ctl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/lib_ahb_to_axi4/Makefile b/verification/block/lib_ahb_to_axi4/Makefile index 188a5d79255..083d44cd534 100644 --- a/verification/block/lib_ahb_to_axi4/Makefile +++ b/verification/block/lib_ahb_to_axi4/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -15,4 +15,4 @@ VERILOG_SOURCES = \ $(SRCDIR)/lib/ahb_to_axi4.sv \ $(CURDIR)/lib_ahb_to_axi4/ahb_to_axi4_wrapper.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/lib_axi4_to_ahb/Makefile b/verification/block/lib_axi4_to_ahb/Makefile index 64f210b459d..238a838e364 100644 --- a/verification/block/lib_axi4_to_ahb/Makefile +++ b/verification/block/lib_axi4_to_ahb/Makefile @@ -3,8 +3,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -14,4 +14,4 @@ TOPLEVEL = axi4_to_ahb VERILOG_SOURCES = \ $(SRCDIR)/lib/axi4_to_ahb.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/lsu_tl/Makefile b/verification/block/lsu_tl/Makefile index 15f3709a92a..56f6ccb8892 100644 --- a/verification/block/lsu_tl/Makefile +++ b/verification/block/lsu_tl/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -11,7 +11,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_lsu_trigger_wrapper VERILOG_SOURCES = \ - $(CURDIR)/lsu_tl/el2_lsu_trigger_wrapper.sv \ + $(TEST_DIR)/el2_lsu_trigger_wrapper.sv \ $(SRCDIR)/lsu/el2_lsu_trigger.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/lsu_tl/config.vlt b/verification/block/lsu_tl/config.vlt new file mode 100644 index 00000000000..b1917fcc99b --- /dev/null +++ b/verification/block/lsu_tl/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule WIDTHTRUNC -file "*/el2_lsu_trigger_wrapper.sv" + +lint_off -rule UNUSEDPARAM -file "*/el2_lsu_trigger_wrapper.sv" diff --git a/verification/block/pic/Makefile b/verification/block/pic/Makefile index 9b9ab29bbe0..baed1e3474f 100644 --- a/verification/block/pic/Makefile +++ b/verification/block/pic/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -13,4 +13,4 @@ TOPLEVEL = el2_pic_ctrl VERILOG_SOURCES = \ $(SRCDIR)/el2_pic_ctrl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/pic_gw/Makefile b/verification/block/pic_gw/Makefile index 190cc64d176..8bff733160f 100644 --- a/verification/block/pic_gw/Makefile +++ b/verification/block/pic_gw/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -13,4 +13,4 @@ TOPLEVEL = el2_configurable_gw VERILOG_SOURCES = \ $(SRCDIR)/el2_pic_ctrl.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/pmp/Makefile b/verification/block/pmp/Makefile index d54a4be3e07..bf2ae91e444 100644 --- a/verification/block/pmp/Makefile +++ b/verification/block/pmp/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -11,7 +11,7 @@ MODULE ?= $(subst $(space),$(comma),$(subst .py,,$(TEST_FILES))) TOPLEVEL = el2_pmp_wrapper VERILOG_SOURCES = \ - $(CURDIR)/pmp/el2_pmp_wrapper.sv \ + $(TEST_DIR)/el2_pmp_wrapper.sv \ $(SRCDIR)/el2_pmp.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/pmp/config.vlt b/verification/block/pmp/config.vlt new file mode 100644 index 00000000000..b93c6c836e7 --- /dev/null +++ b/verification/block/pmp/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule ASCRANGE -file "*/el2_pmp_wrapper.sv" + +lint_off -rule WIDTHTRUNC -file "*/el2_pmp_wrapper.sv" diff --git a/verification/block/pmp_random/Makefile b/verification/block/pmp_random/Makefile index aa1edb9334f..0d04413847c 100644 --- a/verification/block/pmp_random/Makefile +++ b/verification/block/pmp_random/Makefile @@ -2,8 +2,8 @@ null := space := $(null) # comma := , -CURDIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) -SRCDIR := $(abspath $(CURDIR)../../../../design) +TEST_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))) +SRCDIR := $(abspath $(TEST_DIR)../../../../design) TEST_FILES = $(sort $(wildcard test_*.py)) @@ -12,7 +12,7 @@ TOPLEVEL = el2_pmp_wrapper PMP_TEST := 1 VERILOG_SOURCES = \ - $(CURDIR)/pmp/el2_pmp_wrapper.sv \ + $(TEST_DIR)/el2_pmp_wrapper.sv \ $(SRCDIR)/el2_pmp.sv -include $(CURDIR)/../common.mk +include $(TEST_DIR)/../common.mk diff --git a/verification/block/pmp_random/config.vlt b/verification/block/pmp_random/config.vlt new file mode 100644 index 00000000000..b93c6c836e7 --- /dev/null +++ b/verification/block/pmp_random/config.vlt @@ -0,0 +1,5 @@ +`verilator_config + +lint_off -rule ASCRANGE -file "*/el2_pmp_wrapper.sv" + +lint_off -rule WIDTHTRUNC -file "*/el2_pmp_wrapper.sv" From e821abfafc308fa62e5daf0df5cee816ff56f9f2 Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Tue, 19 Nov 2024 08:15:37 +0100 Subject: [PATCH 2/3] Add new line at the end of the file Signed-off-by: Robert Szczepanski --- design/dec/el2_dec_tlu_ctl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/design/dec/el2_dec_tlu_ctl.sv b/design/dec/el2_dec_tlu_ctl.sv index ac44e784f86..4b184f3a272 100644 --- a/design/dec/el2_dec_tlu_ctl.sv +++ b/design/dec/el2_dec_tlu_ctl.sv @@ -3174,4 +3174,4 @@ import el2_pkg::*; ); -endmodule // dec_timer_ctl \ No newline at end of file +endmodule // dec_timer_ctl From df970a79b39a6c6b4536f1b7a07dfe14e1bad99e Mon Sep 17 00:00:00 2001 From: Robert Szczepanski Date: Tue, 29 Oct 2024 13:34:32 +0100 Subject: [PATCH 3/3] Resolve ASCRANGE lint warning in PMP tests Signed-off-by: Robert Szczepanski --- verification/block/pmp/config.vlt | 2 -- verification/block/pmp/el2_pmp_wrapper.sv | 4 ++-- verification/block/pmp_random/config.vlt | 2 -- verification/block/pmp_random/el2_pmp_wrapper.sv | 4 ++-- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/verification/block/pmp/config.vlt b/verification/block/pmp/config.vlt index b93c6c836e7..b922f40b510 100644 --- a/verification/block/pmp/config.vlt +++ b/verification/block/pmp/config.vlt @@ -1,5 +1,3 @@ `verilator_config -lint_off -rule ASCRANGE -file "*/el2_pmp_wrapper.sv" - lint_off -rule WIDTHTRUNC -file "*/el2_pmp_wrapper.sv" diff --git a/verification/block/pmp/el2_pmp_wrapper.sv b/verification/block/pmp/el2_pmp_wrapper.sv index f6fd4eccd54..0b3fd2f176c 100644 --- a/verification/block/pmp/el2_pmp_wrapper.sv +++ b/verification/block/pmp/el2_pmp_wrapper.sv @@ -16,13 +16,13 @@ module el2_pmp_wrapper input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS], input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS], - output logic [0:PMP_CHANNELS-1] pmp_chan_err + output logic [PMP_CHANNELS-1:0] pmp_chan_err ); logic pmp_chan_err_unpacked[PMP_CHANNELS]; el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES]; for (genvar c = 0; c < PMP_CHANNELS; c++) begin - assign pmp_chan_err[c] = pmp_chan_err_unpacked[c]; + assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c]; end for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin diff --git a/verification/block/pmp_random/config.vlt b/verification/block/pmp_random/config.vlt index b93c6c836e7..b922f40b510 100644 --- a/verification/block/pmp_random/config.vlt +++ b/verification/block/pmp_random/config.vlt @@ -1,5 +1,3 @@ `verilator_config -lint_off -rule ASCRANGE -file "*/el2_pmp_wrapper.sv" - lint_off -rule WIDTHTRUNC -file "*/el2_pmp_wrapper.sv" diff --git a/verification/block/pmp_random/el2_pmp_wrapper.sv b/verification/block/pmp_random/el2_pmp_wrapper.sv index f6fd4eccd54..0b3fd2f176c 100644 --- a/verification/block/pmp_random/el2_pmp_wrapper.sv +++ b/verification/block/pmp_random/el2_pmp_wrapper.sv @@ -16,13 +16,13 @@ module el2_pmp_wrapper input logic [ 31:0] pmp_chan_addr[PMP_CHANNELS], input el2_pmp_type_pkt_t pmp_chan_type[PMP_CHANNELS], - output logic [0:PMP_CHANNELS-1] pmp_chan_err + output logic [PMP_CHANNELS-1:0] pmp_chan_err ); logic pmp_chan_err_unpacked[PMP_CHANNELS]; el2_pmp_cfg_pkt_t pmp_pmpcfg_int [pt.PMP_ENTRIES]; for (genvar c = 0; c < PMP_CHANNELS; c++) begin - assign pmp_chan_err[c] = pmp_chan_err_unpacked[c]; + assign pmp_chan_err[PMP_CHANNELS-1-c] = pmp_chan_err_unpacked[c]; end for (genvar e = 0; e < pt.PMP_ENTRIES; e++) begin