From 1e00195a6491e48c1b9703fac313e1dbbfb22deb Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Fri, 27 Dec 2024 15:49:16 +0100 Subject: [PATCH 01/27] Add cm config --- cm.cfg | 8 ++++++++ tools/Makefile | 3 +++ 2 files changed, 11 insertions(+) create mode 100644 cm.cfg diff --git a/cm.cfg b/cm.cfg new file mode 100644 index 00000000000..3b52363c6b8 --- /dev/null +++ b/cm.cfg @@ -0,0 +1,8 @@ +-module ahb_lite_2to1_mux +-module ahb_lsu_dma_bridge +-module jtagdpi + +-tree tb_top ++tree tb_top.rvtop_wrapper.rvtop + ++module rvtop diff --git a/tools/Makefile b/tools/Makefile index 38d5d3528b7..4b24848d602 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -150,6 +150,8 @@ defines += ${RV_ROOT}/design/include/el2_def.sv defines += $(BUILD_DIR)/el2_pdef.vh includes = -I${BUILD_DIR} -I$(TBDIR)/axi4_mux +CM_HIER_FILE = $(RV_ROOT)/cm.cfg + # Verilator supports only C++14 and newer CFLAGS += -std=c++14 @@ -188,6 +190,7 @@ vcs-build: ${TBFILES} ${BUILD_DIR}/defines.h +error+500 +incdir+${RV_ROOT}/design/lib \ +incdir+${RV_ROOT}/design/include ${BUILD_DIR}/common_defines.vh \ +incdir+$(BUILD_DIR) +libext+.v $(defines) -CFLAGS "${CFLAGS}" \ + -cm_hier $(CM_HIER_FILE) \ -f ${RV_ROOT}/testbench/flist ${TBFILES} ${TB_DPI_SRCS} -l vcs.log touch vcs-build From 54ab41b7fc7f01a7c3ff62f51fa63f85f6abf500 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Fri, 27 Dec 2024 19:03:01 +0100 Subject: [PATCH 02/27] waive rst_vec and nmi_vec signals --- design/dec/el2_dec.sv | 6 ++++++ design/dec/el2_dec_tlu_ctl.sv | 6 ++++++ design/dmi/dmi_wrapper.v | 3 +++ design/el2_veer.sv | 6 ++++++ design/el2_veer_wrapper.sv | 6 ++++++ 5 files changed, 27 insertions(+) diff --git a/design/dec/el2_dec.sv b/design/dec/el2_dec.sv index 008fa8b5050..42741f5d364 100644 --- a/design/dec/el2_dec.sv +++ b/design/dec/el2_dec.sv @@ -47,10 +47,16 @@ module el2_dec output logic dec_tlu_core_empty, input logic rst_l, // reset, active low + // rst_vec is supposed to be connected to a constant in the top level + /*pragma coverage off*/ input logic [31:1] rst_vec, // reset vector, from core pins + /*pragma coverage on*/ input logic nmi_int, // NMI pin + // nmi_vec is supposed to be connected to a constant in the top level + /*pragma coverage off*/ input logic [31:1] nmi_vec, // NMI vector, from pins + /*pragma coverage on*/ input logic i_cpu_halt_req, // Asynchronous Halt request to CPU input logic i_cpu_run_req, // Asynchronous Restart request to CPU diff --git a/design/dec/el2_dec_tlu_ctl.sv b/design/dec/el2_dec_tlu_ctl.sv index ce2dc956a83..5df6313e5dd 100644 --- a/design/dec/el2_dec_tlu_ctl.sv +++ b/design/dec/el2_dec_tlu_ctl.sv @@ -38,9 +38,15 @@ import el2_pkg::*; input logic scan_mode, /*pragma coverage on*/ + //rst_vec is supposed to be connected to constant in the top level + /*pragma coverage off*/ input logic [31:1] rst_vec, // reset vector, from core pins + /*pragma coverage on*/ input logic nmi_int, // nmi pin + //nmi_vec is supposed to be connected to constant in the top level + /*pragma coverage off*/ input logic [31:1] nmi_vec, // nmi vector + /*pragma coverage on*/ input logic i_cpu_halt_req, // Asynchronous Halt request to CPU input logic i_cpu_run_req, // Asynchronous Restart request to CPU diff --git a/design/dmi/dmi_wrapper.v b/design/dmi/dmi_wrapper.v index d9fd74104a2..03152cab83f 100644 --- a/design/dmi/dmi_wrapper.v +++ b/design/dmi/dmi_wrapper.v @@ -34,7 +34,10 @@ module dmi_wrapper( // Processor Signals input core_rst_n, // Core reset input core_clk, // Core clock + //jtag_id is supposed to be connected to a constant in the top level + /* pragma coverage off*/ input [31:1] jtag_id, // JTAG ID + /* pragma coverage on*/ input [31:0] rd_data, // 32 bit Read data from Processor output [31:0] reg_wr_data, // 32 bit Write data to Processor output [6:0] reg_wr_addr, // 7 bit reg address to Processor diff --git a/design/el2_veer.sv b/design/el2_veer.sv index 85b60665310..4d60b4d16ce 100644 --- a/design/el2_veer.sv +++ b/design/el2_veer.sv @@ -29,9 +29,15 @@ import el2_pkg::*; input logic clk, input logic rst_l, input logic dbg_rst_l, + // rst_vec is supposed to be connected to a constant in the top level + /*pragma coverage off*/ input logic [31:1] rst_vec, + /*pragma coverage on*/ input logic nmi_int, + // nmi_vec is supposed to be connected to a constant in the top level + /*pragma coverage off*/ input logic [31:1] nmi_vec, + /*pragma coverage on*/ output logic core_rst_l, // This is "rst_l | dbg_rst_l" output logic active_l2clk, diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index efeee12148e..969c168d814 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -30,10 +30,16 @@ import el2_pkg::*; input logic clk, input logic rst_l, input logic dbg_rst_l, + // rst_vec is supposed to be tied to constant in the top level + /*pragma coverage off*/ input logic [31:1] rst_vec, + /*pragma coverage on*/ input logic nmi_int, + // jtag_id and nmi_vec are supposed to be tied to constants in the top level + /*pragma coverage off*/ input logic [31:1] nmi_vec, input logic [31:1] jtag_id, + /*pragma coverage on*/ output logic [31:0] trace_rv_i_insn_ip, From b12fba626eb4ffd649a27a4ac3c3bc7b95f2a57a Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Fri, 27 Dec 2024 19:13:38 +0100 Subject: [PATCH 03/27] tb_top: toggle reset signal --- testbench/tb_top.sv | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 7941813b81b..a35c7cbc480 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -1019,15 +1019,14 @@ module tb_top `ifndef VERILATOR $dumpfile("dump.vcd"); - $dumpvars(0, tb_top); - //if($test$plusargs("dumpon")) $dumpvars; + $dumpvars(0, tb_top); + rst_l = 1'b1; + rst_l = #5 1'b0; + rst_l = #5 1'b1; forever core_clk = #5 ~core_clk; `endif end -`ifndef VERILATOR - assign rst_l = cycleCnt > 5; -`endif assign porst_l = cycleCnt > 2; //=========================================================================- From eb1d39fcd4a938f795ad1e844831dc268052fe9f Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sat, 28 Dec 2024 21:33:55 +0100 Subject: [PATCH 04/27] testbench: reconnect IC TAG mem --- testbench/tb_top.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index a35c7cbc480..92a98465c52 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -2640,8 +2640,7 @@ if (pt.ICACHE_WAYPACK == 0 ) begin : PACKED_11 `EL2_IC_TAG_PACKED_SRAM(128,104) end // block: WAYS else begin : WAYS - // TODO bring back - // `EL2_IC_TAG_PACKED_SRAM(128,52) + `EL2_IC_TAG_PACKED_SRAM(128,52) end // block: WAYS end // block: size_128 From 91d5abd330df39c04e945324f103a95c0a012dbe Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sat, 28 Dec 2024 21:37:41 +0100 Subject: [PATCH 05/27] testbench: or reduce ME signal in IC_TAG macro --- testbench/icache_macros.svh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/icache_macros.svh b/testbench/icache_macros.svh index 7bfe2c28692..483b9398b56 100644 --- a/testbench/icache_macros.svh +++ b/testbench/icache_macros.svh @@ -3,7 +3,7 @@ `define EL2_IC_TAG_PACKED_SRAM(depth,width) \ ram_be_``depth``x``width ic_way_tag ( \ .CLK (el2_mem_export.clk), \ - .ME (el2_mem_export.ic_tag_clken_final), \ + .ME (|el2_mem_export.ic_tag_clken_final), \ .WE (|el2_mem_export.ic_tag_wren_q[pt.ICACHE_NUM_WAYS-1:0]), \ .WEM (el2_mem_export.ic_tag_wren_biten_vec[``width-1:0]), \ \ From a1e25c1cae212568e4cb2dad3705e98c319d3a20 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sat, 28 Dec 2024 21:21:09 +0000 Subject: [PATCH 06/27] testbench: add cpu halt test --- testbench/tb_top.sv | 64 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 51 insertions(+), 13 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 92a98465c52..d7823f7a7ae 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -22,16 +22,13 @@ module tb_top `include "el2_param.vh" ); - logic i_cpu_halt_req; - logic i_cpu_run_req; - logic mpc_debug_halt_req; - logic mpc_debug_run_req; + logic i_cpu_halt_req, o_cpu_halt_ack, o_cpu_halt_status; + logic i_cpu_run_req, o_cpu_run_ack; + logic mpc_debug_halt_req, mpc_debug_halt_ack; + logic mpc_debug_run_req, mpc_debug_run_ack; + logic o_debug_mode_status; logic lsu_bus_clk_en; - assign i_cpu_halt_req = 1'b0; - assign i_cpu_run_req = 1'b0; - assign mpc_debug_halt_req = 1'b0; - assign mpc_debug_run_req = 1'b1; assign lsu_bus_clk_en = 1'b1; `else module tb_top @@ -1022,13 +1019,54 @@ module tb_top $dumpvars(0, tb_top); rst_l = 1'b1; rst_l = #5 1'b0; - rst_l = #5 1'b1; - forever core_clk = #5 ~core_clk; + rst_l = #25 1'b1; + // halt and start the core + i_cpu_halt_req = 1'b0; + i_cpu_run_req = 1'b0; + mpc_debug_halt_req = 1'b0; + mpc_debug_run_req = 1'b0; + + $display("halting CPU and waiting for ack"); + i_cpu_halt_req = #5 1'b1; + wait(o_cpu_halt_ack == 1); + $display("waiting for halt"); + i_cpu_halt_req = 1'b0; + wait(o_cpu_halt_status == 1'b1); + $display("requesting start and waiting for ack"); + i_cpu_run_req = 1'b1; + wait(o_cpu_run_ack == 1'b1); + $display("waiting for run"); + i_cpu_run_req = 1'b0; + wait(o_cpu_halt_status == 1'b0); + $display("done"); + + $display("requesting mpc halt and wating for ack"); + mpc_debug_halt_req = 1'b1; + wait(mpc_debug_halt_ack == 1'b1); + $display("waiting for debug halt"); + mpc_debug_halt_req = 1'b0; + wait(o_debug_mode_status == 1'b1); + $display("requesting start and waiting for ack"); + mpc_debug_run_req = 1'b1; + wait(mpc_debug_run_ack == 1'b1); + $display("waiting for cpu to start"); + mpc_debug_run_req = 1'b0; + wait(o_debug_mode_status == 1'b0); + $display("done"); `endif end - - assign porst_l = cycleCnt > 2; - +`ifndef VERILATOR + initial begin + forever core_clk = #5 ~core_clk; + end + initial begin + porst_l = 1'b1; + porst_l = #1 1'b0; + porst_l = #10 1'b1; + end +`else + assign porst_l = cycleCnt > 2; +`endif //=========================================================================- // RTL instance //=========================================================================- From 8d67bd8e1d0402bddcfe148fbd77ab5b41346d90 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 10:51:22 +0100 Subject: [PATCH 07/27] CI: run custom regression test in matrix --- .github/workflows/test-regression.yml | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index 4d96c96b116..c71c70364fb 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -109,6 +109,28 @@ jobs: name: Custom regression tests runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] container: centos:8 + strategy: + matrix: + bus: ["axi", "ahb"] + test: ["hello_world", "hello_world_dccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc", + "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned", + "icache", "bitmanip"] + priv: ["0", "1"] + exclude: + # These tests require user mode + - priv: "0" + test: "csr_mseccfg" + - priv: "0" + test: "csr_access" + - priv: "0" + test: "csr_mstatus" + - priv: "0" + test: "modesw" + - priv: "0" + test: "insns" + - priv: "0" + test: "perf_counters" + # end tests which require user mode env: GHA_EXTERNAL_DISK: additional-tools GHA_SA: gh-sa-veer-uploader @@ -119,3 +141,7 @@ jobs: - name: Run tests run: _secret_custom_regression_tests + env: + TEST: ${{ matrix.test }} + BUS: ${{ matrix.bus }} + PRIV: ${{ matrix.priv }} From 5bad8954ebb04f7fe8a2df1bdcc011ee654028f7 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 11:22:10 +0100 Subject: [PATCH 08/27] testbench/hex: add csr_msecfg --- testbench/hex/csr_mseccfg.hex | 257 ++++++++++++++++++++++++++++++++++ 1 file changed, 257 insertions(+) create mode 100755 testbench/hex/csr_mseccfg.hex diff --git a/testbench/hex/csr_mseccfg.hex b/testbench/hex/csr_mseccfg.hex new file mode 100755 index 00000000000..13f77518b33 --- /dev/null +++ b/testbench/hex/csr_mseccfg.hex @@ -0,0 +1,257 @@ +@80000000 +17 21 00 00 13 01 01 FC 97 02 00 00 93 82 82 0F +73 90 52 30 71 22 93 05 05 00 13 05 F0 0F 63 84 +05 00 13 05 10 00 97 02 58 50 93 82 A2 FD 23 80 +A2 00 E3 0A 00 FE 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 00 +00 00 13 00 00 00 13 00 00 00 13 00 00 00 13 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05 A0 83 27 44 FE 13 87 F7 FF +23 22 E4 FE 83 C7 07 00 3E 85 9D 31 83 27 04 FE +85 07 23 20 F4 FE 83 27 C4 FE 03 27 04 FE E3 6D +F7 FC 83 27 C4 FE 3E 85 B6 40 26 44 61 61 82 80 +39 71 06 DE 22 DC 80 00 23 26 A4 FC 23 24 B4 FC +23 26 04 FE 83 27 C4 FC 23 24 F4 FE 99 AC 93 07 +00 02 A3 03 F4 FE 23 20 04 FE 83 27 84 FE 03 C7 +07 00 93 07 50 02 63 0E F7 00 83 27 84 FE 83 C7 +07 00 3E 85 F5 3E 83 27 C4 FE 85 07 23 26 F4 FE +21 AC 83 27 84 FE 85 07 23 24 F4 FE 83 27 84 FE +83 C7 07 00 63 8E 07 20 83 27 84 FE 03 C7 07 00 +93 07 50 02 63 1F F7 00 13 05 50 02 D1 36 ED A2 +93 07 00 03 A3 03 F4 FE 83 27 84 FE 85 07 23 24 +F4 FE 83 27 84 FE 03 C7 07 00 93 07 00 03 E3 01 +F7 FE 83 27 84 FE 03 C7 07 00 93 07 D0 02 63 17 +F7 00 83 27 84 FE 85 07 23 24 F4 FE 83 27 84 FE +03 C7 07 00 93 07 A0 02 63 11 F7 02 83 27 84 FC +13 87 47 00 23 24 E4 FC 9C 43 23 2E F4 FC 83 27 +84 FE 85 07 23 24 F4 FE B5 A0 83 27 84 FE 03 C7 +07 00 93 07 F0 02 63 FF E7 04 83 27 84 FE 03 C7 +07 00 93 07 90 03 63 E7 E7 04 2D A0 03 27 04 FE +BA 87 8A 07 BA 97 86 07 BE 86 83 27 84 FE 13 87 +17 00 23 24 E4 FE 83 C7 07 00 93 87 07 FD B6 97 +23 20 F4 FE 83 27 84 FE 03 C7 07 00 93 07 F0 02 +63 FA E7 00 83 27 84 FE 03 C7 07 00 93 07 90 03 +E3 FE E7 FA 83 27 84 FE 83 C7 07 00 93 87 87 FA +13 07 00 02 63 62 F7 10 13 97 27 00 B7 17 00 80 +93 87 C7 F3 BA 97 9C 43 82 87 83 27 84 FC 13 87 +47 00 23 24 E4 FC 9C 43 03 47 74 FE 3A 86 83 25 +04 FE 3E 85 F5 3E 2A 87 83 27 C4 FE BA 97 23 26 +F4 FE D9 A0 83 27 84 FC 13 87 47 00 23 24 E4 FC +9C 43 03 47 74 FE 3A 86 83 25 04 FE 3E 85 CD 3C +2A 87 83 27 C4 FE BA 97 23 26 F4 FE 71 A8 83 27 +84 FC 13 87 47 00 23 24 E4 FC 9C 43 03 47 74 FE +C1 46 3A 86 83 25 04 FE 3E 85 D9 31 2A 87 83 27 +C4 FE BA 97 23 26 F4 FE 85 A8 83 27 84 FC 13 87 +47 00 23 24 E4 FC 9C 43 03 47 74 FE A1 46 3A 86 +83 25 04 FE 3E 85 69 39 2A 87 83 27 C4 FE BA 97 +23 26 F4 FE 91 A0 83 27 84 FC 13 87 47 00 23 24 +E4 FC 9C 43 93 F7 F7 0F 3E 85 19 34 83 27 C4 FE +85 07 23 26 F4 FE 0D A0 83 27 84 FC 13 87 47 00 +23 24 E4 FC 9C 43 3E 85 21 3C 2A 87 83 27 C4 FE +BA 97 23 26 F4 FE 01 00 83 27 84 FE 85 07 23 24 +F4 FE 83 27 84 FE 83 C7 07 00 E3 92 07 DA 11 A0 +01 00 83 27 C4 FE 3E 85 F2 50 62 54 21 61 82 80 +5D 71 06 D6 22 D4 00 18 23 2E A4 FC 4C C0 10 C4 +54 C4 18 C8 5C C8 23 2C 04 01 23 2E 14 01 93 07 +04 02 23 2C F4 FC 83 27 84 FD 91 17 23 24 F4 FE +83 27 84 FE BE 85 03 25 C4 FD 1D 3B 23 26 A4 FE +83 27 C4 FE 3E 85 B2 50 22 54 61 61 82 80 01 00 +01 11 06 CE 22 CC 00 10 23 26 A4 FE 83 27 C4 FE +93 F7 F7 0F 3E 85 A9 32 AA 87 3E 85 F2 40 62 44 +05 61 82 80 13 00 00 00 13 00 00 00 13 00 00 00 +01 11 06 CE 22 CC 00 10 23 26 A4 FE 23 24 B4 FE +83 27 C4 FE 93 F7 F7 0F 3E 85 EF F0 7F 91 AA 87 +3E 85 F2 40 62 44 05 61 82 80 13 00 00 00 01 00 +01 11 06 CE 22 CC 00 10 23 26 A4 FE 03 25 C4 FE +EF F0 1F 92 AA 87 3E 85 F2 40 62 44 05 61 82 80 +5D 71 06 D6 22 D4 00 18 23 2E A4 FC 4C C0 10 C4 +54 C4 18 C8 5C C8 23 2C 04 01 23 2E 14 01 93 07 +04 02 23 2C F4 FC 83 27 84 FD 91 17 23 24 F4 FE +83 27 84 FE BE 85 03 25 C4 FD 9D 31 23 26 A4 FE +83 27 C4 FE 3E 85 B2 50 22 54 61 61 82 80 01 00 +79 71 22 D6 00 18 23 24 04 FE 05 48 23 22 04 FF +29 A8 73 28 00 B8 23 24 04 FF 73 28 00 B0 23 26 +04 FF 73 28 00 B8 23 22 04 FF 83 28 84 FE 03 28 +44 FE E3 90 08 FF 03 28 44 FE 23 2C 04 FD 23 2E +04 FC 03 28 84 FD 93 17 08 00 01 47 03 28 C4 FE +42 86 81 46 33 65 C7 00 B3 E5 D7 00 2A 87 AE 87 +3A 85 BE 85 32 54 45 61 82 80 +@80000CEC +43 68 65 63 6B 69 6E 67 20 74 68 61 74 20 6D 73 +65 63 63 66 67 20 69 73 20 61 6C 6C 2D 7A 65 72 +6F 2E 2E 2E 00 00 00 00 45 52 52 4F 52 3A 20 6D +73 65 63 63 66 67 3D 30 78 25 30 38 58 0A 00 00 +6F 6B 2E 00 43 68 65 63 6B 69 6E 67 20 69 66 20 +6D 73 65 63 63 66 67 2E 52 4C 42 20 69 73 20 77 +72 69 74 65 61 62 6C 65 2E 2E 2E 00 45 52 52 4F +52 3A 20 6D 73 65 63 63 66 67 2E 4D 4D 4C 20 63 +61 6E 6E 6F 74 20 62 65 20 73 65 74 00 00 00 00 +45 52 52 4F 52 3A 20 6D 73 65 63 63 66 67 2E 52 +4C 42 20 63 61 6E 6E 6F 74 20 62 65 20 63 6C 65 +61 72 65 64 00 00 00 00 43 68 65 63 6B 69 6E 67 +20 69 66 20 6D 73 65 63 63 66 67 2E 52 4C 42 3D +31 20 61 6C 6C 6F 77 73 20 50 4D 50 20 72 65 67 +69 6F 6E 73 20 74 6F 20 62 65 20 75 6E 6C 6F 63 +6B 65 64 2E 2E 2E 00 00 45 52 52 4F 52 3A 20 63 +61 6E 6E 6F 74 20 6C 6F 63 6B 20 50 4D 50 20 72 +65 67 69 6F 6E 20 30 00 45 52 52 4F 52 3A 20 63 +61 6E 6E 6F 74 20 75 6E 6C 6F 63 6B 20 50 4D 50 +20 72 65 67 69 6F 6E 20 30 00 00 00 43 68 65 63 +6B 69 6E 67 20 69 66 20 6D 73 65 63 63 66 67 2E +52 4C 42 20 63 61 6E 6E 6F 74 20 62 65 20 73 65 +74 20 69 66 20 61 6E 79 20 50 4D 50 20 72 65 67 +69 6F 6E 20 69 73 20 6C 6F 63 6B 65 64 2E 2E 2E +00 00 00 00 45 52 52 4F 52 3A 20 6D 73 65 63 63 +66 67 2E 52 4C 42 20 63 61 6E 20 73 74 69 6C 6C +20 62 65 20 73 65 74 00 43 68 65 63 6B 69 6E 67 +20 69 66 20 6D 73 65 63 63 66 67 2E 4D 4D 4C 20 +63 61 6E 6E 6F 74 20 62 65 20 63 6C 65 61 72 65 +64 2E 2E 2E 00 00 00 00 45 52 52 4F 52 3A 20 6D +73 65 63 63 66 67 2E 4D 4D 4C 20 63 61 6E 20 62 +65 20 63 6C 65 61 72 65 64 00 00 00 43 68 65 63 +6B 69 6E 67 20 69 66 20 6D 73 65 63 63 66 67 2E +4D 4D 57 50 20 63 61 6E 6E 6F 74 20 62 65 20 63 +6C 65 61 72 65 64 2E 2E 2E 00 00 00 45 52 52 4F +52 3A 20 6D 73 65 63 63 66 67 2E 4D 4D 57 50 20 +63 61 6E 20 62 65 20 63 6C 65 61 72 65 64 00 00 +9E 0A 00 80 38 0B 00 80 38 0B 00 80 38 0B 00 80 +38 0B 00 80 38 0B 00 80 38 0B 00 80 38 0B 00 80 +38 0B 00 80 38 0B 00 80 38 0B 00 80 F6 0A 00 80 +4A 0A 00 80 38 0B 00 80 38 0B 00 80 38 0B 00 80 +38 0B 00 80 38 0B 00 80 38 0B 00 80 38 0B 00 80 +38 0B 00 80 38 0B 00 80 38 0B 00 80 CA 0A 00 80 +38 0B 00 80 38 0B 00 80 38 0B 00 80 18 0B 00 80 +38 0B 00 80 74 0A 00 80 38 0B 00 80 38 0B 00 80 +9E 0A 00 80 +@D0580000 +00 00 00 00 From 2ebf40d947924da35713219cef57e05499ec029d Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 18:47:03 +0100 Subject: [PATCH 09/27] testbench/axi4_mux: drop timescale --- testbench/axi4_mux/arbiter.v | 1 - testbench/axi4_mux/axi_crossbar.v | 1 - testbench/axi4_mux/axi_crossbar_addr.v | 1 - testbench/axi4_mux/axi_crossbar_rd.v | 1 - testbench/axi4_mux/axi_crossbar_wr.v | 1 - testbench/axi4_mux/axi_crossbar_wrap_2x1.v | 1 - testbench/axi4_mux/axi_register_rd.v | 1 - testbench/axi4_mux/axi_register_wr.v | 1 - testbench/axi4_mux/priority_encoder.v | 1 - 9 files changed, 9 deletions(-) diff --git a/testbench/axi4_mux/arbiter.v b/testbench/axi4_mux/arbiter.v index 842b5d77be5..b048acbe5d9 100644 --- a/testbench/axi4_mux/arbiter.v +++ b/testbench/axi4_mux/arbiter.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_crossbar.v b/testbench/axi4_mux/axi_crossbar.v index c02cf936ea2..a088d6ce473 100644 --- a/testbench/axi4_mux/axi_crossbar.v +++ b/testbench/axi4_mux/axi_crossbar.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_crossbar_addr.v b/testbench/axi4_mux/axi_crossbar_addr.v index e240150cebf..2e41f4e9dc1 100644 --- a/testbench/axi4_mux/axi_crossbar_addr.v +++ b/testbench/axi4_mux/axi_crossbar_addr.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_crossbar_rd.v b/testbench/axi4_mux/axi_crossbar_rd.v index cc43a8c29e4..8440410e891 100644 --- a/testbench/axi4_mux/axi_crossbar_rd.v +++ b/testbench/axi4_mux/axi_crossbar_rd.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_crossbar_wr.v b/testbench/axi4_mux/axi_crossbar_wr.v index 7f733d98275..f6fb510b7ee 100644 --- a/testbench/axi4_mux/axi_crossbar_wr.v +++ b/testbench/axi4_mux/axi_crossbar_wr.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_crossbar_wrap_2x1.v b/testbench/axi4_mux/axi_crossbar_wrap_2x1.v index 8012952cf9e..1b836b124a8 100644 --- a/testbench/axi4_mux/axi_crossbar_wrap_2x1.v +++ b/testbench/axi4_mux/axi_crossbar_wrap_2x1.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_register_rd.v b/testbench/axi4_mux/axi_register_rd.v index 9af8a6dab62..bbf2d396892 100644 --- a/testbench/axi4_mux/axi_register_rd.v +++ b/testbench/axi4_mux/axi_register_rd.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/axi_register_wr.v b/testbench/axi4_mux/axi_register_wr.v index d8bfba929c3..9efc0401f74 100644 --- a/testbench/axi4_mux/axi_register_wr.v +++ b/testbench/axi4_mux/axi_register_wr.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* diff --git a/testbench/axi4_mux/priority_encoder.v b/testbench/axi4_mux/priority_encoder.v index 2c1ea966409..1831f5dae50 100644 --- a/testbench/axi4_mux/priority_encoder.v +++ b/testbench/axi4_mux/priority_encoder.v @@ -26,7 +26,6 @@ THE SOFTWARE. // Language: Verilog 2001 `resetall -`timescale 1ns / 1ps `default_nettype none /* From 67f9c3809e79541ee2325f5329b30b878416f97b Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 18:49:11 +0100 Subject: [PATCH 10/27] Makefile: add axi4_mux files to TBFILES --- tools/Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/Makefile b/tools/Makefile index 4b24848d602..ae6643339d3 100755 --- a/tools/Makefile +++ b/tools/Makefile @@ -143,7 +143,16 @@ TBFILES = $(TBDIR)/tb_top_pkg.sv \ $(TBDIR)/ahb_sif.sv \ $(TBDIR)/jtagdpi/jtagdpi.sv \ $(TBDIR)/ahb_lite_2to1_mux.sv \ - $(TBDIR)/ahb_lsu_dma_bridge.sv + $(TBDIR)/ahb_lsu_dma_bridge.sv \ + $(TBDIR)/axi4_mux/axi_crossbar_wrap_2x1.v \ + $(TBDIR)/axi4_mux/arbiter.v \ + $(TBDIR)/axi4_mux/axi_crossbar_addr.v \ + $(TBDIR)/axi4_mux/axi_crossbar_rd.v \ + $(TBDIR)/axi4_mux/axi_crossbar.v \ + $(TBDIR)/axi4_mux/axi_crossbar_wr.v \ + $(TBDIR)/axi4_mux/axi_register_rd.v \ + $(TBDIR)/axi4_mux/axi_register_wr.v \ + $(TBDIR)/axi4_mux/priority_encoder.v defines = $(BUILD_DIR)/common_defines.vh defines += ${RV_ROOT}/design/include/el2_def.sv From 9d19ae34c60e037ff64c1779e1d4ea1189f5d221 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 18:49:50 +0100 Subject: [PATCH 11/27] openocd_test: detect the simulation binary wait for common simulation log line --- .github/scripts/openocd_test.sh | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh index e1e54867e63..559e556e052 100755 --- a/.github/scripts/openocd_test.sh +++ b/.github/scripts/openocd_test.sh @@ -42,11 +42,18 @@ echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR # Start the simulation echo -e "Starting simulation..." -obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & +if [ -f obj_dir/Vtb_top ]; then + obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & +elif [ -f ./simv ]; then + ./simv >"${SIM_LOG}" 2>&1 & +else + echo "No simulation binary found, exiting" + exit 1 +fi SIM_PID=$! # Wait -wait_for_phrase "${SIM_LOG}" "VerilatorTB: Start of sim" +wait_for_phrase "${SIM_LOG}" " remote_bitbang_port 5000" if [ $? -ne 0 ]; then echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}" print_logs From 0596ebc143c8331d09bfe5456bf44babf6ebf56e Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 18:50:42 +0100 Subject: [PATCH 12/27] utils.sh: use date for bash 4 compatibility --- .github/scripts/utils.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/utils.sh b/.github/scripts/utils.sh index b3b7bd506ca..d923e335dec 100644 --- a/.github/scripts/utils.sh +++ b/.github/scripts/utils.sh @@ -33,8 +33,8 @@ wait_for_phrase () { fi # Wait for the phrase - DEADLINE=$((${EPOCHSECONDS} + 30)) - while [ ${EPOCHSECONDS} -lt ${DEADLINE} ] + DEADLINE=$(($(date +%s) + 30)) + while [ $(date +%s) -lt ${DEADLINE} ] do # Check for the phrase grep "$2" "$1" >/dev/null From edb22bf0b5a3b61cef4955553c30230f77d36007 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 18:57:13 +0100 Subject: [PATCH 13/27] testbench: enable dmi core in all simulators --- testbench/tb_top.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index d7823f7a7ae..1ef46f13d65 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -218,9 +218,7 @@ module tb_top logic dmi_core_enable; - `ifdef VERILATOR always_comb dmi_core_enable = ~(o_cpu_halt_status); - `endif `ifdef RV_OPENOCD_TEST // SB and LSU AHB master mux From 5186e9e716e94e78d66c85305b3530266182de3f Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 19:07:07 +0100 Subject: [PATCH 14/27] openocd_test: use diferent sim start strings for diferent binaries --- .github/scripts/openocd_test.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh index 559e556e052..74da044c3e9 100755 --- a/.github/scripts/openocd_test.sh +++ b/.github/scripts/openocd_test.sh @@ -43,8 +43,10 @@ echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR # Start the simulation echo -e "Starting simulation..." if [ -f obj_dir/Vtb_top ]; then + SIM_START_STRING="VerilatorTB: Start of sim" obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & elif [ -f ./simv ]; then + SIM_START_STRING=" remote_bitbang_port 5000" ./simv >"${SIM_LOG}" 2>&1 & else echo "No simulation binary found, exiting" @@ -53,7 +55,7 @@ fi SIM_PID=$! # Wait -wait_for_phrase "${SIM_LOG}" " remote_bitbang_port 5000" +wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}" if [ $? -ne 0 ]; then echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}" print_logs From 5d7500c51aa16a0c0ba9dcb5e2f9bb96ecc6907a Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 19:40:47 +0100 Subject: [PATCH 15/27] CI: add custom openocd tests --- .github/workflows/test-openocd.yml | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/.github/workflows/test-openocd.yml b/.github/workflows/test-openocd.yml index 6952e48b9ed..a3670341223 100644 --- a/.github/workflows/test-openocd.yml +++ b/.github/workflows/test-openocd.yml @@ -99,3 +99,24 @@ jobs: with: name: openocd_coverage_data path: results/*.info + + custom-openocd-tests: + name: Run Custom OpenOCD tests + runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] + container: centos:8 + strategy: + fail-fast: false + matrix: + bus: ["axi4"] + env: + GHA_EXTERNAL_DISK: additional-tools + GHA_SA: gh-sa-veer-uploader + steps: + - uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Run tests + run: _secret_custom_openocd_tests + env: + BUS: ${{ matrix.bus }} From 692ed2eef86bb3f24727bd3b65ea349f73788083 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 22:15:25 +0100 Subject: [PATCH 16/27] gdb_test: set GCC_PREFIX is it is not set --- .github/scripts/gdb_test.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh index c74e87b2ffc..809c84db3d5 100755 --- a/.github/scripts/gdb_test.sh +++ b/.github/scripts/gdb_test.sh @@ -18,7 +18,9 @@ SIM_LOG=`realpath sim.log` OPENOCD_LOG=`realpath openocd.log` -GCC_PREFIX=riscv64-unknown-elf +if [ -z $GCC_PREFIX ]; then + GCC_PREFIX=riscv64-unknown-elf +fi # Ensure that RISC-V toolchain is installed if ! which ${GCC_PREFIX}-gcc >/dev/null; then From 9ff760c3661ee68809064e57cc527cf454c94b37 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 22:16:07 +0100 Subject: [PATCH 17/27] test.gdb: drop failing memory accesses --- .github/scripts/test.gdb | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/.github/scripts/test.gdb b/.github/scripts/test.gdb index 59e2d8c81ac..c1ec1f4f719 100644 --- a/.github/scripts/test.gdb +++ b/.github/scripts/test.gdb @@ -126,19 +126,5 @@ continue delete -# This causes an error. Let's execute it anyway for coverage. -echo Accessing region at 0xe0000000...\n -set *(0xe0000000) = 0x01234567 -set *(0xe0000004) = 0x89ABCDEF -set *(0xe0000008) = 0x55555555 -set *(0xe000000C) = 0xAAAAAAAA -print/x *0xe0000000@4 -echo Accessing region at 0xf0000000...\n -set *(0xf0000000) = 0x01234567 -set *(0xf0000004) = 0x89ABCDEF -set *(0xf0000008) = 0x55555555 -set *(0xf000000C) = 0xAAAAAAAA -print/x *0xf0000000@4 - # end the simulation gracefully set *(volatile unsigned char*)0xd0580000 = 0xff From d99fb40f60ec0b268a18420fa88b8b14536be2e0 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 22:27:51 +0100 Subject: [PATCH 18/27] gdb_test: chose proper sim binary and sim start string --- .github/scripts/gdb_test.sh | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh index 809c84db3d5..a2c255b51a5 100755 --- a/.github/scripts/gdb_test.sh +++ b/.github/scripts/gdb_test.sh @@ -60,11 +60,20 @@ echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR # Start the simulation echo -e "Starting simulation..." -./obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & +if [ -f obj_dir/Vtb_top ]; then + SIM_START_STRING="VerilatorTB: Start of sim" + obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & +elif [ -f ./simv ]; then + SIM_START_STRING=" remote_bitbang_port 5000" + ./simv >"${SIM_LOG}" 2>&1 & +else + echo "No simulation binary found, exiting" + exit 1 +fi SIM_PID=$! # Wait -wait_for_phrase "${SIM_LOG}" "Start of sim" +wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}" # TODO handle proper string in the output instead of waiting sleep 10s retcode=$? From 64cff1ec75bccbde839d7b4f780dc03ea138fc31 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 22:28:25 +0100 Subject: [PATCH 19/27] sim_gdb: shorten sleep --- .github/scripts/gdb_test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh index a2c255b51a5..63c5328168a 100755 --- a/.github/scripts/gdb_test.sh +++ b/.github/scripts/gdb_test.sh @@ -75,7 +75,7 @@ SIM_PID=$! # Wait wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}" # TODO handle proper string in the output instead of waiting -sleep 10s +sleep 1s retcode=$? if [ $retcode -ne 0 ]; then echo -e "${COLOR_RED}Failed to start the simulation: $retcode ${COLOR_OFF}" From 5883d7eccae2daa5b69bfe93152a8c4c38e70483 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Sun, 29 Dec 2024 22:30:33 +0100 Subject: [PATCH 20/27] cm.cfg drop axi_crossbar_wrap_2x1 --- cm.cfg | 1 + 1 file changed, 1 insertion(+) diff --git a/cm.cfg b/cm.cfg index 3b52363c6b8..138b3644003 100644 --- a/cm.cfg +++ b/cm.cfg @@ -1,6 +1,7 @@ -module ahb_lite_2to1_mux -module ahb_lsu_dma_bridge -module jtagdpi +-module axi_crossbar_wrap_2x1 -tree tb_top +tree tb_top.rvtop_wrapper.rvtop From 49805a54115cde4bfd73c021583cc00426c353a6 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 30 Dec 2024 13:18:37 +0100 Subject: [PATCH 21/27] openocd/gdb test: update sim options --- .github/scripts/gdb_test.sh | 2 +- .github/scripts/openocd_test.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh index 63c5328168a..ebfc68e05a8 100755 --- a/.github/scripts/gdb_test.sh +++ b/.github/scripts/gdb_test.sh @@ -65,7 +65,7 @@ if [ -f obj_dir/Vtb_top ]; then obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & elif [ -f ./simv ]; then SIM_START_STRING=" remote_bitbang_port 5000" - ./simv >"${SIM_LOG}" 2>&1 & + ./simv +vcs+lic+wait -cm line+cond+fsm >"${SIM_LOG}" 2>&1 & else echo "No simulation binary found, exiting" exit 1 diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh index 74da044c3e9..1ef0bfabaae 100755 --- a/.github/scripts/openocd_test.sh +++ b/.github/scripts/openocd_test.sh @@ -47,7 +47,7 @@ if [ -f obj_dir/Vtb_top ]; then obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & elif [ -f ./simv ]; then SIM_START_STRING=" remote_bitbang_port 5000" - ./simv >"${SIM_LOG}" 2>&1 & + ./simv +vcs+lic+wait -cm line+cond+fsm >"${SIM_LOG}" 2>&1 & else echo "No simulation binary found, exiting" exit 1 From 9983c50513752b23c72b3fd81793dc55d107c5fd Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 30 Dec 2024 15:20:32 +0100 Subject: [PATCH 22/27] openocd/gdb: gather more data --- .github/scripts/gdb_test.sh | 2 +- .github/scripts/openocd_test.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/gdb_test.sh b/.github/scripts/gdb_test.sh index ebfc68e05a8..9039b691a6a 100755 --- a/.github/scripts/gdb_test.sh +++ b/.github/scripts/gdb_test.sh @@ -65,7 +65,7 @@ if [ -f obj_dir/Vtb_top ]; then obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & elif [ -f ./simv ]; then SIM_START_STRING=" remote_bitbang_port 5000" - ./simv +vcs+lic+wait -cm line+cond+fsm >"${SIM_LOG}" 2>&1 & + ./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 & else echo "No simulation binary found, exiting" exit 1 diff --git a/.github/scripts/openocd_test.sh b/.github/scripts/openocd_test.sh index 1ef0bfabaae..5288b2d0b96 100755 --- a/.github/scripts/openocd_test.sh +++ b/.github/scripts/openocd_test.sh @@ -47,7 +47,7 @@ if [ -f obj_dir/Vtb_top ]; then obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 & elif [ -f ./simv ]; then SIM_START_STRING=" remote_bitbang_port 5000" - ./simv +vcs+lic+wait -cm line+cond+fsm >"${SIM_LOG}" 2>&1 & + ./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 & else echo "No simulation binary found, exiting" exit 1 From f129fb58459a1d2e0cdd334f33eacd458e820a9b Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 30 Dec 2024 19:17:47 +0100 Subject: [PATCH 23/27] CI: merge Verilator reports and pass them to custom step --- .github/workflows/report-coverage.yml | 69 +++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/.github/workflows/report-coverage.yml b/.github/workflows/report-coverage.yml index 146ed93b7fb..d636ea95fda 100644 --- a/.github/workflows/report-coverage.yml +++ b/.github/workflows/report-coverage.yml @@ -100,10 +100,73 @@ jobs: coverage.toggle.info coverage.branch.info + merge-verilator-reports: + name: Merge Verilator info data + runs-on: ubuntu-latest + container: ghcr.io/antmicro/cores-veer-el2:20241223 + steps: + - uses: actions/checkout@v3 + with: + submodules: recursive + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: regression_tests_coverage_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: verification_tests_coverage_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: uarch_tests_coverage_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: riscv-dv_coverage_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: riscof_coverage_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: openocd_coverage_data + path: ./ + + - name: Merge data + shell: bash + run: | + git clone https://github.com/linux-test-project/lcov -b v2.3-beta + PATH="`pwd`/lcov/bin:$PATH" + ls *_toggle.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --rc lcov_branch_coverage=1 -o coverage_toggle_verilator.info" }' | bash + ls *_line.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" -o coverage_line_verilator.info" }' | bash + + - name: Pack artifacts + if: always() + uses: actions/upload-artifact@v3 + with: + name: verilator_coverage_data + path: | + coverage_toggle_verilator.info + coverage_line_verilator.info + custom-coverage-report: name: Custom coverage report runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ] container: centos:8 + needs: [merge-verilator-reports] env: GHA_EXTERNAL_DISK: additional-tools GHA_SA: gh-sa-veer-uploader @@ -113,6 +176,12 @@ jobs: with: submodules: recursive + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: verilator_coverage_data + path: ./ + - name: Prepare Environment run: _secret_prepare_env From 5d419e14da6d3a034dedbaa15deb3f4db1263994 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Mon, 30 Dec 2024 13:10:01 +0100 Subject: [PATCH 24/27] Bump verilator Signed-off-by: Ryszard Rozak --- .github/workflows/report-coverage.yml | 4 ++-- .github/workflows/test-openocd.yml | 2 +- .github/workflows/test-regression-exceptions.yml | 2 +- .github/workflows/test-regression.yml | 2 +- .github/workflows/test-renode.yml | 2 +- .github/workflows/test-riscof.yml | 2 +- .github/workflows/test-riscv-dv.yml | 2 +- .github/workflows/test-uarch.yml | 4 ++-- .github/workflows/test-uvm.yml | 2 +- .github/workflows/test-verification.yml | 2 +- 10 files changed, 12 insertions(+), 12 deletions(-) diff --git a/.github/workflows/report-coverage.yml b/.github/workflows/report-coverage.yml index d636ea95fda..ad02792da58 100644 --- a/.github/workflows/report-coverage.yml +++ b/.github/workflows/report-coverage.yml @@ -8,7 +8,7 @@ jobs: coverage-report: name: Coverage report runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 env: DEBIAN_FRONTEND: "noninteractive" @@ -103,7 +103,7 @@ jobs: merge-verilator-reports: name: Merge Verilator info data runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 steps: - uses: actions/checkout@v3 with: diff --git a/.github/workflows/test-openocd.yml b/.github/workflows/test-openocd.yml index a3670341223..0277f17620f 100644 --- a/.github/workflows/test-openocd.yml +++ b/.github/workflows/test-openocd.yml @@ -8,7 +8,7 @@ jobs: tests: name: Run OpenOCD tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: fail-fast: false matrix: diff --git a/.github/workflows/test-regression-exceptions.yml b/.github/workflows/test-regression-exceptions.yml index 119b7b80a43..aa149358f4c 100644 --- a/.github/workflows/test-regression-exceptions.yml +++ b/.github/workflows/test-regression-exceptions.yml @@ -8,7 +8,7 @@ jobs: regression-tests: name: Regression exceptions tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: matrix: bus: ["axi"] diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index c71c70364fb..9c9a3758588 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -8,7 +8,7 @@ jobs: regression-tests: name: Regression tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: matrix: bus: ["axi", "ahb"] diff --git a/.github/workflows/test-renode.yml b/.github/workflows/test-renode.yml index 45dbb3ae644..7a374d2a269 100644 --- a/.github/workflows/test-renode.yml +++ b/.github/workflows/test-renode.yml @@ -6,7 +6,7 @@ on: jobs: tests: runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: fail-fast: false env: diff --git a/.github/workflows/test-riscof.yml b/.github/workflows/test-riscof.yml index fd441e36c17..389142b1e0e 100644 --- a/.github/workflows/test-riscof.yml +++ b/.github/workflows/test-riscof.yml @@ -8,7 +8,7 @@ jobs: tests: name: Run RISCOF tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: fail-fast: false matrix: diff --git a/.github/workflows/test-riscv-dv.yml b/.github/workflows/test-riscv-dv.yml index 621f56f2456..1b286c7c822 100644 --- a/.github/workflows/test-riscv-dv.yml +++ b/.github/workflows/test-riscv-dv.yml @@ -85,7 +85,7 @@ jobs: run-tests: name: Run RISC-V DV tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 needs: [ generate-config, generate-code ] strategy: fail-fast: false diff --git a/.github/workflows/test-uarch.yml b/.github/workflows/test-uarch.yml index da80f1d00d3..e52cf80515e 100644 --- a/.github/workflows/test-uarch.yml +++ b/.github/workflows/test-uarch.yml @@ -7,7 +7,7 @@ jobs: lint: name: Lint microarchitectural tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 steps: - name: Setup repository uses: actions/checkout@v3 @@ -38,7 +38,7 @@ jobs: tests: name: Microarchitectural tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: matrix: test: diff --git a/.github/workflows/test-uvm.yml b/.github/workflows/test-uvm.yml index 59fc449b579..c625707fbe9 100644 --- a/.github/workflows/test-uvm.yml +++ b/.github/workflows/test-uvm.yml @@ -7,7 +7,7 @@ jobs: tests: name: UVM tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 env: CCACHE_DIR: "/opt/uvm/.cache/" DEBIAN_FRONTEND: "noninteractive" diff --git a/.github/workflows/test-verification.yml b/.github/workflows/test-verification.yml index 054274e5e4f..7c10ab144f4 100644 --- a/.github/workflows/test-verification.yml +++ b/.github/workflows/test-verification.yml @@ -7,7 +7,7 @@ jobs: tests: name: Verification tests runs-on: ubuntu-latest - container: ghcr.io/antmicro/cores-veer-el2:20241223 + container: ghcr.io/antmicro/cores-veer-el2:20241230 strategy: matrix: test: ["test_pyuvm"] From 6c435f962b7e24ab503b79665e06d2bdae76c047 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Tue, 31 Dec 2024 14:22:14 +0100 Subject: [PATCH 25/27] axi memory: align address --- testbench/ahb_sif.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/ahb_sif.sv b/testbench/ahb_sif.sv index 24cc5e2bd15..6bf62aae080 100644 --- a/testbench/ahb_sif.sv +++ b/testbench/ahb_sif.sv @@ -194,7 +194,7 @@ module axi_slv #( always @(posedge aclk) begin if (arvalid && arready) begin - read_address = araddr; + read_address = {araddr[31:3], 3'b000}; rdata <= { mem[read_address+7], mem[read_address+6], @@ -217,7 +217,7 @@ module axi_slv #( end if (awvalid) begin - write_address = awaddr; + write_address = {awaddr[31:3], 3'b000}; awready <= 0; end if (wvalid) begin From c329ad92ad5f487f1464c3c196177fcb931a7b32 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Tue, 31 Dec 2024 14:31:13 +0100 Subject: [PATCH 26/27] Set coverage off on core_id Signed-off-by: Ryszard Rozak --- design/dec/el2_dec.sv | 2 ++ design/dec/el2_dec_tlu_ctl.sv | 2 ++ design/el2_veer.sv | 2 ++ design/el2_veer_wrapper.sv | 2 ++ 4 files changed, 8 insertions(+) diff --git a/design/dec/el2_dec.sv b/design/dec/el2_dec.sv index 42741f5d364..d53430a9c0a 100644 --- a/design/dec/el2_dec.sv +++ b/design/dec/el2_dec.sv @@ -66,7 +66,9 @@ module el2_dec output logic o_cpu_run_ack, // Run request ack output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + /*pragma coverage off*/ input logic [31:4] core_id, // CORE ID + /*pragma coverage on*/ // external MPC halt/run interface input logic mpc_debug_halt_req, // Async halt request diff --git a/design/dec/el2_dec_tlu_ctl.sv b/design/dec/el2_dec_tlu_ctl.sv index 5df6313e5dd..ac44e784f86 100644 --- a/design/dec/el2_dec_tlu_ctl.sv +++ b/design/dec/el2_dec_tlu_ctl.sv @@ -175,7 +175,9 @@ import el2_pkg::*; output logic o_cpu_run_ack, // run req ack output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + /*pragma coverage off*/ input logic [31:4] core_id, // Core ID + /*pragma coverage on*/ // external MPC halt/run interface input logic mpc_debug_halt_req, // Async halt request diff --git a/design/el2_veer.sv b/design/el2_veer.sv index 4d60b4d16ce..7d21113bf42 100644 --- a/design/el2_veer.sv +++ b/design/el2_veer.sv @@ -64,7 +64,9 @@ import el2_pkg::*; output logic o_cpu_run_ack, // Core Acknowledge to run request output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + /*pragma coverage off*/ input logic [31:4] core_id, // CORE ID + /*pragma coverage on*/ // external MPC halt/run interface input logic mpc_debug_halt_req, // Async halt request diff --git a/design/el2_veer_wrapper.sv b/design/el2_veer_wrapper.sv index 969c168d814..b087ff6ca93 100644 --- a/design/el2_veer_wrapper.sv +++ b/design/el2_veer_wrapper.sv @@ -405,7 +405,9 @@ import el2_pkg::*; output logic jtag_tdo, // JTAG TDO output logic jtag_tdoEn, // JTAG Test Data Output enable + /*pragma coverage off*/ input logic [31:4] core_id, + /*pragma coverage on*/ // Memory Export Interface el2_mem_if.veer_sram_src el2_mem_export, From 3b3844e04394e311bca7ba3e09b664880949bb8a Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Mon, 30 Dec 2024 20:42:42 +0100 Subject: [PATCH 27/27] CI: generate data for coverview --- .github/scripts/prepare_coverage_data.sh | 161 +++++++++++++++++++++++ .github/workflows/publish-webpage.yml | 8 ++ .github/workflows/report-coverage.yml | 139 +++++++++++-------- 3 files changed, 256 insertions(+), 52 deletions(-) create mode 100755 .github/scripts/prepare_coverage_data.sh diff --git a/.github/scripts/prepare_coverage_data.sh b/.github/scripts/prepare_coverage_data.sh new file mode 100755 index 00000000000..04ea4fa509c --- /dev/null +++ b/.github/scripts/prepare_coverage_data.sh @@ -0,0 +1,161 @@ +set -e +set -o pipefail + +cat <> split.py +import sys +files = {} +active_file = None +with open(sys.argv[1], 'r') as file: + for line in file: + if line[0:1] == "#": + continue + elif line[0:3] == "SF:": + active_file = line.replace("\n", "").split(":")[1] + files[active_file] = {} + files[active_file]["da"] = [] + files[active_file]["brda"] = [] + files[active_file]["brf"] = 0 + files[active_file]["brh"] = 0 + elif line[0:3] == "DA:": + files[active_file]["da"].append(line.replace("\n", "").split(":")[1:]) + elif line[0:5] == "BRDA:": + files[active_file]["brda"].append(line.replace("\n", "").split(":")[1:]) + elif line[0:4] == "BRF:": + files[active_file]["brf"] = int(line.replace("\n", "").split(":")[1]) + elif line[0:4] == "BRH:": + files[active_file]["brh"] = int(line.replace("\n", "").split(":")[1]) + elif "end_of_record" in line: + active_file = None +if sys.argv[2] == "--branch": + print("TN:verilator_coverage") + for f in files: + print("SF:%s" % f) + for brda in files[f]["brda"]: + brda_line = brda[0].split(",")[0] + for da in files[f]["da"]: + da_line = da[0].split(",")[0] + if da_line == brda_line: + print("DA:%s" % (",".join(da))) + files[f]["da"].remove(da) + print("BRDA:%s" % (",".join(brda))) + print("end_of_record") +elif sys.argv[2] == "--line": + print("TN:verilator_coverage") + for f in files: + print("SF:%s" % f) + for da in files[f]["da"]: + da_line = da[0].split(",")[0] + found = False + for brda in files[f]["brda"]: + brda_line = brda[0].split(",")[0] + if da_line == brda_line: + found = True + if not found: + print("DA:%s" % (",".join(da))) + print("end_of_record") + sys.exit(0) +EOF + +cat <> preprocess.py +import sys +filter = None +in_file = False +if sys.argv[2] == "--filter": + filter = sys.argv[3] +print("TN:verilator_coverage") +with open(sys.argv[1], 'r') as file: + for line in file: + line = line.replace("\n", "") + if line[0:3] == "SF:": + if filter == None or line.startswith("SF:%s" % filter): + in_file = True + print(line) + continue + else: + in_file = False + continue + if not in_file: + continue + if "end_of_record" in line: + in_file = False + print(line) + continue + if line[0:1] == "#": + print(line) + elif line[0:3] == "DA:": + data = line.split(",") + line = "%s,%d" % (data[0], int(data[1]) > 0) + print(line) + elif line[0:5] == "BRDA:": + data = line.split(",") + line = "%s,%s,%s,%d" % (data[0],data[1],data[2], int(data[3]) > 0) + print(line) + else: + print(line) +EOF + +mkdir info_files +mv *.info info_files +cd info_files +git clone https://github.com/linux-test-project/lcov -b v2.3-beta +PATH="`pwd`/lcov/bin:$PATH" + +ls *_toggle.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --ignore-errors inconsistent --rc lcov_branch_coverage=1 -o coverage_toggle_verilator.info" }' | bash +ls *_branch.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --ignore-errors inconsistent --rc lcov_branch_coverage=1 -o coverage_line_verilator.info" }' | bash + +cp coverage_toggle_verilator.info ../ +cp coverage_line_verilator.info ../ + +cd ../ +rm -rf info_files + +mv coverage_line_verilator.info line.info +python3 split.py line.info --branch > coverage_branch_verilator.info +python3 split.py line.info --line > coverage_line_verilator.info + +find . -type f -name 'coverage_*.info' -exec sed -i 's_^SF:.*Cores-VeeR-EL2/_SF:_g' {} \; + +python3 preprocess.py coverage_line_verilator.info --filter "design/" > _coverage_line.info +python3 preprocess.py coverage_toggle_verilator.info --filter "design/" > _coverage_toggle.info +python3 preprocess.py coverage_branch_verilator.info --filter "design/" > _coverage_branch.info + +cp _coverage_line.info coverage_line_verilator.info +cp _coverage_branch.info coverage_branch_verilator.info +cp _coverage_toggle.info coverage_toggle_verilator.info + +grep 'SF:' coverage_*.info | cut -d ":" -f 3 | sort | uniq > files.txt + +export BRANCH=$GITHUB_HEAD_REF +export COMMIT=$GITHUB_SHA +{ + while read file + do + if [ -f $file ]; then + echo "### FILE: $file" + cat "$file" + else + echo "### SKIPPING: $file" + fi + done +} < files.txt > sources.txt + +mkdir test_data +cp coverage_line_*.info coverage_toggle_*.info coverage_branch_* sources.txt test_data + +# add logo +cp docs/dashboard-styles/assets/chips-alliance-logo-mono.svg test_data/logo.svg + +# add config.json +echo -n '{ "datasets": { "verilator": { "line": "coverage_line_verilator.info", "branch": "coverage_branch_verilator.info", "toggle": "coverage_toggle_verilator.info" } }, "title": "VeeR EL2 coverage dashboard", "commit": "' > test_data/config.json +echo -n $COMMIT >> test_data/config.json +echo -n '", "branch": "' >> test_data/config.json +echo -n $BRANCH >> test_data/config.json +echo -n '", "repo": "cores-veer-el2", "timestamp": "' >> test_data/config.json +echo -n `date +"%Y-%m-%dT%H:%M:%S.%3N%z"` >> test_data/config.json +echo -n '" }' >> test_data/config.json + +cat test_data/config.json + +cd test_data +zip ../data.zip * +cd .. diff --git a/.github/workflows/publish-webpage.yml b/.github/workflows/publish-webpage.yml index d99e6180d0a..60eb9b4d758 100644 --- a/.github/workflows/publish-webpage.yml +++ b/.github/workflows/publish-webpage.yml @@ -69,6 +69,7 @@ jobs: - name: Update webpage if: github.event_name != 'pull_request' run: | + mv coverage_dashboard/*.zip . sis -d webpage \ --include-documentation \ --doc-project-name "Cores VeeR EL2" \ @@ -79,11 +80,15 @@ jobs: rm -rf public.new/html/main/docs_rendered mkdir -p public.new/html/main/docs_rendered mv ./docs_rendered/* public.new/html/main/docs_rendered + mv data.zip public.new/html/main/ + mv data_v.zip public.new/html/main/ + echo ${GITHUB_RUN_ID} > public.new/html/main/run_id tar -acf webpage.tar.gz public.new - name: Update webpage PR if: github.event_name == 'pull_request' run: | + mv coverage_dashboard/*.zip . sis -d webpage \ --include-documentation \ --doc-project-name "Cores VeeR EL2" \ @@ -94,6 +99,9 @@ jobs: rm -rf public.new/html/dev/${{ github.event.number }}/docs_rendered mkdir -p public.new/html/dev/${{ github.event.number }}/docs_rendered mv ./docs_rendered/* public.new/html/dev/${{ github.event.number }}/docs_rendered + mv data.zip public.new/html/dev/${{ github.event.number }}/ + mv data_v.zip public.new/html/dev/${{ github.event.number }}/ + echo ${GITHUB_RUN_ID} > public.new/html/dev/${{ github.event.number }}/run_id tar -acf webpage.tar.gz public.new - name: Add redirect index page diff --git a/.github/workflows/report-coverage.yml b/.github/workflows/report-coverage.yml index ad02792da58..4ad3869776a 100644 --- a/.github/workflows/report-coverage.yml +++ b/.github/workflows/report-coverage.yml @@ -5,40 +5,16 @@ on: jobs: - coverage-report: - name: Coverage report + merge-verilator-reports: + name: Merge Verilator info data runs-on: ubuntu-latest container: ghcr.io/antmicro/cores-veer-el2:20241230 env: DEBIAN_FRONTEND: "noninteractive" - steps: - - name: Setup repository - uses: actions/checkout@v3 - - - name: Install coverage dependencies - shell: bash - run: | - python3 -m venv .venv - source .venv/bin/activate - pip install -r .github/scripts/requirements-coverage.txt - echo "PATH=$PATH" >> $GITHUB_ENV - - # This step is needed to have the same VeeR codebase as used in tests - - name: Configure VeeR - shell: bash - run: | - export RV_ROOT=`pwd` - make defines.h -f $RV_ROOT/tools/Makefile - - - name: Setup lcov - shell: bash - run: | - git clone https://github.com/linux-test-project/lcov - pushd lcov - git checkout v2.1 - echo "LCOV_PATH=`realpath bin`" >> "$GITHUB_ENV" - popd + - uses: actions/checkout@v3 + with: + submodules: recursive - name: Download coverage reports uses: actions/download-artifact@v3 @@ -76,38 +52,66 @@ jobs: name: openocd_coverage_data path: ./ - - name: Generate reports + - name: Merge data shell: bash run: | - export PATH=${{ env.LCOV_PATH }}:${PATH} - sis -d reports . --report-dir report --src-pattern \*design\* - cat *_toggle.info > coverage.toggle.info - cat *_branch.info > coverage.branch.info + sudo apt update + sudo apt install -y zip unzip + .github/scripts/prepare_coverage_data.sh - name: Pack artifacts if: always() uses: actions/upload-artifact@v3 with: - name: coverage_report - path: ./report + name: verilator_coverage_data + path: | + coverage_toggle_verilator.info + coverage_line_verilator.info + coverage_branch_verilator.info - name: Pack artifacts if: always() uses: actions/upload-artifact@v3 with: - name: combined_coverage_data + name: coverview_data path: | - coverage.toggle.info - coverage.branch.info + data.zip - merge-verilator-reports: - name: Merge Verilator info data + coverage-report: + name: Coverage report runs-on: ubuntu-latest container: ghcr.io/antmicro/cores-veer-el2:20241230 + needs: [merge-verilator-reports, custom-coverage-report] + env: + DEBIAN_FRONTEND: "noninteractive" + steps: - - uses: actions/checkout@v3 - with: - submodules: recursive + - name: Setup repository + uses: actions/checkout@v3 + + - name: Install coverage dependencies + shell: bash + run: | + python3 -m venv .venv + source .venv/bin/activate + pip install -r .github/scripts/requirements-coverage.txt + echo "PATH=$PATH" >> $GITHUB_ENV + + # This step is needed to have the same VeeR codebase as used in tests + - name: Configure VeeR + shell: bash + run: | + export RV_ROOT=`pwd` + make defines.h -f $RV_ROOT/tools/Makefile + + - name: Setup lcov + shell: bash + run: | + git clone https://github.com/linux-test-project/lcov + pushd lcov + git checkout v2.1 + echo "LCOV_PATH=`realpath bin`" >> "$GITHUB_ENV" + popd - name: Download coverage reports uses: actions/download-artifact@v3 @@ -145,22 +149,47 @@ jobs: name: openocd_coverage_data path: ./ - - name: Merge data + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: coverview_data + path: ./ + + - name: Download coverage reports + uses: actions/download-artifact@v3 + with: + name: data_v + path: ./ + + - name: Generate reports shell: bash run: | - git clone https://github.com/linux-test-project/lcov -b v2.3-beta - PATH="`pwd`/lcov/bin:$PATH" - ls *_toggle.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" --rc lcov_branch_coverage=1 -o coverage_toggle_verilator.info" }' | bash - ls *_line.info | xargs printf -- '-a %s\n' | xargs echo | awk '{ print "lcov "$0" -o coverage_line_verilator.info" }' | bash + sudo apt update + sudo apt install -y zip unzip + export PATH=${{ env.LCOV_PATH }}:${PATH} + sis -d reports . --report-dir report --src-pattern \*design\* + cp data.zip report + cp data_v.zip report + + cat *_toggle.info > coverage.toggle.info + cat *_branch.info > coverage.branch.info - name: Pack artifacts if: always() uses: actions/upload-artifact@v3 with: - name: verilator_coverage_data + name: coverage_report + path: ./report + + - name: Pack artifacts + if: always() + uses: actions/upload-artifact@v3 + with: + name: combined_coverage_data path: | - coverage_toggle_verilator.info - coverage_line_verilator.info + coverage.toggle.info + coverage.branch.info + custom-coverage-report: name: Custom coverage report @@ -187,3 +216,9 @@ jobs: - name: Generate custom report run: _secret_custom_report + + - name: Pack artifacts + uses: actions/upload-artifact@v3 + with: + name: data_v + path: ./data_v.zip