From 48ccfa93f508dc7704563e20b21df19e425ee652 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Wed, 4 Dec 2024 18:01:32 +0100 Subject: [PATCH 1/5] icache export: assign signals with ranges --- design/ifu/el2_ifu_ic_mem.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/design/ifu/el2_ifu_ic_mem.sv b/design/ifu/el2_ifu_ic_mem.sv index 9b3743bfe1f..35db09447db 100644 --- a/design/ifu/el2_ifu_ic_mem.sv +++ b/design/ifu/el2_ifu_ic_mem.sv @@ -297,7 +297,7 @@ import el2_pkg::*; // Use exported ICache interface. always_comb begin - wb_dout_pre_up = icache_export.wb_dout_pre_up; + wb_dout_pre_up[i][k] = icache_export.wb_dout_pre_up[i][k]; end if (pt.ICACHE_BYPASS_ENABLE == 1) begin assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); @@ -358,7 +358,7 @@ import el2_pkg::*; // Use exported ICache interface. always_comb begin - wb_dout_pre_up = icache_export.wb_dout_pre_up; + wb_dout_pre_up[i][k][68-1:0] = icache_export.wb_dout_pre_up[i][k][68-1:0]; end if (pt.ICACHE_BYPASS_ENABLE == 1) begin assign wrptr_in_up[i][k] = (wrptr_up[i][k] == (pt.ICACHE_NUM_BYPASS-1)) ? '0 : (wrptr_up[i][k] + 1'd1); @@ -439,8 +439,8 @@ import el2_pkg::*; // Use exported ICache interface. always_comb begin - icache_export.ic_b_sb_bit_en_vec = ic_b_sb_bit_en_vec; - wb_packeddout_pre = icache_export.wb_packeddout_pre; + icache_export.ic_b_sb_bit_en_vec[k] = ic_b_sb_bit_en_vec[k]; + wb_packeddout_pre[k] = icache_export.wb_packeddout_pre[k]; end for (genvar i=0; i Date: Thu, 5 Dec 2024 13:07:56 +0100 Subject: [PATCH 2/5] bring back icache --- testbench/tb_top.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 966a8e08c58..88e184a8d22 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -2337,8 +2337,7 @@ end : Gen_iccm_enable `EL2_PACKED_IC_DATA_SRAM(512,284,71,k) end // block: WAYS else begin : WAYS - // TODO bring back - // `EL2_PACKED_IC_DATA_SRAM(512,142,71,k) + `EL2_PACKED_IC_DATA_SRAM(512,142,71,k) end // block: WAYS end // block: size_512 From 31dbec4fcb15935ed20502899a3b0d6fdfe783aa Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 5 Dec 2024 14:05:38 +0100 Subject: [PATCH 3/5] do not define DCCM_ECC_WIDTH --- design/lib/el2_mem_if.sv | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/design/lib/el2_mem_if.sv b/design/lib/el2_mem_if.sv index 29e94ebb24d..3ccb306006a 100644 --- a/design/lib/el2_mem_if.sv +++ b/design/lib/el2_mem_if.sv @@ -22,8 +22,6 @@ import el2_pkg::*; interface el2_mem_if #( `include "el2_param.vh" ) (); - localparam DCCM_ECC_WIDTH = pt.DCCM_FDATA_WIDTH - pt.DCCM_DATA_WIDTH; - ////////////////////////////////////////// // Clock logic clk; @@ -47,9 +45,9 @@ interface el2_mem_if #( logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank; logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank; logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank; - logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank; + logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank; logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout; - logic [pt.DCCM_NUM_BANKS-1:0][ DCCM_ECC_WIDTH-1:0] dccm_bank_ecc; + logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_bank_ecc; ////////////////////////////////////////// // ICACHE DATA From 61adcc12d505e2f3219c9544dac855435963dad0 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 5 Dec 2024 15:50:29 +0100 Subject: [PATCH 4/5] use unique names for blocks --- testbench/tb_top.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index 88e184a8d22..0cc5c770776 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -2290,7 +2290,7 @@ end : Gen_iccm_enable end // block: PACKED_0 // WAY PACKED - else begin : PACKED_1 + else begin : PACKED_10 // generate IC DATA PACKED SRAMS for 2/4 ways for (genvar k=0; k Date: Thu, 5 Dec 2024 17:47:45 +0100 Subject: [PATCH 5/5] add icache test --- .github/workflows/test-regression.yml | 3 +- testbench/asm/icache.ld | 8 +++++ testbench/asm/icache.s | 51 +++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 testbench/asm/icache.ld create mode 100644 testbench/asm/icache.s diff --git a/.github/workflows/test-regression.yml b/.github/workflows/test-regression.yml index ddbbe51f8d8..b4124c94a55 100644 --- a/.github/workflows/test-regression.yml +++ b/.github/workflows/test-regression.yml @@ -13,7 +13,8 @@ jobs: matrix: bus: ["axi", "ahb"] test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc", - "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned"] + "csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned", + "icache"] coverage: ["branch", "toggle"] #TODO: add functional coverage priv: ["0", "1"] exclude: diff --git a/testbench/asm/icache.ld b/testbench/asm/icache.ld new file mode 100644 index 00000000000..9d27be1ff5e --- /dev/null +++ b/testbench/asm/icache.ld @@ -0,0 +1,8 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS { + .text : { *(.text*) } + . = 0x10000; + .data : { *(.*data) *(.rodata*)} +} diff --git a/testbench/asm/icache.s b/testbench/asm/icache.s new file mode 100644 index 00000000000..83cf3408d14 --- /dev/null +++ b/testbench/asm/icache.s @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2024 Antmicro +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +#include "defines.h" + +#define STDOUT 0xd0580000 + + .set mfdc, 0x7f9 + .set mrac, 0x7c0 +// Code to execute +.section .text +.global _start +_start: + // Enable Caches in MRAC + li x1, 0x5f555555 + csrw mrac, x1 + li x3, 4 + csrw mfdc, x3 // disable store merging + + li t3, 0 // counter for the outer loop + li t5, 100 // limit the outer loop to 100 iterations +outer: + beq t3, t5, report_success + addi t3, t3, 1 + li t4, 123 +inner: + addi t4, t4, -1 + bne t4, zero, inner + jal x0, outer +report_success: + // write 0xff to STDOUT to report success + li x3, STDOUT + li x2, 0xff + sw x2, 0(x3) +end: + nop + j end +.long 0,1,2,3,4