diff --git a/verification/block/lib_ahb_to_axi4/Makefile b/verification/block/lib_ahb_to_axi4/Makefile index 083d44cd534..c401e503ea3 100644 --- a/verification/block/lib_ahb_to_axi4/Makefile +++ b/verification/block/lib_ahb_to_axi4/Makefile @@ -13,6 +13,6 @@ TOPLEVEL = ahb_to_axi4_wrapper VERILOG_SOURCES = \ $(SRCDIR)/lib/ahb_to_axi4.sv \ - $(CURDIR)/lib_ahb_to_axi4/ahb_to_axi4_wrapper.sv + $(TEST_DIR)/ahb_to_axi4_wrapper.sv include $(TEST_DIR)/../common.mk diff --git a/verification/block/lib_ahb_to_axi4/testbench.py b/verification/block/lib_ahb_to_axi4/testbench.py index 539574cbd78..ad7ab4e5bf9 100644 --- a/verification/block/lib_ahb_to_axi4/testbench.py +++ b/verification/block/lib_ahb_to_axi4/testbench.py @@ -365,7 +365,7 @@ def __init__(self, name, parent, uut, signal_prefix="", signal_map=None): self.axi_awready.value = 0 self.axi_wready.value = 0 self.axi_arready.value = 0 - self.axi_rready.value = 0 + self.axi_rvalid.value = 0 async def _wait(self, signal, max_cycles=200): """ diff --git a/verification/block/lib_axi4_to_ahb/testbench.py b/verification/block/lib_axi4_to_ahb/testbench.py index 273750de699..3adb68092fd 100644 --- a/verification/block/lib_axi4_to_ahb/testbench.py +++ b/verification/block/lib_axi4_to_ahb/testbench.py @@ -302,7 +302,7 @@ def __init__(self, name, parent): def build_phase(self): self.env = BaseEnvironment("env", self) - cocotb.top.rst_l = 0 + cocotb.top.rst_l.value = 0 def start_clock(self, name): period = ConfigDB().get(None, "", "TEST_CLK_PERIOD") @@ -312,30 +312,30 @@ def start_clock(self, name): async def do_reset(self, signalName, timeLength="100e-9", isActiveHigh=True): - cocotb.top.rst_l = 0 - cocotb.top.free_clk = 0 - cocotb.top.bus_clk_en = 1 - cocotb.top.clk_override = 0 - cocotb.top.dec_tlu_force_halt = 0 - cocotb.top.axi_awvalid = 0 - cocotb.top.axi_awid = 0 - cocotb.top.axi_awaddr = 0 - cocotb.top.axi_awsize = 0 - cocotb.top.axi_awprot = 0 - cocotb.top.axi_wvalid = 0 - cocotb.top.axi_wdata = 0 - cocotb.top.axi_wstrb = 0 - cocotb.top.axi_wlast = 0 - cocotb.top.axi_bready = 0 - cocotb.top.axi_arvalid = 0 - cocotb.top.axi_arid = 0 - cocotb.top.axi_araddr = 0 - cocotb.top.axi_arsize = 0 - cocotb.top.axi_arprot = 0 - cocotb.top.axi_rready = 0 - cocotb.top.ahb_hrdata = 0 - cocotb.top.ahb_hready = 0 - cocotb.top.ahb_hresp = 0 + cocotb.top.rst_l.value = 0 + cocotb.top.free_clk.value = 0 + cocotb.top.bus_clk_en.value = 1 + cocotb.top.clk_override.value = 0 + cocotb.top.dec_tlu_force_halt.value = 0 + cocotb.top.axi_awvalid.value = 0 + cocotb.top.axi_awid.value = 0 + cocotb.top.axi_awaddr.value = 0 + cocotb.top.axi_awsize.value = 0 + cocotb.top.axi_awprot.value = 0 + cocotb.top.axi_wvalid.value = 0 + cocotb.top.axi_wdata.value = 0 + cocotb.top.axi_wstrb.value = 0 + cocotb.top.axi_wlast.value = 0 + cocotb.top.axi_bready.value = 0 + cocotb.top.axi_arvalid.value = 0 + cocotb.top.axi_arid.value = 0 + cocotb.top.axi_araddr.value = 0 + cocotb.top.axi_arsize.value = 0 + cocotb.top.axi_arprot.value = 0 + cocotb.top.axi_rready.value = 0 + cocotb.top.ahb_hrdata.value = 0 + cocotb.top.ahb_hready.value = 0 + cocotb.top.ahb_hresp.value = 0 signal = getattr(cocotb.top, signalName) signal.value = int(isActiveHigh) diff --git a/verification/block/pmp/test_multiple_configs.py b/verification/block/pmp/test_multiple_configs.py index 99214af71f7..d1eeb90389c 100644 --- a/verification/block/pmp/test_multiple_configs.py +++ b/verification/block/pmp/test_multiple_configs.py @@ -83,10 +83,10 @@ async def body(self): await self.pmp_seqr.start_item(item) await self.pmp_seqr.finish_item(item) - self.checkRangeBoundary(LOWER_BOUNDARY) + await self.checkRangeBoundary(LOWER_BOUNDARY) for _ in range(test_iterations): await self.randomAccessInAddrRange(LOWER_BOUNDARY, UPPER_BOUNDARY) - self.checkRangeBoundary(UPPER_BOUNDARY) + await self.checkRangeBoundary(UPPER_BOUNDARY) # ==============================================================================