diff --git a/testbench/icache_macros.svh b/testbench/icache_macros.svh index 02c4203481d..7bfe2c28692 100644 --- a/testbench/icache_macros.svh +++ b/testbench/icache_macros.svh @@ -2,14 +2,14 @@ `define EL2_IC_TAG_PACKED_SRAM(depth,width) \ ram_be_``depth``x``width ic_way_tag ( \ - .CLK (clk), \ - .ME (ic_tag_clken_final), \ - .WE (|ic_tag_wren_q[pt.ICACHE_NUM_WAYS-1:0]), \ - .WEM (ic_tag_wren_biten_vec[``width-1:0]), \ + .CLK (el2_mem_export.clk), \ + .ME (el2_mem_export.ic_tag_clken_final), \ + .WE (|el2_mem_export.ic_tag_wren_q[pt.ICACHE_NUM_WAYS-1:0]), \ + .WEM (el2_mem_export.ic_tag_wren_biten_vec[``width-1:0]), \ \ - .D ({pt.ICACHE_NUM_WAYS{ic_tag_wr_data[``width/pt.ICACHE_NUM_WAYS-1:0]}}), \ - .ADR (ic_rw_addr_q[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), \ - .Q (ic_tag_data_raw_packed_pre[``width-1:0]), \ + .D ({pt.ICACHE_NUM_WAYS{el2_mem_export.ic_tag_wr_data[``width/pt.ICACHE_NUM_WAYS-1:0]}}), \ + .ADR (el2_mem_export.ic_rw_addr_q[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), \ + .Q (el2_mem_export.ic_tag_data_raw_packed_pre[``width-1:0]), \ .ROP ( ), \ \ .TEST1 (1'b0), \ @@ -28,12 +28,12 @@ `define EL2_IC_TAG_SRAM(depth,width,i) \ ram_``depth``x``width ic_way_tag ( \ - .CLK (clk), \ - .ME(ic_tag_clken_final[i]), \ - .WE (ic_tag_wren_q[i]), \ - .D (ic_tag_wr_data[``width-1:0]), \ - .ADR(ic_rw_addr_q[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), \ - .Q (ic_tag_data_raw_pre[i][``width-1:0]), \ + .CLK (el2_mem_export.clk), \ + .ME(el2_mem_export.ic_tag_clken_final[i]), \ + .WE (el2_mem_export.ic_tag_wren_q[i]), \ + .D (el2_mem_export.ic_tag_wr_data[``width-1:0]), \ + .ADR(el2_mem_export.ic_rw_addr_q[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), \ + .Q (el2_mem_export.ic_tag_data_raw_pre[i][``width-1:0]), \ .ROP ( ), \ \ .TEST1 (1'b0), \ @@ -52,13 +52,13 @@ `define EL2_PACKED_IC_DATA_SRAM(depth,width,waywidth,k) \ ram_be_``depth``x``width ic_bank_sb_way_data ( \ - .CLK (clk), \ - .WE (|ic_b_sb_wren[k]), // OR of all the ways in the bank \ - .WEM (ic_b_sb_bit_en_vec[k]), // 284 bits of bit enables \ - .D ({pt.ICACHE_NUM_WAYS{ic_sb_wr_data[k][``waywidth-1:0]}}), \ - .ADR (ic_rw_addr_bank_q[k][pt.ICACHE_INDEX_HI:pt.ICACHE_DATA_INDEX_LO]), \ - .Q (wb_packeddout_pre[k]), \ - .ME (|ic_bank_way_clken_final[k]), \ + .CLK (el2_mem_export.clk), \ + .WE (|el2_mem_export.ic_b_sb_wren[k]), // OR of all the ways in the bank \ + .WEM (el2_mem_export.ic_b_sb_bit_en_vec[k]), // 284 bits of bit enables \ + .D ({pt.ICACHE_NUM_WAYS{el2_mem_export.ic_sb_wr_data[k][``waywidth-1:0]}}), \ + .ADR (el2_mem_export.ic_rw_addr_bank_q[k][pt.ICACHE_INDEX_HI:pt.ICACHE_DATA_INDEX_LO]), \ + .Q (el2_mem_export.wb_packeddout_pre[k]), \ + .ME (|el2_mem_export.ic_bank_way_clken_final[k]), \ .ROP ( ), \ .TEST1 (1'b0), \ .RME (1'b0), \ @@ -76,12 +76,12 @@ `define EL2_IC_DATA_SRAM(depth,width,i,k) \ ram_``depth``x``width ic_bank_sb_way_data ( \ - .CLK (clk), \ - .ME(ic_bank_way_clken_final_up[i][k]), \ - .WE (ic_b_sb_wren[k][i]), \ - .D (ic_sb_wr_data[k][``width-1:0]), \ - .ADR(ic_rw_addr_bank_q[k][pt.ICACHE_INDEX_HI:pt.ICACHE_DATA_INDEX_LO]), \ - .Q (wb_dout_pre_up[i][k]), \ + .CLK (el2_mem_export.clk), \ + .ME(el2_mem_export.ic_bank_way_clken_final_up[i][k]), \ + .WE (el2_mem_export.ic_b_sb_wren[k][i]), \ + .D (el2_mem_export.ic_sb_wr_data[k][``width-1:0]), \ + .ADR(el2_mem_export.ic_rw_addr_bank_q[k][pt.ICACHE_INDEX_HI:pt.ICACHE_DATA_INDEX_LO]), \ + .Q (el2_mem_export.wb_dout_pre_up[i][k]), \ .ROP ( ), \ .TEST1 (1'b0), \ .RME (1'b0), \ diff --git a/testbench/tb_top.sv b/testbench/tb_top.sv index c4a49b31c57..0fbf06fb2fb 100644 --- a/testbench/tb_top.sv +++ b/testbench/tb_top.sv @@ -2227,48 +2227,7 @@ end : Gen_iccm_enable `include "icache_macros.svh" - // Define signals for ICache export interface to be used in macros that instantiate memory. - - logic clk; - logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren; - logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] ic_b_sb_bit_en_vec; - logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] wb_packeddout_pre; - logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_sb_wr_data; - logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q; - logic [pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final; - logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final_up; - logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][71-1:0] wb_dout_pre_up; - logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_clken_final; - logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_wren_q; - logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_wren_biten_vec; - logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_data_raw_packed_pre; - logic [25:0] ic_tag_wr_data; - logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] ic_rw_addr_q; - logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] ic_tag_data_raw_pre; - - always_comb begin - clk = el2_mem_export.clk; - ic_b_sb_wren = el2_mem_export.ic_b_sb_wren; - ic_b_sb_bit_en_vec = el2_mem_export.ic_b_sb_bit_en_vec; - ic_sb_wr_data = el2_mem_export.ic_sb_wr_data; - ic_rw_addr_bank_q = el2_mem_export.ic_rw_addr_bank_q; - ic_bank_way_clken_final = el2_mem_export.ic_bank_way_clken_final; - ic_bank_way_clken_final_up = el2_mem_export.ic_bank_way_clken_final_up; - - el2_mem_export.wb_packeddout_pre = wb_packeddout_pre; - el2_mem_export.wb_dout_pre_up = wb_dout_pre_up; - - ic_tag_clken_final = el2_mem_export.ic_tag_clken_final; - ic_tag_wren_q = el2_mem_export.ic_tag_wren_q; - ic_tag_wren_biten_vec = el2_mem_export.ic_tag_wren_biten_vec; - ic_tag_wr_data = el2_mem_export.ic_tag_wr_data; - ic_rw_addr_q = el2_mem_export.ic_rw_addr_q; - - el2_mem_export.ic_tag_data_raw_packed_pre = ic_tag_data_raw_packed_pre; - el2_mem_export.ic_tag_data_raw_pre = ic_tag_data_raw_pre; - end - - // ICACHE DATA +// ICACHE DATA if (pt.ICACHE_WAYPACK == 0 ) begin : PACKED_0 for (genvar i=0; i