From 43b1b146224fd40c5ed7d92f2f3e153be7a1dbd9 Mon Sep 17 00:00:00 2001 From: Krzysztof Bieganski Date: Wed, 8 Nov 2023 19:06:50 +0100 Subject: [PATCH] Format UVM testbench sources Signed-off-by: Krzysztof Bieganski --- testbench/uvm/mem/hdl/mem_agent.sv | 6 +-- testbench/uvm/mem/hdl/mem_base_test.sv | 31 +++++++-------- testbench/uvm/mem/hdl/mem_driver.sv | 17 ++++---- testbench/uvm/mem/hdl/mem_interface.sv | 8 +++- testbench/uvm/mem/hdl/mem_scoreboard.sv | 53 +++++++++++++------------ testbench/uvm/mem/hdl/mem_seq_item.sv | 19 ++++----- testbench/uvm/mem/hdl/mem_sequence.sv | 28 ++++++------- testbench/uvm/mem/hdl/mem_sequencer.sv | 6 +-- testbench/uvm/mem/hdl/mem_wr_rd_test.sv | 6 +-- testbench/uvm/mem/hdl/tbench_top.sv | 45 +++++++++++---------- 10 files changed, 114 insertions(+), 105 deletions(-) diff --git a/testbench/uvm/mem/hdl/mem_agent.sv b/testbench/uvm/mem/hdl/mem_agent.sv index 59896b60a85..184a9f742ea 100644 --- a/testbench/uvm/mem/hdl/mem_agent.sv +++ b/testbench/uvm/mem/hdl/mem_agent.sv @@ -22,7 +22,7 @@ class mem_agent extends uvm_agent; //--------------------------------------- // constructor //--------------------------------------- - function new (string name, uvm_component parent); + function new(string name, uvm_component parent); super.new(name, parent); endfunction : new @@ -35,7 +35,7 @@ class mem_agent extends uvm_agent; monitor = mem_monitor::type_id::create("monitor", this); //creating driver and sequencer only for ACTIVE agent - if(get_is_active() == UVM_ACTIVE) begin + if (get_is_active() == UVM_ACTIVE) begin driver = mem_driver::type_id::create("driver", this); sequencer = mem_sequencer::type_id::create("sequencer", this); end @@ -45,7 +45,7 @@ class mem_agent extends uvm_agent; // connect_phase - connecting the driver and sequencer port //--------------------------------------- function void connect_phase(uvm_phase phase); - if(get_is_active() == UVM_ACTIVE) begin + if (get_is_active() == UVM_ACTIVE) begin driver.seq_item_port.connect(sequencer.seq_item_export); end endfunction : connect_phase diff --git a/testbench/uvm/mem/hdl/mem_base_test.sv b/testbench/uvm/mem/hdl/mem_base_test.sv index 320f1a77a05..444747489e8 100644 --- a/testbench/uvm/mem/hdl/mem_base_test.sv +++ b/testbench/uvm/mem/hdl/mem_base_test.sv @@ -15,8 +15,8 @@ class mem_model_base_test extends uvm_test; //--------------------------------------- // constructor //--------------------------------------- - function new(string name = "mem_model_base_test",uvm_component parent=null); - super.new(name,parent); + function new(string name = "mem_model_base_test", uvm_component parent = null); + super.new(name, parent); endfunction : new //--------------------------------------- @@ -40,20 +40,19 @@ class mem_model_base_test extends uvm_test; //--------------------------------------- // end_of_elobaration phase //--------------------------------------- - function void report_phase(uvm_phase phase); - uvm_report_server svr; - super.report_phase(phase); - - svr = uvm_report_server::get_server(); - if(svr.get_severity_count(UVM_FATAL)+svr.get_severity_count(UVM_ERROR)>0) begin - `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) - `uvm_info(get_type_name(), "---- TEST FAIL ----", UVM_NONE) - `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) - end - else begin - `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) - `uvm_info(get_type_name(), "---- TEST PASS ----", UVM_NONE) - `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) + function void report_phase(uvm_phase phase); + uvm_report_server svr; + super.report_phase(phase); + + svr = uvm_report_server::get_server(); + if (svr.get_severity_count(UVM_FATAL) + svr.get_severity_count(UVM_ERROR) > 0) begin + `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) + `uvm_info(get_type_name(), "---- TEST FAIL ----", UVM_NONE) + `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) + end else begin + `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) + `uvm_info(get_type_name(), "---- TEST PASS ----", UVM_NONE) + `uvm_info(get_type_name(), "---------------------------------------", UVM_NONE) end endfunction diff --git a/testbench/uvm/mem/hdl/mem_driver.sv b/testbench/uvm/mem/hdl/mem_driver.sv index c338dee63da..c11c0e67e6c 100644 --- a/testbench/uvm/mem/hdl/mem_driver.sv +++ b/testbench/uvm/mem/hdl/mem_driver.sv @@ -15,7 +15,7 @@ class mem_driver extends uvm_driver #(mem_seq_item); //--------------------------------------- // Constructor //--------------------------------------- - function new (string name, uvm_component parent); + function new(string name, uvm_component parent); super.new(name, parent); endfunction : new @@ -24,9 +24,9 @@ class mem_driver extends uvm_driver #(mem_seq_item); //--------------------------------------- function void build_phase(uvm_phase phase); super.build_phase(phase); - if(!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif)) - `uvm_fatal("NO_VIF",{"virtual interface must be set for: ",get_full_name(),".vif"}); - endfunction: build_phase + if (!uvm_config_db#(virtual mem_if)::get(this, "", "vif", vif)) + `uvm_fatal("NO_VIF", {"virtual interface must be set for: ", get_full_name(), ".vif"}); + endfunction : build_phase //--------------------------------------- // run phase @@ -50,14 +50,13 @@ class mem_driver extends uvm_driver #(mem_seq_item); `DRIV_IF.addr <= req.addr; - if(req.wr_en) begin // write operation + if (req.wr_en) begin // write operation `uvm_info(get_type_name(), $sformatf("WR: 0x%08X <= 0x%08X", req.addr, req.wdata), UVM_LOW) - `DRIV_IF.wr_en <= 1'b1;//req.wr_en; + `DRIV_IF.wr_en <= 1'b1; //req.wr_en; `DRIV_IF.wdata <= req.wdata; @(posedge vif.clk); - end - else if(req.rd_en) begin //read operation - `DRIV_IF.rd_en <= 1'b1;//req.rd_en; + end else if (req.rd_en) begin //read operation + `DRIV_IF.rd_en <= 1'b1; //req.rd_en; @(posedge vif.clk); `DRIV_IF.rd_en <= 0; @(posedge vif.clk); diff --git a/testbench/uvm/mem/hdl/mem_interface.sv b/testbench/uvm/mem/hdl/mem_interface.sv index fabcf7694c1..86e6dfa671b 100644 --- a/testbench/uvm/mem/hdl/mem_interface.sv +++ b/testbench/uvm/mem/hdl/mem_interface.sv @@ -2,9 +2,13 @@ // mem_interface - www.verificationguide.com //------------------------------------------------------------------------- -interface mem_if (input logic clk,reset); +interface mem_if ( + input logic clk, + reset +); - `include "el2_param.vh" ; + `include "el2_param.vh" + ; //--------------------------------------- //declaring the signals diff --git a/testbench/uvm/mem/hdl/mem_scoreboard.sv b/testbench/uvm/mem/hdl/mem_scoreboard.sv index cb21adb91e1..d3fa2e50c01 100644 --- a/testbench/uvm/mem/hdl/mem_scoreboard.sv +++ b/testbench/uvm/mem/hdl/mem_scoreboard.sv @@ -4,7 +4,8 @@ class mem_scoreboard extends uvm_scoreboard; - `include "el2_param.vh" ; + `include "el2_param.vh" + ; //--------------------------------------- // declaring pkt_qu to store the pkt's recived from monitor @@ -14,18 +15,18 @@ class mem_scoreboard extends uvm_scoreboard; //--------------------------------------- // sc_mem //--------------------------------------- - bit [pt.DCCM_FDATA_WIDTH-1:0] sc_mem [int]; + bit [pt.DCCM_FDATA_WIDTH-1:0] sc_mem[int]; //--------------------------------------- //port to recive packets from monitor //--------------------------------------- - uvm_analysis_imp#(mem_seq_item, mem_scoreboard) item_collected_export; + uvm_analysis_imp #(mem_seq_item, mem_scoreboard) item_collected_export; `uvm_component_utils(mem_scoreboard) //--------------------------------------- // new - constructor //--------------------------------------- - function new (string name, uvm_component parent); + function new(string name, uvm_component parent); super.new(name, parent); endfunction : new //--------------------------------------- @@ -33,9 +34,9 @@ class mem_scoreboard extends uvm_scoreboard; //--------------------------------------- function void build_phase(uvm_phase phase); super.build_phase(phase); - item_collected_export = new("item_collected_export", this); - foreach(sc_mem[i]) sc_mem[i] = {(pt.DCCM_FDATA_WIDTH){1'b1}}; - endfunction: build_phase + item_collected_export = new("item_collected_export", this); + foreach (sc_mem[i]) sc_mem[i] = {(pt.DCCM_FDATA_WIDTH) {1'b1}}; + endfunction : build_phase //--------------------------------------- // write task - recives the pkt from monitor and pushes into queue @@ -53,28 +54,28 @@ class mem_scoreboard extends uvm_scoreboard; mem_seq_item mem_pkt; forever begin - wait(pkt_qu.size() > 0); + wait (pkt_qu.size() > 0); mem_pkt = pkt_qu.pop_front(); - if(mem_pkt.wr_en) begin + if (mem_pkt.wr_en) begin sc_mem[mem_pkt.addr] = mem_pkt.wdata; - `uvm_info(get_type_name(),$sformatf("------ :: WRITE DATA :: ------"),UVM_LOW) - `uvm_info(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr),UVM_LOW) - `uvm_info(get_type_name(),$sformatf("Data: %0h",mem_pkt.wdata),UVM_LOW) - `uvm_info(get_type_name(),"------------------------------------",UVM_LOW) - end - else if(mem_pkt.rd_en) begin - if(sc_mem[mem_pkt.addr] == mem_pkt.rdata) begin - `uvm_info(get_type_name(),$sformatf("------ :: READ DATA Match :: ------"),UVM_LOW) - `uvm_info(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr),UVM_LOW) - `uvm_info(get_type_name(),$sformatf("Expected Data: %0h Actual Data: %0h",sc_mem[mem_pkt.addr],mem_pkt.rdata),UVM_LOW) - `uvm_info(get_type_name(),"------------------------------------",UVM_LOW) - end - else begin - `uvm_error(get_type_name(),"------ :: READ DATA Mismatch :: ------") - `uvm_error(get_type_name(),$sformatf("Addr: %0h",mem_pkt.addr)) - `uvm_error(get_type_name(),$sformatf("Expected Data: %0h Actual Data: %0h",sc_mem[mem_pkt.addr],mem_pkt.rdata)) - `uvm_error(get_type_name(),"------------------------------------") + `uvm_info(get_type_name(), $sformatf("------ :: WRITE DATA :: ------"), UVM_LOW) + `uvm_info(get_type_name(), $sformatf("Addr: %0h", mem_pkt.addr), UVM_LOW) + `uvm_info(get_type_name(), $sformatf("Data: %0h", mem_pkt.wdata), UVM_LOW) + `uvm_info(get_type_name(), "------------------------------------", UVM_LOW) + end else if (mem_pkt.rd_en) begin + if (sc_mem[mem_pkt.addr] == mem_pkt.rdata) begin + `uvm_info(get_type_name(), $sformatf("------ :: READ DATA Match :: ------"), UVM_LOW) + `uvm_info(get_type_name(), $sformatf("Addr: %0h", mem_pkt.addr), UVM_LOW) + `uvm_info(get_type_name(), $sformatf("Expected Data: %0h Actual Data: %0h", + sc_mem[mem_pkt.addr], mem_pkt.rdata), UVM_LOW) + `uvm_info(get_type_name(), "------------------------------------", UVM_LOW) + end else begin + `uvm_error(get_type_name(), "------ :: READ DATA Mismatch :: ------") + `uvm_error(get_type_name(), $sformatf("Addr: %0h", mem_pkt.addr)) + `uvm_error(get_type_name(), $sformatf( + "Expected Data: %0h Actual Data: %0h", sc_mem[mem_pkt.addr], mem_pkt.rdata)) + `uvm_error(get_type_name(), "------------------------------------") end end end diff --git a/testbench/uvm/mem/hdl/mem_seq_item.sv b/testbench/uvm/mem/hdl/mem_seq_item.sv index 1920d07542b..9be1ae5ef19 100644 --- a/testbench/uvm/mem/hdl/mem_seq_item.sv +++ b/testbench/uvm/mem/hdl/mem_seq_item.sv @@ -4,25 +4,26 @@ class mem_seq_item extends uvm_sequence_item; - `include "el2_param.vh" ; + `include "el2_param.vh" + ; //--------------------------------------- //data and control fields //--------------------------------------- - rand bit [pt.DCCM_BITS-1:0] addr; - rand bit wr_en; - rand bit rd_en; + rand bit [ pt.DCCM_BITS-1:0] addr; + rand bit wr_en; + rand bit rd_en; rand bit [pt.DCCM_FDATA_WIDTH-1:0] wdata; - bit [pt.DCCM_FDATA_WIDTH-1:0] rdata; + bit [pt.DCCM_FDATA_WIDTH-1:0] rdata; //--------------------------------------- //Utility and Field macros //--------------------------------------- `uvm_object_utils_begin(mem_seq_item) - `uvm_field_int(addr,UVM_ALL_ON) - `uvm_field_int(wr_en,UVM_ALL_ON) - `uvm_field_int(rd_en,UVM_ALL_ON) - `uvm_field_int(wdata,UVM_ALL_ON) + `uvm_field_int(addr, UVM_ALL_ON) + `uvm_field_int(wr_en, UVM_ALL_ON) + `uvm_field_int(rd_en, UVM_ALL_ON) + `uvm_field_int(wdata, UVM_ALL_ON) `uvm_object_utils_end //--------------------------------------- diff --git a/testbench/uvm/mem/hdl/mem_sequence.sv b/testbench/uvm/mem/hdl/mem_sequence.sv index 78177606dcc..d7680df02de 100644 --- a/testbench/uvm/mem/hdl/mem_sequence.sv +++ b/testbench/uvm/mem/hdl/mem_sequence.sv @@ -5,7 +5,7 @@ //========================================================================= // mem_sequence - random stimulus //========================================================================= -class mem_sequence extends uvm_sequence#(mem_seq_item); +class mem_sequence extends uvm_sequence #(mem_seq_item); `uvm_object_utils(mem_sequence) @@ -22,14 +22,14 @@ class mem_sequence extends uvm_sequence#(mem_seq_item); // create, randomize and send the item to driver //--------------------------------------- virtual task body(); - repeat(2) begin - req = mem_seq_item::type_id::create("req"); - wait_for_grant(); - req.randomize(); - req.addr = (req.addr / 4) * 4; // Align to 4 - send_request(req); - wait_for_item_done(); - end + repeat (2) begin + req = mem_seq_item::type_id::create("req"); + wait_for_grant(); + req.randomize(); + req.addr = (req.addr / 4) * 4; // Align to 4 + send_request(req); + wait_for_item_done(); + end endtask endclass //========================================================================= @@ -37,7 +37,7 @@ endclass //========================================================================= // write_sequence - "write" type //========================================================================= -class write_sequence extends uvm_sequence#(mem_seq_item); +class write_sequence extends uvm_sequence #(mem_seq_item); `uvm_object_utils(write_sequence) @@ -63,7 +63,7 @@ endclass //========================================================================= // read_sequence - "read" type //========================================================================= -class read_sequence extends uvm_sequence#(mem_seq_item); +class read_sequence extends uvm_sequence #(mem_seq_item); `uvm_object_utils(read_sequence) @@ -89,7 +89,7 @@ endclass //========================================================================= // write_read_sequence - "write" followed by "read" //========================================================================= -class write_read_sequence extends uvm_sequence#(mem_seq_item); +class write_read_sequence extends uvm_sequence #(mem_seq_item); `uvm_object_utils(write_read_sequence) @@ -126,7 +126,7 @@ endclass //========================================================================= // wr_rd_sequence - "write" followed by "read" (sequence's inside sequences) //========================================================================= -class wr_rd_sequence extends uvm_sequence#(mem_seq_item); +class wr_rd_sequence extends uvm_sequence #(mem_seq_item); //--------------------------------------- //Declaring sequences @@ -143,7 +143,7 @@ class wr_rd_sequence extends uvm_sequence#(mem_seq_item); endfunction virtual task body(); - repeat(10) begin + repeat (10) begin `uvm_do(seq) end endtask diff --git a/testbench/uvm/mem/hdl/mem_sequencer.sv b/testbench/uvm/mem/hdl/mem_sequencer.sv index b62f7902f54..b2b2578f191 100644 --- a/testbench/uvm/mem/hdl/mem_sequencer.sv +++ b/testbench/uvm/mem/hdl/mem_sequencer.sv @@ -8,9 +8,9 @@ // uvm_sequencer#(mem_seq_item); `ifdef VERILATOR -class mem_sequencer extends uvm_sequencer#(mem_seq_item,mem_seq_item); +class mem_sequencer extends uvm_sequencer #(mem_seq_item,mem_seq_item); `else -class mem_sequencer extends uvm_sequencer#(mem_seq_item); +class mem_sequencer extends uvm_sequencer #(mem_seq_item); `endif `uvm_component_utils(mem_sequencer) @@ -19,7 +19,7 @@ class mem_sequencer extends uvm_sequencer#(mem_seq_item); //constructor //--------------------------------------- function new(string name, uvm_component parent); - super.new(name,parent); + super.new(name, parent); endfunction endclass diff --git a/testbench/uvm/mem/hdl/mem_wr_rd_test.sv b/testbench/uvm/mem/hdl/mem_wr_rd_test.sv index 5a33f063f10..98661e2fa1b 100644 --- a/testbench/uvm/mem/hdl/mem_wr_rd_test.sv +++ b/testbench/uvm/mem/hdl/mem_wr_rd_test.sv @@ -13,8 +13,8 @@ class mem_wr_rd_test extends mem_model_base_test; //--------------------------------------- // constructor //--------------------------------------- - function new(string name = "mem_wr_rd_test",uvm_component parent=null); - super.new(name,parent); + function new(string name = "mem_wr_rd_test", uvm_component parent = null); + super.new(name, parent); endfunction : new //--------------------------------------- @@ -33,7 +33,7 @@ class mem_wr_rd_test extends mem_model_base_test; task run_phase(uvm_phase phase); phase.raise_objection(this); - seq.start(env.mem_agnt.sequencer); + seq.start(env.mem_agnt.sequencer); phase.drop_objection(this); endtask : run_phase diff --git a/testbench/uvm/mem/hdl/tbench_top.sv b/testbench/uvm/mem/hdl/tbench_top.sv index 71c3537f3e0..e77000e7cd6 100644 --- a/testbench/uvm/mem/hdl/tbench_top.sv +++ b/testbench/uvm/mem/hdl/tbench_top.sv @@ -30,7 +30,7 @@ module tbench_top; //--------------------------------------- initial begin reset = 1; - #5 reset =0; + #5 reset = 0; end //--------------------------------------- @@ -44,46 +44,51 @@ module tbench_top; //--------------------------------------- //interface instance //--------------------------------------- - mem_if intf(clk,reset); + mem_if intf ( + clk, + reset + ); //--------------------------------------- //DUT instance //--------------------------------------- el2_lsu_dccm_mem DUT ( - .clk (intf.clk), - .active_clk (intf.clk), - .rst_l (~intf.reset), - .clk_override (1'b0), - .scan_mode (1'b0), + .clk (intf.clk), + .active_clk (intf.clk), + .rst_l (~intf.reset), + .clk_override(1'b0), + .scan_mode (1'b0), - .dccm_wren (intf.wr_en), - .dccm_rden (intf.rd_en), - .dccm_wr_addr_hi (intf.addr), - .dccm_wr_addr_lo (intf.addr), - .dccm_rd_addr_hi (intf.addr), - .dccm_rd_addr_lo (intf.addr), - .dccm_wr_data_hi (intf.wdata), - .dccm_wr_data_lo (intf.wdata), - .dccm_rd_data_hi (), // For aligned read/write this should match the lo part - .dccm_rd_data_lo (intf.rdata) + .dccm_wren (intf.wr_en), + .dccm_rden (intf.rd_en), + .dccm_wr_addr_hi(intf.addr), + .dccm_wr_addr_lo(intf.addr), + .dccm_rd_addr_hi(intf.addr), + .dccm_rd_addr_lo(intf.addr), + .dccm_wr_data_hi(intf.wdata), + .dccm_wr_data_lo(intf.wdata), + .dccm_rd_data_hi(), // For aligned read/write this should match the lo part + .dccm_rd_data_lo(intf.rdata) ); // Debug, dump memory signals on each clock cycle always @(posedge intf.clk) - $display("a:%08X w:%d wd:%08X r:%d rd:%08X", + $display( + "a:%08X w:%d wd:%08X r:%d rd:%08X", intf.addr, intf.wr_en, intf.wdata, intf.rd_en, - intf.rdata); + intf.rdata + ); //--------------------------------------- //passing the interface handle to lower heirarchy using set method //and enabling the wave dump //--------------------------------------- initial begin - uvm_config_db#(virtual mem_if)::set(uvm_root::get(),"*","vif",intf); + uvm_config_db#(virtual mem_if)::set(uvm_root::get(), "*", "vif", intf); end //---------------------------------------