diff --git a/BUILD.bazel b/BUILD.bazel index 885571722c52..7b3e08e1dedc 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -17,10 +17,245 @@ package( ], ) -load("//build/kernel/kleaf:common_kernels.bzl", "define_common_kernels") +package( + default_visibility = [ + "//private/google-modules:__subpackages__", + ], +) + +load("//build/bazel_common_rules/dist:dist.bzl", "copy_to_dist_dir") +load("//build/kernel/kleaf:common_kernels.bzl", "aarch64_outs", "define_common_kernels") +load("//build/kleaf:kernel.bzl", "kernel_build", "kernel_modules_install") +load("@kernel_toolchain_info//:dict.bzl", "CLANG_VERSION") + +_aarch64_additional_kmi_symbol_lists = [ + # keep sorted + "android/abi_gki_aarch64_core", + "android/abi_gki_aarch64_db845c", + "android/abi_gki_aarch64_exynos", + "android/abi_gki_aarch64_fips140", + "android/abi_gki_aarch64_generic", + "android/abi_gki_aarch64_hikey960", + "android/abi_gki_aarch64_rockchip", + "android/abi_gki_aarch64_type_visibility", + "android/abi_gki_aarch64_virtual_device", +] + +define_common_kernels(target_configs = { + # Sync with build.config.gki.aarch64 + "kernel_aarch64": { + "kmi_symbol_list": "android/abi_gki_aarch64", + "additional_kmi_symbol_lists": _aarch64_additional_kmi_symbol_lists, + "abi_definition": "android/abi_gki_aarch64.xml", + }, + "kernel_aarch64_debug": { + "kmi_symbol_list": "android/abi_gki_aarch64", + "additional_kmi_symbol_lists": _aarch64_additional_kmi_symbol_lists, + "abi_definition": "android/abi_gki_aarch64.xml", + }, +}) + +kernel_build( + name = "cloudripper", + srcs = glob( + ["**"], + exclude = [ + ".*", + ".*/**", + "BUILD.bazel", + "**/*.bzl", + ], + ), + outs = aarch64_outs + [ + # Sync with build.config.cloudripper + "arch/arm64/boot/dts/google/gs201-a0.dtb", + "arch/arm64/boot/dts/google/dtbo.img", + + # TODO(b/197995714): Add other things built by build.sh + # "abi_symbollist", + # "boot.img", + # "vendor_boot.img", + ], + build_config = "build.config.cloudripper", + module_outs = [ + "acpm_flexpmu_dbg.ko", + "acpm_mbox_test.ko", + "at24.ko", + "bbd.ko", + "bcm47765.ko", + "bc_max77759.ko", + "bcm_dbg.ko", + "boot_device_spi.ko", + "bts.ko", + "clk_exynos.ko", + "cmupmucal.ko", + "cpif.ko", + "cpif_page.ko", + "cp_thermal_zone.ko", + "dbgcore-dump.ko", + "debug-reboot.ko", + "debug-snapshot-debug-kinfo.ko", + "dss.ko", + "dwc3-exynos-usb.ko", + "ect_parser.ko", + "eh.ko", + "ehld.ko", + "exynos-acme.ko", + "exynos-adv-tracer.ko", + "exynos-bcm_dbg-dump.ko", + "exynos-coresight-etm.ko", + "exynos-coresight.ko", + "exynos-cpuhp.ko", + "exynos-cpupm.ko", + "exynos-debug-test.ko", + "exynos_devfreq.ko", + "exynos_dit.ko", + "exynos-dm.ko", + "exynos-ecc-handler.ko", + "exynos_mct.ko", + "exynos_mfc.ko", + "exynos-pcie-iommu.ko", + "exynos-pd-dbg.ko", + "exynos-pd_el3.ko", + "exynos-pd.ko", + "exynos-pm.ko", + "exynos_pm_qos.ko", + "exynos-pmu-if.ko", + "exynos-seclog.ko", + "exynos_tty.ko", + "g2d.ko", + "google_bcl.ko", + "gpu_cooling.ko", + "gs_acpm.ko", + "gsa_gsc.ko", + "gsa.ko", + "gs-chipid.ko", + "gs_thermal.ko", + "gvotable.ko", + "hardlockup-debug.ko", + "hardlockup-watchdog.ko", + "i2c-acpm.ko", + "i2c-dev.ko", + "i2c-exynos5.ko", + "itmon.ko", + "keycombo.ko", + "keydebug.ko", + "logbuffer.ko", + "lzo.ko", + "lzo-rle.ko", + "max77759_contaminant.ko", + "max77759_helper.ko", + "memlat-devfreq.ko", + "odpm.ko", + "pcie-exynos-core.ko", + "pcie-exynos-gs201-rc-cal.ko", + "phy-exynos-mipi-dsim.ko", + "phy-exynos-mipi.ko", + "phy-exynos-usbdrd-super.ko", + "pinctrl-samsung-core.ko", + "pinctrl-slg51000.ko", + "pinctrl-slg51002.ko", + "pixel-boot-metrics.ko", + "pixel-debug-test.ko", + "pl330.ko", + "pmic_class.ko", + "power_stats.ko", + "rtc-s2mpg12.ko", + "s2mpg12-key.ko", + "s2mpg12-mfd.ko", + "s2mpg12-powermeter.ko", + "s2mpg12-regulator.ko", + "s2mpg13-mfd.ko", + "s2mpg13-powermeter.ko", + "s2mpg13-regulator.ko", + "s2mpg1x-gpio.ko", + "s3c2410_wdt.ko", + "samsung_dma_heap.ko", + "samsung-dma.ko", + "samsung-iommu-group.ko", + "samsung_iommu.ko", + "samsung-secure-iova.ko", + "sbb-mux.ko", + "sched_tp.ko", + "sg.ko", + "shm_ipc.ko", + "sjtag-driver.ko", + "slc_acpm.ko", + "slc_dummy.ko", + "slc_pmon.ko", + "slc_pt.ko", + "slg51000-core.ko", + "slg51000-regulator.ko", + "slg51002-core.ko", + "slg51002-regulator.ko", + "smfc.ko", + "spidev.ko", + "spi-s3c64xx.ko", + "sscoredump.ko", + "stmvl53l1.ko", + "systrace.ko", + "tcpci_max77759.ko", + "trusty-core.ko", + "trusty-ipc.ko", + "trusty-irq.ko", + "trusty-log.ko", + "trusty-test.ko", + "trusty-virtio.ko", + "ufs-exynos-core.ko", + "usb_f_dm1.ko", + "usb_f_dm.ko", + "usb_f_etr_miu.ko", + "usb_psy.ko", + "vh_cgroup.ko", + "vh_fs.ko", + "vh_i2c.ko", + "vh_preemptirq_long.ko", + "vh_sched.ko", + "vh_thermal.ko", + "videobuf2-dma-sg.ko", + "xhci-exynos.ko", + "zcomp_cpu.ko", + "zcomp_eh.ko", + "zram.ko", + "zsmalloc.ko", + ], + deps = [ + "//prebuilts/misc/linux-x86/libufdt:mkdtimg", + ], +) -# This uses android/abi_gki_aarch64* in kmi_configs. If the list of -# glob(["android/abi_gki_aarch64*"]) differs from -# KMI_SYMBOL_LIST + ADDITIONAL_KMI_SYMBOL_LISTS in build.config.gki.aarch64, -# or TRIM_NONLISTED_KMI changes, override kmi_configs here. -define_common_kernels() +kernel_modules_install( + name = "cloudripper_modules_install", + kernel_build = ":cloudripper", + kernel_modules = [ + "//private/google-modules/amplifiers/cs35l41:cs35l41.cloudripper", + "//private/google-modules/amplifiers/cs35l45:cs35l45.cloudripper", + "//private/google-modules/amplifiers/cs40l26:cs40l26.cloudripper", + "//private/google-modules/amplifiers/drv2624:drv2624.cloudripper", + "//private/google-modules/aoc/alsa:alsa.cloudripper", + "//private/google-modules/aoc/usb:usb.cloudripper", + "//private/google-modules/aoc:aoc.cloudripper", + "//private/google-modules/bluetooth/broadcom:broadcom.cloudripper", + "//private/google-modules/bms:bms.cloudripper", + "//private/google-modules/display/samsung:samsung.cloudripper", + "//private/google-modules/edgetpu/drivers/edgetpu:edgetpu.cloudripper", + "//private/google-modules/gpu/mali_kbase:mali_kbase.cloudripper", + "//private/google-modules/gpu/mali_pixel:mali_pixel.cloudripper", + "//private/google-modules/lwis:lwis.cloudripper", + "//private/google-modules/nfc:nfc.cloudripper", + "//private/google-modules/power/reset:reset.cloudripper", + "//private/google-modules/touch/common:common.cloudripper", + "//private/google-modules/touch/sec:sec.cloudripper", + "//private/google-modules/uwb/kernel:kernel.cloudripper", + "//private/google-modules/video/gchips:gchips.cloudripper", + "//private/google-modules/wlan/bcmdhd4389:bcmdhd4389.cloudripper", + ], +) + +copy_to_dist_dir( + name = "cloudripper_dist", + data = [ + ":cloudripper_for_dist", + ":cloudripper_modules_install", + ], +) diff --git a/Documentation/ABI/testing/sysfs-bus-i2c-devices-slg51002 b/Documentation/ABI/testing/sysfs-bus-i2c-devices-slg51002 new file mode 100644 index 000000000000..64f4897da219 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-i2c-devices-slg51002 @@ -0,0 +1,12 @@ +What: /sys/bus/i2c/devices/.../chip_id +Date: June 2021 +KernelVersion: 5.10 +Contact: CY Tseng +Description: Reports the chip identifier as a hexadecimal number. + +What: /sys/bus/i2c/devices/.../chip_always_on +Date: June 2021 +KernelVersion: 5.10 +Contact: CY Tseng +Description: Sets the power state of the device. 0 sets the device into + power saving mode. 1 sets the device into power always-on mode. diff --git a/Documentation/ABI/testing/sysfs-driver-ufs-pixel b/Documentation/ABI/testing/sysfs-driver-ufs-pixel index 87ef17510050..42cefd420724 100644 --- a/Documentation/ABI/testing/sysfs-driver-ufs-pixel +++ b/Documentation/ABI/testing/sysfs-driver-ufs-pixel @@ -1,3 +1,22 @@ + +What: /sys/devices/platform/<....>ufs/power_stats +Date: April, 2022 +Contact: "Konstantin Vyshetsky" +Description: + This directory contains UFS power related statistical info. + fdevinit_read_count: number of time fDeviceInit flag read was + issued + fdevinit_read_max_latency_us: total amount of time in + microseconds fDeviceInit flag read operations consumed + fdevinit_read_time_spent_us: maximum latency in microseconds + of a single fDeviceInit flag read operation + fdevinit_set_count: number of time fDeviceInit flag set was + issued + fdevinit_set_max_latency_us: total amount of time in + microseconds fDeviceInit flag set operations consumed + fdevinit_set_time_spent_us: maximum latency in microseconds + of a single fDeviceInit flag set operation + What: /sys/devices/platform/<....>ufs/power_info Date: December, 2020 Contact: "Konstantin Vyshetsky" diff --git a/Makefile.ext_modules.cloudripper b/Makefile.ext_modules.cloudripper new file mode 100644 index 000000000000..4691ce4bb800 --- /dev/null +++ b/Makefile.ext_modules.cloudripper @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only + +rel_path := ../google-modules + +ext_modules := +ext_modules += amplifiers/audiometrics +ext_modules += amplifiers/cs35l41 +ext_modules += amplifiers/cs35l45 +ext_modules += amplifiers/cs40l26 +ext_modules += amplifiers/drv2624 +ext_modules += aoc +ext_modules += aoc/alsa +ext_modules += aoc/usb +ext_modules += bluetooth/broadcom +ext_modules += bms +ext_modules += display/samsung +ext_modules += edgetpu/janeiro/drivers/edgetpu +ext_modules += gpu/mali_kbase +ext_modules += gpu/mali_pixel +ext_modules += gxp/gs201 +ext_modules += lwis +ext_modules += nfc +ext_modules += power/reset +ext_modules += touch/common +ext_modules += touch/focaltech/ft3658 +ext_modules += touch/sec +ext_modules += touch/synaptics +ext_modules += wlan/wlan_ptracker +ext_modules += wlan/bcmdhd4389 +ext_modules += video/gchips + +# Add any modules which have their own UAPI headers to this list. This will +# cause the build to run the module makefile with headers_install target. +has_uapi_headers := +has_uapi_headers += touch/common +has_uapi_headers += video/gchips + +install_uapi_headers_targets := $(has_uapi_headers:=_headers_install) + +ifneq ($(wildcard $(KERNEL_SRC)/$(rel_path)/uwb/kernel),) +ext_modules += uwb/kernel +endif + +.PHONY: $(ext_modules) $(install_uapi_headers_targets) depmod allmodules + +allmodules: $(ext_modules) $(install_uapi_headers_targets) depmod + +touch/focaltech/ft3658: | touch/common + +touch/sec: | touch/common + +touch/synaptics: | touch/common + +aoc/alsa: | aoc + +aoc/usb: | aoc/alsa aoc + +power/reset: | bms + +# amplifiers/cs35l45 and amplifiers/cs35l41 both build identical version of +# snd-soc-wm-adsp.ko. To make sure the makefiles don't step on each other, +# create this fake order only dependency +# TODO(b/198105924): Identically named kernel modules: snd-soc-wm-adsp.ko +amplifiers/cs35l45: | amplifiers/cs35l41 + +gxp/gs201: | edgetpu/janeiro/drivers/edgetpu + +include $(KERNEL_SRC)/Makefile.ext_modules.include diff --git a/Makefile.ext_modules.slider b/Makefile.ext_modules.slider index 0ff3c92ce60f..44701addae00 100644 --- a/Makefile.ext_modules.slider +++ b/Makefile.ext_modules.slider @@ -23,11 +23,13 @@ ext_modules += touch/common ext_modules += touch/fts/ftm5 ext_modules += touch/sec ext_modules += wlan/bcmdhd4389 +ext_modules += video/gchips # Add any modules which have their own UAPI headers to this list. This will # cause the build to run the module makefile with headers_install target. has_uapi_headers := has_uapi_headers += touch/common +has_uapi_headers += video/gchips install_uapi_headers_targets := $(has_uapi_headers:=_headers_install) diff --git a/OWNERS b/OWNERS index f354ffdfbf08..052a34572804 100644 --- a/OWNERS +++ b/OWNERS @@ -1,13 +1,9 @@ file:/OWNERS_core per-file build*=set noparent per-file build*=saravanak@google.com,elavila@google.com,willmcvicker@google.com -per-file vendor_dlkm*=* +per-file vendor_{boot,kernel,dlkm}*=* +per-file Makefile.ext_modules*=* per-file build.config.slider*=* +per-file BUILD.bazel=* per-file repack_kernel_boot_images.sh=* per-file download_hlos_boot_images_and_repack_kernel_boot_images.sh=* - -# These changes will be reviewed by pixel kernel module approvers, see go/pixelkernel-owners-approval-of-kernel-modules for details. -per-file vendor_{boot,kernel_boot}*=set noparent -per-file vendor_{boot,kernel_boot}*=file:kernel/private/google-modules/misc:android-gs-pixel-mainline:OWNERS_kernel_modules -per-file Makefile.ext_modules*=set noparent -per-file Makefile.ext_modules*=file:kernel/private/google-modules/misc:android-gs-pixel-mainline:OWNERS_kernel_modules diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 8aa576d2b698..581cce734f4d 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -39,6 +39,7 @@ + @@ -87,16 +88,19 @@ + + + @@ -115,6 +119,7 @@ + @@ -231,12 +236,15 @@ + + + @@ -253,13 +261,18 @@ + + + + + @@ -272,13 +285,20 @@ + + + + + + + @@ -302,6 +322,9 @@ + + + @@ -310,6 +333,8 @@ + + @@ -325,6 +350,8 @@ + + @@ -342,6 +369,8 @@ + + @@ -627,6 +656,7 @@ + @@ -635,6 +665,7 @@ + @@ -650,6 +681,7 @@ + @@ -663,9 +695,11 @@ + + @@ -738,6 +772,7 @@ + @@ -909,13 +944,16 @@ + + + @@ -936,6 +974,11 @@ + + + + + @@ -1001,6 +1044,8 @@ + + @@ -1185,6 +1230,7 @@ + @@ -1197,6 +1243,7 @@ + @@ -1417,6 +1464,7 @@ + @@ -1599,6 +1647,9 @@ + + + @@ -1707,8 +1758,11 @@ + + + @@ -1747,9 +1801,11 @@ + + @@ -1853,7 +1909,15 @@ + + + + + + + + @@ -1983,6 +2047,7 @@ + @@ -2093,6 +2158,7 @@ + @@ -2100,6 +2166,8 @@ + + @@ -2272,6 +2340,8 @@ + + @@ -2292,6 +2362,7 @@ + @@ -2362,6 +2433,7 @@ + @@ -2493,6 +2565,8 @@ + + @@ -2545,6 +2619,12 @@ + + + + + + @@ -2595,6 +2675,7 @@ + @@ -2709,6 +2790,7 @@ + @@ -2723,11 +2805,13 @@ + + @@ -2743,9 +2827,11 @@ + + @@ -2817,6 +2903,8 @@ + + @@ -3001,7 +3089,10 @@ + + + @@ -3202,6 +3293,7 @@ + @@ -3482,21 +3574,27 @@ + + + + + + @@ -3508,9 +3606,16 @@ + + + + + + + @@ -3622,6 +3727,7 @@ + @@ -3713,6 +3819,8 @@ + + @@ -3745,12 +3853,15 @@ + + + @@ -3767,13 +3878,18 @@ + + + + + @@ -3786,13 +3902,20 @@ + + + + + + + @@ -3816,6 +3939,9 @@ + + + @@ -3824,6 +3950,8 @@ + + @@ -3839,6 +3967,8 @@ + + @@ -3848,8 +3978,14 @@ + + + + + + @@ -3886,6 +4022,7 @@ + @@ -3941,6 +4078,7 @@ + @@ -3952,6 +4090,7 @@ + @@ -4071,71 +4210,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -4219,14 +4293,6 @@ - - - - - - - - @@ -4879,6 +4945,14 @@ + + + + + + + + @@ -4912,7 +4986,7 @@ - + @@ -5436,6 +5510,14 @@ + + + + + + + + @@ -6490,34 +6572,34 @@ - - - - - - - - - - - - - - - + - + + + + + + + + + + + + + + + @@ -7277,6 +7359,7 @@ + @@ -7747,7 +7830,7 @@ - + @@ -7943,6 +8026,10 @@ + + + + @@ -8885,7 +8972,7 @@ - + @@ -9192,6 +9279,11 @@ + + + + + @@ -9461,6 +9553,23 @@ + + + + + + + + + + + + + + + + + @@ -9515,6 +9624,11 @@ + + + + + @@ -9968,23 +10082,7 @@ - - - - - - - - - - - - - - - - - + @@ -10410,9 +10508,6 @@ - - - @@ -11220,6 +11315,7 @@ + @@ -11295,6 +11391,7 @@ + @@ -11950,7 +12047,7 @@ - + @@ -12474,6 +12571,7 @@ + @@ -12486,6 +12584,7 @@ + @@ -12550,6 +12649,7 @@ + @@ -13027,7 +13127,29 @@ - + + + + + + + + + + + + + + + + + + + + + + + @@ -13289,72 +13411,72 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -14403,6 +14525,7 @@ + @@ -14952,7 +15075,7 @@ - + @@ -15081,6 +15204,7 @@ + @@ -15828,6 +15952,7 @@ + @@ -16875,6 +17000,23 @@ + + + + + + + + + + + + + + + + + @@ -18041,6 +18183,7 @@ + @@ -19899,7 +20042,7 @@ - + @@ -19912,6 +20055,10 @@ + + + + @@ -20113,6 +20260,7 @@ + @@ -20796,6 +20944,7 @@ + @@ -21597,6 +21746,20 @@ + + + + + + + + + + + + + + @@ -21834,7 +21997,7 @@ - + @@ -23426,6 +23589,23 @@ + + + + + + + + + + + + + + + + + @@ -24258,7 +24438,7 @@ - + @@ -25605,6 +25785,7 @@ + @@ -26222,7 +26403,7 @@ - + @@ -26518,6 +26699,23 @@ + + + + + + + + + + + + + + + + + @@ -26803,6 +27001,7 @@ + @@ -28138,6 +28337,7 @@ + @@ -28274,6 +28474,7 @@ + @@ -28507,6 +28708,11 @@ + + + + + @@ -28665,6 +28871,11 @@ + + + + + @@ -29125,6 +29336,14 @@ + + + + + + + + @@ -29797,6 +30016,7 @@ + @@ -31176,6 +31396,20 @@ + + + + + + + + + + + + + + @@ -33822,6 +34056,7 @@ + @@ -33867,7 +34102,7 @@ - + @@ -34739,6 +34974,11 @@ + + + + + @@ -35548,6 +35788,7 @@ + @@ -36654,7 +36895,7 @@ - + @@ -36933,13 +37174,13 @@ - + - + @@ -37948,24 +38189,36 @@ - - - - - - - - + - + + + + - + - + + + + + + + + + + + + + + + + + @@ -40165,6 +40418,7 @@ + @@ -41045,6 +41299,14 @@ + + + + + + + + @@ -44236,7 +44498,6 @@ - @@ -44568,6 +44829,7 @@ + @@ -45147,11 +45409,6 @@ - - - - - @@ -45491,6 +45748,7 @@ + @@ -46602,6 +46860,7 @@ + @@ -47648,14 +47907,6 @@ - - - - - - - - @@ -47717,6 +47968,7 @@ + @@ -47959,13 +48211,13 @@ - + - + - + @@ -47974,7 +48226,7 @@ - + @@ -48078,6 +48330,9 @@ + + + @@ -48351,6 +48606,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -48529,6 +48804,7 @@ + @@ -49619,32 +49895,7 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - + @@ -49738,6 +49989,12 @@ + + + + + + @@ -51162,6 +51419,7 @@ + @@ -51193,6 +51451,7 @@ + @@ -51603,6 +51862,14 @@ + + + + + + + + @@ -52126,7 +52393,7 @@ - + @@ -52841,6 +53108,11 @@ + + + + + @@ -54464,6 +54736,7 @@ + @@ -54809,7 +55082,6 @@ - @@ -55537,6 +55809,7 @@ + @@ -55723,6 +55996,29 @@ + + + + + + + + + + + + + + + + + + + + + + + @@ -58159,61 +58455,61 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -61008,6 +61304,7 @@ + @@ -61499,6 +61796,7 @@ + @@ -61759,7 +62057,7 @@ - + @@ -61850,7 +62148,7 @@ - + @@ -62900,6 +63198,14 @@ + + + + + + + + @@ -65170,6 +65476,11 @@ + + + + + @@ -65786,6 +66097,7 @@ + @@ -65866,7 +66178,7 @@ - + @@ -66153,6 +66465,10 @@ + + + + @@ -66581,7 +66897,7 @@ - + @@ -66728,6 +67044,10 @@ + + + + @@ -66803,6 +67123,7 @@ + @@ -66829,6 +67150,7 @@ + @@ -67124,69 +67446,69 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -67439,25 +67761,25 @@ - + - + - + - + - + - + - + @@ -67955,6 +68277,7 @@ + @@ -68518,6 +68841,11 @@ + + + + + @@ -68556,12 +68884,12 @@ - + - + - + @@ -69436,6 +69764,7 @@ + @@ -70050,7 +70379,7 @@ - + @@ -70077,7 +70406,7 @@ - + @@ -70088,7 +70417,7 @@ - + @@ -70894,7 +71223,7 @@ - + @@ -70907,7 +71236,7 @@ - + @@ -70937,7 +71266,7 @@ - + @@ -70980,7 +71309,7 @@ - + @@ -71007,7 +71336,7 @@ - + @@ -71015,7 +71344,7 @@ - + @@ -71023,7 +71352,7 @@ - + @@ -71036,25 +71365,25 @@ - + - + - + - + - + - + - + @@ -71087,7 +71416,7 @@ - + @@ -71098,7 +71427,7 @@ - + @@ -71111,7 +71440,7 @@ - + @@ -71157,7 +71486,7 @@ - + @@ -71182,15 +71511,15 @@ - + - + - + @@ -71198,7 +71527,7 @@ - + @@ -71292,7 +71621,7 @@ - + @@ -71300,21 +71629,21 @@ - + - + - + - + - + @@ -71351,10 +71680,10 @@ - + - + @@ -71370,7 +71699,7 @@ - + @@ -71397,10 +71726,10 @@ - + - + @@ -71444,7 +71773,7 @@ - + @@ -71457,7 +71786,7 @@ - + @@ -71487,7 +71816,7 @@ - + @@ -71500,7 +71829,7 @@ - + @@ -71536,13 +71865,13 @@ - + - + - + @@ -71603,7 +71932,7 @@ - + @@ -71614,13 +71943,13 @@ - + - + @@ -71628,7 +71957,7 @@ - + @@ -71644,7 +71973,7 @@ - + @@ -71748,7 +72077,7 @@ - + @@ -71897,10 +72226,10 @@ - + - + @@ -71916,27 +72245,27 @@ - + - + - + - + - + - + - + @@ -71952,22 +72281,22 @@ - + - + - + - + - + - + @@ -72026,36 +72355,36 @@ - + - + - + - + - + - + - + - + - + - + @@ -72066,7 +72395,7 @@ - + @@ -72090,96 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@@ - + - + @@ -98927,7 +99309,7 @@ - + @@ -98935,7 +99317,7 @@ - + @@ -98943,7 +99325,7 @@ - + @@ -98951,12 +99333,12 @@ - + - + @@ -98964,7 +99346,7 @@ - + @@ -98972,7 +99354,7 @@ - + @@ -98980,7 +99362,7 @@ - + @@ -98988,7 +99370,7 @@ - + @@ -98996,7 +99378,7 @@ - + @@ -99004,7 +99386,7 @@ - + @@ -99045,7 +99427,7 @@ - + @@ -99059,7 +99441,7 @@ - + @@ -99085,7 +99467,7 @@ - + @@ -99150,7 +99532,7 @@ - + @@ -99161,7 +99543,7 @@ - + @@ -99178,7 +99560,7 @@ - + @@ -99222,7 +99604,7 @@ - + @@ -99233,7 +99615,7 @@ - + @@ -99244,7 +99626,7 @@ - + @@ -99264,7 +99646,7 @@ - + @@ -99272,7 +99654,7 @@ - + @@ -99289,7 +99671,7 @@ - + @@ -99318,7 +99700,7 @@ - + @@ -99335,7 +99717,7 @@ - + @@ -99349,17 +99731,17 @@ - + - + - + @@ -99367,7 +99749,7 @@ - + @@ -99378,7 +99760,7 @@ - + @@ -99386,7 +99768,7 @@ - + @@ -99427,7 +99809,7 @@ - + @@ -99435,7 +99817,7 @@ - + @@ -99443,7 +99825,7 @@ - + @@ -99457,7 +99839,7 @@ - + @@ -99477,7 +99859,7 @@ - + @@ -99485,7 +99867,7 @@ - + @@ -99493,7 +99875,7 @@ - + @@ -99501,12 +99883,12 @@ - + - + @@ -99514,7 +99896,7 @@ - + @@ -99525,7 +99907,7 @@ - + @@ -99533,18 +99915,18 @@ - + - + - - + + @@ -99558,12 +99940,12 @@ - + - + @@ -99571,12 +99953,12 @@ - + - + @@ -99584,12 +99966,12 @@ - + - + @@ -99606,7 +99988,7 @@ - + @@ -99614,7 +99996,7 @@ - + @@ -99622,12 +100004,12 @@ - + - + @@ -99635,7 +100017,7 @@ - + @@ -99643,7 +100025,7 @@ - + @@ -99660,12 +100042,12 @@ - + - + @@ -99691,7 +100073,7 @@ - + @@ -99702,7 +100084,7 @@ - + @@ -99722,7 +100104,7 @@ - + @@ -99745,7 +100127,7 @@ - + @@ -99759,12 +100141,12 @@ - + - + @@ -99775,7 +100157,7 @@ - + @@ -99789,7 +100171,7 @@ - + @@ -99800,7 +100182,7 @@ - + @@ -99814,7 +100196,7 @@ - + @@ -99828,12 +100210,12 @@ - + - + @@ -99841,7 +100223,7 @@ - + @@ -99855,7 +100237,7 @@ - + @@ -99863,7 +100245,7 @@ - + @@ -99874,7 +100256,7 @@ - + @@ -99891,7 +100273,7 @@ - + @@ -99911,7 +100293,7 @@ - + @@ -99928,7 +100310,7 @@ - + @@ -99939,7 +100321,7 @@ - + @@ -99947,7 +100329,7 @@ - + @@ -99955,7 +100337,7 @@ - + @@ -99963,7 +100345,7 @@ - + @@ -99977,7 +100359,7 @@ - + @@ -99985,7 +100367,7 @@ - + @@ -99996,7 +100378,7 @@ - + @@ -100013,7 +100395,7 @@ - + @@ -100039,7 +100421,7 @@ - + @@ -100050,7 +100432,7 @@ - + @@ -100061,7 +100443,7 @@ - + @@ -100118,7 +100500,20 @@ - + + + + + + + + + + + + + + @@ -100468,11 +100863,6 @@ - - - - - @@ -100754,6 +101144,7 @@ + @@ -101233,6 +101624,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -101660,6 +102071,7 @@ + @@ -101976,6 +102388,7 @@ + @@ -102183,7 +102596,7 @@ - + @@ -102210,7 +102623,7 @@ - + @@ -102685,6 +103098,29 @@ + + + + + + + + + + + + + + + + + + + + + + + @@ -102838,6 +103274,20 @@ + + + + + + + + + + + + + + @@ -103300,7 +103750,50 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -104810,7 +105303,7 @@ - + @@ -104888,6 +105381,7 @@ + @@ -105041,6 +105535,7 @@ + @@ -107009,6 +107504,7 @@ + @@ -107679,7 +108175,7 @@ - + @@ -107904,6 +108400,7 @@ + @@ -108995,7 +109492,7 @@ - + @@ -109401,6 +109898,8 @@ + + @@ -109614,6 +110113,11 @@ + + + + + @@ -109898,6 +110402,11 @@ + + + + + @@ -109926,6 +110435,12 @@ + + + + + + @@ -109966,6 +110481,11 @@ + + + + + @@ -109990,10 +110510,10 @@ - - - - + + + + @@ -110080,6 +110600,13 @@ + + + + + + + @@ -110328,8 +110855,8 @@ - - + + @@ -110746,6 +111273,11 @@ + + + + + @@ -110787,6 +111319,18 @@ + + + + + + + + + + + + @@ -110904,25 +111448,43 @@ - - - - + + + + - - - - - - - - + + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + @@ -110937,6 +111499,12 @@ + + + + + + @@ -110952,6 +111520,11 @@ + + + + + @@ -110982,21 +111555,21 @@ - - - + + + - - - - + + + + - - - - + + + + @@ -111017,13 +111590,19 @@ - - - - - - - + + + + + + + + + + + + + @@ -111032,14 +111611,30 @@ - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + @@ -111075,6 +111670,21 @@ + + + + + + + + + + + + + + + @@ -111224,6 +111834,22 @@ + + + + + + + + + + + + + + + + @@ -111276,6 +111902,19 @@ + + + + + + + + + + + + + @@ -111363,6 +112002,16 @@ + + + + + + + + + + @@ -111402,12 +112051,15 @@ + + + @@ -111424,32 +112076,44 @@ - - - + + + + + + + + - - - + + + - + + - + + + + + + + @@ -111473,6 +112137,9 @@ + + + @@ -111481,6 +112148,8 @@ + + @@ -111496,6 +112165,8 @@ + + @@ -111589,6 +112260,14 @@ + + + + + + + + @@ -111897,10 +112576,10 @@ - - - - + + + + @@ -111992,8 +112671,8 @@ - - + + @@ -112840,16 +113519,16 @@ - - + + - - + + - - + + @@ -112987,30 +113666,30 @@ - - - - - - - + + + + + + + - - - - - + + + + + - - - - - - - - + + + + + + + + @@ -113027,25 +113706,25 @@ - - - - - - - - - - - + + + + + + + + + + + - - - - - - + + + + + + @@ -113087,9 +113766,9 @@ - - - + + + @@ -113128,24 +113807,24 @@ - - - + + + - - - + + + - - - + + + - - - + + + @@ -113162,9 +113841,9 @@ - - - + + + @@ -113185,6 +113864,12 @@ + + + + + + @@ -113216,6 +113901,11 @@ + + + + + @@ -113225,12 +113915,16 @@ + + + + @@ -113282,6 +113976,20 @@ + + + + + + + + + + + + + + @@ -113318,6 +114026,8 @@ + + @@ -113347,6 +114057,19 @@ + + + + + + + + + + + + + @@ -113375,6 +114098,20 @@ + + + + + + + + + + + + + + @@ -113725,6 +114462,11 @@ + + + + + @@ -114198,7 +114940,7 @@ - + @@ -114378,16 +115120,16 @@ - - + + - - + + @@ -114616,6 +115358,11 @@ + + + + + @@ -114630,6 +115377,11 @@ + + + + + @@ -114652,6 +115404,10 @@ + + + + @@ -114757,6 +115513,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -115095,6 +115875,16 @@ + + + + + + + + + + @@ -115690,81 +116480,81 @@ - - - + + + - - - + + + - - - - - + + + + + - - - + + + - - - + + + - - - - - + + + + + - - + + - - - + + + - - + + - - - + + + - - - - + + + + - - + + - - - - + + + + - - + + - - - + + + @@ -116160,6 +116950,10 @@ + + + + @@ -116168,8 +116962,8 @@ - - + + @@ -116218,6 +117012,11 @@ + + + + + @@ -117339,6 +118138,12 @@ + + + + + + @@ -118021,10 +118826,10 @@ - - - - + + + + @@ -118032,16 +118837,16 @@ - - + + - - + + - - + + @@ -118303,6 +119108,18 @@ + + + + + + + + + + + + @@ -118835,6 +119652,11 @@ + + + + + @@ -118843,12 +119665,20 @@ + + + + + + + + @@ -119035,6 +119865,13 @@ + + + + + + + @@ -119051,6 +119888,13 @@ + + + + + + + @@ -119272,16 +120116,16 @@ - - - + + + - - - - - + + + + + @@ -119410,8 +120254,8 @@ - - + + @@ -119435,29 +120279,29 @@ - - - + + + - - - - - + + + + + - - - + + + - - + + - - + + @@ -119530,10 +120374,10 @@ - - - - + + + + @@ -119592,10 +120436,49 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -119650,6 +120533,7 @@ + @@ -119810,11 +120694,11 @@ - + - - + + @@ -120017,8 +120901,8 @@ - - + + @@ -120270,6 +121154,9 @@ + + + @@ -120812,10 +121699,10 @@ - + - + @@ -120846,6 +121733,12 @@ + + + + + + @@ -120878,6 +121771,19 @@ + + + + + + + + + + + + + @@ -121351,11 +122257,11 @@ - - - - - + + + + + @@ -121712,6 +122618,15 @@ + + + + + + + + + @@ -121818,6 +122733,10 @@ + + + + @@ -122164,6 +123083,11 @@ + + + + + @@ -122874,6 +123798,17 @@ + + + + + + + + + + + @@ -123130,6 +124065,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -123282,10 +124243,10 @@ - + - + @@ -123389,6 +124350,12 @@ + + + + + + @@ -123524,17 +124491,17 @@ - - - - - + + + + + - - - - + + + + @@ -123765,8 +124732,8 @@ - - + + @@ -123959,6 +124926,10 @@ + + + + @@ -124028,6 +124999,11 @@ + + + + + @@ -124053,6 +125029,11 @@ + + + + + @@ -124068,20 +125049,20 @@ - - + + - - - - - - + + + + + + @@ -124104,34 +125085,34 @@ - - - - + + + + - - - - + + + + - - - - - - + + + + + + - - - - - - - - + + + + + + + + @@ -124143,6 +125124,10 @@ + + + + @@ -124156,6 +125141,10 @@ + + + + @@ -124229,7 +125218,7 @@ - + @@ -124418,29 +125407,29 @@ - - + + - - - + + + - - - - + + + + - - - - + + + + - - + + @@ -124478,7 +125467,7 @@ - + @@ -124493,6 +125482,16 @@ + + + + + + + + + + @@ -124904,9 +125903,9 @@ - - - + + + @@ -125515,10 +126514,27 @@ - - - - + + + + + + + + + + + + + + + + + + + + + @@ -126568,6 +127584,11 @@ + + + + + @@ -126660,13 +127681,14 @@ + - - - + + + - - + + @@ -127218,36 +128240,36 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + @@ -127266,11 +128288,11 @@ - - - - - + + + + + @@ -127352,8 +128374,8 @@ - - + + @@ -127969,6 +128991,10 @@ + + + + @@ -128004,10 +129030,25 @@ + + + + + + + + + + + + + + + @@ -128029,6 +129070,12 @@ + + + + + + @@ -128048,6 +129095,12 @@ + + + + + + @@ -128106,10 +129159,22 @@ + + + + + + + + + + + + @@ -128120,6 +129185,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -128646,16 +129747,16 @@ - - - - + + + + - - - - + + + + @@ -128686,6 +129787,10 @@ + + + + @@ -128702,23 +129807,23 @@ - - - - + + + + - - - - + + + + - - - - - + + + + + @@ -128955,8 +130060,8 @@ - - + + @@ -129160,7 +130265,6 @@ - diff --git a/android/abi_gki_aarch64_db845c b/android/abi_gki_aarch64_db845c index 69be1905a229..ec944e48a1b9 100644 --- a/android/abi_gki_aarch64_db845c +++ b/android/abi_gki_aarch64_db845c @@ -54,7 +54,6 @@ cpumask_next cpu_number __cpu_online_mask - crc32_le debugfs_create_dir debugfs_create_file debugfs_create_u32 @@ -185,7 +184,6 @@ free_irq generic_handle_irq get_device - get_random_bytes gic_nonsecure_priorities gpiochip_add_data_with_key gpiochip_add_pin_range @@ -419,7 +417,6 @@ preempt_schedule_notrace prepare_to_wait_event printk - pskb_expand_head put_device __put_task_struct qcom_smem_state_register @@ -505,7 +502,6 @@ simple_read_from_buffer single_open single_release - skb_clone skb_dequeue skb_pull skb_push @@ -553,6 +549,7 @@ strlen strncmp strncpy + strnlen strpbrk strsep __sw_hweight32 @@ -655,9 +652,11 @@ cfg80211_vendor_cmd_reply cpu_latency_qos_add_request cpu_latency_qos_remove_request + crc32_le device_get_mac_address device_set_wakeup_enable firmware_request_nowarn + get_random_bytes guid_gen idr_for_each ieee80211_alloc_hw_nm @@ -710,11 +709,13 @@ init_uts_ns __kfifo_alloc __kfifo_free + ktime_get_with_offset __local_bh_enable_ip memmove __nla_parse nla_put param_ops_ulong + pskb_expand_head regulatory_hint rfc1042_header skb_copy @@ -751,44 +752,6 @@ devm_clk_bulk_get_optional iommu_map -# required by ax88179_178a.ko - eth_platform_get_mac_address - ethtool_op_get_link - ethtool_op_get_ts_info - eth_validate_addr - generic_mii_ioctl - mii_ethtool_get_link_ksettings - mii_ethtool_gset - mii_ethtool_set_link_ksettings - mii_nway_restart - netdev_err - netdev_info - netdev_warn - netif_carrier_on - usb_deregister - usbnet_disconnect - usbnet_get_endpoints - usbnet_get_msglevel - usbnet_get_stats64 - usbnet_link_change - usbnet_nway_reset - usbnet_open - usbnet_probe - usbnet_read_cmd - usbnet_read_cmd_nopm - usbnet_resume - usbnet_set_msglevel - usbnet_skb_return - usbnet_start_xmit - usbnet_stop - usbnet_suspend - usbnet_tx_timeout - usbnet_update_max_qlen - usbnet_write_cmd - usbnet_write_cmd_async - usbnet_write_cmd_nopm - usb_register_driver - # required by bam_dma.ko dma_async_device_register dma_async_device_unregister @@ -1303,9 +1266,6 @@ usb_put_hcd usb_remove_hcd -# required by pdr_interface.ko - strnlen - # required by phy-qcom-qmp.ko of_clk_get_by_name __of_reset_control_get @@ -1489,6 +1449,7 @@ refcount_dec_and_mutex_lock release_sock sk_alloc + skb_clone skb_copy_bits skb_copy_datagram_iter skb_free_datagram @@ -1577,7 +1538,9 @@ snd_ctl_add snd_ctl_new1 snd_pcm_add_chmap_ctls - snd_pcm_create_iec958_consumer_hw_params + snd_pcm_create_iec958_consumer_default + snd_pcm_fill_iec958_consumer + snd_pcm_fill_iec958_consumer_hw_params snd_pcm_hw_constraint_eld # required by snd-soc-qcom-common.ko @@ -1701,3 +1664,42 @@ # required by wcd934x.ko mfd_add_devices mfd_remove_devices + +# preserved by --additions-only + eth_platform_get_mac_address + ethtool_op_get_link + ethtool_op_get_ts_info + eth_validate_addr + generic_mii_ioctl + mii_ethtool_get_link_ksettings + mii_ethtool_gset + mii_ethtool_set_link_ksettings + mii_nway_restart + netdev_err + netdev_info + netdev_warn + netif_carrier_on + snd_pcm_create_iec958_consumer_hw_params + usb_deregister + usbnet_disconnect + usbnet_get_endpoints + usbnet_get_msglevel + usbnet_get_stats64 + usbnet_link_change + usbnet_nway_reset + usbnet_open + usbnet_probe + usbnet_read_cmd + usbnet_read_cmd_nopm + usbnet_resume + usbnet_set_msglevel + usbnet_skb_return + usbnet_start_xmit + usbnet_stop + usbnet_suspend + usbnet_tx_timeout + usbnet_update_max_qlen + usbnet_write_cmd + usbnet_write_cmd_async + usbnet_write_cmd_nopm + usb_register_driver diff --git a/android/abi_gki_aarch64_exynos b/android/abi_gki_aarch64_exynos new file mode 100644 index 000000000000..b5d9be87a521 --- /dev/null +++ b/android/abi_gki_aarch64_exynos @@ -0,0 +1,779 @@ +[abi_symbol_list] +# commonly used symbols + add_timer + add_timer_on + adjust_managed_page_count + alloc_chrdev_region + alloc_netdev_mqs + __alloc_pages_nodemask + __alloc_percpu + __alloc_skb + alloc_workqueue + __arch_copy_from_user + __arch_copy_to_user + arm64_const_caps_ready + arm64_use_ng_mappings + __arm_smccc_smc + atomic_notifier_call_chain + atomic_notifier_chain_register + atomic_notifier_chain_unregister + bcmp + bitmap_parse + bitmap_parselist + bitmap_print_to_pagebuf + blocking_notifier_call_chain + blocking_notifier_chain_register + blocking_notifier_chain_unregister + bpf_trace_run1 + bpf_trace_run2 + bpf_trace_run3 + bpf_trace_run4 + bpf_trace_run5 + bpf_trace_run6 + bpf_trace_run7 + cancel_delayed_work + cancel_delayed_work_sync + cancel_work_sync + cdev_add + cdev_del + cdev_init + __cfi_slowpath + __check_object_size + __class_create + class_destroy + class_unregister + clk_disable + clk_enable + clk_get + clk_get_rate + __clk_is_enabled + clk_prepare + clk_put + clk_set_parent + clk_set_rate + clk_unprepare + cma_alloc + cma_release + compat_alloc_user_space + complete + complete_all + completion_done + config_ep_by_speed + config_group_init_type_name + console_suspend_enabled + console_unlock + __const_udelay + __cpu_active_mask + cpu_bit_bitmap + cpufreq_cpu_get + cpufreq_cpu_put + cpufreq_quick_get + cpufreq_register_notifier + cpufreq_unregister_notifier + __cpuhp_remove_state + __cpuhp_setup_state + cpu_hwcap_keys + cpu_hwcaps + cpumask_next + cpumask_next_and + cpu_number + __cpu_online_mask + __cpu_possible_mask + cpu_scale + cpu_subsys + crc32_le + crypto_destroy_tfm + crypto_register_alg + crypto_register_scomp + crypto_unregister_alg + crypto_unregister_scomp + _ctype + debugfs_create_bool + debugfs_create_dir + debugfs_create_file + debugfs_create_u32 + debugfs_remove + default_llseek + delayed_work_timer_fn + del_timer + del_timer_sync + destroy_workqueue + dev_driver_string + _dev_emerg + _dev_err + device_create + device_create_bin_file + device_create_file + device_destroy + device_for_each_child + device_initialize + device_init_wakeup + device_property_present + device_property_read_u32_array + device_remove_file + _dev_info + __dev_kfree_skb_any + devm_add_action + devm_clk_get + devm_free_irq + devm_ioremap + devm_ioremap_resource + devm_iounmap + devm_kasprintf + devm_kfree + devm_kmalloc + devm_kmemdup + __devm_of_phy_provider_register + devm_phy_create + devm_phy_get + devm_pinctrl_get + devm_pinctrl_put + devm_platform_ioremap_resource + devm_regulator_get + __devm_request_region + devm_request_threaded_irq + __devm_reset_control_get + _dev_notice + dev_pm_opp_add + dev_pm_opp_find_freq_ceil + dev_pm_opp_get_voltage + dev_pm_opp_put + dev_set_name + _dev_warn + disable_irq + disable_irq_nosync + dma_alloc_attrs + dma_buf_attach + dma_buf_begin_cpu_access + dma_buf_detach + dma_buf_end_cpu_access + dma_buf_export + dma_buf_get + dma_buf_map_attachment + dma_buf_mmap + dma_buf_put + dma_buf_unmap_attachment + dma_buf_vmap + dma_buf_vunmap + dma_fence_add_callback + dma_fence_context_alloc + dma_fence_default_wait + dma_fence_get_status + dma_fence_init + dma_fence_release + dma_fence_remove_callback + dma_fence_signal + dma_free_attrs + dma_heap_buffer_alloc + dma_heap_find + dma_heap_put + dmam_alloc_attrs + dma_map_page_attrs + dma_map_sg_attrs + dma_release_channel + dma_request_chan + dma_set_coherent_mask + dma_set_mask + dma_sync_sg_for_cpu + dma_sync_sg_for_device + dma_sync_single_for_cpu + dma_sync_single_for_device + dma_unmap_page_attrs + dma_unmap_sg_attrs + down + down_interruptible + down_read + down_write + driver_unregister + dump_stack + enable_irq + event_triggers_call + failure_tracking + fd_install + find_last_bit + find_next_bit + find_next_zero_bit + find_vpid + finish_wait + flush_dcache_page + flush_work + flush_workqueue + fput + free_irq + free_netdev + __free_pages + free_pages + free_percpu + freq_qos_update_request + generic_file_llseek + gen_pool_add_owner + gen_pool_alloc_algo_owner + gen_pool_free_owner + get_cpu_device + get_device + __get_free_pages + get_thermal_instance + get_unused_fd_flags + gic_nonsecure_priorities + gpiod_direction_input + gpiod_direction_output_raw + gpiod_get_raw_value + gpiod_set_raw_value + gpiod_to_irq + gpio_free + gpio_request + gpio_request_one + gpio_to_desc + gserial_alloc_line + gserial_connect + gserial_disconnect + handle_level_irq + handle_nested_irq + hex_dump_to_buffer + hrtimer_active + hrtimer_cancel + hrtimer_forward + hrtimer_init + hrtimer_start_range_ns + i2c_add_numbered_adapter + i2c_del_adapter + i2c_del_driver + i2c_new_dummy_device + i2c_register_driver + i2c_smbus_read_byte_data + i2c_smbus_read_i2c_block_data + i2c_smbus_write_byte_data + i2c_smbus_write_i2c_block_data + i2c_transfer + i2c_transfer_buffer_flags + i2c_unregister_device + idr_alloc + idr_remove + __iio_device_register + iio_device_unregister + __init_rwsem + __init_swait_queue_head + init_task + init_timer_key + init_wait_entry + __init_waitqueue_head + input_allocate_device + input_event + input_free_device + input_register_device + input_set_capability + input_unregister_device + iomem_resource + iommu_get_domain_for_dev + iommu_map_sg + iommu_register_device_fault_handler + iommu_unmap + iommu_unregister_device_fault_handler + __ioremap + iounmap + __irq_alloc_descs + irq_get_irq_data + irq_modify_status + irq_of_parse_and_map + irq_set_affinity_hint + irq_set_chip_and_handler_name + irq_set_chip_data + irq_set_irq_wake + irq_to_desc + is_console_locked + is_vmalloc_addr + jiffies + jiffies_to_msecs + jiffies_to_usecs + kasan_flag_enabled + kasprintf + kernel_kobj + __kfifo_alloc + __kfifo_free + __kfifo_in + __kfifo_to_user + kfree + kfree_skb + kimage_voffset + __kmalloc + kmalloc_caches + kmalloc_order_trace + kmem_cache_alloc + kmem_cache_alloc_trace + kmem_cache_create + kmem_cache_destroy + kmem_cache_free + kmemdup + kobject_create_and_add + kobject_init_and_add + kobject_put + kobject_uevent_env + krealloc + kstrdup + kstrndup + kstrtobool + kstrtobool_from_user + kstrtoint + kstrtoint_from_user + kstrtoll + kstrtou8 + kstrtouint + kstrtouint_from_user + kstrtoull + kthread_bind + kthread_create_on_node + kthread_delayed_work_timer_fn + kthread_flush_worker + __kthread_init_worker + kthread_queue_work + kthread_should_stop + kthread_stop + kthread_worker_fn + ktime_get + ktime_get_mono_fast_ns + ktime_get_raw_ts64 + ktime_get_real_ts64 + ktime_get_ts64 + ktime_get_with_offset + kvfree + kvfree_call_rcu + kvmalloc_node + __list_add_valid + __list_del_entry_valid + __log_post_read_mmio + __log_read_mmio + __log_write_mmio + loops_per_jiffy + lzo1x_decompress_safe + memcpy + __memcpy_fromio + __memcpy_toio + memdup_user + memset + __memset_io + memstart_addr + mfd_add_devices + mfd_remove_devices + misc_deregister + misc_register + mod_delayed_work_on + mod_timer + module_layout + module_put + __msecs_to_jiffies + msleep + msleep_interruptible + __mutex_init + mutex_is_locked + mutex_lock + mutex_lock_interruptible + mutex_trylock + mutex_unlock + napi_complete_done + napi_gro_receive + __napi_schedule + napi_schedule_prep + __netdev_alloc_skb + netif_napi_add + netif_receive_skb + netif_tx_wake_queue + nla_put + no_llseek + nonseekable_open + noop_llseek + nr_cpu_ids + ns_to_kernel_old_timeval + ns_to_timespec64 + __num_online_cpus + of_address_to_resource + of_alias_get_id + of_count_phandle_with_args + of_device_get_match_data + of_device_is_available + of_device_is_compatible + of_find_compatible_node + of_find_device_by_node + of_find_matching_node_and_match + of_find_node_by_name + of_find_node_opts_by_path + of_find_property + of_get_child_by_name + of_get_cpu_node + of_get_named_gpio_flags + of_get_next_available_child + of_get_next_child + of_get_property + of_iomap + of_machine_is_compatible + of_match_device + of_match_node + of_n_addr_cells + of_n_size_cells + of_parse_phandle + of_phandle_iterator_init + of_phandle_iterator_next + of_platform_populate + of_property_count_elems_of_size + of_property_match_string + of_property_read_string + of_property_read_string_helper + of_property_read_u32_index + of_property_read_variable_u32_array + of_prop_next_string + of_prop_next_u32 + of_reserved_mem_device_init_by_idx + of_reserved_mem_device_release + of_reserved_mem_lookup + of_root + __page_pinner_put_page + panic + panic_notifier_list + param_array_ops + param_ops_bool + param_ops_charp + param_ops_int + param_ops_string + param_ops_uint + param_ops_ulong + PDE_DATA + __per_cpu_offset + perf_trace_buf_alloc + perf_trace_run_bpf_submit + pfn_valid + phy_power_off + phy_power_on + pinctrl_lookup_state + pinctrl_select_state + pin_user_pages + platform_device_unregister + __platform_driver_register + platform_driver_unregister + platform_get_irq + platform_get_irq_byname + platform_get_resource + platform_get_resource_byname + __pm_relax + pm_relax + __pm_runtime_disable + pm_runtime_enable + pm_runtime_forbid + pm_runtime_force_resume + pm_runtime_force_suspend + __pm_runtime_idle + __pm_runtime_resume + pm_runtime_set_autosuspend_delay + __pm_runtime_set_status + __pm_runtime_suspend + __pm_runtime_use_autosuspend + __pm_stay_awake + pm_stay_awake + pm_wakeup_ws_event + power_supply_changed + power_supply_get_by_name + power_supply_get_drvdata + power_supply_get_property + power_supply_register + power_supply_set_property + power_supply_unregister + preempt_schedule + preempt_schedule_notrace + prepare_to_wait_event + print_hex_dump + printk + proc_create + proc_create_data + proc_mkdir + proc_set_user + put_device + __put_page + __put_task_struct + put_unused_fd + queue_delayed_work_on + queue_work_on + ___ratelimit + raw_notifier_call_chain + raw_notifier_chain_register + _raw_read_lock + _raw_read_unlock + _raw_spin_lock + _raw_spin_lock_bh + _raw_spin_lock_irq + _raw_spin_lock_irqsave + _raw_spin_trylock + _raw_spin_unlock + _raw_spin_unlock_bh + _raw_spin_unlock_irq + _raw_spin_unlock_irqrestore + _raw_write_lock_irqsave + _raw_write_unlock_irqrestore + rb_insert_color + __rcu_read_lock + __rcu_read_unlock + refcount_warn_saturate + regcache_cache_only + __register_chrdev + register_chrdev_region + register_pm_notifier + register_reboot_notifier + register_restart_handler + register_shrinker + register_syscore_ops + regmap_read + regmap_update_bits_base + regmap_write + regulator_disable + regulator_enable + regulator_get + regulator_get_optional + regulator_is_enabled + regulator_put + regulator_set_voltage + release_firmware + __release_region + remap_pfn_range + remove_cpu + remove_proc_entry + request_firmware + __request_region + request_threaded_irq + reset_control_assert + reset_control_deassert + return_address + rtc_class_close + rtc_class_open + rtc_read_time + sched_clock + sched_setscheduler_nocheck + schedule + schedule_timeout + scnprintf + seq_lseek + seq_printf + seq_puts + seq_read + seq_release + set_cpus_allowed_ptr + sg_alloc_table + sg_free_table + sg_init_table + sg_miter_next + sg_miter_start + sg_miter_stop + sg_next + __sg_page_iter_next + __sg_page_iter_start + simple_attr_open + simple_attr_read + simple_attr_release + simple_attr_write + simple_open + simple_read_from_buffer + simple_write_to_buffer + single_open + single_release + skb_copy_expand + skb_dequeue + skb_pull + skb_push + skb_put + skb_queue_head + skb_queue_purge + skb_queue_tail + skb_trim + smp_call_function + smp_call_function_single + snd_pcm_format_width + snd_soc_dapm_get_enum_double + snd_soc_dapm_get_volsw + snd_soc_dapm_ignore_suspend + snd_soc_dapm_info_pin_switch + snd_soc_dapm_put_enum_double + snd_soc_dapm_put_volsw + snd_soc_dapm_sync + snd_soc_get_enum_double + snd_soc_get_volsw + snd_soc_info_enum_double + snd_soc_info_volsw + snd_soc_put_enum_double + snd_soc_put_volsw + snd_soc_register_component + snd_soc_unregister_component + snprintf + sort + sprintf + sscanf + __stack_chk_fail + static_key_slow_dec + static_key_slow_inc + stpcpy + strcasecmp + strcat + strchr + strcmp + strcpy + strlcat + strlcpy + strlen + strncasecmp + strncmp + strncpy + strnlen + strrchr + strscpy + strsep + strstr + __sw_hweight32 + __sw_hweight64 + sync_file_create + sync_file_get_fence + synchronize_rcu + syscon_regmap_lookup_by_phandle + sysfs_add_file_to_group + sysfs_create_bin_file + sysfs_create_file_ns + sysfs_create_group + sysfs_create_groups + sysfs_create_link + sysfs_emit + sysfs_notify + sysfs_remove_file_ns + sysfs_remove_group + sysfs_streq + system_wq + sys_tz + __tasklet_hi_schedule + tasklet_init + tasklet_kill + __tasklet_schedule + thermal_of_cooling_device_register + thermal_zone_get_temp + thermal_zone_get_zone_by_name + time64_to_tm + _totalram_pages + trace_event_buffer_commit + trace_event_buffer_reserve + trace_event_ignore_this_pid + trace_event_raw_init + trace_event_reg + trace_handle_return + __traceiter_android_vh_cpu_idle_enter + __traceiter_android_vh_cpu_idle_exit + __traceiter_device_pm_callback_end + __traceiter_device_pm_callback_start + __traceiter_pelt_cfs_tp + __traceiter_rwmmio_post_read + __traceiter_rwmmio_read + __traceiter_rwmmio_write + __traceiter_suspend_resume + __tracepoint_android_vh_cpu_idle_enter + __tracepoint_android_vh_cpu_idle_exit + __tracepoint_device_pm_callback_end + __tracepoint_device_pm_callback_start + __tracepoint_pelt_cfs_tp + tracepoint_probe_register + __tracepoint_rwmmio_post_read + __tracepoint_rwmmio_read + __tracepoint_rwmmio_write + __tracepoint_suspend_resume + trace_print_array_seq + trace_raw_output_prep + trace_seq_printf + try_module_get + __udelay + unpin_user_page + __unregister_chrdev + unregister_chrdev_region + unregister_pm_notifier + unregister_shrinker + up + up_read + up_write + usb_add_function + usb_copy_descriptors + usb_ep_autoconfig + usb_function_register + usb_function_unregister + usb_hub_find_child + usb_interface_id + usb_put_function_instance + usb_register_notify + usb_string_id + usb_unregister_notify + __usecs_to_jiffies + usleep_range + v4l2_ctrl_handler_free + v4l2_ctrl_handler_init_class + v4l2_ctrl_handler_setup + v4l2_ctrl_new_custom + v4l2_ctrl_new_std + v4l2_ctrl_new_std_menu + v4l2_device_register + v4l2_device_register_subdev + v4l2_device_set_name + v4l2_device_unregister + v4l2_device_unregister_subdev + v4l2_fh_add + v4l2_fh_del + v4l2_fh_exit + v4l2_fh_init + v4l2_i2c_subdev_init + v4l2_m2m_buf_queue + v4l2_m2m_buf_remove + v4l2_m2m_ctx_init + v4l2_m2m_ctx_release + v4l2_m2m_dqbuf + v4l2_m2m_get_curr_priv + v4l2_m2m_get_vq + v4l2_m2m_init + v4l2_m2m_job_finish + v4l2_m2m_mmap + v4l2_m2m_next_buf + v4l2_m2m_poll + v4l2_m2m_qbuf + v4l2_m2m_release + v4l2_m2m_reqbufs + v4l2_m2m_streamoff + v4l2_m2m_streamon + v4l2_subdev_call_wrappers + v4l2_subdev_init + v4l_bound_align_image + vabits_actual + vb2_buffer_done + vb2_dma_sg_memops + vb2_dqbuf + vb2_mmap + vb2_plane_cookie + vb2_plane_vaddr + vb2_poll + vb2_qbuf + vb2_querybuf + vb2_queue_init + vb2_queue_release + vb2_reqbufs + vb2_streamoff + vb2_streamon + vfree + video_devdata + video_device_alloc + video_device_release + video_ioctl2 + __video_register_device + video_unregister_device + vmalloc + vmalloc_to_pfn + vmap + vscnprintf + vsnprintf + vunmap + vzalloc + wait_for_completion + wait_for_completion_interruptible + wait_for_completion_interruptible_timeout + wait_for_completion_timeout + __wake_up + wake_up_process + wakeup_source_add + wakeup_source_register + wakeup_source_remove + wakeup_source_unregister + __warn_printk diff --git a/android/abi_gki_aarch64_generic b/android/abi_gki_aarch64_generic index caf27681f820..098cb2bdd633 100644 --- a/android/abi_gki_aarch64_generic +++ b/android/abi_gki_aarch64_generic @@ -189,6 +189,7 @@ cfg80211_vendor_cmd_reply __cfi_slowpath __check_object_size + check_preempt_curr __class_create class_destroy class_interface_unregister @@ -629,6 +630,7 @@ drm_add_modes_noedid drm_atomic_add_affected_connectors drm_atomic_add_affected_planes + drm_atomic_bridge_chain_disable drm_atomic_commit drm_atomic_get_connector_state drm_atomic_get_crtc_state @@ -754,6 +756,7 @@ drm_mode_object_find drm_mode_object_get drm_mode_object_put + drm_mode_parse_command_line_for_connector drm_mode_probed_add drm_modeset_acquire_fini drm_modeset_acquire_init @@ -962,6 +965,7 @@ gpiod_get_raw_value_cansleep gpiod_get_value gpiod_get_value_cansleep + gpiod_set_debounce gpiod_set_raw_value gpiod_set_raw_value_cansleep gpiod_set_value @@ -988,8 +992,12 @@ hid_allocate_device hid_debug hid_destroy_device + hid_hw_start hid_input_report + hid_open_report hid_parse_report + __hid_register_driver + hid_unregister_driver hrtimer_active hrtimer_cancel hrtimer_forward @@ -1050,6 +1058,7 @@ __init_swait_queue_head init_task init_timer_key + init_user_ns init_wait_entry __init_waitqueue_head input_alloc_absinfo @@ -1373,6 +1382,7 @@ nr_cpu_ids nr_irqs ns_capable + ns_capable_noaudit nsec_to_clock_t ns_to_timespec64 __num_online_cpus @@ -1793,6 +1803,7 @@ __request_percpu_irq __request_region request_threaded_irq + resched_curr resume_cpus return_address revalidate_disk_size @@ -2212,12 +2223,15 @@ __traceiter_android_rvh_post_init_entity_util_avg __traceiter_android_rvh_preempt_disable __traceiter_android_rvh_preempt_enable + __traceiter_android_rvh_prepare_prio_fork __traceiter_android_rvh_remove_entity_load_avg __traceiter_android_rvh_sched_fork __traceiter_android_rvh_select_task_rq_fair __traceiter_android_rvh_select_task_rq_rt __traceiter_android_rvh_set_iowait + __traceiter_android_rvh_setscheduler __traceiter_android_rvh_set_task_cpu + __traceiter_android_rvh_set_user_nice __traceiter_android_rvh_typec_tcpci_chk_contaminant __traceiter_android_rvh_typec_tcpci_get_vbus __traceiter_android_rvh_uclamp_eff_get @@ -2230,13 +2244,18 @@ __traceiter_android_rvh_update_rt_rq_load_avg __traceiter_android_rvh_util_est_update __traceiter_android_vh_arch_set_freq_scale + __traceiter_android_vh_bh_lru_install + __traceiter_android_vh_binder_restore_priority + __traceiter_android_vh_binder_set_priority __traceiter_android_vh_cma_alloc_adjust __traceiter_android_vh_cma_alloc_finish __traceiter_android_vh_cma_alloc_start __traceiter_android_vh_cpu_idle_enter __traceiter_android_vh_cpu_idle_exit + __traceiter_android_vh_do_madvise_blk_plug __traceiter_android_vh_dump_throttled_rt_tasks __traceiter_android_vh_dup_task_struct + __traceiter_android_vh_early_resume_begin __traceiter_android_vh_enable_thermal_genl_check __traceiter_android_vh_ep_create_wakeup_source __traceiter_android_vh_get_user_pages @@ -2248,12 +2267,19 @@ __traceiter_android_vh_mm_compaction_end __traceiter_android_vh_of_i2c_get_board_info __traceiter_android_vh_pagecache_get_page + __traceiter_android_vh_pagevec_drain __traceiter_android_vh_pin_user_pages + __traceiter_android_vh_rebuild_root_domains_bypass + __traceiter_android_vh_reclaim_pages_plug + __traceiter_android_vh_resume_end __traceiter_android_vh_rmqueue __traceiter_android_vh_sched_setaffinity_early __traceiter_android_vh_scheduler_tick __traceiter_android_vh_setscheduler_uclamp __traceiter_android_vh_show_max_freq + __traceiter_android_vh_shrink_inactive_list_blk_plug + __traceiter_android_vh_shrink_lruvec_blk_plug + __traceiter_android_vh_skip_lru_disable __traceiter_android_vh_snd_compr_use_pause_in_drain __traceiter_android_vh_sound_usb_support_cpu_suspend __traceiter_android_vh_sysrq_crash @@ -2277,6 +2303,9 @@ __traceiter_android_vh_ufs_update_sysfs __traceiter_android_vh_usb_dev_resume __traceiter_android_vh_usb_dev_suspend + __traceiter_android_vh_zap_pte_range_tlb_end + __traceiter_android_vh_zap_pte_range_tlb_force_flush + __traceiter_android_vh_zap_pte_range_tlb_start __traceiter_clock_set_rate __traceiter_cpu_frequency __traceiter_device_pm_callback_end @@ -2284,6 +2313,8 @@ __traceiter_dwc3_readl __traceiter_dwc3_writel __traceiter_gpu_mem_total + __traceiter_irq_handler_entry + __traceiter_irq_handler_exit __traceiter_mm_vmscan_direct_reclaim_begin __traceiter_mm_vmscan_direct_reclaim_end __traceiter_pelt_cfs_tp @@ -2299,6 +2330,8 @@ __traceiter_sched_switch __traceiter_sched_util_est_cfs_tp __traceiter_sched_util_est_se_tp + __traceiter_softirq_entry + __traceiter_softirq_exit __traceiter_suspend_resume trace_output_call __tracepoint_android_rvh_arm64_serror_panic @@ -2326,12 +2359,15 @@ __tracepoint_android_rvh_post_init_entity_util_avg __tracepoint_android_rvh_preempt_disable __tracepoint_android_rvh_preempt_enable + __tracepoint_android_rvh_prepare_prio_fork __tracepoint_android_rvh_remove_entity_load_avg __tracepoint_android_rvh_sched_fork __tracepoint_android_rvh_select_task_rq_fair __tracepoint_android_rvh_select_task_rq_rt __tracepoint_android_rvh_set_iowait + __tracepoint_android_rvh_setscheduler __tracepoint_android_rvh_set_task_cpu + __tracepoint_android_rvh_set_user_nice __tracepoint_android_rvh_typec_tcpci_chk_contaminant __tracepoint_android_rvh_typec_tcpci_get_vbus __tracepoint_android_rvh_uclamp_eff_get @@ -2344,13 +2380,18 @@ __tracepoint_android_rvh_update_rt_rq_load_avg __tracepoint_android_rvh_util_est_update __tracepoint_android_vh_arch_set_freq_scale + __tracepoint_android_vh_bh_lru_install + __tracepoint_android_vh_binder_restore_priority + __tracepoint_android_vh_binder_set_priority __tracepoint_android_vh_cma_alloc_adjust __tracepoint_android_vh_cma_alloc_finish __tracepoint_android_vh_cma_alloc_start __tracepoint_android_vh_cpu_idle_enter __tracepoint_android_vh_cpu_idle_exit + __tracepoint_android_vh_do_madvise_blk_plug __tracepoint_android_vh_dump_throttled_rt_tasks __tracepoint_android_vh_dup_task_struct + __tracepoint_android_vh_early_resume_begin __tracepoint_android_vh_enable_thermal_genl_check __tracepoint_android_vh_ep_create_wakeup_source __tracepoint_android_vh_get_user_pages @@ -2362,12 +2403,19 @@ __tracepoint_android_vh_mm_compaction_end __tracepoint_android_vh_of_i2c_get_board_info __tracepoint_android_vh_pagecache_get_page + __tracepoint_android_vh_pagevec_drain __tracepoint_android_vh_pin_user_pages + __tracepoint_android_vh_rebuild_root_domains_bypass + __tracepoint_android_vh_reclaim_pages_plug + __tracepoint_android_vh_resume_end __tracepoint_android_vh_rmqueue __tracepoint_android_vh_sched_setaffinity_early __tracepoint_android_vh_scheduler_tick __tracepoint_android_vh_setscheduler_uclamp __tracepoint_android_vh_show_max_freq + __tracepoint_android_vh_shrink_inactive_list_blk_plug + __tracepoint_android_vh_shrink_lruvec_blk_plug + __tracepoint_android_vh_skip_lru_disable __tracepoint_android_vh_snd_compr_use_pause_in_drain __tracepoint_android_vh_sound_usb_support_cpu_suspend __tracepoint_android_vh_sysrq_crash @@ -2391,6 +2439,9 @@ __tracepoint_android_vh_ufs_update_sysfs __tracepoint_android_vh_usb_dev_resume __tracepoint_android_vh_usb_dev_suspend + __tracepoint_android_vh_zap_pte_range_tlb_end + __tracepoint_android_vh_zap_pte_range_tlb_force_flush + __tracepoint_android_vh_zap_pte_range_tlb_start __tracepoint_clock_set_rate __tracepoint_cpu_frequency __tracepoint_device_pm_callback_end @@ -2398,6 +2449,8 @@ __tracepoint_dwc3_readl __tracepoint_dwc3_writel __tracepoint_gpu_mem_total + __tracepoint_irq_handler_entry + __tracepoint_irq_handler_exit __tracepoint_mm_vmscan_direct_reclaim_begin __tracepoint_mm_vmscan_direct_reclaim_end __tracepoint_pelt_cfs_tp @@ -2415,6 +2468,8 @@ __tracepoint_sched_switch __tracepoint_sched_util_est_cfs_tp __tracepoint_sched_util_est_se_tp + __tracepoint_softirq_entry + __tracepoint_softirq_exit __tracepoint_suspend_resume trace_print_array_seq trace_print_bitmask_seq diff --git a/android/abi_gki_aarch64_rockchip b/android/abi_gki_aarch64_rockchip new file mode 100644 index 000000000000..07fd8de4b52f --- /dev/null +++ b/android/abi_gki_aarch64_rockchip @@ -0,0 +1,434 @@ +[abi_symbol_list] +# commonly used symbols + atomic_notifier_chain_register + cancel_delayed_work_sync + __cfi_slowpath + clk_bulk_disable + clk_bulk_enable + clk_bulk_prepare + clk_bulk_unprepare + clk_disable + clk_enable + clk_gate_ops + clk_get + __clk_get_name + clk_get_rate + clk_notifier_register + clk_prepare + clk_put + clk_register + clk_set_rate + clk_unprepare + __const_udelay + cpumask_next + __cpu_online_mask + __cpu_possible_mask + delayed_work_timer_fn + _dev_err + devfreq_recommended_opp + device_init_wakeup + _dev_info + devm_clk_bulk_get_all + devm_clk_get + devm_clk_hw_register + devm_clk_register + devm_ioremap_resource + devm_kfree + devm_kmalloc + devm_nvmem_register + devm_platform_ioremap_resource + devm_regulator_get + devm_regulator_get_optional + devm_request_threaded_irq + devm_reset_control_array_get + dev_pm_opp_find_freq_ceil + dev_pm_opp_get_opp_count + dev_pm_opp_get_opp_table + dev_pm_opp_get_voltage + dev_pm_opp_put + dev_pm_opp_put_opp_table + devres_add + devres_alloc_node + devres_free + _dev_warn + down_read + down_write + init_timer_key + iounmap + irq_set_irq_wake + irq_to_desc + kfree + __kmalloc + kmalloc_caches + kmem_cache_alloc_trace + ktime_get + __list_add_valid + __log_post_read_mmio + __log_read_mmio + __log_write_mmio + memcpy + module_layout + __msecs_to_jiffies + msleep + __mutex_init + mutex_lock + mutex_unlock + nr_cpu_ids + nvmem_cell_put + nvmem_cell_read + of_clk_add_provider + of_clk_del_provider + of_clk_get + of_clk_get_by_name + of_clk_get_parent_count + of_clk_src_simple_get + of_count_phandle_with_args + of_device_get_match_data + of_device_is_available + of_find_matching_node_and_match + of_find_property + of_get_next_available_child + of_get_next_child + of_iomap + of_match_device + of_match_node + of_nvmem_cell_get + of_parse_phandle + of_property_count_elems_of_size + of_property_read_string + of_property_read_string_helper + of_property_read_u32_index + of_property_read_variable_u32_array + panic_notifier_list + __platform_driver_probe + __platform_driver_register + platform_driver_unregister + platform_get_irq + platform_get_resource + pm_clk_create + pm_clk_destroy + print_hex_dump + printk + __put_task_struct + queue_delayed_work_on + regmap_read + regmap_update_bits_base + regmap_write + regulator_disable + regulator_enable + regulator_get_voltage + regulator_put + regulator_set_voltage + reset_control_assert + reset_control_deassert + snprintf + sprintf + __stack_chk_fail + strcmp + syscon_node_to_regmap + syscon_regmap_lookup_by_phandle + sysfs_create_file_ns + system_freezable_wq + system_wq + thermal_zone_get_zone_by_name + __traceiter_rwmmio_post_read + __traceiter_rwmmio_read + __traceiter_rwmmio_write + __tracepoint_rwmmio_post_read + __tracepoint_rwmmio_read + __tracepoint_rwmmio_write + __udelay + update_devfreq + up_read + up_write + usleep_range + +# required by clk-link.ko + pm_clk_add + pm_clk_resume + pm_clk_suspend + __pm_runtime_disable + pm_runtime_enable + +# required by clk-pwm.ko + devm_pwm_get + of_clk_add_hw_provider + of_clk_hw_simple_get + pwm_apply_state + +# required by clk-rockchip.ko + clk_divider_ops + clk_divider_ro_ops + clk_fixed_factor_ops + clk_fractional_divider_ops + __clk_get_hw + clk_get_parent + clk_hw_get_flags + clk_hw_get_name + clk_hw_get_parent + clk_hw_get_rate + clk_hw_register_composite + clk_hw_round_rate + __clk_mux_determine_rate + clk_mux_ops + clk_mux_ro_ops + clk_notifier_unregister + clk_register_divider_table + clk_register_fixed_factor + clk_register_gate + clk_register_mux_table + clk_unregister + gcd + kmemdup + match_string + of_clk_src_onecell_get + rational_best_approximation + _raw_spin_lock_irqsave + _raw_spin_unlock_irqrestore + register_restart_handler + reset_controller_register + __warn_printk + +# required by clk-scmi.ko + clk_hw_set_rate_range + devm_of_clk_add_hw_provider + of_clk_hw_onecell_get + scmi_driver_register + scmi_driver_unregister + +# required by industrialio-triggered-buffer.ko + iio_alloc_pollfunc + iio_dealloc_pollfunc + iio_device_attach_buffer + +# required by io-domain.ko + _dev_crit + regulator_register_notifier + regulator_unregister_notifier + +# required by kfifo_buf.ko + iio_buffer_init + iio_buffer_put + __kfifo_alloc + __kfifo_free + __kfifo_in + __kfifo_to_user + mutex_lock_interruptible + +# required by nvmem-rockchip-otp.ko + devm_clk_bulk_get + param_ops_uint + +# required by pm_domains.ko + clk_bulk_put + of_genpd_add_provider_onecell + panic + param_ops_bool + pm_clk_add_clk + pm_genpd_add_subdomain + pm_genpd_init + pm_genpd_remove + strrchr + +# required by rockchip-cpuinfo.ko + nvmem_cell_get + +# required by rockchip-dfi.ko + devm_devfreq_event_add_edev + gic_nonsecure_priorities + +# required by rockchip.ko + __genphy_config_aneg + genphy_resume + genphy_soft_reset + genphy_suspend + mdiobus_read + mdiobus_write + phy_drivers_register + phy_drivers_unregister + +# required by rockchip_bus.ko + cpufreq_register_notifier + cpu_topology + +# required by rockchip_debug.ko + atomic_notifier_chain_unregister + nr_irqs + __per_cpu_offset + +# required by rockchip_dmc.ko + cpufreq_cpu_get + cpufreq_cpu_put + __cpufreq_driver_target + cpufreq_quick_get + cpu_latency_qos_add_request + cpu_latency_qos_update_request + cpu_number + cpus_read_lock + cpus_read_unlock + devfreq_add_governor + devfreq_event_disable_edev + devfreq_event_enable_edev + devfreq_event_get_edev_by_phandle + devfreq_event_get_edev_count + devfreq_event_get_event + devfreq_monitor_resume + devfreq_monitor_start + devfreq_monitor_stop + devfreq_monitor_suspend + devfreq_resume_device + devfreq_suspend_device + devfreq_update_interval + devm_devfreq_add_device + devm_devfreq_register_opp_notifier + _dev_notice + dev_pm_opp_put_regulators + dev_pm_opp_register_set_opp_helper + dev_pm_opp_set_rate + dev_pm_opp_set_regulators + dev_pm_opp_unregister_set_opp_helper + disable_irq + enable_irq + finish_wait + init_wait_entry + __init_waitqueue_head + input_close_device + input_open_device + input_register_handle + input_register_handler + input_unregister_handle + kstrtouint + __memset_io + of_devfreq_cooling_register_power + of_get_child_by_name + platform_get_irq_byname + prepare_to_wait_event + queue_work_on + ___ratelimit + schedule_timeout + __wake_up + +# required by rockchip_dmc_common.ko + down_write_trylock + +# required by rockchip_opp_select.ko + dev_pm_opp_disable + dev_pm_opp_of_add_table + dev_pm_opp_set_prop_name + of_find_node_opts_by_path + of_machine_is_compatible + regulator_get_linear_step + regulator_get_optional + +# required by rockchip_pm_config.ko + of_find_node_by_name + of_get_named_gpio_flags + +# required by rockchip_pvtm.ko + debugfs_create_dir + debugfs_create_file + debugfs_remove + seq_lseek + seq_printf + seq_puts + seq_read + single_open + single_release + +# required by rockchip_pwm_remotectl.ko + arm64_const_caps_ready + cpu_hwcap_keys + devm_input_allocate_device + input_event + input_register_device + input_set_capability + irq_set_affinity_hint + jiffies + jiffies_to_msecs + mod_timer + of_get_property + param_ops_int + __pm_relax + pm_wakeup_ws_event + __tasklet_hi_schedule + tasklet_init + wakeup_source_add + wakeup_source_remove + +# required by rockchip_saradc.ko + complete + devm_add_action + devm_iio_device_alloc + __devm_iio_device_register + __devm_reset_control_get + find_next_bit + iio_get_time_ns + iio_push_to_buffers + iio_trigger_notify_done + __init_swait_queue_head + wait_for_completion_timeout + +# required by rockchip_sip.ko + arm64_use_ng_mappings + __arm_smccc_smc + __ioremap + memstart_addr + pfn_valid + sched_clock + vmap + +# required by rockchip_system_monitor.ko + add_cpu + bitmap_parselist + blocking_notifier_call_chain + blocking_notifier_chain_register + blocking_notifier_chain_unregister + dev_pm_opp_find_freq_floor + dev_pm_qos_add_request + dev_pm_qos_remove_request + dev_pm_qos_update_request + freq_qos_add_request + freq_qos_remove_request + freq_qos_update_request + kobject_create_and_add + kstrdup + kstrtoull + __list_del_entry_valid + memset + mod_delayed_work_on + register_pm_notifier + register_reboot_notifier + regulator_get + remove_cpu + strchr + strsep + strstr + thermal_zone_get_temp + +# required by rockchip_thermal.ko + devm_pinctrl_get + devm_thermal_zone_of_sensor_register + pinctrl_lookup_state + pinctrl_select_state + thermal_zone_device_disable + thermal_zone_device_enable + thermal_zone_device_update + +# required by rtc-hym8563.ko + _bcd2bin + _bin2bcd + device_property_present + devm_rtc_device_register + i2c_del_driver + i2c_register_driver + i2c_smbus_read_byte_data + i2c_smbus_read_i2c_block_data + i2c_smbus_write_byte_data + i2c_smbus_write_i2c_block_data + rtc_valid_tm + +# required by timer-rockchip.ko + clockevents_config_and_register + irq_of_parse_and_map + of_device_is_compatible + request_threaded_irq diff --git a/android/abi_gki_aarch64_type_visibility b/android/abi_gki_aarch64_type_visibility new file mode 100644 index 000000000000..8a98e59ea81b --- /dev/null +++ b/android/abi_gki_aarch64_type_visibility @@ -0,0 +1,5 @@ +[abi_symbol_list] + +# for type visibility + GKI_struct_blk_mq_alloc_data + GKI_struct_cgroup_taskset diff --git a/arch/arm64/boot/dts/google/Makefile b/arch/arm64/boot/dts/google/Makefile index 838e9efb28f0..c0c3f06622a3 100644 --- a/arch/arm64/boot/dts/google/Makefile +++ b/arch/arm64/boot/dts/google/Makefile @@ -48,4 +48,81 @@ gs101-raven-proto1_1.dtbo-base := gs101-b0.dtb gs101-dpm-user.dtbo-base := gs101-b0.dtb + +dtb-$(CONFIG_SOC_GS201) += \ + gs201-a0.dtb \ + gs201-b0.dtb \ + +soc-dtbo-$(CONFIG_SOC_GS201) += \ + gs201-dpm-eng.dtbo \ + gs201-dpm-user.dtbo \ + gs201-dpm-userdebug.dtbo \ + +DTC_FLAGS_gs201-dpm-eng += -a 4096 +DTC_FLAGS_gs201-dpm-user += -a 4096 +DTC_FLAGS_gs201-dpm-userdebug += -a 4096 + +dtbo-$(CONFIG_BOARD_CLOUDRIPPER) += \ + gs201-cloudripper-dev.dtbo \ + gs201-ravenclaw-dev1_0.dtbo \ + gs201-ravenclaw-dev1_1.dtbo \ + gs201-cheetah-proto1.dtbo \ + gs201-cheetah-proto1_1.dtbo \ + gs201-cheetah-proto1_1-wingboard.dtbo \ + gs201-cheetah-evt1.dtbo \ + gs201-cheetah-evt1-wingboard.dtbo \ + gs201-cheetah-evt1-nfc.dtbo \ + gs201-cheetah-evt1_1.dtbo \ + gs201-cheetah-evt1_1-wingboard.dtbo \ + gs201-cheetah-dvt1.dtbo \ + gs201-cheetah-pvt1.dtbo \ + gs201-cheetah-mp.dtbo \ + gs201-panther-proto1.dtbo \ + gs201-panther-proto1_1.dtbo \ + gs201-panther-proto1_1-wingboard.dtbo \ + gs201-panther-evt1.dtbo \ + gs201-panther-evt1-wingboard.dtbo \ + gs201-panther-evt1_1.dtbo \ + gs201-panther-evt1_1-wingboard.dtbo \ + gs201-panther-dvt1.dtbo \ + gs201-panther-pvt1.dtbo \ + gs201-panther-mp.dtbo + +dtbo-$(CONFIG_BOARD_GS201_EMULATOR) += \ + gs201-emulator.dtbo + +dtbo-$(CONFIG_BOARD_GS201_HYBRID) += \ + gs201-hybrid.dtbo + +gs201-cloudripper-dev.dtbo-base := gs201-a0.dtb +gs201-ravenclaw-dev1_0.dtbo-base := gs201-a0.dtb +gs201-ravenclaw-dev1_1.dtbo-base := gs201-a0.dtb +gs201-cheetah-proto1.dtbo-base := gs201-a0.dtb +gs201-cheetah-proto1_1.dtbo-base := gs201-a0.dtb +gs201-cheetah-proto1_1-wingboard.dtbo-base := gs201-a0.dtb +gs201-cheetah-evt1.dtbo-base := gs201-a0.dtb +gs201-cheetah-evt1-wingboard.dtbo-base := gs201-a0.dtb +gs201-cheetah-evt1-nfc.dtbo-base := gs201-a0.dtb +gs201-cheetah-evt1_1.dtbo-base := gs201-a0.dtb +gs201-cheetah-evt1_1-wingboard.dtbo-base := gs201-a0.dtb +gs201-cheetah-dvt1.dtbo-base := gs201-a0.dtb +gs201-cheetah-pvt1.dtbo-base := gs201-a0.dtb +gs201-cheetah-mp.dtbo-base := gs201-a0.dtb +gs201-panther-proto1.dtbo-base := gs201-a0.dtb +gs201-panther-proto1_1.dtbo-base := gs201-a0.dtb +gs201-panther-proto1_1-wingboard.dtbo-base := gs201-a0.dtb +gs201-panther-evt1.dtbo-base := gs201-a0.dtb +gs201-panther-evt1-wingboard.dtbo-base := gs201-a0.dtb +gs201-panther-evt1_1.dtbo-base := gs201-a0.dtb +gs201-panther-evt1_1-wingboard.dtbo-base := gs201-a0.dtb +gs201-panther-dvt1.dtbo-base := gs201-a0.dtb +gs201-panther-pvt1.dtbo-base := gs201-a0.dtb +gs201-panther-mp.dtbo-base := gs201-a0.dtb +gs201-emulator.dtbo-base := gs201-a0.dtb +gs201-hybrid.dtbo-base := gs201-a0.dtb + +gs201-dpm-eng.dtbo-base := gs201-a0.dtb +gs201-dpm-user.dtbo-base := gs201-a0.dtb +gs201-dpm-userdebug.dtbo-base := gs201-a0.dtb + MKDTIMG_FLAGS += --page_size=4096 --id=/:board_id --rev=/:board_rev diff --git a/arch/arm64/boot/dts/google/gs101-audio.dtsi b/arch/arm64/boot/dts/google/gs101-audio.dtsi index 1760c572b838..cdc588b86a9b 100644 --- a/arch/arm64/boot/dts/google/gs101-audio.dtsi +++ b/arch/arm64/boot/dts/google/gs101-audio.dtsi @@ -543,6 +543,21 @@ }; }; + dai_fe_cap_inj_rx: fe_capture_inject_rx { + dai-name = "audio_capture_inject"; + stream-name = "audio_capture_inject"; + id = ; + playback; + cpu { + sound-dai = <&aud_aoc_path IDX_CAP_INJ_RX>; + }; + platform { + rx1 { + of_drv = <&aoc_incall_ep>; + }; + }; + }; + dai_be_i2s0_rx: be_i2s0_rx { dai-name = "I2S_0_RX Playback"; stream-name = "I2S_0_RX Playback"; diff --git a/arch/arm64/boot/dts/google/gs101-bts.dtsi b/arch/arm64/boot/dts/google/gs101-bts.dtsi index 1ceb5c747de4..0691f031f4a8 100644 --- a/arch/arm64/boot/dts/google/gs101-bts.dtsi +++ b/arch/arm64/boot/dts/google/gs101-bts.dtsi @@ -10,7 +10,7 @@ * */ -#include +#include / { exynos-bts { diff --git a/arch/arm64/boot/dts/google/gs101-common-bcl.dtsi b/arch/arm64/boot/dts/google/gs101-common-bcl.dtsi index 375f3ff54ae6..1224aff6d292 100644 --- a/arch/arm64/boot/dts/google/gs101-common-bcl.dtsi +++ b/arch/arm64/boot/dts/google/gs101-common-bcl.dtsi @@ -43,7 +43,7 @@ zone_name = "BATT_SOC_MOD"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 0>; + thermal-sensors = <&google_mitigation 9>; trips { soc_trip:soc-trip { @@ -58,7 +58,7 @@ zone_name = "VDROOP1"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 1>; + thermal-sensors = <&google_mitigation 10>; trips { vdroop1: vdroop1{ temperature = <1000>; @@ -72,7 +72,7 @@ zone_name = "VDROOP2"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 2>; + thermal-sensors = <&google_mitigation 11>; trips { vdroop2: vdroop2{ temperature = <1200>; @@ -86,7 +86,7 @@ zone_name = "BATOILO"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 3>; + thermal-sensors = <&google_mitigation 12>; trips { batoilo: batoilo{ temperature = <5000>; @@ -100,7 +100,7 @@ zone_name = "PMIC_120C"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 4>; + thermal-sensors = <&google_mitigation 13>; trips { pmic_120c: pmic-120c { temperature = <1200>; @@ -114,7 +114,7 @@ zone_name = "PMIC_140C"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 5>; + thermal-sensors = <&google_mitigation 14>; trips { pmic_140c: pmic-140c { temperature = <1400>; @@ -128,7 +128,7 @@ zone_name = "PMIC_OVERHEAT"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 6>; + thermal-sensors = <&google_mitigation 15>; trips { pmic_overheat: pmic-overheat{ temperature = <2000>; @@ -149,7 +149,7 @@ zone_name = "SMPL_GM"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 0>; + thermal-sensors = <&google_mitigation 0>; trips { smpl:smpl_0 { @@ -163,7 +163,7 @@ zone_name = "OCP_CPU1"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 1>; + thermal-sensors = <&google_mitigation 1>; trips { ocp_cpu1:ocp-cpu1 { @@ -177,7 +177,7 @@ zone_name = "OCP_CPU2"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 2>; + thermal-sensors = <&google_mitigation 2>; trips { ocp_cpu2:ocp-cpu2 { @@ -191,7 +191,7 @@ zone_name = "SOFT_OCP_CPU1"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 3>; + thermal-sensors = <&google_mitigation 3>; trips { soft_ocp_cpu1:soft-ocp-cpu1 { @@ -205,7 +205,7 @@ zone_name = "SOFT_OCP_CPU2"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 4>; + thermal-sensors = <&google_mitigation 4>; trips { soft_ocp_cpu2:soft-ocp-cpu2 { @@ -219,7 +219,7 @@ zone_name = "OCP_TPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 5>; + thermal-sensors = <&google_mitigation 5>; trips { ocp_tpu:ocp-tpu{ @@ -233,7 +233,7 @@ zone_name = "SOFT_OCP_TPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 6>; + thermal-sensors = <&google_mitigation 6>; trips { soft_ocp_tpu:soft-ocp-tpu { @@ -247,7 +247,7 @@ zone_name = "OCP_GPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg11mfd 0>; + thermal-sensors = <&google_mitigation 7>; trips { ocp_gpu:ocp-gpu{ @@ -261,7 +261,7 @@ zone_name = "SOFT_OCP_GPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg11mfd 1>; + thermal-sensors = <&google_mitigation 8>; trips { soft_ocp_gpu:soft-ocp-gpu { diff --git a/arch/arm64/boot/dts/google/gs101-common-gps.dtsi b/arch/arm64/boot/dts/google/gs101-common-gps.dtsi index 33b185c33db3..ea83e76ff78c 100644 --- a/arch/arm64/boot/dts/google/gs101-common-gps.dtsi +++ b/arch/arm64/boot/dts/google/gs101-common-gps.dtsi @@ -17,6 +17,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi5_bus &spi5_cs_func>; + swap-mode = <1>; bcm4775@0 { compatible = "ssp,bcm4775"; @@ -54,4 +55,4 @@ samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; }; -}; \ No newline at end of file +}; diff --git a/arch/arm64/boot/dts/google/gs101-common.dtsi b/arch/arm64/boot/dts/google/gs101-common.dtsi index 3a6e065cbbe0..e086e23bd7a2 100644 --- a/arch/arm64/boot/dts/google/gs101-common.dtsi +++ b/arch/arm64/boot/dts/google/gs101-common.dtsi @@ -375,3 +375,9 @@ sensor_3v3-supply = <&s_ldo6_reg>; sensor_power_list = "sensor_1v8", "sensor_3v3"; }; + +&aoc { + sensor_1v8-supply = <&s_ldo7_reg>; + sensor_3v3-supply = <&s_ldo6_reg>; + sensor_power_list = "sensor_1v8", "sensor_3v3"; +}; diff --git a/arch/arm64/boot/dts/google/gs101-cp-s5200-sit.dtsi b/arch/arm64/boot/dts/google/gs101-cp-s5200-sit.dtsi index ba2d54a67355..cc077cf52173 100644 --- a/arch/arm64/boot/dts/google/gs101-cp-s5200-sit.dtsi +++ b/arch/arm64/boot/dts/google/gs101-cp-s5200-sit.dtsi @@ -71,15 +71,7 @@ legacy_raw_buffer_offset = <0x3000>; legacy_raw_txq_size = <0x1FD000>; legacy_raw_rxq_size = <0x200000>; - - /* - * Legacy Priority Queue - * (available only if CONFIG_MODEM_IF_LEGACY_QOS used) - */ - legacy_raw_qos_head_tail_offset = <0x30>; - legacy_raw_qos_buffer_offset = <0x400000>; - legacy_raw_qos_txq_size = <0x100000>; - legacy_raw_qos_rxq_size = <0x100000>; + legacy_raw_rx_buffer_cached = <0>; offset_srinfo_offset = <0x64>; offset_capability_offset = <0x70>; @@ -140,170 +132,196 @@ sbi_ap2cp_kerneltime_usec_pos = <0>; /* Packet processor */ - pktproc_support = <1>; - pktproc_version = <2>; - - pktproc_cp_base = <0x20000000>; - pktproc_info_rgn_offset = <0x00000000>; - pktproc_info_rgn_size = <0x00000100>; - pktproc_desc_rgn_offset = <0x00000100>; - pktproc_desc_rgn_size = <0x000FFF00>; - pktproc_buff_rgn_offset = <0x00100000>; + pktproc_use_36bit_addr = <0>; + pktproc_cp_base = <0x0 0x20000000>; + + pktproc_dl_support = <1>; + pktproc_dl_version = <2>; + + pktproc_dl_info_rgn_offset = <0x00000000>; + pktproc_dl_info_rgn_size = <0x00001000>; + pktproc_dl_desc_rgn_offset = <0x00001000>; + pktproc_dl_desc_rgn_size = <0x000FF000>; + pktproc_dl_buff_rgn_offset = <0x00100000>; + pktproc_dl_buff_rgn_size = <0x01B00000>; /* Size of data region is defined * by reserved mem size */ - pktproc_info_desc_rgn_cached = <1>; - pktproc_buff_rgn_cached = <1>; + pktproc_dl_info_rgn_cached = <1>; + pktproc_dl_desc_rgn_cached = <1>; + pktproc_dl_buff_rgn_cached = <1>; /* 0:ringbuf mode, 1:sktbuf mode */ - pktproc_desc_mode = <1>; - pktproc_num_queue = <1>; - pktproc_use_exclusive_irq = <0>; - pktproc_exclusive_irq_idx = ; - pktproc_use_buff_mng = <0>; - pktproc_desc_num_ratio_percent = <100>; - pktproc_use_napi = <1>; + pktproc_dl_desc_mode = <1>; + pktproc_dl_num_queue = <1>; + pktproc_dl_use_exclusive_irq = <0>; /* H/W IO cache coherency */ - pktproc_use_hw_iocc = <1>; - pktproc_max_packet_size = <2048>; - pktproc_use_dedicated_baaw = <1>; - pktproc_use_36bit_data_addr = <0>; + pktproc_dl_use_hw_iocc = <1>; + pktproc_dl_max_packet_size = <2048>; + pktproc_dl_use_dedicated_baaw = <0>; /* Packet processor for UL */ - pktproc_support_ul = <1>; - pktproc_ul_cp_base = <0x26000000>; - pktproc_ul_info_rgn_offset = <0x00000000>; - pktproc_ul_info_rgn_size = <0x00000100>; - pktproc_ul_desc_rgn_offset = <0x00000100>; - pktproc_ul_desc_rgn_size = <0x000FFF00>; - pktproc_ul_buff_rgn_offset = <0x00100000>; + pktproc_ul_support = <1>; + pktproc_ul_info_rgn_offset = <0x06000000>; + pktproc_ul_info_rgn_size = <0x00001000>; + pktproc_ul_desc_rgn_offset = <0x06001000>; + pktproc_ul_desc_rgn_size = <0x00020000>; + pktproc_ul_buff_rgn_offset = <0x06021000>; + pktproc_ul_buff_rgn_size = <0x003DF000>; pktproc_ul_padding_required = <1>; /* for s5123 EVT1 only */ pktproc_ul_num_queue = <2>; pktproc_ul_max_packet_size = <2048>; - pktproc_ul_info_desc_rgn_cached = <1>; + pktproc_ul_info_rgn_cached = <1>; + pktproc_ul_desc_rgn_cached = <1>; pktproc_ul_buff_rgn_cached = <1>; pktproc_ul_use_hw_iocc = <1>; /* H/W IO cache coherency */ /* TPMON: CP throughput monitor */ cpif_tpmon { - tpmon_trigger_mbps = <30>; - tpmon_trigger_msec_min = <100>; - tpmon_trigger_msec_max = <500>; + trigger_msec_min = <500>; + trigger_msec_max = <1500>; - tpmon_monitor_interval_msec = <100>; - tpmon_monitor_hold_msec = <3000>; - tpmon_monitor_stop_mbps = <15>; + monitor_interval_msec = <1000>; + monitor_hold_msec = <3000>; + monitor_stop_mbps = <15>; - tpmon_boost_hold_msec = <6000>; - tpmon_unboost_tp_percent = <40>; + boost_hold_msec = <6000>; - tpmon_irq_affinity_0 { - tpmon,enable = <0>; - tpmon,name = "IRQ_0"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = ; - tpmon,threshold = <500>; /* Mbps */ - tpmon,values = <0 5>; - }; - tpmon_irq_affinity_dit_pktproc_q { - tpmon,enable = <1>; - tpmon,name = "IRQ_DIT_PKTPROC_Q"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - /* PktProc rear~fore usage */ - tpmon,threshold = <6000>; - tpmon,values = <2 5>; - tpmon,urgent = <1>; - }; - tpmon_irq_affinity_dit_q { - tpmon,enable = <1>; - tpmon,name = "IRQ_DIT_Q"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <7000>; /* DIT src queue */ - tpmon,values = <2 5>; - tpmon,urgent = <1>; - }; - tpmon_irq_affinity_dit { - tpmon,enable = <1>; - tpmon,name = "IRQ_DIT"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <250>; /* Mbps */ - tpmon,values = <2 5>; - }; - tpmon_rps_q { - tpmon,enable = <0>; - tpmon,name = "RPS_Q"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - /* Netdev backlog queue */ - tpmon,threshold = <3000>; - tpmon,values = <0x03 0xC0>; - }; - tpmon_rps_tp { - tpmon,enable = <1>; - tpmon,name = "RPS_TP"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <250 1600>; /* Mbps */ - tpmon,values = <0x03 0x30 0xC0>; + tpmon_rps { + boost_name = "RPS"; + target = ; + extra_idx = <0>; + level = <0x03 0x30 0xC0>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <250 1600>; + unboost_threshold_mbps = <100 600>; + }; }; + tpmon_gro_flush_time { - tpmon,enable = <1>; - tpmon,name = "GRO"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <200>; /* Mbps */ - tpmon,values = <100000 2000000>; + boost_name = "GRO"; + target = ; + extra_idx = <0>; + level = <250000 2000000>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <100>; + unboost_threshold_mbps = <50>; + }; }; + tpmon_mif { - tpmon,enable = <1>; - tpmon,name = "MIF"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <1100>; /* Mbps */ - tpmon,values = <0 1014000>; - tpmon,check_udp = <1>; + boost_name = "MIF"; + target = ; + extra_idx = <0>; + level = <0 1014000>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <1100>; + unboost_threshold_mbps = <400>; + }; }; + tpmon_cpu_cl0 { - tpmon,enable = <0>; - tpmon,name = "CL0"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <100 300>; /* Mbps */ - tpmon,values = <0 1066000 1274000>; - tpmon,check_udp = <1>; + boost_name = "CL0"; + target = ; + extra_idx = <0>; + level = <0 1066000 1274000>; + + boost0 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <100 300>; + unboost_threshold_mbps = <40 120>; + }; }; + tpmon_cpu_cl1 { - tpmon,enable = <1>; - tpmon,name = "CL1"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <4>; - tpmon,threshold = <2000>; /* Mbps */ - tpmon,values = <0 1663000>; - tpmon,check_udp = <0>; + boost_name = "CL1"; + target = ; + extra_idx = <4>; + level = <0 1663000>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <2000>; + unboost_threshold_mbps = <800>; + }; }; + tpmon_pcie_low_power { - tpmon,enable = <1>; - tpmon,name = "PCIE_LP"; - tpmon,measure = ; - tpmon,target = ; - tpmon,idx = <0>; - tpmon,threshold = <3000>; /* Mbps */ - tpmon,values = <1 0>; + boost_name = "PCIE_LP"; + target = ; + extra_idx = <0>; + level = <1 0>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <3000>; + unboost_threshold_mbps = <1200>; + }; + }; + + tpmon_irq_affinity_0 { + boost_name = "IRQ_0"; + target = ; + extra_idx = <3>; + level = <0x04 0x20>; + + boost0 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <500>; + unboost_threshold_mbps = <200>; + }; + }; + + tpmon_irq_dit { + boost_name = "IRQ_DIT"; + target = ; + extra_idx = <0>; + level = <0x04 0x20>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <250>; + unboost_threshold_mbps = <100>; + }; + + boost1 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <6000>; + unboost_threshold_mbps = <2000>; + }; + + boost2 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <7000>; + unboost_threshold_mbps = <2000>; + }; }; }; @@ -340,7 +358,7 @@ iod,format = ; iod,io_type = ; iod,link_type = ; - iod,attrs = <(0x0)>; + iod,attrs = <(IO_ATTR_STATE_RESET_NOTI)>; }; io_device_4 { iod,name = "umts_loopback"; diff --git a/arch/arm64/boot/dts/google/gs101-display-timing.dtsi b/arch/arm64/boot/dts/google/gs101-display-timing.dtsi index fe97587799a1..cd6844184a59 100644 --- a/arch/arm64/boot/dts/google/gs101-display-timing.dtsi +++ b/arch/arm64/boot/dts/google/gs101-display-timing.dtsi @@ -78,6 +78,22 @@ hs-clk = <969>; esc-clk = <20>; }; + 1840x2208 { + mode-name = "1840x2208"; + pmsk = < + 0x2 0xD0 0x2 0x5555 /* p m s k */ + >; + hs-clk = <1280>; + esc-clk = <20>; + }; + 1080x2092 { + mode-name = "1080x2092"; + pmsk = < + 0x2 0xEE 0x3 0xA155 /* p m s k */ + >; + hs-clk = <730>; + esc-clk = <20>; + }; }; }; diff --git a/arch/arm64/boot/dts/google/gs101-dit.dtsi b/arch/arm64/boot/dts/google/gs101-dit.dtsi index 9d87beaf5428..a2670b61d632 100644 --- a/arch/arm64/boot/dts/google/gs101-dit.dtsi +++ b/arch/arm64/boot/dts/google/gs101-dit.dtsi @@ -28,16 +28,17 @@ dit_sharability_offset = <0x00001108>; dit_sharability_value = <0x00110011>; - /* xx(major).yy(mid).zz(minor).rr(reserved) */ - dit_hw_version = <0x02010000>; dit_hw_capabilities = <(DIT_CAP_MASK_NONE)>; dit_use_tx = <1>; dit_use_rx = <1>; dit_use_clat = <0>; - dit_hal_linked = <1>; - dit_rx_extra_desc_ring_len = <2048>; + dit_use_recycling = <0>; + + dit_hal_support = <1>; + dit_hal_enqueue_rx = <0>; + dit_rx_extra_desc_ring_len = <2048>; dit_irq_affinity = <2>; }; }; diff --git a/arch/arm64/boot/dts/google/gs101-dma-heap.dtsi b/arch/arm64/boot/dts/google/gs101-dma-heap.dtsi index f5fca128ca9d..7cb94b2c160d 100644 --- a/arch/arm64/boot/dts/google/gs101-dma-heap.dtsi +++ b/arch/arm64/boot/dts/google/gs101-dma-heap.dtsi @@ -105,6 +105,15 @@ dma-heap,alignment = <0x10000>; status = "disabled"; }; + + mfc_fw_dma_heap { + compatible = "samsung,dma-heap-carveout"; + memory-region = <&mfc_fw>; + dma-heap,name = "mfc_fw"; + dma-heap,secure; + dma-heap,protection_id = <2>; + dma-heap,alignment = <0x10000>; + }; }; &reserved_memory { @@ -213,4 +222,10 @@ <0x0 0x80000000 0x80000000>; status = "disabled"; }; + + mfc_fw: mfc_fw { + size = <0x210000>; + alloc-ranges = <0x0 0x80000000 0x80000000>; + alignment = <0x0 0x00010000>; + }; }; diff --git a/arch/arm64/boot/dts/google/gs101-drm-dpu.dtsi b/arch/arm64/boot/dts/google/gs101-drm-dpu.dtsi index d36246b564d6..cfd6cdd6ba53 100644 --- a/arch/arm64/boot/dts/google/gs101-drm-dpu.dtsi +++ b/arch/arm64/boot/dts/google/gs101-drm-dpu.dtsi @@ -302,6 +302,9 @@ connector = <0x1 0x2 0x8>; hibernation; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; }; drmdecon1: drmdecon@0x1C301000 { @@ -352,6 +355,9 @@ * DSI0(0x1), DSI1(0x2), VIDI(0x8) */ connector = <0x1 0x2 0x8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; }; drmdecon2: drmdecon@0x1C302000 { @@ -401,6 +407,9 @@ * DSI0(0x1), DSI1(0x2), VIDI(0x8) */ connector = <0x8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; }; disp_vddi: disp-vddi { diff --git a/arch/arm64/boot/dts/google/gs101-gpu.dtsi b/arch/arm64/boot/dts/google/gs101-gpu.dtsi index f39963d9a5cf..f2318ae147f7 100644 --- a/arch/arm64/boot/dts/google/gs101-gpu.dtsi +++ b/arch/arm64/boot/dts/google/gs101-gpu.dtsi @@ -85,6 +85,9 @@ 302000 151000 0 70 1 0 0 0 0 0 >; + /* DVFS step up value */ + gpu_dvfs_step_up_val = <2>; + /* DVFS Level locks */ gpu_dvfs_max_freq = <800000>; gpu_dvfs_min_freq = <250000>; diff --git a/arch/arm64/boot/dts/google/gs101-mfc.dtsi b/arch/arm64/boot/dts/google/gs101-mfc.dtsi index c9896abe1ef9..6304134c6038 100644 --- a/arch/arm64/boot/dts/google/gs101-mfc.dtsi +++ b/arch/arm64/boot/dts/google/gs101-mfc.dtsi @@ -24,9 +24,6 @@ samsung,tzmp; - /* for F/W buffer */ - memory-region = <&mfc_fw_rmem>; - /* MFC version */ /* ip_ver is set in gs101-a0.dts and gs101-b0.dts */ @@ -187,6 +184,9 @@ /* need control for mfc idle clock */ idle_clk_ctrl = <0>; + /* Encoder RGB CSC formula by VUI from F/W */ + enc_rgb_csc_by_fw = <1>; + /* Sub nodes for MFC core */ #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/google/gs101-pcie.dtsi b/arch/arm64/boot/dts/google/gs101-pcie.dtsi index 7fab2c4141c0..83dc3e0d0592 100644 --- a/arch/arm64/boot/dts/google/gs101-pcie.dtsi +++ b/arch/arm64/boot/dts/google/gs101-pcie.dtsi @@ -44,6 +44,7 @@ use-sysmmu = "false"; use-ia = "false"; use-l1ss = "false"; + use-secure-atu = "false"; pmu-offset = <0x3ec0>; max-link-speed = ; status = "disabled"; @@ -86,6 +87,7 @@ use-sysmmu = "false"; use-ia = "false"; use-l1ss = "false"; + use-secure-atu = "false"; pmu-offset = <0x3ec4>; max-link-speed = ; s2mpu = <&s2mpu_hsi2>; diff --git a/arch/arm64/boot/dts/google/gs101-pmic.dtsi b/arch/arm64/boot/dts/google/gs101-pmic.dtsi index 3f571bfc6ba0..13b06b14cd4a 100644 --- a/arch/arm64/boot/dts/google/gs101-pmic.dtsi +++ b/arch/arm64/boot/dts/google/gs101-pmic.dtsi @@ -1199,4 +1199,5 @@ &acpm_mbox_test { main-pmic = <&s2mpg10mfd>; sub-pmic = <&s2mpg11mfd>; + acpm-ipc-channel = <2>; }; diff --git a/arch/arm64/boot/dts/google/gs101-raven-display.dtsi b/arch/arm64/boot/dts/google/gs101-raven-display.dtsi index 5aa50e34251e..12c9d61306aa 100644 --- a/arch/arm64/boot/dts/google/gs101-raven-display.dtsi +++ b/arch/arm64/boot/dts/google/gs101-raven-display.dtsi @@ -35,3 +35,15 @@ regulator-enable-ramp-delay = <125>; }; +&dsim_modes { + dsim-modes { + 1080x2340 { + mode-name = "1080x2340"; + pmsk = < + 0x2 0xDB 0x2 0x1355 /* p m s k */ + >; + hs-clk = <1346>; + esc-clk = <20>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs101-raven-uwb.dtsi b/arch/arm64/boot/dts/google/gs101-raven-uwb.dtsi index c135e1fb7b3f..734467bf7ac4 100644 --- a/arch/arm64/boot/dts/google/gs101-raven-uwb.dtsi +++ b/arch/arm64/boot/dts/google/gs101-raven-uwb.dtsi @@ -32,7 +32,7 @@ &pinctrl_4 { dw3xxx_ap_rst: dw3xxx-ap-rst { samsung,pins = "gpp11-0"; - samsung,pin-function = ; + samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; @@ -54,7 +54,7 @@ pinctrl-0 = <&spi10_cs &dw3xxx_irq &dw3xxx_ap_rst &dw3xxx_sync>; spi-max-frequency = <40000000>; - uwbhal,reset-gpio = <&aoc_gpiochip 0 GPIO_OPEN_DRAIN>; + uwbhal,reset-gpio = <&gpp11 0 GPIO_OPEN_DRAIN>; power_reg_2p5-supply = <&s_ldo4_reg>; power_reg_1p8-supply = <&s_ldo14_reg>; diff --git a/arch/arm64/boot/dts/google/gs101-raviole-bcl.dtsi b/arch/arm64/boot/dts/google/gs101-raviole-bcl.dtsi index 50d4aca3b5cd..12c0b633906b 100644 --- a/arch/arm64/boot/dts/google/gs101-raviole-bcl.dtsi +++ b/arch/arm64/boot/dts/google/gs101-raviole-bcl.dtsi @@ -30,6 +30,7 @@ cpu2_clkdivstep = <0x801>; cpu1_clkdivstep = <0x0>; cpu0_clkdivstep = <0x1>; + odpm_ratio = <3>; gpios = <&gpa5 5 GPIO_ACTIVE_HIGH>, /* VDROOP1 */ <&gpa5 6 GPIO_ACTIVE_HIGH>; /* VDROOP2 */ }; @@ -43,7 +44,7 @@ zone_name = "BATT_SOC_MOD"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 0>; + thermal-sensors = <&google_mitigation 9>; trips { soc_trip:soc-trip { @@ -58,7 +59,7 @@ zone_name = "VDROOP1"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 1>; + thermal-sensors = <&google_mitigation 10>; trips { vdroop1: vdroop1{ temperature = <1000>; @@ -72,7 +73,7 @@ zone_name = "VDROOP2"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 2>; + thermal-sensors = <&google_mitigation 11>; trips { vdroop2: vdroop2{ temperature = <1200>; @@ -86,7 +87,7 @@ zone_name = "BATOILO"; polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 3>; + thermal-sensors = <&google_mitigation 12>; trips { batoilo: batoilo{ temperature = <5000>; @@ -100,7 +101,7 @@ zone_name = "PMIC_120C"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 4>; + thermal-sensors = <&google_mitigation 13>; trips { pmic_120c: pmic-120c { temperature = <1200>; @@ -114,7 +115,7 @@ zone_name = "PMIC_140C"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 5>; + thermal-sensors = <&google_mitigation 14>; trips { pmic_140c: pmic-140c { temperature = <1400>; @@ -128,7 +129,7 @@ zone_name = "PMIC_OVERHEAT"; polling-delay-passive = <1000>; polling-delay = <0>; - thermal-sensors = <&google_mitigation 6>; + thermal-sensors = <&google_mitigation 15>; trips { pmic_overheat: pmic-overheat{ temperature = <2000>; @@ -149,7 +150,7 @@ zone_name = "SMPL_GM"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 0>; + thermal-sensors = <&google_mitigation 0>; trips { smpl:smpl_0 { @@ -163,7 +164,7 @@ zone_name = "OCP_CPU1"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 1>; + thermal-sensors = <&google_mitigation 1>; trips { ocp_cpu1:ocp-cpu1 { @@ -177,7 +178,7 @@ zone_name = "OCP_CPU2"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 2>; + thermal-sensors = <&google_mitigation 2>; trips { ocp_cpu2:ocp-cpu2 { @@ -191,7 +192,7 @@ zone_name = "SOFT_OCP_CPU1"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 3>; + thermal-sensors = <&google_mitigation 3>; trips { soft_ocp_cpu1:soft-ocp-cpu1 { @@ -205,7 +206,7 @@ zone_name = "SOFT_OCP_CPU2"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 4>; + thermal-sensors = <&google_mitigation 4>; trips { soft_ocp_cpu2:soft-ocp-cpu2 { @@ -219,7 +220,7 @@ zone_name = "OCP_TPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 5>; + thermal-sensors = <&google_mitigation 5>; trips { ocp_tpu:ocp-tpu{ @@ -233,7 +234,7 @@ zone_name = "SOFT_OCP_TPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg10mfd 6>; + thermal-sensors = <&google_mitigation 6>; trips { soft_ocp_tpu:soft-ocp-tpu { @@ -247,7 +248,7 @@ zone_name = "OCP_GPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg11mfd 0>; + thermal-sensors = <&google_mitigation 7>; trips { ocp_gpu:ocp-gpu{ @@ -261,7 +262,7 @@ zone_name = "SOFT_OCP_GPU"; polling-delay-passive = <100>; polling-delay = <0>; - thermal-sensors = <&s2mpg11mfd 1>; + thermal-sensors = <&google_mitigation 8>; trips { soft_ocp_gpu:soft-ocp-gpu { diff --git a/arch/arm64/boot/dts/google/gs101-rmem.dtsi b/arch/arm64/boot/dts/google/gs101-rmem.dtsi index fd18be6cd354..c566e39274c3 100644 --- a/arch/arm64/boot/dts/google/gs101-rmem.dtsi +++ b/arch/arm64/boot/dts/google/gs101-rmem.dtsi @@ -141,11 +141,5 @@ compatible = "exynos,seclog"; reg = <0 SECLOG_LOG_BUF_BASE SECLOG_LOG_BUF_TOTAL_SIZE>; }; - - mfc_fw_rmem: mfc_fw_rmem { - compatible = "samsung,exynos-mfc"; - size = <0x200000>; - alignment = <0x0 0x00010000>; - }; }; }; diff --git a/arch/arm64/boot/dts/google/gs101-whitefin2-wcharger.dtsi b/arch/arm64/boot/dts/google/gs101-whitefin2-wcharger.dtsi index 2325c8d285eb..45d0e021dfe4 100644 --- a/arch/arm64/boot/dts/google/gs101-whitefin2-wcharger.dtsi +++ b/arch/arm64/boot/dts/google/gs101-whitefin2-wcharger.dtsi @@ -67,7 +67,6 @@ interrupt-names = "p9382_int"; idt,irq_gpio = <&gpa9 7 GPIO_ACTIVE_LOW>; - idt,gpio_qien = <&gpp27 3 GPIO_ACTIVE_HIGH>; idt,has_wlc_dc = <0>; }; }; diff --git a/arch/arm64/boot/dts/google/gs101.dtsi b/arch/arm64/boot/dts/google/gs101.dtsi index a6b49f2581cc..46665f7c78cd 100644 --- a/arch/arm64/boot/dts/google/gs101.dtsi +++ b/arch/arm64/boot/dts/google/gs101.dtsi @@ -469,6 +469,13 @@ acpm_mbox_test: mbox { compatible = "google,acpm-mbox-test"; + mfd-regulator-list-main = + <0x119 0x11C 0x11F 0x122 + 0x125 0x128 0x12B 0x134 + 0x14C 0x14E 0x151>; + mfd-regulator-list-sub = + <0x113 0x116 0x119 0x11C + 0x11E 0x126 0x129 0x143>; }; acpm { @@ -496,7 +503,7 @@ dump-size = <0x3B000>; /* 236KB */ acpm-ipc-channel = <12>; fvmap_addr = <0x31000>; - panic-action = ; + panic-action = ; }; acpm_stats { @@ -665,6 +672,7 @@ /* but refclk shouldn't be omitted */ phyclk_mux = "none"; phy_refclk = "phy_ref"; + phy_ref_clock = <26000000>; /* * if Main phy has the other phy, diff --git a/arch/arm64/boot/dts/google/gs201-a0.dts b/arch/arm64/boot/dts/google/gs201-a0.dts new file mode 100644 index 000000000000..a5cdf999097f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-a0.dts @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/dts-v1/; +/ { + /* soc revision info */ + soc_id = <0x09855000 0x00000000>; +}; + +#include "gs201.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + pause_enable; + resume_threshold = <110>; + pause_threshold = <115>; + pause_cpus = "6-7"; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <5>; + integral_cutoff = <0>; + sustainable_power = <2000>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "MID"; + id = <1>; + ect_nouse; + pause_enable; + resume_threshold = <110>; + pause_threshold = <115>; + pause_cpus = "4-5"; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_alert1: big-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + big_alert2: big-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_alert1: mid-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + mid_alert2: mid-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_alert1: little-alert1 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + little_alert2: little-alert2 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert1: gpu-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert2: isp-alert2 { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert3: isp-alert3 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert4: isp-alert4 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert5: isp-alert5 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert6: isp-alert6 { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_hot: isp-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert1: tpu-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_switch_on: aur-switch-on { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_control_temp: aur-control-temp { + temperature = <95000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert3: aur-alert3 { + temperature = <98000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_alert4: aur-alert4 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_hardlimit: aur-hardlimit { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_dfs: aur-dfs { + temperature = <115000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_hot: aur-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&aur_control_temp>; + cooling-device = <&gxp_cooling 0 0>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-aoc.dtsi b/arch/arm64/boot/dts/google/gs201-aoc.dtsi new file mode 100644 index 000000000000..267043e3e805 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-aoc.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * AoC device tree source + * + * Copyright 2019 Google,LLC. + */ + +/ { + mbox_aoc: mbox@176a0000 { + compatible = "google,mailbox-whitechapel"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0x18300000 0x1000>; + interrupts = ; + mbox-name = "aoc2ap"; + #mbox-cells = <1>; + + wc-mbox-non-wake-channels = <0x7000>; + }; + + pinctrl@10840000 { + aoc_vsync_pins: aoc-vsync-pins { + /* go/p22-gpio */ + samsung,pins = "gpp3-1", "gpp5-1", "gpp7-1", "gpp9-1"; + samsung,pin-function = ; + }; + }; + + aoc: aoc@19000000 { + compatible = "google,aoc"; + + reg = <0x0 0x19000000 0x01000000>, + <0x0 0x181D0000 0x00001000>, + <0x0 0x1A0B0000 0x00001000>, + <0x0 0x1A060000 0x00005000>; + + reg-names = "blk_aoc", "aoc_req", "aoc_s2mpu", "ssmt_aoc"; + + interrupts = ; + interrupt-names = "watchdog"; + + pinctrl-names = "default"; + pinctrl-0 = <&aoc_vsync_pins>; + + iommus = <&sysmmu_asoc>; + memory-region = <&aoc_reserve>; + samsung,iommu-group = <&iommu_group_aoc>; + + mbox-names = "aoc2ap"; + mboxes = <&mbox_aoc 0 + &mbox_aoc 1 + &mbox_aoc 2 + &mbox_aoc 3 + &mbox_aoc 4 + &mbox_aoc 5 + &mbox_aoc 6 + &mbox_aoc 7 + &mbox_aoc 8 + &mbox_aoc 9 + &mbox_aoc 10 + &mbox_aoc 11 + &mbox_aoc 12 + &mbox_aoc 13 + &mbox_aoc 14 + &mbox_aoc 15 + >; + + acpm-ipc-channel = <13>; + + force-vnom = <0>; + + gsa-device = <&gsa>; + }; + aoc_gpiochip: aoc_gpiochip { + compatible = "google,aoc_uwb_rst"; + gpio-controller; + #gpio-cells = <2>; + ngpio = <1>; + }; + +}; diff --git a/arch/arm64/boot/dts/google/gs201-b0.dts b/arch/arm64/boot/dts/google/gs201-b0.dts new file mode 100644 index 000000000000..251c232fba72 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-b0.dts @@ -0,0 +1,684 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC silicon revision B0 + * + * Copyright 2020-2022 Google LLC. + * + */ + +/dts-v1/; +/ { + /* soc revision info */ + /* The bootloader combines the value 0x09855000 of the product id + * register with the value 0x1 of the major revision register before it + * compares the combined value with the first word of the soc_id + * property. + */ + soc_id = <0x09855001 0x00000000>; +}; + +#include "gs201.dtsi" +#include "gs201-sysmmu_sync.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +&s2mpu_aur_idma { + sysmmu_syncs = <&sysmmu_sync_aur_idma>; +}; +&s2mpu_aur_inst_data { + sysmmu_syncs = <&sysmmu_sync_aur_inst_data>; +}; +&s2mpu_bo { + sysmmu_syncs = <&sysmmu_sync_bo>; +}; +&s2mpu_cpucl0 { + sysmmu_syncs = <&sysmmu_sync_cpucl0>; +}; +&s2mpu_csis0 { + sysmmu_syncs = <&sysmmu_sync_csis0>; +}; +&s2mpu_csis1 { + sysmmu_syncs = <&sysmmu_sync_csis1>; +}; +&s2mpu_dns { + sysmmu_syncs = <&sysmmu_sync_dns>; +}; +&s2mpu_dpu0 { + sysmmu_syncs = <&sysmmu_sync_dpu0>; +}; +&s2mpu_dpu1 { + sysmmu_syncs = <&sysmmu_sync_dpu1>; +}; +&s2mpu_dpu2 { + sysmmu_syncs = <&sysmmu_sync_dpu2>; +}; +&s2mpu_eh { + sysmmu_syncs = <&sysmmu_sync_eh>; +}; +&s2mpu_g2d0 { + sysmmu_syncs = <&sysmmu_sync_g2d0>; +}; +&s2mpu_g2d1 { + sysmmu_syncs = <&sysmmu_sync_g2d1>; +}; +&s2mpu_g2d2 { + sysmmu_syncs = <&sysmmu_sync_g2d2>; +}; +&s2mpu_g3aa { + sysmmu_syncs = <&sysmmu_sync_g3aa>; +}; +&s2mpu_g3d { + sysmmu_syncs = <&sysmmu_sync_g3d0 &sysmmu_sync_g3d1 + &sysmmu_sync_g3d2 &sysmmu_sync_g3d3>; +}; +&s2mpu_gdc0 { + sysmmu_syncs = <&sysmmu_sync_gdc0>; +}; +&s2mpu_gdc1 { + sysmmu_syncs = <&sysmmu_sync_gdc1>; +}; +&s2mpu_gdc2 { + sysmmu_syncs = <&sysmmu_sync_gdc2>; +}; +&s2mpu_gsa { + sysmmu_syncs = <&sysmmu_sync_gsa>; +}; +&s2mpu_hsi0 { + sysmmu_syncs = <&sysmmu_sync_hsi0>; +}; +&s2mpu_hsi1 { + sysmmu_syncs = <&sysmmu_sync_hsi1>; +}; +&s2mpu_hsi2 { + sysmmu_syncs = <&sysmmu_sync_hsi2>; +}; +&s2mpu_ipp { + sysmmu_syncs = <&sysmmu_sync_ipp>; +}; +&s2mpu_mcsc0 { + sysmmu_syncs = <&sysmmu_sync_mcsc0>; +}; +&s2mpu_mcsc1 { + sysmmu_syncs = <&sysmmu_sync_mcsc1>; +}; +&s2mpu_mcsc2 { + sysmmu_syncs = <&sysmmu_sync_mcsc2>; +}; +&s2mpu_mfc0 { + sysmmu_syncs = <&sysmmu_sync_mfc0>; +}; +&s2mpu_mfc1 { + sysmmu_syncs = <&sysmmu_sync_mfc1>; +}; +&s2mpu_misc { + sysmmu_syncs = <&sysmmu_sync_misc>; +}; +&s2mpu_tnr0 { + sysmmu_syncs = <&sysmmu_sync_tnr0>; +}; +&s2mpu_tnr1 { + sysmmu_syncs = <&sysmmu_sync_tnr1>; +}; +&s2mpu_tnr2 { + sysmmu_syncs = <&sysmmu_sync_tnr2>; +}; +&s2mpu_tnr3 { + sysmmu_syncs = <&sysmmu_sync_tnr3>; +}; +&s2mpu_tnr4 { + sysmmu_syncs = <&sysmmu_sync_tnr4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <2>; + integral_cutoff = <10>; + sustainable_power = <2000>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "MID"; + id = <1>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <40>; + k_pu = <40>; + k_i = <0>; + i_max = <0>; + sustainable_power = <350>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <100>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + hardlimit_enable; + hardlimit_clr_threshold = <103>; + hardlimit_threshold = <105>; + hardlimit_cooling_state = ; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_alert1: big-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + big_alert2: big-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_alert1: mid-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + mid_alert2: mid-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_alert1: little-alert1 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + little_alert2: little-alert2 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert1: gpu-alert1 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert2: isp-alert2 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert3: isp-alert3 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert4: isp-alert4 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert5: isp-alert5 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + isp_alert6: isp-alert6 { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_hot: isp-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert1: tpu-alert1 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <106000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_switch_on: aur-switch-on { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_control_temp: aur-control-temp { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert3: aur-alert3 { + temperature = <102000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_alert4: aur-alert4 { + temperature = <104000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_hardlimit: aur-hardlimit { + temperature = <105000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + aur_dfs: aur-dfs { + temperature = <110000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_hot: aur-hot { + temperature = <120000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&aur_control_temp>; + cooling-device = <&gxp_cooling 0 0>; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-b0_v2-ipop.dts b/arch/arm64/boot/dts/google/gs201-b0_v2-ipop.dts new file mode 100644 index 000000000000..9f01987bd34d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-b0_v2-ipop.dts @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC silicon revision B0 + * + * Copyright 2020-2022 Google LLC. + * + */ + +/dts-v1/; +/ { + /* List of SoCs that this device tree is compatible with */ + soc_compatible { + B0_IPOP { + description = "B0,IPOP"; + product_id = <0x09855>; + major = <0x1>; + minor = <0x0>; + pkg_mode = <0x1>; + }; + }; +}; + +#include "gs201.dtsi" + +&mfc { + ip_ver = <0x15060000>; + /* FW base security ctrl */ + security_ctrl = <1>; +}; +&mfc_core0 { + ip_ver = <0x15060000>; +}; + +&bts_smc0 { + reg = <0x0 0x2084F258 0x4>; +}; +&bts_smc1 { + reg = <0x0 0x2094F258 0x4>; +}; +&bts_smc2 { + reg = <0x0 0x20A4F258 0x4>; +}; +&bts_smc3 { + reg = <0x0 0x20B4F258 0x4>; +}; + +/ { + tmuctrl_0: BIG@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "BIG"; + id = <0>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <50>; + i_max = <2>; + integral_cutoff = <10>; + sustainable_power = <2000>; + control_temp_step = <50>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_1: MID@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "MID"; + id = <1>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <1000>; + control_temp_step = <50>; + + tmu_work_affinity = "0-7"; + hotplug_work_affinity = "0-3"; + has-dfs-support; + dfs_throttled_cpus = "4-7"; + }; + + tmuctrl_2: LITTLE@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "LITTLE"; + id = <2>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <40>; + k_pu = <40>; + k_i = <0>; + i_max = <0>; + sustainable_power = <350>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_3: G3D@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "G3D"; + id = <3>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <50>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_4: ISP@100A0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100A0000 0x800>; + interrupts = ; + tmu_name = "ISP"; + id = <4>; + ect_nouse; + #thermal-sensor-cells = <0>; + + tmu_work_affinity = "0-7"; + }; + + tmuctrl_5: TPU@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "TPU"; + id = <5>; + ect_nouse; + #thermal-sensor-cells = <0>; + + use-pi-thermal; + polling_delay_on = <50>; + polling_delay_off = <0>; + k_po = <60>; + k_pu = <60>; + k_i = <20>; + i_max = <5>; + integral_cutoff = <20>; + sustainable_power = <200>; + control_temp_step = <50>; + + tmu_work_affinity = "0-7"; + has-dfs-support; + }; + + tmuctrl_6: AUR@100B0000 { + compatible = "samsung,gs201-tmu-v2"; + reg = <0x0 0x100B0000 0x800>; + interrupts = ; + tmu_name = "AUR"; + id = <6>; + ect_nouse; + #thermal-sensor-cells = <0>; + tmu_work_affinity = "0-7"; + }; + + thermal_zones: thermal-zones { + big_thermal: BIG { + zone_name = "BIG_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_0>; + + trips { + big_cold: big-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_switch_on: big-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_control_temp: big-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + big_alert1: big-alert1 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + big_alert2: big-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_alert3: big-alert3 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + big_dfs: big-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + big_hot: big-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&big_control_temp>; + cooling-device = <&cpufreq_domain2 0 0>; + }; + }; + }; + mid_thermal: MID { + zone_name = "MID_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_1>; + + trips { + mid_cold: mid-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_switch_on: mid-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_control_temp: mid-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + mid_alert1: mid-alert1 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + mid_alert2: mid-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_alert3: mid-alert3 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + mid_dfs: mid-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + mid_hot: mid-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&mid_control_temp>; + cooling-device = <&cpufreq_domain1 0 0>; + }; + }; + }; + little_thermal: LITTLE { + zone_name = "LITTLE_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_2>; + + trips { + little_cold: little-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_switch_on: little-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_control_temp: little-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + little_alert1: little-alert1 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + little_alert2: little-alert2 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert5: little-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + little_alert6: little-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + little_hot: little-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&little_control_temp>; + cooling-device = <&cpufreq_domain0 0 0>; + }; + }; + }; + gpu_thermal: G3D { + zone_name = "G3D_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_3>; + + trips { + gpu_cold: gpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_switch_on: gpu-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_control_temp: gpu-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert0: gpu-alert0 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_alert1: gpu-alert1 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_alert2: gpu-alert2 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + gpu_dfs: gpu-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + gpu_hot: gpu-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&gpu_control_temp>; + cooling-device = <&mali + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + isp_thermal: ISP { + zone_name = "ISP_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_4>; + + trips { + isp_alert0: isp-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + isp_alert1: isp-alert1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert2: isp-alert2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + isp_alert3: isp-alert3 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert4: isp-alert4 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert5: isp-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + isp_alert6: isp-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + isp_hot: isp-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + tpu_thermal: TPU { + zone_name = "TPU_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_5>; + + trips { + tpu_cold: tpu-cold { + temperature = <20000>; + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_switch_on: tpu-switch-on { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_control_temp: tpu-control-temp { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert0: tpu-alert0 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + tpu_alert1: tpu-alert1 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_alert2: tpu-alert2 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + tpu_dfs: tpu-dfs { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + tpu_hot: tpu-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + cooling-maps { + map0 { + trip = <&tpu_control_temp>; + cooling-device = <&tpu_cooling 0 0>; + }; + }; + }; + aur_thermal: AUR { + zone_name = "AUR_THERMAL"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tmuctrl_6>; + + trips { + aur_alert0: aur-alert0 { + temperature = <20000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "active"; + }; + aur_alert1: aur-alert1 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert2: aur-alert2 { + temperature = <90000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + aur_alert3: aur-alert3 { + temperature = <92000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert4: aur-alert4 { + temperature = <94000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert5: aur-alert5 { + temperature = <96000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + aur_alert6: aur-alert6 { + temperature = <100000>; /* millicelsius */ + hysteresis = <5000>; /* millicelsius */ + type = "passive"; + }; + aur_hot: aur-hot { + temperature = <115000>; /* millicelsius */ + hysteresis = <3000>; /* millicelsius */ + type = "hot"; + }; + }; + }; + }; +}; + +&pixel_em_table { + profiles = + "default + cpu0 { + 300000 26 18 + 574000 50 31 + 738000 64 40 + 930000 81 54 + 1098000 96 72 + 1197000 104 82 + 1328000 116 95 + 1401000 122 107 + 1598000 140 139 + 1704000 149 162 + 1803000 158 186 + } + cpu4 { + 400000 129 56 + 553000 179 85 + 696000 226 114 + 799000 259 138 + 910000 295 166 + 1024000 332 203 + 1197000 388 260 + 1328000 431 308 + 1491000 484 384 + 1663000 540 510 + 1836000 596 615 + 1999000 649 757 + 2130000 692 908 + 2253000 732 1086 + 2348000 763 1262 + } + cpu6 { + 500000 179 115 + 851000 305 194 + 984000 353 237 + 1106000 397 283 + 1277000 458 371 + 1426000 512 464 + 1582000 568 556 + 1745000 626 682 + 1826000 656 755 + 2048000 735 960 + 2188000 786 1116 + 2252000 809 1219 + 2401000 862 1495 + 2507000 900 1721 + 2630000 944 2034 + 2704000 971 2247 + 2802000 1006 2598 + 2850000 1024 2774 + } + ", + "cam1 + cpu0 { + 300000 38 12 + 574000 47 18 + 738000 71 22 + 930000 92 40 + 1098000 93 77 + 1197000 103 93 + 1328000 104 112 + 1401000 134 132 + 1598000 141 171 + 1704000 157 205 + 1803000 166 239 + } + cpu4 { + 400000 165 89 + 553000 178 121 + 696000 191 154 + 799000 207 178 + 910000 223 210 + 1024000 240 240 + 1197000 287 289 + 1328000 334 334 + 1491000 381 393 + 1663000 427 466 + 1836000 474 532 + 1999000 521 633 + 2130000 568 727 + 2253000 615 841 + 2348000 662 963 + } + cpu6 { + 500000 193 208 + 851000 274 314 + 984000 289 360 + 1106000 305 403 + 1277000 307 482 + 1426000 340 549 + 1582000 379 606 + 1745000 453 691 + 1826000 477 739 + 2048000 538 877 + 2188000 599 1007 + 2252000 659 1070 + 2401000 720 1266 + 2507000 781 1414 + 2630000 842 1638 + 2704000 902 1809 + 2802000 963 2099 + 2850000 1024 2262 + } + ", + "cam2 + cpu0 { + 300000 38 12 + 574000 47 18 + 738000 61 22 + 930000 77 40 + 1098000 92 77 + 1197000 101 93 + 1328000 114 112 + 1401000 121 132 + 1598000 141 171 + 1704000 153 205 + 1803000 166 239 + } + cpu4 { + 400000 165 89 + 553000 178 121 + 696000 201 154 + 799000 217 178 + 910000 238 210 + 1024000 285 240 + 1197000 327 289 + 1328000 357 334 + 1491000 380 393 + 1663000 419 466 + 1836000 460 532 + 1999000 521 633 + 2130000 568 727 + 2253000 615 841 + 2348000 662 963 + } + cpu6 { + 500000 193 208 + 851000 267 314 + 984000 295 360 + 1106000 320 403 + 1277000 357 482 + 1426000 390 549 + 1582000 419 606 + 1745000 471 691 + 1826000 497 739 + 2048000 568 877 + 2188000 620 1007 + 2252000 650 1070 + 2401000 720 1266 + 2507000 781 1414 + 2630000 842 1638 + 2704000 902 1809 + 2802000 963 2099 + 2850000 1024 2262 + } + ", + "ui + cpu0 { + 300000 60 24 + 574000 114 52 + 738000 147 72 + 930000 185 101 + 1098000 218 132 + 1197000 238 155 + 1328000 264 186 + 1401000 278 204 + 1598000 317 269 + 1704000 338 309 + 1803000 358 358 + } + cpu4 { + 400000 146 85 + 553000 202 131 + 696000 254 184 + 799000 292 227 + 910000 333 278 + 1024000 374 336 + 1197000 437 440 + 1328000 485 537 + 1491000 545 658 + 1663000 608 821 + 1836000 671 1021 + 1999000 730 1247 + 2130000 778 1479 + 2253000 823 1712 + 2348000 858 1925 + } + cpu6 { + 500000 180 165 + 851000 306 340 + 984000 354 422 + 1106000 397 518 + 1277000 459 650 + 1426000 512 786 + 1582000 568 944 + 1745000 627 1157 + 1826000 656 1265 + 2048000 736 1608 + 2188000 786 1863 + 2252000 809 2019 + 2401000 863 2345 + 2507000 901 2634 + 2630000 945 3029 + 2704000 972 3326 + 2802000 1007 3797 + 2850000 1024 4064 + } + "; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-bigo.dtsi b/arch/arm64/boot/dts/google/gs201-bigo.dtsi new file mode 100644 index 000000000000..754174d25d81 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-bigo.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bigocean device tree source + * + * Copyright 2021 Google LLC. + * + */ + +#include +/ { + bigocean: bigocean@1CB00000 { + compatible = "google,bigocean"; + status = "ok"; + reg = <0x0 0x1CB00000 0x550 + 0x0 0x1CA94000 0xa00>; + reg-names = "bo", "ssmt_bo_pid"; + interrupts = ; + bigo-opp-table = <&bigo_opp_table>; + bigo-bw-table = <&bigo_bw_table>; + iommus = <&sysmmu_bo>; + samsung,iommu-group = <&iommu_group_bo>; + pt_id = "bigocean"; + power-domains = <&pd_bo>; + samsung,tzmp; + }; + + bigo_opp_table: bigo_opp_table { + opp-95000000 { + freq-khz = <95000>; + /* 1920x1088@30fps */ + load-pps = <61200>; + }; + opp-222000000 { + freq-khz = <222000>; + /* 1920x1088@60fps */ + load-pps = <122400>; + }; + opp-400000000 { + freq-khz = <400000>; + /* 4096x2160@30fps */ + load-pps = <259200>; + }; + opp-620000000 { + freq-khz = <620000>; + /* 4096x2160@60fps */ + load-pps = <518400>; + }; + }; + + bigo_bw_table: bigo_bw_table { + bw-1080p-30 { + rd-bw = <190000>; + wr-bw = <85000>; + pk-bw = <210000>; + load-pps = <61200>; + }; + bw-1080p-60 { + rd-bw = <340000>; + wr-bw = <165000>; + pk-bw = <410000>; + load-pps = <122400>; + }; + bw-2160p-30 { + rd-bw = <700000>; + wr-bw = <340000>; + pk-bw = <820000>; + load-pps = <259200>; + }; + bw-2160p-60 { + rd-bw = <6000000>; + wr-bw = <2000000>; + pk-bw = <8000000>; + load-pps = <518400>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-bts.dtsi b/arch/arm64/boot/dts/google/gs201-bts.dtsi new file mode 100644 index 000000000000..3ad313c748ef --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-bts.dtsi @@ -0,0 +1,1811 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG EXYNOS SoC BTS device tree source + * + * Copyright (c) 2018 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SAMSUNG EXYNOS SoC BTS device nodes are listed in this file. + * EXYNOS based board files should include this file. + * + */ + +#include + +/ { + exynos-bts { + compatible = "samsung,exynos-bts"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* BUS1 to INT mapping table */ + bus1_int_map = < + /* + * bus1 int + * clk clk + *------------- + */ + 620000 533000 + 533000 465000 + 400000 332000 + 310000 267000 + 267000 200000 + 200000 155000 + 134000 100000 + >; + + list-scen = "default", + "mfc_uhd", + "mfc_uhd_10bit", + "mfc_8k_dec30", + "g3d_performance", + "tpu_performance", + "dp_default", + "camera_default", + "mfc_uhd_enc60"; + + rt-names = "DECON0", + "csi", + "ipp", + "g3aa"; + + /* TREX_D_NOCL0 */ + + bts_corem0{ + #address-cells = <2>; + #size-cells = <1>; + ranges; + reg = <0x0 0x1E4B4000 0x400>; + status = "okay"; + bts-type = ; + }; + bts_corem1{ + reg = <0x0 0x1E4C4000 0x400>; + status = "okay"; + bts-type = ; + }; + bts_corem2{ + reg = <0x0 0x1E4D4000 0x400>; + status = "okay"; + bts-type = ; + }; + bts_corem3{ + reg = <0x0 0x1E4E4000 0x400>; + status = "okay"; + bts-type = ; + }; + + /* SMC */ + bts_smc0: bts_smc0 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = ; + }; + bts_smc1: bts_smc1 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = ; + }; + bts_smc2: bts_smc2 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = ; + }; + bts_smc3: bts_smc3 { + /* reg is set in gs101-a0.dts and gs101-b0.dts */ + status = "okay"; + bts-type = ; + }; + + /* TREX_VC_NUM */ + bts_vc_num_0 { + reg = <0x0 0x1EA81000 0x4>; + status = "okay"; + bts-type = ; + vc-string = "gsa, cssys, aoc, alive"; + }; + bts_vc_num_1 { + reg = <0x0 0x1EA81004 0x4>; + status = "okay"; + bts-type = ; + vc-string = "na, na, hsi1, hs10"; + }; + bts_vc_num_2 { + reg = <0x0 0x1F601000 0x4>; + status = "okay"; + bts-type = ; + vc-string = "dns, csis1, csis0, bo"; + }; + bts_vc_num_3 { + reg = <0x0 0x1F601004 0x4>; + status = "okay"; + bts-type = ; + vc-string = "g2d0, dpu2, dpu1, dpu0"; + }; + bts_vc_num_4 { + reg = <0x0 0x1F601008 0x4>; + status = "okay"; + bts-type = ; + vc-string = "gdc0, g3aa, g2d2, g2d1"; + }; + bts_vc_num_5 { + reg = <0x0 0x1F60100C 0x4>; + status = "okay"; + bts-type = ; + vc-string = "ipp, hsi2, gdc2, gdc1"; + }; + bts_vc_num_6 { + reg = <0x0 0x1F601010 0x4>; + status = "okay"; + bts-type = ; + vc-string = "mfc0, mcsc2, mcsc1, mcsc0"; + }; + bts_vc_num_7 { + reg = <0x0 0x1F601014 0x4>; + status = "okay"; + bts-type = ; + vc-string = "tnr1, tnr0, misc, mfc1"; + }; + bts_vc_num_8 { + reg = <0x0 0x1F601018 0x4>; + status = "okay"; + bts-type = ; + vc-string = "na, tnr4, tnr3, tnr2"; + }; + bts_vc_num_9 { + reg = <0x0 0x20511000 0x4>; + status = "okay"; + bts-type = ; + vc-string = "gpu1, gpu0, aur1, aur0"; + }; + bts_vc_num_10 { + reg = <0x0 0x20511004 0x4>; + status = "okay"; + bts-type = ; + vc-string = "tpu, gpummu, gpu3, gpu2"; + }; + bts_vc_num_11 { + reg = <0x0 0x1E501000 0x4>; + status = "okay"; + bts-type = ; + vc-string = "cpu3, cpu2, cpu1, cpu0"; + }; + bts_vc_num_12 { + reg = <0x0 0x20512000 0x4>; + status = "okay"; + bts-type = ; + vc-string = "pbcg_trex_d_nocl1a"; + }; + + /* TREX_D_NOCL2A */ + bts_nocl2a_0 { + reg = <0x0 0x1F5B2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl2a_1 { + reg = <0x0 0x1F5C2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl2a_2 { + reg = <0x0 0x1F5D2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl2a_3 { + reg = <0x0 0x1F5E2000 0x100>; + status = "okay"; + bts-type = ; + }; + /* TREX_D_NOCL1A */ + bts_nocl1a_0 { + reg = <0x0 0x204C2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl1a_1 { + reg = <0x0 0x204D2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl1a_2 { + reg = <0x0 0x204E2000 0x100>; + status = "okay"; + bts-type = ; + }; + bts_nocl1a_3 { + reg = <0x0 0x204F2000 0x100>; + status = "okay"; + bts-type = ; + }; + /* TREX_D_NOCL1B */ + bts_nocl1b { + reg = <0x0 0x1EA62000 0x100>; + status = "okay"; + bts-type = ; + }; + + /* TREX_D_NOCL2A */ + bts_bo { + reg = <0x0 0x1F400000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_csis0 { + reg = <0x0 0x1F410000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <0>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + ex_qurgent_on = <1>; + }; + }; + bts_csis1 { + reg = <0x0 0x1F420000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <0>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + ex_qurgent_on = <1>; + }; + }; + bts_dns { + reg = <0x0 0x1F430000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0xF>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_dpu0 { + reg = <0x0 0x1F440000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_dpu1 { + reg = <0x0 0x1F450000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + qurgent_th_w = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_dpu2 { + reg = <0x0 0x1F460000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0x20>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <1>; + qurgent_th_r = <0xC>; + qurgent_th_w = <0x6>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x8>; + awqos = <0x8>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + ex_qurgent_on = <0>; + }; + }; + bts_gdc0 { + reg = <0x0 0x1F470000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gdc1 { + reg = <0x0 0x1F480000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gdc2 { + reg = <0x0 0x1F490000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xA>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d0 { + reg = <0x0 0x1F4A0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d1 { + reg = <0x0 0x1F4B0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g2d2 { + reg = <0x0 0x1F4C0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_g3aa { + reg = <0x0 0x1F4D0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <1>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + }; + }; + bts_hsi2 { + reg = <0x0 0x1F4E0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_ipp { + reg = <0x0 0x1F4F0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0xC>; + awqos = <0xC>; + rmo = <0xFFFF>; + wmo = <0x40>; + qurgent_on = <1>; + qurgent_th_r = <0x10>; + qurgent_th_w = <0x10>; + blocking_on = <0>; + }; + }; + bts_mcsc0 { + reg = <0x0 0x1F500000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mcsc1 { + reg = <0x0 0x1F510000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mcsc2 { + reg = <0x0 0x1F520000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x8>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mfc0 { + reg = <0x0 0x1F530000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x40>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x12>; + wmo = <0x12>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_mfc1 { + reg = <0x0 0x1F540000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x14>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x40>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x10>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x12>; + wmo = <0x12>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_misc { + reg = <0x0 0x1F550000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0xF>; + wmo = <0xF>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr0 { + reg = <0x0 0x1F560000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x32>; + wmo = <0x9>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr1 { + reg = <0x0 0x1F570000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x32>; + wmo = <0x9>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr2 { + reg = <0x0 0x1F580000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x1>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr3 { + reg = <0x0 0x1F590000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x10>; + wmo = <0x1>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tnr4 { + reg = <0x0 0x1F5A0000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x6>; + wmo = <0x6>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x18>; + wmo = <0x7>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_NOCL1A */ + bts_aur0 { + reg = <0x0 0x20400000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_aur1 { + reg = <0x0 0x20410000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu0 { + reg = <0x0 0x20430000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu1 { + reg = <0x0 0x20440000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu2 { + reg = <0x0 0x20450000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gpu3 { + reg = <0x0 0x20460000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_10bit { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_8k_dec30 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + g3d_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x20>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + dp_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + camera_default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + mfc_uhd_enc60 { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x14>; + wmo = <0x8>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_tpu { + reg = <0x0 0x20470000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + tpu_performance { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + rmo = <0x40>; + wmo = <0x20>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_NOCL1B */ + bts_alive { + reg = <0x0 0x1EA00000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_aoc { + reg = <0x0 0x1EA10000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + qurgent_th_r = <0xF>; + qurgent_th_w = <0xF>; + blocking_on = <0>; + }; + }; + bts_cssys { + reg = <0x0 0x1EA20000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_gsa { + reg = <0x0 0x1EA30000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_hsi0 { + reg = <0x0 0x1EA40000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_hsi1 { + reg = <0x0 0x1EA50000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <0>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + /* TREX_D_CORE */ + bts_cpu0 { + reg = <0x0 0x1E400000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu1 { + reg = <0x0 0x1E410000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu2 { + reg = <0x0 0x1E420000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + bts_cpu3 { + reg = <0x0 0x1E430000 0x100>; + status = "okay"; + bts-type = ; + default { + stat_on = <1>; + bypass = <0>; + arqos = <0x4>; + awqos = <0x4>; + qurgent_on = <0>; + blocking_on = <0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-audio.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-audio.dtsi new file mode 100644 index 000000000000..be4b561de3af --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-audio.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Cheetah common audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * + * cs35l41_l = top + * cs35l41_r = bottom + */ +#include +#include +#include + +&aoc { + aoc-board-cfg = "C10"; + aoc-board-id = <0x30301>; + aoc-board-rev = <0x10000>; +}; + +&dai_be_tdm0_rx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&dai_be_tdm0_tx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs35l41_l { + comp = <&cs35l41_l>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + + sys@cs35l41_r { + comp = <&cs35l41_r>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + cs35l41_l_irq: cs35l41-l-irq { + samsung,pins = "gpa6-3"; /* XEINT_3 - AMP1_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_irq: cs35l41-r-irq { + samsung,pins = "gpa8-6"; /* XEINT_18 - AMP2_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +/* GPIO_PERIC0 */ +&pinctrl_4 { + cs35l41_clk: cs35l41-clk { + samsung,pins = "gpp14-0"; /* XAPC_USI7_RXD_CLK_SCL - AUDIO_SPI_CLK */ + samsung,pin-drv = ; + }; + + cs35l41_mosi: cs35l41-mosi { + samsung,pins = "gpp14-1"; /* XAPC_USI7_TXD_DO_SDA - AUDIO_SPI_MOSI */ + samsung,pin-drv = ; + }; + + cs35l41_miso: cs35l41-miso { + samsung,pins = "gpp14-2"; /* XAPC_USI7_RTSn_DI - AUDIO_SPI_MISO */ + samsung,pin-pud = ; + }; + + cs35l41_cs1: cs35l41-cs1 { + samsung,pins = "gpp14-3"; /* XAPC_USI7_CTSN_CSN - AUDIO_AMP1_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_l_rst: cs35l41-l-rst { + samsung,pins = "gpp17-1"; /* XAPC_VSYNC8 - AMP1_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + cs35l41_cs2: cs35l41-cs2 { + samsung,pins = "gpp22-1"; /* XAPC_GPIO5 - AUDIO_AMP2_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_rst: cs35l41-r-rst { + samsung,pins = "gpp25-2"; /* XAPC_USI13_RTSn_DI - AMP2_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi7_cs_func { + samsung,pins = "gpp14-3"; + samsung,pin-drv = ; +}; + +&spi_7 { + /* XAPC_USI7 */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus &spi7_cs_func &cs35l41_cs2 + &cs35l41_miso &cs35l41_mosi &cs35l41_clk>; + cs-gpios = <&gpp14 3 GPIO_ACTIVE_HIGH>, <&gpp22 1 GPIO_ACTIVE_HIGH>; + + cs35l41_l: cs35l41@0 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <0>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_l_irq &cs35l41_l_rst>; + + interrupt-parent = <&gpa6>; + interrupts = <3 0 0>; + + reset-gpios = <&gpp17 1 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + cirrus,hibernate-enable; + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio = <&gpp14 3 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; + + + cs35l41_r: cs35l41@1 { + #sound-dai-cells = <1>; + sound-name-prefix = "R"; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <1>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_r_irq &cs35l41_r_rst>; + + interrupt-parent = <&gpa8>; + interrupts = <6 0 0>; + + reset-gpios = <&gpp25 2 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + cirrus,hibernate-enable; + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio =<&gpp22 1 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-battery-data.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-battery-data.dtsi new file mode 100644 index 000000000000..588addeaa24c --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-battery-data.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries + * + * Copyright 2020 Google LLC + * + */ + +maxim,config { + + /* R4_p1_gen.ini, 2021-01-21, b/174787673, generic model */ + maxim,default-a1-0k { + maxim,batt-id-kohm = <0>; + maxim,model-version = <0>; + maxim,fg-model = /bits/ 16 < + 0x9760 0xa510 0xb100 0xb600 0xb7a0 0xb900 0xba70 0xbc70 + 0xbde0 0xbfc0 0xc250 0xc510 0xc990 0xcea0 0xd040 0xd750 + 0x0060 0x0120 0x0200 0x0710 0x0e80 0x0df0 0x1430 0x1bd0 + 0x1520 0x0d70 0x0950 0x08e0 0x0800 0x0780 0x06b0 0x01e0 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x2038 /* RelaxCFG */ + /* 0x0028 */ 0x260E /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5F00 /* FullSOCthr */ + /* 0x0035 */ 0x0994 /* FullCAPRep */ + /* 0x0018 */ 0x0994 /* DesignCap */ + /* 0x0046 */ 0x0c80 /* dPacc */ + /* 0x0045 */ 0x0099 /* dQacc */ + /* 0x0023 */ 0x0994 /* FullCAPNom */ + /* 0x003A */ 0xA561 /* V_empty */ + /* 0x0012 */ 0x1100 /* QResidual00 */ + /* 0x0022 */ 0x0800 /* QResidual10 */ + /* 0x0032 */ 0x0301 /* QResidual20 */ + /* 0x0042 */ 0x0302 /* QResidual30 */ + /* 0x0038 */ 0x0700 /* RCOMP0 */ + /* 0x0039 */ 0x223E /* TempCo */ + /* 0x001E */ 0x0310 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x0000 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0xc623 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; + + /* ATL: 3138_1_102621_BC59_RC2_send.043.model_ATL, 2021-11-18, b/204198596 */ + maxim,cos-a1-1k { + maxim,batt-id-kohm = <1>; + maxim,model-version = <1>; + maxim,force-reset-model-data; + maxim,fg-model = /bits/ 16 < + 0xa4e0 0xb750 0xb8a0 0xba60 0xbc10 0xbdd0 0xbf30 0xc070 + 0xc1e0 0xc4b0 0xc7f0 0xcd80 0xd130 0xd4e0 0xd920 0xdca0 + 0x0120 0x1240 0x0c00 0x12a0 0x1400 0x1700 0x1060 0x0fd0 + 0x07e0 0x07f0 0x07c0 0x06d0 0x06c0 0x06f0 0x0640 0x0640 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x0839 /* RelaxCFG */ + /* 0x0028 */ 0x260e /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5f00 /* FullSOCthr */ + /* 0x0035 */ 0x09C5 /* FullCAPRep */ + /* 0x0018 */ 0x09C5 /* DesignCap */ + /* 0x0046 */ 0x3200 /* dPacc */ + /* 0x0045 */ 0x0271 /* dQacc */ + /* 0x0023 */ 0x09C5 /* FullCAPNom */ + /* 0x003A */ 0xA561 /* V_empty */ + /* 0x0012 */ 0x2080 /* QResidual00 */ + /* 0x0022 */ 0x0e80 /* QResidual10 */ + /* 0x0032 */ 0x0580 /* QResidual20 */ + /* 0x0042 */ 0x0480 /* QResidual30 */ + /* 0x0038 */ 0x0770 /* RCOMP0 */ + /* 0x0039 */ 0x2202 /* TempCo */ + /* 0x001E */ 0x0628 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x1900 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0x0623 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; + + /* LSN: 3139_1_102621_BC59_RC2_send.044.model_LSN, 2021-11-18, b/204198596 */ + maxim,lsn-a1-3k { + maxim,batt-id-kohm = <3>; + maxim,model-version = <1>; + maxim,force-reset-model-data; + maxim,fg-model = /bits/ 16 < + 0xa510 0xb740 0xb830 0xb930 0xbaf0 0xbc20 0xbd10 0xbe50 + 0xbfa0 0xc240 0xc430 0xc6f0 0xcb30 0xd0d0 0xd690 0xdc30 + 0x0130 0x1100 0x0f10 0x0d00 0x1400 0x1970 0x15e0 0x1600 + 0x0dd0 0x07a0 0x07d0 0x07f0 0x06d0 0x06b0 0x06a0 0x06a0 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x0839 /* RelaxCFG */ + /* 0x0028 */ 0x260e /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5f00 /* FullSOCthr */ + /* 0x0035 */ 0x09C5 /* FullCAPRep */ + /* 0x0018 */ 0x09C5 /* DesignCap */ + /* 0x0046 */ 0x3200 /* dPacc */ + /* 0x0045 */ 0x0271 /* dQacc */ + /* 0x0023 */ 0x09C5 /* FullCAPNom */ + /* 0x003A */ 0xA561 /* V_empty */ + /* 0x0012 */ 0x1e00 /* QResidual00 */ + /* 0x0022 */ 0x0f00 /* QResidual10 */ + /* 0x0032 */ 0x0780 /* QResidual20 */ + /* 0x0042 */ 0x0580 /* QResidual30 */ + /* 0x0038 */ 0x0740 /* RCOMP0 */ + /* 0x0039 */ 0x0f02 /* TempCo */ + /* 0x001E */ 0x0628 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x1900 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0x0623 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-battery.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-battery.dtsi new file mode 100644 index 000000000000..16c8a45d7fd7 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-battery.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to raven + * + * Copyright 2021 Google,LLC + * + */ + +&google_battery { + google,chg-battery-capacity = <4926>; +}; + +&max77759_fg { + /delete-property/ maxim,force-batt-id; + + maxim,filtercfg-temp = <100>; + maxim,filtercfg-temp-hysteresis = <30>; + maxim,filtercfg-default = /bits/ 16 <0xc613>; + maxim,filtercfg-adjust = /bits/ 16 <0xc617>; + + maxim,fg-data { + #include "gs201-cheetah-battery-data.dtsi" + }; +}; + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + google_battery: google,battery { + google,ttf-temp-idx= <2>; + google,ttf-adapter = <3000>; + google,ttf-soc-table = <40 47 49 70 82 84 86 88 92 100>; + google,ttf-elap-table = <41 47 54 59 76 84 93 111 152 176>; + google,ttf-tier-table = <0 48 72>; + + google,aacr-disable; + + google,batt-id-1-atl { + google,batt-id = <1>; + google,aacr-ref-cycles = <200 300 400 500 600 700 800>; + google,aacr-ref-fade10 = < 10 23 34 44 54 63 71>; + }; + + google,batt-id-3-lsn { + google,batt-id = <3>; + google,aacr-ref-cycles = <300 400 500 600 700 800>; + google,aacr-ref-fade10 = < 14 26 38 48 57 66>; + }; + }; + + google_bms { + nvmem-names = "6-00500"; + /* pack eeprom is available only with P20+ batteries */ + google,bee-name = "6-00500"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-camera.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-camera.dtsi new file mode 100644 index 000000000000..3d668efd931f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-camera.dtsi @@ -0,0 +1,977 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 camera lwis device tree for cheetah + * + * Copyright 2021 Google LLC. + * + */ + +#include +#include +#include + +&slg51002_ldo1 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&slg51002_ldo2 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&slg51002_ldo3 { + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <2250000>; +}; + +&slg51002_ldo4 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + +&slg51002_ldo5 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&slg51002_ldo6 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; +}; + +&slg51002_ldo7 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; +}; + +&slg51002_ldo8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; +}; + +&s_ldo12_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&pinctrl_4 { + hsi2c1_bus: hsi2c1-bus { + samsung,pin-pud = ; + }; + + hsi2c1_bus_in: hsi2c1-bus-in { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c2_bus: hsi2c2-bus { + samsung,pin-pud = ; + }; + + hsi2c2_bus_in: hsi2c2-bus-in { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c3_bus: hsi2c3-bus { + samsung,pin-pud = ; + }; + + hsi2c3_bus_in: hsi2c3-bus-in { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c4_bus: hsi2c4-bus { + samsung,pin-pud = ; + }; + + hsi2c4_bus_in: hsi2c4-bus-in { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&hsi2c_1 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp2 0 GPIO_ACTIVE_HIGH &gpp2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c1_bus_in>; + pinctrl-1 = <&hsi2c1_bus>; + pinctrl-2 = <&hsi2c1_bus_in>; +}; + +&hsi2c_2 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp4 0 GPIO_ACTIVE_HIGH &gpp4 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <950000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c2_bus_in>; + pinctrl-1 = <&hsi2c2_bus>; + pinctrl-2 = <&hsi2c2_bus_in>; +}; + +&hsi2c_3 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp6 0 GPIO_ACTIVE_HIGH &gpp6 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <950000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c3_bus_in>; + pinctrl-1 = <&hsi2c3_bus>; + pinctrl-2 = <&hsi2c3_bus_in>; +}; + +&hsi2c_4 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp8 0 GPIO_ACTIVE_HIGH &gpp8 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c4_bus_in>; + pinctrl-1 = <&hsi2c4_bus>; + pinctrl-2 = <&hsi2c4_bus_in>; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp24 0 GPIO_ACTIVE_HIGH &gpp24 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <400000>; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-1 = <&hsi2c15_bus>; + pinctrl-2 = <&hsi2c15_bus>; +}; +/ { + fragment@lwiscamera { + target-path = "/"; + __overlay__ { + /* REAR CAMERA NAGUAL */ + sensor0: sensor@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-nagual"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x3D>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + /* CSID_RST_L GPP2[2] */ + reset-gpios = <&gpp2 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo1-supply = <&slg51002_ldo1>; + ldo4-supply = <&slg51002_ldo4>; + ldo8-supply = <&slg51002_ldo8>; + gpio3-supply = <&slg51002_gpio3>; + + clocks = + <&clock CIS_CLK3>, + <&clock GATE_DFTMUX_CMU_CIS_CLK3>; + clock-names = + "CIS_CLK3", + "GATE_DFTMUX_CMU_CIS_CLK3"; + clock-rates = + <26000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk4_fn>; + pinctrl-1 = <&sensor_mclk4_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo4", + "gpio3", + "ldo8", + "ldo1", + "reset", + "mclk_on"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "regulator", + "regulator", + "gpio", + "pinctrl"; + power-up-seq-delays-us = + <0 + 1000 + 0 + 0 + 2000 + 1000 + 9000>; + + /* Power down sequence */ + power-down-seqs = + "mclk_off", + "reset", + "ldo1", + "ldo8", + "gpio3", + "ldo4", + "s2mpg13_ldo12"; + power-down-seq-types = + "pinctrl", + "gpio", + "regulator", + "regulator", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 0 + 0 + 6000 + 0 + 0>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + /* FRONT CAMERA DOKKAEBI */ + sensor1: sensor@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-dokkaebi"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x10>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + reset-gpios = <&gpp4 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo8-supply = <&slg51002_ldo8>; + gpio4-supply = <&slg51002_gpio4>; + + clocks = + <&clock CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>; + clock-names = + "CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK1"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk2_fn>; + pinctrl-1 = <&sensor_mclk2_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo8", + "gpio4", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <0 + 0 + 1000 + 1000 + 8000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "gpio4", + "ldo8", + "s2mpg13_ldo12"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 1000 + 0 + 0 + 1000>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <1>; + }; + + /* REAR ULTRA WIDE CAMERA SANDWORM */ + sensor2: sensor@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x1A>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* GPIOs */ + reset-gpios = <&gpp6 3 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo2-supply = <&slg51002_ldo2>; + ldo6-supply = <&slg51002_ldo6>; + + clocks = + <&clock CIS_CLK0>, + <&clock GATE_DFTMUX_CMU_CIS_CLK0>; + clock-names = + "CIS_CLK0", + "GATE_DFTMUX_CMU_CIS_CLK0"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk1_fn>; + pinctrl-1 = <&sensor_mclk1_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo6", + "ldo2", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <0 + 0 + 1000 + 1000 + 10000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo2", + "ldo6", + "s2mpg13_ldo12"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 0 + 0 + 1000>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <2>; + }; + + /* REAR Folded Tele Camera KRAKEN */ + sensor3: sensor@3 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-kraken"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x2D>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + /* RTCAM_RST_L GPP6[2] */ + reset-gpios = <&gpp6 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo3-supply = <&slg51002_ldo3>; + ldo7-supply = <&slg51002_ldo7>; + + clocks = + <&clock CIS_CLK2>, + <&clock GATE_DFTMUX_CMU_CIS_CLK2>; + clock-names = + "CIS_CLK2", + "GATE_DFTMUX_CMU_CIS_CLK2"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk3_fn>; + pinctrl-1 = <&sensor_mclk3_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo7", + "ldo3", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <300 + 0 + 0 + 1000 + 10000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo7", + "s2mpg13_ldo12", + "ldo3"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0 + 1000 + 0 + 0>; + + i2c-lock-group-id = <3>; + }; + + /* EEPROM GARGOYLE for NAGUAL*/ + eeprom0: eeprom@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + gpio1-supply = <&slg51002_gpio1>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "gpio1"; + power-up-seq-types = + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "gpio1", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000>; + + i2c-lock-group-id = <0>; + }; + + /* EEPROM SMAUG for DOKKAEBI */ + eeprom1: eeprom@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-dokkaebi"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x51>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + + i2c-lock-group-id = <1>; + }; + + /* EEPROM SMAUG for SANDWORM */ + eeprom2: eeprom@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x50>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + + i2c-lock-group-id = <2>; + }; + + /* EEPROM JOTNAR for KRAKEN*/ + eeprom3: eeprom@3 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo5-supply = <&slg51002_ldo5>; + gpio1-supply = <&slg51002_gpio1>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo5", + "gpio1"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "gpio1", + "ldo5", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0 + 0>; + + i2c-lock-group-id = <3>; + }; + + /* Actuator SLENDERMAN for NAGUAL*/ + actuator0: actuator@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-slenderman"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0xC>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo4-supply = <&slg51002_ldo4>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo4"; + power-up-seq-types = + "regulator", + "regulator"; + power-up-seq-delays-us = + <0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "ldo4", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + /* Actuator JOTNAR for KRAKEN */ + actuator1: actuator@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo5-supply = <&slg51002_ldo5>; + gpio1-supply = <&slg51002_gpio1>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo5", + "gpio1"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "gpio1", + "ldo5", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <3>; + }; + + /* Actuator SLENDERMAN for SANDWORM*/ + actuator2: actuator@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-slenderman-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0xF>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo4-supply = <&slg51002_ldo4>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo4"; + power-up-seq-types = + "regulator", + "regulator"; + power-up-seq-delays-us = + <0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "ldo4", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <2>; + }; + + /* Ois GARGOYLE for NAGUAL*/ + ois0: ois@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "ois-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + gpio1-supply = <&slg51002_gpio1>; + gpio2-supply = <&slg51002_gpio2>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "gpio1", + "gpio2"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "gpio2", + "gpio1", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <5000 + 4000 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + /* Ois JOTNAR for KRAKEN */ + ois1: ois@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "ois-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo5-supply = <&slg51002_ldo5>; + gpio1-supply = <&slg51002_gpio1>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo5", + "gpio1"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "gpio1", + "ldo5", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <3>; + }; + + flash0: flash@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "flash-lm3644"; + + /* I2C */ + i2c-bus = <&hsi2c_15>; + i2c-addr = <0x63>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power Management hibernation (deep sleep) */ + /* 1 : enable, 0 : disable */ + pm-hibernation = <0>; + + /* GPIOs */ + /* HW_ENABLE GPP8[2] */ + /* FLASH_STROBE GPP27[0] */ + enable-gpios = + <&gpp8 2 GPIO_ACTIVE_HIGH + &gpp27 0 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-charging.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-charging.dtsi new file mode 100644 index 000000000000..5946d88ae5c9 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-charging.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to cheetah + * + * Copyright 2021 Google,LLC + * + */ + + +&pca9468_dc { + pca9468,input-current-limit = <2500000>; /* 5A max */ +}; + +&google_charger { + google,thermal-mitigation = <5000000 4000000 2500000 1000000>; + google,wlc-fcc-thermal-mitigation = <5000000 5000000 4000000 2500000 1000000>; + google,thermal-stats-lvl-map = <0 3 5 8>; +}; + +&google_cpm { + /* google,mdis_in = &max77759tcpc, "wireless" */ + /* google,mdis_out = "main-charger", "pca94xx-mains"; */ + + // thermal budgets + google,mdis-thermal-mitigation = + <4352000 3483000 2659000 2058000 1536000 1095000 736000 580000 258000>; + // source ONLINE selection criteria + google,mdis-out-sel-online = <1 2>; + // PD+main-charger, WLC+main-charger + google,mdis-out0-limits = + <5000000 3500000 3000000 2500000 2000000 1500000 1000000 500000 500000 + 1100000 500000 500000 500000 250000 250000 100000 100000 100000>; + // PPS_CP+pca94xx-mains, // WLC_CP+pca94xx-mains + google,mdis-out1-limits = + <5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 + 5000000 4000000 3000000 2500000 2500000 2000000 1500000 1000000 0>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-common.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-common.dtsi new file mode 100644 index 000000000000..bf1c5a737105 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-common.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +#include + +#include "gs201-common.dtsi" +#include "gs201-cloudripper-battery.dtsi" +#include "gs201-cloudripper-bcl.dtsi" +#include "gs201-cloudripper-bluetooth.dtsi" +#include "gs201-pantah-charging.dtsi" +#include "gs201-cloudripper-cp-s5300-sit.dtsi" +#include "gs201-cloudripper-ese.dtsi" +#include "gs201-cloudripper-gsa-gsc.dtsi" +#include "gs201-cloudripper-nfc.dtsi" +#include "gs201-cloudripper-sbbm.dtsi" +#include "gs201-cloudripper-wlan.dtsi" + +#include "gs201-ravenclaw-fingerprint.dtsi" +#include "gs201-ravenclaw-usecases.dtsi" +#include "gs201-ravenclaw-uwb.dtsi" + +#include "gs201-pantah-camera-pmic.dtsi" +#include "gs201-cheetah-camera.dtsi" +#include "gs201-cheetah-display.dtsi" +#include "gs201-cheetah-pmic.dtsi" +#include "gs201-cheetah-touch.dtsi" +#include "gs201-cheetah-thermal.dtsi" +#include "gs201-cheetah-audio.dtsi" +#include "gs201-cheetah-battery.dtsi" +#include "gs101-faceauth-dma-heap.dtsi" +#include "gs201-cheetah-charging.dtsi" +#include "gs201-cheetah-wcharger.dtsi" +#include "gs201-cheetah-usb.dtsi" +#include "gs201-pantah-pmic.dtsi" \ No newline at end of file diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-display-common.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-display-common.dtsi new file mode 100644 index 000000000000..198d668233dc --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-display-common.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common display configurations for Cheetah display. + * + * Copyright 2021 Google LLC + * + */ + +reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; +vddd-supply = <&m_ldo28_reg>; +vddd-normal-microvolt = ; +vddd-lp-microvolt = ; +vci-supply = <&m_ldo27_reg>; +vddi-supply = <&s_bucka_reg>; +touch = <&spitouch>; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-display-constants.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-display-constants.dtsi new file mode 100644 index 000000000000..8be2a9d1b120 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-display-constants.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah display-specific constants + * + * Copyright 2021 Google LLC. + * + */ +#define CHEETAH_VCI_MICROVOLT 3025000 +#define CHEETAH_VDDD_NORMAL_MICROVOLT 1200000 +#define CHEETAH_3HC4_VDDD_NORMAL_MICROVOLT 1125000 +#define CHEETAH_VDDD_LP_MICROVOLT 1050000 diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-display.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-display.dtsi new file mode 100644 index 000000000000..597f0e77dd28 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-display.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Display nodes for cloudripper-related boards. + * + * Copyright 2021 Google LLC + * + */ +#include "gs201-cheetah-display-constants.dtsi" + +&drmdsim0 { + sdc_s6e3hc3_c10: panel@0 { + compatible = "samsung,s6e3hc3-c10"; + label = "sdc-s6e3hc3-c10"; + channel = <0>; + #include "gs201-cheetah-display-common.dtsi" + }; + panel@1 { + compatible = "samsung,emul"; + label = "samsung-emul"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + }; + boe_nt37290: panel@2 { + compatible = "boe,nt37290"; + label = "boe-nt37290"; + channel = <0>; + #include "gs201-cheetah-display-common.dtsi" + }; + sdc_s6e3hc4: panel@3 { + compatible = "samsung,s6e3hc4"; + label = "sdc-s6e3hc4"; + channel = <0>; + #include "gs201-cheetah-display-common.dtsi" + }; +}; + +&dsim_modes { + dsim-modes { + 1080x2340 { + mode-name = "1080x2340"; + pmsk = < + 0x2 0xDB 0x2 0x1355 /* p m s k */ + >; + hs-clk = <1346>; + esc-clk = <20>; + }; + }; +}; + +&sdc_s6e3hc4 { + vddd-normal-microvolt = ; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-dvt1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-dvt1.dts new file mode 100644 index 000000000000..4703fe63d421 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-dvt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30304>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH DVT 1.0 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-evt1-nfc.dts b/arch/arm64/boot/dts/google/gs201-cheetah-evt1-nfc.dts new file mode 100644 index 000000000000..df332b1406b8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-evt1-nfc.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30303>; + board_rev = <0x10003>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH EVT 1.0 with EVT NFC based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-evt1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-cheetah-evt1-wingboard.dts new file mode 100644 index 000000000000..d1da7059198d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-evt1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30303>; + board_rev = <0x10002>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH EVT 1.0 Wingboard based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-evt1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-evt1.dts new file mode 100644 index 000000000000..5f7ada19c755 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-evt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30303>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH EVT 1.0 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1-wingboard.dts new file mode 100644 index 000000000000..8873f1fe26b6 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2022 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30303>; + board_rev = <0x10101>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH EVT 1.1 Wingboard based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1.dts new file mode 100644 index 000000000000..cacd817dec28 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-evt1_1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30303>; + board_rev = <0x10100>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH EVT 1.1 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-mp.dts b/arch/arm64/boot/dts/google/gs201-cheetah-mp.dts new file mode 100644 index 000000000000..fa385cabbb8f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-mp.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" + +/ { + board_id = <0x30306>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH MP based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-pmic.dtsi new file mode 100644 index 000000000000..9629a24714ca --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-pmic.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah-specific PMIC settings + * + * Copyright 2021 Google LLC. + * + */ + +/* Display: Cheetah VDDD-supply's power source */ +&m_buck6_reg { + regulator-initial-mode = ; +}; + +/* Display: vci-supply voltage */ +&m_ldo27_reg { + regulator-min-microvolt = ; + regulator-max-microvolt = ; +}; + +/* Display: Cheetah VDDD-supply voltage */ +&m_ldo28_reg { + regulator-initial-mode = ; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + regulator-ramp-delay = <1200>; + regulator-enable-ramp-delay = <125>; +}; + +/* UWB: Ravenclaw and Cheetah use LDO[16,17]S for UWB */ +&s_ldo16_reg { + regulator-always-on; + regulator-initial-mode = ; +}; + +/* UWB: Ravenclaw and Cheetah use LDO[16,17]S for UWB */ +&s_ldo17_reg { + regulator-always-on; + regulator-initial-mode = ; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-proto1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-proto1.dts new file mode 100644 index 000000000000..caf451b430c6 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-proto1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-cheetah-wcharger-proto.dtsi" + +/ { + board_id = <0x30302>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH Proto 1.0 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1-wingboard.dts new file mode 100644 index 000000000000..3664817d911b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-cheetah-wcharger-proto.dtsi" + +/ { + board_id = <0x30302>; + board_rev = <0x10101>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH Proto 1.1 Wingboard based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1.dts new file mode 100644 index 000000000000..4ee06472e760 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-proto1_1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-cheetah-wcharger-proto.dtsi" + +/ { + board_id = <0x30302>; + board_rev = <0x10100>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH Proto 1.1 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-pvt1.dts b/arch/arm64/boot/dts/google/gs201-cheetah-pvt1.dts new file mode 100644 index 000000000000..08160efa9ecc --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-pvt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cheetah device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cheetah-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30305>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 CHEETAH PVT 1.0 based on GS201"; + compatible = "google,GS201 CHEETAH", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-thermal.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-thermal.dtsi new file mode 100644 index 000000000000..b6aeeac6412f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-thermal.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 cheetah-specific thermal device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include + +&acpm_mfd_bus1 { + s2mpg13mfd@2f { + gs201_tm1: gs201_spmic_tm1 { + compatible = "google,s2mpg13-spmic-thermal"; + #thermal-sensor-cells = <1>; + adc_chan_en = /bits/ 8 <0xFF>; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + neutral_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 0>; + trips { + trip_config0: trip-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 1>; + trips { + trip_config1: trip-config1 { + temperature = <56000>; + hysteresis = <1000>; + type = "passive"; + }; + backup_shutdown_sw: backup-shutdown-sw { + temperature = <57000>; + hysteresis = <1000>; + type = "critical"; + }; + backup_shutdown_hw: backup-shutdown-hw { + temperature = <59000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + qi_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 2>; + trips { + trip_config2: trip-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 3>; + trips { + trip_config3: trip-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 4>; + trips { + trip_config4: trip-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + disp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 5>; + trips { + trip_config5: trip-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + batt_therm_sidekey { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 6>; + trips { + trip_config6: trip-config6 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + gnss_tcxo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 7>; + trips { + trip_config7: trip-config7 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-touch.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-touch.dtsi new file mode 100644 index 000000000000..29d93c9bd8f8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-touch.dtsi @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Cheetah touch device tree source. + * + * Copyright 2021 Google Inc. + * + */ + +#include +#include + +&m_ldo25_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /delete-property/ regulator-always-on; +}; + +&m_ldo26_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /delete-property/ regulator-always-on; +}; + +&spitouch { + status = "ok"; + + compatible = "synaptics,tcm-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + synaptics,avdd-name = "avdd"; + synaptics,vdd-name = "vdd"; + synaptics,power-delay-ms = <200>; + synaptics,irq-gpio = <&gpa7 0 0x2008>; /* IRQF_ONESHOT | IRQF_TRIGGER_LOW */ + synaptics,irq-on-state = <0>; + synaptics,reset-gpio = <&gpp23 2 0>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + synaptics,reset-delay-ms = <200>; + synaptics,spi-mode = <0>; + synaptics,spi-byte-delay-us = <0>; + synaptics,spi-block-delay-us = <0>; + synaptics,pixels-per-mm = <20>; + synaptics,compression-threshold = <15>; + synaptics,grip-delta-threshold = <50>; + synaptics,grip-border-threshold = <50>; + synaptics,panel_map = <&sdc_s6e3hc3_c10>, + <&sdc_s6e3hc4>, + <&boe_nt37290>; + synaptics,firmware_names = "synaptics.img", + "synaptics.img", + "synaptics_b.img"; + synaptics,touch_offload_id = /bits/ 8 <'c' '1' '0' '0'>; + synaptics,udfps-coords = <720 2360>; + synaptics,dynamic-report-rate; + + controller-data { + cs-gpio = <&gpp20 3 0>; + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <0>; + cs-clock-delay = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-usb.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-usb.dtsi new file mode 100644 index 000000000000..1eabba103ac5 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-usb.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Oriole USB device tree source + * + * Copyright 2022 Google,LLC + */ + +&usb_hs_tune { + status = "disabled"; + hs_tune_cnt = <6>; + /* value = */ + hs_tune1 { + tune_name = "tx_pre_emp"; + tune_value = <0x3 0x3>; + }; + + hs_tune2 { + tune_name = "tx_vref"; + tune_value = <0x6 0x6>; + }; + + hs_tune3 { + tune_name = "rx_sqrx"; + tune_value = <0x2 0x2>; + }; + + hs_tune4 { + tune_name = "utmi_clk"; + tune_value = <0x1 0x1>; + }; + + hs_tune5 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune6 { + tune_name = "tx_res"; + tune_value = <0x1 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-wcharger-proto.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-wcharger-proto.dtsi new file mode 100644 index 000000000000..e9d1fb3bbf7a --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-wcharger-proto.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2022 Google Inc. + */ + +&hsi2c_15 { + p9412@3c { + fod = [B2 2E 93 3B 8B 2B 94 0E 98 02 9E ED 19 06 01 3C]; + fod_epp = [AD 54 83 7F 89 46 87 46 8A 37 8D 1F 32 11 01 50]; + google,q_value = <56>; + idt,has_rtx = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cheetah-wcharger.dtsi b/arch/arm64/boot/dts/google/gs201-cheetah-wcharger.dtsi new file mode 100644 index 000000000000..e8fef173cf7b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cheetah-wcharger.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2020 Google Inc. + */ + +#include "gs201-pantah-wcharger.dtsi" + +&hsi2c_15 { + p9412@3c { + fod = [AD 2E 8D 39 87 24 95 06 97 FC 9C E6 19 06 01 3C]; + fod_epp = [AD 54 83 7A 89 44 87 46 8A 33 8D 17 32 11 01 50]; + fod_hpp = [A2 5B 83 7F 8F 13 8D 12 87 3E 8F E1 32 11 01 50]; + fod_hpp_hv = [B0 7F 91 7E 91 38 8E 3E 8B 42 8E 23 32 11 01 50]; + google,q_value = <56>; + google,tx4191_q = <29>; + idt,has_rtx = <1>; + + google,alignment_scalar_low_current = <300>; + google,alignment_scalar_high_current = <100>; + google,alignment_offset_low_current = <123000>; + google,alignment_offset_high_current = <139000>; + google,alignment_current_threshold = <500>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-audio.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-audio.dtsi new file mode 100644 index 000000000000..1c5c029182d4 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-audio.dtsi @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Cloudripper-specific audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include +#include +#include +#include + +&dai_be_tdm0_rx { + codec { + sound-dai = <&cs35l45_1 0>, + <&cs35l45_2 0>, + <&cs35l45_3 0>; + }; +}; + +&dai_be_tdm0_tx { + codec { + sound-dai = <&cs35l45_1 0>, + <&cs35l45_2 0>, + <&cs35l45_3 0>; + }; +}; + +&dai_be_haptic_rx_codec { + sound-dai = <&cs40l26_codec 0>, <&cs40l26_codec_2 0>; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs35l45_1 { + comp = <&cs35l45_1>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + sys@cs35l45_2 { + comp = <&cs35l45_2>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + sys@cs35l45_3 { + comp = <&cs35l45_3>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + sys@cs40l26_codec_2 { + comp = <&cs40l26_codec_2>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + cs35l45_1_irq: cs35l45-1-irq { + samsung,pins = "gpa6-3"; /* XEINT_3 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l45_2_irq: cs35l45-2-irq { + samsung,pins = "gpa8-6"; /* XEINT_26 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l45_3_irq: cs35l45-3-irq { + samsung,pins = "gpa6-2"; /* XEINT_2 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + hapt_amp2_irq: hapt-amp2-irq { + samsung,pins = "gpa8-0"; /* XEINT_12 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +/* GPIO_PERIC0 */ +&pinctrl_4 { + cs35l45_1_rst: cs35l45-1-rst { + samsung,pins = "gpp17-1"; /* XAPC_VSYNC8 */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + cs35l45_miso: cs35l45-miso { + samsung,pins = "gpp14-2"; + samsung,pin-pud = ; + }; + + cs35l45_mosi: cs35l45-mosi { + samsung,pins = "gpp14-1"; + samsung,pin-drv = ; + }; + + cs35l45_clk: cs35l45-clk { + samsung,pins = "gpp14-0"; + samsung,pin-drv = ; + }; + hapt_amp2_rst: hapt-amp2-rst { + samsung,pins = "gpp18-2"; /* XAPC_USI14_RTSn_DI */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi7_cs_func { + samsung,pins = "gpp14-3"; + samsung,pin-drv = ; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + cs35l45_2_rst: cs35l45-2-rst { + samsung,pins = "gpp25-2"; /* XAPC_USI13_RTSN_DI */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + cs35l45_cs2: cs35l45-cs2 { + samsung,pins = "gpp22-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + cs35l45_cs3: cs35l45-cs3 { + samsung,pins = "gpp26-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&s2mpg13_pinctrl { + cs35l45_3_rst: cs35l45-3-rst { + }; +}; + +&spi_7 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus &spi7_cs_func &cs35l45_cs2 &cs35l45_cs3 + &cs35l45_miso &cs35l45_mosi &cs35l45_clk>; + cs-gpios = <&gpp14 3 GPIO_ACTIVE_HIGH>, <&gpp22 1 GPIO_ACTIVE_HIGH>, + <&gpp26 4 GPIO_ACTIVE_HIGH>; + + cs35l45_1: cs35l45@0 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l45"; + spi-max-frequency = <16000000>; + reg = <0>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l45_1_irq &cs35l45_1_rst>; + + interrupt-parent = <&gpa6>; + interrupts = <3 0 0>; + + reset-gpios = <&gpp17 1 GPIO_ACTIVE_HIGH>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,use-tdm-slots; + cirrus,asp-sdout-hiz-ctrl = <3>; + /* cirrus,tuning-has-prefix; + cirrus,left-channel-amp; */ + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x5>; + gpio-invert = <1>; + }; + + controller-data { + cs-gpio = <&gpp14 3 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; + + cs35l45_2: cs35l45@1 { + #sound-dai-cells = <1>; + sound-name-prefix = "R"; + compatible = "cirrus,cs35l45"; + spi-max-frequency = <16000000>; + reg = <1>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l45_2_irq &cs35l45_2_rst>; + + interrupt-parent = <&gpa8>; + interrupts = <6 0 0>; + + reset-gpios = <&gpp25 2 GPIO_ACTIVE_HIGH>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,asp-sdout-hiz-ctrl = <3>; + /*cirrus,tuning-has-prefix; + cirrus,right-channel-amp;*/ + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x5>; + gpio-invert = <1>; + }; + + controller-data { + cs-gpio =<&gpp22 1 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; + + cs35l45_3: cs35l45@2 { + #sound-dai-cells = <1>; + sound-name-prefix = "E"; + compatible = "cirrus,cs35l45"; + spi-max-frequency = <16000000>; + reg = <2>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l45_3_irq>; + + interrupt-parent = <&gpa6>; + interrupts = <2 0 0>; + + reset-gpios = <&s2mpg13_gpio 7 GPIO_ACTIVE_HIGH>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,asp-sdout-hiz-ctrl = <3>; + /*cirrus,tuning-has-prefix; + cirrus,right-channel-amp;*/ + + cirrus,gpio-ctrl2 { + gpio-ctrl = <0x5>; + gpio-invert = <1>; + }; + + controller-data { + cs-gpio =<&gpp26 4 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; +}; + +&aoc { + aoc-board-cfg = "cr"; + aoc-board-id = <0x30101>; + aoc-board-rev = <0x10000>; +}; + +&cs40l26a_haptics { + pinctrl-0 = <&hapt_amp2_irq &hapt_amp2_rst &hapt_amp_trig>; + + interrupt-parent = <&gpa8>; + interrupts = <0 0 0>; + + reset-gpios = <&gpp18 2 0>; + + status = "okay"; +}; + +&hsi2c_8 { + #address-cells = <1>; + #size-cells = <0>; + + cs40l26a_haptics_2: cs40l26a@42 { + compatible = "cirrus,cs40l26a"; + reg = <0x42>; + dev-name = "cs40l26a-dual"; /* sysfs folder name */ + input-device-name = "cs40l26_dual_input"; /* input device name */ + + pinctrl-names = "default"; + pinctrl-0 = <&hapt_amp_irq &hapt_amp_rst>; + + interrupt-parent = <&gpa8>; + interrupts = <1 0 0>; + + reset-gpios = <&gpp24 3 0>; + + /* TODO (b/185767279): check the trigger & refclk pin usage. */ + + status = "okay"; + + cs40l26_codec_2: cs40l26_codec_2@snd { + #sound-dai-cells = <1>; + sound-name-prefix = "HR"; + compatible = "cs40l26-codec"; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-battery.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-battery.dtsi new file mode 100644 index 000000000000..af55b12f3b3b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-battery.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to raviole + * + * Copyright 2020 Google,LLC + * + */ + +#include + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + + google_battery: google,battery { + status = "okay"; + compatible = "google,battery"; + google,fg-psy-name = "maxfg"; + + /* charge table */ + google,chg-temp-limits = <0 100 200 420 460 480 550>; + google,chg-cv-limits = <4200000 4300000 4450000>; + google,chg-cc-limits = < + 30 10 0 + 50 30 30 + 100 70 50 + 80 50 50 + 50 50 0 + 30 0 0 + >; + + google,ttf-temp-idx= <2>; + google,ttf-adapter = <1800>; + google,ttf-soc-table = <49 59 72 78 93 95 98 100>; + google,ttf-elap-table = <45 52 56 67 78 91 104 120>; + google,ttf-tier-table = <0 71 78>; + + /* IRDrop Compensation */ + google,fv-uv-resolution = <10000>; + /* NOTE: high value for DC charging */ + google,fv-uv-margin-dpct = <1025>; + /* tier switch */ + google,cv-range-accuracy = <20000>; + google,cv-otv-margin = <12000>; + google,cv-debounce-cnt = <3>; + google,cv-tier-ov-cnt = <10>; + google,cv-tier-switch-cnt = <3>; + + google,eeprom-pairing; + + /* rest charging */ + google,chg-rest-rate = <15>; + google,chg-rest-soc = <80>; + /* TRICKLE-DEFEND threshold */ + google,bd-trickle-recharge-soc = <80>; + /* Enable TRICKLE-DEFEND */ + google,bd-trickle-enable; + /* Battery virtual sensor */ + google,batt-vs-tz-name = "batt_vs"; + + /* record over temperature time */ + google,temp-record-thr = <300 350 400>; + google,soc-record-thr = <90 90 95>; + + #thermal-sensor-cells = <0>; + #cooling-cells = <2>; + }; + + google_bms { + nvmem = <&pack_bee>; + nvmem-names = "6-00500"; + /* pack eeprom is available only with P20+ batteries */ + google,bee-name = "6-00500"; + }; + + }; + }; +}; + +&pinctrl_0 { +/* [MAX77759: FG_INTB] > FG_INT_L > [XEINT_23 : SC59845XWE] */ + if_pmic_fg_irq: if-pmic-fg-irq { + samsung,pins = "gpa9-3"; /* XEINT_23 */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_0 { +/* [MAX77729FEWN : INTB] > IF_PMIC_IRQ_L > [XEINT_24 : SC59845XWE] */ + if_pmic_irq: if-pmic-irq { + samsung,pins = "gpa9-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + +}; + +&hsi2c13_bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + + pack_bee: m24c08@50 { + status = "okay"; + compatible = "at,24c08"; + + reg = <0x50>; + }; +}; + +&hsi2c_13 { + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + /* also as max77759 pmic */ + max77729_pmic:max77729pmic@0x66 { + status = "okay"; + compatible = "maxim,max77729pmic"; + reg = <0x66>; + + pinctrl-names = "default"; + pinctrl-0 = <&if_pmic_irq>; + max777x9,irq-gpio = <&gpa9 4 GPIO_ACTIVE_LOW>; + + max77759,max_m5 = <&max77759_fg>; + + max777x9_gpio: max777x9_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + + interrupt-parent = <&gpa9>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <5 IRQ_TYPE_NONE>, + <6 IRQ_TYPE_NONE>; + }; + }; + + max77759_fg:max77759fg@0x36 { + status = "okay"; + compatible = "maxim,max77759"; + reg = <0x36>; + + /* FG_INT_L -> XEINT_23 */ + pinctrl-names = "default"; + pinctrl-0 = <&if_pmic_fg_irq>; + maxim,irq-gpio = <&gpa9 3 GPIO_ACTIVE_LOW>; + + maxim,gauge-type = <2>; + maxim,force-batt-id = <170>; + maxim,rsense-default = <500>; + maxim,batt-id-range-pct = <0>; + + maxim,psy-type-unknown; + maxim,fg-data { + #include "gs101-fake-battery-data.dtsi" + }; + }; + + max77759_chg:max77759chrg@0x69 { + status = "okay"; + compatible = "maxim,max77759chrg"; + reg = <0x69>; + + interrupt-parent = <&gpa9>; + max77759,irq-gpio = <&gpa9 4 GPIO_ACTIVE_LOW>; + + max77759,max_m5 = <&max77759_fg>; + max77759,pmic = <&max77729_pmic>; + + max77759,chg-term-voltage = <4400>; + + #thermal-sensor-cells = <1>; + }; + +}; + + diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-bcl.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-bcl.dtsi new file mode 100644 index 000000000000..a832de6f1aba --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-bcl.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 Cloudripper-specific bcl device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + google_mitigation: google,mitigation { + compatible = "google,google-bcl"; + #thermal-sensor-cells = <1>; + google,charger = <&max77759_chg>; + google,power-supply = <&max77759_fg>; + google,main-power = <&s2mpg12mfd>; + google,sub-power = <&s2mpg13mfd>; + ppm_settings = <0>; + mpmm_settings = <0x1a>; + tpu_con_heavy = <0xfff041c3>; + tpu_con_light = <0xfff041c1>; + tpu_clkdivstep = <0x1>; + gpu_con_heavy = <0xfff04385>; + gpu_con_light = <0xfff041c1>; + gpu_clkdivstep = <0x1>; + cpu2_clkdivstep = <0x1>; + cpu1_clkdivstep = <0x1>; + cpu0_clkdivstep = <0x1>; + odpm_ratio = <3>; + gpios = <&gpa5 5 0>, /* VDROOP1 */ + <&gpa5 6 0>; /* VDROOP2 */ + }; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + batoilo { + zone_name = "BATOILO"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 12>; + trips { + batoilo: batoilo{ + temperature = <5000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + vdroop1 { + zone_name = "VDROOP1"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 10>; + trips { + vdroop1: vdroop1{ + temperature = <1000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + vdroop2 { + zone_name = "VDROOP2"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 11>; + trips { + vdroop2: vdroop2{ + temperature = <1200>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + battery_cycle { + zone_name = "BATTERY_CYCLE"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_battery>; + }; + + pmic_120c { + zone_name = "PMIC_120C"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 13>; + trips { + pmic_120c: pmic-120c { + temperature = <1200>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmic_140c { + zone_name = "PMIC_140C"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 14>; + trips { + pmic_140c: pmic-140c { + temperature = <1400>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + pmic_overheat { + zone_name = "PMIC_OVERHEAT"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 15>; + trips { + pmic_overheat: pmic-overheat{ + temperature = <2000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + + soc { + zone_name = "BATT_SOC_MOD"; + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 9>; + + trips { + soc_trip:soc-trip { + temperature = <80>; + hysteresis = <0>; + type = "passive"; + }; + }; + }; + + smpl_gm { + zone_name = "SMPL_GM"; + polling-delay-passive = <1000>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 0>; + + trips { + smpl:smpl_0 { + temperature = <1100>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_cpu1 { + zone_name = "OCP_CPU1"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 1>; + + trips { + ocp_cpu1:ocp-cpu1 { + temperature = <8000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_cpu2 { + zone_name = "OCP_CPU2"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 2>; + + trips { + ocp_cpu2:ocp-cpu2 { + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_cpu1 { + zone_name = "SOFT_OCP_CPU1"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 3>; + + trips { + soft_ocp_cpu1:soft-ocp-cpu1 { + temperature = <8000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_cpu2 { + zone_name = "SOFT_OCP_CPU2"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 4>; + + trips { + soft_ocp_cpu2:soft-ocp-cpu2 { + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_tpu { + zone_name = "OCP_TPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 5>; + + trips { + ocp_tpu:ocp-tpu{ + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_tpu { + zone_name = "SOFT_OCP_TPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 6>; + + trips { + soft_ocp_tpu:soft-ocp-tpu { + temperature = <8500>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + ocp_gpu { + zone_name = "OCP_GPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 7>; + + trips { + ocp_gpu:ocp-gpu{ + temperature = <12000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; + soft_ocp_gpu { + zone_name = "SOFT_OCP_GPU"; + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&google_mitigation 8>; + + trips { + soft_ocp_gpu:soft-ocp-gpu { + temperature = <9000>; + hysteresis = <100>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-bluetooth.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-bluetooth.dtsi new file mode 100644 index 000000000000..09d147dbf984 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-bluetooth.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Bluetooth device tree for raven. + * + * Copyright 2021 Google LLC + * + */ + +#include +#include + +&pinctrl_4 { + bt_timesync: bt-timesync { + samsung,pins = "gpp11-1"; + samsung,pin-function= ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&btbcm { + pinctrl-0 = <&bt_reg_on &bt_dev_wake &bt_host_wake &bt_timesync>; + timesync-gpios = <&gpp11 1 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-camera-av5.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-camera-av5.dtsi new file mode 100644 index 000000000000..d5da71459068 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-camera-av5.dtsi @@ -0,0 +1,1047 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 camera lwis device tree source for av5 + * + * Copyright 2021 Google LLC. + * + */ + +#include +#include +#include + +&pinctrl_4 { + hsi2c1_bus: hsi2c1-bus { + samsung,pin-pud = ; + }; + + hsi2c1_bus_in: hsi2c1-bus-in { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c2_bus: hsi2c2-bus { + samsung,pin-pud = ; + }; + + hsi2c2_bus_in: hsi2c2-bus-in { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c3_bus: hsi2c3-bus { + samsung,pin-pud = ; + }; + + hsi2c3_bus_in: hsi2c3-bus-in { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c4_bus: hsi2c4-bus { + samsung,pin-pud = ; + }; + + hsi2c4_bus_in: hsi2c4-bus-in { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&hsi2c_1 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp2 0 GPIO_ACTIVE_HIGH &gpp2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c1_bus_in>; + pinctrl-1 = <&hsi2c1_bus>; + pinctrl-2 = <&hsi2c1_bus_in>; +}; + +&hsi2c_2 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp4 0 GPIO_ACTIVE_HIGH &gpp4 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c2_bus_in>; + pinctrl-1 = <&hsi2c2_bus>; + pinctrl-2 = <&hsi2c2_bus_in>; +}; + +&hsi2c_3 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp6 0 GPIO_ACTIVE_HIGH &gpp6 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c3_bus_in>; + pinctrl-1 = <&hsi2c3_bus>; + pinctrl-2 = <&hsi2c3_bus_in>; +}; + +&hsi2c_4 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp8 0 GPIO_ACTIVE_HIGH &gpp8 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c4_bus_in>; + pinctrl-1 = <&hsi2c4_bus>; + pinctrl-2 = <&hsi2c4_bus_in>; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp24 0 GPIO_ACTIVE_HIGH &gpp24 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <400000>; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-1 = <&hsi2c15_bus>; + pinctrl-2 = <&hsi2c15_bus>; +}; +/ { + fragment@lwiscamera { + target-path = "/"; + __overlay__ { + /* REAR CAMERA NAGUAL */ + sensor0: sensor@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-nagual"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x3D>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + /* CSID_RST_L GPP2[2] */ + reset-gpios = <&gpp2 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo2-supply = <&slg51000_ldo2>; + ldo3-supply = <&slg51000_ldo3>; + + clocks = + <&clock CIS_CLK3>, + <&clock GATE_DFTMUX_CMU_CIS_CLK3>; + clock-names = + "CIS_CLK3", + "GATE_DFTMUX_CMU_CIS_CLK3"; + clock-rates = + <26000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk4_fn>; + pinctrl-1 = <&sensor_mclk4_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo2", + "ldo3", + "reset", + "mclk_on"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "gpio", + "pinctrl"; + power-up-seq-delays-us = + <1000 + 1000 + 1000 + 1000 + 9000>; + + /* Power down sequence */ + power-down-seqs = + "mclk_off", + "reset", + "ldo3", + "ldo2", + "ldo1"; + power-down-seq-types = + "pinctrl", + "gpio", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 2000 + 1000 + 1000>; + }; + + /* FRONT CAMERA BURAQ */ + sensor1: sensor@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-buraq"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x1A>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* GPIOs */ + reset-gpios = <&gpp4 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo7-supply = <&slg51000_ldo7>; + + clocks = + <&clock CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>; + clock-names = + "CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK1"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk2_fn>; + pinctrl-1 = <&sensor_mclk2_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo7", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <1000 + 1000 + 1000 + 8000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo7", + "ldo1"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 1000 + 1000>; + }; + + /* REAR ULTRA WIDE CAMERA SANDWORM */ + sensor2: sensor@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x1A>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* GPIOs */ + reset-gpios = <&gpp6 3 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo4-supply = <&slg51000_ldo4>; + + clocks = + <&clock CIS_CLK0>, + <&clock GATE_DFTMUX_CMU_CIS_CLK0>; + clock-names = + "CIS_CLK0", + "GATE_DFTMUX_CMU_CIS_CLK0"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk1_fn>; + pinctrl-1 = <&sensor_mclk1_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo4", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <3000 + 1000 + 1000 + 10000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo4", + "ldo1"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 3000 + 1000>; + }; + + /* REAR CAMERA LAMASSU */ + sensor3: sensor@3 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-lamassu"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x1A>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* GPIOs */ + /* RTCAM_RST_L GPP6[2] */ + reset-gpios = <&gpp6 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo5-supply = <&slg51000_ldo5>; + ldo6-supply = <&slg51000_ldo6>; + + /* RTCAM_EN_S2MPG11 GPIO8 */ + enable-gpios = + <&s2mpg13_gpio 2 GPIO_ACTIVE_HIGH>; + + clocks = + <&clock CIS_CLK2>, + <&clock GATE_DFTMUX_CMU_CIS_CLK2>; + clock-names = + "CIS_CLK2", + "GATE_DFTMUX_CMU_CIS_CLK2"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk3_fn>; + pinctrl-1 = <&sensor_mclk3_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo5", + "enable", + "ldo6", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "gpio", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <1000 + 3000 + 1000 + 0 + 0 + 8000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo6", + "enable", + "ldo5", + "ldo1"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "gpio", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 1000 + 1000 + 3000 + 1000 + 1000>; + }; + + /* FRONT CAMERA DOKKAEBI */ + sensor4: sensor@4 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-dokkaebi"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x10>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + reset-gpios = <&gpp4 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo7-supply = <&slg51000_ldo7>; + + clocks = + <&clock CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>; + clock-names = + "CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK1"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk2_fn>; + pinctrl-1 = <&sensor_mclk2_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo7", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <1000 + 1000 + 1000 + 8000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo7", + "ldo1"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 1000 + 1000>; + }; + + /* REAR TELE CAMERA KRAKEN */ + sensor5: sensor@5 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-kraken"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x2D>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + /* RTCAM_RST_L GPP6[2] */ + reset-gpios = <&gpp6 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo5-supply = <&slg51000_ldo5>; + ldo6-supply = <&slg51000_ldo6>; + + /* RTCAM_EN_S2MPG11 GPIO8 */ + enable-gpios = + <&s2mpg13_gpio 2 GPIO_ACTIVE_HIGH>; + + clocks = + <&clock CIS_CLK2>, + <&clock GATE_DFTMUX_CMU_CIS_CLK2>; + clock-names = + "CIS_CLK2", + "GATE_DFTMUX_CMU_CIS_CLK2"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk3_fn>; + pinctrl-1 = <&sensor_mclk3_out>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo5", + "enable", + "ldo6", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "gpio", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <1000 + 3000 + 1000 + 0 + 0 + 10000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo6", + "enable", + "ldo5", + "ldo1"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "gpio", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 1000 + 1000 + 3000 + 1000 + 1000>; + }; + + /* EEPROM GARGOYLE for NAGUAL*/ + eeprom0: eeprom@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo2-supply = <&slg51000_ldo2>; + ldo3-supply = <&slg51000_ldo3>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo2", + "ldo3"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo3", + "ldo2", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <2000 + 1000 + 1000>; + }; + + /* EEPROM SMAUG for BURAQ */ + eeprom1: eeprom@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-buraq"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x51>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + + /* Power up sequence */ + power-up-seqs = + "ldo1"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo1"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + }; + + /* EEPROM SMAUG for SANDWORM */ + eeprom2: eeprom@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x50>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + + /* Power up sequence */ + power-up-seqs = + "ldo1"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo1"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + }; + + /* EEPROM JOTNAR for LAMASSU*/ + eeprom3: eeprom@3 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo5-supply = <&slg51000_ldo5>; + ldo6-supply = <&slg51000_ldo6>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo5", + "ldo6"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 4000 + 0000>; + + /* Power down sequence */ + power-down-seqs = + "ldo6", + "ldo5", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 4000 + 1000>; + }; + + /* Actuator SLENDERMAN for NAGUAL*/ + actuator0: actuator@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-slenderman"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0xC>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo2-supply = <&slg51000_ldo2>; + ldo3-supply = <&slg51000_ldo3>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo2", + "ldo3"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo3", + "ldo2", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <2000 + 1000 + 1000>; + }; + + /* Actuator JOTNAR for LAMASSU / KRAKEN */ + actuator1: actuator@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo5-supply = <&slg51000_ldo5>; + ldo6-supply = <&slg51000_ldo6>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo5", + "ldo6"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 4000 + 0000>; + + /* Power down sequence */ + power-down-seqs = + "ldo6", + "ldo5", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 4000 + 1000>; + }; + + /* Actuator SLENDERMAN for SANDWORM */ + actuator2: actuator@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-slenderman-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0xF>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo2-supply = <&slg51000_ldo2>; + ldo3-supply = <&slg51000_ldo3>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo2", + "ldo3"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo3", + "ldo2", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <2000 + 1000 + 1000>; + }; + + /* Ois GARGOYLE for NAGUAL*/ + ois0: ois@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "ois-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo2-supply = <&slg51000_ldo2>; + ldo3-supply = <&slg51000_ldo3>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo2", + "ldo3"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo3", + "ldo2", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <2000 + 1000 + 1000>; + }; + + /* Ois JOTNAR for LAMASSU*/ + ois1: ois@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "ois-jotnar"; + + /* I2C */ + i2c-bus = <&hsi2c_4>; + i2c-addr = <0x34>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + ldo1-supply = <&slg51000_ldo1>; + ldo5-supply = <&slg51000_ldo5>; + ldo6-supply = <&slg51000_ldo6>; + + /* Power up sequence */ + power-up-seqs = + "ldo1", + "ldo5", + "ldo6"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 4000 + 0000>; + + /* Power down sequence */ + power-down-seqs = + "ldo6", + "ldo5", + "ldo1"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 4000 + 1000>; + }; + + flash0: flash@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "flash-lm3644"; + + /* I2C */ + i2c-bus = <&hsi2c_15>; + i2c-addr = <0x63>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power Management hibernation (deep sleep) */ + /* 1 : enable, 0 : disable */ + pm-hibernation = <0>; + + /* GPIOs */ + /* HW_ENABLE GPP8[2] */ + /* FLASH_STROBE GPP27[0] */ + enable-gpios = + <&gpp8 2 GPIO_ACTIVE_HIGH + &gpp27 0 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-camera-pmic-av5.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-camera-pmic-av5.dtsi new file mode 100644 index 000000000000..aac5beb6cf56 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-camera-pmic-av5.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 pmic device tree source for av5 + * + * Copyright 2021 Google LLC. + * + */ + +#include +#include + +&hsi2c_8 { + /* SLG51000 */ + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + slg51000: slg51000@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + status = "ok"; + dlg,pu-gpios = <&s2mpg13_gpio 4 GPIO_ACTIVE_HIGH>; + dlg,buck-gpios = <&s2mpg13_gpio 3 GPIO_ACTIVE_HIGH>; + dlg,bb-gpios = <&s2mpg13_gpio 1 GPIO_ACTIVE_HIGH>; + dlg,cs-gpios = <&s2mpg13_gpio 0 GPIO_ACTIVE_HIGH>; + dlg,op-mode = <4>; + dlg,reg-init-cells = <2>; + + regulators { + slg51000_ldo1: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_ldo2: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <2250000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_ldo3: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_ldo4: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_ldo5: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_ldo6: ldo6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_ldo7: ldo7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_ldo_dummy: ldo_dummy { + regulator-name = "ldo_dummy"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + + slg51000_gpio: slg51000_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + gpio-ranges = <&slg51000_pinctrl 0 0 8>; + }; + + slg51000_pinctrl: slg51000_pinctrl { + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-charging.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-charging.dtsi new file mode 100644 index 000000000000..dca873da373d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-charging.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to raviole + * + * Copyright 2021 Google,LLC + * + */ + +/ { + fragment@charging { + target-path = "/"; + __overlay__ { + + google_cpm: google,cpm { + status = "okay"; + compatible = "google,cpm"; + google,chg-power-supplies = "main-charger", + "pca94xx-mains"; + + /* S2MPG12X01 -> GPIO_1 -> CHARGE_PUMP_EN */ + google,dc-en = <&s2mpg12_gpio 1 0>; + /* DC enabled by default */ + google,dc-en-value = <1>; + google,dc_limit-demand = <560000>; + google,dc_limit-vbatt = <4350000>; + google,dc_limit-vbatt_min = <3400000>; + + google,tcpm-power-supply = <&max77759tcpc>; + google,wlc_dc-power-supply = "wireless"; + google,pps-awake; + }; + + google_charger: google,charger { + status = "okay"; + compatible = "google,charger"; + #cooling-cells = <2>; + + google,chg-power-supply = "gcpm"; + google,bat-power-supply = "battery"; + google,usb-power-supply = "usb"; + + google,fv-max-uv = <4450000>; + + google,thermal-mitigation = <4000000 3000000 + 2000000 1000000 500000>; + google,wlc-thermal-mitigation = <1100000 500000 250000 110000>; + google,wlc-fcc-thermal-limits = <4000000 3000000 + 2000000 1000000 500000>; + + /* b/170700459 thresholds, updated in b/191070950 */ + google,bd-resume-abs-temp = <280>; + google,bd-resume-soc = <50>; + google,bd-resume-time = <14400>; /* 4 hours */ + google,bd-resume-temp = <290>; + google,bd-trigger-time = <21600>; /* 6 hours */ + google,bd-trigger-temp = <350>; + google,bd-trigger-voltage = <4270000>; + google,bd-recharge-voltage = <4250000>; + google,bd-drainto-soc = <80>; + google,bd-recharge-soc = <79>; + /* Enable TEMP-DEFEND */ + google,bd-temp-enable; + google,bd-temp-dry-run; + }; + + google_bms { + nvmem = <&pack_bee>; + }; + + }; + }; +}; + +&pinctrl_0 { + + dc_charger_irq: dc-charger-irq { + samsung,pins = "gpa9-0"; /* XEINT_20 (PLC_INT_L) */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + + +&max77759_chg { + max77759,psy-name = "main-charger"; +}; + +&hsi2c_13 { + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + pca9468_dc: pca9468@57 { + compatible = "nxp,pca9468"; + reg = <0x57>; + + pca9468,psy_name = "pca94xx-mains"; + + pinctrl-names = "default"; + pinctrl-0 = <&dc_charger_irq>; + + interrupt-parent = <&gpa9>; + pca9468,irq-gpio = <&gpa9 0 GPIO_ACTIVE_LOW>; /* PLC_INT_L */ + + pca9468,float-voltage = <4300000>; /* 4.3V */ + + pca9468,input-itopoff = <500000>; /* 500mA */ + pca9468,sense-resistance = <0>; /* 5mOhm */ + pca9468,switching-frequency = <3>; /* 980KHz */ + + /* disable USBC NTC */ + pca9468,ntc-threshold = <0>; /* disabled */ + + /* USBC thermal zone */ + google,usb-port-tz-name = "usbc-therm-adc"; + + /* irdrop */ + google,irdrop-limits = <105000 75000 0>; + + pca9468,google_cpm = <&google_cpm>; + }; + +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-common.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-common.dtsi new file mode 100644 index 000000000000..18f98e8350bd --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-common.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cloudripper device tree source (inhereted by Ravenclaw too) + * + * Copyright 2020 Google,LLC + */ + +#include "gs201-common.dtsi" +#include "gs201-cloudripper-battery.dtsi" +#include "gs201-cloudripper-bcl.dtsi" +#include "gs201-cloudripper-bluetooth.dtsi" +#include "gs201-cloudripper-camera-av5.dtsi" +#include "gs201-cloudripper-camera-pmic-av5.dtsi" +#include "gs201-cloudripper-charging.dtsi" +#include "gs201-cloudripper-cp-s5300-sit.dtsi" +#include "gs201-cloudripper-ese.dtsi" +#include "gs201-cloudripper-fingerprint.dtsi" +#include "gs201-cloudripper-gsa-gsc.dtsi" +#include "gs201-cloudripper-ldaf.dtsi" +#include "gs201-cloudripper-nfc.dtsi" +#include "gs201-cloudripper-sbbm.dtsi" +#include "gs201-cloudripper-wlan.dtsi" +#include "gs101-faceauth-dma-heap.dtsi" + diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-cp-s5300-sit.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-cp-s5300-sit.dtsi new file mode 100644 index 000000000000..3295a32fe8f4 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-cp-s5300-sit.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include "gs201-cp-s5300-sit.dtsi" +#include "gs101-cp-s5200-thermal-zone.dtsi" + +/ { + fragment@modemif { + target-path = "/"; + __overlay__ { + #address-cells = <2>; + #size-cells = <1>; + + /* Modem interface information */ + cpif { + pinctrl-names = "default"; + pinctrl-0 = <&s5100_ap2cp_cp_pwr_on>, + <&s5100_ap2cp_cp_nreset_n>, + <&s5100_cp2ap_cp_ps_hold>, + <&s5100_ap2cp_wakeup>, + <&s5100_cp2ap_wakeup>, + <&s5100_ap2cp_dump_noti>, + <&s5100_ap2cp_pda_active>, + <&s5100_cp2ap_phone_active>, + <&s5100_ap2cp_cp_wrst_n>, + <&s5100_cp2ap_cp_wrst_n>, + <&s5100_ap2cp_pm_wrst_n>; + + /* Definition of GPIOs */ + gpio_ap2cp_wake_up = <&gph0 2 0x1>; + gpio_ap2cp_dump_noti = <&gph0 3 0x1>; + gpio_ap2cp_cp_pwr_on = <&gph1 2 0x1>; + gpio_ap2cp_pda_active = <&gph1 1 0x1>; + gpio_ap2cp_nreset_n = <&gph1 3 0x1>; + gpio_ap2cp_cp_wrst_n = <&gph1 6 0x1>; + gpio_ap2cp_pm_wrst_n = <&gpa0 3 0x1>; + + gpio_cp2ap_phone_active = <&gpa8 4 0x1>; + gpio_cp2ap_cp_ps_hold = <&gpa8 2 0x1>; + gpio_cp2ap_wake_up = <&gpa8 3 0x1>; + + /* + * The pad assignment of CP2AP_ACTIVE is not in PAD_ALIVE + * to be registered wake-up source. (Bug 152900487) + * CP2AP_ACTIVE is assigned to XEINT_17 for factor designs. + */ + mif,cp2ap_active_not_alive = <0>; + }; + }; + }; +}; + +&pinctrl_0 { + s5100_cp2ap_cp_wrst_n: s5100_cp2ap_cp_wrst_n { + samsung,pins = "gpa0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = ; + }; + + s5100_ap2cp_pm_wrst_n: s5100_ap2cp_pm_wrst_n { + samsung,pins = "gpa0-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + }; +}; + +&pinctrl_1 { + s5100_cp2ap_wakeup: s5100_cp2ap_wakeup { + samsung,pins = "gpa8-3"; + samsung,pin-function = <0xf>; + samsung,pin-pud = ; + }; + + s5100_cp2ap_phone_active: s5100_cp2ap_phone_active { + samsung,pins = "gpa8-4"; + samsung,pin-function = <0xf>; + samsung,pin-pud = ; + }; + + s5100_cp2ap_cp_ps_hold: s5100_cp2ap_cp_ps_hold { + samsung,pins = "gpa8-2"; + samsung,pin-pud = ; + }; +}; + +&pinctrl_6 { + s5100_ap2cp_cp_nreset_n: s5100_ap2cp_cp_nreset_n { + samsung,pins = "gph1-3"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_cp_pwr_on: s5100_ap2cp_cp_pwr_on { + samsung,pins = "gph1-2"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_pda_active: s5100_ap2cp_pda_active { + samsung,pins = "gph1-1"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_wakeup: s5100_ap2cp_wakeup { + samsung,pins = "gph0-2"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_dump_noti: s5100_ap2cp_dump_noti { + samsung,pins = "gph0-3"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + + s5100_ap2cp_cp_wrst_n: s5100_ap2cp_cp_wrst_n { + samsung,pins = "gph1-6"; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-dev.dts b/arch/arm64/boot/dts/google/gs201-cloudripper-dev.dts new file mode 100644 index 000000000000..4be92eefdc3e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-dev.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cloudripper DEV device tree source + * + * Copyright 2020 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-cloudripper-common.dtsi" + +#include "gs201-cloudripper-audio.dtsi" +#include "gs201-cloudripper-pmic.dtsi" +#include "gs201-cloudripper-touch.dtsi" +#include "gs201-cloudripper-display.dtsi" +#include "gs201-max20339-ovp.dtsi" +#include "gs201-cloudripper-thermal.dtsi" +#include "gs201-cloudripper-wcharger.dtsi" +#include "gs201-cloudripper-usecases.dtsi" + +/ { + board_id = <0x30101>; + board_rev = <0x000000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 Cloudripper DEV based on GS201"; + compatible = "google,GS201 CLOUDRIPPER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-display.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-display.dtsi new file mode 100644 index 000000000000..d2eb46629b22 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-display.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Display nodes for slider-related boards. + * + * Copyright 2021 Google LLC + * + */ + +#include +#include "gs201-cheetah-display-constants.dtsi" + +&drmdsim0 { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e3hc2-fhd"; + label = "samsung-s6e3hc2-fhd"; + channel = <0>; + touch = <&spitouch>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + vci-supply = <&m_ldo27_reg>; + vddi-supply = <&m_ldo24_reg>; + }; + panel@1 { + compatible = "samsung,emul"; + label = "samsung-emul"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&drmdsim1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6e3hc3"; + label = "samsung-s6e3hc3"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + vddd-supply = <&m_ldo28_reg>; + vddd-normal-microvolt = ; + vddd-lp-microvolt = ; + vci-supply = <&s_ldo6_reg>; + vddi-supply = <&s_bucka_reg>; + }; + panel@1 { + compatible = "samsung,emul"; + label = "samsung-emul"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + }; + panel@2 { + compatible = "samsung,s6e3fc3-p10"; + label = "sdc-s6e3fc3-p10"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + vci-supply = <&s_ldo6_reg>; + vddi-supply = <&s_bucka_reg>; + }; + panel@3 { + compatible = "samsung,s6e3hc3-c10"; + label = "sdc-s6e3hc3-c10"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + vddd-normal-microvolt = ; + vddd-lp-microvolt = ; + vci-supply = <&s_ldo6_reg>; + vddi-supply = <&s_bucka_reg>; + }; + panel@4 { + compatible = "samsung,s6e3hc4"; + label = "sdc-s6e3hc4"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + vddd-normal-microvolt = ; + vddd-lp-microvolt = ; + vci-supply = <&s_ldo6_reg>; + vddi-supply = <&s_bucka_reg>; + }; + panel@5 { + compatible = "boe,nt37290"; + label = "boe-nt37290"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpp23 0 GPIO_ACTIVE_HIGH>; + vddd-normal-microvolt = ; + vddd-lp-microvolt = ; + vci-supply = <&s_ldo6_reg>; + vddi-supply = <&s_bucka_reg>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-ese.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-ese.dtsi new file mode 100644 index 000000000000..093b85c4270a --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-ese.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include +#include + +&pinctrl_6 { + ese1_spi_rst: ese1-spi-rst { + samsung,pins ="gph1-4"; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + ese2_spi_rst: ese2-spi-rst { + samsung,pins ="gph0-4"; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi10_bus { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&spi10_cs { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&spi17_bus { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&pinctrl_0 { + spi17_bus_off: spi17-bus-off { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + spi17_cs_on: spi17-cs-on { + samsung,pins = "gpa4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-val = <1>; + }; + spi17_cs_off: spi17-cs-off { + samsung,pins = "gpa4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; +}; + +&spi_17 { + /* XAPM_USI0 */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&gpa4 3 GPIO_ACTIVE_HIGH>; + + ese2: ese@0 { + compatible = "st,st33spi"; + reg = <0>; + spi-max-frequency = <8000000>; + esereset-gpio = <&gph0 4 GPIO_ACTIVE_HIGH>; + power_mode = "ST33"; + pinctrl-names = "default","on","off"; + pinctrl-0 = <&spi17_bus_off &spi17_cs_off &ese2_spi_rst>; + pinctrl-1 = <&spi17_bus &spi17_cs_on &ese2_spi_rst>; + pinctrl-2 = <&spi17_bus_off &spi17_cs_off &ese2_spi_rst>; + + controller-data { + cs-gpio = <&gpa4 3 GPIO_ACTIVE_HIGH>; + cs-clock-delay = <10>; + cs-init-state = <0>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; + +&spi_10 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus &spi10_cs &ese1_spi_rst>; + cs-gpios = <&gpp21 3 GPIO_ACTIVE_HIGH>; + + ese1: ese@0 { + compatible = "st,st54spi"; + reg = <0>; + spi-max-frequency = <8000000>; + esereset-gpio = <&gph1 4 GPIO_ACTIVE_HIGH>; + power_mode = "ST54J"; + + controller-data { + cs-gpio = <&gpp21 3 GPIO_ACTIVE_HIGH>; + cs-clock-delay = <10>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-fingerprint.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-fingerprint.dtsi new file mode 100644 index 000000000000..d06435d59fdb --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-fingerprint.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Goodix fps device tree source + * + * Copyright 2021 Google,LLC. + */ + +&odm { + goodixfp { + status = "okay"; + compatible = "goodix,fingerprint"; + interrupt-parent = <&gpa8>; + interrupts = <7 0>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + fp-gpio-irq = <&gpa8 7 GPIO_ACTIVE_HIGH>; + fp-gpio-reset = <&gpp1 1 GPIO_ACTIVE_LOW>; + }; +}; + +&s_ldo15_reg { + regulator-always-on; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-gsa-gsc.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-gsa-gsc.dtsi new file mode 100644 index 000000000000..6cf3daf2bbcc --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-gsa-gsc.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* Setup GSA_GSC proxy driver to talk to GSC over GSA */ +&gsa { + gsa_gsc@0 { + compatible = "google,gs101-gsa-gsc-v1"; + + interrupt-parent = <&gpa0>; + interrupts = <5 0 0>; + gsc,ctdl_ap_irq = <&gpa0 0 0>; // XPCIE0_WAKEN0 + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-ldaf.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-ldaf.dtsi new file mode 100644 index 000000000000..ea6c690b8d77 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-ldaf.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 ldaf(Laser Detection Auto Focus) device tree source + * Copyright 2021 Google LLC. + * + */ + +#include + +&stmvl53l1 { + vio-type = "regulator"; + vio-supply = <&slg51000_ldo1>; + vio-voltage = <0>; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-nfc.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-nfc.dtsi new file mode 100644 index 000000000000..78cf90a63704 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-nfc.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ +#include +#include + +&pinctrl_6 { + nfc_rst: nfc-rst { + samsung,pins = "gph1-5"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + nfc_pidle: nfc-pidle { + samsung,pins = "gph0-5"; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&hsi2c_8 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + status = "okay"; + st21nfc@08 { + compatible = "st,st21nfc"; + reg = <0x08>; + dev-name = "st21nfc"; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_rst &nfc_pidle>; + interrupt-parent = <&gpa9>; + interrupts = <0 0 0>; + reset-gpios = <&gph1 5 0>; + irq-gpios = <&gpa9 1 0>; + clkreq-gpios = <&gpp25 3 0>; + pidle-gpios = <&gph0 5 0>; + st,pidle_active_low; + clock-names = "nfc_ref_clk"; + clocks = <&clock CLKOUT1>; + pmu_clk_pad = <0x3e84>; + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-pmic.dtsi new file mode 100644 index 000000000000..2c0fc6bcea83 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-pmic.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cloudripper-specific PMIC settings + * + * Copyright 2021 Google LLC. + * + */ +#include "gs201-raven-display-constants.dtsi" + +/* Cloudripper uses LDO23M for audio - MIC2 */ +&m_ldo23_reg { + regulator-always-on; + regulator-initial-mode = ; +}; + +/* Cloudripper uses LDO24M for display - R3 Display VDDI */ +&m_ldo24_reg { + regulator-always-on; + regulator-initial-mode = ; +}; + +/* Cheetah, Ravenclaw & Cloudripper use LDO28M for display. */ +&m_ldo28_reg { + regulator-initial-mode = ; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + regulator-ramp-delay = <1200>; + regulator-enable-ramp-delay = <125>; +}; + +/* Cloudripper uses LDO4S for audio - ALC5682 */ +&s_ldo4_reg { + regulator-always-on; + regulator-initial-mode = ; +}; + +/* Display: RAVEN VCI */ +&s_ldo6_reg { + regulator-min-microvolt = ; + regulator-max-microvolt = ; + regulator-always-on; + regulator-initial-mode = ; +}; + +/* Cloudripper uses LDO[26,27]S for EXTRA S5910 VDD[12,18] */ +&s_ldo26_reg { + regulator-initial-mode = ; + regulator-always-on; +}; + +&s_ldo27_reg { + regulator-initial-mode = ; + regulator-always-on; +}; + +/* Cloudripper uses LDO28S for audio - HEADPHONE CODEC (MICVIDD) */ +&s_ldo28_reg { + regulator-initial-mode = ; + regulator-always-on; +}; + +/* ODPM */ +&m_ext4_rail { + schematic-name = "VSYS_PWR_DISPLAY"; + subsys-name = "Display"; +}; + +&s_ext4_rail { + schematic-name = "VSYS_PWR_WLAN_BT"; + subsys-name = "WLAN-BT"; +}; + +&s_ext5_rail { + schematic-name = "VSEN_C5_NC"; + subsys-name = "Spare"; +}; + +&s_ext6_rail { + schematic-name = "VSYS_PWR_MMWAVE"; + subsys-name = "Cellular"; +}; + +/* VSEN_C3 not available: replace to L3M_VDD_AOC_RET*/ +&ch3 { + rail-name = "LDO3M"; +}; + +/* VSEN_C5 not available: replace to VSYS_PWR_MMWAVE */ +&ch14 { + rail-name = "VSEN_C6"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-sbbm.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-sbbm.dtsi new file mode 100644 index 000000000000..fbcf3c0708b8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-sbbm.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SideBand Bit Multiplexer device tree source + * + * Copyright 2021 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +/ { + fragment@sbbmux { + target-path = "/"; + __overlay__ { + sbb_mux: sbb-mux { + compatible = "google,sbb-mux"; + gpios = <&gpp18 0 0>, <&gpp18 1 0>, <&gpp0 2 0>, <&gpp1 0 0>; + gpio_names = "C1_T0__KIBBLE1_TRIG0", + "C1_T1__KIBBLE1_TRIG1", + "C1_T2__KIBBLE1_TRIG2", + "C1_T3__KIBBLE1_TRIG3"; + default_signals = "gp_region_0", "gp_region_1", + "gp_region_2", "gp_region_3"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-thermal.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-thermal.dtsi new file mode 100644 index 000000000000..5f7faa6bba04 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-thermal.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 Cloudripper-specific thermal device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include + +&acpm_mfd_bus1 { + s2mpg13mfd@2f { + gs201_tm1: gs201_spmic_tm1 { + compatible = "google,s2mpg13-spmic-thermal"; + #thermal-sensor-cells = <1>; + adc_chan_en = /bits/ 8 <0x23>; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + skin_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 0>; + trips { + trip_config0: trip-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 1>; + trips { + trip_config1: trip-config1 { + temperature = <56000>; + hysteresis = <1000>; + type = "passive"; + }; + backup_shutdown_sw: backup-shutdown-sw { + temperature = <57000>; + hysteresis = <1000>; + type = "critical"; + }; + backup_shutdown_hw: backup-shutdown-hw { + temperature = <59000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + qi_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 2>; + trips { + trip_config2: trip-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + spmic_therm_3 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 3>; + trips { + trip_config3: trip-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 4>; + trips { + trip_config4: trip-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + disp1_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 5>; + trips { + trip_config5: trip-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + disp2_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 6>; + trips { + trip_config6: trip-config6 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + gnss_tcxo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 7>; + trips { + trip_config7: trip-config7 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-touch.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-touch.dtsi new file mode 100644 index 000000000000..bfb25b875242 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-touch.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Cloudripper device tree source + * + * Copyright 2021 Google Inc. + * + */ + +#include +#include + +/* + * Touch is connected to spi_0, pins: + * CLK=GPP20[0], MOSI=GPP20[1], MISO=GPP20[2], CS=GPP20[3] + * TS_RESET_L = C26 = XAPC_USI11_RTSN_DI = GPP23[2] = <&gpp23 2 0> + * TS_INT_L = AT22 = XEINT_8 = GPA7[0] = <&gpa7 0 0> + * + * DVDD = PP1800_L25M_TSP_DVDD = ??? = VLDO25M = "PP1800_L25M_TSP"? + * AVDD = PP3300_L26M_TS_AVDD = ??? = VLDO26M = "PP3300_L26M_TSP"? + * + * AP2AOC: XHSI1_GPIO2 - GPH1[0] -> XAOC_GPIO13 - gpio_in[87] + * AOC2AP: XAOC_GPIO2 - gpio_in[39] -> XEINT_22 - GPA9[2] + */ + +&tbn { + tbn,aoc2ap_gpio = <&gpa9 2 GPIO_ACTIVE_LOW>; +}; + +&spi_0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus &spi0_cs_func>; +}; + +&spitouch { + status = "ok"; + compatible = "sec,sec_ts"; + + spi-max-frequency = <16000000>; // Whitefin/R3 set to 16000000 + spi-cpol; + spi-cpha; + + sec,spi_cs_gpio = <&gpp20 3 0>; + sec,irq_gpio = <&gpa7 0 0>; + sec,reset_gpio = <&gpp23 2 0>; + sec,firmware_name = "s6sy79x.bin"; + sec,mis_cal_check = <1>; + sec,heatmap_mode = <1>; + + sec,max_coords = <1080 2340>; + + controller-data { + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <1>; + }; +}; + +/* R4 TS_DVDD */ +&s_ldo12_reg { + regulator-always-on; + regulator-initial-mode = ; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-usecases.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-usecases.dtsi new file mode 100644 index 000000000000..b464cd6033b0 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-usecases.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Usecases specific to the gs101 platform + * + * Copyright 2020 Google,LLC + * + */ + +/* system use cases */ +&max77759_chg { + // external boost + max77759,bst-on = <&max777x9_gpio 4 GPIO_ACTIVE_HIGH>; + max77759,bst-sel = <&s2mpg12_gpio 3 GPIO_ACTIVE_HIGH>; + max77759,extbst-ctl = <&max77759_tcpc_gpio 0 GPIO_ACTIVE_HIGH>; + max77759,extbst-mode = <&s2mpg12_gpio 4 GPIO_ACTIVE_HIGH>; + + max77759,ls2-en = <&max20339_gpio 1 GPIO_ACTIVE_HIGH>; + max77759,sw-en = <&max20339_gpio 4 GPIO_ACTIVE_HIGH>; + + // NBC workaround + max77759,lsw1-is_open = <&max20339_gpio 5 GPIO_ACTIVE_HIGH>; + max77759,lsw1-is_closed = <&max20339_gpio 6 GPIO_ACTIVE_HIGH>; + max77759,vin-is_valid = <&max20339_gpio 3 GPIO_ACTIVE_HIGH>; + + //max77759,cpout-en = <&p9xxx_gpio 1 GPIO_ACTIVE_HIGH>; + //max77759,cpout-ctl = <&p9xxx_gpio 3 GPIO_ACTIVE_HIGH>; + + /* b/202526678 handles for WLC_RX->WLC_RX+GPIO */ + max77759,wlc-en = <&gpp0 0 GPIO_ACTIVE_HIGH>; + max77759,wlc-vout_is_invalid = <&p9xxx_gpio 14 GPIO_ACTIVE_HIGH>; + /* b/202526678 add inhibit pin */ + max77759,wlc-vbus_en = <&p9xxx_gpio 15 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-wcharger.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-wcharger.dtsi new file mode 100644 index 000000000000..7f0c7edbbf50 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-wcharger.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2020 Google Inc. + */ + +#include +#include + +/ { + fragment@wlc { + target-path = "/"; + __overlay__ { + google,charger { + google,wlc-power-supply = "wireless"; + }; + }; + }; +}; + +&pinctrl_0 { + /* XIENT_25 P9412 Wireless Charger Interrupt */ + wc_irq: wc_irq { + samsung,pins = "gpa9-5"; /* QI_INT_R */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_4 { + /* XAPC_GPIO0 P9412 Wireless Charger Enable */ + wc_en: wc_en { + samsung,pins = "gpp0-0"; /* QI_EN_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + + p9412@3c { + dev-name = "p9412"; + compatible = "idt,p9412"; + reg = <0x3c>; + status = "ok"; + + idt,has_rtx = <1>; + /* Granvilla GPIO 2~4 */ + idt,gpio_ben = <&s2mpg12_gpio 4 GPIO_ACTIVE_HIGH>; + idt,gpio_switch = <&s2mpg12_gpio 3 GPIO_ACTIVE_HIGH>; + idt,gpio_extben = <&s2mpg12_gpio 2 GPIO_ACTIVE_HIGH>; + + /* WLCDC */ + idt,gpio_dc_switch = <&s2mpg12_gpio 0 GPIO_ACTIVE_HIGH>; + idt,max_vout_mv = <19500>; + idt,has_wlc_dc = <0>; + + idt,gpio_qi_vbus_en = <&gpp0 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wc_irq &wc_en>; + + idt,gpio_qien = <&gpp0 0 GPIO_ACTIVE_HIGH>; + idt,irq_gpio = <&gpa9 5 GPIO_ACTIVE_LOW>; + + p9xxx_gpio: p9xxx_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cloudripper-wlan.dtsi b/arch/arm64/boot/dts/google/gs201-cloudripper-wlan.dtsi new file mode 100644 index 000000000000..38ad175fc5f3 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cloudripper-wlan.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 wlan device tree source + * + * Copyright 2021 Google,LLC + */ + +#include +#include +#include + +&pinctrl_1 { + wlan_host_wake: wlan_host_wake { + samsung,pins = "gpa6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_7 { + cfg_wlanen: cfg_wlanen { + samsung,pins = "gph2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + wlan_dev_wake: wlan_dev_wake { + samsung,pins = "gph2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pcie_1 { + pinctrl-0 = <&pcie1_clkreq &pcie1_perst &cfg_wlanen &wlan_host_wake &wlan_dev_wake>; + use-cache-coherency = "true"; + dma-coherent; + + wlan { + compatible = "android,bcmdhd_wlan"; + wl_reg_on = <&gph2 4 0x1>; /* wlan reg_on pin */ + wl_host_wake = <&gpa6 1 0x1>; /* wlan oob pin */ + wl_dev_wake = <&gph2 5 0x1>; /* wlan dev pin */ + ch-num = <1>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-common-audio.dtsi b/arch/arm64/boot/dts/google/gs201-common-audio.dtsi new file mode 100644 index 000000000000..20554d23af7f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common-audio.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 common audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include "gs201-cs40l26a-config.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-common-bluetooth.dtsi b/arch/arm64/boot/dts/google/gs201-common-bluetooth.dtsi new file mode 100644 index 000000000000..4c36354804d6 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common-bluetooth.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Bluetooth device tree for gs101 boards. + * + * Copyright 2021 Google LLC + * + */ + +#include +#include + +&pinctrl_4 { + bt_reg_on: bt-reg-on { + samsung,pins ="gpp16-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + bt_dev_wake: bt-dev-wake { + samsung,pins ="gpp16-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_1 { + bt_host_wake: bt-host-wake { + samsung,pins ="gpa6-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&serial_18 { + status = "okay"; +}; + +&odm { + btbcm: btbcm { + compatible = "goog,nitrous"; + pinctrl-0 = <&bt_reg_on &bt_dev_wake &bt_host_wake>; + pinctrl-names = "default"; + shutdown-gpios = <&gpp16 2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpa6 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpp16 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-common-gps.dtsi b/arch/arm64/boot/dts/google/gs201-common-gps.dtsi new file mode 100644 index 000000000000..888d370c6921 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common-gps.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 GPS device tree source + * + * Copyright 2021 Google,LLC + */ + +#include +#include +#include + +&spi_5 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus &spi5_cs_func>; + + dma-mode; + dmas = <&pdma0 10 &pdma0 11>; + swap-mode = <1> ; + + bcm4775@0 { + compatible = "ssp,bcm4775"; + reg = <0>; + spi-max-frequency = <26000000>; + spi-cpol; + spi-cpha; + + pinctrl-names = "default"; + pinctrl-0 = + <&gps_host_req &gps_mcu_req &gps_mcu_resp &gps_nstandby>; + + mcu-req-gpios = <&gpp4 3 GPIO_ACTIVE_HIGH>; + nstandby-gpios= <&gph2 3 GPIO_ACTIVE_LOW>; + host-req-gpios = <&gpa6 4 GPIO_ACTIVE_HIGH>; + mcu-resp-gpios = <&gph2 2 GPIO_ACTIVE_HIGH>; + + controller-data { + samsung,spi-feedback-delay = <1>; + samsung,spi-chip-select-mode = <0>; + }; + }; +}; + +&pinctrl_1 { + gps_host_req: gps-host-req { + samsung,pins = "gpa6-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_4 { + gps_mcu_req: gps-mcu-req { + samsung,pins = "gpp4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_7 { + gps_mcu_resp: gps-mcu-resp { + samsung,pins = "gph2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + gps_nstandby: gps-nstandby { + samsung,pins ="gph2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-common-touch.dtsi b/arch/arm64/boot/dts/google/gs201-common-touch.dtsi new file mode 100644 index 000000000000..7b85854230eb --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common-touch.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Cloudripper device tree source + * + * Copyright 2021 Google Inc. + * + */ + +/* Touch is connected to spi_0, pins: + * CLK=GPP20[0], MOSI=GPP20[1], MISO=GPP20[2], CS=GPP20[3] + * TS_RESET_L = C26 = XAPC_USI11_RTSN_DI = GPP23[2] = <&gpp23 2 0> + * TS_INT_L = AT22 = XEINT_8 = GPA7[0] = <&gpa7 0 0> + * + * DVDD = PP1800_L25M_TSP_DVDD = ??? = VLDO25M = "PP1800_L25M_TSP"? + * AVDD = PP3300_L26M_TS_AVDD = ??? = VLDO26M = "PP3300_L26M_TSP"? + * + * AP2AOC: XHSI1_GPIO2 - GPH1[0] -> XAOC_GPIO13 - gpio_in[87] + * AOC2AP: XAOC_GPIO8 - gpio_in[74] -> XEINT_19 - GPA8[7] + */ + +#include + +/ { + fragment@touch_bus_negotiator { + target-path = "/"; + __overlay__ { + tbn: tbn { + compatible = "touch_bus_negotiator"; + + /* Low: AP, High: AOC */ + /* Note: The following GPIO flags are not used by the driver. */ + tbn,ap2aoc_gpio = <&gph1 0 GPIO_ACTIVE_LOW>; + tbn,aoc2ap_gpio = <&gpa8 7 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; + +&pinctrl_1 { + ts_irq: ts-irq { + samsung,pins = "gpa7-0"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + aoc2ap_irq: aoc2ap-irq { + samsung,pins = "gpa8-7"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_5 { + ts_reset: ts-reset { + samsung,pins = "gpp23-2"; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + ts_spi_bus_active: ts_spi_bus_active { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ts_spi_miso_active: ts_spi_miso_active { + samsung,pins = "gpp20-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ts_spi_cs_active: ts_spi_cs_active { + samsung,pins = "gpp20-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ts_spi_bus_sleep: ts_spi_bus_sleep { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + ts_spi_cs_sleep: ts_spi_cs_sleep { + samsung,pins = "gpp20-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&pinctrl_6 { + ap2aoc: ap2aoc-spi-sel { + samsung,pins = "gph1-0"; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi_0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <>; + + spitouch: touchscreen@0 { + status = "disabled"; + reg = <0>; + + pinctrl-names = "ts_active", "ts_suspend"; + pinctrl-0 = <&ts_irq &ts_reset &ap2aoc &aoc2ap_irq + &ts_spi_bus_active &ts_spi_miso_active &ts_spi_cs_active>; + pinctrl-1 = <&ts_spi_bus_sleep &ts_spi_cs_sleep>; + + vdd-supply = <&m_ldo25_reg>; /* VIO 1.8V */ + avdd-supply = <&m_ldo26_reg>; /* AVDD 3.3V */ + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-common-typec.dtsi b/arch/arm64/boot/dts/google/gs201-common-typec.dtsi new file mode 100644 index 000000000000..fa498658909e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common-typec.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, Google LLC + * + * Cloudripper Type-C device tree + */ +#include +#include +#include + +&hsi2c_13{ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max77759tcpc: max77759tcpc@25 { + status = "okay"; + dev-name = "max77759tcpc"; + compatible = "max77759tcpc"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pd_irq>; + interrupt-parent = <&gpa9>; + usbpd,usbpd_int = <&gpa9 7 GPIO_ACTIVE_LOW>; + usb-psy-name = "usb"; + /* Enable when BMS is up */ + chg-psy-name = "gcpm"; + /* Default OVP IC is SLG59H1313C. Config others in overlay if needed. */ + ovp-present; + in-switch-gpio = <&max777x9_gpio 5 GPIO_ACTIVE_LOW>; + quick-ramp-vbus-ovp; + conn = <&conn>; + orientation-switch; + + conn: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + self-powered; + op-sink-microwatt = <2600000>; + new-source-frs-typec-current = ; + usb-role-switch; + slow-charger-loop; + /* + * b/174044466: Extboost can only do ~1A. + * However, max77759 operating in reverse boost + * mode (0xA) can do till 1.5A. + * Since extboost is the primary path, set this + * to 900mA. + */ + source-pdos = ; + sink-pdos = ; + sink-vdos = ; + sink-vdos-v1 = ; + + port { + #address-cells = <1>; + #size-cells = <0>; + mux_notification_src: endpoint@0 { + reg = <0>; + remote-endpoint = <&mux_notification_snk>; + }; + + }; + }; + + port { + #address-cells = <1>; + #size-cells = <0>; + + mux_notification_snk: endpoint@0 { + reg = <0>; + remote-endpoint = <&mux_notification_src>; + }; + }; + + /* EXT_BST_EN exposed as GPIO */ + max77759_tcpc_gpio: max77759_tcpc_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <1>; + }; + }; +}; + +&hsi2c13_bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-pud = ; +}; + +&pinctrl_0 { + usb_pd_irq: usb-pd-irq { + samsung,pins = "gpa9-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +/ { + fragment@typec { + target-path = "/"; + __overlay__ { + google,usbc_port_cooling_dev { + extcon = <&max77759tcpc>; + compatible = "google,usbc_port_cooling_dev"; + google,usb-cd-polling-interval-ms = <5000>; + google,usb-cd-connected-interval-ms = <700>; + google,usb-cd-unplug-interval-sec = <2>; + #cooling-cells = <2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-common.dtsi b/arch/arm64/boot/dts/google/gs201-common.dtsi new file mode 100644 index 000000000000..6e4f9038a182 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-common.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common device tree for all gs201 boards. + * + * Copyright 2021 Google LLC + * + */ +#include +#include "gs201-common-audio.dtsi" +#include "gs201-common-bluetooth.dtsi" +#include "gs201-common-gps.dtsi" +#include "gs201-common-touch.dtsi" +#include "gs201-common-typec.dtsi" +#include "gs201-ldaf.dtsi" +#include "gs201-pmic.dtsi" + +#include + +&serial_0 { + status = "okay"; +}; + +&pinctrl_1 { + key_volup: key-volup { + samsung,pins = "gpa8-5"; /* VOL_UP_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_0 { + key_power: key-power { + samsung,pins = "gpa10-0"; /* PMIC_PWRON_OD_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + key_voldown: key-voldown { + samsung,pins = "gpa10-1"; /* VOL_DN_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + +}; + +&gpio_keys { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown &key_volup &key_power>; + button@1 { + label = "gpio-keys: KEY_VOLUMEDOWN"; + linux,code = <114>; + gpios = <&gpa10 1 0xf>; + wakeup-source; + }; + button@2 { + label = "gpio-keys: KEY_VOLUMEUP"; + linux,code = <115>; + gpios = <&gpa8 5 0xf>; + wakeup-source; + }; +}; + +&udc { + adj-sof-accuracy = <1>; + samsung,no-extra-delay; + usb_host_device_timeout = <0x7ff>; /* Max value */ + extcon = <&max77759tcpc>; + + u1u2_exitfail_quirk; + /* ux_exit_in_px should be defined in MK, LT */ + ux_exit_in_px_quirk; + /* elastic_buf_mode_quirk should be defined in MK */ + elastic_buf_mode_quirk; + xhci_l2_support = <1>; + + usbdrd_dwc3: dwc3 { + dr_mode = "peripheral"; + maximum-speed = "super-speed-plus"; + usb-psy-name = "usb"; + snps,quirk-frame-length-adjustment = <0x20>; + + snps,has-lpm-erratum; + snps,lpm-nyet-threshold = <0>; + + /* + * dis-u2-freeclk-exists-quirk, dis_u2_susphy_quirk are alternative. + * One of them should be selected + */ + snps,dis-u2-freeclk-exists-quirk; + /*snps,dis_u2_susphy_quirk;*/ + + /* http://b/171478776 : disabling U1/U2 speed up NCM tethering by >2x */ + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + xhci_l2_support = <1>; + }; +}; + +&usbdrd_phy0 { + usb_hs_tune:hs_tune { + status = "disabled"; + hs_tune_cnt = <6>; + /* value = */ + hs_tune1 { + tune_name = "tx_pre_emp"; + tune_value = <0x1 0x1>; + }; + + hs_tune2 { + tune_name = "tx_vref"; + tune_value = <0x8 0x8>; + }; + + hs_tune3 { + tune_name = "rx_sqrx"; + tune_value = <0x5 0x5>; + }; + + hs_tune4 { + tune_name = "utmi_clk"; + tune_value = <0x1 0x1>; + }; + + hs_tune5 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune6 { + tune_name = "tx_res"; + tune_value = <0x3 0x3>; + }; + }; + + usb_ss_tune:ss_tune { + status = "disabled"; + ss_tune_cnt = <36>; + /* value = */ + /* 0xffffffff means using default value */ + ss_tune1 { + tune_name = "ssrx_sqhs_th_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune2 { + tune_name = "ssrx_sqhs_th_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune3 { + tune_name = "ssrx_lfps_th"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune4 { + tune_name = "ssrx_adap_coef_sel"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune5 { + tune_name = "ssrx_mf_eq_psel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune6 { + tune_name = "ssrx_mf_eq_psel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune7 { + tune_name = "ssrx_mf_eq_zsel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune8 { + tune_name = "ssrx_mf_eq_zsel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune9 { + tune_name = "ssrx_hf_eq_rsel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune10 { + tune_name = "ssrx_hf_eq_rsel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune11 { + tune_name = "ssrx_hf_eq_csel_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune12 { + tune_name = "ssrx_hf_eq_csel_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune13 { + tune_name = "ssrx_dfe_1tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune14 { + tune_name = "ssrx_dfe_1tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune15 { + tune_name = "ssrx_dfe_2tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune16 { + tune_name = "ssrx_dfe_2tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune17 { + tune_name = "ssrx_dfe_3tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune18 { + tune_name = "ssrx_dfe_3tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune19 { + tune_name = "ssrx_dfe_4tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune20 { + tune_name = "ssrx_dfe_4tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune21 { + tune_name = "ssrx_dfe_5tap_ctrl_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune22 { + tune_name = "ssrx_dfe_5tap_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune23 { + tune_name = "ssrx_term_cal"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune24 { + tune_name = "sstx_amp_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune25 { + tune_name = "sstx_deemp_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune26 { + tune_name = "sstx_pre_shoot_ss"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune27 { + tune_name = "sstx_amp_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune28 { + tune_name = "sstx_deemp_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune29 { + tune_name = "sstx_pre_shoot_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune30 { + tune_name = "sstx_idrv_up"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune31 { + tune_name = "sstx_lfps_idrv_up"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune32 { + tune_name = "sstx_up_term"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune33 { + tune_name = "sstx_dn_term"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune34 { + tune_name = "rext_ovrd"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune35 { + tune_name = "ssrx_cdr_fbb_fine_ctrl_sp"; + tune_value = <0xffffffff 0xffffffff>; + }; + + ss_tune36 { + tune_name = "ssrx_cdr_fbb_fine_ctrl_ssp"; + tune_value = <0xffffffff 0xffffffff>; + }; + }; +}; + +&usbdrd_phy0 { + status = "okay"; + + hs_tune_param = <&usb_hs_tune>; + ss_tune_param = <&usb_ss_tune>; + extcon = <&max77759tcpc>; + + vdd_hsi-supply = <&m_ldo7_reg>; + /* PP0850_L8M_USB: AVDD_PLL_USB, AVDD085_USB20, AVDD085_USBDP */ + /* PP1800_L9M_USB: AVDD18_USB20, AVDD18_USBDP */ + /* PP3000_L10M_USB: AVDD33_USB20 */ + vdd085-supply = <&m_ldo8_reg>; + vdd18-supply = <&m_ldo9_reg>; + vdd30-supply = <&m_ldo10_reg>; +}; + +&pcie_0 { /* pcie ch0 used for the connection with CP */ + status = "okay"; + use-cache-coherency = "true"; + use-msi = "true"; + use-sicd = "true"; + use-ia = "true"; + use-l1ss = "true"; + phy-power-off = "false"; + use-pcieon-sleep = "true"; + use-sysmmu = "true"; + use-secure-atu = "true"; + ep-device-type = ; + vreg1-supply = <&m_ldo16_reg>; /* PP0850_L16M_PCIE0: AVDD085_PCIE_GEN4_0 */ + vreg2-supply = <&m_ldo18_reg>; /* PP1800_L18M_PCIE0: AVDD18_PCIE_GEN4_0 */ +}; + +&sysmmu_hsi1 { + use-map-once = "true"; + status = "okay"; +}; + +&pcie_1 { /* pcie ch1 used for the connection with WiFi */ + status = "okay"; + num-lanes = <1>; + use-sicd = "true"; + use-ia = "true"; + use-l1ss = "true"; + use-sysmmu = "true"; + max-link-speed = ; + ep-device-type = ; + pcie,wlan-gpio = <&gph2 4 0x1 /* WLAN_EN */ >; /* WLAN_REG_ON */ + vreg1-supply = <&s_ldo3_reg>; /* PP0850_L3S_PCIE1: AVDD085_PCIE_GEN4_1 */ + vreg2-supply = <&s_ldo18_reg>; /* PP1800_L18S_PCIE1: AVDD18_PCIE_GEN4_1 */ +}; + +&aoc { + sensor_1v8-supply = <&s_ldo7_reg>; + sensor_3v3-supply = <&s_ldo5_reg>; + sensor_power_list = "sensor_1v8", "sensor_3v3"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cp-s5300-sit.dtsi b/arch/arm64/boot/dts/google/gs201-cp-s5300-sit.dtsi new file mode 100644 index 000000000000..4d1281fb4419 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cp-s5300-sit.dtsi @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019-2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include + +/ { + fragment@modemif { + target-path = "/"; + __overlay__ { + #address-cells = <2>; + #size-cells = <1>; + + /* Modem interface information */ + cpif { + compatible = "samsung,exynos-cp"; + status = "okay"; + + pci_ch_num = <0>; + pci_db_addr = <0x14E60000>; + cpboot_spi_bus_num = <9>; + + /* */ + mif,name = "s5300"; + mif,cp_num = <0>; + mif,modem_type = ; + mif,protocol = ; + mif,ipc_version = ; + mif,link_type = ; + mif,link_name = "PCIE"; + mif,link_attrs = <( + LINK_ATTR_XMIT_BTDLR_PCIE | + LINK_ATTR_XMIT_BTDLR | + LINK_ATTR_DUMP_ALIGNED | + LINK_ATTR_BOOT_ALIGNED | + LINK_ATTR_MEM_DUMP | + LINK_ATTR_MEM_BOOT | + LINK_ATTR_DPRAM_MAGIC)>; + mif,interrupt_types = ; + mif,capability_check = <1>; + + /* Mailbox interrupt number from AP to CP */ + mif,int_ap2cp_msg = <0>; + mif,int_ap2cp_wakeup = <1>; + mif,int_ap2cp_status = <2>; + mif,int_ap2cp_active = <3>; + mif,int_ap2cp_lcd_status = <4>; + mif,int_ap2cp_pcie_link_ack = <14>; + mif,int_ap2cp_uart_noti = <15>; + + /* Mailbox interrupt number from CP to AP */ + mif,irq_cp2ap_msg = <0>; + mif,irq_cp2ap_status = <2>; + mif,irq_cp2ap_active = <3>; + mif,irq_cp2ap_wakelock = <8>; + mif,irq_cp2ap_ratmode = <9>; + + /* Legacy Buffers (FMT, RAW) */ + legacy_fmt_head_tail_offset = <0x8>; + legacy_fmt_buffer_offset = <0x1000>; + legacy_fmt_txq_size = <0x1000>; + legacy_fmt_rxq_size = <0x1000>; + legacy_raw_head_tail_offset = <0x18>; + legacy_raw_buffer_offset = <0x3000>; + legacy_raw_txq_size = <0x1FD000>; + legacy_raw_rxq_size = <0x200000>; + legacy_raw_rx_buffer_cached = <0>; + + offset_srinfo_offset = <0x64>; + offset_capability_offset = <0x70>; + + srinfo_offset = <0x300>; + srinfo_size = <0x400>; + capability_offset = <0xA0>; + + /* capability value */ + ap_capability_0 = <0x0>; + ap_capability_1 = <0x0>; + + /* + * Control messages containing two elements + * + * + * + */ + ap2cp_msg = ; + cp2ap_msg = ; + ap2cp_united_status = ; + cp2ap_united_status = ; + ap2cp_kerneltime = ; + ap2cp_handover_block_info = ; + + /* Status bit info + * for mbx_ap2cp_united_status + */ + sbi_lcd_status_mask = <0x1>; + sbi_lcd_status_pos = <27>; + sbi_crash_type_mask = <0xf>; + sbi_crash_type_pos = <23>; + sbi_uart_noti_mask = <0x1>; + sbi_uart_noti_pos = <16>; + sbi_ds_det_mask = <0x3>; + sbi_ds_det_pos = <14>; + sbi_pda_active_mask = <0x1>; + sbi_pda_active_pos = <5>; + sbi_ap_status_mask = <0xf>; + sbi_ap_status_pos = <1>; + + /* Status bit info + * for mbx_cp2ap_united_status + */ + sbi_cp_rat_mode_mask = <0x3f>; + sbi_cp_rat_mode_pos = <26>; + sbi_cp2ap_wakelock_mask = <0x1>; + sbi_cp2ap_wakelock_pos = <6>; + sbi_lte_active_mask = <0x1>; + sbi_lte_active_pos = <5>; + sbi_cp_status_mask = <0xf>; + sbi_cp_status_pos = <1>; + + /* Status bit info for mbx_ap2cp_kerneltime */ + sbi_ap2cp_kerneltime_sec_mask = <0xfff>; + sbi_ap2cp_kerneltime_sec_pos = <20>; + sbi_ap2cp_kerneltime_usec_mask = <0xfffff>; + sbi_ap2cp_kerneltime_usec_pos = <0>; + + /* Packet processor */ + pktproc_use_36bit_addr = <0>; + pktproc_cp_base = <0x0 0x20000000>; + + pktproc_dl_support = <1>; + pktproc_dl_version = <2>; + + pktproc_dl_info_rgn_offset = <0x00000000>; + pktproc_dl_info_rgn_size = <0x00001000>; + pktproc_dl_desc_rgn_offset = <0x00001000>; + pktproc_dl_desc_rgn_size = <0x000FF000>; + pktproc_dl_buff_rgn_offset = <0x00100000>; + pktproc_dl_buff_rgn_size = <0x01B00000>; + /* Size of data region is defined + * by reserved mem size + */ + + pktproc_dl_info_rgn_cached = <1>; + pktproc_dl_desc_rgn_cached = <1>; + pktproc_dl_buff_rgn_cached = <1>; + + /* 0:ringbuf mode, 1:sktbuf mode */ + pktproc_dl_desc_mode = <1>; + pktproc_dl_num_queue = <4>; + pktproc_dl_use_exclusive_irq = <1>; + /* H/W IO cache coherency */ + pktproc_dl_use_hw_iocc = <1>; + pktproc_dl_max_packet_size = <1584>; + pktproc_dl_use_dedicated_baaw = <0>; + + /* Packet processor for UL */ + pktproc_ul_support = <1>; + pktproc_ul_info_rgn_offset = <0x01C00000>; + pktproc_ul_info_rgn_size = <0x00001000>; + pktproc_ul_desc_rgn_offset = <0x01C01000>; + pktproc_ul_desc_rgn_size = <0x0008F000>; + pktproc_ul_buff_rgn_offset = <0x01C90000>; + pktproc_ul_buff_rgn_size = <0x00370000>; + pktproc_ul_padding_required = <1>; /* for s5123 EVT1 only */ + pktproc_ul_num_queue = <2>; + pktproc_ul_max_packet_size = <2048>; + pktproc_ul_hiprio_ack_only = <1>; + pktproc_ul_info_rgn_cached = <1>; + pktproc_ul_desc_rgn_cached = <1>; + pktproc_ul_buff_rgn_cached = <1>; + pktproc_ul_use_hw_iocc = <1>; /* H/W IO cache coherency */ + + /* TPMON: CP throughput monitor */ + cpif_tpmon { + trigger_msec_min = <500>; + trigger_msec_max = <1500>; + + monitor_interval_msec = <1000>; + monitor_hold_msec = <3000>; + monitor_stop_mbps = <15>; + + boost_hold_msec = <6000>; + + tpmon_rps { + boost_name = "RPS"; + target = ; + extra_idx = <0>; + level = <0x03 0x30 0xC0>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <500 1600>; + unboost_threshold_mbps = <200 600>; + }; + }; + + tpmon_gro_flush_time { + boost_name = "GRO"; + target = ; + extra_idx = <0>; + level = <250000 2000000>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <100>; + unboost_threshold_mbps = <50>; + }; + }; + + tpmon_mif { + boost_name = "MIF"; + target = ; + extra_idx = <0>; + level = <0 1014000>; + + boost0 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <1100>; + unboost_threshold_mbps = <400>; + }; + }; + + tpmon_cpu_cl0 { + boost_name = "CL0"; + target = ; + extra_idx = <0>; + level = <0 1066000 1274000>; + + boost0 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <100 300>; + unboost_threshold_mbps = <40 120>; + }; + }; + + tpmon_cpu_cl1 { + boost_name = "CL1"; + target = ; + extra_idx = <4>; + level = <0 799000>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <2000>; + unboost_threshold_mbps = <800>; + }; + }; + + tpmon_pcie_low_power { + boost_name = "PCIE_LP"; + target = ; + extra_idx = <0>; + level = <1 0>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <3000>; + unboost_threshold_mbps = <1200>; + }; + }; + + tpmon_irq_affinity_0 { + boost_name = "IRQ_0"; + target = ; + extra_idx = <3>; + level = <0x0C 0x30>; + + boost0 { + enable = <1>; + measure = ; + proto = ; + boost_threshold = <500>; + unboost_threshold_mbps = <200>; + }; + }; + + tpmon_irq_dit { + boost_name = "IRQ_DIT"; + target = ; + extra_idx = <0>; + level = <0x04 0x20>; + + boost0 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <250>; + unboost_threshold_mbps = <100>; + }; + + boost1 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <6000>; + unboost_threshold_mbps = <2000>; + }; + + boost2 { + enable = <0>; + measure = ; + proto = ; + boost_threshold = <7000>; + unboost_threshold_mbps = <2000>; + }; + }; + }; + + /* IO devices */ + iodevs { + io_device_0 { + iod,name = "umts_ipc"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <2>; + }; + io_device_1 { + iod,name = "umts_rfs0"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_2 { + iod,name = "umts_router"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_3 { + iod,name = "umts_dm0"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(IO_ATTR_STATE_RESET_NOTI)>; + }; + io_device_4 { + iod,name = "umts_loopback"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_5 { + iod,name = "rmnet"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <30>; + }; + io_device_6 { + iod,name = "umts_dummy"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_7 { + iod,name = "multipdp"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_8 { + iod,name = "umts_boot0"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(IO_ATTR_NO_CHECK_MAXQ)>; + }; + io_device_9 { + iod,name = "umts_rcs0"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_10 { + iod,name = "umts_rcs1"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_11 { + iod,name = "umts_wfc0"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_12 { + iod,name = "umts_wfc1"; + iod,ch = ; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + io_device_13 { + iod,name = "oem_ipc"; + iod,ch = <129>; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(IO_ATTR_MULTI_CH)>; + iod,ch_count = <8>; + }; + io_device_14 { + iod,name = "oem_test"; + iod,ch = <137>; + iod,format = ; + iod,io_type = ; + iod,link_type = ; + iod,attrs = <(0x0)>; + }; + }; + }; + + /* Shared memory information*/ + cp_shmem { + compatible = "samsung,exynos-cp-shmem"; + + memory-region = + <&cp_rmem>, + <&cp_msi_rmem>, + <&cp_rmem_1>, + <&cp_aoc_rmem>; + + cp_num = <0>; + use_mem_map_on_cp = <0>; + + regions { + ipc { + region,name = "IPC"; + region,index = ; + region,rmem = <0>; + region,offset = <0x00000000>; + region,size = <0x00800000>; + region,cached = <1>; + }; + msi { + region,name = "MSI"; + region,index = ; + region,rmem = <1>; + region,offset = <0x00000000>; + region,size = <0x00001000>; + region,cached = <0>; + }; + pktproc { + region,name = "PKTPROC"; + region,index = ; + region,rmem = <2>; + region,offset = <0x00000000>; + region,size = <0x01C00000>; + /* Cached info is defined by pktproc itself */ + }; + pktproc_ul { + region,name = "PKTPROC_UL"; + region,index = ; + region,rmem = <2>; + region,offset = <0x01C00000>; + region,size = <0x00400000>; + /* Cached info is defined by pktproc_ul itself */ + }; + vss_aoc { + region,name = "VSS_AOC"; + region,index = ; + region,rmem = <3>; + region,offset = <0x00000000>; + region,size = <0x00003000>; + region,cached = <0>; + }; + }; + }; + }; + }; +}; + +&spi9_cs_func { + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; +}; + +&spi_9 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus &spi9_cs_func>; + cpboot_spi@0 { + compatible = "samsung,exynos-cp-spi"; + reg = <0x0>; + spi-max-frequency = <2150000>; + controller-data { + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cpu.dtsi b/arch/arm64/boot/dts/google/gs201-cpu.dtsi new file mode 100644 index 000000000000..83fdd15768c7 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cpu.dtsi @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC CPU device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * GS201 SoC CPU device nodes are listed in this file. + * GS201 based board files should include this file. + * + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + #define CPU_CL0 "0-3" + #define CPU_CL1 "4-5" + #define CPU_CL2 "6-7" + #define CPU_ALL "0-7" + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu1: cpu@0100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu2: cpu@0200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0200>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu3: cpu@0300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0300>; + enable-method = "psci"; + cpu-idle-states = <&ANANKE_CPU_SLEEP>; + capacity-dmips-mhz = <250>; + dynamic-power-coefficient = <89>; + }; + cpu4: cpu@0400 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0400>; + enable-method = "psci"; + cpu-idle-states = <&HERCULES_CPU_SLEEP>; + capacity-dmips-mhz = <927>; + dynamic-power-coefficient = <513>; + }; + cpu5: cpu@0500 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0500>; + enable-method = "psci"; + cpu-idle-states = <&HERCULES_CPU_SLEEP>; + capacity-dmips-mhz = <927>; + dynamic-power-coefficient = <513>; + }; + cpu6: cpu@0600 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0600>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <757>; + }; + cpu7: cpu@0700 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0700>; + enable-method = "psci"; + cpu-idle-states = <&HERA_CPU_SLEEP>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <757>; + }; + + idle-states { + entry-method = "arm,psci"; + + ANANKE_CPU_SLEEP: ananke-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <70>; + exit-latency-us = <160>; + min-residency-us = <2000>; + status = "okay"; + }; + + HERCULES_CPU_SLEEP: hercules-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <150>; + exit-latency-us = <190>; + min-residency-us = <2500>; + status = "okay"; + }; + + HERA_CPU_SLEEP: hera-cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <235>; + exit-latency-us = <220>; + min-residency-us = <3500>; + status = "okay"; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + exynos-cpuphp { + compatible = "samsung,exynos-cpuhp"; + status = "okay"; + }; + + cpupm { + #define POWERMODE_TYPE_CLUSTER 0 + #define POWERMODE_TYPE_SYSTEM 1 + + compatible = "samsung,exynos-cpupm"; + status = "okay"; + + cpd_cl0 { + device_type = "cpupm"; + target-residency = <10000>; + type = ; + cal-id = <0>; + siblings = CPU_CL0; + }; + + cpd_cl1 { + device_type = "cpupm"; + target-residency = <10000>; + type = ; + cal-id = <1>; + siblings = CPU_CL1; + entry-allowed = CPU_CL1; + }; + + cpd_cl2 { + device_type = "cpupm"; + target-residency = <10000>; + type = ; + cal-id = <2>; + siblings = CPU_CL2; + entry-allowed = CPU_CL2; + }; + + sicd { + device_type = "cpupm"; + target-residency = <10000>; + type = ; + siblings = CPU_ALL; + entry-allowed = CPU_ALL; + }; + + wakeup-mask { + wakeup-masks { + wakeup-mask { + mask-reg-offset = <0x3944>; + stat-reg-offset = <0x3950>; + mask = <0x0ff00000>; + }; + wakeup-mask2 { + mask-reg-offset = <0x3964>; + stat-reg-offset = <0x3970>; + mask = <0x00>; + }; + }; + + eint-wakeup-masks { + eint-wakeup-mask { + mask-reg-offset = <0x3a80>; + }; + eint-wakeup-mask2 { + mask-reg-offset = <0x3a84>; + }; + eint-wakeup-mask3 { + mask-reg-offset = <0x3a88>; + }; + }; + }; + + idle-ip { + extern-idle-ip = + "dbg_core"; + }; + }; + + exynos-acme { + compatible = "samsung,exynos-acme"; + status = "okay"; + + cpufreq_domain0: domain@0 { + sibling-cpus = CPU_CL0; + cal-id = ; + dm-type = ; + + min-freq = <300000>; + max-freq = <1803000>; + resume-freq = <1197000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <2>; + tz-cooling-name = "LITTLE"; + max-dfs-count= <0>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&lit_mif_perf>; + }; + }; + + cpufreq_domain1: domain@1 { + sibling-cpus = CPU_CL1; + cal-id = ; + dm-type = ; + + min-freq = <400000>; + max-freq = <2348000>; + resume-freq = <1491000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <1>; + tz-cooling-name = "MID"; + max-dfs-count = <2>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&med_ank_perf>; + }; + }; + + cpufreq_domain2: domain@2 { + sibling-cpus = CPU_CL2; + cal-id = ; + dm-type = ; + + min-freq = <500000>; + max-freq = <2850000>; + resume-freq = <1826000>; + + #cooling-cells = <2>; /* min followed by max */ + ect-coeff-index = <0>; + tz-cooling-name = "BIG"; + max-dfs-count = <2>; + skip-boot-pmqos; + use-em-coeff; + + dm-constraints { + list = <&big_ank_perf>; + }; + }; + }; + + dm-tables { + lit_mif_perf: dm-table@0000 { + }; + med_ank_perf: dm-table@0003 { + const-type = ; + dm-constraint = ; + driver-cal-id = ; + constraint-cal-id = ; + + /* CL1 CL0 */ + table = < 2348000 1328000 + 2253000 1197000 + 2130000 1098000 + 1999000 1098000 + 1836000 1098000 + 1663000 1098000 + 1491000 930000 + 1328000 930000 + 1197000 738000 + 1024000 738000 + 910000 574000 + 799000 574000 + 696000 574000 + 553000 574000 + 400000 300000 >; + }; + big_ank_perf: dm-table@0006 { + const-type = ; + dm-constraint = ; + driver-cal-id = ; + constraint-cal-id = ; + + /* CL2 CL0 */ + table = < 2850000 1401000 + 2802000 1401000 + 2704000 1401000 + 2630000 1401000 + 2507000 1401000 + 2401000 1401000 + 2252000 1328000 + 2188000 1328000 + 2048000 1197000 + 1826000 1098000 + 1745000 1098000 + 1582000 930000 + 1426000 930000 + 1277000 738000 + 1106000 738000 + 984000 738000 + 851000 574000 + 500000 300000 >; + }; + }; + + pixel_em_table: pixel-em { + compatible = "google,pixel-em"; + profiles = + "cam1 + cpu0 { + 300000 38 6 + 574000 47 11 + 738000 71 14 + 930000 92 29 + 1098000 93 60 + 1197000 103 73 + 1328000 104 89 + 1401000 134 106 + 1598000 141 138 + 1704000 157 167 + 1803000 166 195 + } + cpu4 { + 400000 165 73 + 553000 178 99 + 696000 191 126 + 799000 207 146 + 910000 223 172 + 1024000 240 197 + 1197000 287 237 + 1328000 334 274 + 1491000 381 322 + 1663000 427 382 + 1836000 474 436 + 1999000 521 519 + 2130000 568 596 + 2253000 615 689 + 2348000 662 789 + } + cpu6 { + 500000 193 160 + 851000 274 245 + 984000 289 282 + 1106000 305 317 + 1277000 307 381 + 1426000 340 435 + 1582000 379 481 + 1745000 453 549 + 1826000 477 588 + 2048000 538 699 + 2188000 599 804 + 2252000 659 855 + 2401000 720 1013 + 2507000 781 1132 + 2630000 842 1313 + 2704000 902 1451 + 2802000 963 1685 + 2850000 1024 1816 + } + ", + "cam2 + cpu0 { + 300000 38 6 + 574000 47 11 + 738000 61 14 + 930000 77 29 + 1098000 92 60 + 1197000 101 73 + 1328000 114 89 + 1401000 121 106 + 1598000 141 138 + 1704000 153 167 + 1803000 166 195 + } + cpu4 { + 400000 165 73 + 553000 178 99 + 696000 201 126 + 799000 217 146 + 910000 238 172 + 1024000 285 197 + 1197000 327 237 + 1328000 357 274 + 1491000 380 322 + 1663000 419 382 + 1836000 460 436 + 1999000 521 519 + 2130000 568 596 + 2253000 615 689 + 2348000 662 789 + } + cpu6 { + 500000 193 160 + 851000 267 245 + 984000 295 282 + 1106000 320 317 + 1277000 357 381 + 1426000 390 435 + 1582000 419 481 + 1745000 471 549 + 1826000 497 588 + 2048000 568 699 + 2188000 620 804 + 2252000 650 855 + 2401000 720 1013 + 2507000 781 1132 + 2630000 842 1313 + 2704000 902 1451 + 2802000 963 1685 + 2850000 1024 1816 + } + ", + "ui + cpu0 { + 300000 60 16 + 574000 114 39 + 738000 147 56 + 930000 185 80 + 1098000 218 106 + 1197000 238 125 + 1328000 264 151 + 1401000 278 166 + 1598000 317 220 + 1704000 338 253 + 1803000 358 294 + } + cpu4 { + 400000 146 70 + 553000 202 107 + 696000 254 151 + 799000 292 186 + 910000 333 228 + 1024000 374 275 + 1197000 437 361 + 1328000 485 440 + 1491000 545 539 + 1663000 608 673 + 1836000 671 837 + 1999000 730 1022 + 2130000 778 1212 + 2253000 823 1403 + 2348000 858 1578 + } + cpu6 { + 500000 180 125 + 851000 306 266 + 984000 354 332 + 1106000 397 410 + 1277000 459 516 + 1426000 512 626 + 1582000 568 753 + 1745000 627 925 + 1826000 656 1012 + 2048000 736 1289 + 2188000 786 1494 + 2252000 809 1620 + 2401000 863 1883 + 2507000 901 2116 + 2630000 945 2435 + 2704000 972 2674 + 2802000 1007 3054 + 2850000 1024 3269 + } + "; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-cs40l26a-config.dtsi b/arch/arm64/boot/dts/google/gs201-cs40l26a-config.dtsi new file mode 100644 index 000000000000..6bf5a728df4a --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-cs40l26a-config.dtsi @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 cs40l26 device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * +*/ + +#include +#include + +&dai_be_haptic_rx { + dai_be_haptic_rx_codec: codec { + sound-dai = <&cs40l26_codec 0>; + }; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs40l26_codec { + comp = <&cs40l26_codec>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + hapt_amp_irq: hapt-amp-irq { + samsung,pins = "gpa8-1"; /* XEINT_13 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + hapt_amp_rst: hapt-amp-rst { + samsung,pins = "gpp24-3"; /* XAPC_USI15_CTSn_CSn */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hapt_amp_trig: hapt-amp-trig { + samsung,pins = "gpp24-2"; /* XAPC_USI15_RTSn_DI */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&hsi2c_8 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + + clock-frequency = <400000>; + + cs40l26a_haptics: cs40l26a@43 { + compatible = "cirrus,cs40l26a"; + reg = <0x43>; + dev-name = "cs40l26a"; /* sysfs folder name */ + input-device-name = "cs40l26_input"; /* input device name */ + + pinctrl-names = "default"; + pinctrl-0 = <&hapt_amp_irq &hapt_amp_rst &hapt_amp_trig>; + + interrupt-parent = <&gpa8>; + interrupts = <1 0 0>; + + reset-gpios = <&gpp24 3 0>; + + cirrus,bst-dcm-en = <0>; + cirrus,pwle-zero-cross-en; + cirrus,vpbr-enable; + cirrus,vpbr-thld-mv = <3000>; /* 3.0V */ + cirrus,bst-expl-mode-disable; + cirrus,bst-ipk-microamp = <2500000>; /* 2.5A */ + cirrus,boost-ctl-microvolt = <11000000>;/* 11V */ + cirrus,f0-default = <0x244000>; /* 145 Hz */ + cirrus,redc-default = <0x68000>; /* 13 Ohm */ + + status = "okay"; + + cs40l26_codec: cs40l26_codec@snd { + #sound-dai-cells = <1>; + compatible = "cs40l26-codec"; + status = "okay"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-debug.dtsi b/arch/arm64/boot/dts/google/gs201-debug.dtsi new file mode 100644 index 000000000000..ddf1ce8ea384 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-debug.dtsi @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * debug device tree source code for gs201 SoC + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include "gs201-dpm.dtsi" +#include "gs201-ppmu.dtsi" +/ { + dss: dss { + compatible = "google,debug-snapshot"; + freq_names = "LIT", "MID", "BIG", "INT", "MIF", "ISP", + "DISP", "INTCAM", "TPU", "TNR", "MFC", + "BO"; + memory-region = <&header>, <&log_kevents>, <&log_bcm>, <&log_s2d>, + <&log_arrdumpreset>, <&log_arrdumppanic>, + <&log_slcdump>, <&log_preslcdump>, + <&log_itmon>; + panic-action = ; + }; + + hardlockup-debugger { + compatible = "google,hardlockup-debug"; + use_multistage_wdt_irq = <830>; /* IRQ_WDT_CLUSTER1_MISC + 32 */ + }; + + hardlockup-watchdog { + compatible = "google,hardlockup-watchdog"; + sampling_time = <4>; + opportunity_count = <3>; + panic = <1>; + }; + + dss-built { + compatible = "google,debug-snapshot-built"; + memory-region = <&header>; + }; + + dss-qdump { + compatible = "google,debug-snapshot-qdump"; + }; + + dss-sfrdump { + compatible = "google,debug-snapshot-sfrdump"; + /* + * -----------<< Example >>------------------- + * dump-info { + * #address-cells = <1>; + * #size-cells = <1>; + * + * gic-setenable { + * reg = <0x11f01100 0x100>; + * }; + * gic-setpend { + * reg = <0x11f01200 0x100>; + * }; + * gic-setactive { + * reg = <0x11f01300 0x100>; + * }; + *}; + */ + }; + + dss-debug-kinfo { + compatible = "google,debug-snapshot-debug-kinfo"; + memory-region = <&debug_kinfo_reserved>; + }; + + exynos-debug-test { + compatible = "google,exynos-debug-test"; + ps_hold_control_offset = <0x3e9c>; + nr_cpu = <0x8>; + nr_little_cpu = <0x4>; + nr_mid_cpu = <0x2>; + nr_big_cpu = <0x2>; + little_cpu_start = <0x0>; + mid_cpu_start = <0x4>; + big_cpu_start = <0x6>; + }; + + keydebug { + compatible = "keydebug"; + key_down_delay = <6000>; + keys_down = <116 115>; + dbg_fn_delay = <2000>; + }; + + debug-kinfo { + compatible = "google,debug-kinfo"; + memory-region = <&debug_kinfo_reserved>; + }; + + boot-metrics { + compatible = "google,boot-metrics"; + + reg = <0x0 0x02038000 0x00001000>; + reg-names = "ns_sram_base"; + offset = <0x880>; + }; + + gs201-itmon { + compatible = "google,gs201-itmon"; + interrupts = + , + , + , + , + , + , + , + ; + panic_count = <0>; + err_fatal = ; + err_drex_tmout = ; + err_ip = ; + err_cpu = ; + err_unhandled = ; + }; + + coresight@2b000000 { + compatible = "google,exynos-coresight"; + dbg_base = <0x2b810000>, <0x2b910000>, <0x2ba10000>, <0x2bb10000>, + <0x2bc10000>, <0x2bd10000>, <0x2be10000>, <0x2bf10000>; + cti_base = <0x2b820000>, <0x2b920000>, <0x2ba20000>, <0x2bb20000>, + <0x2bc20000>, <0x2bd20000>, <0x2be20000>, <0x2bf20000>; + pmu_base = <0x2b830000>, <0x2b930000>, <0x2ba30000>, <0x2bb30000>, + <0x2bc30000>, <0x2bd30000>, <0x2be30000>, <0x2bf30000>; + gpr_base = <0x2b001000>; + dbgack-mask = <0xff00000>; + halt = <1>; + retention = <1>; + }; + + ecc-handler { + compatible = "google,exynos-ecc-handler"; + interrupts = , /* DSU */ + , /* CORE0 */ + , /* CORE1 */ + , /* CORE2 */ + , /* CORE3 */ + , /* CORE4 */ + , /* CORE5 */ + , /* CORE6 */ + ; /* CORE7 */ + + interrupt-names ="DSU, L3 DATA or TAG or Snoop filter RAM", + "CORE0, L1,L2 DATA or TAG RAM", + "CORE1, L1,L2 DATA or TAG RAM", + "CORE2, L1,L2 DATA or TAG RAM", + "CORE3, L1,L2 DATA or TAG RAM", + "CORE4, L1,L2 DATA or TAG RAM", + "CORE5, L1,L2 DATA or TAG RAM", + "CORE6, L1,L2 DATA or TAG RAM", + "CORE7, L1,L2 DATA or TAG RAM"; + }; + + exynos-etm { + compatible = "google,exynos-etm"; + cs_base = <0x2b000000>; + boot-start = <0>; + funnel-num = <3>; + etf-num = <2>; + trex-num = <4>; + /* funnel-port = <(funnel num) (port num)>; */ + etm0 { + device_type = "etm"; + offset = <0x840000>; + funnel-port = <0 0>; + }; + etm1 { + device_type = "etm"; + offset = <0x940000>; + funnel-port = <0 1>; + }; + etm2 { + device_type = "etm"; + offset = <0xa40000>; + funnel-port = <1 0>; + }; + etm3 { + device_type = "etm"; + offset = <0xb40000>; + funnel-port = <1 1>; + }; + etm4 { + device_type = "etm"; + offset = <0xc40000>; + funnel-port = <1 2>; + }; + etm5 { + device_type = "etm"; + offset = <0xd40000>; + funnel-port = <1 3>; + }; + etm6 { + device_type = "etm"; + offset = <0xe40000>; + funnel-port = <0 2>; + }; + etm7 { + device_type = "etm"; + offset = <0xf40000>; + funnel-port = <0 3>; + }; + etf0@4000 { + device_type = "etf"; + offset = <0x4000>; + funnel-port = <2 0>; + }; + etf1@5000 { + device_type = "etf"; + offset = <0x5000>; + funnel-port = <2 1>; + }; + funnel0@7000 { + device_type = "funnel"; + offset = <0x7000>; + }; + funnel1@8000 { + device_type = "funnel"; + offset = <0x8000>; + }; + funnel2@9000 { + device_type = "funnel"; + offset = <0x9000>; + }; + etr@A000 { + device_type = "etr"; + sfr_base = <0x2b00c000 0x100>; + qch-offset = <0x2c>; + offset = <0xA000>; + buf-size = <0x100000>; + }; + bdu@10000 { + device_type = "bdu"; + offset = <0x10000>; + funnel-port = <1 5>; + }; + bdu_etf@11000 { + device_type = "bdu_etf"; + offset = <0x11000>; + }; + trex0 { + device_type = "trex"; + mux_ctrl = <0x66>; + dbg_trace_addr = <0x1ea83010>; + dbg_trace_val = <5>; + }; + trex1 { + device_type = "trex"; + mux_ctrl = <0x77>; + dbg_trace_addr = <0x1f603010>; + dbg_trace_val = <26>; + }; + trex2 { + device_type = "trex"; + mux_ctrl = <0x88>; + dbg_trace_addr = <0x204e3010>; + dbg_trace_val = <8>; + }; + trex3 { + device_type = "trex"; + mux_ctrl = <0x55>; + dbg_trace_addr = <0x1e503010>; + dbg_trace_val = <8>; + }; + }; + + etm0: etm@2b840000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2b840000 0x1000>; + cpu = <&cpu0>; + + coresight-name = "coresight-etm0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + }; + + etm1: etm@2b940000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2b940000 0x1000>; + cpu = <&cpu1>; + + coresight-name = "coresight-etm1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + }; + + etm2: etm@2ba40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2ba40000 0x1000>; + cpu = <&cpu2>; + + coresight-name = "coresight-etm2"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + }; + + etm3: etm@2bb40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bb40000 0x1000>; + cpu = <&cpu3>; + + coresight-name = "coresight-etm3"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + }; + + etm4: etm@2bc40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bc40000 0x1000>; + cpu = <&cpu4>; + + coresight-name = "coresight-etm4"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm4_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + }; + + etm5: etm@2bd40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bd40000 0x1000>; + cpu = <&cpu5>; + + coresight-name = "coresight-etm5"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm5_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + }; + + etm6: etm@2be40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2be40000 0x1000>; + cpu = <&cpu6>; + + coresight-name = "coresight-etm6"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm6_out_port: endpoint { + remote-endpoint = <&funnel0_in_port2>; + }; + }; + }; + }; + + etm7: etm@2bf40000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb95d>; + + reg = <0 0x2bf40000 0x1000>; + cpu = <&cpu7>; + + coresight-name = "coresight-etm7"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + arm,coresight-loses-context-with-cpu; + + out-ports { + port { + etm7_out_port: endpoint { + remote-endpoint = <&funnel0_in_port3>; + }; + }; + }; + }; + + funnel0: funnel@2b007000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b007000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel0_out_port: endpoint { + remote-endpoint = <&etf0_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel0_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel0_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel0_in_port2: endpoint { + remote-endpoint = <&etm6_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel0_in_port3: endpoint { + remote-endpoint = <&etm7_out_port>; + }; + }; + }; + }; + + funnel1: funnel@2b008000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b008000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel1_out_port: endpoint { + remote-endpoint = <&etf1_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel1_in_port0: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel1_in_port1: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + + port@2 { + reg = <2>; + funnel1_in_port2: endpoint { + remote-endpoint = <&etm4_out_port>; + }; + }; + + port@3 { + reg = <3>; + funnel1_in_port3: endpoint { + remote-endpoint = <&etm5_out_port>; + }; + }; + }; + }; + + funnel2: funnel@2b009000 { + compatible = "arm,primecell"; + arm,primecell-periphid = <0x000bb908>; + + reg = <0 0x2b009000 0x1000>; + reg-names = "funnel-base"; + + coresight-name = "coresight-funnel2"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + funnel2_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel2_in_port0: endpoint { + remote-endpoint = <&etf0_out_port>; + }; + }; + + port@1 { + reg = <1>; + funnel2_in_port1: endpoint { + remote-endpoint = <&etf1_out_port>; + }; + }; + }; + }; + + etf0: etf@2b004000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b004000 0x1000>; + + coresight-name = "coresight-etf0"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf0_in_port: endpoint { + remote-endpoint = <&funnel0_out_port>; + }; + }; + }; + + out-ports { + port { + etf0_out_port: endpoint { + remote-endpoint = <&funnel2_in_port0>; + }; + }; + }; + }; + + etf1: etf@2b005000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b005000 0x1000>; + + coresight-name = "coresight-etf1"; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf1_in_port: endpoint { + remote-endpoint = <&funnel1_out_port>; + }; + }; + }; + + out-ports { + port { + etf1_out_port: endpoint { + remote-endpoint = <&funnel2_in_port1>; + }; + }; + }; + }; + + etr: etr@2b00a000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + arm,primecell-periphid = <0x001bb961>; + reg = <0 0x2b00a000 0x1000>; + + coresight-name = "coresight-etr"; + arm,scatter-gather; + + clocks = <&clock ATCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&funnel2_out_port>; + }; + }; + }; + }; + + etr-miu@110B0000 { + compatible = "google,gs101-etr-miu"; + reg = <0x0 0x110B0000 0x100>; + tmc_buf_addr = <0x00000010 0x00000000>; + tmc_buf_size = <0x80000000>; + }; + + exynos-adv_tracer { + compatible = "google,exynos-adv-tracer"; + reg = <0x0 0x18360000 0x1000>; + reg-names = "mailbox"; + interrupts = ; + pmu-dbgcore-config = <0x3080>; + pmu-dbgcore-status = <0x3084>; + intr-bitoffset = <0>; + status = "ok"; + }; + + exynos_adv_tracer_s2d { + compatible = "google,exynos-adv-tracer-s2d"; + plugin-len = <3>; + plugin-name = "S2D"; + pmu-burnin-ctrl = <0x3cd0>; + sel-scanmode-bit = <25>; + dbgsel-sw-bit = <4>; + blk-list = "AOC", "AOCCORE", "AUR", "AURCORE", "BO", "BOCORE", + "CMU", "CPUCL0", "CLUSTER0", "CSIS", + "DISP", "DNS", "DPU", "EH", "G2D", "G3AA", + "G3D", "GPU", "GDC", "GSA", "HSI0", "HSI1", + "HSI2", "IPP", "ITP", "MCSC", "MFC", "MIF0", "MIF1", + "MIF2", "MIF3", "NOCL0", "NOCL1A", "NOCL1B", "NOCL2A", + "PDP", "PERIC0", "PERIC1", "TNR", + "TPU", "TPUCORE", "SLC0", "SLC1", "SLC2", "SLC3"; + status = "ok"; + }; + + exynos-ehld { + compatible = "google,exynos-ehld"; + #address-cells = <1>; + #size-cells = <1>; + cs_base = <0x2b000000>; + status = "ok"; + + dbgc { + /* IPC */ + plugin-len = <4>; + plugin-name = "ELD"; + support = <1>; + interval = <1000>; + warn-count = <4>; + use-tick-timer = <0>; + }; + + cpu0 { + dbg-offset = <0x810000>; + }; + cpu1 { + dbg-offset = <0x910000>; + }; + cpu2 { + dbg-offset = <0xa10000>; + }; + cpu3 { + dbg-offset = <0xb10000>; + }; + cpu4 { + dbg-offset = <0xc10000>; + }; + cpu5 { + dbg-offset = <0xd10000>; + }; + cpu6 { + dbg-offset = <0xe10000>; + }; + cpu7 { + dbg-offset = <0xf10000>; + }; + }; + + sjtag_ap { + compatible = "google,sjtag"; + ms-per-tick = <5590>; + ipc-timeout-ms = <450>; + pubkey = /bits/ 8 <0xc1 0x13 0xb3 0x1d 0x85 0x6a 0xac 0xc2 0x35 0xf1 0xd7 0x9e + 0x08 0x91 0xc6 0xab 0x16 0xf8 0xfd 0x2f 0x14 0xaa 0x91 0x1d + 0x85 0xc0 0xf6 0x08 0xb1 0xa3 0xfe 0xb8 0x2f 0xa2 0x11 0x1a + 0x6b 0x2b 0xcb 0x21 0x29 0x8b 0xda 0xba 0x30 0x2d 0xb0 0x52 + 0x8f 0x19 0x8f 0x77 0x2b 0x0c 0x69 0x29 0x04 0x14 0x7b 0x3c + 0x5c 0x96 0x74 0x90 0x7e 0x01 0x00 0x00 0x37 0x6a 0x20 0x58 + 0xd3 0xc0 0xb9 0xd0 0x36 0xd1 0x7b 0x1a 0x98 0xc7 0x4b 0xb3 + 0xf8 0xb4 0x13 0xcc 0xf0 0x82 0x17 0x44 0x1e 0x5e 0x64 0xa3 + 0x2e 0x62 0x8b 0x6e 0x14 0xa1 0x45 0x14 0x75 0xc3 0x86 0xff + 0x4d 0x05 0x8b 0x6a 0x42 0x94 0xd7 0x04 0xc2 0x1c 0xe8 0x34 + 0xda 0xed 0x1e 0xbb 0x9a 0x0f 0xcc 0xad 0x3f 0xbe 0xf9 0x4c + 0x52 0x01 0x00 0x00>; + dbg-domain = <0x8028eff9>; + access-lvl = <0xc0000cc0 0xfcffffc3>; + dbg-itvl = <0>; + gsa-device = <&gsa>; + }; + + sjtag_gsa { + compatible = "google,sjtag"; + ms-per-tick = <5590>; + ipc-timeout-ms = <450>; + pubkey = /bits/ 8 <0xe2 0x15 0xce 0xbb 0xc4 0xcb 0x55 0x24 0xf9 0xb3 0x54 0xd8 + 0x3f 0x71 0xf7 0xd5 0x16 0x2b 0xa3 0x38 0x74 0x31 0x4b 0x9b + 0x4d 0xa3 0x5f 0xe8 0x5b 0xf0 0x34 0xa1 0x00 0x96 0x71 0x31 + 0x25 0x34 0x97 0xcd 0x83 0xb8 0x59 0x5e 0xa3 0xdb 0xb5 0xe8 + 0x9e 0x7f 0xb0 0x9d 0x10 0x16 0x7e 0x02 0x27 0x90 0x47 0x74 + 0x71 0xc1 0x37 0xcb 0x81 0x00 0x00 0x00 0x68 0xb9 0xd3 0x84 + 0x72 0x4f 0xa3 0xdf 0x5e 0x7a 0x51 0x83 0x75 0x79 0x02 0x5b + 0x77 0xd5 0x43 0x05 0x00 0x40 0xa6 0x64 0x92 0x33 0xcf 0x32 + 0x43 0x8c 0x5b 0x46 0x92 0xc0 0x96 0x41 0x7a 0x4a 0x01 0xed + 0xd1 0x2d 0x58 0xe2 0x3e 0xb3 0x4b 0xfa 0x0c 0x8c 0x69 0x11 + 0x46 0x25 0x3d 0xa4 0xb7 0x20 0x9b 0x82 0x87 0xb0 0x9e 0x95 + 0xc6 0x01 0x00 0x00>; + dbg-domain = <0x0000006f>; + access-lvl = <0x00000000 0x00003cff>; + dbg-itvl = <0>; + gsa-device = <&gsa>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-dit.dtsi b/arch/arm64/boot/dts/google/gs201-dit.dtsi new file mode 100644 index 000000000000..5ae2cce0cfd1 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dit.dtsi @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung CP interface device tree source + * + * Copyright (c) 2019-2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include + +/ { + dit { + compatible = "samsung,exynos-dit"; + status = "okay"; + + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + interrupt-names = "DIT-RxDst00", "DIT-RxDst1", "DIT-RxDst2", "DIT-Tx"; + + reg = <0x0 0x10190000 0x00010000>, <0x0 0x10030000 0x00002000>; + reg-names = "dit", "sysreg"; + + /* DIT_SHARABILITY_CON or DIT_BUS_CON */ + dit_sharability_offset = <0x00001108>; + dit_sharability_value = <0x00110011>; + + dit_hw_capabilities = <(DIT_CAP_MASK_NONE)>; + + dit_use_tx = <0>; + dit_use_rx = <0>; + dit_use_clat = <0>; + dit_use_recycling = <0>; + + dit_hal_support = <1>; + dit_hal_enqueue_rx = <0>; + + dit_rx_extra_desc_ring_len = <2048>; + dit_irq_affinity = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-dpm-eng.dts b/arch/arm64/boot/dts/google/gs201-dpm-eng.dts new file mode 100644 index 000000000000..01ab09711b39 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-eng.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-eng.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-dpm-eng.dtsi b/arch/arm64/boot/dts/google/gs201-dpm-eng.dtsi new file mode 100644 index 000000000000..d585cc3de5db --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-eng.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +&dpm { + version = <101>; + variant = "eng"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <1>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <1>; + }; + + abl { + ramdump_mode = ; + ramdump2usb = ; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = ; + el1_ia = ; + el1_undef = ; + el1_sp_pc = ; + el1_inv = ; + el1_serror = ; + }; + }; +}; /* end of dpm */ diff --git a/arch/arm64/boot/dts/google/gs201-dpm-user.dts b/arch/arm64/boot/dts/google/gs201-dpm-user.dts new file mode 100644 index 000000000000..882aa5cc5074 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-user.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-user.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-dpm-user.dtsi b/arch/arm64/boot/dts/google/gs201-dpm-user.dtsi new file mode 100644 index 000000000000..40da34895f86 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-user.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +&dpm { + version = <101>; + variant = "user"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <0>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <0>; + }; + + abl { + ramdump_mode = <0>; + ramdump2usb = <0>; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = ; + el1_ia = ; + el1_undef = ; + el1_sp_pc = ; + el1_inv = ; + el1_serror = ; + }; + }; +}; /* end of dpm */ + +&log_arrdumppanic { + status = "disabled"; +}; + +&log_preslcdump { + status = "disabled"; +}; + +&log_slcdump { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dts b/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dts new file mode 100644 index 000000000000..1c809c9378df --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dts @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; +/plugin/; + +#include "gs201-dpm-userdebug.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dtsi b/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dtsi new file mode 100644 index 000000000000..f9c1201240b5 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm-userdebug.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include + +&dpm { + version = <101>; + variant = "userdebug"; + + security { + cp_mem_not_clear = <0>; + dbg_mem_enable = <1>; + seh_enable = <0>; + pm_test_enable = <0>; + seclog_enable = <0>; + harxlog_enable = <0>; + sdm_enable = <0>; + ERXPFG_enable = <1>; + }; + + abl { + ramdump_mode = ; + ramdump2usb = ; + }; + + feature { + /* dump-mode support */ + dump-mode { + enabled = <1>; + file-support = <0>; + }; + + event { + method = DSS_LOG_TASK, + DSS_LOG_WORK, + DSS_LOG_CPUIDLE, + DSS_LOG_SUSPEND, + DSS_LOG_IRQ, + DSS_LOG_HRTIMER, + DSS_LOG_CLK, + DSS_LOG_PMU, + DSS_LOG_FREQ, + DSS_LOG_DM, + DSS_LOG_REGULATOR, + DSS_LOG_THERMAL, + DSS_LOG_ACPM, + DSS_LOG_PRINTK; + }; + + /* debug-kinfo support */ + debug-kinfo { + enabled = <1>; + }; + }; + + policy { + exception { + pre_log = <1>; + + el1_da = ; + el1_ia = ; + el1_undef = ; + el1_sp_pc = ; + el1_inv = ; + el1_serror = ; + }; + }; +}; /* end of dpm */ + +&log_arrdumppanic { + status = "disabled"; +}; + +&log_preslcdump { + status = "disabled"; +}; + +&log_slcdump { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-dpm.dtsi b/arch/arm64/boot/dts/google/gs201-dpm.dtsi new file mode 100644 index 000000000000..8b58ae2247bb --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-dpm.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Debug Policy Manager device tree source + * + * Copyright 2021 Google LLC + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + dpm: dpm { + }; /* end of dpm */ +}; /* end of root */ + +/* default settings built into kernel dt */ +#include "gs201-dpm-user.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-drm-dpu.dtsi b/arch/arm64/boot/dts/google/gs201-drm-dpu.dtsi new file mode 100644 index 000000000000..207615b1ff24 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-drm-dpu.dtsi @@ -0,0 +1,533 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG GS201 SoC device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#include +#include +#include +#include "gs201-pinctrl.dtsi" +#include "gs201-sysmmu.dtsi" +#include "gs101-display-timing.dtsi" + +/ { + drmdpp0: drmdpp@0x1C0B0000 { /* L0 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B0000 0x1000>, /* DPU_DMA */ + <0x0 0x1C0D0000 0x1000>, /* DPP */ + <0x0 0x1C0E0000 0x1000>; /* HDR */ + reg-names = "dma", "dpp", "hdr"; + + /* DPU_DMA IRQ, DPP IRQ */ + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + /* Each bit indicates DPP attribute */ + /* 0:AFBC 1:BLOCK 2:FLIP 3:ROT 4:CSC 5:SCALE 6:HDR 11:HDR10P */ + /* 16:IDMA 17:ODMA 18:DPP */ + attr = <0x50047>; + port = <0>; /* AXI port number */ + + /* 1: scale X, 2: 1/2x scale down, 4: 1/4x scale down */ + scale_down = <1>; + /* 1: scale X, 2: 2x scale up, 4: 4x scale up */ + scale_up = <1>; + + dpp,id = <0>; + }; + + drmdpp1: drmdpp@0x1C0B1000 { /* L1 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B1000 0x1000>, + <0x0 0x1C0D1000 0x1000>, + <0x0 0x1C0E1000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <0>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <1>; + dpp,video; + }; + + drmdpp2: drmdpp@0x1C0B2000 { /* L2 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B2000 0x1000>, + <0x0 0x1C0D2000 0x1000>, + <0x0 0x1C0E2000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + attr = <0x50047>; + port = <1>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <2>; + }; + + drmdpp3: drmdpp@0x1C0B3000 { /* L3 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B3000 0x1000>, + <0x0 0x1C0D3000 0x1000>, + <0x0 0x1C0E3000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <1>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <3>; + dpp,video; + }; + + drmdpp4: drmdpp@0x1C0B4000 { /* L4 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B4000 0x1000>, + <0x0 0x1C0D4000 0x1000>, + <0x0 0x1C0E4000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + attr = <0x50047>; + port = <2>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <4>; + }; + + drmdpp5: drmdpp@0x1C0B5000 { /* L5 */ + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B5000 0x1000>, + <0x0 0x1C0D5000 0x1000>, + <0x0 0x1C0E5000 0x1000>; + reg-names = "dma", "dpp", "hdr"; + + interrupts = , + ; + interrupt-names = "dma", "dpp"; + + attr = <0x50C7F>; + port = <2>; + scale_down = <4>; + scale_up = <8>; + + dpp,id = <5>; + dpp,video; + }; + + drmdpp8: drmdpp@0x1C0B8000 { + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B8000 0x1000>; + reg-names = "dma"; + + interrupts = ; + interrupt-names = "dma"; + + /* 20:RCD */ + attr = <0x100000>; + port = <0>; + dpp,id = <6>; + }; + + drmdpp9: drmdpp@0x1C0B9000 { + compatible = "samsung,exynos-dpp"; + reg = <0x0 0x1C0B9000 0x1000>; + reg-names = "dma"; + + interrupts = ; + interrupt-names = "dma"; + + /* 20:RCD */ + attr = <0x100000>; + port = <1>; + dpp,id = <7>; + }; + + drmdpp12: drmdpp@0x1C0BC000 { /* L12 : WB */ + compatible = "samsung,exynos-writeback"; + reg = <0x0 0x1C0BC000 0x1000>, <0x0 0x1C0DC000 0x1000>; + reg-names = "dma", "dpp"; + + interrupts = ; + interrupt-names = "dma"; + + /* 4:CSC 10:SBWC 17:ODMA 18:DPP */ + attr = <0x60410>; + port = <2>; + scale_down = <1>; + scale_up = <1>; + + dpp,id = <8>; + }; + + disp_ss: disp_ss@0x1C221000 { + compatible = "samsung,exynos9-disp_ss"; + reg = <0x0 0x1C221000 0x10>; + reg-names = "sys"; + }; + + mipi_phy_dsim0_m4m4: dphy_m4s4_dsim0@0x1C2E0000 { + compatible = "samsung,mipi-phy-m4m4"; + isolation = <0x3eb8>; + owner = <0>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + drmdsim0: drmdsim@0x1C2C0000 { + compatible = "samsung,exynos-dsim"; + reg = <0x0 0x1C2C0000 0x300>, /* DSI */ + <0x0 0x1C2E0100 0x700>, /* M4M4S0 PHY */ + <0x0 0x1C2E0000 0x100>; /* M4M4S0 PHY BIAS */ + reg-names = "dsi", "dphy", "dphy-extra"; + + dsim,id = <0>; + + interrupts = ; + interrupt-names = "dsim"; + + phys = <&mipi_phy_dsim0_m4m4 0>; + phy-names = "dsim_dphy"; + + dsim_mode = <&dsim_modes>; + dphy_diag = <&dphy_diags>; + + te_from = <0>; + /* EINT for TE */ + te-gpio = <&gpp0 3 0xf>; + + /* pinctrl */ + pinctrl-names = "hw_te_on", "hw_te_off"; + pinctrl-0 = <&disp_te_pri_on>; + pinctrl-1 = <&disp_te_pri_off>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + drmdsim1: drmdsim@0x1C2D0000 { + status = "disabled"; + + compatible = "samsung,exynos-dsim"; + reg = <0x0 0x1C2D0000 0x300>, /* DSI */ + <0x0 0x1C2E0900 0x700>, /* M4M4S0 PHY */ + <0x0 0x1C2E0000 0x100>; /* M4M4S0 PHY BIAS */ + reg-names = "dsi", "dphy", "dphy-extra"; + + dsim,id = <1>; + + interrupts = ; + interrupt-names = "dsim"; + + phys = <&mipi_phy_dsim0_m4m4 0>; + phy-names = "dsim_dphy"; + + dsim_mode = <&dsim_modes>; + dphy_diag = <&dphy_diags>; + + te_from = <1>; + /* EINT for TE */ + te-gpio = <&gpp0 4 0xf>; + + pinctrl-names = "hw_te_on", "hw_te_off"; + pinctrl-0 = <&disp_te_sec_on>; + pinctrl-1 = <&disp_te_sec_off>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + drmdecon0: drmdecon@0x1C240000 { + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C240000 0x6000>, /* DECON0_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C270000 0x6000>, /* DECON0_WINCON */ + <0x0 0x1C2A0000 0xF000>, /* DQE0 */ + <0x0 0x1C0BE000 0x1000>; /* CGC_DMA */ + + reg-names = "main", "win", "sub", "wincon", "dqe", "cgc-dma"; + + decon,id = <0>; + cgc-dma,id = <9>; + + interrupts = , + , + , + , + , + ; + interrupt-names = "frame_start", "frame_done", "extra", + "dimming_start", "dimming_end", "cgc-dma"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + /* Urgent */ + rd_en = <1>; + rd_hi_thres = <0x800>; + rd_lo_thres = <0x400>; + rd_wait_cycle = <0x10>; + wr_en = <0>; + wr_hi_thres = <0x0>; + wr_lo_thres = <0x0>; + + /* DTA */ + dta_en = <1>; + dta_hi_thres = <0x3200>; + dta_lo_thres = <0x600>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x1 0x2 0x8>; + + hibernation; + rcd = <&drmdpp8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + drmdecon1: drmdecon@0x1C241000 { + status = "disabled"; + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C241000 0x6000>, /* DECON1_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C280000 0x6000>, /* DECON1_WINCON */ + <0x0 0x1C2B0000 0xF000>, /* DQE1 */ + <0x0 0x1C0BF000 0x1000>; /* CGC_DMA */ + reg-names = "main", "win", "sub", "wincon", "dqe", "cgc-dma"; + + decon,id = <1>; + cgc-dma,id = <10>; + + interrupts = , + , + , + , + , + ; + interrupt-names = "frame_start", "frame_done", "extra", + "dimming_start", "dimming_end", "cgc-dma"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + /* Urgent */ + rd_en = <1>; + rd_hi_thres = <0x800>; + rd_lo_thres = <0x400>; + rd_wait_cycle = <0x11>; + wr_en = <0>; + wr_hi_thres = <0x0>; + wr_lo_thres = <0x0>; + + /* DTA */ + dta_en = <1>; + dta_hi_thres = <0x3200>; + dta_lo_thres = <0x600>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x1 0x2 0x8>; + + hibernation; + rcd = <&drmdpp9>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + drmdecon2: drmdecon@0x1C242000 { + compatible = "samsung,exynos-decon"; + reg = <0x0 0x1C242000 0x4000>, /* DECON2_MAIN */ + <0x0 0x1C250000 0x6000>, /* DECON_WIN */ + <0x0 0x1C260000 0x10000>, /* DECON_SUB */ + <0x0 0x1C290000 0x6000>; /* DECON2_WINCON */ + reg-names = "main", "win", "sub", "wincon"; + + decon,id = <2>; + + interrupts = , + , + ; + interrupt-names = "frame_start", "frame_done", "extra"; + iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>; + samsung,iommu-group = <&iommu_group_dpu>; + samsung,tzmp; + + max_win = <6>; + + /* BTS */ + ppc = <2>; /* pixel per clock */ + ppc_rotator = <4>; /* rotator ppc : 4(9830), 8(9840) */ + ppc_scaler = <2>; /* scaler ppc : 2(9830), 4(9840) */ + delay_comp = <4>; /* line delay for afbc or sbwc : DMA */ + delay_scaler = <3>; /* line delay for scaler : DPP */ + + /* bus info */ + bus_width = <16>; /* 16-Byte : 128-bit bus */ + bus_util = <65>; /* 65% */ + rot_util = <60>; /* UTIL gets worse at rotation */ + + /* dpu dvfs */ + dfs_lv_cnt = <7>; + dfs_lv = <664000 533000 465000 400000 310000 267000 134000>; + + dpps = <&drmdpp0 &drmdpp1 &drmdpp2 &drmdpp3 &drmdpp4 &drmdpp5>; + + /* + * connector type that can be connected to the DECON. please + * refer to enum exynos_drm_output_type in exynos_drm_drv.h + * + * DSI0(0x1), DSI1(0x2), VIDI(0x8) + */ + connector = <0x8>; + + itmon,port = "DPU", "DISP"; + itmon,dest = "DPU", "DISP"; + }; + + disp_vddi: disp-vddi { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddi"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_en: disp-vddr_en { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_en"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_0: disp-vddr_0 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_0"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddr_1: disp-vddr_1 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddr_1"; + regulator-boot-on; + enable-active-high; + }; + + disp_vddd: disp-vddd { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vddd"; + regulator-boot-on; + enable-active-high; + }; + + disp_vci: disp-vci { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_vci"; + regulator-boot-on; + enable-active-high; + }; + + disp_bl_en: disp-bl_en { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "disp_bl_en"; + regulator-boot-on; + enable-active-high; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-emulator.dts b/arch/arm64/boot/dts/google/gs201-emulator.dts new file mode 100644 index 000000000000..1b3bb3940a45 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-emulator.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * +*/ + +/dts-v1/; +/plugin/; + +/ { + fragment@zebu { + target-path="/"; + __overlay__ { + model = "GS201 EVT0 EMULATOR ML3_DEV06 board based on GS201"; + compatible = "samsung,GS201", "samsung,GS201 EMULATOR"; + + firmware { + android: android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system: system { + compatible = "android,system"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/system"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + vendor: vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + }; + }; + }; + + virtio_block@0x14630000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x14630000 0x10000>; + interrupts = <0 222 4>; + }; + }; + }; +}; + +/ { + fragment@serial0 { + target-path = "/"; + __overlay__ { + uart@10A00000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + }; + }; + }; +}; + +&serial_0 { + samsung,fifo-size = <256>; + clocks = <&ext_26m>, <&ext_26m>; + status = "okay"; +}; + +&mct { + clocks = <&ext_26m>, <&ext_26m>; +}; + +&memory_0 { + reg = <0x0 0x80000000 0x40000000>; +}; + +&chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 root=/dev/ram0 rw ramdisk_size=65536 initrd=0x84000000,64M clk_ignore_unused mem=1024M maxcpus=1 firmware_class.path=/vendor/firmware androidboot.first_stage_console=1 androidboot.force_normal_boot=1"; +}; + +&pinctrl_6 { + status = "disabled"; +}; + +&pinctrl_7 { + status = "disabled"; +}; + +&amba { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-gpu.dtsi b/arch/arm64/boot/dts/google/gs201-gpu.dtsi new file mode 100644 index 000000000000..7cfd72fb853f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-gpu.dtsi @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 Mali GPU device tree source + * + * Copyright 2021 Google LLC + * + */ + +/ { + mali_mgm: physical-memory-group-manager { + compatible = "arm,physical-memory-group-manager"; + pt_id = "GPU"; + }; + + mali_pcm: priority-control-manager { + compatible = "arm,priority-control-manager"; + }; + + mali_pma: protected-memory-allocator { + compatible = "arm,protected-memory-allocator"; + }; + + mali: mali@28000000 { + compatible = "arm,malit6xx"; + reg = <0x0 0x28000000 0x1000000>; + interrupts = + , + , + ; + interrupt-names = "JOB", "MMU", "GPU"; + + /* Power */ + power-domains = <&pd_g3d>, <&pd_embedded_g3d>; + power-domain-names = "top", "cores"; + g3d_genpd_name = "pd-embedded_g3d"; + gpu_pmu_status_reg_offset = <0x2004>; + gpu_pmu_status_local_pwr_mask = <0x1>; /*0x1 << 0*/ + power_policy = "adaptive"; + + /* Memory */ + physical-memory-group-manager = <&mali_mgm>; + + /* Priority control */ + /*priority-control-manager = <&mali_pcm>;*/ + + /* Protected memory allocator */ + protected-memory-allocator = <&mali_pma>; + + /* Clocks */ + gpu0_cmu_cal_id = ; + gpu1_cmu_cal_id = ; + + /* DVFS */ + gpu_dvfs_governor = "quickstep"; + gpu_dvfs_clockdown_hysteresis = <50>; + + /* DVFS v1 operating points */ + gpu_dvfs_table_size_v1 = <11 10>; /**/ + gpu_dvfs_table_v1 = < + /* + *gpu0 gpu1 down up hys int mif little middle big + * clk clk util util ticks min min min min max + *-------------------------------------------------------------------------- + */ + 996000 848000 85 100 1 533000 3172000 0 0 0 + 996000 762000 81 97 1 0 845000 0 0 0 + 885000 701000 76 94 1 0 845000 0 0 0 + 750000 572000 85 96 2 0 0 0 0 0 + 750000 510000 83 97 3 0 0 0 0 0 + 603000 471000 78 95 3 0 0 0 0 0 + 603000 400000 80 96 3 0 0 0 0 0 + 470000 351000 76 95 3 0 0 0 0 0 + 470000 302000 72 94 3 0 0 0 0 0 + 302000 251000 67 94 2 0 0 0 0 0 + 302000 202000 0 92 1 0 0 0 0 0 + >; + + /* DVFS v2 operating points */ + gpu_dvfs_table_size_v2 = <13 10>; /**/ + gpu_dvfs_table_v2 = < + /* + *gpu0 gpu1 down up hys int mif little middle big + * clk clk util util ticks min min min min max + *-------------------------------------------------------------------------- + */ + 996000 848000 85 100 1 533000 3172000 0 0 0 + 996000 762000 81 97 1 0 845000 0 0 0 + 885000 701000 76 94 1 0 845000 0 0 0 + 885000 633000 80 95 2 0 0 0 0 0 + 750000 572000 85 96 2 0 0 0 0 0 + 750000 510000 83 97 3 0 0 0 0 0 + 603000 471000 78 95 3 0 0 0 0 0 + 603000 434000 79 95 3 0 0 0 0 0 + 603000 400000 80 96 3 0 0 0 0 0 + 470000 351000 76 95 3 0 0 0 0 0 + 470000 302000 72 94 3 0 0 0 0 0 + 302000 251000 67 94 2 0 0 0 0 0 + 302000 202000 0 92 1 0 0 0 0 0 + >; + + /* DVFS step up value */ + gpu_dvfs_step_up_val = <3>; + + /* DVFS Level locks */ + gpu_dvfs_max_freq = <900000>; + gpu_dvfs_min_freq = <0>; + + /* QOS */ + gpu_dvfs_qos_bts_scenario = "g3d_performance"; + gpu_dvfs_qos_bts_threshold = <400000>; + + /* Thermal */ + #cooling-cells = <2>; + gpu_power_coeff = <625>; + ect-coeff-index = <3>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-gsa.dtsi b/arch/arm64/boot/dts/google/gs201-gsa.dtsi new file mode 100644 index 000000000000..ada087c6f626 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-gsa.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/ { + gsa: gsa-ns { + compatible = "google,gs101-gsa-v1"; + #address-cells = <2>; + #size-cells = <1>; + + /* NS mailbox */ + reg = <0 0x17c90000 0x1000>; + interrupts = ; + + s2mpu = <&s2mpu_gsa>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-gxp.dtsi b/arch/arm64/boot/dts/google/gs201-gxp.dtsi new file mode 100644 index 000000000000..607c2d261be2 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-gxp.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GXP device tree source + * + * Copyright 2021 Google,LLC + */ + +#include + +/ { + /* GXP */ + gxp: gxp@25C00000 { + compatible = "google,gxp"; + /* + * DMA buffers are expected in the last 512 MiB of 32-bit space, + * Addresses > 0xF1C00000 are for debug dumpbuffer/firmware + */ + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x30000000 0xC0000000>; + reg = <0x0 0x25C00000 0x01400000 + /* Mailboxes */ + 0x0 0x18380000 0x00001000 + 0x0 0x183A0000 0x00001000 + 0x0 0x183C0000 0x00001000 + 0x0 0x183E0000 0x00001000 + /* SSMTs */ + 0x0 0x25AD0000 0x00010000 + 0x0 0x25AE0000 0x00010000>; + reg-names = "aur", + "mailbox0", "mailbox1", "mailbox2", "mailbox3", + "ssmt_idma", "ssmt_inst_data"; + interrupts = ; + tpu-device = <&edgetpu>; + gsa-device = <&gsa>; + gxp-tpu-mbx-offset = <0x0 0xC0000>; + iommus = <&sysmmu_aur_idma>, <&sysmmu_aur_inst_data>; + samsung,iommu-group = <&iommu_group_aur>; + gxp-fw-region = <&gxp_fw_reserved>; + gxp-scratchpad-region = <&gxp_scratchpad_reserved>; + gxp-memory-per-core = <0 512>; + }; + gxp_cooling: gxp-cooling { + #cooling-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-hybrid.dts b/arch/arm64/boot/dts/google/gs201-hybrid.dts new file mode 100644 index 000000000000..afc171e7212f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-hybrid.dts @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * +*/ + +/dts-v1/; +/plugin/; + +/ { + fragment@zebu { + target-path="/"; + __overlay__ { + model = "GS201 EVT0 HYBRID EMULATOR ML3_DEV06 board based on GS201"; + compatible = "samsung,GS201", "samsung,GS201 EMULATOR"; + + firmware { + android: android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system: system { + compatible = "android,system"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/system"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + vendor: vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/14620000.dwmmc2/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro"; + fsmgr_flags = "wait"; + status = "okay"; + }; + }; + }; + }; + + virtio_block@0x14630000 { + compatible = "virtio,mmio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x14630000 0x10000>; + interrupts = <0 222 4>; + }; + }; + }; +}; + +/ { + fragment@serial0 { + target-path = "/"; + __overlay__ { + uart@10A00000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + }; + }; + }; +}; + +&serial_0 { + samsung,fifo-size = <256>; + clocks = <&ext_26m>, <&ext_26m>; + status = "okay"; +}; + +&mct { + clocks = <&ext_1m>, <&ext_1m>; +}; + +&memory_0 { + reg = <0x0 0x80000000 0x40000000>; +}; + +&chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 root=/dev/ram0 rw ramdisk_size=65536 initrd=0x84000000,64M clk_ignore_unused mem=1024M maxcpus=1 firmware_class.path=/vendor/firmware androidboot.first_stage_console=1 androidboot.force_normal_boot=1 clocksource=arch_sys_counter"; +}; + +&pinctrl_6 { + status = "disabled"; +}; + +&pinctrl_7 { + status = "disabled"; +}; + +&amba { + status = "disabled"; +}; + +&dwmmc_2 { + status = "okay"; +}; + +/* [TEMP] Temporarily disable SysMMU power-domains as this feature has not yet + * been implemented on the hybrid emulator. + * + * Also disable the TPU SysMMU instance because it is not available on the + * hybrid emulator. + */ + +&sysmmu_bo { + power-domains; +}; + +&sysmmu_csis0 { + power-domains; +}; + +&sysmmu_csis1 { + power-domains; +}; + +&sysmmu_dns { + power-domains; +}; + +&sysmmu_dpu0 { + power-domains; +}; + +&sysmmu_dpu1 { + power-domains; +}; + +&sysmmu_dpu2 { + power-domains; +}; + +&sysmmu_g2d0 { + power-domains; +}; + +&sysmmu_g2d1 { + power-domains; +}; + +&sysmmu_g2d2 { + power-domains; +}; + +&sysmmu_g3aa { + power-domains; +}; + +&sysmmu_gdc0 { + power-domains; +}; + +&sysmmu_gdc1 { + power-domains; +}; + +&sysmmu_gdc2 { + power-domains; +}; + +&sysmmu_ipp { + power-domains; +}; + +&sysmmu_mcsc0 { + power-domains; +}; + +&sysmmu_mcsc1 { + power-domains; +}; + +&sysmmu_mcsc2 { + power-domains; +}; + +&sysmmu_mfc0 { + power-domains; +}; + +&sysmmu_mfc1 { + power-domains; +}; + +&sysmmu_tnr0 { + power-domains; +}; + +&sysmmu_tnr1 { + power-domains; +}; + +&sysmmu_tnr2 { + power-domains; +}; + +&sysmmu_tnr3 { + power-domains; +}; + +&sysmmu_tnr4 { + power-domains; +}; + +&sysmmu_tpu { + status = "disabled"; + power-domains; +}; + +&sysmmu_aur_idma { + power-domains; +}; + +&sysmmu_aur_inst_data { + power-domains; +}; diff --git a/arch/arm64/boot/dts/google/gs201-isp-event-info.dtsi b/arch/arm64/boot/dts/google/gs201-isp-event-info.dtsi new file mode 100644 index 000000000000..ec86237061e3 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-isp-event-info.dtsi @@ -0,0 +1,4467 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 ISP device tree for interrupt events + * + * Copyright 2021 Google LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + /* + * CSI Interrupt Event Definitions + */ + + csi_ctx0_csis_int0: csi-event-info@0 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx1_csis_int0: csi-event-info@1 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx2_csis_int0: csi-event-info@2 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx3_csis_int0: csi-event-info@3 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx4_csis_int0: csi-event-info@4 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx5_csis_int0: csi-event-info@5 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx6_csis_int0: csi-event-info@6 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx7_csis_int0: csi-event-info@7 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x14>; + irq-reset-reg = <0x0 0x14>; + irq-mask-reg = <0x0 0x10>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx0_csis_int1: csi-event-info@8 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx1_csis_int1: csi-event-info@9 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx2_csis_int1: csi-event-info@10 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx3_csis_int1: csi-event-info@11 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx4_csis_int1: csi-event-info@12 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx5_csis_int1: csi-event-info@13 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx6_csis_int1: csi-event-info@14 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx7_csis_int1: csi-event-info@15 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x1c>; + irq-reset-reg = <0x0 0x1c>; + irq-mask-reg = <0x0 0x18>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + csi_ctx0_fs_int: csi-event-info@16 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx1_fs_int: csi-event-info@17 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx2_fs_int: csi-event-info@18 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx3_fs_int: csi-event-info@19 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx4_fs_int: csi-event-info@20 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx5_fs_int: csi-event-info@21 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx6_fs_int: csi-event-info@22 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx7_fs_int: csi-event-info@23 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x24>; + irq-reset-reg = <0x0 0x24>; + irq-mask-reg = <0x0 0x20>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx0_fe_int: csi-event-info@24 { + irq-reg-space = "csis-link0"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx1_fe_int: csi-event-info@25 { + irq-reg-space = "csis-link1"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx2_fe_int: csi-event-info@26 { + irq-reg-space = "csis-link2"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx3_fe_int: csi-event-info@27 { + irq-reg-space = "csis-link3"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx4_fe_int: csi-event-info@28 { + irq-reg-space = "csis-link4"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx5_fe_int: csi-event-info@29 { + irq-reg-space = "csis-link5"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx6_fe_int: csi-event-info@30 { + irq-reg-space = "csis-link6"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ctx7_fe_int: csi-event-info@31 { + irq-reg-space = "csis-link7"; + irq-src-reg = <0x0 0x2c>; + irq-reset-reg = <0x0 0x2c>; + irq-mask-reg = <0x0 0x28>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_zsl_dma_ctx0_int: csi_zsl_dma-event-info@32 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x1408>; + irq-reset-reg = <0x0 0x1408>; + irq-mask-reg = <0x0 0x1404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_zsl_dma_ctx1_int: csi_zsl_dma-event-info@33 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x2408>; + irq-reset-reg = <0x0 0x2408>; + irq-mask-reg = <0x0 0x2404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_zsl_dma_ctx2_int: csi_zsl_dma-event-info@34 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x3408>; + irq-reset-reg = <0x0 0x3408>; + irq-mask-reg = <0x0 0x3404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_strp_dma_ctx0_int: csi_strp_dma-event-info@35 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x4408>; + irq-reset-reg = <0x0 0x4408>; + irq-mask-reg = <0x0 0x4404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_strp_dma_ctx1_int: csi_strp_dma-event-info@36 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x5408>; + irq-reset-reg = <0x0 0x5408>; + irq-mask-reg = <0x0 0x5404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_strp_dma_ctx2_int: csi_strp_dma-event-info@37 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x6408>; + irq-reset-reg = <0x0 0x6408>; + irq-mask-reg = <0x0 0x6404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_csis_dma_ctx0_int: csi_csis_dma-event-info@38 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x7408>; + irq-reset-reg = <0x0 0x7408>; + irq-mask-reg = <0x0 0x7404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_csis_dma_ctx1_int: csi_csis_dma-event-info@39 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x8408>; + irq-reset-reg = <0x0 0x8408>; + irq-mask-reg = <0x0 0x8404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_csis_dma_ctx2_int: csi_csis_dma-event-info@40 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0x9408>; + irq-reset-reg = <0x0 0x9408>; + irq-mask-reg = <0x0 0x9404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_csis_dma_ctx3_int: csi_csis_dma-event-info@41 { + irq-reg-space = "csis-dma"; + irq-src-reg = <0x0 0xa408>; + irq-reset-reg = <0x0 0xa408>; + irq-mask-reg = <0x0 0xa404>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + csi_ebuf0_int: csi_ebuf-event-info@42 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + ; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + csi_ebuf1_int: csi_ebuf-event-info@43 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + ; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + csi_ebuf2_int: csi_ebuf-event-info@44 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + ; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + csi_ebuf3_int: csi_ebuf-event-info@45 { + irq-reg-space = "csis-ebuf"; + irq-src-reg = <0x0 0xd0>; + irq-reset-reg = <0x0 0xd8>; + irq-mask-reg = <0x0 0xd4>; + + critical-irq-events = + ; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + /* + * G3AA Interrupt Event Definitions + */ + + g3aa_ctx0_interrupts: g3aa-event-info@0 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x5c>; + irq-reset-reg = <0x0 0x60>; + irq-mask-reg = <0x0 0x58>; + irq-reg-bitwidth = <16>; + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + g3aa_ctx1_interrupts: g3aa-event-info@1 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x6c>; + irq-reset-reg = <0x0 0x70>; + irq-mask-reg = <0x0 0x68>; + irq-reg-bitwidth = <16>; + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + g3aa_ctx2_interrupts: g3aa-event-info@2 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x7c>; + irq-reset-reg = <0x0 0x80>; + irq-mask-reg = <0x0 0x78>; + irq-reg-bitwidth = <16>; + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + g3aa_error_interrupts: g3aa-event-info@3 { + irq-reg-space = "g3aa"; + irq-src-reg = <0x0 0x5e>; + irq-reset-reg = <0x0 0x62>; + irq-mask-reg = <0x0 0x5a>; + irq-reg-bitwidth = <16>; + irq-events = + , + , + , + ; + int-reg-bits = + , + , + , + ; + }; + + /* + * GDC Interrupt Event Definitions + */ + gdc_int0: gdc-event-info@0 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gdc_int1: gdc-event-info@1 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + gdc_cmdq_int: gdc-event-info@2 { + irq-reg-space = "gdc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + /* + * GTNR-ALIGN Interrupt Event Definitions + */ + gtnr_align_int: gtnr_align-event-info@0 { + irq-reg-space = "tnr_align"; + irq-src-reg = <0x0 0x40>; + irq-reset-reg = <0x0 0x40>; + irq-mask-reg = <0x0 0x44>; + irq-mask-reg-toggle; + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + gtnr_align_secu_int_mute: gtnr_align-event-info@1 { + irq-reg-space = "tnr_align"; + irq-src-reg = <0x0 0xc0>; + irq-reset-reg = <0x0 0xc8>; + irq-mask-reg = <0x0 0xc4>; + + irq-events = + , + ; + int-reg-bits = + , + ; + }; + + /* + * GTNR-MERGE Interrupt Event Definitions + */ + gtnr_merge_int0: gtnr_merge-event-info@0 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gtnr_merge_int1: gtnr_merge-event-info@1 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + , + , + , + , + ; + int-reg-bits = + , + , + , + , + ; + }; + gtnr_merge_cmdq_int: gtnr_merge-event-info@2 { + irq-reg-space = "tnr"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; +}; + + + /* + * IPP Interrupt Event Definitions + */ + + ipp_ctx0_int1: ipp-event-info@0 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_ctx1_int1: ipp-event-info@1 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_ctx2_int1: ipp-event-info@2 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x20c>; + irq-reset-reg = <0x0 0x210>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_ctx0_int2: ipp-event-info@3 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + ipp_ctx1_int2: ipp-event-info@4 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + ipp_ctx2_int2: ipp-event-info@5 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x21c>; + irq-reset-reg = <0x0 0x220>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx0_int0: ipp_fro-event-info@6 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx1_int0: ipp_fro-event-info@7 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx2_int0: ipp_fro-event-info@8 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x3dd0>; + irq-reset-reg = <0x0 0x3dc4>; + irq-mask-reg = <0x0 0x208>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx0_int1: ipp_fro-event-info@9 { + irq-reg-space = "ipp0"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx1_int1: ipp_fro-event-info@10 { + irq-reg-space = "ipp1"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + ipp_fro_ctx2_int1: ipp_fro-event-info@11 { + irq-reg-space = "ipp2"; + irq-src-reg = <0x0 0x3dd4>; + irq-reset-reg = <0x0 0x3dc8>; + irq-mask-reg = <0x0 0x218>; + + irq-events = + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + ; + }; + + /* + * ITP Interrupt Event Definitions + */ + itp_itp_int0: itp-event-info@0 { + irq-reg-space = "itp"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + itp_itp_cmdq_int: itp-event-info@1 { + irq-reg-space = "itp"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + itp_dns_int0: itp-event-info@2 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + itp_dns_int1: itp-event-info@3 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + ; + }; + + itp_dns_cmdq_int: itp-event-info@4 { + irq-reg-space = "dns"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + itp_itsc_int0: itp-event-info@5 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + itp_itsc_int1: itp-event-info@6 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + ; + int-reg-bits = + ; + }; + + itp_itsc_cmdq_int: itp-event-info@7 { + irq-reg-space = "itsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + /* + * MCSC Interrupt Event Definitions + */ + mcsc_int0: mcsc-event-info@0 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + mcsc_int1: mcsc-event-info@1 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + mcsc_cmdq_int: mcsc-event-info@2 { + irq-reg-space = "mcsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; + + /* + * PDP Interrupt Event Definitions + */ + + pdp_ctx0_int_src1: pdp-event-info@0 { + irq-reg-space = "pdp-core0"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdp_ctx1_int_src1: pdp-event-info@1 { + irq-reg-space = "pdp-core1"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdp_ctx2_int_src1: pdp-event-info@2 { + irq-reg-space = "pdp-core2"; + irq-src-reg = <0x0 0x10c>; + irq-reset-reg = <0x0 0x110>; + irq-mask-reg = <0x0 0x108>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdp_ctx0_int_src2: pdp-event-info@3 { + irq-reg-space = "pdp-core0"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdp_ctx1_int_src2: pdp-event-info@4 { + irq-reg-space = "pdp-core1"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pdp_ctx2_int_src2: pdp-event-info@5 { + irq-reg-space = "pdp-core2"; + irq-src-reg = <0x0 0x11c>; + irq-reset-reg = <0x0 0x120>; + irq-mask-reg = <0x0 0x118>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + /* + * SCSC Interrupt Event Definitions + */ + scsc_int0: scsc-event-info@0 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x808>; + irq-reset-reg = <0x0 0x80c>; + irq-mask-reg = <0x0 0x804>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + scsc_int1: scsc-event-info@1 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x818>; + irq-reset-reg = <0x0 0x81c>; + irq-mask-reg = <0x0 0x814>; + + irq-events = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + int-reg-bits = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + scsc_cmdq_int: scsc-event-info@2 { + irq-reg-space = "scsc"; + irq-src-reg = <0x0 0x4f8>; + irq-reset-reg = <0x0 0x4fc>; + irq-mask-reg = <0x0 0x4f4>; + + irq-events = + , + , + ; + int-reg-bits = + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-isp.dtsi b/arch/arm64/boot/dts/google/gs201-isp.dtsi new file mode 100644 index 000000000000..ee0b548618e2 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-isp.dtsi @@ -0,0 +1,980 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 ISP device tree source + * + * Copyright 2021 Google LLC. + */ + +#include +#include +#include +#include "gs201-isp-event-info.dtsi" + +/ { + sysreg_csis_reset: system-controller@1A420500 { + compatible = "samsung,exynos-csis", "syscon"; + reg = <0x0 0x1A420500 0x8>; + }; + + mipi_phy_csis0_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F1300 { + /* DPHY 4.5 Gbps 4lane */ + /* CPHY 2.5 Gbps 3lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <0>; /* reset bit */ + reg = <0x0 0x1A4F1300 0x500>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis1_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F1B00 { + /* DPHY 4.5 Gbps 4lane */ + /* CPHY 2.5 Gbps 3lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <1>; /* reset bit */ + reg = <0x0 0x1A4F1B00 0x500>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis2_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2300 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <2>; /* reset bit */ + reg = <0x0 0x1A4F2300 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis3_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2600 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <3>; /* reset bit */ + reg = <0x0 0x1A4F2600 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis4_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2B00 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <4>; /* reset bit */ + reg = <0x0 0x1A4F2B00 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis5_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F2E00 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <5>; /* reset bit */ + reg = <0x0 0x1A4F2E00 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis6_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F3300 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 2lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <6>; /* reset bit */ + reg = <0x0 0x1A4F3300 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + mipi_phy_csis7_m0s4s4s4s4s4: dcphy_m0s4s4s4s4s4_csi0@1A4F3600 { + /* DPHY 4.5 Gbps 2lane */ + /* CPHY 2.5 Gbps 1lane */ + compatible = "samsung,mipi-phy-m0s4s4s4s4s4"; + samsung,pmu-syscon = <&pmu_system_controller>; + isolation = <0x3ebc>; /* PMU address offset */ + samsung,reset-sysreg = <&sysreg_csis_reset>; + reset = <7>; /* reset bit */ + reg = <0x0 0x1A4F3600 0x300>; + owner = <1>; /* 0: DSI, 1: CSI */ + #phy-cells = <1>; + }; + + lwis_top: lwis_top@0 { + compatible = "google,lwis-top-device"; + + /* Device node name */ + node-name = "top"; + }; + + lwis_dpm: lwis_dpm@0 { + compatible = "google,lwis-dpm-device"; + + /* Device node name */ + node-name = "dpm"; + }; + + lwis_csi: lwis_csi@1A440000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "csi"; + + /* Register space */ + reg = + <0x0 0x1A440000 0x1000>, /* MIPI-CSIS0 */ + <0x0 0x1A450000 0x1000>, /* MIPI-CSIS1 */ + <0x0 0x1A460000 0x1000>, /* MIPI-CSIS2 */ + <0x0 0x1A470000 0x1000>, /* MIPI-CSIS3 */ + <0x0 0x1A480000 0x1000>, /* MIPI-CSIS4 */ + <0x0 0x1A490000 0x1000>, /* MIPI-CSIS5 */ + <0x0 0x1A4A0000 0x1000>, /* MIPI-CSIS6 */ + <0x0 0x1A4B0000 0x1000>, /* MIPI-CSIS7 */ + <0x0 0x1A4C0000 0x100>, /* CSIS EBUF */ + <0x0 0x1A4D0000 0x10000>, /* CSIS DMA */ + <0x0 0x1A4F0000 0x10000>, /* CSIS PHY */ + <0x0 0x1A420000 0x10000>; /* SYSREG CSIS */ + + reg-names = + "csis-link0", + "csis-link1", + "csis-link2", + "csis-link3", + "csis-link4", + "csis-link5", + "csis-link6", + "csis-link7", + "csis-ebuf", + "csis-dma", + "csis-phy", + "csis-sysreg"; + + /* Clocks */ + clocks = + <&clock UMUX_CLKCMU_CSIS_NOC>, + <&clock GATE_DFTMUX_CMU_CIS_CLK0>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK2>, + <&clock GATE_DFTMUX_CMU_CIS_CLK3>, + <&clock GATE_DFTMUX_CMU_CIS_CLK4>, + <&clock GATE_DFTMUX_CMU_CIS_CLK5>, + <&clock GATE_DFTMUX_CMU_CIS_CLK6>, + <&clock GATE_DFTMUX_CMU_CIS_CLK7>, + <&clock CIS_CLK0>, + <&clock CIS_CLK1>, + <&clock CIS_CLK2>, + <&clock CIS_CLK3>, + <&clock CIS_CLK4>, + <&clock CIS_CLK5>, + <&clock CIS_CLK6>, + <&clock CIS_CLK7>; + clock-names = + "UMUX_CLKCMU_CSIS_NOC", + "GATE_DFTMUX_CMU_CIS_CLK0", + "GATE_DFTMUX_CMU_CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK2", + "GATE_DFTMUX_CMU_CIS_CLK3", + "GATE_DFTMUX_CMU_CIS_CLK4", + "GATE_DFTMUX_CMU_CIS_CLK5", + "GATE_DFTMUX_CMU_CIS_CLK6", + "GATE_DFTMUX_CMU_CIS_CLK7", + "CIS_CLK0", + "CIS_CLK1", + "CIS_CLK2", + "CIS_CLK3", + "CIS_CLK4", + "CIS_CLK5", + "CIS_CLK6", + "CIS_CLK7"; + clock-rates = <0>; + + clock-family = ; + bts-scenario = "camera_default"; + + interrupts = + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS4_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS5_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS6_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS7_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ZSL_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_STRP_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_CSIS_DMA3_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW0_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW1_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW2_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_EBUF_OVERFLOW3_CSIS IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "csi-link0-src0", + "csi-link0-src1", + "csi-link0-fs", + "csi-link0-fe", + "csi-link1-src0", + "csi-link1-src1", + "csi-link1-fs", + "csi-link1-fe", + "csi-link2-src0", + "csi-link2-src1", + "csi-link2-fs", + "csi-link2-fe", + "csi-link3-src0", + "csi-link3-src1", + "csi-link3-fs", + "csi-link3-fe", + "csi-link4-src0", + "csi-link4-src1", + "csi-link4-fs", + "csi-link4-fe", + "csi-link5-src0", + "csi-link5-src1", + "csi-link5-fs", + "csi-link5-fe", + "csi-link6-src0", + "csi-link6-src1", + "csi-link6-fs", + "csi-link6-fe", + "csi-link7-src0", + "csi-link7-src1", + "csi-link7-fs", + "csi-link7-fe", + "zsl-dma0", + "zsl-dma1", + "zsl-dma2", + "strp-dma0", + "strp-dma1", + "strp-dma2", + "csis-dma0", + "csis-dma1", + "csis-dma2", + "csis-dma3", + "csi-ebuf0", + "csi-ebuf1", + "csi-ebuf2", + "csi-ebuf3"; + interrupt-event-infos = + <&csi_ctx0_csis_int0>, + <&csi_ctx0_csis_int1>, + <&csi_ctx0_fs_int>, + <&csi_ctx0_fe_int>, + <&csi_ctx1_csis_int0>, + <&csi_ctx1_csis_int1>, + <&csi_ctx1_fs_int>, + <&csi_ctx1_fe_int>, + <&csi_ctx2_csis_int0>, + <&csi_ctx2_csis_int1>, + <&csi_ctx2_fs_int>, + <&csi_ctx2_fe_int>, + <&csi_ctx3_csis_int0>, + <&csi_ctx3_csis_int1>, + <&csi_ctx3_fs_int>, + <&csi_ctx3_fe_int>, + <&csi_ctx4_csis_int0>, + <&csi_ctx4_csis_int1>, + <&csi_ctx4_fs_int>, + <&csi_ctx4_fe_int>, + <&csi_ctx5_csis_int0>, + <&csi_ctx5_csis_int1>, + <&csi_ctx5_fs_int>, + <&csi_ctx5_fe_int>, + <&csi_ctx6_csis_int0>, + <&csi_ctx6_csis_int1>, + <&csi_ctx6_fs_int>, + <&csi_ctx6_fe_int>, + <&csi_ctx7_csis_int0>, + <&csi_ctx7_csis_int1>, + <&csi_ctx7_fs_int>, + <&csi_ctx7_fe_int>, + <&csi_zsl_dma_ctx0_int>, + <&csi_zsl_dma_ctx1_int>, + <&csi_zsl_dma_ctx2_int>, + <&csi_strp_dma_ctx0_int>, + <&csi_strp_dma_ctx1_int>, + <&csi_strp_dma_ctx2_int>, + <&csi_csis_dma_ctx0_int>, + <&csi_csis_dma_ctx1_int>, + <&csi_csis_dma_ctx2_int>, + <&csi_csis_dma_ctx3_int>, + <&csi_ebuf0_int>, + <&csi_ebuf1_int>, + <&csi_ebuf2_int>, + <&csi_ebuf3_int>; + + phys = + <&mipi_phy_csis0_m0s4s4s4s4s4 0>, + <&mipi_phy_csis1_m0s4s4s4s4s4 0>, + <&mipi_phy_csis2_m0s4s4s4s4s4 0>, + <&mipi_phy_csis3_m0s4s4s4s4s4 0>, + <&mipi_phy_csis4_m0s4s4s4s4s4 0>, + <&mipi_phy_csis5_m0s4s4s4s4s4 0>, + <&mipi_phy_csis6_m0s4s4s4s4s4 0>, + <&mipi_phy_csis7_m0s4s4s4s4s4 0>; + phy-names = + "csis0_dcphy", + "csis1_dcphy", + "csis2_dcphy", + "csis3_dcphy", + "csis4_dcphy", + "csis5_dcphy", + "csis6_dcphy", + "csis7_dcphy"; + + iommus = + <&sysmmu_csis0>, + <&sysmmu_csis1>; + power-domains = <&pd_pdp>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_pdp: lwis_pdp@1AA40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "pdp"; + + /* Register space */ + reg = + <0x0 0x1AA40000 0x10000>, /* PDP CORE0 */ + <0x0 0x1AA50000 0x10000>, /* PDP CORE1 */ + <0x0 0x1AA60000 0x10000>, /* PDP CORE2 */ + <0x0 0x1AA20000 0x10000>, /* SYSREG PDP */ + <0x0 0x1A820400 0x4>, /* SYSREG G3AA */ + <0x0 0x1AC40000 0x10000>, /* IPP CORE0 */ + <0x0 0x1AC50000 0x10000>, /* IPP CORE1 */ + <0x0 0x1AC60000 0x10000>, /* IPP CORE2 */ + <0x0 0x1A840000 0x20000>, /* G3AA */ + <0x0 0x1A800000 0x10000>; /* G3AA CMU*/ + reg-names = + "pdp-core0", + "pdp-core1", + "pdp-core2", + "sysreg-pdp", + "sysreg-g3aa", + "ipp-core0", + "ipp-core1", + "ipp-core2", + "g3aa-core", + "g3aa-cmu"; + + clocks = + <&clock UMUX_CLKCMU_PDP_NOC>, + <&clock UMUX_CLKCMU_PDP_VRA>; + clock-names = + "UMUX_CLKCMU_PDP_NOC", + "UMUX_CLKCMU_PDP_VRA"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 IRQ_PDP_TOP0_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE0 */ + <0 IRQ_PDP_TOP1_PDP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_PDP_TOP2_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE1 */ + <0 IRQ_PDP_TOP3_PDP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_PDP_TOP4_PDP IRQ_TYPE_LEVEL_HIGH>, /* PDP_CORE2 */ + <0 IRQ_PDP_TOP5_PDP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "pdp-ctx0-src1", + "pdp-ctx0-src2", + "pdp-ctx1-src1", + "pdp-ctx1-src2", + "pdp-ctx2-src1", + "pdp-ctx2-src2"; + interrupt-event-infos = + <&pdp_ctx0_int_src1>, + <&pdp_ctx0_int_src2>, + <&pdp_ctx1_int_src1>, + <&pdp_ctx1_int_src2>, + <&pdp_ctx2_int_src1>, + <&pdp_ctx2_int_src2>; + + iommus = + <&sysmmu_csis1>, + <&sysmmu_ipp>, + <&sysmmu_g3aa>; + power-domains = <&pd_pdp>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_ipp: lwis_ipp@1AC40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "ipp"; + + /* Register space */ + reg = + <0x0 0x1AC40000 0x10000>, /* IPP0 */ + <0x0 0x1AC50000 0x10000>, /* IPP1 */ + <0x0 0x1AC60000 0x10000>; /* IPP2 */ + reg-names = + "ipp0", + "ipp1", + "ipp2"; + + clocks = <&clock UMUX_CLKCMU_IPP_NOC>; + clock-names = "UMUX_CLKCMU_IPP_NOC"; + clock-rates = <0>; + clock-family = ; + + interrupts = + <0 IRQ_IPP_CH0_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP0 */ + <0 IRQ_IPP_CH0_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH0_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH0_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP1 */ + <0 IRQ_IPP_CH1_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH1_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_0_IPP IRQ_TYPE_LEVEL_HIGH>, /* IPP2 */ + <0 IRQ_IPP_CH2_1_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_0_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_IPP_CH2_1_IPP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "ipp0-int1", + "ipp0-int2", + "ipp0_fro_int0", + "ipp0_fro_int1", + "ipp1-int1", + "ipp1-int2", + "ipp1_fro_int0", + "ipp1_fro_int1", + "ipp2-int1", + "ipp2-int2", + "ipp2_fro_int0", + "ipp2_fro_int1"; + interrupt-event-infos = + <&ipp_ctx0_int1>, + <&ipp_ctx0_int2>, + <&ipp_fro_ctx0_int0>, + <&ipp_fro_ctx0_int1>, + <&ipp_ctx1_int1>, + <&ipp_ctx1_int2>, + <&ipp_fro_ctx1_int0>, + <&ipp_fro_ctx1_int1>, + <&ipp_ctx2_int1>, + <&ipp_ctx2_int2>, + <&ipp_fro_ctx2_int0>, + <&ipp_fro_ctx2_int1>; + + iommus = <&sysmmu_ipp>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_gtnr_align: lwis_gtnr_align@1AC80000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gtnr-align"; + + /* Register space */ + reg = + <0x0 0x1AC80000 0x10000>, /* TNR_ALIGN */ + <0x0 0x1AC03100 0x4>, /* TNR_A_CLOCK */ + <0x0 0x1AEB4400 0x88>, /* TNR_ALIGN_M0 */ + <0x0 0x1AEC4400 0x88>; /* TNR_ALIGN_M4 */ + reg-names = + "tnr_align", + "tnr_a_clock", + "tnr_align_m0", + "tnr_align_m4"; + + clocks = + <&clock UMUX_CLKCMU_IPP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>; + clock-names = + "UMUX_CLKCMU_IPP_NOC", + "UMUX_CLKCMU_DNS_NOC"; + clock-rates = <0>; + clock-family = ; + + interrupts = + <0 IRQ_TNR_A_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MUTE_GTNR_ALIGN_IPP IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gtnr-align-int", + "gtnr-align-mute"; + interrupt-event-infos = + <>nr_align_int>, + <>nr_align_secu_int_mute>; + + iommus = + <&sysmmu_ipp>, + <&sysmmu_dns>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_gtnr_merge: lwis_gtnr_merge@1BC40000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gtnr-merge"; + + /* Register space */ + reg = + <0x0 0x1BC40000 0x10000>, /* TNR */ + <0x0 0x1BE84000 0xA00>, /* TNR SSMT D0 */ + <0x0 0x1BE94000 0xA00>, /* TNR SSMT D1 */ + <0x0 0x1BEA4000 0xA00>, /* TNR SSMT D2 */ + <0x0 0x1BEB4000 0xA00>, /* TNR SSMT D3 */ + <0x0 0x1BEC4000 0xA00>, /* TNR SSMT D4 */ + <0x0 0x1BED4000 0xA00>, /* TNR SSMT D5 */ + <0x0 0x1BEE4000 0xA00>, /* TNR SSMT D6 */ + <0x0 0x1BEF4000 0xA00>, /* TNR SSMT D7 */ + <0x0 0x1BC030E4 0x8>, /* TNR_QCH */ + <0x0 0x1BC20400 0x4>; /* TNR SYSREG */ + reg-names = + "tnr", + "tnr_ssmt_d0", + "tnr_ssmt_d1", + "tnr_ssmt_d2", + "tnr_ssmt_d3", + "tnr_ssmt_d4", + "tnr_ssmt_d5", + "tnr_ssmt_d6", + "tnr_ssmt_d7", + "tnr_qch", + "tnr_sysreg"; + + clocks = <&clock UMUX_CLKCMU_TNR_NOC>; + clock-names = "UMUX_CLKCMU_TNR_NOC"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 IRQ_TNR_0_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TNR_1_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TNR_0_TNR IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gtnr-merge-int0", + "gtnr-merge-int1", + "gtnr-merge-cmdq-int"; + interrupt-event-infos = + <>nr_merge_int0>, + <>nr_merge_int1>, + <>nr_merge_cmdq_int>; + + iommus = + <&sysmmu_tnr0>, + <&sysmmu_tnr1>, + <&sysmmu_tnr2>, + <&sysmmu_tnr3>, + <&sysmmu_tnr4>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_g3aa: lwis_g3aa@1A840000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "g3aa"; + + /* Register space */ + reg = + <0x0 0x1A840000 0x20000>, /* G3AA */ + <0x0 0x1A820000 0x10000>, /* SYSREG_G3AA */ + <0x0 0x1A860000 0x10000>; /* LINEBUFFER_G3AA */ + reg-names = + "g3aa", + "sysreg-g3aa", + "linebuffer-g3aa"; + + clocks = <&clock UMUX_CLKCMU_G3AA_G3AA>; + clock-names = "UMUX_CLKCMU_G3AA_G3AA"; + clock-rates = <0>; + clock-family = ; + + interrupts = + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_G3AA_G3AA IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "g3aa-ctx0-int", + "g3aa-ctx1-int", + "g3aa-ctx2-int", + "g3aa-err-int"; + interrupt-event-infos = + <&g3aa_ctx0_interrupts>, + <&g3aa_ctx1_interrupts>, + <&g3aa_ctx2_interrupts>, + <&g3aa_error_interrupts>; + + iommus = <&sysmmu_g3aa>; + samsung,iommu-group = <&iommu_group_isp>; + }; + + lwis_itp: lwis_itp@1B450000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "itp"; + + /* Register space */ + reg = + <0x0 0x1B450000 0x10000>, /* ITP */ + <0x0 0x1B040000 0x10000>, /* DNS */ + <0x0 0x1B740000 0x10000>, /* ITSC */ + <0x0 0x1B020000 0x10000>, /* SYSREG DNS */ + <0x0 0x1B894000 0xA00>; /* SSMT D0 ITSC */ + reg-names = + "itp", + "dns", + "itsc", + "sysreg_dns", + "ssmt_d0_itsc"; + + clocks = + <&clock UMUX_CLKCMU_ITP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>, + <&clock UMUX_CLKCMU_MCSC_ITSC>; + clock-names = + "UMUX_CLKCMU_ITP_NOC", + "UMUX_CLKCMU_DNS_NOC", + "UMUX_CLKCMU_MCSC_ITSC"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 INTREQ_ITP_0_ITP IRQ_TYPE_LEVEL_HIGH>, + <0 INTREQ_ITP_0_ITP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_0_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_1_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_DNS_0_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_1_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_ITSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "itp-itp-int0", + "itp-itp-cmdq-int", + "itp-dns-int0", + "itp-dns-int1", + "itp-dns-cmdq-int", + "itp-itsc-int0", + "itp-itsc-int1", + "itp-itsc-cmdq-int"; + interrupt-event-infos = + <&itp_itp_int0>, + <&itp_itp_cmdq_int>, + <&itp_dns_int0>, + <&itp_dns_int1>, + <&itp_dns_cmdq_int>, + <&itp_itsc_int0>, + <&itp_itsc_int1>, + <&itp_itsc_cmdq_int>; + + iommus = + <&sysmmu_dns>, + <&sysmmu_mcsc0>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + + transaction-thread-priority = <99>; + }; + + lwis_mcsc: lwis_mcsc@1B760000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "mcsc"; + + /* Register space */ + reg = + <0x0 0x1B760000 0x10000>, /* MCSC */ + <0x0 0x1B8C4000 0xA00>; /* SSMT D0 MCSC */ + reg-names = + "mcsc", + "ssmt_d0_mcsc"; + + clocks = <&clock UMUX_CLKCMU_MCSC_MCSC>; + clock-names = "UMUX_CLKCMU_MCSC_MCSC"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 IRQ_MCSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MCSC_1_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MCSC_0_MCSC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "mcsc-int0", + "mcsc-int1", + "mcsc-cmdq-int"; + interrupt-event-infos = + <&mcsc_int0>, + <&mcsc_int1>, + <&mcsc_cmdq_int>; + + iommus = + <&sysmmu_mcsc1>, + <&sysmmu_mcsc2>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_scsc: lwis_scsc@1D080000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "scsc"; + + /* Register space */ + reg = + <0x0 0x1D080000 0x10000>, /* SCSC */ + <0x0 0x1D204000 0xA00>; /* SSMT SCSC */ + reg-names = + "scsc", + "ssmt_d0_scsc"; + + clocks = <&clock UMUX_CLKCMU_GDC_SCSC>; + clock-names = "UMUX_CLKCMU_GDC_SCSC"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 IRQ_SCSC_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SCSC_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SCSC_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "scsc-int0", + "scsc-int1", + "scsc-cmdq-int"; + interrupt-event-infos = + <&scsc_int0>, + <&scsc_int1>, + <&scsc_cmdq_int>; + + iommus = <&sysmmu_gdc2>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_gdc0: lwis_gdc@1D040000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gdc0"; + + /* Register space */ + reg = + <0x0 0x1D040000 0x10000>, /* GDC0 */ + <0x0 0x1D134000 0xA00>; /* GDC0 SSMT */ + reg-names = + "gdc", + "gdc_ssmt"; + + clocks = <&clock UMUX_CLKCMU_GDC_GDC0>; + clock-names = "UMUX_CLKCMU_GDC_GDC0"; + clock-rates = <0>; + + clock-family = ; + + interrupts = + <0 IRQ_GDC0_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC0_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC0_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gdc-int0", + "gdc-int1", + "gdc-cmdq-int"; + interrupt-event-infos = + <&gdc_int0>, + <&gdc_int1>, + <&gdc_cmdq_int>; + + iommus = <&sysmmu_gdc0>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_gdc1: lwis_gdc@1D060000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "gdc1"; + + /* Register space */ + reg = + <0x0 0x1D060000 0x10000>, /* GDC1 */ + <0x0 0x1D144000 0xA00>; /* GDC1 SSMT */ + reg-names = + "gdc", + "gdc_ssmt"; + + clocks = <&clock UMUX_CLKCMU_GDC_GDC1>; + clock-names = "UMUX_CLKCMU_GDC_GDC1"; + clock-rates = <0>; + clock-family = ; + + interrupts = + <0 IRQ_GDC1_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC1_IRQ_1_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_GDC1_IRQ_0_GDC IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = + "gdc-int0", + "gdc-int1", + "gdc-cmdq-int"; + interrupt-event-infos = + <&gdc_int0>, + <&gdc_int1>, + <&gdc_cmdq_int>; + + iommus = <&sysmmu_gdc1>; + samsung,iommu-group = <&iommu_group_isp>; + samsung,tzmp = "true"; + }; + + lwis_votf: lwis_votf@1A4E0000 { + compatible = "google,lwis-ioreg-device"; + + /* Device node name */ + node-name = "votf"; + + /* Register space */ + reg = + <0x0 0x1A4E0000 0x10000>, /* CSIS C2SERV */ + <0x0 0x1AA70000 0x10000>, /* PDP C2SERV */ + <0x0 0x1B050000 0x10000>, /* DNS C2SERV */ + <0x0 0x1BC50000 0x10000>, /* TNR C2SERV */ + <0x0 0x1B750000 0x10000>, /* ITSC C2SERV */ + <0x0 0x1B770000 0x10000>, /* MCSC C2SERV */ + <0x0 0x1D050000 0x10000>, /* GDC0 C2SERV */ + <0x0 0x1D070000 0x10000>, /* GDC1 C2SERV */ + <0x0 0x1D090000 0x10000>; /* SCSC C2SERV */ + reg-names = + "csis-c2serv", + "pdp-c2serv", + "dns-c2serv", + "tnr-c2serv", + "itsc-c2serv", + "mcsc-c2serv", + "gdc0-c2serv", + "gdc1-c2serv", + "scsc-c2serv"; + + clocks = + <&clock UMUX_CLKCMU_CSIS_NOC>, + <&clock UMUX_CLKCMU_PDP_NOC>, + <&clock UMUX_CLKCMU_DNS_NOC>, + <&clock UMUX_CLKCMU_TNR_NOC>, + <&clock UMUX_CLKCMU_ITP_NOC>, + <&clock UMUX_CLKCMU_MCSC_ITSC>, + <&clock UMUX_CLKCMU_GDC_GDC0>, + <&clock UMUX_CLKCMU_GDC_GDC1>, + <&clock UMUX_CLKCMU_GDC_SCSC>; + clock-names = + "UMUX_CLKCMU_CSIS_NOC", + "UMUX_CLKCMU_PDP_NOC", + "UMUX_CLKCMU_DNS_NOC", + "UMUX_CLKCMU_TNR_NOC", + "UMUX_CLKCMU_ITP_NOC", + "UMUX_CLKCMU_MCSC_NOC", + "UMUX_CLKCMU_GDC_GDC0", + "UMUX_CLKCMU_GDC_GDC1", + "UMUX_CLKCMU_GDC_SCSC"; + clock-rates = <0>; + + iommus = + <&sysmmu_gdc0>, + <&sysmmu_gdc1>, + <&sysmmu_gdc2>, + <&sysmmu_ipp>, + <&sysmmu_dns>, + <&sysmmu_mcsc0>, + <&sysmmu_mcsc1>, + <&sysmmu_mcsc2>, + <&sysmmu_tnr0>, + <&sysmmu_tnr1>, + <&sysmmu_tnr2>, + <&sysmmu_tnr3>, + <&sysmmu_tnr4>, + <&sysmmu_csis0>, + <&sysmmu_csis1>; + samsung,iommu-group = <&iommu_group_isp>; + + power-domains = + <&pd_pdp>, + <&pd_csis>, + <&pd_gdc>, + <&pd_itp>, + <&pd_mcsc>, + <&pd_tnr>; + }; + + lwis_slc: lwis_slc@0 { + compatible = "google,lwis-slc-device"; + + /* Device node name */ + node-name = "slc"; + + /* SLC partitions */ + pt_id = + "CAMERA2WAY", + "CAMERA4WAY0", + "CAMERA4WAY1", + "CAMERA4WAY2", + "CAMERA6WAY0", + "CAMERA6WAY1", + "CAMERA6WAY2", + "CAMERA8WAY0"; + + pt_size = <512 1024 1024 1024 1536 1536 1536 2048>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ldaf.dtsi b/arch/arm64/boot/dts/google/gs201-ldaf.dtsi new file mode 100644 index 000000000000..3fab09e1b70e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ldaf.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 ldaf(Laser Detection Auto Focus) device tree source + * Copyright 2021 Google LLC. + * + */ + +#include + +&pinctrl_1 { + ldaf_irq: ldaf-irq { + samsung,pins = "gpa6-5"; /* XEINT_5 */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&hsi2c_1 { + /* VL53L1 */ + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + stmvl53l1: stmvl53l1@29 { + compatible = "st,stmvl53l1"; + reg = <0x29>; + /* XAPC_MCLK8: GPP17[0] */ + xsdn-gpio = <&gpp17 0 GPIO_ACTIVE_LOW>; + /* XAPC_USI4_CTSn_CSn: GPP8[3] */ + pwren-gpio = <&gpp8 3 GPIO_ACTIVE_HIGH>; + /* XEINT_5: GPA6[5] */ + intr-gpio = <&gpa6 5 GPIO_ACTIVE_LOW>; + + vio-type = "regulator"; + vio-supply = <&s_ldo12_reg>; + vio-voltage = <1800000>; + + pinctrl-names = "default"; + pinctrl-0 = <&ldaf_irq>; + + status = "ok"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-max20339-ovp.dtsi b/arch/arm64/boot/dts/google/gs201-max20339-ovp.dtsi new file mode 100644 index 000000000000..f6c74c3ec1a6 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-max20339-ovp.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021, Google LLC + * + * MAX20339 OVP device node. + */ +#include +#include + +&hsi2c_13{ + #address-cells = <1>; + #size-cells = <0>; + + max20339_ovp: max20339ovp@35 { + status = "okay"; + compatible = "max20339ovp"; + reg = <0x35>; + + /* OVP interrupt on MW pmic GPIO6 */ + max20339,irq-gpio = <&max777x9_gpio 5 GPIO_ACTIVE_LOW>; + + /* LoadSwitch 1 and LoadSwitch 2 mapped as gpios. */ + max20339_gpio: max20339_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; +}; + +&max77759tcpc { + /delete-property/ ovp-present; + in-switch-gpio = <&max20339_gpio 4 GPIO_ACTIVE_HIGH>; + max20339,ovp = <&max20339_ovp>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-mfc.dtsi b/arch/arm64/boot/dts/google/gs201-mfc.dtsi new file mode 100644 index 000000000000..3449985b65e8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-mfc.dtsi @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * SAMSUNG EXYNOS SoC mfc device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#include + +/ { + mfc: mfc { + /* Basic setting */ + compatible = "samsung,exynos-mfc"; + + /* for vb2 device */ + iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>; + samsung,iommu-group = <&iommu_group_mfc>; + samsung,iommu-reserved-map = <0x0 0x0 0x10000000>, + <0x0 0x10000000 0x100000>; + /* Enable if there is vOTF */ + /* samsung,iommu-identity-map = <0x0 0x15E1F000 0x10000>; */ + + samsung,tzmp; + + /* MFC version */ + /* ip_ver is set in gs101-a0.dts and gs101-b0.dts */ + + /* Debug mode (disable needs sysmmu,async-fault) */ + debug_mode = <0>; + + /* NAL-Q size */ + nal_q_entry_size = <512>; + nal_q_dump_size = <376>; + + /* Features */ + nal_q = <1 0x0>; + skype = <1 0x0>; + black_bar = <0 0x0>; + color_aspect_dec = <1 0x0>; + static_info_dec = <1 0x0>; + color_aspect_enc = <1 0x0>; + static_info_enc = <1 0x180314>; + hdr10_plus = <1 0x180709>; + vp9_stride_align = <1 0x0>; + sbwc_uncomp = <1 0x190702>; + mem_clear = <1 0x0>; + /* Support from v11.0 (except 11.2) */ + wait_fw_status = <1 0x190122>; + wait_nalq_status = <1 0x191107>; + /* DRM switch predict for cache flush */ + drm_switch_predict = <1 0x0>; + /* Support SBWC per-frame control for encoder src */ + sbwc_enc_src_ctrl = <1 0x200110>; + average_qp = <1 0x201030>; + mv_search_mode = <1 0x201118>; + enc_idr_flag = <1 0x210614>; + min_quality_mode = <1 0x210629>; + + /* AV1 Decoder */ + support_av1_dec = <0>; + /* Support AV1 Film Grain Feature */ + av1_film_grain = <0 0>; + + /* Default 10bit format for decoding (1: P010, 0: 8+2) */ + P010_decoding = <1>; + /* Dithering option for 8bit display device */ + dithering_enable = <0>; + /* Decoder stride align (default: 16) */ + stride_align = <64>; + /* Decoder stride calculation type (new: 1, old: 0) */ + stride_type = <1>; + + /* Formats */ + support_10bit = <1>; + support_422 = <1>; + support_rgb = <1>; + + /* SBWC */ + support_sbwc = <1>; + support_sbwcl = <1>; + support_afbc = <1>; + + /* SBWC decoder max resolution */ + sbwc_dec_max_width = <1920>; + sbwc_dec_max_height = <1088>; + sbwc_dec_hdr10_off = <1>; + + /* HDR10+ num max window */ + max_hdr_win = <1>; + + /* error type for sync_point display */ + /* (1: concealment display, 2: error display, 3: error no display) */ + display_err_type = <2>; + + /* FW base security ctrl */ + /* security_ctrl is set in gs101-a0.dts and gs101-b0.dts */ + + /* Encoder min bit count control */ + enc_min_bit_cnt = <1>; + + /* Encoder default parameter: max number is 100 */ + enc_param_num = <25>; + enc_param_addr = <0xF7B4 0xF7B8 0xF7B0 0xF798 0xFA2C + 0xF790 0xFA34 0xFA38 0xFA3C 0xF7C0 + 0xF7C8 0xF7CC 0xFA60 0xFDD4 0xFDDC + 0xFB54 0xFB58 0xFBA8 0xFD90 0xFD94 + 0xFD40 0xFD48 0xFD4C 0xFD50 0xFD80>; + enc_param_val = <0x100 0x100 0x0 0x4000 0x3FD00 + 0x0 0x0 0x2710 0x3E8 0x0 + 0x0 0x0 0x0 0x8050F215 0x0 + 0x3011 0x0 0x0 0x2D 0xA00 + 0x1D 0xF4240 0x33003300 0x2 0x1>; + + /* BW : KB/UHD frame */ + bw_enc_h264 = <45456 56112 11170>; + bw_enc_hevc = <46756 52766 9763>; + bw_enc_hevc_10bit = <53865 64753 12556>; + bw_enc_vp8 = <64000 67318 22518>; + bw_enc_vp9 = <72326 59726 16530>; + bw_enc_vp9_10bit = <149085 114928 31419>; + bw_enc_mpeg4 = <44647 55324 9531>; + bw_dec_h264 = <32605 34381 21263>; + bw_dec_hevc = <29973 28851 17538>; + bw_dec_hevc_10bit = <52859 46245 31351>; + bw_dec_vp8 = <28672 30468 22324>; + bw_dec_vp9 = <18351 18947 16877>; + bw_dec_vp9_10bit = <42384 34452 31766>; + bw_dec_av1 = <23787 19570 15856>; + bw_dec_av1_10bit = <41407 35490 29699>; + bw_dec_mpeg4 = <31540 25368 15770>; + + /* BW : KB/UHD frame. For SBWC format */ + /* It is valid when only support_sbwc = <1> */ + sbwc_bw_enc_h264 = <31622 32183 7065>; + sbwc_bw_enc_hevc = <24044 27526 5888>; + sbwc_bw_enc_hevc_10bit = <32666 37594 8841>; + sbwc_bw_enc_vp8 = <32666 37594 8841>; + sbwc_bw_enc_vp9 = <23276 26884 8702>; + sbwc_bw_enc_vp9_10bit = <42302 41116 14052>; + sbwc_bw_enc_mpeg4 = <32666 37594 8841>; + sbwc_bw_dec_h264 = <23757 18603 13620>; + sbwc_bw_dec_hevc = <15309 15387 10279>; + sbwc_bw_dec_hevc_10bit = <20808 20602 14868>; + sbwc_bw_dec_vp8 = <17203 18281 13394>; + sbwc_bw_dec_vp9 = <11121 9691 8999>; + sbwc_bw_dec_vp9_10bit = <17787 15582 14413>; + sbwc_bw_dec_mpeg4 = <18924 15221 9462>; + + /* BW : KB/UHD frame. For recon DPB only SBWC format */ + /* It is valid when only support_sbwc = <1> */ + dpb_sbwc_bw_enc_h264 = <36230 36791 7065>; + dpb_sbwc_bw_enc_hevc = <28662 32144 5888>; + dpb_sbwc_bw_enc_hevc_10bit = <46613 51541 8841>; + dpb_sbwc_bw_enc_vp9 = <26747 31502 8702>; + dpb_sbwc_bw_enc_vp9_10bit = <42302 55063 14052>; + + /* QoS bitrate */ + num_mfc_freq = <5>; + mfc_freqs = <134000 267000 400000 534000 666000>; + /* spec: H264(240M) VP8(80M) */ + max_Kbps = <245760 81920>; + + /* QoS weight (%) */ + qos_weight_h264_hevc = <100>; + qos_weight_vp8_vp9 = <100>; + qos_weight_other_codec = <25>; + qos_weight_3plane = <80>; + qos_weight_10bit = <75>; + qos_weight_422 = <70>; + qos_weight_bframe = <50>; + qos_weight_num_of_ref = <60>; + qos_weight_gpb = <50>; + qos_weight_num_of_tile = <75>; + qos_weight_super64_bframe = <60>; + + /* core balance(%) for resource managing */ + core_balance = <100>; + + /* MFC IOVA threshold (MB) */ + iova_threshold = <0>; + + /* need control for mfc idle clock */ + idle_clk_ctrl = <0>; + + /* Encoder RGB CSC formula by VUI from F/W */ + enc_rgb_csc_by_fw = <1>; + + /* Sub nodes for MFC core */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + + /* MFC core device */ + mfc_core0: MFC-0 { + /* Basic setting */ + compatible = "samsung,exynos-mfc-core"; + id = <0>; + reg = <0x0 0x1C8D0000 0x10000>; + interrupts = <0 IRQ_MFC_MFC IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_mfc"; + clocks = <&clock GATE_MFC>; + iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>; + samsung,iommu-group = <&iommu_group_mfc>; + samsung,iommu-reserved-map = <0x0 0x10000000 0x100000>; + /* samsung,iommu-identity-map = <0x0 0x15E1F000 0x10000> */ + + samsung,tzmp; + samsung,imgloader-s2mpu-support; + + /* MFC version */ + /* ip_ver is set in gs101-a0.dts and gs101-b0.dts */ + + /* Sysmmu check */ + share_sysmmu = <0>; + axid_mask = <0xFFFF>; + mfc_fault_num = <0x0>; + trans_info_offset = <0x1004>; + + /* LLC (Last Level Cache) */ + llc = <0>; + need_llc_flush = <0>; + + /* SLC (System Level Cache) */ + pt_id = "MFC"; + + /* vOTF */ + /* mfc_votf_base = <0x16650000>; */ + /* gdc_votf_base = <0x15E1F000>; */ + /* dpu_votf_base = <0x19CAF000>; */ + + /* QoS */ + num_default_qos_steps = <8>; + num_encoder_qos_steps = <8>; + max_mb = <5480873>; + mfc_freq_control = <1>; + mo_control = <1>; + bw_control = <1>; + + /* Device virtual address */ + #dma-address-cells = <1>; + #dma-size-cells = <1>; + dma-window = <0x0 0xFFFFFFFF>; + + /* Sub nodes for sysmmu, hwfc and mmcache */ + #address-cells = <2>; + #size-cells = <1>; + ranges; + + iommu { + reg = <0x0 0x1C870000 0x9000>, + <0x0 0x1C8A0000 0x9000>; + }; + ssmt { + reg = <0x0 0x1C8E4000 0x100>, + <0x0 0x1C8F4000 0x100>; + }; + sysreg { + reg = <0x0 0x1C820000 0x500>; + }; + + /* Default QoS table */ + mfc_default_qos_table { + mfc_d_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <134000>; + freq_int = <100000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <2058>; + }; + mfc_d_qos_variant_1 { + thrd_mb = <265147>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1379>; + }; + mfc_d_qos_variant_2 { + thrd_mb = <551811>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <676000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1046>; + }; + mfc_d_qos_variant_3 { + thrd_mb = <1202239>; + freq_mfc = <356000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <732>; + }; + mfc_d_qos_variant_4 { + thrd_mb = <1887335>; + freq_mfc = <465000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <655>; + }; + mfc_d_qos_variant_5 { + thrd_mb = <2088750>; + freq_mfc = <664000>; + freq_int = <332000>; + freq_mif = <1539000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_uhd"; + time_fw = <479>; + }; + mfc_d_qos_variant_6 { + thrd_mb = <3197754>; + freq_mfc = <664000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <1>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_uhd_10bit"; + time_fw = <445>; + }; + mfc_d_qos_variant_7 { + thrd_mb = <4385292>; + freq_mfc = <711000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <1>; + mo_uhd_enc60_value = <0>; + bts_scen = "mfc_8k_dec30"; + time_fw = <445>; + }; + }; + + /* Encoder QoS table */ + mfc_encoder_qos_table { + mfc_e_qos_variant_0 { + thrd_mb = <0>; + freq_mfc = <134000>; + freq_int = <100000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <2058>; + }; + mfc_e_qos_variant_1 { + thrd_mb = <265147>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <421000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1379>; + }; + mfc_e_qos_variant_2 { + thrd_mb = <551811>; + freq_mfc = <267000>; + freq_int = <200000>; + freq_mif = <676000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <1046>; + }; + mfc_e_qos_variant_3 { + thrd_mb = <1202239>; + freq_mfc = <356000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <732>; + }; + mfc_e_qos_variant_4 { + thrd_mb = <1887335>; + freq_mfc = <465000>; + freq_int = <332000>; + freq_mif = <1014000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <655>; + }; + mfc_e_qos_variant_5 { + thrd_mb = <2088750>; + freq_mfc = <533000>; + freq_int = <200000>; + freq_mif = <1539000>; + mo_value = <1>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <0>; + bts_scen = "default"; + time_fw = <559>; + }; + mfc_e_qos_variant_6 { + thrd_mb = <2625764>; + freq_mfc = <664000>; + freq_int = <332000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <1>; + bts_scen = "mfc_uhd"; + time_fw = <479>; + }; + mfc_e_qos_variant_7 { + thrd_mb = <3197754>; + freq_mfc = <664000>; + freq_int = <533000>; + freq_mif = <1539000>; + mo_value = <0>; + mo_10bit_value = <0>; + mo_uhd_enc60_value = <1>; + bts_scen = "mfc_uhd_10bit"; + time_fw = <445>; + }; + }; + /* QoS table for performance boost mode */ + mfc_perf_boost_table { + num_cluster = <3>; + freq_cluster = <1742000 1898000 1456000>; + freq_mfc = <711000>; + freq_int = <533000>; + freq_mif = <2730000>; + bts_scen = "mfc_8k_dec30"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-mmc.dtsi b/arch/arm64/boot/dts/google/gs201-mmc.dtsi new file mode 100644 index 000000000000..9c0c1b9045f5 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-mmc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC MMC device tree source + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd + * + */ + +/{ + aliases { + mshc2 = &dwmmc_2; + }; + + dwmmc_2: dwmmc2@14620000 { + compatible = "samsung,exynos-dw-mshc"; + reg = <0x0 0x14620000 0x2000>; + reg-names = "dw_mmc"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + /* + * clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>; + * clock-names = "ciu", "ciu_gate"; + */ + status = "disabled"; + num-slots = <1>; + fixed_voltage; + non-removable; + supports-4bit; + supports-cmd23; + supports-erase; + supports-highspeed; + bypass-for-allpass; + use-fine-tuning; + /* + * card-init-hwacg-ctrl; + */ + fifo-depth = <0x40>; + desc-size = <4>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + clock-frequency = <800000000>; + samsung,dw-mshc-sdr-timing = <3 0 2 0>; + samsung,dw-mshc-ddr-timing = <3 0 2 1>; + num-ref-clks = <9>; + ciu_clkin = <25 50 50 25 50 100 200 50 50>; + /* Swapping clock drive strength */ + clk-drive-number = <6>; + slot@0 { + reg = <0>; + bus-width = <4>; + disable-wp; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pantah-camera-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-pantah-camera-pmic.dtsi new file mode 100644 index 000000000000..50211daafe27 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pantah-camera-pmic.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 camera PMIC device tree for pantah + * + * Copyright 2021 Google LLC. + * + */ + +#include + +&hsi2c_8 { + /* SLG51002 */ + status = "ok"; + #address-cells = <1>; + #size-cells = <0>; + slg51002: slg51002@75 { + compatible = "dlg,slg51002"; + reg = <0x75>; + status = "ok"; + dlg,buck-gpios = <&s2mpg13_gpio 3 GPIO_ACTIVE_HIGH>; + dlg,bb-gpios = <&s2mpg13_gpio 1 GPIO_ACTIVE_HIGH>; + dlg,cs-gpios = <&s2mpg13_gpio 0 GPIO_ACTIVE_HIGH>; + dlg,reg-init-cells = <2>; + + regulators { + slg51002_ldo1: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51002_ldo2: ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51002_ldo3: ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51002_ldo4: ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51002_ldo5: ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51002_ldo6: ldo6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_ldo7: ldo7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_ldo8: ldo8 { + regulator-name = "ldo8"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_gpio1: gpio1 { + regulator-name = "gpio1"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_gpio2: gpio2 { + regulator-name = "gpio2"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_gpio3: gpio3 { + regulator-name = "gpio3"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + + slg51002_gpio4: gpio4 { + regulator-name = "gpio4"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1675000>; + }; + }; + + slg51002_gpio: slg51002_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + gpio-ranges = <&slg51002_pinctrl 0 0 8>; + }; + + slg51002_pinctrl: slg51002_pinctrl { + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pantah-charging.dtsi b/arch/arm64/boot/dts/google/gs201-pantah-charging.dtsi new file mode 100644 index 000000000000..2ee43fb9b76d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pantah-charging.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to panther/cheetah + * + * Copyright 2021 Google,LLC + * + */ + +/ { + fragment@charging { + target-path = "/"; + __overlay__ { + + google_cpm: google,cpm { + status = "okay"; + compatible = "google,cpm"; + #cooling-cells = <2>; + + google,chg-power-supplies = "main-charger", // out-0 + "pca94xx-mains"; // out-1 + + /* S2MPG12X01 -> GPIO_1 -> CHARGE_PUMP_EN */ + google,dc-en = <&s2mpg12_gpio 1 0>; + /* DC enabled by default */ + google,dc-en-value = <1>; + google,dc_limit-demand = <560000>; + google,dc_limit-vbatt = <4350000>; + google,dc_limit-vbatt_min = <3400000>; + + google,tcpm-power-supply = <&max77759tcpc>; // in=0 + google,wlc_dc-power-supply = "wireless"; // in=1 + google,pps-awake; + }; + + google_charger: google,charger { + status = "okay"; + compatible = "google,charger"; + #cooling-cells = <2>; + + google,chg-power-supply = "gcpm"; + google,bat-power-supply = "battery"; + google,usb-power-supply = "usb"; + google,tcpm-power-supply = <&max77759tcpc>; + + google,fv-max-uv = <4450000>; + + google,wlc-thermal-mitigation = <1100000 500000 250000 110000>; + google,therm-wlc-overrides-fcc; + + /* b/170700459 thresholds, updated in b/191070950 */ + google,bd-resume-abs-temp = <280>; + google,bd-resume-soc = <50>; + google,bd-resume-time = <14400>; /* 4 hours */ + google,bd-resume-temp = <290>; + google,bd-trigger-time = <21600>; /* 6 hours */ + google,bd-trigger-temp = <350>; + google,bd-trigger-voltage = <4270000>; + google,bd-recharge-voltage = <4250000>; + google,bd-drainto-soc = <80>; + google,bd-recharge-soc = <79>; + /* Enable TEMP-DEFEND */ + google,bd-temp-enable; + google,bd-temp-dry-run; + + google,chg-termination-5v; + }; + + google_bms { + nvmem = <&pack_bee>; + }; + + google_wlc_charger: google,wlc_charger { + #cooling-cells = <2>; + }; + + google_wlc_fcc_charger: google,wlc_fcc_charger { + #cooling-cells = <2>; + }; + + google_mdis_charger: google,mdis_charger { + #cooling-cells = <2>; + }; + + }; + }; +}; + +&pinctrl_0 { + + dc_charger_irq: dc-charger-irq { + samsung,pins = "gpa9-0"; /* XEINT_20 (PLC_INT_L) */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + + +&max77759_chg { + max77759,psy-name = "main-charger"; +}; + +&hsi2c_13 { + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + clock-frequency = <400000>; + + pca9468_dc: pca9468@57 { + compatible = "nxp,pca9468"; + reg = <0x57>; + + pca9468,psy_name = "pca94xx-mains"; + + pinctrl-names = "default"; + pinctrl-0 = <&dc_charger_irq>; + + interrupt-parent = <&gpa9>; + pca9468,irq-gpio = <&gpa9 0 GPIO_ACTIVE_LOW>; /* PLC_INT_L */ + + pca9468,float-voltage = <4300000>; /* 4.3V */ + + pca9468,input-itopoff = <500000>; /* 500mA */ + pca9468,sense-resistance = <0>; /* 5mOhm */ + pca9468,switching-frequency = <3>; /* 980KHz */ + + /* disable USBC NTC */ + pca9468,ntc-threshold = <0>; /* disabled */ + + /* USBC thermal zone */ + google,usb-port-tz-name = "usbc-therm-adc"; + + /* irdrop */ + google,irdrop-limits = <105000 75000 0>; + + pca9468,google_cpm = <&google_cpm>; + }; + +}; diff --git a/arch/arm64/boot/dts/google/gs201-pantah-pmic-odpm-1.dtsi b/arch/arm64/boot/dts/google/gs201-pantah-pmic-odpm-1.dtsi new file mode 100644 index 000000000000..cf495d7de919 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pantah-pmic-odpm-1.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 pmic odpm device tree source + * + * Copyright 2021 Google LLC. + * + */ + +&s_ext6_rail { + schematic-name = "VSYS_PWR_CAM"; + subsys-name = "Camera"; +}; + +/* replace L9S_GNSS_CORE to VSYS_PWR_CAM */ +&ch15 { + rail-name = "VSEN_C6"; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/google/gs201-pantah-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-pantah-pmic.dtsi new file mode 100644 index 000000000000..a95369e38ec5 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pantah-pmic.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pantah pmic device tree source + * + * Copyright 2021 Google LLC. + * + */ + +&m_ldo23_reg { + schematic-name = "L23M_SPARE"; + subsys-name = "Spare"; +}; + +&m_ldo24_reg { + schematic-name = "L24M_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo4_reg { + schematic-name = "L4S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo6_reg { + schematic-name = "L6S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo7_reg { + schematic-name = "L7S_SENSORS"; +}; + +&s_ldo8_reg { + schematic-name = "L8S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo12_reg { + schematic-name = "L12S_CAMIO"; + subsys-name = "Multimedia"; +}; + +&s_ldo14_reg { + schematic-name = "L14S_ALIVE"; + subsys-name = "Alive"; +}; + +&s_ldo15_reg { + schematic-name = "L15S_UDFPS_AVDD"; +}; + +&s_ldo20_reg { + schematic-name = "L20S_DMIC2"; + subsys-name = "DMIC"; +}; + +&s_ldo22_reg { + schematic-name = "L22S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo26_reg { + schematic-name = "L26S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo27_reg { + schematic-name = "L27S_SPARE"; + subsys-name = "Spare"; +}; + +&s_ldo28_reg { + schematic-name = "L28S_SPARE"; + subsys-name = "Spare"; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-pantah-wcharger.dtsi b/arch/arm64/boot/dts/google/gs201-pantah-wcharger.dtsi new file mode 100644 index 000000000000..3d7c9e64f35e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pantah-wcharger.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2022 Google Inc. + */ + +#include +#include + +/ { + fragment@wlc { + target-path = "/"; + __overlay__ { + google,charger { + google,wlc-power-supply = "wireless"; + }; + }; + }; +}; + +&pinctrl_0 { + /* XIENT_25 P9412 Wireless Charger Interrupt */ + wc_irq: wc_irq { + samsung,pins = "gpa9-5"; /* QI_INT_R */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_4 { + /* XAPC_GPIO0 P9412 Wireless Charger Enable */ + wc_en: wc_en { + samsung,pins = "gpp0-0"; /* QI_EN_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&hsi2c_15 { + p9412@3c { + dev-name = "p9412"; + compatible = "idt,p9412"; + reg = <0x3c>; + status = "ok"; + + /* RTX: configure boost to 7V through wlc chip */ + idt,apbst_en; + + /* Granvilla GPIO 2~4 */ + idt,gpio_ben = <&max777x9_gpio 4 GPIO_ACTIVE_HIGH>; /* EXT_BST_EN */ + idt,gpio_boost = <&s2mpg12_gpio 3 GPIO_ACTIVE_HIGH>; /* WLC_TX_SW_EN */ + /* idt,gpio_switch = <&p9xxx_gpio 3 GPIO_ACTIVE_HIGH>; */ /* EXT_BST_VTRX */ + idt,gpio_extben = <&s2mpg12_gpio 2 GPIO_ACTIVE_HIGH>; /* AP2QI_EXTBST_EN */ + /* CSP */ + idt,fuel-gauge = <&max77759_fg>; + + /* WLCDC */ + idt,gpio_dc_switch = <&s2mpg12_gpio 0 GPIO_ACTIVE_HIGH>; /* WLC_RX_SW_EN */ + idt,max_vout_mv = <19500>; + idt,has_wlc_dc = <1>; + google,power_mitigate_threshold = <90>; + google,has-sw-ramp; + + pinctrl-names = "default"; + pinctrl-0 = <&wc_irq &wc_en>; + + idt,gpio_wlc_en = <&gpp0 0 GPIO_ACTIVE_LOW>; + /* idt,gpio_qi_vbus_en = ; always high after boot */ + idt,gpio_qien = <&gpp0 0 GPIO_ACTIVE_LOW>; + idt,irq_gpio = <&gpa9 5 GPIO_ACTIVE_LOW>; + + /* TXID: Phone type */ + idt,tx_id_phone_type = /bits/ 8 <3>; + + p9xxx_gpio: p9xxx_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-audio.dtsi b/arch/arm64/boot/dts/google/gs201-panther-audio.dtsi new file mode 100644 index 000000000000..2fa690d79f77 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-audio.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Panther common audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * + * cs35l41_l = top + * cs35l41_r = bottom + */ +#include +#include +#include + +&aoc { + aoc-board-cfg = "P10"; + aoc-board-id = <0x30401>; + aoc-board-rev = <0x10000>; +}; + +&dai_be_tdm0_rx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&dai_be_tdm0_tx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs35l41_l { + comp = <&cs35l41_l>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + + sys@cs35l41_r { + comp = <&cs35l41_r>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + cs35l41_l_irq: cs35l41-l-irq { + samsung,pins = "gpa6-3"; /* XEINT_3 - AMP1_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_irq: cs35l41-r-irq { + samsung,pins = "gpa8-6"; /* XEINT_18 - AMP2_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +/* GPIO_PERIC0 */ +&pinctrl_4 { + cs35l41_clk: cs35l41-clk { + samsung,pins = "gpp14-0"; /* XAPC_USI7_RXD_CLK_SCL - AUDIO_SPI_CLK */ + samsung,pin-drv = ; + }; + + cs35l41_mosi: cs35l41-mosi { + samsung,pins = "gpp14-1"; /* XAPC_USI7_TXD_DO_SDA - AUDIO_SPI_MOSI */ + samsung,pin-drv = ; + }; + + cs35l41_miso: cs35l41-miso { + samsung,pins = "gpp14-2"; /* XAPC_USI7_RTSn_DI - AUDIO_SPI_MISO */ + samsung,pin-pud = ; + }; + + cs35l41_cs1: cs35l41-cs1 { + samsung,pins = "gpp14-3"; /* XAPC_USI7_CTSN_CSN - AUDIO_AMP1_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_l_rst: cs35l41-l-rst { + samsung,pins = "gpp17-1"; /* XAPC_VSYNC8 - AMP1_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + cs35l41_cs2: cs35l41-cs2 { + samsung,pins = "gpp22-1"; /* XAPC_GPIO5 - AUDIO_AMP2_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_rst: cs35l41-r-rst { + samsung,pins = "gpp25-2"; /* XAPC_USI13_RTSn_DI - AMP2_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi7_cs_func { + samsung,pins = "gpp14-3"; + samsung,pin-drv = ; +}; + +&spi_7 { + /* XAPC_USI7 */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus &spi7_cs_func &cs35l41_cs2 + &cs35l41_miso &cs35l41_mosi &cs35l41_clk>; + cs-gpios = <&gpp14 3 GPIO_ACTIVE_HIGH>, <&gpp22 1 GPIO_ACTIVE_HIGH>; + + cs35l41_l: cs35l41@0 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <0>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_l_irq &cs35l41_l_rst>; + + interrupt-parent = <&gpa6>; + interrupts = <3 0 0>; + + reset-gpios = <&gpp17 1 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + cirrus,hibernate-enable; + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio = <&gpp14 3 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; + + + cs35l41_r: cs35l41@1 { + #sound-dai-cells = <1>; + sound-name-prefix = "R"; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <1>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_r_irq &cs35l41_r_rst>; + + interrupt-parent = <&gpa8>; + interrupts = <6 0 0>; + + reset-gpios = <&gpp25 2 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + cirrus,hibernate-enable; + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio =<&gpp22 1 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-battery-data.dtsi b/arch/arm64/boot/dts/google/gs201-panther-battery-data.dtsi new file mode 100644 index 000000000000..0adce8169b3e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-battery-data.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries + * + * Copyright 2021 Google LLC + * + */ + +maxim,config { + + /* R4_p1_gen.ini, 2021-01-21, b/174787673, generic model */ + maxim,default-a1-0k { + maxim,batt-id-kohm = <0>; + maxim,model-version = <0>; + maxim,fg-model = /bits/ 16 < + 0x9760 0xa510 0xb100 0xb600 0xb7a0 0xb900 0xba70 0xbc70 + 0xbde0 0xbfc0 0xc250 0xc510 0xc990 0xcea0 0xd040 0xd750 + 0x0060 0x0120 0x0200 0x0710 0x0e80 0x0df0 0x1430 0x1bd0 + 0x1520 0x0d70 0x0950 0x08e0 0x0800 0x0780 0x06b0 0x01e0 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 0x0100 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x2038 /* RelaxCFG */ + /* 0x0028 */ 0x260E /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5F00 /* FullSOCthr */ + /* 0x0035 */ 0x0994 /* FullCAPRep */ + /* 0x0018 */ 0x0994 /* DesignCap */ + /* 0x0046 */ 0x0c80 /* dPacc */ + /* 0x0045 */ 0x0099 /* dQacc */ + /* 0x0023 */ 0x0994 /* FullCAPNom */ + /* 0x003A */ 0xA561 /* V_empty */ + /* 0x0012 */ 0x1100 /* QResidual00 */ + /* 0x0022 */ 0x0800 /* QResidual10 */ + /* 0x0032 */ 0x0301 /* QResidual20 */ + /* 0x0042 */ 0x0302 /* QResidual30 */ + /* 0x0038 */ 0x0700 /* RCOMP0 */ + /* 0x0039 */ 0x223E /* TempCo */ + /* 0x001E */ 0x0310 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x0000 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0xc623 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; + + /* ATL: 1_ATL_3197_021422_BC59_RC2_0217.txt, 2022-03-04, b/222603623#comment1 */ + maxim,cos-a1-1k { + maxim,batt-id-kohm = <1>; + maxim,model-version = <2>; + maxim,force-reset-model-data; + maxim,fg-model = /bits/ 16 < + 0x8c80 0xb770 0xb8f0 0xba50 0xbb40 0xbc30 0xbe00 0xbfd0 + 0xc1b0 0xc3a0 0xc6b0 0xc9c0 0xd020 0xd300 0xd5e0 0xdc30 + 0x0080 0x1070 0x1020 0x0ed0 0x0f00 0x1700 0x1530 0x0c20 + 0x0c40 0x07f0 0x07f0 0x06f0 0x0710 0x06d0 0x06f0 0x06f0 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x0839 /* RelaxCFG */ + /* 0x0028 */ 0x260e /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5f00 /* FullSOCthr */ + /* 0x0035 */ 0x0873 /* FullCAPRep */ + /* 0x0018 */ 0x0873 /* DesignCap */ + /* 0x0046 */ 0x3200 /* dPacc */ + /* 0x0045 */ 0x021c /* dQacc */ + /* 0x0023 */ 0x0873 /* FullCAPNom */ + /* 0x003A */ 0xa561 /* V_empty */ + /* 0x0012 */ 0x1f00 /* QResidual00 */ + /* 0x0022 */ 0x0d80 /* QResidual10 */ + /* 0x0032 */ 0x0480 /* QResidual20 */ + /* 0x0042 */ 0x0400 /* QResidual30 */ + /* 0x0038 */ 0x0740 /* RCOMP0 */ + /* 0x0039 */ 0x1a02 /* TempCo */ + /* 0x001E */ 0x0557 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x1900 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0xc613 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; + + /* LSN: 3_LSN_3198_021422_BC59_RC2_0217.txt, 2022-03-04, b/222603623#comment1 */ + maxim,lsn-a1-3k { + maxim,batt-id-kohm = <3>; + maxim,model-version = <2>; + maxim,force-reset-model-data; + maxim,fg-model = /bits/ 16 < + 0xa4f0 0xb750 0xb8b0 0xba50 0xbbe0 0xbd60 0xbe70 0xbf80 + 0xc170 0xc320 0xc960 0xced0 0xd210 0xd580 0xd8a0 0xdc60 + 0x0160 0x0f30 0x0e00 0x1210 0x1500 0x1800 0x1520 0x0da0 + 0x0be0 0x07f0 0x06c0 0x06f0 0x06e0 0x06f0 0x05f0 0x05f0 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 0x0200 + >; + maxim,fg-params = /bits/ 16 < + /* 0x0036 */ 0xf060 /* IAvgEmpty */ + /* 0x002a */ 0x0839 /* RelaxCFG */ + /* 0x0028 */ 0x260e /* LearnCFG */ + /* 0x001D */ 0x4217 /* Config */ + /* 0x00BB */ 0x0090 /* Config2 */ + /* 0x0013 */ 0x5f00 /* FullSOCthr */ + /* 0x0035 */ 0x0891 /* FullCAPRep */ + /* 0x0018 */ 0x0891 /* DesignCap */ + /* 0x0046 */ 0x3200 /* dPacc */ + /* 0x0045 */ 0x0224 /* dQacc */ + /* 0x0023 */ 0x0891 /* FullCAPNom */ + /* 0x003A */ 0xa561 /* V_empty */ + /* 0x0012 */ 0x2500 /* QResidual00 */ + /* 0x0022 */ 0x1180 /* QResidual10 */ + /* 0x0032 */ 0x0780 /* QResidual20 */ + /* 0x0042 */ 0x0580 /* QResidual30 */ + /* 0x0038 */ 0x0740 /* RCOMP0 */ + /* 0x0039 */ 0x1802 /* TempCo */ + /* 0x001E */ 0x0557 /* ICHGTerm */ + /* 0x002C */ 0xED51 /* TGain */ + /* 0x002D */ 0x1EBA /* TOff */ + /* 0x00B9 */ 0x0014 /* Curve */ + /* 0x002B */ 0x3870 /* MiscCFG */ + /* 0x0004 */ 0x1900 /* AtRate */ + /* 0x0049 */ 0x2241 /* convgcfg */ + /* 0x0029 */ 0xc613 /* FilterCFG */ + /* 0x003c */ 0x2D00 /* TaskPeriod */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-battery.dtsi b/arch/arm64/boot/dts/google/gs201-panther-battery.dtsi new file mode 100644 index 000000000000..0ecf904c3011 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-battery.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to panther + * + * Copyright 2021 Google,LLC + * + */ + +&google_battery { + google,chg-battery-capacity = <4277>; +}; + +&max77759_fg { + /delete-property/ maxim,force-batt-id; + + maxim,filtercfg-temp = <100>; + maxim,filtercfg-temp-hysteresis = <30>; + maxim,filtercfg-default = /bits/ 16 <0xc613>; + maxim,filtercfg-adjust = /bits/ 16 <0xc617>; + + maxim,fg-data { + #include "gs201-panther-battery-data.dtsi" + }; +}; + +/ { + fragment@battery { + target-path = "/"; + __overlay__ { + google_battery: google,battery { + google,ttf-temp-idx= <2>; + google,ttf-adapter = <3000>; + google,ttf-soc-table = <49 57 74 77 87 89 91 93 96 100>; + google,ttf-elap-table = <39 44 57 76 75 84 96 114 150 203>; + google,ttf-tier-table = <0 57 77>; + + google,aacr-disable; + + google,batt-id-1-atl { + google,batt-id = <1>; + google,aacr-ref-cycles = <100 200 300 400 500 600 700>; + google,aacr-ref-fade10 = < 2 15 26 36 46 54 63>; + }; + + google,batt-id-3-lsn { + google,batt-id = <3>; + google,aacr-ref-cycles = <200 300 400 500 600 700 800>; + google,aacr-ref-fade10 = < 7 20 31 41 51 60 69>; + }; + }; + + google_bms { + nvmem-names = "6-00500"; + /* pack eeprom is available only with P20+ batteries */ + google,bee-name = "6-00500"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-camera.dtsi b/arch/arm64/boot/dts/google/gs201-panther-camera.dtsi new file mode 100644 index 000000000000..99d6f1497444 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-camera.dtsi @@ -0,0 +1,702 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 camera lwis device tree for cheetah + * + * Copyright 2021 Google LLC. + * + */ + +#include +#include +#include + +&slg51002_ldo1 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&slg51002_ldo2 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&slg51002_ldo3 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + +&slg51002_ldo4 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + +&slg51002_ldo5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&slg51002_ldo6 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; +}; + +&slg51002_ldo7 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; +}; + +&slg51002_ldo8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; +}; + +&s_ldo12_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&pinctrl_4 { + hsi2c1_bus: hsi2c1-bus { + samsung,pin-pud = ; + }; + + hsi2c1_bus_in: hsi2c1-bus-in { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c2_bus: hsi2c2-bus { + samsung,pin-pud = ; + }; + + hsi2c2_bus_in: hsi2c2-bus-in { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c3_bus: hsi2c3-bus { + samsung,pin-pud = ; + }; + + hsi2c3_bus_in: hsi2c3-bus-in { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hsi2c4_bus: hsi2c4-bus { + samsung,pin-pud = ; + }; + + hsi2c4_bus_in: hsi2c4-bus-in { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pin-drv = ; + }; + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pin-drv = ; + }; + sensor_mclk4_out: sensor-mclk4-out { + samsung,pin-drv = ; + }; + sensor_mclk4_fn: sensor-mclk4-fn { + samsung,pin-drv = ; + }; +}; + +&hsi2c_1 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp2 0 GPIO_ACTIVE_HIGH &gpp2 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c1_bus_in>; + pinctrl-1 = <&hsi2c1_bus>; + pinctrl-2 = <&hsi2c1_bus_in>; +}; + +&hsi2c_2 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp4 0 GPIO_ACTIVE_HIGH &gpp4 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <950000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c2_bus_in>; + pinctrl-1 = <&hsi2c2_bus>; + pinctrl-2 = <&hsi2c2_bus_in>; +}; + +&hsi2c_3 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp6 0 GPIO_ACTIVE_HIGH &gpp6 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <950000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c3_bus_in>; + pinctrl-1 = <&hsi2c3_bus>; + pinctrl-2 = <&hsi2c3_bus_in>; +}; + +&hsi2c_4 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp8 0 GPIO_ACTIVE_HIGH &gpp8 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <1000000>; + samsung,reset-before-trans; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c4_bus_in>; + pinctrl-1 = <&hsi2c4_bus>; + pinctrl-2 = <&hsi2c4_bus_in>; +}; + +&hsi2c_15 { + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpp24 0 GPIO_ACTIVE_HIGH &gpp24 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + clock-frequency = <400000>; + + pinctrl-names = "default","on_i2c","off_i2c"; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-1 = <&hsi2c15_bus>; + pinctrl-2 = <&hsi2c15_bus>; +}; +/ { + fragment@lwiscamera { + target-path = "/"; + __overlay__ { + /* REAR CAMERA NAGUAL */ + sensor0: sensor@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-nagual"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x3D>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + /* CSID_RST_L GPP2[2] */ + reset-gpios = <&gpp2 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo1-supply = <&slg51002_ldo1>; + ldo4-supply = <&slg51002_ldo4>; + ldo8-supply = <&slg51002_ldo8>; + gpio3-supply = <&slg51002_gpio3>; + + clocks = + <&clock CIS_CLK3>, + <&clock GATE_DFTMUX_CMU_CIS_CLK3>; + clock-names = + "CIS_CLK3", + "GATE_DFTMUX_CMU_CIS_CLK3"; + clock-rates = + <26000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk4_fn>; + pinctrl-1 = <&sensor_mclk4_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo4", + "gpio3", + "ldo8", + "ldo1", + "reset", + "mclk_on"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "regulator", + "regulator", + "gpio", + "pinctrl"; + power-up-seq-delays-us = + <0 + 1000 + 0 + 0 + 2000 + 1000 + 9000>; + + /* Power down sequence */ + power-down-seqs = + "mclk_off", + "reset", + "ldo1", + "ldo8", + "gpio3", + "ldo4", + "s2mpg13_ldo12"; + power-down-seq-types = + "pinctrl", + "gpio", + "regulator", + "regulator", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 0 + 0 + 6000 + 0 + 0>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + /* FRONT CAMERA DOKKAEBI */ + sensor1: sensor@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-dokkaebi"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x10>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <16>; + + /* GPIOs */ + reset-gpios = <&gpp4 2 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo5-supply = <&slg51002_ldo5>; + ldo7-supply = <&slg51002_ldo7>; + + clocks = + <&clock CIS_CLK1>, + <&clock GATE_DFTMUX_CMU_CIS_CLK1>; + clock-names = + "CIS_CLK1", + "GATE_DFTMUX_CMU_CIS_CLK1"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk2_fn>; + pinctrl-1 = <&sensor_mclk2_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo7", + "ldo5", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <0 + 0 + 1000 + 1000 + 8000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo5", + "ldo7", + "s2mpg13_ldo12"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 1000 + 0 + 0 + 1000>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <1>; + }; + + /* REAR ULTRA WIDE CAMERA SANDWORM */ + sensor2: sensor@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "sensor-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x1A>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* GPIOs */ + reset-gpios = <&gpp6 3 GPIO_ACTIVE_HIGH>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo2-supply = <&slg51002_ldo2>; + ldo6-supply = <&slg51002_ldo6>; + + clocks = + <&clock CIS_CLK0>, + <&clock GATE_DFTMUX_CMU_CIS_CLK0>; + clock-names = + "CIS_CLK0", + "GATE_DFTMUX_CMU_CIS_CLK0"; + clock-rates = + <24000000>, + <0>; + + /* MCLK Control */ + pinctrl-names = "mclk_on", "mclk_off"; + pinctrl-0 = <&sensor_mclk1_fn>; + pinctrl-1 = <&sensor_mclk1_out>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo6", + "ldo2", + "mclk_on", + "reset"; + power-up-seq-types = + "regulator", + "regulator", + "regulator", + "pinctrl", + "gpio"; + power-up-seq-delays-us = + <0 + 0 + 1000 + 1000 + 10000>; + + /* Power down sequence */ + power-down-seqs = + "reset", + "mclk_off", + "ldo2", + "ldo6", + "s2mpg13_ldo12"; + power-down-seq-types = + "gpio", + "pinctrl", + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000 + 0 + 0 + 1000>; + + /* Thread priority */ + transaction-thread-priority = <99>; + + i2c-lock-group-id = <2>; + }; + + /* EEPROM GARGOYLE for NAGUAL*/ + eeprom0: eeprom@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo3-supply = <&slg51002_ldo3>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo3"; + power-up-seq-types = + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "ldo3", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator"; + power-down-seq-delays-us = + <1000 + 1000>; + + i2c-lock-group-id = <0>; + }; + + /* EEPROM SMAUG for DOKKAEBI */ + eeprom1: eeprom@1 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-dokkaebi"; + + /* I2C */ + i2c-bus = <&hsi2c_2>; + i2c-addr = <0x51>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + + i2c-lock-group-id = <1>; + }; + + /* EEPROM SMAUG for SANDWORM */ + eeprom2: eeprom@2 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "eeprom-smaug-sandworm"; + + /* I2C */ + i2c-bus = <&hsi2c_3>; + i2c-addr = <0x50>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12"; + power-up-seq-types = + "regulator"; + power-up-seq-delays-us = + <1000>; + + /* Power down sequence */ + power-down-seqs = + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator"; + power-down-seq-delays-us = + <1000>; + + i2c-lock-group-id = <2>; + }; + + /* Actuator SLENDERMAN for NAGUAL*/ + actuator0: actuator@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "act-slenderman"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0xC>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo4-supply = <&slg51002_ldo4>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo4"; + power-up-seq-types = + "regulator", + "regulator"; + power-up-seq-delays-us = + <0 + 0>; + + /* Power down sequence */ + power-down-seqs = + "ldo4", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator"; + power-down-seq-delays-us = + <0 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + /* Ois GARGOYLE for NAGUAL*/ + ois0: ois@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "ois-gargoyle"; + + /* I2C */ + i2c-bus = <&hsi2c_1>; + i2c-addr = <0x24>; + + /* Registers */ + reg-addr-bitwidth = <16>; + reg-value-bitwidth = <32>; + + /* Power supplies */ + s2mpg13_ldo12-supply = <&s_ldo12_reg>; + ldo3-supply = <&slg51002_ldo3>; + gpio2-supply = <&slg51002_gpio2>; + + /* Power up sequence */ + power-up-seqs = + "s2mpg13_ldo12", + "ldo3", + "gpio2"; + power-up-seq-types = + "regulator", + "regulator", + "regulator"; + power-up-seq-delays-us = + <1000 + 1000 + 1000>; + + /* Power down sequence */ + power-down-seqs = + "gpio2", + "ldo3", + "s2mpg13_ldo12"; + power-down-seq-types = + "regulator", + "regulator", + "regulator"; + power-down-seq-delays-us = + <5000 + 4000 + 0>; + + /* Thread priority */ + periodic-io-thread-priority = <99>; + + i2c-lock-group-id = <0>; + }; + + flash0: flash@0 { + compatible = "google,lwis-i2c-device"; + + /* Device node name */ + node-name = "flash-lm3644"; + + /* I2C */ + i2c-bus = <&hsi2c_15>; + i2c-addr = <0x63>; + + /* Registers */ + reg-addr-bitwidth = <8>; + reg-value-bitwidth = <8>; + + /* Power Management hibernation (deep sleep) */ + /* 1 : enable, 0 : disable */ + pm-hibernation = <0>; + + /* GPIOs */ + /* HW_ENABLE GPP8[2] */ + /* FLASH_STROBE GPP27[0] */ + enable-gpios = + <&gpp8 2 GPIO_ACTIVE_HIGH + &gpp27 0 GPIO_ACTIVE_LOW>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-charging.dtsi b/arch/arm64/boot/dts/google/gs201-panther-charging.dtsi new file mode 100644 index 000000000000..36dd7f11fd92 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-charging.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Battery device tree entries specific to panther + * + * Copyright 2021 Google,LLC + * + */ + + +&pca9468_dc { + pca9468,input-current-limit = <2200000>; /* 4.4A max */ + pca9468,spread-spectrum; +}; + +&google_charger { + google,thermal-mitigation = <4300000 3680000 2300000 1000000>; + google,wlc-fcc-thermal-mitigation = <4300000 4300000 2300000 1150000 1000000>; + google,thermal-stats-lvl-map = <0 3 5 8>; +}; + +&google_cpm { + /* google,mdis_in = &max77759tcpc, "wireless" */ + /* google,mdis_out = "main-charger", "pca94xx-mains"; */ + + // thermal budgets + google,mdis-thermal-mitigation = + <4258000 3413000 2603000 2017000 1919000 1506000 909000 575000 254000>; + // source ONLINE selection criteria + google,mdis-out-sel-online = <1 2>; + // PD+main-charger, WLC+main-charger + google,mdis-out0-limits = + <4000000 3500000 3000000 3000000 2500000 2000000 1500000 1000000 500000 + 1100000 500000 500000 500000 250000 250000 100000 100000 100000>; + // PPS_CP+pca94xx-mains, // WLC_CP+pca94xx-mains + google,mdis-out1-limits = + <4500000 4500000 4000000 3500000 3500000 3000000 2500000 2000000 1000000 + 4500000 3500000 3000000 3000000 2500000 2000000 1500000 1000000 0>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-common.dtsi b/arch/arm64/boot/dts/google/gs201-panther-common.dtsi new file mode 100644 index 000000000000..8a630baf58e9 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-common.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +#include "gs201-common.dtsi" +#include "gs201-cloudripper-battery.dtsi" +#include "gs201-cloudripper-bcl.dtsi" +#include "gs201-cloudripper-bluetooth.dtsi" +#include "gs201-pantah-charging.dtsi" +#include "gs201-cloudripper-cp-s5300-sit.dtsi" +#include "gs201-cloudripper-ese.dtsi" +#include "gs201-cloudripper-gsa-gsc.dtsi" +#include "gs201-cloudripper-nfc.dtsi" +#include "gs201-cloudripper-sbbm.dtsi" +#include "gs201-cloudripper-wlan.dtsi" + +#include "gs201-ravenclaw-fingerprint.dtsi" +#include "gs201-ravenclaw-usecases.dtsi" + +#include "gs201-pantah-camera-pmic.dtsi" +#include "gs201-panther-camera.dtsi" +#include "gs201-panther-display.dtsi" +#include "gs201-panther-pmic.dtsi" +#include "gs201-panther-touch.dtsi" +#include "gs201-panther-thermal.dtsi" +#include "gs201-panther-audio.dtsi" +#include "gs101-faceauth-dma-heap.dtsi" +#include "gs201-panther-battery.dtsi" +#include "gs201-panther-charging.dtsi" +#include "gs201-panther-wcharger.dtsi" +#include "gs201-panther-usb.dtsi" +#include "gs201-pantah-pmic.dtsi" \ No newline at end of file diff --git a/arch/arm64/boot/dts/google/gs201-panther-display.dtsi b/arch/arm64/boot/dts/google/gs201-panther-display.dtsi new file mode 100644 index 000000000000..fa8e38cf11b0 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-display.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Display nodes for slider-related boards. + * + * Copyright 2021 Google LLC + * + */ + +&drmdsim0 { + sdc_s6e3fc3_p10: panel@0 { + compatible = "samsung,s6e3fc3-p10"; + label = "sdc-s6e3fc3-p10"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + vci-supply = <&m_ldo27_reg>; + vddi-supply = <&s_bucka_reg>; + touch = <&spitouch>; + }; + panel@1 { + compatible = "samsung,emul"; + label = "samsung-emul"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&dsim_modes { + dsim-modes { + 1080x2400 { + mode-name = "1080x2400"; + pmsk = < + 0x2 0xB3 0x2 0x5CAB /* p m s k */ + >; + hs-clk = <1102>; + esc-clk = <20>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/google/gs201-panther-dvt1.dts b/arch/arm64/boot/dts/google/gs201-panther-dvt1.dts new file mode 100644 index 000000000000..9e0432c34d56 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-dvt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30404>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER DVT 1.0 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-evt1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-panther-evt1-wingboard.dts new file mode 100644 index 000000000000..469a72f75c11 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-evt1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30403>; + board_rev = <0x10002>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER EVT 1.0 Wingboard based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-evt1.dts b/arch/arm64/boot/dts/google/gs201-panther-evt1.dts new file mode 100644 index 000000000000..13e7c38eba73 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-evt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30403>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER EVT 1.0 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-evt1_1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-panther-evt1_1-wingboard.dts new file mode 100644 index 000000000000..d6be92ffa986 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-evt1_1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2022 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30403>; + board_rev = <0x10101>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER EVT 1.1 Wingboard based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-evt1_1.dts b/arch/arm64/boot/dts/google/gs201-panther-evt1_1.dts new file mode 100644 index 000000000000..2cae4ca51130 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-evt1_1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30403>; + board_rev = <0x10100>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER EVT 1.1 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-mp.dts b/arch/arm64/boot/dts/google/gs201-panther-mp.dts new file mode 100644 index 000000000000..46e992b29a91 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-mp.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" + +/ { + board_id = <0x30406>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER MP based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-panther-pmic.dtsi new file mode 100644 index 000000000000..8c8c9fedd749 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-pmic.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther-specific PMIC settings + * + * Copyright 2021 Google LLC. + * + */ + +/* Touch: Panther touch controller requires 3.0v typ */ +&m_ldo26_reg { + regulator-max-microvolt = <3000000>; +}; + +/* Display: vci-supply voltage */ +&m_ldo27_reg { + regulator-min-microvolt = <3025000>; + regulator-max-microvolt = <3025000>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-proto1.dts b/arch/arm64/boot/dts/google/gs201-panther-proto1.dts new file mode 100644 index 000000000000..3e8cf92c4c1f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-proto1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-panther-wcharger-proto.dtsi" + +/ { + board_id = <0x30402>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER Proto 1.0 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-proto1_1-wingboard.dts b/arch/arm64/boot/dts/google/gs201-panther-proto1_1-wingboard.dts new file mode 100644 index 000000000000..6235f96ef399 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-proto1_1-wingboard.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-panther-wcharger-proto.dtsi" + +/ { + board_id = <0x30402>; + board_rev = <0x10101>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER Proto 1.1 Wingboard based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-proto1_1.dts b/arch/arm64/boot/dts/google/gs201-panther-proto1_1.dts new file mode 100644 index 000000000000..e6d24dcb08cc --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-proto1_1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-panther-wcharger-proto.dtsi" + +/ { + board_id = <0x30402>; + board_rev = <0x10100>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER Proto 1.1 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-pvt1.dts b/arch/arm64/boot/dts/google/gs201-panther-pvt1.dts new file mode 100644 index 000000000000..9a412de798f4 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-pvt1.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Panther device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-panther-common.dtsi" +#include "gs201-pantah-pmic-odpm-1.dtsi" + +/ { + board_id = <0x30405>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 PANTHER PVT 1.0 based on GS201"; + compatible = "google,GS201 PANTHER", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-thermal.dtsi b/arch/arm64/boot/dts/google/gs201-panther-thermal.dtsi new file mode 100644 index 000000000000..da1b5809a790 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-thermal.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 panther-specific thermal device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include + +&acpm_mfd_bus1 { + s2mpg13mfd@2f { + gs201_tm1: gs201_spmic_tm1 { + compatible = "google,s2mpg13-spmic-thermal"; + #thermal-sensor-cells = <1>; + adc_chan_en = /bits/ 8 <0xFF>; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + neutral_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 0>; + trips { + trip_config0: trip-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 1>; + trips { + trip_config1: trip-config1 { + temperature = <56000>; + hysteresis = <1000>; + type = "passive"; + }; + backup_shutdown_sw: backup-shutdown-sw { + temperature = <57000>; + hysteresis = <1000>; + type = "critical"; + }; + backup_shutdown_hw: backup-shutdown-hw { + temperature = <59000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + qi_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 2>; + trips { + trip_config2: trip-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 3>; + trips { + trip_config3: trip-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 4>; + trips { + trip_config4: trip-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + disp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 5>; + trips { + trip_config5: trip-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + batt_therm_sidekey { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 6>; + trips { + trip_config6: trip-config6 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + gnss_tcxo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 7>; + trips { + trip_config7: trip-config7 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-touch.dtsi b/arch/arm64/boot/dts/google/gs201-panther-touch.dtsi new file mode 100644 index 000000000000..1bc5e80074ce --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-touch.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google P10 touch device tree source + * + * Copyright 2021 Google Inc. + * + */ + +#include + +&m_ldo25_reg { + /delete-property/ regulator-always-on; +}; + +&m_ldo26_reg { + /delete-property/ regulator-always-on; +}; + +/* + * Touch is connected to spi_0, pins: + * CLK=GPP20[0], MOSI=GPP20[1], MISO=GPP20[2], CS=GPP20[3] + * TS_RESET_L = C26 = XAPC_USI11_RTSN_DI = GPP23[2] = <&gpp23 2 0> + * TS_INT_L = AT22 = XEINT_8 = GPA7[0] = <&gpa7 0 0> + * + * DVDD = PP1800_L25M_TSP_DVDD = ??? = VLDO25M = "PP1800_L25M_TSP"? + * AVDD = PP3300_L26M_TS_AVDD = ??? = VLDO26M = "PP3300_L26M_TSP"? + * + * AP2AOC: XHSI1_GPIO2 - GPH1[0] -> XAOC_GPIO13 - gpio_in[87] + * AOC2AP: XAOC_GPIO8 - gpio_in[74] -> XEINT_19 - GPA8[7] + */ + +&ts_irq { + samsung,pins = "gpa7-0"; + samsung,pin-pud = ; + samsung,pin-drv = ; +}; + + +&pinctrl_1 { + ts_irq_sleep: ts-irq-sleep { + samsung,pins = "gpa7-0"; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&spi_0 { + dma-mode; + dmas = <&pdma0 0 &pdma0 1>; + swap-mode = <1> ; +}; + +&spitouch { + status = "ok"; + compatible = "focaltech,ts"; + + spi-max-frequency = <10000000>; + + focaltech,irq-gpio = <&gpa7 0 0>; + focaltech,reset-gpio = <&gpp23 2 0>; + focaltech,max-touch-number = <10>; + focaltech,display-coords = <0 0 1079 2399>; + focaltech,panel_map = <&sdc_s6e3fc3_p10 0>; + focaltech,rx_ch_num = <34>; + focaltech,tx_ch_num = <16>; + focaltech,touch_offload_id = /bits/ 8 <'p' '1' '0' '0'>; + focaltech,mm2px= /bits/ 8 <8>; + + pinctrl-1 = <&ts_spi_bus_sleep &ts_spi_cs_sleep &ts_irq_sleep>; + + controller-data { + cs-gpio = <&gpp20 3 0>; + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <1>; + cs-clock-delay = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-usb.dtsi b/arch/arm64/boot/dts/google/gs201-panther-usb.dtsi new file mode 100644 index 000000000000..1eabba103ac5 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-usb.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Oriole USB device tree source + * + * Copyright 2022 Google,LLC + */ + +&usb_hs_tune { + status = "disabled"; + hs_tune_cnt = <6>; + /* value = */ + hs_tune1 { + tune_name = "tx_pre_emp"; + tune_value = <0x3 0x3>; + }; + + hs_tune2 { + tune_name = "tx_vref"; + tune_value = <0x6 0x6>; + }; + + hs_tune3 { + tune_name = "rx_sqrx"; + tune_value = <0x2 0x2>; + }; + + hs_tune4 { + tune_name = "utmi_clk"; + tune_value = <0x1 0x1>; + }; + + hs_tune5 { + tune_name = "compdis"; + tune_value = <0x7 0x7>; + }; + + hs_tune6 { + tune_name = "tx_res"; + tune_value = <0x1 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-wcharger-proto.dtsi b/arch/arm64/boot/dts/google/gs201-panther-wcharger-proto.dtsi new file mode 100644 index 000000000000..c39f399c809b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-wcharger-proto.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2022 Google Inc. + */ + +&hsi2c_15 { + p9412@3c { + fod = [B7 26 89 3D 89 26 A6 E1 9A F9 9D EC 19 06 01 3C]; + fod_epp = [AC 51 87 6C 90 25 88 44 88 3E 8B 25 20 13 01 50]; + google,q_value = <60>; + idt,has_rtx = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-panther-wcharger.dtsi b/arch/arm64/boot/dts/google/gs201-panther-wcharger.dtsi new file mode 100644 index 000000000000..fe90d0e0b998 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-panther-wcharger.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2020 Google Inc. + */ + +#include "gs201-pantah-wcharger.dtsi" + +&hsi2c_15 { + p9412@3c { + fod = [B7 26 89 3D 89 26 A6 E1 9A F9 9D EC 19 06 01 3C]; + fod_epp = [AC 51 87 6C 90 25 88 44 88 3E 8B 25 20 13 01 50]; + fod_hpp = [FF 22 C5 00 9D E2 96 06 92 02 8E 04 20 13 01 50]; + fod_hpp_hv = [FF 54 C5 00 A6 02 9C 06 95 05 91 09 20 13 01 50]; + google,q_value = <60>; + idt,has_rtx = <1>; + + google,alignment_scalar_low_current = <300>; + google,alignment_scalar_high_current = <100>; + google,alignment_offset_low_current = <124000>; + google,alignment_offset_high_current = <136000>; + google,alignment_current_threshold = <500>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pcie.dtsi b/arch/arm64/boot/dts/google/gs201-pcie.dtsi new file mode 100644 index 000000000000..0c263e263e4b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pcie.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe device tree source code for gs101 SoC + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +/ { + /* HSI1 GEN4_0 */ + pcie_0: pcie@11920000 { + compatible = "samsung,exynos-pcie-rc"; + gpios = <&gph0 0 0x1 /* PERST */>; + reg = <0x0 0x11920000 0x2000 /* elbi base */ + 0x0 0x11950000 0x2000 /* phy base */ + 0x0 0x11820000 0x2000 /* sysreg base */ + 0x0 0x11C00000 0x301000 /* DBI base */ + 0x0 0x11940000 0x1000 /* phy pcs base */ + 0x0 0x40FFE000 0x2000 /* configuration space */ + 0x0 0x11900000 0x1000>; /* I/A space */ + reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + pinctrl-names = "active"; + pinctrl-0 = <&pcie0_clkreq &pcie0_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x14E00000 0 0x40000000 0 0xFF0000>; + ip-ver = <0x984500>; /* gs101 */ + num-lanes = <2>; + ch-num = <0>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <200000>; + separated-msi = <1>; + use-cache-coherency = "false"; + use-pcieon-sleep = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "false"; + use-l1ss = "false"; + use-secure-atu = "false"; + pmu-offset = <0x3ec0>; + max-link-speed = ; + status = "disabled"; + }; + sysmmu_hsi1: sysmmu@11860000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x11860000 0x10000>; + interrupts = <0 IRQ_SYSMMU_HSI1_S1_NS_HSI1 IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + port-name = "PCIe_CH0"; + hsi-block-num = <1>; + pcie-vid-num = <0>; + #iommu-cells = <0>; + ignore-tlb-inval = <1>; + use-map-once = "false"; + status = "okay"; + }; + + /* HSI2 GEN4_1 */ + pcie_1: pcie@14520000 { + compatible = "samsung,exynos-pcie-rc"; + gpios = <&gph2 0 0x1 /* PERST */>; + reg = <0x0 0x14520000 0x2000 /* elbi base */ + 0x0 0x14550000 0x2000 /* phy base */ + 0x0 0x14420000 0x2000 /* sysreg base */ + 0x0 0x14800000 0x301000 /* DBI base */ + 0x0 0x14540000 0x1000 /* phy pcs base */ + 0x0 0x60FFE000 0x2000 /* configuration space */ + 0x0 0x14500000 0x1000>; /* I/A space */ + reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia"; + interrupts = , + , + , + , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 IRQ_PCIE_GEN4A_1_HSI2 0x4>; + samsung,syscon-phandle = <&pmu_system_controller>; + pinctrl-names = "active"; + pinctrl-0 = <&pcie1_clkreq &pcie1_perst>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + /* non-prefetchable memory */ + ranges = <0x82000000 0 0x60000000 0 0x60000000 0 0xFF0000>; + ip-ver = <0x984500>; /* gs101 */ + num-lanes = <2>; + ch-num = <1>; + pcie-clk-num = <0>; + phy-clk-num = <0>; + pcie-pm-qos-int = <200000>; + use-cache-coherency = "false"; + use-pcieon-sleep = "false"; + use-msi = "false"; + use-sicd = "false"; + use-sysmmu = "false"; + use-ia = "false"; + use-l1ss = "false"; + use-secure-atu = "false"; + pmu-offset = <0x3ec4>; + max-link-speed = ; + status = "disabled"; + }; + + sysmmu_hsi2: sysmmu@145C0000 { + compatible = "samsung,pcie-sysmmu"; + reg = <0x0 0x145C0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_HSI2_S1_NS_HSI2 IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + port-name = "PCIe_CH1"; + hsi-block-num = <2>; + pcie-vid-num = <1>; + #iommu-cells = <0>; + use-map-once = "false"; + status = "okay"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pinctrl.dtsi b/arch/arm64/boot/dts/google/gs201-pinctrl.dtsi new file mode 100644 index 000000000000..f2867e5d0df2 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pinctrl.dtsi @@ -0,0 +1,1197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021 Google LLC. + * + */ + +#include +#include + +/ { + /* GPIO_ALIVE */ + pinctrl@180D0000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + ; + }; + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa5: gpa5 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + ; + }; + gpa9: gpa9 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa10: gpa10 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + ; + }; + + uart17_bus: uart17-bus { + samsung,pins = "gpa2-2", "gpa2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart18_bus: uart18-bus { + samsung,pins = "gpa3-0", "gpa3-1", "gpa3-2", "gpa3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + uart18_bus_rts: uart1-bus-rts { + samsung,pins = "gpa3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-val = <1>; + }; + + uart18_bus_tx_dat: uart1-bus-tx-dat { + samsung,pins = "gpa3-1"; + samsung,pin-val = <1>; + }; + + uart18_bus_tx_con: uart1-bus-tx-con { + samsung,pins = "gpa3-1"; + samsung,pin-function = ; + }; + + uart19_bus: uart19-bus { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2", "gpa4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + spi17_bus: spi17-bus { + samsung,pins = "gpa4-0", "gpa4-1", "gpa4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi17_cs: spi17-cs { + samsung,pins = "gpa4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + }; + /* GPIO_FAR_ALIVE */ + pinctrl@180E0000 { + gpa6: gpa6 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa7: gpa7 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + gpa8: gpa8 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + gpa11: gpa11 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = , + ; + }; + + }; + /* GPIO_GSACORE */ + pinctrl@17A80000 { + gps0: gps0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gps1: gps1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gps2: gps2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + /* GPIO_GSACTRL */ + pinctrl@17940000 { + gps3: gps3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; + /* GPIO_HSI1 */ + pinctrl@11840000 { + gph0: gph0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gph1: gph1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + pcie0_clkreq: pcie0_clkreq { + samsung,pins = "gph0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie0_perst: pcie0_perst { + samsung,pins = "gph0-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_HSI2 */ + pinctrl@14440000 { + gph2: gph2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gph4: gph4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gph4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gph4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gph4-3", "gph4-4", "gph4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x { + samsung,pins = "gph4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + pcie1_clkreq: pcie1_clkreq { + samsung,pins = "gph2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = ; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <3>; + }; + pcie1_perst: pcie1_perst { + samsung,pins = "gph2-0"; + samsung,pin-function = <1>; + samsung,pin-drv = ; + samsung,pin-pud = ; + samsung,pin-pud-pdn = ; + samsung,pin-con-pdn = <3>; + }; + }; + /* GPIO_PERIC0 */ + pinctrl@10840000 { + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp3: gpp3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp4: gpp4 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp5: gpp5 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp6: gpp6 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp7: gpp7 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp8: gpp8 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp9: gpp9 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp10: gpp10 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp11: gpp11 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp12: gpp12 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp13: gpp13 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp14: gpp14 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp15: gpp15 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp16: gpp16 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp17: gpp17 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp18: gpp18 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp19: gpp19 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + /* USI_PERIC0_UART_DBG */ + uart0_bus: uart0-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + disp_te_pri_on: disp-te-pri-on { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0xf>; + }; + + disp_te_pri_off: disp-te-pri-off { + samsung,pins = "gpp0-3"; + samsung,pin-function = <0>; + }; + + disp_te_sec_on: disp-te-sec-on { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0xf>; + }; + + disp_te_sec_off: disp-te-sec-off { + samsung,pins = "gpp0-4"; + samsung,pin-function = <0>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk3_out: sensor-mclk3-out { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk3_fn: sensor-mclk3-fn { + samsung,pins = "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk4_out: sensor-mclk4-out { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk4_fn: sensor-mclk4-fn { + samsung,pins = "gpp9-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk5_out: sensor-mclk5-out { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk5_fn: sensor-mclk5-fn { + samsung,pins = "gpp11-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk6_out: sensor-mclk6-out { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk6_fn: sensor-mclk6-fn { + samsung,pins = "gpp13-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk7_out: sensor-mclk7-out { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk7_fn: sensor-mclk7-fn { + samsung,pins = "gpp15-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk8_out: sensor-mclk8-out { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + sensor_mclk8_fn: sensor-mclk8-fn { + samsung,pins = "gpp17-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + hsi2c14_bus: hsi2c14-bus { + samsung,pins = "gpp18-0", "gpp18-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart14_bus_single: uart14-bus { + samsung,pins = "gpp18-0", "gpp18-1", + "gpp18-2", "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi14_bus: spi14-bus { + samsung,pins = "gpp18-0", "gpp18-1", "gpp18-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs: spi14-cs { + samsung,pins = "gpp18-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs_func: spi14-cs-func { + samsung,pins = "gpp18-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c8_bus: hsi2c8-bus { + samsung,pins = "gpp16-0", "gpp16-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-pud-pdn = ; + }; + uart8_bus_single: uart8-bus { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2", + "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi8_bus: spi8-bus { + samsung,pins = "gpp16-0", "gpp16-1", "gpp16-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi8_cs: spi8-cs { + samsung,pins = "gpp16-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi8_cs_func: spi8-cs-func { + samsung,pins = "gpp16-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c7_bus: hsi2c7-bus { + samsung,pins = "gpp14-0", "gpp14-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart7_bus_single: uart7-bus { + samsung,pins = "gpp14-0", "gpp14-1", + "gpp14-2", "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi7_bus: spi7-bus { + samsung,pins = "gpp14-0", "gpp14-1", "gpp14-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi7_cs: spi7-cs { + samsung,pins = "gpp14-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi7_cs_func: spi7-cs-func { + samsung,pins = "gpp14-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c6_bus: hsi2c6-bus { + samsung,pins = "gpp12-0", "gpp12-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart6_bus_single: uart6-bus { + samsung,pins = "gpp12-0", "gpp12-1", + "gpp12-2", "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi6_bus: spi6-bus { + samsung,pins = "gpp12-0", "gpp12-1", "gpp12-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi6_cs: spi6-cs { + samsung,pins = "gpp12-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi6_cs_func: spi6-cs-func { + samsung,pins = "gpp12-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c5_bus: hsi2c5-bus { + samsung,pins = "gpp10-0", "gpp10-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart5_bus_single: uart5-bus { + samsung,pins = "gpp10-0", "gpp10-1", + "gpp10-2", "gpp10-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi5_bus: spi5-bus { + samsung,pins = "gpp10-0", "gpp10-1", "gpp10-2"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + spi5_cs_func: spi5-cs-func { + samsung,pins = "gpp10-3"; + samsung,pin-drv = ; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpp8-0", "gpp8-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart4_bus_single: uart4-bus { + samsung,pins = "gpp8-0", "gpp8-1", + "gpp8-2", "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi4_bus: spi4-bus { + samsung,pins = "gpp8-0", "gpp8-1", "gpp8-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi4_cs: spi4-cs { + samsung,pins = "gpp8-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi4_cs_func: spi4-cs-func { + samsung,pins = "gpp8-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpp6-0", "gpp6-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart3_bus_single: uart3-bus { + samsung,pins = "gpp6-0", "gpp6-1", + "gpp6-2", "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi3_bus: spi3-bus { + samsung,pins = "gpp6-0", "gpp6-1", "gpp6-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi3_cs: spi3-cs { + samsung,pins = "gpp6-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi3_cs_func: spi3-cs-func { + samsung,pins = "gpp6-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpp4-0", "gpp4-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart2_bus_single: uart2-bus { + samsung,pins = "gpp4-0", "gpp4-1", + "gpp4-2", "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi2_bus: spi2-bus { + samsung,pins = "gpp4-0", "gpp4-1", "gpp4-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi2_cs: spi2-cs { + samsung,pins = "gpp4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpp4-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpp2-0", "gpp2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart1_bus_single: uart1-bus { + samsung,pins = "gpp2-0", "gpp2-1", + "gpp2-2", "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi1_bus: spi1-bus { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi1_cs: spi1-cs { + samsung,pins = "gpp2-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpp2-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + }; + /* GPIO_PERIC1 */ + pinctrl@10C40000 { + gpp20: gpp20 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp21: gpp21 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp22: gpp22 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp23: gpp23 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp24: gpp24 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp25: gpp25 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp26: gpp26 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + gpp27: gpp27 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + hsi2c16_bus: hsi2c16-bus { + samsung,pins = "gpp26-0", "gpp26-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart16_bus_single: uart16-bus { + samsung,pins = "gpp26-0", "gpp26-1", + "gpp26-2", "gpp26-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi16_bus: spi16-bus { + samsung,pins = "gpp26-0", "gpp26-1", "gpp26-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi16_cs: spi16-cs { + samsung,pins = "gpp26-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi16_cs_func: spi16-cs-func { + samsung,pins = "gpp26-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c15_bus: hsi2c15-bus { + samsung,pins = "gpp24-0", "gpp24-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + uart15_bus_single: uart15-bus { + samsung,pins = "gpp24-0", "gpp24-1", + "gpp24-2", "gpp24-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi15_bus: spi15-bus { + samsung,pins = "gpp24-0", "gpp24-1", "gpp24-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi15_cs: spi15-cs { + samsung,pins = "gpp24-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi15_cs_func: spi15-cs-func { + samsung,pins = "gpp24-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c13_bus: hsi2c13-bus { + samsung,pins = "gpp25-0", "gpp25-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart13_bus_single: uart13-bus { + samsung,pins = "gpp25-0", "gpp25-1", + "gpp25-2", "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi13_bus: spi13-bus { + samsung,pins = "gpp25-0", "gpp25-1", "gpp25-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi13_cs: spi13-cs { + samsung,pins = "gpp25-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi13_cs_func: spi13-cs-func { + samsung,pins = "gpp25-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c12_bus: hsi2c12-bus { + samsung,pins = "gpp23-4", "gpp23-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart12_bus_single: uart12-bus { + samsung,pins = "gpp23-4", "gpp23-5", + "gpp23-6", "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi12_bus: spi12-bus { + samsung,pins = "gpp23-4", "gpp23-5", "gpp23-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi14_cs2: spi14-cs2 { + samsung,pins = "gpp23-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + spi12_cs: spi12-cs { + samsung,pins = "gpp23-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi12_cs_func: spi12-cs-func { + samsung,pins = "gpp23-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c11_bus: hsi2c11-bus { + samsung,pins = "gpp23-0", "gpp23-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart11_bus_single: uart11-bus { + samsung,pins = "gpp23-0", "gpp23-1", + "gpp23-2", "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi11_bus: spi11-bus { + samsung,pins = "gpp23-0", "gpp23-1", "gpp23-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi11_cs: spi11-cs { + samsung,pins = "gpp23-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi11_cs_func: spi11-cs-func { + samsung,pins = "gpp23-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c10_bus: hsi2c10-bus { + samsung,pins = "gpp21-0", "gpp21-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart10_bus_single: uart10-bus { + samsung,pins = "gpp21-0", "gpp21-1", + "gpp21-2", "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi10_bus: spi10-bus { + samsung,pins = "gpp21-0", "gpp21-1", "gpp21-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi10_cs: spi10-cs { + samsung,pins = "gpp21-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi10_cs_func: spi10-cs-func { + samsung,pins = "gpp21-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c9_bus: hsi2c9-bus { + samsung,pins = "gpp20-4", "gpp20-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart9_bus_single: uart9-bus { + samsung,pins = "gpp20-4", "gpp20-5", + "gpp20-6", "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + spi9_bus: spi9-bus { + samsung,pins = "gpp20-4", "gpp20-5", "gpp20-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi9_cs: spi9-cs { + samsung,pins = "gpp20-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi9_cs_func: spi9-cs-func { + samsung,pins = "gpp20-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpp20-0", "gpp20-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + uart0_bus_single: uart0-bus { + samsung,pins = "gpp20-0", "gpp20-1", + "gpp20-2", "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + }; + spi0_bus: spi0-bus { + samsung,pins = "gpp20-0", "gpp20-1", "gpp20-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi0_cs: spi0-cs { + samsung,pins = "gpp20-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp20-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = ; + }; + }; + /* GPIO_HSI2UFS */ + pinctrl@14460000 { + gph3: gph3 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <3>; + }; + ufs_rst_n: ufs-rst-n { + samsung,pins = "gph3-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + ufs_refclk_out: ufs-refclk-out { + samsung,pins = "gph3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-con-pdn = <3>; + samsung,pin-pud-pdn = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pm-domains.dtsi b/arch/arm64/boot/dts/google/gs201-pm-domains.dtsi new file mode 100644 index 000000000000..707ea1b6a61b --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pm-domains.dtsi @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC PM Domains device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * GS201 SoC PM domains device nodes are listed in this file. + * GS201 based board files can include this file and provide + * values for board specific bindings. + * + */ + +#include + +/ { + pd_aoc: pd-aoc@18061880 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061880 0x20>; + cal_id = <0xB1380000>; + need_smc = <0x1A010204>; + cmu_id = <0x1A000000>; + status = "disabled"; + #power-domain-cells = <0>; + }; + + pd_eh: pd-eh@18061C00 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061C00 0x20>; + cal_id = <0xB1380005>; + need_smc = <0x17010204>; + cmu_id = <0x17000000>; + status = "okay"; + skip-idle-ip; + #power-domain-cells = <0>; + }; + + pd_embedded_g3d: pd-embedded_g3d@18062000 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062000 0x20>; + cal_id = <0xB1380006>; + status = "okay"; + skip-idle-ip; + power-domains = <&pd_g3d>; + #power-domain-cells = <0>; + }; + + pd_g3d: pd-g3d@18061E00 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18061E00 0x20>; + cal_id = <0xB1380007>; + need_smc = <0x27F10204>; + cmu_id = <0x27F00000>; + status = "okay"; + skip-idle-ip; + #power-domain-cells = <0>; + }; + + pd_hsi0: pd-hsi0@18062080 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062080 0x20>; + cal_id = <0xB1380008>; + need_smc = <0x11010204>; + cmu_id = <0x11000000>; + status = "okay"; + #power-domain-cells = <0>; + power-down-ok = ; + skip-idle-ip; + }; + + pd_hsi2: pd-hsi2@18062180 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062180 0x20>; + cal_id = <0xB1380009>; + need_smc = <0x14410204>; + cmu_id = <0x14400000>; + status = "disabled"; + #power-domain-cells = <0>; + }; + + pd_dpu: pd-dpu@18062200 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062200 0x20>; + cal_id = <0xB138000A>; + need_smc = <0x1C010204>; + cmu_id = <0x1C000000>; + status = "okay"; + power-domains = <&pd_disp>; + #power-domain-cells = <0>; + skip-idle-ip; + }; + + pd_disp: pd-disp@18062280 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062280 0x20>; + cal_id = <0xB138000B>; + need_smc = <0x1C210204>; + cmu_id = <0x1C200000>; + status = "okay"; + #power-domain-cells = <0>; + skip-idle-ip; + }; + + pd_g2d: pd-g2d@18062300 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062300 0x20>; + cal_id = <0xB138000C>; + need_smc = <0x1C610204>; + cmu_id = <0x1C600000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_mfc: pd-mfc@18062380 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062380 0x20>; + cal_id = <0xB138000D>; + need_smc = <0x1C810204>; + cmu_id = <0x1C800000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_csis: pd-csis@18062400 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062400 0x20>; + cal_id = <0xB138000E>; + need_smc = <0x1A410204>; + cmu_id = <0x1A400000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_pdp: pd-pdp@18062480 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062480 0x20>; + cal_id = <0xB138000F>; + need_smc = <0x1AA10204>; + cmu_id = <0x1AA00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_dns: pd-dns@18062500 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062500 0x20>; + cal_id = <0xB1380010>; + need_smc = <0x1B010204>; + cmu_id = <0x1B000000>; + status = "okay"; + power-domains = <&pd_itp>; + #power-domain-cells = <0>; + }; + + pd_g3aa: pd-g3aa@18062580 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062580 0x20>; + cal_id = <0xB1380011>; + need_smc = <0x1A810204>; + cmu_id = <0x1A800000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_ipp: pd-ipp@18062600 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062600 0x20>; + cal_id = <0xB1380012>; + need_smc = <0x1AC10204>; + cmu_id = <0x1AC00000>; + status = "okay"; + power-domains = <&pd_pdp>; + #power-domain-cells = <0>; + }; + + pd_itp: pd-itp@18062680 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062680 0x20>; + cal_id = <0xB1380013>; + need_smc = <0x1B410204>; + cmu_id = <0x1B400000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_mcsc: pd-mcsc@18062700 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062700 0x20>; + cal_id = <0xB1380014>; + need_smc = <0x1B710204>; + cmu_id = <0x1B700000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_gdc: pd-gdc@18062780 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062780 0x20>; + cal_id = <0xB1380015>; + need_smc = <0x1D010204>; + cmu_id = <0x1D000000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_tnr: pd-tnr@18062800 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062800 0x20>; + cal_id = <0xB1380016>; + need_smc = <0x1BC10204>; + cmu_id = <0x1BC00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_bo: pd-bo@18062880 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062880 0x20>; + cal_id = <0xB1380017>; + need_smc = <0x1CA10204>; + cmu_id = <0x1CA00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_tpu: pd-tpu@18062900 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062900 0x20>; + cal_id = <0xB1380018>; + need_smc = <0x1CC10204>; + cmu_id = <0x1CC00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + pd_aur: pd-aur@18062980 { + compatible = "samsung,exynos-pd"; + reg = <0x0 0x18062980 0x20>; + cal_id = <0xB1380019>; + need_smc = <0x25A10204>; + cmu_id = <0x25A00000>; + status = "okay"; + #power-domain-cells = <0>; + }; + + dbgdev-pd-aoc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_aoc>; + }; + + dbgdev-pd-eh { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_eh>; + }; + + dbgdev-pd-embedded_g3d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_embedded_g3d>; + }; + + dbgdev-pd-g3d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g3d>; + }; + + dbgdev-pd-hsi0 { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_hsi0>; + }; + + dbgdev-pd-hsi2 { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_hsi2>; + }; + + dbgdev-pd-dpu { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_dpu>; + }; + + dbgdev-pd-disp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_disp>; + }; + + dbgdev-pd-g2d { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g2d>; + }; + + dbgdev-pd-mfc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_mfc>; + }; + + dbgdev-pd-csis { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_csis>; + }; + + dbgdev-pd-pdp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_pdp>; + }; + + dbgdev-pd-dns { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_dns>; + }; + + dbgdev-pd-g3aa { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_g3aa>; + }; + + dbgdev-pd-ipp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_ipp>; + }; + + dbgdev-pd-itp { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_itp>; + }; + + dbgdev-pd-mcsc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_mcsc>; + }; + + dbgdev-pd-gdc { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_gdc>; + }; + + dbgdev-pd-tnr { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_tnr>; + }; + + dbgdev-pd-bo { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_bo>; + }; + + dbgdev-pd-tpu { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_tpu>; + }; + + dbgdev-pd-aur { + compatible = "samsung,exynos-pd-dbg"; + power-domains = <&pd_aur>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-pmic.dtsi new file mode 100644 index 000000000000..29a4e8d2d333 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pmic.dtsi @@ -0,0 +1,1374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * gs201 pmic device tree source + * + * Copyright 2021 Google LLC. + * + */ + +#include +#include +#include +#include +#include + +&pinctrl_0 { + m_pmic_irq: m-pmic-irq { + samsung,pins = "gpa0-6"; + samsung,pin-pud = <0>; + }; + + s_pmic_irq: s-pmic-irq { + samsung,pins = "gpa0-7"; + samsung,pin-pud = <0>; + }; + + smpl_warn: smpl-warn { + samsung,pins = "gpa5-0"; /* SMPL_WARN_R_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&acpm_mfd_bus0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + s2mpg12mfd: s2mpg12mfd@1f { + compatible = "samsung,s2mpg12mfd"; + dev-name = "s2mpg12mfd"; + acpm-ipc-channel = <2>; + s2mpg12,wakeup = "enabled"; + reg = <0x1f>; + interrupts = ; + interrupt-parent = <&gic>; + pinctrl-names = "default"; + pinctrl-0 = <&m_pmic_irq &smpl_warn>; + gpios = <&gpa5 0 0>, /* SMPL_WARN_R_L */ + <&gpa5 1 0>, /* OCP_WARN_CPUCL1_R */ + <&gpa5 2 0>, /* OCP_WARN_CPUCL2_R */ + <&gpa5 3 0>, /* SOFT_OCP_WARN_CPUCL1_R */ + <&gpa5 4 0>, /* SOFT_OCP_WARN_CPUCL2_R */ + <&gpp19 1 0>, /* OCP_WARN_TPU_R */ + <&gpp19 3 0>; /* SOFT_OCP_WARN_TPU_R */ + #thermal-sensor-cells = <1>; + + /* SMPL_WARN */ + smpl_warn_en = <1>; /* 1 : enable , 0 : disable */ + smpl_warn_vth = ; + /* SMPL_Hys[4:3] */ + /* 00(Reserved), 01(200mV), 10(300mV), 11(Reserved) */ + smpl_warn_hys = ; + + /* OCP WARN */ + b2_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + /* ocp warn reset timing control */ + b2_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + /* ocp warn mask when dvs */ + b2_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b2_ocp_warn_lvl = <0>; /* 12.0A */ + + b3_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b3_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b3_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b3_ocp_warn_lvl = <0>; /* 8.0A */ + + b10_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b10_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b10_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b10_ocp_warn_lvl = <0>; /* 12A */ + + b2_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b2_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b2_soft_ocp_warn_lvl = <20>; /* 9.0A */ + + b3_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b3_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b3_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b3_soft_ocp_warn_lvl = <0>; /* 7.0A */ + + b10_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b10_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b10_soft_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b10_soft_ocp_warn_lvl = <0>; /* 8.5A */ + + /* BUCK OCP Detection */ + buck_ocp_ctrl1 = <0xBB>; + buck_ocp_ctrl2 = <0xBB>; + buck_ocp_ctrl3 = <0xBB>; + buck_ocp_ctrl4 = <0xBB>; + buck_ocp_ctrl5 = <0xBB>; + + /* RTC: wtsr/smpl */ + wtsr_en = "enabled"; /* enable */ + coldrst_en = "disabled"; + smpl_en = "disabled"; /* disable */ + wtsr_timer_val = <3>; /* 1000ms */ + coldrst_timer_val = <3>; /* 256ms */ + smpl_timer_val = <4>; /* 500ms */ + sub_smpl_en = "disabled"; /* disable */ + check_jigon = <0>; /* do not check jigon */ + + /* RTC: If first boot, reset rtc to 1/1/2020 12:00:00(Wed) */ + init_time,sec = <0>; + init_time,min = <0>; + init_time,hour = <12>; + init_time,mday = <1>; + init_time,mon = <0>; + init_time,year = <120>; + init_time,wday = <3>; + + /* PCTRLSEL(VGPIO) 1~14 (CONTROL_SEL#) */ + sel_vgpio = <0xC2 0x0B 0x22 0xA2 0x2D 0x2F 0x55 0x55 + 0x0B 0x7D 0x32 0x3C 0x80 0x80>; + + s2mpg12-keys { + button@1 { + label = "pmic-keys: KEY_POWER"; + linux,code = <116>; + wakeup = <1>; + }; + }; + + regulators { + m_buck1_reg: BUCK1M { + regulator-name = "S2MPG12_BUCK1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x1>; + schematic-name = "S1M_VDD_MIF"; + subsys-name = "MIF"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x1>; + }; + + m_buck2_reg: BUCK2M { + regulator-name = "S2MPG12_BUCK2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2>; + schematic-name = "S2M_VDD_CPUCL2"; + subsys-name = "CPU(BIG)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + m_buck3_reg: BUCK3M { + regulator-name = "S2MPG12_BUCK3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x3>; + schematic-name = "S3M_VDD_CPUCL1"; + subsys-name = "CPU(MID)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x4>; + odpm_disable_in_sleep; + }; + + m_buck4_reg: BUCK4M { + regulator-name = "S2MPG12_BUCK4"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x4>; + schematic-name = "S4M_VDD_CPUCL0"; + subsys-name = "CPU(LITTLE)"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x8>; + odpm_disable_in_sleep; + }; + + m_buck5_reg: BUCK5M { + regulator-name = "S2MPG12_BUCK5"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x5>; + schematic-name = "S5M_VDD_INT"; + subsys-name = "INT"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x10>; + odpm_disable_in_sleep; + }; + + m_buck6_reg: BUCK6M { + regulator-name = "S2MPG12_BUCK6"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x6>; + schematic-name = "S6M_LLDO1"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x20>; + odpm_disable_in_sleep; + }; + + m_buck7_reg: BUCK7M { + regulator-name = "S2MPG12_BUCK7"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x7>; + schematic-name = "S7M_VDD_INT_M"; + subsys-name = "INT"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x40>; + odpm_disable_in_sleep; + }; + + m_buck8_reg: BUCK8M { + regulator-name = "S2MPG12_BUCK8"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x8>; + schematic-name = "S8M_LLDO2"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x80>; + }; + + m_buck9_reg: BUCK9M { + regulator-name = "S2MPG12_BUCK9"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x9>; + schematic-name = "S9M_LLDO3"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x1>; + }; + + m_buck10_reg: BUCK10M { + regulator-name = "S2MPG12_BUCK10"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0xA>; + schematic-name = "S10M_VDD_TPU"; + subsys-name = "TPU"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + m_ldo1_reg: LDO1M { + regulator-name = "S2MPG12_LDO1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x21>; + schematic-name = "L1M_ALIVE"; + subsys-name = "Alive"; + }; + + m_ldo2_reg: LDO2M { + regulator-name = "S2MPG12_LDO2"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x22>; + schematic-name = "L2M_ALIVE"; + subsys-name = "Alive"; + }; + + m_ldo3_reg: LDO3M { + regulator-name = "S2MPG12_LDO3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x23>; + schematic-name = "L3M_VDD_AOC_RET"; + subsys-name = "AOC"; + }; + + m_ldo4_reg: LDO4M { + regulator-name = "S2MPG12_LDO4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x24>; + schematic-name = "L4M_HSI"; + subsys-name = "IO"; + }; + + m_ldo5_reg: LDO5M { + regulator-name = "S2MPG12_LDO5"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x25>; + schematic-name = "L5M_TCXO"; + subsys-name = "PLL"; + }; + + m_ldo6_reg: LDO6M { + regulator-name = "S2MPG12_LDO6"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x26>; + schematic-name = "L6M_PLL"; + subsys-name = "PLL"; + }; + + m_ldo7_reg: LDO7M { + regulator-name = "S2MPG12_LDO7"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x27>; + schematic-name = "L7M_VDD_HSI"; + subsys-name = "IO"; + }; + + m_ldo8_reg: LDO8M { + regulator-name = "S2MPG12_LDO8"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x28>; + schematic-name = "L8M_USB"; + subsys-name = "USB"; + }; + + m_ldo9_reg: LDO9M { + regulator-name = "S2MPG12_LDO9"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x29>; + schematic-name = "L9M_USB"; + subsys-name = "USB"; + }; + + m_ldo10_reg: LDO10M { + regulator-name = "S2MPG12_LDO10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-initial-mode = ; + channel-mux-selection = <0x2A>; + schematic-name = "L10M_USB"; + subsys-name = "USB"; + }; + + m_ldo11_reg: LDO11M { + regulator-name = "S2MPG12_LDO11"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2B>; + schematic-name = "L11M_VDD_CPUCL1_M"; + subsys-name = "CPU(MID)"; + }; + + m_ldo12_reg: LDO12M { + regulator-name = "S2MPG12_LDO12"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2C>; + schematic-name = "L12M_VDD_CPUCL0_M"; + subsys-name = "CPU(LITTLE)"; + }; + + m_ldo13_reg: LDO13M { + regulator-name = "S2MPG12_LDO13"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2D>; + schematic-name = "L13M_VDD_TPU_M"; + subsys-name = "TPU"; + }; + + m_ldo14_reg: LDO14M { + regulator-name = "S2MPG12_LDO14"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2E>; + schematic-name = "L14M_TCXO"; + subsys-name = "PLL"; + }; + + m_ldo15_reg: LDO15M { + regulator-name = "S2MPG12_LDO15"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2F>; + schematic-name = "L15M_VDD_SLC_M"; + subsys-name = "SLC"; + }; + + m_ldo16_reg: LDO16M { + regulator-name = "S2MPG12_LDO16"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x30>; + schematic-name = "L16M_PCIE0"; + subsys-name = "PCIE"; + }; + + m_ldo17_reg: LDO17M { + regulator-name = "S2MPG12_LDO17"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x31>; + schematic-name = "L17M_VDD_CPUCL2_M"; + subsys-name = "CPU(BIG)"; + }; + + m_ldo18_reg: LDO18M { + regulator-name = "S2MPG12_LDO18"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x32>; + schematic-name = "L18M_PCIE0"; + subsys-name = "PCIE"; + }; + + m_ldo19_reg: LDO19M { + regulator-name = "S2MPG12_LDO19"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x33>; + schematic-name = "L19M_SPARE"; + subsys-name = "Spare"; + }; + + m_ldo20_reg: LDO20M { + regulator-name = "S2MPG12_LDO20"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x34>; + schematic-name = "L20M_DMIC1"; + subsys-name = "DMIC"; + }; + + m_ldo21_reg: LDO21M { + regulator-name = "S2MPG12_LDO21"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x35>; + schematic-name = "L21M_GSC"; + subsys-name = "GSC"; + }; + + m_ldo22_reg: LDO22M { + regulator-name = "S2MPG12_LDO22"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x36>; + schematic-name = "L22M_SPARE"; + subsys-name = "Spare"; + }; + + m_ldo23_reg: LDO23M { + regulator-name = "S2MPG12_LDO23"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x37>; + schematic-name = "L23M_DMIC2"; + subsys-name = "DMIC"; + }; + + m_ldo24_reg: LDO24M { + regulator-name = "S2MPG12_LDO24"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x38>; + schematic-name = "L24M_DISP_VDDI"; + subsys-name = "Display"; + }; + + m_ldo25_reg: LDO25M { + regulator-name = "S2MPG12_LDO25"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x39>; + schematic-name = "L25M_TSP_DVDD"; + subsys-name = "TSP"; + }; + + m_ldo26_reg: LDO26M { + regulator-name = "S2MPG12_LDO26"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x3A>; + schematic-name = "L26M_TS_AVDD"; + subsys-name = "TS"; + }; + + m_ldo27_reg: LDO27M { + regulator-name = "S2MPG12_LDO27"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x3B>; + schematic-name = "L27M_DISP_VCI"; + subsys-name = "Display"; + }; + + m_ldo28_reg: LDO28M { + regulator-name = "S2MPG12_LDO28"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x3C>; + schematic-name = "L28M_DISP"; + subsys-name = "Display"; + }; + }; + + odpm { + chip-name = "S2MPG12"; + sample-rate-uhz = <125000000>; + sample-rate-external-uhz = <31250000>; + + /* 120 minutes was selected as the spec + * for the sample rate (125sps) + * + * Note, this can be verified based on the + * number of bits in the ACC registers. + * ACC_COUNT is 20 bits. Thus, + * 2^20 - 1 = 1048575 ==> 8388.6 seconds + * ==> 139.81 minutes + */ + max-refresh-time-ms = <(120 * 60 * 1000)>; + + channels { + ch1: channel@0 { + rail-name = "VSEN_C1"; + channel_enabled; + }; + + ch2: channel@1 { + rail-name = "VSEN_C2"; + channel_enabled; + }; + + ch3: channel@2 { + rail-name = "VSEN_C3"; + channel_enabled; + }; + + ch4: channel@3 { + rail-name = "BUCK1M"; + channel_enabled; + }; + + ch5: channel@4 { + rail-name = "BUCK2M"; + channel_enabled; + }; + + ch6: channel@5 { + rail-name = "BUCK3M"; + channel_enabled; + }; + + ch7: channel@6 { + rail-name = "BUCK4M"; + channel_enabled; + }; + + ch8: channel@7 { + rail-name = "BUCK5M"; + channel_enabled; + }; + + ch9: channel@8 { + rail-name = "BUCK8M"; + channel_enabled; + }; + + ch10: channel@9 { + rail-name = "LDO15M"; + channel_enabled; + }; + + ch11: channel@10 { + rail-name = "BUCK10M"; + channel_enabled; + }; + + ch12: channel@11 { + rail-name = "BUCK6M"; + channel_enabled; + }; + }; + + rails { + use-regulators-as-rails; + + /* Additional rails */ + /* Note; VSEN_P is not supported */ + + m_ext4_rail: VSEN_C1 { + external_rail; + channel-en-index = <1>; + channel-mux-selection = <0x5C>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_MMWAVE"; + subsys-name = "Cellular"; + }; + + m_ext5_rail: VSEN_C2 { + external_rail; + channel-en-index = <2>; + channel-mux-selection = <0x5D>; + shunt-res-uohms = <5000>; + schematic-name = "VSYS_PWR_MODEM"; + subsys-name = "Modem"; + }; + + m_ext6_rail: VSEN_C3 { + external_rail; + channel-en-index = <4>; + channel-mux-selection = <0x5E>; + shunt-res-uohms = <5000>; + schematic-name = "VSYS_PWR_RFFE"; + subsys-name = "Cellular"; + }; + }; + }; + + s2mpg12_gpio: s2mpg12_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <6>; + gpio-ranges = <&s2mpg12_pinctrl 0 0 6>; + }; + + s2mpg12_pinctrl: s2mpg12_pinctrl { + }; + }; +}; + +&acpm_mfd_bus1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + s2mpg13mfd: s2mpg13mfd@2f { + compatible = "samsung,s2mpg13mfd"; + dev-name = "s2mpg13mfd"; + acpm-ipc-channel = <2>; + s2mpg13,wakeup = "enabled"; + reg = <0x2f>; + interrupts = <1 0 0>, // OCP_WARN_GPU + <1 0 1>; // SOFT_OCP_WARN_GPU + interrupt-parent = <&gpa0>; + pinctrl-names = "default"; + pinctrl-0 = <&s_pmic_irq>; + gpios = <&gpp19 0 0>, + <&gpp19 2 0>; + #thermal-sensor-cells = <1>; + + b2_ocp_warn_en = <1>; /* 1 : enable, 0 : disable */ + b2_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_ocp_warn_dvs_mask = <0>; /* 0 : not masked, 1 : masked */ + b2_ocp_warn_lvl = <0>; /* 12.0A */ + + b2_soft_ocp_warn_en = <0>; /* 1 : enable, 0 : disable */ + b2_soft_ocp_warn_cnt = <0>; /* 0 : 2 clock, 1 : 32 clock */ + b2_soft_ocp_warn_dvs_mask = <0>;/* 0 : not masked, 1 : masked */ + b2_soft_ocp_warn_lvl = <0>; /* 12.0A */ + + /* BUCK OCP Detection */ + buck_ocp_ctrl1 = <0xBB>; + buck_ocp_ctrl2 = <0xBB>; + buck_ocp_ctrl3 = <0xBB>; + buck_ocp_ctrl4 = <0xBB>; + buck_ocp_ctrl5 = <0xBB>; + buck_ocp_ctrl6 = <0xBB>; + buck_ocp_ctrl7 = <0x0B>; + + /* PCTRLSEL(VGPIO) 1~11 (CONTROL_SEL#) */ + sel_vgpio = <0x92 0x92 0x69 0x0A 0x9A 0x12 + 0xCA 0x81 0x08 0x00 0x8A>; + + regulators { + s_buck1_reg: BUCK1S { + regulator-name = "S2MPG13_BUCK1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x1>; + schematic-name = "S1S_VDD_CAM"; + subsys-name = "Multimedia"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x1>; + odpm_disable_in_sleep; + }; + + s_buck2_reg: BUCK2S { + regulator-name = "S2MPG13_BUCK2"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2>; + schematic-name = "S2S_VDD_G3D"; + subsys-name = "GPU"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x2>; + odpm_disable_in_sleep; + }; + + s_buck3_reg: BUCK3S { + regulator-name = "S2MPG13_BUCK3"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x3>; + schematic-name = "S3S_LLDO1"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x4>; + }; + + s_buck4_reg: BUCK4S { + regulator-name = "S2MPG13_BUCK4"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x4>; + schematic-name = "S4S_VDD2H_MEM"; + subsys-name = "DDR"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x8>; + }; + + s_buck5_reg: BUCK5S { + regulator-name = "S2MPG13_BUCK5"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x5>; + schematic-name = "S5S_VDDQ_MEM"; + subsys-name = "DDR"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x10>; + }; + + s_buck6_reg: BUCK6S { + regulator-name = "S2MPG13_BUCK6"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x6>; + schematic-name = "S6S_LLDO2"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x20>; + }; + + s_buck7_reg: BUCK7S { + regulator-name = "S2MPG13_BUCK7"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x7>; + schematic-name = "S7S_MLDO"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x40>; + }; + + s_buck8_reg: BUCK8S { + regulator-name = "S2MPG13_BUCK8"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x8>; + schematic-name = "S8S_VDD_G3D_L2"; + subsys-name = "GPU"; + buck_rail; + channel-en-byte-offset = <0>; + channel-en-index = <0x80>; + odpm_disable_in_sleep; + }; + + s_buck9_reg: BUCK9S { + regulator-name = "S2MPG13_BUCK9"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x9>; + schematic-name = "S9S_VDD_AOC"; + subsys-name = "AOC"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x1>; + }; + + s_buck10_reg: BUCK10S { + regulator-name = "S2MPG13_BUCK10"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0xA>; + schematic-name = "S10S_LLDO3"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x2>; + }; + + s_bucka_reg: BUCKA { + regulator-name = "S2MPG13_BUCKA"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0xC>; + schematic-name = "SA"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x8>; + }; + + s_buckboost_reg: BUCKBOOST { + regulator-name = "S2MPG13_BUCKBOOST"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x10>; + schematic-name = "BB_HLDO"; + subsys-name = "LDO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x10>; + }; + + s_buckc_reg: BUCKC { + regulator-name = "S2MPG13_BUCKC"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0xD>; + schematic-name = "SC"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x8>; + }; + + s_buckd_reg: BUCKD { + regulator-name = "S2MPG13_BUCKD"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0xB>; + schematic-name = "SD"; + subsys-name = "IO"; + buck_rail; + channel-en-byte-offset = <1>; + channel-en-index = <0x4>; + }; + + s_ldo1_reg: LDO1S { + regulator-name = "S2MPG13_LDO1"; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x21>; + schematic-name = "L1S_VDD_G3D_M"; + subsys-name = "GPU"; + }; + + s_ldo2_reg: LDO2S { + regulator-name = "S2MPG13_LDO2"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x22>; + schematic-name = "L2S_PLL_MIPI_UFS"; + subsys-name = "PLL"; + }; + + s_ldo3_reg: LDO3S { + regulator-name = "S2MPG13_LDO3"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x23>; + schematic-name = "L3S_PCIE1"; + subsys-name = "PCIE"; + }; + + s_ldo4_reg: LDO4S { + regulator-name = "S2MPG13_LDO4"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x24>; + schematic-name = "L4S_HS_AMP"; + subsys-name = "Audio"; + }; + + s_ldo5_reg: LDO5S { + regulator-name = "S2MPG13_LDO5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-initial-mode = ; + channel-mux-selection = <0x25>; + schematic-name = "L5S_PROX"; + subsys-name = "Prox"; + }; + + s_ldo6_reg: LDO6S { + regulator-name = "S2MPG13_LDO6"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x26>; + schematic-name = "L6S_DISP2_VCI"; + subsys-name = "Display"; + }; + + s_ldo7_reg: LDO7S { + regulator-name = "S2MPG13_LDO7"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-initial-mode = ; + channel-mux-selection = <0x27>; + schematic-name = "L7S_SENSORS_FPS"; + subsys-name = "Sensors"; + }; + + s_ldo8_reg: LDO8S { + regulator-name = "S2MPG13_LDO8"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1275000>; + regulator-initial-mode = ; + channel-mux-selection = <0x28>; + schematic-name = "L8S_UFS_VCCQ"; + subsys-name = "UFS"; + }; + + s_ldo9_reg: LDO9S { + regulator-name = "S2MPG13_LDO9"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x29>; + schematic-name = "L9S_GNSS_CORE"; + subsys-name = "GPS"; + }; + + s_ldo10_reg: LDO10S { + regulator-name = "S2MPG13_LDO10"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2A>; + schematic-name = "L10S_GNSS_RF"; + subsys-name = "GPS"; + }; + + s_ldo11_reg: LDO11S { + regulator-name = "S2MPG13_LDO11"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2B>; + schematic-name = "L11S_GNSS_AUX"; + subsys-name = "GPS"; + }; + + s_ldo12_reg: LDO12S { + regulator-name = "S2MPG13_LDO12"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x2C>; + schematic-name = "L12S_TS2_DVDD"; + subsys-name = "Touch"; + }; + + s_ldo13_reg: LDO13S { + regulator-name = "S2MPG13_LDO13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2D>; + schematic-name = "L13S_DPAUX"; + subsys-name = "Display"; + }; + + s_ldo14_reg: LDO14S { + regulator-name = "S2MPG13_LDO14"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2E>; + schematic-name = "L14S_NFC"; + subsys-name = "NFC"; + }; + + s_ldo15_reg: LDO15S { + regulator-name = "S2MPG13_LDO15"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x2F>; + schematic-name = "L15S_UDFPS"; + subsys-name = "FPS"; + }; + + s_ldo16_reg: LDO16S { + regulator-name = "S2MPG13_LDO16"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x30>; + schematic-name = "L16S_UWB"; + subsys-name = "UWB"; + }; + + s_ldo17_reg: LDO17S { + regulator-name = "S2MPG13_LDO17"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x31>; + schematic-name = "L17S_UWB"; + subsys-name = "UWB"; + }; + + s_ldo18_reg: LDO18S { + regulator-name = "S2MPG13_LDO18"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x32>; + schematic-name = "L18S_PCIE1"; + subsys-name = "PCIE"; + }; + + s_ldo19_reg: LDO19S { + regulator-name = "S2MPG13_LDO19"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x33>; + schematic-name = "L19S_DMIC3"; + subsys-name = "DMIC"; + }; + + s_ldo20_reg: LDO20S { + regulator-name = "S2MPG13_LDO20"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x34>; + schematic-name = "L20S_DMIC45"; + subsys-name = "DMIC"; + }; + + s_ldo21_reg: LDO21S { + regulator-name = "S2MPG13_LDO21"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-initial-mode = ; + channel-mux-selection = <0x35>; + schematic-name = "L21S_VDD2L_MEM"; + subsys-name = "DDR"; + }; + + s_ldo22_reg: LDO22S { + regulator-name = "S2MPG13_LDO22"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x36>; + schematic-name = "L22S_UDFPS"; + subsys-name = "FPS"; + }; + + s_ldo23_reg: LDO23S { + regulator-name = "S2MPG13_LDO23"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x37>; + schematic-name = "L23S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo24_reg: LDO24S { + regulator-name = "S2MPG13_LDO24"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x38>; + schematic-name = "L24S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo25_reg: LDO25S { + regulator-name = "S2MPG13_LDO25"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x39>; + schematic-name = "L25S_SPARE"; + subsys-name = "Spare"; + }; + + s_ldo26_reg: LDO26S { + regulator-name = "S2MPG13_LDO26"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x3A>; + schematic-name = "L26S_S5910"; + subsys-name = "S5910"; + }; + + s_ldo27_reg: LDO27S { + regulator-name = "S2MPG13_LDO27"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1950000>; + regulator-initial-mode = ; + channel-mux-selection = <0x3B>; + schematic-name = "L27S_S5910"; + subsys-name = "S5910"; + }; + + s_ldo28_reg: LDO28S { + regulator-name = "S2MPG13_LDO28"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + channel-mux-selection = <0x3C>; + schematic-name = "L28S_HS_AMP"; + subsys-name = "Audio"; + }; + }; + + odpm { + chip-name = "S2MPG13"; + sample-rate-uhz = <125000000>; + sample-rate-external-uhz = <31250000>; + + /* 120 minutes was selected as the spec + * for the sample rate (125sps) + * + * Note, this can be verified based on the + * number of bits in the ACC registers. + * ACC_COUNT is 20 bits. Thus, + * 2^20 - 1 = 1048575 ==> 8388.6 seconds + * ==> 139.81 minutes + */ + max-refresh-time-ms = <(120 * 60 * 1000)>; + + channels { + ch13: channel@0 { + rail-name = "VSEN_C4"; + channel_enabled; + }; + + ch14: channel@1 { + rail-name = "VSEN_C5"; + channel_enabled; + }; + + ch15: channel@2 { + rail-name = "LDO9S"; + channel_enabled; + }; + + ch16: channel@3 { + rail-name = "BUCK1S"; + channel_enabled; + }; + + ch17: channel@4 { + rail-name = "BUCK2S"; + channel_enabled; + }; + + ch18: channel@5 { + rail-name = "BUCK4S"; + channel_enabled; + }; + + ch19: channel@6 { + rail-name = "BUCK5S"; + channel_enabled; + }; + + ch20: channel@7 { + rail-name = "BUCK8S"; + channel_enabled; + }; + + ch21: channel@8 { + rail-name = "BUCK9S"; + channel_enabled; + }; + + ch22: channel@9 { + rail-name = "LDO7S"; + channel_enabled; + }; + + ch23: channel@10 { + rail-name = "LDO14S"; + channel_enabled; + }; + + ch24: channel@11 { + rail-name = "LDO2S"; + channel_enabled; + }; + }; + + rails { + use-regulators-as-rails; + + /* Additional rails */ + /* Note; VSEN_P is not supported */ + + s_ext4_rail: VSEN_C4 { + external_rail; + channel-en-index = <1>; + channel-mux-selection = <0x5C>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_DISPLAY"; + subsys-name = "Display"; + }; + + s_ext5_rail: VSEN_C5 { + external_rail; + channel-en-index = <2>; + channel-mux-selection = <0x5D>; + shunt-res-uohms = <10000>; + schematic-name = "VSYS_PWR_WLAN_BT"; + subsys-name = "WLAN-BT"; + }; + + s_ext6_rail: VSEN_C6 { + external_rail; + channel-en-index = <4>; + channel-mux-selection = <0x5E>; + shunt-res-uohms = <5000>; + schematic-name = "VSEN_C6_NC"; + subsys-name = "Spare"; + }; + }; + }; + + s2mpg13_gpio: s2mpg13_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + gpio-ranges = <&s2mpg13_pinctrl 0 0 8>; + }; + + s2mpg13_pinctrl: s2mpg13_pinctrl { + }; + }; +}; + +&acpm_mbox_test { + main-pmic = <&s2mpg12mfd>; + sub-pmic = <&s2mpg13mfd>; + acpm-ipc-channel = <2>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ppmu.dtsi b/arch/arm64/boot/dts/google/gs201-ppmu.dtsi new file mode 100644 index 000000000000..02157ea5499d --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ppmu.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 PPMU device tree source + * + * Copyright (c) 2021 Google LLC. + * + */ + +#include + +/ { + gs201-ppmu { + compatible = "samsung,exynos-bcm_dbg"; + + pd-name = "pd-csis", "pd-ipp", "pd-tnr", "pd-bo", "pd-g2d", + "pd-misc", "pd-dpu", "pd-pdp", "pd-g3aa", "pd-dns", + "pd-mcsc", "pd-gdc", "pd-mfc", "pd-hsi2", "pd-eh", + "pd-tpu", "pd-gsa", "pd-aoc", "pd-hsi0", "pd-hsi1", + "pd-aur", "pd-itp"; + + max_define_event = ; + /* define_event_index ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_events = , + , + , + , + , + , + ; + default_define_event = ; + + /* sm_id_mask sm_id_value */ + define_filter_id = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_id_active = + , + , + , + , + , + , + ; + /* sm_other_type0 sm_other_mask0 sm_other_value0 */ + define_filter_other_0 = , + , + , + , + , + , + ; + /* sm_other_type1 sm_other_mask1 sm_other_value1 */ + define_filter_other_1 = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_filter_other_active = + , + , + , + , + , + , + ; + + /* peak_mask peak_id */ + define_sample_id = , + , + , + , + , + , + ; + /* ev0 ev1 ev2 ev3 ev4 ev5 ev6 ev7 */ + define_sample_id_enable = + , + , + , + , + , + , + ; + + bcm_ip_nr = <84>; + bcm_ip_print_nr = <10>; + + ip-name = "csis_d1", "csis_d0", "ipp", "msa", "d8_tnr", "d7_tnr", + "d6_tnr", "d5_tnr", "d4_tnr", "d3_tnr", "d2_tnr", + "d1_tnr", "d0_tnr", "bo", "d2_g2d", "d1_g2d", + "d0_g2d", "misc", "dpu2", "dpu1", "dpu0", + "pdp_vra", "g3aa", "d1_dns", "d0-dns", "d1_mcsc", "d0_mcsc", + "d1_itsc", "d0_itsc", "d3_gdc", "d2_gdc", "d1_gdc", "d0_gdc", "d2_scsc", + "d1_scsc", "d0_scsc", "d1_mfc", "d0_mfc", "hsi2", "tpu", + "gpu0", "gpu1", "gpu2", "gpu3", "bus2_m0", + "bus2_m1", "bus2_m2", "bus2_m3", "gsacore", "aoc", + "usb", "hsi0_bus0", "hsi0_aoc", "hsi1", "ace_cpucl1", + "ace_cpucl0", "cpu0", "cpu1", "cpu2", "cpu3", + "core_m0", "core_m1", "core_m2", "core_m3", "core_cci", + "core_dp", "bus0_m0", + "slc_ch0_1", "slc_ch0_0", "slc_ch1_1", "slc_ch1_0", "slc_ch2_1", + "slc_ch2_0", "slc_ch3_1", "slc_ch3_0", "slc_bcast_1", "slc_bcast_0", + "bus1_m0", "bus1_m1", "bus1_m2", "bus1_m3", "aur0", "aur1", "itp"; + + initial_run_bcm_ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, + <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>, <46>, <47>, + <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>, <60>, + <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>, <70>, + <71>, <72>, <73>, <74>, <77>, <78>, <79>, <80>, + <81>, <82>, <83>; + + initial_bcm_run = ; + /* usec (max 1000000 usec) */ + initial_period = <1000>; + initial_bcm_mode = ; + available_stop_owner = ; + buff_size = <0x100000>; + + ipc_bcm_event { + plugin-len = <5>; + plugin-name = "BCM"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-pwm.dtsi b/arch/arm64/boot/dts/google/gs201-pwm.dtsi new file mode 100644 index 000000000000..fe33df779c92 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-pwm.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC PWM device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/ { + sec_pwm: pwm@10DF0000 { + compatible = "samsung,s3c6400-pwm"; + reg = <0x00000000 0x10DF0000 0x00001000>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>; + #pwm-cells = <3>; + clocks = <&clock GATE_PERIC1_TOP0_PWM>, <&clock OSCCLK>; + clock-names = "pwm_pclk", "pwm_sclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-raven-display-constants.dtsi b/arch/arm64/boot/dts/google/gs201-raven-display-constants.dtsi new file mode 100644 index 000000000000..7065ab1723e8 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-raven-display-constants.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Raven display-specific constants + * + * Copyright 2021 Google LLC. + * + */ +#define RAVEN_VCI_MICROVOLT 3025000 +#define RAVEN_VDD_NORMAL_MICROVOLT 1200000 +#define RAVEN_VDD_LP_MICROVOLT 1050000 diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-audio.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-audio.dtsi new file mode 100644 index 000000000000..db841eed8e01 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-audio.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Ravenclaw common audio device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + * + * cs35l41_l = top + * cs35l41_r = bottom + */ +#include +#include +#include + +&aoc { + aoc-board-cfg = "rc"; + aoc-board-id = <0x30201>; + aoc-board-rev = <0x10000>; +}; + +&dai_be_tdm0_rx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&dai_be_tdm0_tx { + codec { + sound-dai = <&cs35l41_l 0>, + <&cs35l41_r 0>; + }; +}; + +&aoc_snd_card { + clks { + sys { + sys@cs35l41_l { + comp = <&cs35l41_l>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + + sys@cs35l41_r { + comp = <&cs35l41_r>; + src = "BCLK"; + /* clk id */ + id = <0>; + /* clk source */ + srcid = <0>; + /* in clk multiple */ + in_mul = <1>; + /* out clk multiple */ + out_mul = <1>; + }; + }; + }; +}; + +/* GPIO_FAR_ALIVE */ +&pinctrl_1 { + cs35l41_l_irq: cs35l41-l-irq { + samsung,pins = "gpa6-3"; /* XEINT_3 - AMP1_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_irq: cs35l41-r-irq { + samsung,pins = "gpa8-6"; /* XEINT_18 - AMP2_IRQ_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +/* GPIO_PERIC0 */ +&pinctrl_4 { + cs35l41_clk: cs35l41-clk { + samsung,pins = "gpp14-0"; /* XAPC_USI7_RXD_CLK_SCL - AUDIO_SPI_CLK */ + samsung,pin-drv = ; + }; + + cs35l41_mosi: cs35l41-mosi { + samsung,pins = "gpp14-1"; /* XAPC_USI7_TXD_DO_SDA - AUDIO_SPI_MOSI */ + samsung,pin-drv = ; + }; + + cs35l41_miso: cs35l41-miso { + samsung,pins = "gpp14-2"; /* XAPC_USI7_RTSn_DI - AUDIO_SPI_MISO */ + samsung,pin-pud = ; + }; + + cs35l41_cs1: cs35l41-cs1 { + samsung,pins = "gpp14-3"; /* XAPC_USI7_CTSN_CSN - AUDIO_AMP1_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_l_rst: cs35l41-l-rst { + samsung,pins = "gpp17-1"; /* XAPC_VSYNC8 - AMP1_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +/* GPIO_PERIC1 */ +&pinctrl_5 { + cs35l41_cs2: cs35l41-cs2 { + samsung,pins = "gpp22-1"; /* XAPC_GPIO5 - AUDIO_AMP2_SPI_CS_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + cs35l41_r_rst: cs35l41-r-rst { + samsung,pins = "gpp25-2"; /* XAPC_USI13_RTSn_DI - AMP2_RESET_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi7_cs_func { + samsung,pins = "gpp14-3"; + samsung,pin-drv = ; +}; + +&spi_7 { + /* XAPC_USI7 */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus &spi7_cs_func &cs35l41_cs2 + &cs35l41_miso &cs35l41_mosi &cs35l41_clk>; + cs-gpios = <&gpp14 3 GPIO_ACTIVE_HIGH>, <&gpp22 1 GPIO_ACTIVE_HIGH>; + + cs35l41_l: cs35l41@0 { + #sound-dai-cells = <1>; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <0>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_l_irq &cs35l41_l_rst>; + + interrupt-parent = <&gpa6>; + interrupts = <3 0 0>; + + reset-gpios = <&gpp17 1 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + /* cirrus,hibernate-enable; */ + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio = <&gpp14 3 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; + + + cs35l41_r: cs35l41@1 { + #sound-dai-cells = <1>; + sound-name-prefix = "R"; + compatible = "cirrus,cs35l41"; + spi-max-frequency = <25000000>; + reg = <1>; + + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&cs35l41_r_irq &cs35l41_r_rst>; + + interrupt-parent = <&gpa8>; + interrupts = <6 0 0>; + + reset-gpios = <&gpp25 2 0>; + + VA-supply = <&s_bucka_reg>; + VP-supply = <&V_SYS_dummy>; + + cirrus,boost-peak-milliamp = <3500>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <30>; + + cirrus,asp-sdout-hiz = <3>; + cirrus,tuning-has-prefix; + cirrus,left-channel-amp; + cirrus,hw-noise-gate-select = <63>; + /* cirrus,hibernate-enable; */ + + cirrus,gpio-config2 { + cirrus,gpio-src-select = <0x5>; + cirrus,gpio-output-enable; + }; + + controller-data { + cs-gpio =<&gpp22 1 GPIO_ACTIVE_HIGH>; + samsung,spi-feedback-delay = <1>; + /* SET SPI CS CONTROL TO AUTOMATIC */ + samsung,spi-chip-select-mode = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-common.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-common.dtsi new file mode 100644 index 000000000000..c2add011e882 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-common.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ravenclaw device tree source + * + * Copyright 2021 Google,LLC + */ + +#include "gs201-cloudripper-common.dtsi" + +#include "gs201-ravenclaw-audio.dtsi" +#include "gs201-ravenclaw-display.dtsi" +#include "gs201-ravenclaw-fingerprint.dtsi" +#include "gs201-ravenclaw-pmic.dtsi" +#include "gs201-ravenclaw-thermal.dtsi" +#include "gs201-ravenclaw-touch.dtsi" +#include "gs201-ravenclaw-typec.dtsi" +#include "gs201-ravenclaw-wcharger.dtsi" +#include "gs201-ravenclaw-usecases.dtsi" +#include "gs201-ravenclaw-uwb.dtsi" diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_0.dts b/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_0.dts new file mode 100644 index 000000000000..d0c49e7d50c1 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_0.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cloudripper DEV device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-ravenclaw-common.dtsi" + +/ { + board_id = <0x30201>; + board_rev = <0x10000>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 Ravenclaw Dev 1.0 based on GS201"; + compatible = "google,GS201 RAVENCLAW", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_1.dts b/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_1.dts new file mode 100644 index 000000000000..13fb21aca315 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-dev1_1.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Cloudripper DEV device tree source + * + * Copyright 2021 Google,LLC + */ + +/dts-v1/; +/plugin/; + +#include "gs201-ravenclaw-common.dtsi" + +/ { + board_id = <0x30201>; + board_rev = <0x10001>; + fragment@boardbase { + target-path="/"; + __overlay__ { + model = "GS201 Ravenclaw Dev 1.1 based on GS201"; + compatible = "google,GS201 RAVENCLAW", "google,GS201"; + }; + }; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-display.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-display.dtsi new file mode 100644 index 000000000000..c328ba31f5d3 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-display.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Display nodes for slider-related boards. + * + * Copyright 2021 Google LLC + * + */ + +#include "gs201-raven-display-constants.dtsi" + +&drmdsim0 { + samsung_s6e3hc3: panel@0 { + compatible = "samsung,s6e3hc3"; + label = "samsung-s6e3hc3"; + channel = <0>; + touch = <&spitouch>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + vddd-supply = <&m_ldo28_reg>; + vddd-normal-microvolt = ; + vddd-lp-microvolt = ; + vci-supply = <&m_ldo27_reg>; + vddi-supply = <&s_bucka_reg>; + }; + panel@1 { + compatible = "samsung,emul"; + label = "samsung-emul"; + channel = <0>; + + /* reset, power */ + reset-gpios = <&gpa7 1 GPIO_ACTIVE_HIGH>; + }; +}; + + diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-fingerprint.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-fingerprint.dtsi new file mode 100644 index 000000000000..f2ab8a89b939 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-fingerprint.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Goodix fps device tree source + * + * Copyright 2021 Google,LLC. + */ + +&pinctrl_4 { + goodixfp_pins: goodixfp_pins { + samsung,pins = "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&odm { + goodixfp { + status = "okay"; + compatible = "goodix,fingerprint"; + interrupt-parent = <&gpa9>; + interrupts = <2 0>; + spi-max-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&goodixfp_pins>; + fp-gpio-irq = <&gpa9 2 GPIO_ACTIVE_HIGH>; + fp-gpio-reset = <&gpp1 1 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-pmic.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-pmic.dtsi new file mode 100644 index 000000000000..7691214d1047 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-pmic.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Ravenclaw-specific PMIC settings + * + * Copyright 2021 Google LLC. + * + */ + +#include "gs201-raven-display-constants.dtsi" + +/* Display: vci-supply voltage */ +&m_ldo27_reg { + regulator-min-microvolt = ; + regulator-max-microvolt = ; +}; + +/* Display: Ravenclaw & Cloudripper use LDO28M for display. */ +&m_ldo28_reg { + regulator-initial-mode = ; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + regulator-ramp-delay = <1200>; + regulator-enable-ramp-delay = <125>; +}; + +/* Fingerprint: Ravenclaw uses LDO15S for Fingerprint. */ +&s_ldo15_reg { + regulator-always-on; +}; + +/* UWB: Ravenclaw and Cheetah use LDO[16,17]S for UWB */ +&s_ldo16_reg { + regulator-always-on; + regulator-initial-mode = ; +}; +&s_ldo17_reg { + regulator-always-on; + regulator-initial-mode = ; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-thermal.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-thermal.dtsi new file mode 100644 index 000000000000..2287db3845b4 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-thermal.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 ravenclaw-specific thermal device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com + */ + +#include + +&acpm_mfd_bus1 { + s2mpg13mfd@2f { + gs201_tm1: gs201_spmic_tm1 { + compatible = "google,s2mpg13-spmic-thermal"; + #thermal-sensor-cells = <1>; + adc_chan_en = /bits/ 8 <0x23>; + }; + }; +}; + +/* Thermal Zones */ +&thermal_zones { + neutral_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 0>; + trips { + trip_config0: trip-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + quiet_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 1>; + trips { + trip_config1: trip-config1 { + temperature = <56000>; + hysteresis = <1000>; + type = "passive"; + }; + backup_shutdown_sw: backup-shutdown-sw { + temperature = <57000>; + hysteresis = <1000>; + type = "critical"; + }; + backup_shutdown_hw: backup-shutdown-hw { + temperature = <59000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + }; + qi_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 2>; + trips { + trip_config2: trip-config2 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 3>; + trips { + trip_config3: trip-config3 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + usb_pwr_therm2 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 4>; + trips { + trip_config4: trip-config4 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + disp_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 5>; + trips { + trip_config5: trip-config5 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + spmic_therm_6 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 6>; + trips { + trip_config6: trip-config6 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + gnss_tcxo_therm { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&gs201_tm1 7>; + trips { + trip_config7: trip-config7 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-touch.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-touch.dtsi new file mode 100644 index 000000000000..1030655efe7f --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-touch.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google Ravenclaw device tree source + * + * Copyright 2021 Google Inc. + * + */ + +#include + +/* + * Touch is connected to spi_0, pins: + * CLK=GPP20[0], MOSI=GPP20[1], MISO=GPP20[2], CS=GPP20[3] + * TS_RESET_L = C26 = XAPC_USI11_RTSN_DI = GPP23[2] = <&gpp23 2 0> + * TS_INT_L = AT22 = XEINT_8 = GPA7[0] = <&gpa7 0 0> + * + * DVDD = PP1800_L25M_TSP_DVDD = ??? = VLDO25M = "PP1800_L25M_TSP"? + * AVDD = PP3300_L26M_TS_AVDD = ??? = VLDO26M = "PP3300_L26M_TSP"? + * + * AP2AOC: XHSI1_GPIO2 - GPH1[0] -> XAOC_GPIO13 - gpio_in[87] + * AOC2AP: XAOC_GPIO8 - gpio_in[74] -> XEINT_19 - GPA8[7] + */ + +&spi_0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus &spi0_cs_func>; +}; + +&spitouch { + status = "okay"; + compatible = "sec,sec_ts"; + + sec,panel_map = <&samsung_s6e3hc3 0>; + + sec,touch_offload_id = /bits/ 8 <'0' '0' 'r' '4'>; + sec,mm2px = /bits/ 8 <20>; + sec,encoded_enable = <1>; + + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + + sec,spi_cs_gpio = <&gpp20 3 0>; + sec,irq_gpio = <&gpa7 0 0>; + sec,reset_gpio = <&gpp23 2 0>; + sec,firmware_name = "s6sy79x.bin"; + sec,mis_cal_check = <1>; + sec,heatmap_mode = <1>; + + sec,max_coords = <1440 3120>; + + controller-data { + samsung,spi-feedback-delay = <0>; + samsung,spi-chip-select-mode = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-typec.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-typec.dtsi new file mode 100644 index 000000000000..71d98602bfca --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-typec.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Google GS201 Ravenclaw Type-C device tree + * + * Copyright (c) 2021 Google, LLC + * + */ + +&max77759tcpc { + ovp-present; + in-switch-gpio = <&max777x9_gpio 5 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-usecases.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-usecases.dtsi new file mode 100644 index 000000000000..4a9558a4c501 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-usecases.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Usecases specific to the gs201 platform + * + * Copyright 2021 Google,LLC + * + */ + +/* system use cases */ +&max77759_chg { + /* external boost */ + max77759,bst-on = <&max777x9_gpio 4 GPIO_ACTIVE_HIGH>; /* MW: OTG_BOOST_EN */ + max77759,extbst-ctl = <&max77759_tcpc_gpio 0 GPIO_ACTIVE_HIGH>; + max77759,extbst-mode = <&s2mpg12_gpio 4 GPIO_ACTIVE_HIGH>; + max77759,cpout-ctl = <&p9xxx_gpio 3 GPIO_ACTIVE_HIGH>; + + /* WLC_TX_SW_EN */ + /* max77759,ls1-en = <&max777x9_gpio 5 GPIO_ACTIVE_HIGH>; */ + /* MW_OVP_EN_L configured by USB driver, not here */ + + max77759,ls2-en = <&s2mpg12_gpio 3 GPIO_ACTIVE_HIGH>; /* GRA-M: WLC_TX_SW_EN */ + + /* b/202526678 handles for WLC_RX->WLC_RX+GPIO */ + max77759,wlc-en = <&gpp0 0 GPIO_ACTIVE_HIGH>; + max77759,wlc-vout_is_invalid = <&p9xxx_gpio 14 GPIO_ACTIVE_HIGH>; + max77759,cpout-en = <&p9xxx_gpio 1 GPIO_ACTIVE_HIGH>; + /* for OTG related usecase*/ + max77759,rx-to-rx-otg-en; /* support RX -> RX+OTG */ + max77759,ext-otg-only; /* use external OTG only */ + /* WLC_TX ON : extboost on -> loadswitch on */ + /* OFF: loadswitch off -> extboost off */ + max77759,bst-lsw-sequence; + + /* The high/low bound of vbatt for FCCM mode */ + max77759,otg-fccm-vbatt-upperbd = <4000>; + max77759,otg-fccm-vbatt-lowerbd = <3900>; + + max77759,gpio_dc_switch = <&p9xxx_gpio 4 GPIO_ACTIVE_HIGH>; /* WLC_RX_SW_EN */ +}; diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-uwb.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-uwb.dtsi new file mode 100644 index 000000000000..412bc32a3f76 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-uwb.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS201 Board device tree source + * + * Copyright (c) 2021 Google, LLC + * https://www.google.com +*/ + +#include +#include + +&pinctrl_1 { + dw3xxx_irq: dw3xxx-irq { + samsung,pins = "gpa6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + + +&pinctrl_4 { + dw3xxx_ap_rst: dw3xxx-ap-rst { + samsung,pins = "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&spi_16 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + dw3xxx_prod@0 { + compatible = "decawave,dw3000"; + reg = <0>; + + interrupt-parent = <&gpa6>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&spi16_cs &dw3xxx_irq &dw3xxx_ap_rst>; + spi-max-frequency = <40000000>; + + uwbhal,reset-gpio = <&gpp2 3 GPIO_OPEN_DRAIN>; + power_reg_2p5-supply = <&s_ldo16_reg>; + power_reg_1p8-supply = <&s_ldo17_reg>; + + decawave,eui64 = /bits/ 64 <0>; + decawave,panid = /bits/ 16 <0>; + + status = "okay"; + + controller-data { + cs-gpio = <&gpp26 3 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&spi16_bus { + samsung,pin-drv = ; + samsung,pin-pud-pdn = ; +}; + +&spi16_cs { + samsung,pin-drv = ; +}; + diff --git a/arch/arm64/boot/dts/google/gs201-ravenclaw-wcharger.dtsi b/arch/arm64/boot/dts/google/gs201-ravenclaw-wcharger.dtsi new file mode 100644 index 000000000000..b11145d01455 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ravenclaw-wcharger.dtsi @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Wireless Charger device tree entries. + * + * Copyright 2020 Google Inc. + */ + +#include +#include + +/ { + fragment@wlc { + target-path = "/"; + __overlay__ { + google,charger { + google,wlc-power-supply = "wireless"; + }; + }; + }; +}; + +&pinctrl_0 { + /* XIENT_25 P9412 Wireless Charger Interrupt */ + wc_irq: wc_irq { + samsung,pins = "gpa9-5"; /* QI_INT_R */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_4 { + /* XAPC_GPIO0 P9412 Wireless Charger Enable */ + wc_en: wc_en { + samsung,pins = "gpp0-0"; /* QI_EN_L */ + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; +}; + +&hsi2c_15 { + p9412@3c { + dev-name = "p9412"; + compatible = "idt,p9412"; + reg = <0x3c>; + status = "ok"; + + /* Support p9412 GPIO */ + idt,has_p9412_gpio; + + idt,has_rtx = <0>; + /* Granvilla GPIO 2~4 */ + idt,gpio_ben = <&max777x9_gpio 4 GPIO_ACTIVE_HIGH>; /* EXT_BST_EN */ + idt,gpio_boost = <&s2mpg12_gpio 3 GPIO_ACTIVE_HIGH>; /* WLC_TX_SW_EN */ + /* idt,gpio_switch = <&p9xxx_gpio 3 GPIO_ACTIVE_HIGH>; */ /* EXT_BST_VTRX */ + idt,gpio_extben = <&s2mpg12_gpio 2 GPIO_ACTIVE_HIGH>; /* AP2QI_EXTBST_EN */ + + /* WLCDC */ + idt,gpio_dc_switch = <&s2mpg12_gpio 0 GPIO_ACTIVE_HIGH>; /* WLC_RX_SW_EN */ + idt,max_vout_mv = <19500>; + idt,has_wlc_dc = <1>; + google,power_mitigate_threshold = <90>; + + pinctrl-names = "default"; + pinctrl-0 = <&wc_irq &wc_en>; + + idt,gpio_qien = <&gpp0 0 GPIO_ACTIVE_HIGH>; + idt,irq_gpio = <&gpa9 5 GPIO_ACTIVE_LOW>; + + p9xxx_gpio: p9xxx_gpio { + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-rmem.dtsi b/arch/arm64/boot/dts/google/gs201-rmem.dtsi new file mode 100644 index 000000000000..98f073518f45 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-rmem.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GS201 SoC reserved memory + * + * Copyright 2021 Google LLC + */ + +#include +#include + +/ { + + bootloader_log { + compatible = "google,bldr_log"; + reg = <0x0 0xfd800000 0x80000>, <0x0 0xfd880000 0x80000>; + reg-names = "bl_log", "bl_old_log"; + memory-region = <&bldr_log_reserved>; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ect_binary: ect_binary { + compatible = "exynos,ect_rmem"; + reg = <0x0 0x90000000 0x0003A000>; + }; + + gsa_reserved_protected: gsa@0x90200000 { + reg = <0x0 0x90200000 0x400000>; + no-map; + }; + + tpu_fw_ctx_reserved: tpu_ctx@0x91E00000 { + reg = <0x0 0x91E00000 0x1200000>; + no-map; + }; + + tpu_fw_reserved: tpu_fw@0x93000000 { + reg = <0x0 0x93000000 0x1000000>; + no-map; + }; + + aoc_reserve: aoc@0x94000000 { + reg = <0x0 0x94000000 0x03000000>; + no-map; + }; + + gxp_fw_reserved: gxp_fw@98000000 { + reg = <0x0 0x98000000 0x0400000>; + no-map; + }; + + gxp_scratchpad_reserved: gxp_scratchpad@98400000 { + reg = <0x0 0x98400000 0x00100000>; + no-map; + }; + + abl_reserved: abl@f8800000 { + reg = <0x0 0xf8800000 0x02000000>; + no-map; + }; + + dss_log_reserved: dss_log_reserved@fd3f0000 { + reg = <0 0xfd3f0000 0x0000e000>; + no-map; + }; + + debug_kinfo_reserved: debug_kinfo_reserved@fd3fe000 { + reg = <0 0xfd3fe000 0x00001000>; + no-map; + }; + + ramoops_mem@fd3ff000 { + compatible = "ramoops"; + reg = <0 0xfd3ff000 0x400000>; + console-size = <0x200000>; + pmsg-size = <0x200000>; + }; + + bldr_log_reserved: bldr_log_reserved@fd800000 { + reg = <0 0xfd800000 0x00100000>; + no-map; + }; + + bldr_log_hist_reserved: bldr_log_hist_reserved@fd900000 { + reg = <0 0xfd900000 0x00002000>; + no-map; + }; + + cp_rmem: cp_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0xEA400000 0x00800000>; + rmem_index = <0>; + }; + + cp_msi_rmem: cp_msi_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0xF6200000 0x00001000>; + rmem_index = <1>; + }; + + cp_rmem_1: cp_rmem_1 { + compatible = "exynos,modem_if"; + reg = <0x0 0xE8000000 0x02000000>; + rmem_index = <2>; + }; + + cp_aoc_rmem: cp_aoc_rmem { + compatible = "exynos,modem_if"; + reg = <0x0 0x197FD000 0x00003000>; + rmem_index = <3>; + }; + + debug_snapshot { + #address-cells = <2>; + #size-cells = <1>; + + header: header { + reg = <0 DSS_HEADER_ADDR DSS_HEADER_SIZE>; + no-map; + }; + log_kevents: log_kevents { + reg = <0 DSS_LOG_KEVENTS_ADDR + DSS_LOG_KEVENTS_SIZE>; + no-map; + }; + log_bcm: log_bcm { + reg = <0 DSS_LOG_BCM_ADDR DSS_LOG_BCM_SIZE>; + no-map; + }; + log_s2d: log_s2d { + reg = <0 DSS_LOG_S2D_ADDR DSS_LOG_S2D_SIZE>; + no-map; + }; + log_arrdumpreset: log_array_reset { + reg = <0 DSS_LOG_ARRAYRESET_ADDR + DSS_LOG_ARRAYRESET_SIZE>; + no-map; + }; + log_arrdumppanic: log_array_panic { + reg = <0 DSS_LOG_ARRAYPANIC_ADDR + DSS_LOG_ARRAYPANIC_SIZE>; + no-map; + }; + log_slcdump: log_slcdump { + reg = <0 DSS_LOG_SLCDUMP_ADDR + DSS_LOG_SLCDUMP_SIZE>; + no-map; + }; + log_preslcdump: log_preslcdump { + reg = <0 DSS_LOG_PRE_SLCDUMP_ADDR + DSS_LOG_SLCDUMP_SIZE>; + no-map; + }; + log_itmon: log_itmon { + reg = <0 DSS_LOG_ITMON_ADDR DSS_LOG_ITMON_SIZE>; + no-map; + }; + }; + + seclog_mem: seclog_mem { + compatible = "exynos,seclog"; + reg = <0 SECLOG_LOG_BUF_BASE SECLOG_LOG_BUF_TOTAL_SIZE>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-s2mpu.dtsi b/arch/arm64/boot/dts/google/gs201-s2mpu.dtsi new file mode 100644 index 000000000000..6e61a0870352 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-s2mpu.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/ { + s2mpu_aur_idma: s2mpu_aur_idma@25a70000 { + compatible = "google,s2mpu"; + reg = <0x0 0x25a70000 0x10000>; + interrupts = ; + power-domains = <&pd_aur>; + }; + + s2mpu_aur_inst_data: s2mpu_aur_inst_data@25aa0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x25aa0000 0x10000>; + interrupts = ; + power-domains = <&pd_aur>; + }; + + s2mpu_bo: s2mpu_bo@1ca60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1ca60000 0x10000>; + interrupts = ; + power-domains = <&pd_bo>; + }; + + s2mpu_cpucl0: s2mpu_cpucl0@20c70000 { + compatible = "google,s2mpu"; + reg = <0x0 0x20c70000 0x10000>; + interrupts = ; + always-on; + }; + + s2mpu_csis0: s2mpu_csis0@1a520000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a520000 0x10000>; + interrupts = ; + power-domains = <&pd_csis>; + }; + + s2mpu_csis1: s2mpu_csis1@1a550000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a550000 0x10000>; + interrupts = ; + power-domains = <&pd_csis>; + }; + + s2mpu_dns: s2s2mpu_dnsmpu@1b0a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b0a0000 0x10000>; + interrupts = ; + power-domains = <&pd_dns>; + }; + + s2mpu_dpu0: s2mpu_dpu0@1c160000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c160000 0x10000>; + interrupts = ; + power-domains = <&pd_dpu>; + }; + + s2mpu_dpu1: s2mpu_dpu1@1c170000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c170000 0x10000>; + interrupts = ; + power-domains = <&pd_dpu>; + }; + + s2mpu_dpu2: s2mpu_dpu2@1c180000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c180000 0x10000>; + interrupts = ; + power-domains = <&pd_dpu>; + }; + + s2mpu_eh: s2mpu_eh@17040000 { + compatible = "google,s2mpu"; + reg = <0x0 0x17040000 0x10000>; + interrupts = ; + }; + + s2mpu_g2d0: s2mpu_g2d0@1c680000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c680000 0x10000>; + interrupts = ; + power-domains = <&pd_g2d>; + }; + + s2mpu_g2d1: s2mpu_g2d1@1c6b0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c6b0000 0x10000>; + interrupts = ; + power-domains = <&pd_g2d>; + }; + + s2mpu_g2d2: s2mpu_g2d2@1c730000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c730000 0x10000>; + interrupts = ; + power-domains = <&pd_g2d>; + }; + + s2mpu_g3aa: s2mpu_g3aa@1a8a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1a8a0000 0x10000>; + interrupts = ; + power-domains = <&pd_g3aa>; + }; + + s2mpu_g3d: s2mpu_g3d@20080000 { + compatible = "google,s2mpu"; + reg = <0x0 0x20080000 0x10000>; + interrupts = ; + always-on; + }; + + s2mpu_gdc0: s2mpu_gdc0@1d0c0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d0c0000 0x10000>; + interrupts = ; + power-domains = <&pd_gdc>; + }; + + s2mpu_gdc1: s2mpu_gdc1@1d0f0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d0f0000 0x10000>; + interrupts = ; + power-domains = <&pd_gdc>; + }; + + s2mpu_gdc2: s2mpu_gdc2@1d120000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1d120000 0x10000>; + interrupts = ; + power-domains = <&pd_gdc>; + }; + + s2mpu_hsi0: s2mpu_hsi0@11070000 { + compatible = "google,s2mpu"; + reg = <0x0 0x11070000 0x10000>; + interrupts = ; + }; + + s2mpu_hsi1: s2mpu_hsi1@11880000 { + compatible = "google,s2mpu"; + reg = <0x0 0x11880000 0x10000>; + interrupts = ; + always-on; + }; + + s2mpu_hsi2: s2mpu_hsi2@145e0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x145e0000 0x10000>; + interrupts = ; + always-on; + }; + + s2mpu_gsa: s2mpu_gsa@17c60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x17c60000 0x10000>; + interrupts = ; + off-at-boot; + }; + + s2mpu_ipp: s2mpu_ipp@1ad20000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1ad20000 0x10000>; + interrupts = ; + power-domains = <&pd_ipp>; + }; + + s2mpu_mcsc0: s2mpu_mcsc0@1b7a0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b7a0000 0x10000>; + interrupts = ; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mcsc1: s2mpu_mcsc1@1b7d0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b7d0000 0x10000>; + interrupts = ; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mcsc2: s2mpu_mcsc2@1b800000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1b800000 0x10000>; + interrupts = ; + power-domains = <&pd_mcsc>; + }; + + s2mpu_mfc0: s2mpu_mfc0@1c890000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c890000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + }; + + s2mpu_mfc1: s2mpu_mfc1@1c8c0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1c8c0000 0x10000>; + interrupts = ; + power-domains = <&pd_mfc>; + }; + + s2mpu_misc: s2mpu_misc@101e0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x101e0000 0x10000>; + interrupts = ; + always-on; + }; + + s2mpu_tnr0: s2mpu_tnr0@1bc90000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bc90000 0x10000>; + interrupts = ; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr1: s2mpu_tnr1@1bcc0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bcc0000 0x10000>; + interrupts = ; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr2: s2mpu_tnr2@1bcf0000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bcf0000 0x10000>; + interrupts = ; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr3: s2mpu_tnr3@1bd20000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bd20000 0x10000>; + interrupts = ; + power-domains = <&pd_tnr>; + }; + + s2mpu_tnr4: s2mpu_tnr4@1bd50000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1bd50000 0x10000>; + interrupts = ; + power-domains = <&pd_tnr>; + }; + + s2mpu_tpu: s2mpu_tpu@1cc60000 { + compatible = "google,s2mpu"; + reg = <0x0 0x1cc60000 0x10000>; + interrupts = ; + power-domains = <&pd_tpu>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-sysmmu.dtsi b/arch/arm64/boot/dts/google/gs201-sysmmu.dtsi new file mode 100644 index 000000000000..0a3ab95b32ea --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-sysmmu.dtsi @@ -0,0 +1,718 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +#include +#include +#include + +/ { + iommu_group_dpu: iommu_group_dpu { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_isp: iommu_group_isp { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_bo: iommu_group_bo { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_mfc: iommu_group_mfc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_aoc: iommu_group_aoc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_g2d: iommu_group_g2d { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_smfc: iommu_group_smfc { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_tpu: iommu_group_tpu { + compatible = "samsung,sysmmu-group"; + }; + + iommu_group_aur: iommu_group_aur { + compatible = "samsung,sysmmu-group"; + }; + + sysmmu_asoc: sysmmu@1A090000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A090000 0x10000>; + interrupts = <0 IRQ_SYSMMU_AOC_S1_NS_AOC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_AOC_S1_S_AOC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A0A0000>; + port-name = "ASOC"; + #iommu-cells = <0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x10, 0x30)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x8, 0x3C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0xC, 0x3C)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x0, 0x3C)>; + }; + + sysmmu_bo: sysmmu@1CA40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1CA40000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_BO_BO IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_BO_BO IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1CA50000>; + port-name = "BO"; + #iommu-cells = <0>; + power-domains = <&pd_bo>; + s2mpus = <&s2mpu_bo>; + sysmmu,no-s2pf; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x1F)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x3, 0x1F)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xE, 0x1F)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x15, 0x1F)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x17, 0x1F)>; + }; + + sysmmu_csis0: sysmmu@1A510000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A510000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_CSIS_S1_S_CSIS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A500000>; + port-name = "CSIS0"; + #iommu-cells = <0>; + power-domains = <&pd_csis>; + s2mpus = <&s2mpu_csis0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x7E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x7E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x7E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC, 0x7E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x7E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0x7E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x7E)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x7E)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C, 0x7E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x7E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x22, 0x7E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0x7E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x32, 0x7E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0x7E)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0x7E)>; + sysmmu,async-fault; + }; + + sysmmu_csis1: sysmmu@1A540000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A540000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_CSIS_S1_S_CSIS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A530000>; + port-name = "CSIS1"; + #iommu-cells = <0>; + power-domains = <&pd_csis>; + s2mpus = <&s2mpu_csis1>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xFE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xFE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0xFE)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC, 0xFE)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0xFE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0xFE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0xFE)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0xFE)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C, 0xFE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0xFE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x22, 0xFE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0xFE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x32, 0xFE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0xFE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0xFE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x80, 0xFE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x82, 0xFE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x84, 0xFE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x86, 0xFE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x88, 0xFE)>, + <21 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8C, 0xFE)>, + <22 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x84, 0xFE)>; + sysmmu,async-fault; + }; + + sysmmu_dns: sysmmu@1B080000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B080000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DNS_S1_NS_DNS IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DNS_S1_S_DNS IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B090000>; + port-name = "DNS"; + #iommu-cells = <0>; + power-domains = <&pd_dns>; + s2mpus = <&s2mpu_dns>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xFE)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xFE)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xFE)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x40, 0xFE)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0xFE)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x42, 0xFE)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x46, 0xFE)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4A, 0xFE)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4E, 0xFE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x52, 0xFE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x42, 0xFE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC0, 0xFE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC4, 0xFE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC8, 0xFE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC2, 0xFE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD0, 0xFE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD4, 0xFE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD8, 0xFE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD2, 0xFE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD6, 0xFE)>; + sysmmu,async-fault; + }; + + sysmmu_dpu0: sysmmu@1C100000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C100000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD0_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD0_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C130000>; + port-name = "DPU L0/L1"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>; + }; + + sysmmu_dpu1: sysmmu@1C110000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C110000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD1_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD1_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C140000>; + port-name = "DPU L2/L3"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu1>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>; + }; + + sysmmu_dpu2: sysmmu@1C120000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C120000 0x10000>; + interrupts = <0 IRQ_SYSMMU_DPUD2_S1_NS_DPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_DPUD2_S1_S_DPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C150000>; + port-name = "DPU L4/L5/W"; + #iommu-cells = <0>; + power-domains = <&pd_dpu>; + s2mpus = <&s2mpu_dpu2>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x7)>, + <2 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x7)>, + <3 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x5, 0x7)>, + <4 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x7)>, + <5 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x7, 0x7)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0x7)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1, 0x7)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x7)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x3, 0x7)>; + }; + + sysmmu_g2d0: sysmmu@1C660000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C660000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C670000>; + port-name = "G2D0"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d0>; + sysmmu,default_tlb = ; + }; + + sysmmu_g2d1: sysmmu@1C690000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C690000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C6A0000>; + port-name = "G2D1"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d1>; + sysmmu,default_tlb = ; + }; + + sysmmu_g2d2: sysmmu@1C710000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C710000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C720000>; + port-name = "JPEG"; + #iommu-cells = <0>; + power-domains = <&pd_g2d>; + s2mpus = <&s2mpu_g2d2>; + sysmmu,default_tlb = ; + }; + + sysmmu_g3aa: sysmmu@1A880000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1A880000 0x10000>; + interrupts = <0 IRQ_SYSMMU_G3AA_S1_NS_G3AA IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_G3AA_S1_S_G3AA IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1A890000>; + port-name = "G3AA"; + #iommu-cells = <0>; + power-domains = <&pd_g3aa>; + s2mpus = <&s2mpu_g3aa>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x38)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x38)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x38)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x38)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x28, 0x38)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x30, 0x38)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x38, 0x38)>; + sysmmu,async-fault; + }; + + sysmmu_gdc0: sysmmu@1D0A0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D0A0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D0B0000>; + port-name = "GDC0"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0xA, 0xE)>, + <4 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xE)>, + <5 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_gdc1: sysmmu@1D0D0000{ + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D0D0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D0E0000>; + port-name = "GDC1"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc1>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL32, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0xA, 0xE)>, + <4 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x0, 0xE)>, + <5 TLB_CFG(BL16, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_gdc2: sysmmu@1D100000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1D100000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_GDC_S1_NS_GDC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_GDC_S1_S_GDC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1D110000>; + port-name = "SCSC"; + #iommu-cells = <0>; + power-domains = <&pd_gdc>; + s2mpus = <&s2mpu_gdc2>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x1E)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x1E)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x1E)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x1E)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x1E)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x1E)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x1E)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x1E)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x1E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x1E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x1E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x1E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x12, 0x1E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x16, 0x1E)>; + sysmmu,async-fault; + }; + +#if 0 + /* + * When GSA is in power collapse SysMMU block below is not accessible. + * Linux kernel driver need to coordinate access to this block with GSA + * if this block needs to be programmed, although, currently, there is + * no usecase that would require this. Disable it for now. + */ + sysmmu_gsa: sysmmu@17C40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x17C40000 0x10000>; + interrupts = <0 SYSMMU_NS__INTERRUPT_GSA IRQ_TYPE_LEVEL_HIGH>, + <0 SYSMMU_S__INTERRUPT_GSA IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x17C50000>; + port-name = "GSA"; + #iommu-cells = <0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x0, 0x6F)>; + }; +#endif + + sysmmu_ipp: sysmmu@1AD00000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1AD00000 0x10000>; + interrupts = <0 IRQ_SYSMMU_IPP_S1_NS_IPP IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_IPP_S1_S_IPP IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1AD10000>; + port-name = "IPP"; + #iommu-cells = <0>; + power-domains = <&pd_ipp>; + s2mpus = <&s2mpu_ipp>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = < 1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3FE)>, + < 2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x3FE)>, + < 3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x80, 0x3FE)>, + < 4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x84, 0x3FE)>, + < 5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x88, 0x3FE)>, + < 6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x90, 0x3FE)>, + < 7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x94, 0x3FE)>, + < 8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x98, 0x3FE)>, + < 9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA0, 0x3FE)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA4, 0x3FE)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xA8, 0x3FE)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x100, 0x3FE)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x190, 0x3FE)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x220, 0x3FE)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x40, 0x3FE)>, + <16 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x50, 0x3FE)>, + <17 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x60, 0x3FE)>, + <18 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xC0, 0x3FE)>, + <19 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xD0, 0x3FE)>, + <20 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0xE0, 0x3FE)>, + <21 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x140, 0x3FE)>, + <22 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x150, 0x3FE)>, + <23 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x160, 0x3FE)>, + <24 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1C0, 0x3FE)>, + <25 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1D0, 0x3FE)>, + <26 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x1E0, 0x3FE)>, + <27 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x240, 0x3FE)>, + <28 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x250, 0x3FE)>, + <29 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x260, 0x3FE)>, + <30 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2E0, 0x3FE)>, + <31 TLB_CFG(BL8, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2C0, 0x3E0)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc0: sysmmu@1B780000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B780000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B790000>; + port-name = "ITSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xE)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0xE)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0xE)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0xE)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc1: sysmmu@1B7B0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B7B0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B7C0000>; + port-name = "MCSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc1>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x3E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x3E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x3E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x3E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x8, 0x3E)>, + <8 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x2, 0x3E)>, + <9 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x6, 0x3E)>, + <10 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3E)>, + <11 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x3E)>, + <12 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x3E)>, + <13 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x20, 0x3E)>, + <14 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x24, 0x3E)>, + <15 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x28, 0x3E)>; + sysmmu,async-fault; + }; + + sysmmu_mcsc2: sysmmu@1B7E0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1B7E0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_MCSC_S1_S_MCSC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1B7F0000>; + port-name = "MCSC"; + #iommu-cells = <0>; + power-domains = <&pd_mcsc>; + s2mpus = <&s2mpu_mcsc2>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3E)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x8, 0x3E)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x2, 0x3E)>, + <4 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x6, 0x3E)>, + <5 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x10, 0x3E)>, + <6 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x14, 0x3E)>, + <7 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x18, 0x3E)>; + sysmmu,async-fault; + }; + + sysmmu_mfc0: sysmmu@1C870000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C870000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,async-fault; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C880000>; + port-name = "MFC0"; + #iommu-cells = <0>; + power-domains = <&pd_mfc>; + s2mpus = <&s2mpu_mfc0>; + sysmmu,default_tlb = ; + }; + + sysmmu_mfc1: sysmmu@1C8A0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1C8A0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,async-fault; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1C8B0000>; + port-name = "MFC1"; + #iommu-cells = <0>; + power-domains = <&pd_mfc>; + s2mpus = <&s2mpu_mfc1>; + sysmmu,default_tlb = ; + }; + + sysmmu_tnr0: sysmmu@1BC70000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BC70000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D0_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D0_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BC80000>; + port-name = "TNR0"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr0>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x4, 0x7C)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x40, 0x7C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x44, 0x7C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr1: sysmmu@1BCA0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BCA0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D1_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D1_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BCB0000>; + port-name = "TNR1"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr1>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0x3C)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0x3C)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr2: sysmmu@1BCD0000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BCD0000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D2_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D2_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BCE0000>; + port-name = "TNR2"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr2>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr3: sysmmu@1BD00000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BD00000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D3_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D3_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BD10000>; + port-name = "TNR3"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr3>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0x3C)>; + sysmmu,async-fault; + }; + + sysmmu_tnr4: sysmmu@1BD30000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1BD30000 0x10000>; + interrupts = <0 IRQ_SYSMMU_D4_TNR_S1_NS_TNR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_D4_TNR_S1_S_TNR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1BD40000>; + port-name = "TNR4"; + #iommu-cells = <0>; + power-domains = <&pd_tnr>; + s2mpus = <&s2mpu_tnr4>; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x80, 0xC0)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x0, 0xC0)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_WRITE SYSMMU_ID_MASK(0x4, 0xC0)>; + sysmmu,async-fault; + }; + + sysmmu_tpu: sysmmu@1CC40000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x1CC40000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_TPU_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_TPU_TPU IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x1CC50000>; + port-name = "TPU"; + #iommu-cells = <0>; + power-domains = <&pd_tpu>; + s2mpus = <&s2mpu_tpu>; + sysmmu,no-s2pf; + sysmmu,default_tlb = ; + sysmmu,tlb_property = <1 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_READ SYSMMU_ID_MASK(0x4, 0xC)>, + <2 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0x8, 0xC)>, + <3 TLB_CFG(BL1, PREFETCH_PREDICTION) DIR_RW SYSMMU_ID_MASK(0xC, 0xC)>; + sysmmu,async-fault; + }; + + /* Often referred to as "sysmmu_aur0" in documentation */ + sysmmu_aur_idma: sysmmu@25A50000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x25A50000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_AUR0_AUR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_AUR0_AUR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x25A60000>; + port-name = "AUR_IDMA"; + #iommu-cells = <0>; + power-domains = <&pd_aur>; + s2mpus = <&s2mpu_aur_idma>; + sysmmu,no-s2pf; + sysmmu,async-fault; + }; + + /* Often referred to as "sysmmu_aur1" in documentation */ + sysmmu_aur_inst_data: sysmmu@25A80000 { + compatible = "samsung,sysmmu-v8"; + reg = <0x0 0x25A80000 0x10000>; + interrupts = <0 IRQ_SYSMMU_S1_NS_AUR1_AUR IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_SYSMMU_S1_S_AUR1_AUR IRQ_TYPE_LEVEL_HIGH>; + qos = <15>; + sysmmu,secure-irq; + sysmmu,secure_base = <0x25A90000>; + port-name = "AUR_INST_DATA"; + #iommu-cells = <0>; + power-domains = <&pd_aur>; + s2mpus = <&s2mpu_aur_inst_data>; + sysmmu,no-s2pf; + sysmmu,async-fault; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-sysmmu_sync.dtsi b/arch/arm64/boot/dts/google/gs201-sysmmu_sync.dtsi new file mode 100644 index 000000000000..e00f58a0202e --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-sysmmu_sync.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2022 Google LLC. + * + */ + +/ { + sysmmu_sync_aur_idma: sysmmu_sync_aur_idma@25b10000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x25b10000 0x10000>; + }; + + sysmmu_sync_aur_inst_data: sysmmu_sync_aur_inst_data@25b20000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x25b20000 0x10000>; + }; + + sysmmu_sync_bo: sysmmu_sync_bo@1caa0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1caa0000 0x10000>; + }; + + sysmmu_sync_cpucl0: sysmmu_sync_cpucl0@20cd0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x20cd0000 0x10000>; + }; + + sysmmu_sync_csis0: sysmmu_sync_csis0@1a560000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a560000 0x10000>; + }; + + sysmmu_sync_csis1: sysmmu_sync_csis1@1a570000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a570000 0x10000>; + }; + + sysmmu_sync_dns: sysmmu_sync_dns@1b060000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b060000 0x10000>; + }; + + sysmmu_sync_dpu0: sysmmu_sync_dpu0@1c040000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c040000 0x10000>; + }; + + sysmmu_sync_dpu1: sysmmu_sync_dpu1@1c050000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c050000 0x10000>; + }; + + sysmmu_sync_dpu2: sysmmu_sync_dpu2@1c060000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c060000 0x10000>; + }; + + sysmmu_sync_eh: sysmmu_sync_eh@17070000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x17070000 0x10000>; + }; + + sysmmu_sync_g2d0: sysmmu_sync_g2d0@1c6e0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c6e0000 0x10000>; + }; + + sysmmu_sync_g2d1: sysmmu_sync_g2d1@1c6f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c6f0000 0x10000>; + }; + + sysmmu_sync_g2d2: sysmmu_sync_g2d2@1c750000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c750000 0x10000>; + }; + + sysmmu_sync_g3aa: sysmmu_sync_g3aa@1a8b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1a8b0000 0x10000>; + }; + + sysmmu_sync_g3d0: sysmmu_sync_g3d0@20090000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x20090000 0x10000>; + }; + + sysmmu_sync_g3d1: sysmmu_sync_g3d1@200a0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x200a0000 0x10000>; + }; + + sysmmu_sync_g3d2: sysmmu_sync_g3d2@200b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x200b0000 0x10000>; + }; + + sysmmu_sync_g3d3: sysmmu_sync_g3d3@201f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x201f0000 0x10000>; + }; + + sysmmu_sync_gdc0: sysmmu_sync_gdc0@1d2d0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2d0000 0x10000>; + }; + + sysmmu_sync_gdc1: sysmmu_sync_gdc1@1d2e0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2e0000 0x10000>; + }; + + sysmmu_sync_gdc2: sysmmu_sync_gdc2@1d2f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1d2f0000 0x10000>; + }; + + sysmmu_sync_gsa: sysmmu_sync_gsa@17c70000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x17c70000 0x10000>; + }; + + sysmmu_sync_hsi0: sysmmu_sync_hsi0@11110000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x11110000 0x10000>; + }; + + sysmmu_sync_hsi1: sysmmu_sync_hsi1@118b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x118b0000 0x10000>; + }; + + sysmmu_sync_hsi2: sysmmu_sync_hsi2@145f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x145f0000 0x10000>; + }; + + sysmmu_sync_ipp: sysmmu_sync_ipp@1acf0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1acf0000 0x10000>; + }; + + sysmmu_sync_mcsc0: sysmmu_sync_mcsc0@1b990000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b990000 0x10000>; + }; + + sysmmu_sync_mcsc1: sysmmu_sync_mcsc1@1b9a0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b9a0000 0x10000>; + }; + + sysmmu_sync_mcsc2: sysmmu_sync_mcsc2@1b9b0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1b9b0000 0x10000>; + }; + + sysmmu_sync_mfc0: sysmmu_sync_mfc0@1c900000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c900000 0x10000>; + }; + + sysmmu_sync_mfc1: sysmmu_sync_mfc1@1c910000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1c910000 0x10000>; + }; + + sysmmu_sync_misc: sysmmu_sync_misc@101f0000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x101f0000 0x10000>; + }; + + sysmmu_sync_tnr0: sysmmu_sync_tnr0@1bf00000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf00000 0x10000>; + }; + + sysmmu_sync_tnr1: sysmmu_sync_tnr1@1bf10000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf10000 0x10000>; + }; + + sysmmu_sync_tnr2: sysmmu_sync_tnr2@1bf20000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf20000 0x10000>; + }; + + sysmmu_sync_tnr3: sysmmu_sync_tnr3@1bf30000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf30000 0x10000>; + }; + + sysmmu_sync_tnr4: sysmmu_sync_tnr4@1bf40000 { + compatible = "google,sysmmu_sync"; + reg = <0x0 0x1bf40000 0x10000>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-tpu.dtsi b/arch/arm64/boot/dts/google/gs201-tpu.dtsi new file mode 100644 index 000000000000..e816f3c961d0 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-tpu.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Edge TPU device tree source + * + * Copyright 2021 Google,LLC + * + */ + +/ { + /* TPU */ + edgetpu: janeiro@1CE00000 { + compatible = "google,darwinn"; + #dma-address-cells = <1>; + #dma-size-cells = <1>; + /* TPU uses regions under 0x18000000 for special purpose */ + dma-window = <0x18000000 0xE7FFF000>; + reg = <0x0 0x1CE00000 0x200000 + 0x0 0x1CCF0000 0x10000>; + reg-names = "tpu", "ssmt"; + interrupts = <0 IRQ_MAILBOX_TPU2AP_NS_TPU_0_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_1_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_2_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_3_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_4_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_5_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_6_TPU IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_MAILBOX_TPU2AP_NS_TPU_7_TPU IRQ_TYPE_LEVEL_HIGH>; + /* TODO(b/195608852): Enable coherency */ + iommus = <&sysmmu_tpu>; + samsung,iommu-group = <&iommu_group_tpu>; + status = "okay"; + memory-region = <&tpu_fw_reserved>, <&tpu_fw_ctx_reserved>; + edgetpu,shareability = <0x1cc20000>; + gsa-device = <&gsa>; + tpu_dvfs_table_size = <7 2>; /**/ + /* + * DVFS values calculated from average power with real-world workloads + */ + tpu_dvfs_table = < + /* when updating tpu_dvfs_table, update tpu_dvfs_table_size as well + * freq power(mW) + *---------------------------------- + * TODO(b/192394098): update these with more accurate numbers for PRO + */ + 1066000 4420 + 967000 4101 + 845000 2578 + 712000 1982 + 627000 1749 + 455000 1277 + 226000 0 + >; + }; + tpu_cooling: tpu-cooling { + #cooling-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201-ufs.dtsi b/arch/arm64/boot/dts/google/gs201-ufs.dtsi new file mode 100644 index 000000000000..fd822822929a --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-ufs.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Samsung's SoC UFS device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include + +/ { + sysreg_hsi2_system_controller: system-controller@14420000 { + compatible = "google,gs201-sysreg-hsi2", "syscon"; + reg = <0x0 0x14420000 0x1000>; + }; + + ufs: ufs@0x14700000 { + /* ----------------------- */ + /* 1. SYSTEM CONFIGURATION */ + /* ----------------------- */ + compatible ="samsung,exynos-ufs"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + reg = + <0x0 0x14700000 0x200>, /* HCI standard */ + <0x0 0x14701100 0x200>, /* Vendor specificed */ + <0x0 0x14780000 0xa000>, /* UNIPRO */ + <0x0 0x14600000 0x100>, /* UFS protector */ + <0x0 0x14704000 0x3000>, /* phy */ + <0x0 0x14708000 0x804>; /* cport */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + clocks = + /* aclk clock */ + <&clock GATE_UFS_EMBD>, + /* unipro clocks */ + <&clock UFS_EMBD>; + + clock-names = + /* aclk clocks */ + "GATE_UFS_EMBD", + /* unipro clocks */ + "UFS_EMBD"; + + /* ----------------------- */ + /* 2. UFS COMMON */ + /* ----------------------- */ + freq-table-hz = <0 0>, <0 0>; + + vcc-supply = <&ufs_fixed_vcc>; + vcc-fixed-regulator; + + /* ----------------------- */ + /* 3. UFS EXYNOS */ + /* ----------------------- */ + /* power mode change */ + ufs,pmd-attr-lane = /bits/ 8 <2>; + ufs,pmd-attr-gear = /bits/ 8 <4>; + + /* evt version for UFS CAL */ + evt-ver = /bits/ 8 <0>; + + /* board type for UFS CAL */ + brd-for-cal = /bits/ 8 <1>; /* (1:SMDK, 16:UNIV) board */ + + /* DMA coherent callback, should be coupled with 'ufs-sys' */ + dma-coherent; + + /* UFS IO coherency */ + samsung,sysreg-phandle = <&sysreg_hsi2_system_controller>; + + fmp-id = <0>; + smu-id = <0>; + + /* GSA (KDN) device */ + gsa-device = <&gsa>; + + /* UTRD bug fixed */ + fixed-prdt-req_list-ocs; + + /* ----------------------- */ + /* 4. ADDITIONAL NODES */ + /* ----------------------- */ + ufs-phy-iso { + offset = <0x3ec8>; + mask = <0x1>; + val = <0x1>; + }; + ufs-iocc { + offset = <0x710>; + mask = <0x3>; + val = <0x3>; + }; + ufs-perf { + active = <0>; + + freq-cluster1 = <1066000>; + freq-cluster0 = <1794000>; + chunk = <128>; + count-b = <40>; + count-l = <48>; + period-in-ms-b = <160>; + period-in-ms-l = <3>; + reset-delay-in-ms = <30>; + }; + }; + + ufs_fixed_vcc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 0>; + regulator-boot-on; + enable-active-high; + }; + +}; diff --git a/arch/arm64/boot/dts/google/gs201-usi.dtsi b/arch/arm64/boot/dts/google/gs201-usi.dtsi new file mode 100644 index 000000000000..e37d7eb86c54 --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201-usi.dtsi @@ -0,0 +1,1134 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +/ { + aliases { + hsi2c0 = &hsi2c_0; + hsi2c1 = &hsi2c_1; + hsi2c2 = &hsi2c_2; + hsi2c3 = &hsi2c_3; + hsi2c4 = &hsi2c_4; + hsi2c5 = &hsi2c_5; + hsi2c6 = &hsi2c_6; + hsi2c7 = &hsi2c_7; + hsi2c8 = &hsi2c_8; + hsi2c9 = &hsi2c_9; + hsi2c10 = &hsi2c_10; + hsi2c11 = &hsi2c_11; + hsi2c12 = &hsi2c_12; + hsi2c13 = &hsi2c_13; + hsi2c14 = &hsi2c_14; + hsi2c15 = &hsi2c_15; + hsi2c16 = &hsi2c_16; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + spi5 = &spi_5; + spi6 = &spi_6; + spi7 = &spi_7; + spi8 = &spi_8; + spi9 = &spi_9; + spi10 = &spi_10; + spi11 = &spi_11; + spi12 = &spi_12; + spi13 = &spi_13; + spi14 = &spi_14; + spi15 = &spi_15; + spi16 = &spi_16; + spi17 = &spi_17; + uart1 = &serial_1; + uart2 = &serial_2; + uart3 = &serial_3; + uart4 = &serial_4; + uart5 = &serial_5; + uart6 = &serial_6; + uart7 = &serial_7; + uart8 = &serial_8; + uart9 = &serial_9; + uart10 = &serial_10; + uart11 = &serial_11; + uart12 = &serial_12; + uart13 = &serial_13; + uart14 = &serial_14; + uart15 = &serial_15; + uart16 = &serial_16; + uart17 = &serial_17; + uart18 = &serial_18; + uart19 = &serial_19; + }; + + sysreg_peric0: syscon@10821000 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x10821000 0x1000>; + }; + + sysreg_peric1: syscon@10C21000 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x10C21000 0x1000>; + }; + + sysreg_apm: syscon@180204E0 { + compatible = "samsung,exynos-sysreg", "syscon"; + reg = <0x0 0x180204e0 0x1000>; + }; + + hsi2c_1: hsi2c@10900000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI1_USI>, <&clock GATE_PERIC0_TOP0_USI1_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp2 0 0x1>; + gpio_sda= <&gpp2 1 0x1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + hsi2c_2: hsi2c@10910000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI2_USI>, <&clock GATE_PERIC0_TOP0_USI2_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp4 0 0x1>; + gpio_sda= <&gpp4 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + hsi2c_3: hsi2c@10920000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI3_USI>, <&clock GATE_PERIC0_TOP0_USI3_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp6 0 0x1>; + gpio_sda= <&gpp6 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + hsi2c_4: hsi2c@10930000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI4_USI>, <&clock GATE_PERIC0_TOP0_USI4_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp8 0 0x1>; + gpio_sda= <&gpp8 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + hsi2c_5: hsi2c@10940000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c5_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI5_USI>, <&clock GATE_PERIC0_TOP0_USI5_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp10 0 0x1>; + gpio_sda= <&gpp10 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + hsi2c_6: hsi2c@10950000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c6_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI6_USI>, <&clock GATE_PERIC0_TOP0_USI6_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp12 0 0x1>; + gpio_sda= <&gpp12 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + hsi2c_7: hsi2c@10960000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c7_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI7_USI>, <&clock GATE_PERIC0_TOP0_USI7_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp14 0 0x1>; + gpio_sda= <&gpp14 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + hsi2c_8: hsi2c@10970000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c8_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI8_USI>, <&clock GATE_PERIC0_TOP0_USI8_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp16 0 0x1>; + gpio_sda= <&gpp16 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + hsi2c_14: hsi2c@10A20000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c14_bus>; + clocks = <&clock VDOUT_CLK_PERIC0_USI14_USI>, <&clock GATE_PERIC0_TOP1_USI14_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp18 0 0x1>; + gpio_sda= <&gpp18 1 0x1>; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + hsi2c_0: hsi2c@10D10000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI0_USI>, <&clock GATE_PERIC1_TOP0_USI0_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp20 0 0x1>; + gpio_sda= <&gpp20 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + hsi2c_9: hsi2c@10D20000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c9_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI9_USI>, <&clock GATE_PERIC1_TOP0_USI9_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp20 4 0x1>; + gpio_sda= <&gpp20 5 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + hsi2c_10: hsi2c@10D30000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c10_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI10_USI>, <&clock GATE_PERIC1_TOP0_USI10_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp21 0 0x1>; + gpio_sda= <&gpp21 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + hsi2c_11: hsi2c@10D40000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c11_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_PERIC1_TOP0_USI11_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp23 0 0x1>; + gpio_sda= <&gpp23 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + hsi2c_12: hsi2c@10D50000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c12_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI12_USI>, <&clock GATE_PERIC1_TOP0_USI12_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp23 4 0x1>; + gpio_sda= <&gpp23 5 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + hsi2c_13: hsi2c@10D60000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c13_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI13_USI>, <&clock GATE_PERIC1_TOP0_USI13_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp25 0 0x1>; + gpio_sda= <&gpp25 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + hsi2c_15: hsi2c@10DA0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,no_lose_arbitration; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c15_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI15_USI>, <&clock GATE_PERIC1_TOP0_USI15_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp24 0 0x1>; + gpio_sda= <&gpp24 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + hsi2c_16: hsi2c@10DB0000 { + compatible = "samsung,exynos5-hsi2c"; + samsung,check-transdone-int; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + default-clk = <200000000>; + samsung,scl-clk-stretching; + samsung,usi-i2c-v2; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c16_bus>; + clocks = <&clock VDOUT_CLK_PERIC1_USI16_USI>, <&clock GATE_PERIC1_TOP0_USI16_USI>; + clock-names = "ipclk_hsi2c", "gate_hsi2c_clk"; + gpio_scl= <&gpp26 0 0x1>; + gpio_sda= <&gpp26 1 0x1>; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + spi_1: spi@10900000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 2 &pdma0 3>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI1_USI>, <&clock GATE_PERIC0_TOP0_USI1_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + spi_2: spi@10910000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 4 &pdma0 5>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI2_USI>, <&clock GATE_PERIC0_TOP0_USI2_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + spi_3: spi@10920000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 6 &pdma0 7>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI3_USI>, <&clock GATE_PERIC0_TOP0_USI3_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + spi_4: spi@10930000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 8 &pdma0 9>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI4_USI>, <&clock GATE_PERIC0_TOP0_USI4_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + spi_5: spi@10940000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 10 &pdma0 11>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI5_USI>, <&clock GATE_PERIC0_TOP0_USI5_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + spi_6: spi@10950000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 12 &pdma0 13>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI6_USI>, <&clock GATE_PERIC0_TOP0_USI6_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi6_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + spi_7: spi@10960000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 14 &pdma0 15>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI7_USI>, <&clock GATE_PERIC0_TOP0_USI7_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi7_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + spi_8: spi@10970000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 16 &pdma0 17>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI8_USI>, <&clock GATE_PERIC0_TOP0_USI8_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi8_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + spi_14: spi@10A20000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 28 &pdma0 29>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC0_USI14_USI>, <&clock GATE_PERIC0_TOP1_USI14_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi14_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + spi_0: spi@10D10000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 0 &pdma0 1>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI0_USI>, <&clock GATE_PERIC1_TOP0_USI0_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + spi_9: spi@10D20000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 18 &pdma0 19>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI9_USI>, <&clock GATE_PERIC1_TOP0_USI9_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi9_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + spi_10: spi@10D30000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 20 &pdma0 21>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI10_USI>, <&clock GATE_PERIC1_TOP0_USI10_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi10_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + spi_11: spi@10D40000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 22 &pdma0 23>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI11_USI>, <&clock GATE_PERIC1_TOP0_USI11_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi11_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + spi_12: spi@10D50000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 24 &pdma0 25>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI12_USI>, <&clock GATE_PERIC1_TOP0_USI12_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi12_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + spi_13: spi@10D60000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma1 0 &pdma1 1>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI13_USI>, <&clock GATE_PERIC1_TOP0_USI13_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi13_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + spi_15: spi@10DA0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma1 2 &pdma1 3>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI15_USI>, <&clock GATE_PERIC1_TOP0_USI15_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi15_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + spi_16: spi@10DB0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; +// dma-mode; +// dmas = <&pdma0 26 &pdma0 27>; + dma-names = "tx", "rx"; + clocks = <&clock VDOUT_CLK_PERIC1_USI16_USI>, <&clock GATE_PERIC1_TOP0_USI16_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi16_bus>; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + /* BLK_PERIC0 USI1_USI */ + serial_1: serial@10900000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI1_USI>, <&clock VDOUT_CLK_PERIC0_USI1_USI>; + clock-names = "gate_uart_clk1", "ipclk_uart1"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10900000 0x00001000>; + status = "disabled"; + }; + serial_2: serial@10910000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI2_USI>, <&clock VDOUT_CLK_PERIC0_USI2_USI>; + clock-names = "gate_uart_clk2", "ipclk_uart2"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10910000 0x00001000>; + status = "disabled"; + }; + serial_3: serial@10920000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI3_USI>, <&clock VDOUT_CLK_PERIC0_USI3_USI>; + clock-names = "gate_uart_clk3", "ipclk_uart3"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10920000 0x00001000>; + status = "disabled"; + }; + serial_4: serial@10930000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI4_USI>, <&clock VDOUT_CLK_PERIC0_USI4_USI>; + clock-names = "gate_uart_clk4", "ipclk_uart4"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10930000 0x00001000>; + status = "disabled"; + }; + serial_5: serial@10940000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI5_USI>, <&clock VDOUT_CLK_PERIC0_USI5_USI>; + clock-names = "gate_uart_clk5", "ipclk_uart5"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10940000 0x00001000>; + status = "disabled"; + }; + serial_6: serial@10950000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI6_USI>, <&clock VDOUT_CLK_PERIC0_USI6_USI>; + clock-names = "gate_uart_clk6", "ipclk_uart6"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10950000 0x00001000>; + status = "disabled"; + }; + serial_7: serial@10960000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI7_USI>, <&clock VDOUT_CLK_PERIC0_USI7_USI>; + clock-names = "gate_uart_clk7", "ipclk_uart7"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10960000 0x00001000>; + status = "disabled"; + }; + serial_8: serial@10970000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP0_USI8_USI>, <&clock VDOUT_CLK_PERIC0_USI8_USI>; + clock-names = "gate_uart_clk8", "ipclk_uart8"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10970000 0x00001000>; + status = "disabled"; + }; + serial_14: serial@10A20000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart14_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP1_USI14_USI>, <&clock VDOUT_CLK_PERIC0_USI14_USI>; + clock-names = "gate_uart_clk14", "ipclk_uart14"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric0>; + samsung,usi-offset = <0x00000028>; + reg = <0x00000000 0x10a20000 0x00001000>; + status = "disabled"; + }; + /* BLK_PERIC1 USI0_USI */ + serial_usi0: serial@10D10000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC0_TOP1_USI0_UART>, <&clock VDOUT_CLK_PERIC0_USI0_UART>; + clock-names = "gate_uart_clk15", "ipclk_uart15"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x10d10000 0x00001000>; + status = "disabled"; + }; + serial_9: serial@10D20000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI9_USI>, <&clock VDOUT_CLK_PERIC1_USI9_USI>; + clock-names = "gate_uart_clk9", "ipclk_uart9"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x10d20000 0x00001000>; + status = "disabled"; + }; + serial_10: serial@10D30000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart10_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI10_USI>, <&clock VDOUT_CLK_PERIC1_USI10_USI>; + clock-names = "gate_uart_clk10", "ipclk_uart10"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x10d30000 0x00001000>; + status = "disabled"; + }; + serial_11: serial@10D40000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart11_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI11_USI>, <&clock VDOUT_CLK_PERIC1_USI11_USI>; + clock-names = "gate_uart_clk11", "ipclk_uart11"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000000c>; + reg = <0x00000000 0x10d40000 0x00001000>; + status = "disabled"; + }; + serial_12: serial@10D50000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart12_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI12_USI>, <&clock VDOUT_CLK_PERIC1_USI12_USI>; + clock-names = "gate_uart_clk12", "ipclk_uart12"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000010>; + reg = <0x00000000 0x10d50000 0x00001000>; + status = "disabled"; + }; + serial_13: serial@10D60000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart13_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI13_USI>, <&clock VDOUT_CLK_PERIC1_USI13_USI>; + clock-names = "gate_uart_clk13", "ipclk_uart13"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000014>; + reg = <0x00000000 0x10d60000 0x00001000>; + status = "disabled"; + }; + serial_15: serial@10DA0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart15_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI15_USI>, <&clock VDOUT_CLK_PERIC1_USI15_USI>; + clock-names = "gate_uart_clk15", "ipclk_uart15"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x00000018>; + reg = <0x00000000 0x10da0000 0x00001000>; + status = "disabled"; + }; + serial_16: serial@10DB0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart16_bus_single>; /* or _bus_dual */ + clocks = <&clock GATE_PERIC1_TOP0_USI16_USI>, <&clock VDOUT_CLK_PERIC1_USI16_USI>; + clock-names = "gate_uart_clk16", "ipclk_uart16"; + interrupts = ; + samsung,usi-phandle = <&sysreg_peric1>; + samsung,usi-offset = <0x0000001c>; + reg = <0x00000000 0x10db0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_UART */ + serial_17: serial@181A0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <256>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart17_bus>; /* or _bus_dual */ + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_UART>; + clock-names = "gate_uart_clk17", "ipclk_uart17"; + interrupts = ; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000000>; + reg = <0x00000000 0x181a0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI1_UART */ + serial_18: serial@181B0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <256>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + samsung,rts-gpio-control; + samsung,uart-logging; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default", "rts", "tx_dat"; + pinctrl-0 = <&uart18_bus>; /* or _bus_dual */ + pinctrl-1 = <&uart18_bus_rts &uart18_bus_tx_con>; + pinctrl-2 = <&uart18_bus_tx_dat>; + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI1_UART>; + clock-names = "gate_uart_clk18", "ipclk_uart18"; + interrupts = ; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000004>; + reg = <0x00000000 0x181b0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_USI */ + serial_19: serial@181C0000 { + compatible = "samsung,exynos-uart"; + samsung,fifo-size = <64>; + reg-io-width = <4>; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart19_bus>; /* or _bus_dual */ + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_USI>; + clock-names = "gate_uart_clk19", "ipclk_uart19"; + interrupts = ; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x181c0000 0x00001000>; + status = "disabled"; + }; + /* BLK_ALIVE APM_USI0_USI */ + spi_17: spi@181C0000 { + compatible = "samsung,exynos-spi"; + samsung,spi-fifosize = <64>; + swap-mode; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + dma-names = "tx", "rx"; + clocks = <&clock MUX_APM_FUNC>, <&clock DOUT_CLK_APM_USI0_USI>; + clock-names = "ipclk_spi", "gate_spi_clk"; + interrupts = ; + samsung,usi-phandle = <&sysreg_apm>; + samsung,usi-offset = <0x00000008>; + reg = <0x00000000 0x181c0000 0x00001000>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/google/gs201.dtsi b/arch/arm64/boot/dts/google/gs201.dtsi new file mode 100644 index 000000000000..a2d492d7d7eb --- /dev/null +++ b/arch/arm64/boot/dts/google/gs201.dtsi @@ -0,0 +1,1495 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "gs201-rmem.dtsi" +#include "gs101-trusty.dtsi" +#include "gs201-bts.dtsi" +#include "gs101-cp-tm.dtsi" +#include "gs201-cpu.dtsi" +#include "gs201-dit.dtsi" +#include "gs201-drm-dpu.dtsi" +#include "gs201-gpu.dtsi" +#include "gs201-aoc.dtsi" +#include "gs101-audio.dtsi" +#include "gs201-gsa.dtsi" +#include "gs201-pinctrl.dtsi" +#include "gs201-pm-domains.dtsi" +#include "gs201-sysmmu.dtsi" +#include "gs201-usi.dtsi" +#include "gs201-s2mpu.dtsi" +#include "gs201-ufs.dtsi" +#include "gs201-mmc.dtsi" +#include "gs201-tpu.dtsi" +#include "gs201-gxp.dtsi" +#include "gs101-dma-heap.dtsi" +#include "gs201-isp.dtsi" +#include "gs201-debug.dtsi" +#include "gs201-pcie.dtsi" +#include "gs201-bigo.dtsi" +#include "gs201-mfc.dtsi" +#include "gs201-pwm.dtsi" + +/ { + compatible = "google,gs201"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + pinctrl6 = &pinctrl_6; + pinctrl7 = &pinctrl_7; + pinctrl8 = &pinctrl_8; + uart0 = &serial_0; + + }; + + ect { + parameter_address = <0x90000000>; + parameter_size = <0x53000>; + }; + + exynos-ect { + compatible = "samsung,exynos-ect"; + memory-region = <&ect_binary>; + }; + + chipid@10000000 { + compatible = "google,gs201-chipid"; + reg = <0x0 0x10000000 0xD000>; + }; + + chosen: chosen { + bootargs = "earlycon=exynos4210,mmio32,0x10A00000 console=ttySAC0,115200n8 clocksource=arch_sys_counter root=/dev/ram0 rw ramdisk_size=65536 androidboot.hardware.platform=gs201 androidboot.debug_level=0x4948 firmware_class.path=/vendor/firmware reserve-fimc=0xffffff90f9fe0000 clk_ignore_unused loop.max_part=7 coherent_pool=4M no_console_suspend softlockup_panic=1 maxcpus=8 sysrq_always_enabled kasan_multi_shot ehld.noehld=1"; + }; + + odm: odm { + compatible = "simple-bus"; + ranges; + + /* reserved for overlay by ODM */ + }; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x10000>, /* GICD */ + <0x0 0x10440000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <24576000>; + }; + + ext_24_5m: ext_24_5m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-output-names = "ext-24_5m"; + }; + + ext_100m: ext_100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ext-100m"; + }; + + ext_200m: ext_200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "ext-200m"; + }; + + ext_26m: ext_26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_1m: ext_1m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "ext-1m"; + }; + + mct: mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10050000 0x800>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&mct_map>; + interrupts = <0>, <1>, <2>, <3>, + <4>, <5>, <6>, <7>, + <8>, <9>, <10>, <11>; + clocks = <&clock OSCCLK>, <&clock GATE_MCT>; + clock-names = "fin_pll", "mct"; + + mct_map: mct-map { + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0 &gic 0 IRQ_MCT_G0_MISC IRQ_TYPE_LEVEL_HIGH>, + <1 &gic 0 IRQ_MCT_G1_MISC IRQ_TYPE_LEVEL_HIGH>, + <2 &gic 0 IRQ_MCT_G2_MISC IRQ_TYPE_LEVEL_HIGH>, + <3 &gic 0 IRQ_MCT_G3_MISC IRQ_TYPE_LEVEL_HIGH>, + <4 &gic 0 IRQ_MCT_L0_MISC IRQ_TYPE_LEVEL_HIGH>, + <5 &gic 0 IRQ_MCT_L1_MISC IRQ_TYPE_LEVEL_HIGH>, + <6 &gic 0 IRQ_MCT_L2_MISC IRQ_TYPE_LEVEL_HIGH>, + <7 &gic 0 IRQ_MCT_L3_MISC IRQ_TYPE_LEVEL_HIGH>, + <8 &gic 0 IRQ_MCT_L4_MISC IRQ_TYPE_LEVEL_HIGH>, + <9 &gic 0 IRQ_MCT_L5_MISC IRQ_TYPE_LEVEL_HIGH>, + <10 &gic 0 IRQ_MCT_L6_MISC IRQ_TYPE_LEVEL_HIGH>, + <11 &gic 0 IRQ_MCT_L7_MISC IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + eh: eh@17100000 { + compatible = "google,eh"; + reg = <0x0 0x17100000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + clocks = <&clock DOUT_CLK_EH_NOCP>; + clock-names = "eh-clock"; + power-domains = <&pd_eh>; + google,eh,ignore-gctrl-reset; + s2mpu = <&s2mpu_eh>; + }; + + serial_0: uart@10A00000 { + compatible = "samsung,exynos-uart"; + samsung,separate-uart-clk; + samsung,usi-serial-v2; + samsung,dbg-uart-ch; + samsung,dbg-uart-baud = <115200>; + samsung,dbg-word-len = <8>; + reg-io-width = <4>; + reg = <0x0 0x10A00000 0x100>; + samsung,fifo-size = <256>; + interrupts = ; + clocks = <&clock GATE_PERIC0_TOP1_USI0_UART>, <&clock VDOUT_CLK_PERIC0_USI0_UART>; + clock-names = "gate_uart_clk0", "ipclk_uart0"; + status = "disabled"; + }; + + /* GPIO_ALIVE */ + pinctrl_0: pinctrl@180D0000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x180d0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* DMA */ + amba: amba { + #address-cells = <2>; + #size-cells = <1>; + compatible = "arm,amba-bus"; + interrupt-parent = <&gic>; + ranges; + pdma0: pdma0@10110000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10110000 0x1000>; + interrupts = ; + clocks = <&ext_100m>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + #dma-multi-irq = <1>; + dma-arwrapper = <0x10114400>, + <0x10114420>, + <0x10114440>, + <0x10114460>, + <0x10114480>, + <0x101144A0>, + <0x101144C0>, + <0x101144E0>; + dma-awwrapper = <0x10114404>, + <0x10114424>, + <0x10114444>, + <0x10114464>, + <0x10114484>, + <0x101144A4>, + <0x101144C4>, + <0x101144E4>; + dma-instwrapper = <0x10114500>; + dma-mask-bit = <36>; + coherent-mask-bit = <36>; + }; + }; + + /* GPIO_FAR_ALIVE */ + pinctrl_1: pinctrl@180E0000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x180e0000 0x00001000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* GPIO_GSACORE */ + pinctrl_2: pinctrl@17A80000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x17a80000 0x00001000>; + }; + /* GPIO_GSACTRL */ + pinctrl_3: pinctrl@17940000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x17940000 0x00001000>; + }; + /* GPIO_PERIC0 */ + pinctrl_4: pinctrl@10840000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x10840000 0x00001000>; + interrupts = ; + }; + /* GPIO_PERIC1 */ + pinctrl_5: pinctrl@10C40000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x10C40000 0x00001000>; + interrupts = ; + }; + /* GPIO_HSI1 */ + pinctrl_6: pinctrl@11840000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x11840000 0x00001000>; + interrupts = ; + }; + /* GPIO_HSI2 */ + pinctrl_7: pinctrl@14440000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x14440000 0x00001000>; + interrupts = ; + }; + /* GPIO_HSI2UFS */ + pinctrl_8: pinctrl@14460000 { + compatible = "google,gs201-pinctrl"; + reg = <0x00000000 0x14460000 0x00001000>; + interrupts = ; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + exynos-pm { + compatible = "samsung,exynos-pm"; + reg = <0x0 0x180D0000 0x1000>, + <0x0 0x180E0000 0x1000>, + <0x0 0x10540204 0x100>, + <0x0 0x18300000 0x100>; /* GS_MAILBOX_AP_AOCA3_HOST */ + reg-names = "gpio_alive_base", + "gpio_far_alive_base", + "gicd_ispendrn_base", + "mailbox_ap_aoc_host"; + num-eint = <64>; /* EINT_0 ~ 44 */ + num-eint-far = <32>; /* EINT_45 ~ 66 */ + gpa-use = <8>, <7>, <5>, <4>, <4>, <7>, <8>, <2>, <8>, <4>, <8>, <2>; + num-gic = <30>; + suspend_mode_idx = <8>; + + pcieon_suspend_available = <1>; + pcieon_suspend_mode_idx = <13>; + + /* WAKEUP_STAT, WAKEUP2_STAT */ + wakeup_stat_offset = <0x3950>, <0x3970>; + wakeup_int_en_offset = <0x3944>, <0x3964>; + wakeup_int_en = <0x1001f0bf>, <0x01f0>; + + eint_wakeup_mask_offset = <0x3a80>, <0x3a84>, <0x3a88>; + wakeup-stat-eint = <0x30>; + wakeup-stat-rtc = <0>; + + wake_lock = <0>; /* 1: held wake_lock */ + + wakeup_stats { + wakeup_stat { + ws-name = + "RTC_ALARM", /* [ 0] */ + "RTC_TICK", /* [ 1] */ + "TRTC_ALARM", /* [ 2] */ + "TRTC_TICK", /* [ 3] */ + "EINT", /* [ 4] */ + "EINT_FAR", /* [ 5] */ + "MAILBOX_APM2AP", /* [ 6] */ + "MAILBOX_AOC2AP", /* [ 7] */ + "L1SUB_PCIE_GEN4A_0", /* [ 8] */ + "L1SUB_PCIE_GEN4B_0", /* [ 9] */ + "L1SUB_PCIE_GEN4A_1", /* [10] */ + "L1SUB_PCIE_GEN4B_1", /* [11] */ + "EXT_PCIE_GEN4A_0", /* [12] */ + "EXT_PCIE_GEN4B_0", /* [13] */ + "EXT_PCIE_GEN4A_1", /* [14] */ + "EXT_PCIE_GEN4B_1", /* [15] */ + "USB_REWA", /* [16] */ + "USBDP", /* [17] */ + "MMC_CARD", /* [18] */ + "TIMER", /* [19] */ + "CLUSTER0_CPU0_nIRQOUT",/* [20] */ + "CLUSTER0_CPU1_nIRQOUT",/* [21] */ + "CLUSTER0_CPU2_nIRQOUT",/* [22] */ + "CLUSTER0_CPU3_nIRQOUT",/* [23] */ + "CLUSTER1_CPU0_nIRQOUT",/* [24] */ + "CLUSTER1_CPU1_nIRQOUT",/* [25] */ + "CLUSTER2_CPU0_nIRQOUT",/* [26] */ + "CLUSTER2_CPU1_nIRQOUT",/* [27] */ + "INTREQ_PCIE_GEN4A_0", /* [28] */ + "INTREQ_PCIE_GEN4B_0", /* [29] */ + "INTREQ_PCIE_GEN4A_1", /* [30] */ + "INTREQ_PCIE_GEN4B_1"; /* [31] */ + }; + + wakeup_stat2 { + ws-name = + "RESERVED", /* [ 0] */ + "RESERVED", /* [ 1] */ + "USB20_PHY_FS_VMINUS_WAKEUP",/* [ 2] */ + "USB20_PHY_FS_VPLUS_WAKEUP", /* [ 3] */ + "MAILBOX_APM2AP", /* [ 4] */ + "MAILBOX_AOCA322AP", /* [ 5] */ + "MAILBOX_AOCF12AP", /* [ 6] */ + "MAILBOX_AOCP62AP", /* [ 7] */ + "MAILBOX_DBGCORE2AP", /* [ 8] */ + "MAILBOX_AUR02AP", /* [ 9] */ + "MAILBOX_AUR12AP", /* [10] */ + "MAILBOX_AUR22AP", /* [11] */ + "MAILBOX_AUR32AP", /* [12] */ + "VGPIO2PMU_EINT", /* [13] */ + "RESERVED", /* [14] */ + "RESERVED", /* [15] */ + "RESERVED", /* [16] */ + "RESERVED", /* [17] */ + "RESERVED", /* [18] */ + "RESERVED", /* [19] */ + "RESERVED", /* [20] */ + "RESERVED", /* [21] */ + "RESERVED", /* [22] */ + "RESERVED", /* [23] */ + "RESERVED", /* [24] */ + "RESERVED", /* [25] */ + "RESERVED", /* [26] */ + "RESERVED", /* [27] */ + "RESERVED", /* [28] */ + "RESERVED", /* [29] */ + "RESERVED", /* [30] */ + "RESERVED"; /* [31] */ + }; + }; + }; + + exynos-pmu { + compatible = "samsung,exynos-pmu"; + samsung,syscon-phandle = <&pmu_system_controller>; + reg = <0x0 0x18060000 0x10000>; + reg-names = "pmu_alive"; + }; + + pmu_system_controller: system-controller@18060000 { + compatible = "samsung,gs101-pmu", "syscon"; + reg = <0x0 0x18060000 0x10000>; + }; + + dsu-pmu-0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + exynos-reboot { + compatible = "samsung,exynos-reboot"; + syscon = <&pmu_system_controller>; + reboot-cmd-offset = <0x0810>; + force-warm-reboot-on-thermal-shutdown; + }; + + gpio_keys: gpio_keys { + compatible = "gpio-keys"; + }; + + cal_if { + compatible = "samsung,exynos_cal_if"; + reg = <0x0 0x1e080000 0x8000>; + acpm-ipc-channel = <0>; + }; + + clock: clock-controller@0x1e080000 { + compatible = "samsung,gs201-clock"; + reg = <0x0 0x1e080000 0x8000>; + #clock-cells = <1>; + acpm-ipc-channel = <0>; + }; + + acpm_flexpmu_dbg { + compatible = "google,acpm-flexpmu-dbg"; + }; + + acpm_mbox_test: mbox { + compatible = "google,acpm-mbox-test"; + mfd-regulator-list-main = + <0x118 0x11A 0x11C 0x11E + 0x120 0x124 0x12A 0x136 + 0x137 0x138 0x13A 0x13C>; + mfd-regulator-list-sub = + <0x110 0x112 0x116 0x118 + 0x11E 0x120 0x12C>; + }; + + acpm { + compatible = "google,gs-acpm"; + #address-cells = <2>; + #size-cells = <1>; + acpm-ipc-channel = <4>; + reg = <0x0 0x18040000 0x1000>; /* TIMER_APM */ + reg-names = "timer_apm"; + peritimer-cnt = <0xFFFF>; + }; + + acpm_ipc { + compatible = "google,gs-acpm-ipc"; + #address-cells = <2>; + #size-cells = <1>; + interrupts = ; + reg = <0x0 0x18210000 0x01000>, /* AP2APM MAILBOX */ + <0x0 0x18500000 0x48000>, /* APM SRAM */ + <0x0 0x1802048C 0x00014>; /* ALIVE_FRC_CTRL */ + initdata-base = <0xA000>; + debug-log-level = <0>; + logging-period = <500>; + dump-base = <0x18505000>; + dump-size = <0x43000>; /* 268KB(= 288 - 20) */ + acpm-ipc-channel = <12>; + fvmap_addr = <0x31000>; + panic-action = ; + }; + + acpm_stats { + compatible = "google,power-stats"; + timer-frequency-hz = <49152000>; + }; + + slc-dummy { + compatible = "google,pt"; + dummy { + id_size_priority = < 0x5 0x1001 0x1000 0x8002>; + }; + }; + + slc-acpm { + compatible = "google,slc-acpm"; + acpm-ipc-channel = <10>; + pt_id = "AoC_Sleep"; /* for testing */ + async { + acpm-ipc-channel = <11>; + }; + BYPASS { + /* vptid 0, size 0, priority 15 (lowest), pbha 0 */ + id_size_priority = < 0x0 0x1 0xf 0x0 >; + }; + LEFTOVER { + /* vptid 1, all size, priority 15 (lowest), pbha 1 */ + id_size_priority = < 0x1 0xffffffff 0xf 0x1 >; + }; + AoC_Sleep { + /* vptid 2, size 0, priority 0 (highest), pbha 2 */ + id_size_priority = < 0x2 0xffffffff 0x0 0x2 >; + }; + GPU { + /* vptid 2, all size, priority 0 (highest), pbha 5 */ + id_size_priority = < 0x2 0xffffffff 0x0 0x5 >; + }; + CAMERA2WAY { + /* vptid 3, size 512KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00002001 0x0 0x0 >; + }; + CAMERA4WAY0 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA4WAY1 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA4WAY2 { + /* vptid 3, size 1024KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00010001 0x0 0x0 >; + }; + CAMERA6WAY0 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA6WAY1 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA6WAY2 { + /* vptid 3, size 1536KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x3 0x00020001 0x0 0x0 >; + }; + CAMERA8WAY0 { + /* vptid 4, size 2048KB, priority 0 (highest), pbha 0 */ + id_size_priority = < 0x4 0x00040001 0x0 0x0 >; + }; + bigocean { + /* vptid 3, 1536-256KB size, priority 0, pbha 0 */ + id_size_priority = < 0x3 0x0003f001 0x0 0x0 >; + }; + MFC { + /* vptid 9, 2*256KB, priority 0 (highest), pbha ? */ + id_size_priority = < 0x9 0x00002001 0x0 0x0>; + }; + }; + + acpm_mfd_bus0: acpm_mfd_bus@18100000 { + compatible = "google,i2c-acpm"; + status = "okay"; + }; + + acpm_mfd_bus1: acpm_mfd_bus@18110000 { + compatible = "google,i2c-acpm"; + status = "okay"; + }; + + smfc: smfc@1C700000 { + compatible = "samsung,exynos8890-jpeg"; + reg = <0x0 0x1C700000 0x1000>; + interrupts = <0 IRQ_JPEG_G2D IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clock GATE_JPEG>; + clock-names = "gate"; + power-domains = <&pd_g2d>; + samsung,iommu-group = <&iommu_group_smfc>; + iommus = <&sysmmu_g2d2>; + dma-coherent; + }; + + udc: usb@11210000 { + compatible = "samsung,exynos9-dwusb"; + clocks = <&clock GATE_USB31DRD_SLV_LINK>, + <&clock MUX_HSI0_USB20_REF>, + <&clock VDOUT_CLK_TOP_HSI0_NOC>; + //clock-names = "aclk", "sclk"; + clock-names = "aclk", "sclk", "bus"; + reg = <0x0 0x11210000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + power-domains = <&pd_hsi0>; + status = "okay"; + + interrupts = ; + tx-fifo-resize = <0>; + adj-sof-accuracy = <0>; + is_not_vbus_pad = <1>; + enable_sprs_transfer = <1>; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* check susphy support */ + //suspend_clk_freq = <19200000>; + /* INT min lock support */ + usb-pm-qos-int = <200000>; + usb_host_device_timeout = <0x7ff>; /* Max value */ + + usbdrd_dwc3: dwc3 { + compatible = "synopsys,dwc3"; + clocks = <&clock GATE_USB31DRD_SLV_LINK>, + <&clock MUX_HSI0_USB20_REF>; + clock-names = "aclk", "sclk"; + reg = <0x0 0x11210000 0x10000>; + interrupts = ; + memory-region = <&xhci_dma>; + dr_mode = "peripheral"; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + /* support usb offloading, 0: disabled, 1: audio */ + offload = <1>; + direct-usb-access; + }; + }; + + usbdrd_phy0: phy@11200000 { + compatible = "samsung,exynos-usbdrd-phy"; + reg = <0x0 0x11200000 0x200>, + <0x0 0x110F0000 0x2800>, + <0x0 0x11100000 0x800>, + <0x0 0x11210000 0x10000>; + power-domains = <&pd_hsi0>; + interrupts = , + ; + clocks = <&clock MUX_HSI0_USB20_REF>, + <&clock GATE_USB31DRD_SLV_LINK>; + clock-names = "phy_ref", "aclk"; + samsung,pmu-syscon = <&pmu_system_controller>; + pmu_mask = <0x0>; + /*pmu_mask_pll = <0x1>;*/ + pmu_offset = <0x3EB0>; + pmu_offset_dp = <0x3EB4>; + /* USBDP combo phy version - 0x200 */ + phy_version = <0x301>; + /* if it doesn't need phy user mux, */ + /* you should write "none" */ + /* but refclk shouldn't be omitted */ + phyclk_mux = "none"; + phy_refclk = "phy_ref"; + phy_ref_clock = <19200000>; + s2mpu = <&s2mpu_hsi0>; + + /* + * if Main phy has the other phy, + * it must be set to 1 just for usbphy_info + */ + has_other_phy = <0>; + /* + * if combo phy is used, it must be set to 1. + * usbphy_sub_info is enabled + */ + has_combo_phy = <1>; + sub_phy_version = <0x404>; + + /* ip type */ + /* USB3DRD = 0 */ + /* USB3HOST = 1 */ + /* USB2DRD = 2 */ + /* USB2HOST = 3 */ + ip_type = <0x0>; + + /* for PHY CAL */ + /* choice only one item */ + phy_refsel_clockcore = <1>; + phy_refsel_ext_osc = <0>; + phy_refsel_xtal = <0>; + phy_refsel_diff_pad = <0>; + phy_refsel_diff_internal = <0>; + phy_refsel_diff_single = <0>; + + /* true : 1 , false : 0 */ + use_io_for_ovc = <0>; + common_block_disable = <1>; + is_not_vbus_pad = <1>; + used_phy_port = <0>; + + status = "okay"; + + #phy-cells = <1>; + ranges; + }; + + exynos_dm: exynos-dm@17000000 { + compatible = "samsung,exynos-dvfs-manager"; + reg = <0x0 0x17000000 0x0>; + acpm-ipc-channel = <1>; + dm_domains { + cpufreq_cl0 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl0"; + }; + cpufreq_cl1 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl1"; + }; + cpufreq_cl2 { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cpu_cl2"; + }; + devfreq_mif { + dm-index = ; + available = "true"; + policy_use = "true"; + cal_id = ; + dm_type_name = "dm_mif"; + }; + devfreq_int { + dm-index = ; + available = "true"; + policy_use = "true"; + cal_id = ; + dm_type_name = "dm_int"; + }; + devfreq_intcam { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_intcam"; + }; + devfreq_cam { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_cam"; + }; + devfreq_tpu { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_tpu"; + }; + devfreq_tnr { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_tnr"; + }; + devfreq_disp { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_disp"; + }; + devfreq_mfc { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_mfc"; + }; + devfreq_bo { + dm-index = ; + available = "true"; + cal_id = ; + dm_type_name = "dm_BO"; + }; + }; + }; + + exynos_devfreq { + compatible = "samsung,exynos-devfreq-root"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + devfreq_0: devfreq_mif@17000010 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000010 0x0>; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + clocks = <&clock UMUX_MIF_DDRPHY2X>; + clock-names = "DEVFREQ"; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <421000 421000 421000 421000 3172000 1014000>; + /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */ + + /* governor data */ + governor = ; + + /* boot_info */ + boot_info = <60 2730000>; + + dfs_id = ; + acpm-ipc-channel = <1>; + use_acpm = "true"; + + /* ALT-DVFS */ + use_get_dev = "true"; + um_count = <2 4 4>; + um_list = < + /* PPC_CPUCL0_D0_EVENT PPC_CPUCL0_D1_EVENT */ + 0x1E110000 0x1E120000 + /* PPC_CCI_M0_EVENT PPC_CCI_M1_EVENT */ + 0x1E130000 0x1E140000 + /* PPC_CCI_M2_EVENT PPC_CCI_M3_EVENT */ + 0x1E150000 0x1E160000 + /* PPC_BUS2_M0_EVENT PPC_BUS2_M1_EVENT */ + 0x1E170000 0x1E180000 + /* PPC_BUS2_M2_EVENT PPC_BUS2_M3_EVENT */ + 0x1E190000 0x1E1A0000 + >; + + use_alt_dvfs; + polling_ms = <0>; + target_load = <60 10 40>; + min_sample_time = <20>; + hold_sample_time = <60>; + hispeed_load = <100>; + hispeed_freq = <1352000>; + + /* MIF to INT mapping table used in ALT DVFS */ + mif_int_map = < + /* + * mif_clk int_clk + *----------------- + */ + 3172000 533000 + 2730000 465000 + 2028000 332000 + 1539000 267000 + 1352000 200000 + 1014000 155000 + 546000 100000 + >; + }; + + devfreq_1: devfreq_int@17000020 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000020 0x0>; + devfreq_type = ; + devfreq_domain_name = "INT"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <100000 100000 100000 100000 533000 533000>; + /* */ + + /* boot_info */ + boot_info = <60 465000>; + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + acpm-ipc-channel = <1>; + use_acpm = "true"; + }; + + devfreq_2: devfreq_intcam@17000030 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000030 0x0>; + devfreq_type = ; + devfreq_domain_name = "INTCAM"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_3: devfreq_disp@17000040 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000040 0x0>; + devfreq_type = ; + devfreq_domain_name = "DISP"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <134000 134000 134000 134000 664000 664000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_4: devfreq_cam@17000050 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000050 0x0>; + devfreq_type = ; + devfreq_domain_name = "CAM"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + + dfs_id = ; + }; + + devfreq_5: devfreq_tnr@17000060 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000060 0x0>; + devfreq_type = ; + devfreq_domain_name = "TNR"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <67000 67000 67000 67000 664000 664000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_6: devfreq_mfc@17000070 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000070 0x0>; + devfreq_type = ; + devfreq_domain_name = "MFC"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <100000 100000 100000 100000 711000 711000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + + devfreq_7: devfreq_bo@17000080 { + compatible = "samsung,exynos-devfreq"; + reg = <0x0 0x17000080 0x0>; + devfreq_type = ; + devfreq_domain_name = "BO"; + pm_qos_class = ; + pm_qos_class_max = ; + ess_flag = ; + dm-index = ; + + /* Delay time */ + use_delay_time = "false"; + + freq_info = <95000 95000 95000 95000 620000 620000>; + /* */ + + /* governor data */ + governor = ; + + bts_update = "false"; + dfs_id = ; + }; + }; + + gs_memlat_devfreq { + compatible = "memlat-devfreq-root"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + + mif_cpu0_mem_lat: devfreq_mif_cpu0_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu1_mem_lat: devfreq_mif_cpu1_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu2_mem_lat: devfreq_mif_cpu2_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu3_mem_lat: devfreq_mif_cpu3_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + + mif_cpu4_mem_lat: devfreq_mif_cpu4_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu5_mem_lat: devfreq_mif_cpu5_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu6_mem_lat: devfreq_mif_cpu6_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + + mif_cpu7_mem_lat: devfreq_mif_cpu7_memlat@17000010 { + compatible = "memlat-devfreq"; + devfreq_type = ; + devfreq_domain_name = "MIF"; + pm_qos_class = ; + pm_qos_class_max = ; + dm-index = ; + clock-names = "DEVFREQ"; + polling_ms = <10>; + + /* governor data */ + governor = ; + dfs_id = ; + + }; + }; + + cpu0_memlat_cpugrp: cpu0-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu0>; + + cpu0_cpu_mif_latmon: cpu0-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu0>; + target-dev = <&mif_cpu0_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu1_memlat_cpugrp: cpu1-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu1>; + + cpu1_cpu_mif_latmon: cpu1-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu1>; + target-dev = <&mif_cpu1_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu2_memlat_cpugrp: cpu2-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu2>; + + cpu2_cpu_mif_latmon: cpu2-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu2>; + target-dev = <&mif_cpu2_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + cpu3_memlat_cpugrp: cpu3-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu3>; + + cpu3_cpu_mif_latmon: cpu3-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu3>; + target-dev = <&mif_cpu3_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 300000 421000 >, + < 574000 546000 >, + < 738000 676000 >, + < 930000 845000 >, + < 1098000 1014000 >, + < 1197000 1352000 >, + < 1328000 1539000 >, + < 1598000 1716000 >, + < 1803000 2028000 >, + < 2024000 2535000 >; + }; + }; + + + cpu4_memlat_cpugrp: cpu4-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu4>; + + cpu4_cpu_mif_latmon: cpu4-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu4>; + target-dev = <&mif_cpu4_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 400000 421000 >, + < 553000 546000 >, + < 696000 676000 >, + < 799000 845000 >, + < 1024000 1014000 >, + < 1491000 1716000 >, + < 1836000 2028000 >, + < 2130000 2288000 >, + < 2253000 2730000 >; + }; + }; + + cpu5_memlat_cpugrp: cpu5-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu5>; + + cpu5_cpu_mif_latmon: cpu5-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu5>; + target-dev = <&mif_cpu5_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 400000 421000 >, + < 553000 546000 >, + < 696000 676000 >, + < 799000 845000 >, + < 1024000 1014000 >, + < 1491000 1716000 >, + < 1836000 2028000 >, + < 2130000 2288000 >, + < 2253000 2730000 >; + }; + }; + + cpu6_memlat_cpugrp: cpu6-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu6>; + + cpu6_cpu_mif_latmon: cpu6-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu6>; + target-dev = <&mif_cpu6_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 10000 421000 >, + < 100000 845000 >, + < 851000 1014000 >, + < 1106000 1352000 >, + < 1277000 1539000 >, + < 1582000 1716000 >, + < 1826000 2028000 >, + < 2048000 2288000 >, + < 2252000 2730000 >, + < 2507000 3172000 >; + }; + }; + + cpu7_memlat_cpugrp: cpu7-cpugrp { + compatible = "arm-memlat-cpugrp"; + cpulist = <&cpu7>; + + cpu7_cpu_mif_latmon: cpu7-cpu-mif-latmon { + compatible = "arm-memlat-mon"; + cpulist = <&cpu7>; + target-dev = <&mif_cpu7_mem_lat>; + cachemiss-ev = <0x2A>; + core-dev-table = + < 10000 421000 >, + < 100000 845000 >, + < 851000 1014000 >, + < 1106000 1352000 >, + < 1277000 1539000 >, + < 1582000 1716000 >, + < 1826000 2028000 >, + < 2048000 2288000 >, + < 2252000 2730000 >, + < 2507000 3172000 >; + }; + }; + + g2d: g2d@1C640000 { + compatible = "samsung,gs201-g2d"; + reg = <0x0 0x1C640000 0xA000>; + interrupts = <0 IRQ_G2D_G2D IRQ_TYPE_LEVEL_HIGH>; + samsung,iommu-group = <&iommu_group_g2d>; + iommus = <&sysmmu_g2d0>, <&sysmmu_g2d1>; + clocks = <&clock GATE_G2D>; + clock-names = "gate"; + samsung,tzmp; + hw_ppc = + /* sc_up none x1 x1/4 x1/9 x1/16 */ + <3800 3200 2100 2600 3300 3600 /* rgb32 non-rotated */ + 3500 3600 2100 2700 3300 3800 /* rgb32 rotated */ + 3700 3500 3600 4300 4300 3500 /* yuv2p non-rotated */ + 2600 2800 3200 3900 4300 3600 /* yuv2p rotated */ + 3600 2600 1400 900 1000 1000 /* sbwc non-rotated */ + 2600 2600 1400 900 1000 1000 /* sbwc rotated */ + 1600 3400 300 500 800 700 /*rgb afbc non-rotated*/ + 1400 3600 300 800 900 900 /*rgb afbc rotated*/ + 2900 2000 800 300 300 400 /*yuv afbc non-rotated*/ + 2600 2000 800 300 300 400 /*yuv afbc rotated*/ + 2800>; /* colorfill */ + + g2d_dvfs_table = <533000 711000 + 465000 400000 + 332000 332000 + 200000 200000 + 100000 100000 + >; + itmon,port = "G2D0", "G2D1"; + itmon,dest = "G2D"; + dvfs_mif = ; + dvfs_int = ; + }; + + watchdog_cl0: watchdog_cl0@10060000 { + compatible = "google,gs201-cl0-wdt"; + reg = <0x0 0x10060000 0x100>; + interrupts = ; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CL0>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <0>; /* if little cluster then index is 0*/ + }; + + watchdog_cl1: watchdog_cl1@10070000 { + compatible = "google,gs201-cl1-wdt"; + reg = <0x0 0x10070000 0x100>; + interrupts = ; + clocks = <&clock OSCCLK>, <&clock GATE_WDT_CL1>; + clock-names = "rate_watchdog", "gate_watchdog"; + timeout-sec = <30>; + samsung,syscon-phandle = <&pmu_system_controller>; + index = <1>; /* if little cluster then index is 0*/ + use_multistage_wdt; /* Use FIQ debug watchdog */ + }; + + acpm_tmu { + acpm-ipc-channel = <9>; + }; + + /* Secure Log */ + seclog { + compatible = "samsung,exynos-seclog"; + interrupts = ; + memory-region = <&seclog_mem>; + }; + pps { + compatible = "pps-gpio"; + gpios = <&gpp15 1 GPIO_ACTIVE_HIGH>; + assert-falling-edge = <0>; + }; +}; diff --git a/arch/arm64/configs/OWNERS b/arch/arm64/configs/OWNERS index d42000ef8412..a8a3bf31fe6a 100644 --- a/arch/arm64/configs/OWNERS +++ b/arch/arm64/configs/OWNERS @@ -1,4 +1,6 @@ per-file slider_gki.fragment = * +per-file cloudripper_gki.fragment = * +per-file gs201_*.fragment = * per-file db845c_gki.fragment = file:/OWNERS_core per-file defconfig = file:/OWNERS_core per-file gki_defconfig = file:/OWNERS_core diff --git a/arch/arm64/configs/cloudripper_gki.fragment b/arch/arm64/configs/cloudripper_gki.fragment new file mode 100644 index 000000000000..3f6475784a0e --- /dev/null +++ b/arch/arm64/configs/cloudripper_gki.fragment @@ -0,0 +1,169 @@ +# +# Cloudripper add-on configs +# + +# CONFIG_MODULE_SIG is not set +CONFIG_ACPM_DVFS=m +CONFIG_ACPM_FLEXPMU_DBG=m +CONFIG_ACPM_MBOX_TEST=m +CONFIG_ACPM_POWER_STATS=m +CONFIG_ARM_DSU_PMU=m +CONFIG_ARM_EXYNOS_ACME=m +CONFIG_ARM_EXYNOS_DEVFREQ=m +CONFIG_ARM_MEMLAT_MON=m +CONFIG_BCM_GPS_SPI_DRIVER=m +CONFIG_BIGOCEAN=m +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BOARD_CLOUDRIPPER=y +CONFIG_CAL_IF=m +CONFIG_CHR_DEV_SG=m +CONFIG_CH_EXTENSION=m +CONFIG_CLKSRC_EXYNOS_MCT=m +CONFIG_COMMON_CLK_SAMSUNG=m +CONFIG_CORESIGHT=m +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m +CONFIG_CORESIGHT_SOURCE_ETM4X=m +CONFIG_CPIF_TP_MONITOR=m +CONFIG_CP_PKTPROC=m +CONFIG_CP_PKTPROC_UL=m +CONFIG_CP_THERMAL=m +CONFIG_DBGCORE_DUMP=m +CONFIG_DEBUG_REBOOT=m +CONFIG_DEBUG_SNAPSHOT=m +CONFIG_DEBUG_SNAPSHOT_DEBUG_KINFO=m +CONFIG_DEVFREQ_GOV_MEMLAT=m +CONFIG_DEVFREQ_GOV_SIMPLE_INTERACTIVE=y +CONFIG_DMABUF_HEAPS_SAMSUNG_CARVEOUT=y +CONFIG_DMABUF_HEAPS_SAMSUNG_CHUNK=y +CONFIG_DMABUF_HEAPS_SAMSUNG_CMA=y +CONFIG_DMABUF_HEAPS_SAMSUNG_SYSTEM=y +CONFIG_DMABUF_SAMSUNG_HEAPS=m +CONFIG_DRV_SAMSUNG_PMIC=m +CONFIG_ECT=m +CONFIG_EEPROM_AT24=m +CONFIG_EXYNOS_ACPM_THERMAL=m +CONFIG_EXYNOS_ADV_TRACER=m +CONFIG_EXYNOS_ADV_TRACER_S2D=m +CONFIG_EXYNOS_ALT_DVFS=m +CONFIG_EXYNOS_BCM_DBG=m +CONFIG_EXYNOS_BCM_DBG_DUMP=m +CONFIG_EXYNOS_BCM_DBG_PPMU=y +CONFIG_EXYNOS_BTS=m +CONFIG_EXYNOS_CONTENT_PATH_PROTECTION=m +CONFIG_EXYNOS_CORESIGHT=m +CONFIG_EXYNOS_CORESIGHT_ETF=y +CONFIG_EXYNOS_CORESIGHT_ETM=m +CONFIG_EXYNOS_CORESIGHT_ETR=y +CONFIG_EXYNOS_CPUHP=m +CONFIG_EXYNOS_CPUPM=m +CONFIG_EXYNOS_CPU_THERMAL=m +CONFIG_EXYNOS_DEBUG_TEST=m +CONFIG_EXYNOS_DVFS_MANAGER=m +CONFIG_EXYNOS_ECC_HANDLER=m +CONFIG_EXYNOS_EHLD=m +CONFIG_EXYNOS_GRAPHICS_G2D=m +CONFIG_EXYNOS_ITMON=m +CONFIG_EXYNOS_MODEM_IF=m +CONFIG_EXYNOS_PCIE_IOMMU=m +CONFIG_EXYNOS_PD=m +CONFIG_EXYNOS_PD_DBG=m +CONFIG_EXYNOS_PM=m +CONFIG_EXYNOS_PMU_IF=m +CONFIG_EXYNOS_PM_QOS=m +CONFIG_EXYNOS_SECURE_LOG=m +CONFIG_GOODIX_FINGERPRINT=m +CONFIG_GOOGLE_BCL=m +CONFIG_GOOGLE_EH=m +CONFIG_GOOGLE_LOGBUFFER=m +CONFIG_GOOGLE_VOTABLE=m +CONFIG_GPIOLIB=y +CONFIG_GPU_THERMAL=m +CONFIG_GS101_THERMAL_V2=m +CONFIG_GSA=m +CONFIG_GSA_GSC=m +CONFIG_GSA_PKVM=y +CONFIG_GSOC_PMIC_THERMAL=m +CONFIG_GS_ACPM=m +CONFIG_GS_CHIPID=m +CONFIG_GS_SJTAG=m +CONFIG_GS_SLC_ACPM=m +CONFIG_HARDLOCKUP_DEBUG=m +CONFIG_HARDLOCKUP_WATCHDOG=m +CONFIG_I2C_ACPM=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_EXYNOS5=m +CONFIG_INPUT_KEYCOMBO=m +CONFIG_INPUT_KEYDEBUG=m +CONFIG_KERNEL_TOP=m +CONFIG_INPUT_STMVL53L1=m +CONFIG_KEYBOARD_S2MPG12=m +CONFIG_LINK_DEVICE_PCIE_IOCC=y +CONFIG_LINK_DEVICE_PCIE_IOMMU=y +CONFIG_LOG_BUF_SHIFT=22 +CONFIG_MFD_S2MPG12=m +CONFIG_MFD_S2MPG13=m +CONFIG_MFD_S2MPG1X_GPIO=m +CONFIG_MFD_SLG51000=m +CONFIG_MFD_SLG51002=m +CONFIG_MODEM_IF_QOS=m +CONFIG_ODPM=m +CONFIG_PCI_EXYNOS=m +CONFIG_PCI_EXYNOS_CAL_GS201=m +CONFIG_PHY_EXYNOS_MIPI=m +CONFIG_PHY_EXYNOS_MIPI_DSIM=m +CONFIG_PHY_EXYNOS_USBDRD=m +CONFIG_PHY_SAMSUNG_USB_GEN2_V4=y +CONFIG_PINCTRL_GS=m +CONFIG_PINCTRL_SAMSUNG=m +CONFIG_PINCTRL_SLG51000=m +CONFIG_PINCTRL_SLG51002=m +CONFIG_PIXEL_BOOT_METRICS=m +CONFIG_PIXEL_DEBUG_TEST=m +CONFIG_PIXEL_STAT=m +CONFIG_PERF_METRICS=m +CONFIG_PKVM_S2MPU=m +CONFIG_POWER_RESET_EXYNOS=m +CONFIG_PPS=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_REGULATOR_S2MPG12=m +CONFIG_REGULATOR_S2MPG13=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_SLG51002=m +CONFIG_RTC_DRV_S2MPG12=m +CONFIG_S3C2410_WATCHDOG=m +CONFIG_SAMSUNG_DMADEV=m +CONFIG_SAMSUNG_IOMMU=m +CONFIG_SBB_MUX=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_UFS_EXYNOS=m +CONFIG_SCSI_UFS_PIXEL_FIPS140=m +CONFIG_SEC_MODEM_S5100=m +CONFIG_SENSORS_SSP_BBD=m +CONFIG_SERIAL_EXYNOS=m +CONFIG_SHM_IPC=m +CONFIG_SLC_PARTITION_MANAGER=m +CONFIG_SLC_PMON=y +CONFIG_SOC_GOOGLE=y +CONFIG_SOC_GS201=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SPI_S3C64XX=m +CONFIG_SPI_SPIDEV=m +CONFIG_SUBSYSTEM_COREDUMP=m +CONFIG_SUSPEND_DURING_VOICE_CALL=y +CONFIG_SYSRQ_HOOK=m +CONFIG_TRUSTY=m +CONFIG_TRUSTY_DMA_BUF_FFA_TAG=y +CONFIG_TRUSTY_CRASH_IS_PANIC=y +CONFIG_TYPEC_COOLING_DEV=m +CONFIG_TYPEC_MAX77759=m +CONFIG_USB_CONFIGFS_F_DM=m +CONFIG_USB_CONFIGFS_F_ETR_MIU=m +CONFIG_USB_CONFIGFS_RNDIS=m +CONFIG_USB_DWC3_EXYNOS=m +CONFIG_USB_XHCI_EXYNOS=m +CONFIG_VIDEO_EXYNOS_MFC=m +CONFIG_VIDEO_EXYNOS_SMFC=m +CONFIG_ZCOMP_EH=m +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZSMALLOC=m diff --git a/arch/arm64/configs/gs201_emulator.fragment b/arch/arm64/configs/gs201_emulator.fragment new file mode 100644 index 000000000000..36e1dda578b5 --- /dev/null +++ b/arch/arm64/configs/gs201_emulator.fragment @@ -0,0 +1,18 @@ +CONFIG_LOG_BUF_SHIFT=22 +CONFIG_SOC_GOOGLE=y +CONFIG_SOC_GS201=y +CONFIG_BOARD_EMULATOR=y +CONFIG_BOARD_GS201_EMULATOR=y +CONFIG_GS_CHIPID=y +CONFIG_SERIAL_EXYNOS=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_EXYNOS5=m +CONFIG_PINCTRL_SAMSUNG=y +CONFIG_PINCTRL_GS=y +CONFIG_CLKSRC_EXYNOS_MCT=y +CONFIG_SLC_PMON=y +CONFIG_GPIOLIB=y +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_CPU_IDLE is not set +# CONFIG_EXYNOS_PD_EL3 is not set diff --git a/arch/arm64/configs/gs201_hybrid.fragment b/arch/arm64/configs/gs201_hybrid.fragment new file mode 100644 index 000000000000..5af9c11d7479 --- /dev/null +++ b/arch/arm64/configs/gs201_hybrid.fragment @@ -0,0 +1,20 @@ +CONFIG_LOG_BUF_SHIFT=22 +CONFIG_SOC_GOOGLE=y +CONFIG_SOC_GS201=y +CONFIG_BOARD_EMULATOR=y +CONFIG_BOARD_GS201_HYBRID=y +CONFIG_GS_CHIPID=y +CONFIG_SERIAL_EXYNOS=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_EXYNOS5=m +CONFIG_PINCTRL_SAMSUNG=y +CONFIG_PINCTRL_GS=y +CONFIG_CLKSRC_EXYNOS_MCT=y +CONFIG_SLC_PMON=y +CONFIG_GPIOLIB=y +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_CPU_IDLE is not set +# CONFIG_EXYNOS_PD_EL3 is not set +# CONFIG_VH_KERNEL is not set +CONFIG_SAMSUNG_IOMMU=m diff --git a/arch/arm64/configs/rockchip_gki.fragment b/arch/arm64/configs/rockchip_gki.fragment new file mode 100644 index 000000000000..6253108101a8 --- /dev/null +++ b/arch/arm64/configs/rockchip_gki.fragment @@ -0,0 +1,342 @@ +CONFIG_AP6XXX=m +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ARM_ROCKCHIP_BUS_DEVFREQ=m +CONFIG_ARM_ROCKCHIP_CPUFREQ=m +CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_CW2017=m +CONFIG_BATTERY_CW221X=m +CONFIG_BATTERY_RK817=m +CONFIG_BATTERY_RK818=m +CONFIG_BLK_DEV_NVME=m +CONFIG_BMA2XX_ACC=m +CONFIG_CHARGER_BQ25700=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_RK818=m +CONFIG_CHARGER_SC89890=m +CONFIG_CHARGER_SGM41542=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_ROCKCHIP=m +CONFIG_COMMON_CLK_SCMI=m +CONFIG_COMPASS_AK8963=m +CONFIG_COMPASS_AK8975=m +CONFIG_COMPASS_DEVICE=m +CONFIG_CPUFREQ_DT=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_RK3588=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +CONFIG_CRYPTO_DEV_ROCKCHIP=m +CONFIG_CRYPTO_DEV_ROCKCHIP_DEV=m +CONFIG_CRYPTO_GHASH_ARM64_CE=m +CONFIG_CRYPTO_SHA1_ARM64_CE=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_DEVFREQ_EVENT_ROCKCHIP_NOCP=m +CONFIG_DMABUF_HEAPS_CMA=m +CONFIG_DMABUF_HEAPS_SYSTEM=m +CONFIG_DRAGONRISE_FF=y +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_DW_HDMI_CEC=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_MAXIM_MAX96745=m +CONFIG_DRM_MAXIM_MAX96752F=m +CONFIG_DRM_MAXIM_MAX96755F=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_RK1000_TVE=m +CONFIG_DRM_RK630_TVE=m +CONFIG_DRM_ROCKCHIP=m +CONFIG_DRM_ROCKCHIP_RK628=m +CONFIG_DRM_ROHM_BU18XL82=m +CONFIG_DRM_SII902X=m +CONFIG_DTC_SYMBOLS=y +CONFIG_DW_WATCHDOG=m +CONFIG_GPIO_ROCKCHIP=m +CONFIG_GREENASIA_FF=y +CONFIG_GSENSOR_DEVICE=m +CONFIG_GS_DA223=m +CONFIG_GS_KXTJ9=m +CONFIG_GS_LIS3DH=m +CONFIG_GS_LSM303D=m +CONFIG_GS_MC3230=m +CONFIG_GS_MMA7660=m +CONFIG_GS_MMA8452=m +CONFIG_GS_MXC6655XA=m +CONFIG_GS_SC7660=m +CONFIG_GS_SC7A20=m +CONFIG_GS_SC7A30=m +CONFIG_GYROSCOPE_DEVICE=m +CONFIG_GYRO_EWTSA=m +CONFIG_GYRO_L3G20D=m +CONFIG_GYRO_L3G4200D=m +CONFIG_GYRO_LSM330=m +CONFIG_GYRO_MPU6500=m +CONFIG_GYRO_MPU6880=m +CONFIG_HALL_DEVICE=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_ALPS=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_EZKEY=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_GYRATION=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_ICADE=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LENOVO=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_WALTOP=m +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HS_MH248=m +CONFIG_HW_RANDOM_ROCKCHIP=m +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_HID=m +CONFIG_I2C_RK3X=m +CONFIG_IEP=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_KEYBOARD_ADC=m +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_RGB13H=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LIGHT_DEVICE=m +CONFIG_LSM330_ACC=m +CONFIG_LS_CM3217=m +CONFIG_LS_CM3218=m +CONFIG_LS_STK3410=m +CONFIG_LS_UCS14620=m +CONFIG_MALI_BIFROST=m +CONFIG_MALI_BIFROST_DEBUG=y +CONFIG_MALI_BIFROST_EXPERT=y +CONFIG_MALI_CSF_SUPPORT=y +CONFIG_MALI_PLATFORM_NAME="rk" +CONFIG_MALI_PWRSOFT_765=y +CONFIG_MFD_RK628=m +CONFIG_MFD_RK630_I2C=m +CONFIG_MFD_RK806_SPI=m +CONFIG_MFD_RK808=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_ROCKCHIP=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MPU6500_ACC=m +CONFIG_MPU6880_ACC=m +CONFIG_OPTEE=m +CONFIG_PANTHERLORD_FF=y +CONFIG_PCIEASPM_EXT=m +CONFIG_PCIE_DW_ROCKCHIP=m +CONFIG_PCIE_ROCKCHIP_HOST=m +CONFIG_PHY_ROCKCHIP_CSI2_DPHY=m +CONFIG_PHY_ROCKCHIP_DP=m +CONFIG_PHY_ROCKCHIP_EMMC=m +CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m +CONFIG_PHY_ROCKCHIP_INNO_HDMI=m +CONFIG_PHY_ROCKCHIP_INNO_USB2=m +CONFIG_PHY_ROCKCHIP_INNO_USB3=m +CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=m +CONFIG_PHY_ROCKCHIP_NANENG_EDP=m +CONFIG_PHY_ROCKCHIP_PCIE=m +CONFIG_PHY_ROCKCHIP_SAMSUNG_DCPHY=m +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=m +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=m +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=m +CONFIG_PHY_ROCKCHIP_TYPEC=m +CONFIG_PHY_ROCKCHIP_USB=m +CONFIG_PHY_ROCKCHIP_USBDP=m +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_RK806=m +CONFIG_PINCTRL_ROCKCHIP=m +CONFIG_PL330_DMA=m +CONFIG_PROXIMITY_DEVICE=m +CONFIG_PS_STK3410=m +CONFIG_PS_UCS14620=m +CONFIG_PWM_ROCKCHIP=m +CONFIG_REGULATOR_ACT8865=m +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_LP8752=m +CONFIG_REGULATOR_MP8865=m +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_RK806=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_RK860X=m +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_WL2868C=m +CONFIG_REGULATOR_XZ3216=m +CONFIG_RFKILL_RK=m +CONFIG_RK_CONSOLE_THREAD=y +CONFIG_RK_HEADSET=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_CDN_DP=y +CONFIG_ROCKCHIP_CPUINFO=m +CONFIG_ROCKCHIP_DEBUG=m +CONFIG_ROCKCHIP_DW_DP=y +CONFIG_ROCKCHIP_DW_HDCP2=m +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_EFUSE=m +CONFIG_ROCKCHIP_GRF=m +CONFIG_ROCKCHIP_INNO_HDMI=y +CONFIG_ROCKCHIP_IODOMAIN=m +CONFIG_ROCKCHIP_IOMMU=m +CONFIG_ROCKCHIP_IPA=m +CONFIG_ROCKCHIP_LVDS=y +CONFIG_ROCKCHIP_MPP_AV1DEC=y +CONFIG_ROCKCHIP_MPP_IEP2=y +CONFIG_ROCKCHIP_MPP_JPGDEC=y +CONFIG_ROCKCHIP_MPP_RKVDEC=y +CONFIG_ROCKCHIP_MPP_RKVDEC2=y +CONFIG_ROCKCHIP_MPP_RKVENC=y +CONFIG_ROCKCHIP_MPP_RKVENC2=y +CONFIG_ROCKCHIP_MPP_SERVICE=m +CONFIG_ROCKCHIP_MPP_VDPU1=y +CONFIG_ROCKCHIP_MPP_VDPU2=y +CONFIG_ROCKCHIP_MPP_VEPU1=y +CONFIG_ROCKCHIP_MPP_VEPU2=y +CONFIG_ROCKCHIP_MULTI_RGA=m +CONFIG_ROCKCHIP_OPP=m +CONFIG_ROCKCHIP_OTP=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_ROCKCHIP_PM_DOMAINS=m +CONFIG_ROCKCHIP_PVTM=m +CONFIG_ROCKCHIP_REMOTECTL=m +CONFIG_ROCKCHIP_REMOTECTL_PWM=m +CONFIG_ROCKCHIP_RGB=y +CONFIG_ROCKCHIP_RKNPU=m +CONFIG_ROCKCHIP_SARADC=m +CONFIG_ROCKCHIP_SIP=m +CONFIG_ROCKCHIP_SUSPEND_MODE=m +CONFIG_ROCKCHIP_SYSTEM_MONITOR=m +CONFIG_ROCKCHIP_THERMAL=m +CONFIG_ROCKCHIP_TIMER=m +CONFIG_ROCKCHIP_VENDOR_STORAGE=m +CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y +CONFIG_RTC_DRV_HYM8563=m +CONFIG_RTC_DRV_RK808=m +CONFIG_SENSOR_DEVICE=m +CONFIG_SERIAL_8250_DW=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DUMMY_CODEC=m +CONFIG_SND_SOC_ES7202=m +CONFIG_SND_SOC_ES7210=m +CONFIG_SND_SOC_ES7243E=m +CONFIG_SND_SOC_ES8311=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8323=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8396=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RK_CODEC_DIGITAL=m +CONFIG_SND_SOC_ROCKCHIP=m +CONFIG_SND_SOC_ROCKCHIP_HDMI=m +CONFIG_SND_SOC_ROCKCHIP_I2S=m +CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m +CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=m +CONFIG_SND_SOC_ROCKCHIP_PDM=m +CONFIG_SND_SOC_ROCKCHIP_SPDIF=m +CONFIG_SND_SOC_ROCKCHIP_SPDIFRX=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_SPIDEV=m +CONFIG_SW_SYNC=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_TEE=m +CONFIG_TEST_POWER=m +CONFIG_TOUCHSCREEN_ELAN5515=m +CONFIG_TOUCHSCREEN_GSL3673=m +CONFIG_TOUCHSCREEN_GSLX680_PAD=m +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_HUSB311=m +CONFIG_UCS12CM0=m +CONFIG_USB_DWC2=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_OHCI_HCD=m +# CONFIG_USB_OHCI_HCD_PCI is not set +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_VIDEO_AW36518=m +CONFIG_VIDEO_AW8601=m +CONFIG_VIDEO_CN3927V=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_FP5510=m +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_GC2385=m +CONFIG_VIDEO_GC4C33=m +CONFIG_VIDEO_GC8034=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_LT6911UXC=m +CONFIG_VIDEO_LT7911D=m +CONFIG_VIDEO_NVP6188=m +CONFIG_VIDEO_OV02B10=m +CONFIG_VIDEO_OV13850=m +CONFIG_VIDEO_OV13855=m +CONFIG_VIDEO_OV50C40=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_RK628_BT1120=m +CONFIG_VIDEO_RK628_CSI=m +CONFIG_VIDEO_RK_IRCUT=m +CONFIG_VIDEO_ROCKCHIP_CIF=m +CONFIG_VIDEO_ROCKCHIP_ISP=m +CONFIG_VIDEO_ROCKCHIP_ISPP=m +CONFIG_VIDEO_S5K3L6XX=m +CONFIG_VIDEO_S5KJN1=m +CONFIG_VIDEO_SGM3784=m +CONFIG_VIDEO_THCV244=m +CONFIG_VL6180=m +CONFIG_WIFI_BUILD_MODULE=y +CONFIG_WL_ROCKCHIP=m +CONFIG_ZRAM=m +CONFIG_ZSMALLOC=m +# CONFIG_USB_DUMMY_HCD is not set diff --git a/arch/arm64/configs/slider_gki.fragment b/arch/arm64/configs/slider_gki.fragment index 41dbd3dbdbbb..f9d0f88ea1ea 100644 --- a/arch/arm64/configs/slider_gki.fragment +++ b/arch/arm64/configs/slider_gki.fragment @@ -47,6 +47,7 @@ CONFIG_USB_CONFIGFS_F_DM=m CONFIG_USB_CONFIGFS_RNDIS=m CONFIG_INPUT_KEYCOMBO=m # CONFIG_INPUT_KEYDEBUG is not set +CONFIG_KERNEL_TOP=m CONFIG_INPUT_STMVL53L1=m CONFIG_PHY_EXYNOS_USBDRD=m CONFIG_PHY_SAMSUNG_USB_GEN2_V4=y @@ -79,11 +80,12 @@ CONFIG_SEC_MODEM_S5100=m CONFIG_CP_PKTPROC=m CONFIG_CP_PKTPROC_UL=m CONFIG_CPIF_TP_MONITOR=m -CONFIG_LINK_DEVICE_PCIE_GPIO_WA=m -CONFIG_CP_WRESET_WA=m +CONFIG_LINK_DEVICE_PCIE_GPIO_WA=y +CONFIG_CP_WRESET_WA=y CONFIG_CP_THERMAL=m CONFIG_SUSPEND_DURING_VOICE_CALL=m -CONFIG_MODEM_IF_LEGACY_QOS=m +CONFIG_CH_EXTENSION=m +CONFIG_MODEM_IF_QOS=m CONFIG_CH_EXTENSION=m CONFIG_VIDEO_EXYNOS_MFC=m CONFIG_EXYNOS_BTS=m @@ -94,7 +96,6 @@ CONFIG_GS_S2MPU=m CONFIG_SLC_PARTITION_MANAGER=m CONFIG_GS_SLC_ACPM=m CONFIG_SLC_PMON=y -CONFIG_PIXEL_EM=m CONFIG_ACPM_FLEXPMU_DBG=m CONFIG_ACPM_POWER_STATS=m CONFIG_ACPM_MBOX_TEST=m @@ -102,6 +103,7 @@ CONFIG_TYPEC_FUSB307=m CONFIG_TYPEC_MAX77759=m CONFIG_GS101_THERMAL_V2=m CONFIG_EXYNOS_ACPM_THERMAL=m +CONFIG_LINK_DEVICE_PCIE_IOCC=y CONFIG_EXYNOS_CPU_THERMAL=m CONFIG_GPU_THERMAL=m CONFIG_ISP_THERMAL=m @@ -153,6 +155,7 @@ CONFIG_USB_CONFIGFS_F_ETR_MIU=m CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y CONFIG_SOFT_WATCHDOG=m CONFIG_PIXEL_STAT=m +# CONFIG_PERF_METRICS is not set CONFIG_ARM_MEMLAT_MON=m CONFIG_DEVFREQ_GOV_MEMLAT=m CONFIG_TYPEC_COOLING_DEV=m diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h index ef1cf41ea394..edca12fd852e 100644 --- a/arch/arm64/include/asm/kvm_asm.h +++ b/arch/arm64/include/asm/kvm_asm.h @@ -75,6 +75,7 @@ enum __kvm_host_smccc_func { __KVM_HOST_SMCCC_FUNC___vgic_v3_save_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs, __KVM_HOST_SMCCC_FUNC___pkvm_init_shadow, + __KVM_HOST_SMCCC_FUNC___pkvm_init_shadow_vcpu, __KVM_HOST_SMCCC_FUNC___pkvm_teardown_shadow, __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load, __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put, diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 86cbee644a39..366999f8698a 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2129,6 +2129,17 @@ static int pkvm_drop_host_privileges(void) * once the host stage 2 is installed. */ static_branch_enable(&kvm_protected_mode_initialized); + + /* + * Fixup the boot mode so that we don't take spurious round + * trips via EL2 on cpu_resume. Flush to the PoC for a good + * measure, so that it can be observed by a CPU coming out of + * suspend with the MMU off. + */ + __boot_cpu_mode[0] = __boot_cpu_mode[1] = BOOT_CPU_MODE_EL1; + dcache_clean_poc((unsigned long)__boot_cpu_mode, + (unsigned long)(__boot_cpu_mode + 2)); + on_each_cpu(_kvm_host_prot_finalize, &ret, 1); return ret; } @@ -2286,6 +2297,16 @@ static int __init early_kvm_mode_cfg(char *arg) if (!arg) return -EINVAL; + if (strcmp(arg, "none") == 0) { + kvm_mode = KVM_MODE_NONE; + return 0; + } + + if (!is_hyp_mode_available()) { + pr_warn_once("KVM is not available. Ignoring kvm-arm.mode\n"); + return 0; + } + if (strcmp(arg, "protected") == 0) { if (!is_kernel_in_hyp_mode()) kvm_mode = KVM_MODE_PROTECTED; @@ -2300,11 +2321,6 @@ static int __init early_kvm_mode_cfg(char *arg) return 0; } - if (strcmp(arg, "none") == 0) { - kvm_mode = KVM_MODE_NONE; - return 0; - } - return -EINVAL; } early_param("kvm-arm.mode", early_kvm_mode_cfg); diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 14a80b0e2f91..ceb6808c2d80 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -13,6 +13,7 @@ #include #include #include +#include #if !defined (__KVM_NVHE_HYPERVISOR__) && !defined (__KVM_VHE_HYPERVISOR__) #error Hypervisor code only! @@ -165,7 +166,8 @@ static void enter_exception64(struct kvm_vcpu *vcpu, unsigned long target_mode, *vcpu_pc(vcpu) = vbar + offset; old = *vcpu_cpsr(vcpu); - new = get_except64_cpsr(old, kvm_has_mte(vcpu->kvm), sctlr, target_mode); + new = get_except64_cpsr(old, kvm_has_mte(kern_hyp_va(vcpu->kvm)), sctlr, + target_mode); *vcpu_cpsr(vcpu) = new; __vcpu_write_spsr(vcpu, old); } diff --git a/arch/arm64/kvm/hyp/include/nvhe/pkvm.h b/arch/arm64/kvm/hyp/include/nvhe/pkvm.h index 80ecc831fc31..de7f607dde58 100644 --- a/arch/arm64/kvm/hyp/include/nvhe/pkvm.h +++ b/arch/arm64/kvm/hyp/include/nvhe/pkvm.h @@ -42,14 +42,20 @@ struct kvm_shadow_vm { /* The total size of the donated shadow area. */ size_t shadow_area_size; + /* + * The number of vcpus initialized and ready to run in the shadow vm. + * Modifying this is protected by shadow_lock. + */ + unsigned int nr_vcpus; + struct kvm_arch arch; struct kvm_pgtable pgt; struct kvm_pgtable_mm_ops mm_ops; struct hyp_pool pool; hyp_spinlock_t lock; - /* Array of the shadow state per vcpu. */ - struct shadow_vcpu_state shadow_vcpus[0]; + /* Array of the shadow state pointers per vcpu. */ + struct shadow_vcpu_state *shadow_vcpus[0]; }; static inline bool vcpu_is_protected(struct kvm_vcpu *vcpu) @@ -65,6 +71,9 @@ extern phys_addr_t pvmfw_size; void hyp_shadow_table_init(void *tbl); int __pkvm_init_shadow(struct kvm *kvm, void *shadow_va, size_t size, void *pgd); +int __pkvm_init_shadow_vcpu(unsigned int shadow_handle, + struct kvm_vcpu *host_vcpu, + void *shadow_vcpu_hva); int __pkvm_teardown_shadow(int shadow_handle); struct kvm_vcpu *get_shadow_vcpu(int shadow_handle, unsigned int vcpu_idx); void put_shadow_vcpu(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 14f9da9f87b9..9901e102f330 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -1006,6 +1006,17 @@ static void handle___pkvm_init_shadow(struct kvm_cpu_context *host_ctxt) shadow_size, pgd); } +static void handle___pkvm_init_shadow_vcpu(struct kvm_cpu_context *host_ctxt) +{ + DECLARE_REG(unsigned int, shadow_handle, host_ctxt, 1); + DECLARE_REG(struct kvm_vcpu *, host_vcpu, host_ctxt, 2); + DECLARE_REG(void *, shadow_vcpu_hva, host_ctxt, 3); + + cpu_reg(host_ctxt, 1) = __pkvm_init_shadow_vcpu(shadow_handle, + host_vcpu, + shadow_vcpu_hva); +} + static void handle___pkvm_teardown_shadow(struct kvm_cpu_context *host_ctxt) { DECLARE_REG(int, shadow_handle, host_ctxt, 1); @@ -1079,6 +1090,7 @@ static const hcall_t host_hcall[] = { HANDLE_FUNC(__vgic_v3_save_vmcr_aprs), HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs), HANDLE_FUNC(__pkvm_init_shadow), + HANDLE_FUNC(__pkvm_init_shadow_vcpu), HANDLE_FUNC(__pkvm_teardown_shadow), HANDLE_FUNC(__pkvm_vcpu_load), HANDLE_FUNC(__pkvm_vcpu_put), diff --git a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c index ff5d7d1044e5..20c65f7489ed 100644 --- a/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c +++ b/arch/arm64/kvm/hyp/nvhe/iommu/s2mpu.c @@ -24,6 +24,10 @@ #define PA_MAX ((phys_addr_t)SZ_1G * NR_GIGABYTES) +#define SYNC_MAX_RETRIES 5 +#define SYNC_TIMEOUT 5 +#define SYNC_TIMEOUT_MULTIPLIER 3 + #define CTX_CFG_ENTRY(ctxid, nr_ctx, vid) \ (CONTEXT_CFG_VALID_VID_CTX_VID(ctxid, vid) \ | (((ctxid) < (nr_ctx)) ? CONTEXT_CFG_VALID_VID_CTX_VALID(ctxid) : 0)) @@ -158,11 +162,20 @@ static void __set_control_regs(struct pkvm_iommu *dev) writel_relaxed(ctrl0, dev->va + REG_NS_CTRL0); } -/* Poll the given SFR until its value has all bits of a given mask set. */ -static void __wait_until(void __iomem *addr, u32 mask) +/* + * Poll the given SFR until its value has all bits of a given mask set. + * Returns true if successful, false if not successful after a given number of + * attempts. + */ +static bool __wait_until(void __iomem *addr, u32 mask, size_t max_attempts) { - while ((readl_relaxed(addr) & mask) != mask) - continue; + size_t i; + + for (i = 0; i < max_attempts; i++) { + if ((readl_relaxed(addr) & mask) == mask) + return true; + } + return false; } /* Poll the given SFR as long as its value has all bits of a given mask set. */ @@ -175,14 +188,27 @@ static void __wait_while(void __iomem *addr, u32 mask) static void __wait_for_invalidation_complete(struct pkvm_iommu *dev) { struct pkvm_iommu *sync; + size_t i, timeout; /* * Wait for transactions to drain if SysMMU_SYNCs were registered. * Assumes that they are in the same power domain as the S2MPU. + * + * The algorithm will try initiating the SYNC if the SYNC_COMP_COMPLETE + * bit has not been set after a given number of attempts, increasing the + * timeout exponentially each time. If this cycle fails a given number + * of times, the algorithm will give up completely to avoid deadlock. */ for_each_child(sync, dev) { - writel_relaxed(SYNC_CMD_SYNC, sync->va + REG_NS_SYNC_CMD); - __wait_until(sync->va + REG_NS_SYNC_COMP, SYNC_COMP_COMPLETE); + timeout = SYNC_TIMEOUT; + for (i = 0; i < SYNC_MAX_RETRIES; i++) { + writel_relaxed(SYNC_CMD_SYNC, sync->va + REG_NS_SYNC_CMD); + if (__wait_until(sync->va + REG_NS_SYNC_COMP, + SYNC_COMP_COMPLETE, timeout)) { + break; + } + timeout *= SYNC_TIMEOUT_MULTIPLIER; + } } /* Must not access SFRs while S2MPU is busy invalidating (v9 only). */ diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c index 6ca172ac3445..810436d85608 100644 --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c @@ -1915,7 +1915,14 @@ static int hyp_zero_page(phys_addr_t phys) if (!addr) return -EINVAL; memset(addr, 0, PAGE_SIZE); - __clean_dcache_guest_page(addr, PAGE_SIZE); + /* + * Prefer kvm_flush_dcache_to_poc() over __clean_dcache_guest_page() + * here as the latter may elide the CMO under the assumption that FWB + * will be enabled on CPUs that support it. This is incorrect for the + * host stage-2 and would otherwise lead to a malicious host potentially + * being able to read the content of newly reclaimed guest pages. + */ + kvm_flush_dcache_to_poc(addr, PAGE_SIZE); return hyp_fixmap_unmap(); } diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 9b2e303dd124..d43ccfd72e04 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -276,9 +276,9 @@ struct kvm_vcpu *get_shadow_vcpu(int shadow_handle, unsigned int vcpu_idx) hyp_spin_lock(&shadow_lock); vm = find_shadow_by_handle(shadow_handle); - if (!vm || vm->created_vcpus <= vcpu_idx) + if (!vm || vm->nr_vcpus <= vcpu_idx) goto unlock; - vcpu = &vm->shadow_vcpus[vcpu_idx].vcpu; + vcpu = &vm->shadow_vcpus[vcpu_idx]->vcpu; /* Ensure vcpu isn't loaded on more than one cpu simultaneously. */ if (unlikely(vcpu->arch.pkvm.loaded_on_cpu)) { @@ -370,126 +370,139 @@ static int copy_features(struct kvm_vcpu *shadow_vcpu, struct kvm_vcpu *host_vcp return 0; } -static void unpin_host_vcpus(struct shadow_vcpu_state *shadow_vcpus, int nr_vcpus) +static void unpin_host_vcpu(struct shadow_vcpu_state *shadow_vcpu) { - int i; - - for (i = 0; i < nr_vcpus; i++) { - struct kvm_vcpu *host_vcpu = shadow_vcpus[i].vcpu.arch.pkvm.host_vcpu; - struct kvm_vcpu *shadow_vcpu = &shadow_vcpus[i].vcpu; - size_t sve_state_size; - void *sve_state; + struct kvm_vcpu *host_vcpu = shadow_vcpu->vcpu.arch.pkvm.host_vcpu; + size_t sve_state_size; + void *sve_state = shadow_vcpu->vcpu.arch.sve_state; - hyp_unpin_shared_mem(host_vcpu, host_vcpu + 1); + hyp_unpin_shared_mem(host_vcpu, host_vcpu + 1); - if (!test_bit(KVM_ARM_VCPU_SVE, shadow_vcpu->arch.features)) - continue; + if (!sve_state) + return; - sve_state = shadow_vcpu->arch.sve_state; - sve_state = kern_hyp_va(sve_state); - sve_state_size = vcpu_sve_state_size(shadow_vcpu); - hyp_unpin_shared_mem(sve_state, sve_state + sve_state_size); - } + sve_state = kern_hyp_va(sve_state); + sve_state_size = vcpu_sve_state_size(&shadow_vcpu->vcpu); + hyp_unpin_shared_mem(sve_state, sve_state + sve_state_size); } -static int set_host_vcpus(struct shadow_vcpu_state *shadow_vcpus, int nr_vcpus, - struct kvm_vcpu **vcpu_array, size_t vcpu_array_size) +static void unpin_host_vcpus(struct shadow_vcpu_state *shadow_vcpus[], int nr_vcpus) { int i; - if (vcpu_array_size < sizeof(*vcpu_array) * nr_vcpus) - return -EINVAL; - - for (i = 0; i < nr_vcpus; i++) { - struct kvm_vcpu *host_vcpu = kern_hyp_va(vcpu_array[i]); - - if (hyp_pin_shared_mem(host_vcpu, host_vcpu + 1)) { - unpin_host_vcpus(shadow_vcpus, i); - return -EBUSY; - } - - shadow_vcpus[i].vcpu.arch.pkvm.host_vcpu = host_vcpu; - } - - return 0; + for (i = 0; i < nr_vcpus; i++) + unpin_host_vcpu(shadow_vcpus[i]); } -static int init_shadow_structs(struct kvm *kvm, struct kvm_shadow_vm *vm, - struct kvm_vcpu **vcpu_array, int nr_vcpus) +static int init_ptrauth(struct kvm_vcpu *shadow_vcpu) { - int i; - int ret; + int ret = 0; + if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, shadow_vcpu->arch.features) || + test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, shadow_vcpu->arch.features)) + ret = kvm_vcpu_enable_ptrauth(shadow_vcpu); + return ret; +} +static void init_shadow_vm(struct kvm *kvm, struct kvm_shadow_vm *vm, + int nr_vcpus) +{ vm->host_kvm = kvm; vm->created_vcpus = nr_vcpus; vm->arch.pkvm.pvmfw_load_addr = kvm->arch.pkvm.pvmfw_load_addr; vm->arch.pkvm.enabled = READ_ONCE(kvm->arch.pkvm.enabled); +} - for (i = 0; i < nr_vcpus; i++) { - struct shadow_vcpu_state *shadow_state = &vm->shadow_vcpus[i]; - struct kvm_vcpu *shadow_vcpu = &shadow_state->vcpu; - struct kvm_vcpu *host_vcpu = shadow_vcpu->arch.pkvm.host_vcpu; - - shadow_vcpu->kvm = kvm; - shadow_vcpu->vcpu_id = host_vcpu->vcpu_id; - shadow_vcpu->vcpu_idx = i; - - ret = copy_features(shadow_vcpu, host_vcpu); - if (ret) - return ret; - - if (test_bit(KVM_ARM_VCPU_SVE, shadow_vcpu->arch.features)) { - size_t sve_state_size; - void *sve_state; - - shadow_vcpu->arch.sve_state = READ_ONCE(host_vcpu->arch.sve_state); - shadow_vcpu->arch.sve_max_vl = READ_ONCE(host_vcpu->arch.sve_max_vl); - - sve_state = kern_hyp_va(shadow_vcpu->arch.sve_state); - sve_state_size = vcpu_sve_state_size(shadow_vcpu); - - if (!shadow_vcpu->arch.sve_state || !sve_state_size || - hyp_pin_shared_mem(sve_state, - sve_state + sve_state_size)) { - clear_bit(KVM_ARM_VCPU_SVE, - shadow_vcpu->arch.features); - shadow_vcpu->arch.sve_state = NULL; - shadow_vcpu->arch.sve_max_vl = 0; - return -EINVAL; - } - } +static int init_shadow_vcpu(struct shadow_vcpu_state *shadow_state, + struct kvm_vcpu *host_vcpu, + struct kvm_shadow_vm *vm, int vcpu_idx) +{ + struct kvm_vcpu *shadow_vcpu = &shadow_state->vcpu; + int ret; - if (vm->arch.pkvm.enabled) - pkvm_vcpu_init_traps(shadow_vcpu); - kvm_reset_pvm_sys_regs(shadow_vcpu); + host_vcpu = kern_hyp_va(host_vcpu); + if (hyp_pin_shared_mem(host_vcpu, host_vcpu + 1)) + return -EBUSY; - vm->vcpus[i] = shadow_vcpu; - shadow_state->vm = vm; + if (host_vcpu->vcpu_idx != vcpu_idx) { + ret = -EINVAL; + goto done; + } - shadow_vcpu->arch.hw_mmu = &vm->arch.mmu; - shadow_vcpu->arch.pkvm.shadow_vm = vm; - shadow_vcpu->arch.power_off = true; + shadow_vcpu->arch.pkvm.host_vcpu = host_vcpu; + shadow_vcpu->kvm = vm->host_kvm; + shadow_vcpu->vcpu_id = host_vcpu->vcpu_id; + shadow_vcpu->vcpu_idx = vcpu_idx; - if (test_bit(KVM_ARM_VCPU_POWER_OFF, shadow_vcpu->arch.features)) { - shadow_vcpu->arch.pkvm.power_state = PSCI_0_2_AFFINITY_LEVEL_OFF; - } else if (pvm_has_pvmfw(vm)) { - if (vm->pvmfw_entry_vcpu) - return -EINVAL; + ret = copy_features(shadow_vcpu, host_vcpu); + if (ret) + goto done; - vm->pvmfw_entry_vcpu = shadow_vcpu; - shadow_vcpu->arch.reset_state.reset = true; - shadow_vcpu->arch.pkvm.power_state = PSCI_0_2_AFFINITY_LEVEL_ON_PENDING; - } else { - struct vcpu_reset_state *reset_state = &shadow_vcpu->arch.reset_state; + ret = init_ptrauth(shadow_vcpu); + if (ret) + goto done; - reset_state->pc = *vcpu_pc(host_vcpu); - reset_state->r0 = vcpu_get_reg(host_vcpu, 0); - reset_state->reset = true; - shadow_vcpu->arch.pkvm.power_state = PSCI_0_2_AFFINITY_LEVEL_ON_PENDING; + if (test_bit(KVM_ARM_VCPU_SVE, shadow_vcpu->arch.features)) { + size_t sve_state_size; + void *sve_state; + + shadow_vcpu->arch.sve_state = + READ_ONCE(host_vcpu->arch.sve_state); + shadow_vcpu->arch.sve_max_vl = + READ_ONCE(host_vcpu->arch.sve_max_vl); + + sve_state = kern_hyp_va(shadow_vcpu->arch.sve_state); + sve_state_size = vcpu_sve_state_size(shadow_vcpu); + + if (!shadow_vcpu->arch.sve_state || !sve_state_size || + hyp_pin_shared_mem(sve_state, sve_state + sve_state_size)) { + clear_bit(KVM_ARM_VCPU_SVE, shadow_vcpu->arch.features); + shadow_vcpu->arch.sve_state = NULL; + shadow_vcpu->arch.sve_max_vl = 0; + ret = -EINVAL; + goto done; } } - return 0; + if (vm->arch.pkvm.enabled) + pkvm_vcpu_init_traps(shadow_vcpu); + kvm_reset_pvm_sys_regs(shadow_vcpu); + + vm->vcpus[vcpu_idx] = shadow_vcpu; + shadow_state->vm = vm; + + shadow_vcpu->arch.hw_mmu = &vm->arch.mmu; + shadow_vcpu->arch.pkvm.shadow_vm = vm; + shadow_vcpu->arch.power_off = true; + + if (test_bit(KVM_ARM_VCPU_POWER_OFF, shadow_vcpu->arch.features)) { + shadow_vcpu->arch.pkvm.power_state = + PSCI_0_2_AFFINITY_LEVEL_OFF; + } else if (pvm_has_pvmfw(vm)) { + if (vm->pvmfw_entry_vcpu) { + ret = -EINVAL; + goto done; + } + + vm->pvmfw_entry_vcpu = shadow_vcpu; + shadow_vcpu->arch.reset_state.reset = true; + shadow_vcpu->arch.pkvm.power_state = + PSCI_0_2_AFFINITY_LEVEL_ON_PENDING; + } else { + struct vcpu_reset_state *reset_state = + &shadow_vcpu->arch.reset_state; + + reset_state->pc = *vcpu_pc(host_vcpu); + reset_state->r0 = vcpu_get_reg(host_vcpu, 0); + reset_state->reset = true; + shadow_vcpu->arch.pkvm.power_state = + PSCI_0_2_AFFINITY_LEVEL_ON_PENDING; + } + +done: + if (ret) + unpin_host_vcpu(shadow_state); + + return ret; } static bool __exists_shadow(struct kvm *host_kvm) @@ -578,7 +591,7 @@ static size_t pkvm_get_shadow_size(int num_vcpus) { /* Shadow space for the vm struct and all of its vcpu states. */ return sizeof(struct kvm_shadow_vm) + - sizeof(struct shadow_vcpu_state) * num_vcpus; + sizeof(struct shadow_vcpu_state *) * num_vcpus; } /* @@ -600,14 +613,14 @@ static int check_shadow_size(int nr_vcpus, size_t shadow_size) return 0; } -static void drain_shadow_vcpus(struct shadow_vcpu_state *shadow_vcpus, +static void drain_shadow_vcpus(struct shadow_vcpu_state *shadow_vcpus[], unsigned int nr_vcpus, struct kvm_hyp_memcache *mc) { int i; for (i = 0; i < nr_vcpus; i++) { - struct kvm_vcpu *shadow_vcpu = &shadow_vcpus[i].vcpu; + struct kvm_vcpu *shadow_vcpu = &shadow_vcpus[i]->vcpu; struct kvm_hyp_memcache *vcpu_mc = &shadow_vcpu->arch.pkvm_memcache; void *addr; @@ -632,8 +645,6 @@ static void drain_shadow_vcpus(struct shadow_vcpu_state *shadow_vcpus, * Must be a multiple of the page size. * pgd: The host va of the area being donated for the stage-2 PGD for the VM. * Must be page aligned. Its size is implied by the VM's VTCR. - * Note: An array to the host KVM VCPUs (host VA) is passed via the pgd, as to - * not to be dependent on how the VCPU's are layed out in struct kvm. * * Return a unique handle to the protected VM on success, * negative error code on failure. @@ -685,19 +696,13 @@ int __pkvm_init_shadow(struct kvm *kvm, if (ret) goto err_remove_mappings; - ret = set_host_vcpus(vm->shadow_vcpus, nr_vcpus, pgd, pgd_size); - if (ret) - goto err_remove_pgd; - - ret = init_shadow_structs(kvm, vm, pgd, nr_vcpus); - if (ret < 0) - goto err_unpin_host_vcpus; + init_shadow_vm(kvm, vm, nr_vcpus); /* Add the entry to the shadow table. */ hyp_spin_lock(&shadow_lock); ret = insert_shadow_table(kvm, vm, shadow_size); if (ret < 0) - goto err_unlock_unpin_host_vcpus; + goto err_unlock; ret = kvm_guest_prepare_stage2(vm, pgd); if (ret) @@ -708,34 +713,105 @@ int __pkvm_init_shadow(struct kvm *kvm, err_remove_shadow_table: remove_shadow_table(vm->shadow_handle); -err_unlock_unpin_host_vcpus: +err_unlock: hyp_spin_unlock(&shadow_lock); -err_unpin_host_vcpus: - unpin_host_vcpus(vm->shadow_vcpus, nr_vcpus); -err_remove_pgd: WARN_ON(__pkvm_hyp_donate_host(hyp_virt_to_pfn(pgd), nr_pgd_pages)); - err_remove_mappings: /* Clear the donated shadow memory on failure to avoid data leaks. */ memset(vm, 0, shadow_size); WARN_ON(__pkvm_hyp_donate_host(hyp_phys_to_pfn(shadow_pa), shadow_size >> PAGE_SHIFT)); - err: hyp_unpin_shared_mem(kvm, kvm + 1); return ret; } +/* + * Initialize the protected vcpu state shadow copy in host-donated memory. + * + * shadow_handle: The handle for the protected vm. + * host_vcpu: A pointer to the corresponding host vcpu (host va). + * shadow_vcpu_hva: The host va of the area being donated for the vcpu state. + * Must be page aligned. The size of the area must be equal to + * the paged-aligned size of kvm_shadow_vcpu_state. + * + * Return 0 on success, negative error code on failure. + */ +int __pkvm_init_shadow_vcpu(unsigned int shadow_handle, + struct kvm_vcpu *host_vcpu, + void *shadow_vcpu_hva) +{ + struct kvm_shadow_vm *vm; + struct shadow_vcpu_state *shadow_state = kern_hyp_va(shadow_vcpu_hva); + size_t vcpu_state_sz = sizeof(*shadow_state); + u64 nr_pages = PAGE_ALIGN(vcpu_state_sz) >> PAGE_SHIFT; + unsigned int idx; + int ret; + + if (!PAGE_ALIGNED(shadow_vcpu_hva)) + return -EINVAL; + + ret = __pkvm_host_donate_hyp(hyp_virt_to_pfn(shadow_state), + nr_pages); + if (ret) + return ret; + + memset(shadow_state, 0, vcpu_state_sz); + + hyp_spin_lock(&shadow_lock); + + vm = find_shadow_by_handle(shadow_handle); + if (!vm) { + ret = -ENOENT; + goto unlock; + } + + idx = vm->nr_vcpus; + if (idx >= vm->created_vcpus) { + ret = -EINVAL; + goto unlock; + } + + ret = init_shadow_vcpu(shadow_state, host_vcpu, vm, idx); + if (ret) + goto unlock; + + vm->shadow_vcpus[idx] = shadow_state; + vm->nr_vcpus++; +unlock: + hyp_spin_unlock(&shadow_lock); + + if (ret) { + memset(shadow_state, 0, vcpu_state_sz); + WARN_ON(__pkvm_hyp_donate_host(hyp_virt_to_pfn(shadow_state), + nr_pages)); + } + + return ret; +} + +static void teardown_donated_memory(struct kvm_hyp_memcache *mc, void *addr, + size_t size) +{ + u64 pfn = hyp_phys_to_pfn(__hyp_pa(addr)); + u64 nr_pages = size >> PAGE_SHIFT; + void *start; + + memset(addr, 0, size); + + for (start = addr; start < addr + size; start += PAGE_SIZE) + push_hyp_memcache(mc, start, hyp_virt_to_phys); + + WARN_ON(__pkvm_hyp_donate_host(pfn, nr_pages)); +} + int __pkvm_teardown_shadow(int shadow_handle) { struct kvm_hyp_memcache *mc; struct kvm_shadow_vm *vm; struct kvm *host_kvm; - size_t shadow_size; + unsigned int nr_vcpus; int err; - u64 pfn; - u64 nr_pages; - void *addr; int i; /* Lookup then remove entry from the shadow table. */ @@ -751,6 +827,9 @@ int __pkvm_teardown_shadow(int shadow_handle) goto err_unlock; } + host_kvm = vm->host_kvm; + nr_vcpus = vm->nr_vcpus; + /* * Clear the tracking for last_loaded_vcpu for all cpus for this vm in * case the same addresses for those vcpus are reused for future vms. @@ -770,22 +849,17 @@ int __pkvm_teardown_shadow(int shadow_handle) hyp_spin_unlock(&shadow_lock); /* Reclaim guest pages, and page-table pages */ - mc = &vm->host_kvm->arch.pkvm.teardown_mc; + mc = &host_kvm->arch.pkvm.teardown_mc; reclaim_guest_pages(vm, mc); - drain_shadow_vcpus(vm->shadow_vcpus, vm->created_vcpus, mc); - unpin_host_vcpus(vm->shadow_vcpus, vm->created_vcpus); + drain_shadow_vcpus(vm->shadow_vcpus, nr_vcpus, mc); + unpin_host_vcpus(vm->shadow_vcpus, nr_vcpus); - /* Push the metadata pages to the teardown memcache */ - shadow_size = vm->shadow_area_size; - host_kvm = vm->host_kvm; - memset(vm, 0, shadow_size); - for (addr = vm; addr < ((void *)vm + shadow_size); addr += PAGE_SIZE) - push_hyp_memcache(mc, addr, hyp_virt_to_phys); - hyp_unpin_shared_mem(host_kvm, host_kvm + 1); + for (i = 0; i < nr_vcpus; i++) + teardown_donated_memory(mc, vm->shadow_vcpus[i], + PAGE_ALIGN(sizeof(vm->shadow_vcpus[i]))); + teardown_donated_memory(mc, vm, vm->shadow_area_size); - pfn = hyp_phys_to_pfn(__hyp_pa(vm)); - nr_pages = shadow_size >> PAGE_SHIFT; - WARN_ON(__pkvm_hyp_donate_host(pfn, nr_pages)); + hyp_unpin_shared_mem(host_kvm, host_kvm + 1); return 0; err_unlock: @@ -851,14 +925,7 @@ void pkvm_reset_vcpu(struct kvm_vcpu *vcpu) WARN_ON(!reset_state->reset); - if (test_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, vcpu->arch.features) || - test_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, vcpu->arch.features)) { - /* - * This call should not fail since we've already checked for - * feature support on initialization. - */ - WARN_ON(kvm_vcpu_enable_ptrauth(vcpu)); - } + init_ptrauth(vcpu); /* Reset core registers */ memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); @@ -913,7 +980,7 @@ struct kvm_vcpu *pvm_mpidr_to_vcpu(struct kvm_shadow_vm *vm, unsigned long mpidr mpidr &= MPIDR_HWID_BITMASK; - for (i = 0; i < vm->created_vcpus; i++) { + for (i = 0; i < READ_ONCE(vm->nr_vcpus); i++) { vcpu = vm->vcpus[i]; if (mpidr == kvm_vcpu_get_mpidr_aff(vcpu)) @@ -1030,7 +1097,7 @@ static bool pvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu) * then if at least one is PENDING_ON then return PENDING_ON. * Otherwise, return OFF. */ - for (i = 0; i < vm->created_vcpus; i++) { + for (i = 0; i < READ_ONCE(vm->nr_vcpus); i++) { tmp = vm->vcpus[i]; mpidr = kvm_vcpu_get_mpidr_aff(tmp); @@ -1240,7 +1307,7 @@ static bool pkvm_memunshare_call(struct kvm_vcpu *vcpu) static bool pkvm_install_ioguard_page(struct kvm_vcpu *vcpu, u64 *exit_code) { - u32 retval = SMCCC_RET_SUCCESS; + u64 retval = SMCCC_RET_SUCCESS; u64 ipa = smccc_get_arg1(vcpu); int ret; @@ -1332,6 +1399,8 @@ bool kvm_handle_pvm_hvc64(struct kvm_vcpu *vcpu, u64 *exit_code) return pkvm_install_ioguard_page(vcpu, exit_code); case ARM_SMCCC_VENDOR_HYP_KVM_MMIO_GUARD_UNMAP_FUNC_ID: if (__pkvm_remove_ioguard_page(vcpu, vcpu_get_reg(vcpu, 1))) + val[0] = SMCCC_RET_INVALID_PARAMETER; + else val[0] = SMCCC_RET_SUCCESS; break; case ARM_SMCCC_VENDOR_HYP_KVM_MMIO_GUARD_INFO_FUNC_ID: diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c index f7f6b08dd371..e335c9b2c00a 100644 --- a/arch/arm64/kvm/pkvm.c +++ b/arch/arm64/kvm/pkvm.c @@ -120,8 +120,8 @@ void __init kvm_hyp_reserve(void) */ static int __create_el2_shadow(struct kvm *kvm) { - struct kvm_vcpu *vcpu, **vcpu_array; - size_t pgd_sz, shadow_sz; + struct kvm_vcpu *vcpu; + size_t pgd_sz, shadow_sz, vcpu_state_sz; void *pgd, *shadow_addr; unsigned long idx; int shadow_handle; @@ -140,21 +140,15 @@ static int __create_el2_shadow(struct kvm *kvm) if (!pgd) return -ENOMEM; - /* Allocate memory to donate to hyp for the kvm and vcpu state. */ + /* Allocate memory to donate to hyp for the kvm and vcpu state pointers. */ shadow_sz = PAGE_ALIGN(KVM_SHADOW_VM_SIZE + - SHADOW_VCPU_STATE_SIZE * kvm->created_vcpus); + sizeof(void *) * kvm->created_vcpus); shadow_addr = alloc_pages_exact(shadow_sz, GFP_KERNEL_ACCOUNT); if (!shadow_addr) { ret = -ENOMEM; goto free_pgd; } - /* Stash the vcpu pointers into the PGD */ - BUILD_BUG_ON(KVM_MAX_VCPUS > (PAGE_SIZE / sizeof(u64))); - vcpu_array = pgd; - kvm_for_each_vcpu(idx, vcpu, kvm) - vcpu_array[idx] = vcpu; - /* Donate the shadow memory to hyp and let hyp initialize it. */ ret = kvm_call_hyp_nvhe(__pkvm_init_shadow, kvm, shadow_addr, shadow_sz, pgd); @@ -166,8 +160,35 @@ static int __create_el2_shadow(struct kvm *kvm) /* Store the shadow handle given by hyp for future call reference. */ kvm->arch.pkvm.shadow_handle = shadow_handle; + /* Donate memory for the vcpu state at hyp and initialize it. */ + vcpu_state_sz = PAGE_ALIGN(SHADOW_VCPU_STATE_SIZE); + kvm_for_each_vcpu (idx, vcpu, kvm) { + void *vcpu_state; + + /* Indexing of the vcpus to be sequential starting at 0. */ + if (WARN_ON(vcpu->vcpu_idx != idx)) { + ret = -EINVAL; + goto destroy_vm; + } + vcpu_state = alloc_pages_exact(vcpu_state_sz, GFP_KERNEL_ACCOUNT); + if (!vcpu_state) { + ret = -ENOMEM; + goto destroy_vm; + } + + ret = kvm_call_hyp_nvhe(__pkvm_init_shadow_vcpu, shadow_handle, + vcpu, vcpu_state); + if (ret) { + free_pages_exact(vcpu_state, vcpu_state_sz); + goto destroy_vm; + } + } + return 0; +destroy_vm: + kvm_shadow_destroy(kvm); + return ret; free_shadow: free_pages_exact(shadow_addr, shadow_sz); free_pgd: diff --git a/block/Makefile b/block/Makefile index af3d044abaf1..05daaf8282a1 100644 --- a/block/Makefile +++ b/block/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_BLK_SED_OPAL) += sed-opal.o obj-$(CONFIG_BLK_PM) += blk-pm.o obj-$(CONFIG_BLK_INLINE_ENCRYPTION) += keyslot-manager.o blk-crypto.o obj-$(CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK) += blk-crypto-fallback.o +obj-$(CONFIG_ANDROID_VENDOR_HOOKS) += vendor_hooks.o diff --git a/block/vendor_hooks.c b/block/vendor_hooks.c new file mode 100644 index 000000000000..db033b9e2835 --- /dev/null +++ b/block/vendor_hooks.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* vendor_hook.c + * + * Copyright 2022 Google LLC + */ +#include "blk.h" +#include "blk-mq-tag.h" +#include "blk-mq.h" +#include + +#define CREATE_TRACE_POINTS +#include +#include +#include + +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_blk_alloc_rqs); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_blk_rq_ctx_init); + +/* + * For type visibility + */ +const struct blk_mq_alloc_data *GKI_struct_blk_mq_alloc_data; +EXPORT_SYMBOL_GPL(GKI_struct_blk_mq_alloc_data); + diff --git a/build.config.cloudripper b/build.config.cloudripper new file mode 100644 index 000000000000..f16fba404826 --- /dev/null +++ b/build.config.cloudripper @@ -0,0 +1,56 @@ +DEFCONFIG=cloudripper_gki_defconfig +GKI_FRAGMENT_DEFCONFIG=${KERNEL_DIR}/arch/arm64/configs/cloudripper_gki.fragment + +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.gs101 + +# Set BUILD_VENDOR_KERNEL_BOOT to 1 to build vendor_kernel_boot and remove vendor_boot +# artifacts and arguments since we don't need to update vendor_boot anymore. +BUILD_VENDOR_BOOT_IMG="" +BUILD_VENDOR_KERNEL_BOOT=1 +KERNEL_VENDOR_CMDLINE="" +VENDOR_BOOTCONFIG="" +INITRAMFS_VENDOR_RAMDISK_FRAGMENT_NAME="" +VENDOR_RAMDISK_BINARY="" +GKI_RAMDISK_PREBUILT_BINARY="" + +MAKE_GOALS="$MAKE_GOALS +modules +google/gs201-a0.dtb +google/gs201-b0.dtb +google/dtbo.img +google/gs201-dpm-eng.dtbo +google/gs201-dpm-user.dtbo +google/gs201-dpm-userdebug.dtbo +" + +FILES=" +arch/arm64/boot/dts/google/gs201-a0.dtb +arch/arm64/boot/dts/google/gs201-b0.dtb +arch/arm64/boot/dts/google/dtbo.img +arch/arm64/boot/dts/google/gs201-dpm-eng.dtbo +arch/arm64/boot/dts/google/gs201-dpm-user.dtbo +arch/arm64/boot/dts/google/gs201-dpm-userdebug.dtbo +" + +if [ -z "$MIXED_BUILD" ]; then +FILES="$FILES +$DEVICE_KERNEL_FILES +" +fi + +# Concatenate vendor_kernel_boot_modules.gs201 (platform common) and vendor_kernel_boot_modules.cloudripper (device specified) into one file +POST_KERNEL_BUILD_CMDS="concat_vendor_boot_modules" +function concat_vendor_boot_modules() { + cat ${KERNEL_DIR}/vendor_kernel_boot_modules.gs201 \ + ${KERNEL_DIR}/vendor_kernel_boot_modules.cloudripper > \ + ${OUT_DIR}/vendor_kernel_boot_modules.concat + MODULES_LIST=${OUT_DIR}/vendor_kernel_boot_modules.concat +} + +VENDOR_DLKM_MODULES_BLOCKLIST=${KERNEL_DIR}/vendor_dlkm.blocklist.cloudripper + +EXT_MODULES_MAKEFILE=${KERNEL_DIR}/Makefile.ext_modules.cloudripper +# Explicitly clear EXT_MODULES because build.config.gs101 might set it to +# "private/google-modules/uwb/kernel" which we don't want because uwb/kernel is +# already built by Makefile.ext_modules.cloudripper +EXT_MODULES="" diff --git a/build.config.common b/build.config.common index c79b701ad9f5..b675fb0fccce 100644 --- a/build.config.common +++ b/build.config.common @@ -1,6 +1,6 @@ . ${ROOT_DIR}/${KERNEL_DIR}/build.config.constants -BRANCH=android13-gs-pixel-5.10-gs101 +BRANCH=android13-gs-pixel-5.10 KMI_GENERATION=4 LLVM=1 diff --git a/build.config.gki.aarch64 b/build.config.gki.aarch64 index 8914faa432a0..02fd62db16e9 100644 --- a/build.config.gki.aarch64 +++ b/build.config.gki.aarch64 @@ -9,17 +9,19 @@ Image.lz4 Image.gz " +# Sync with BUILD.bazel ABI_DEFINITION=android/abi_gki_aarch64.xml -# Update BUILD.bazel, define_common_kernels() if the list differs from -# android/abi_gki_aarch64* in the filesystem. KMI_SYMBOL_LIST=android/abi_gki_aarch64 ADDITIONAL_KMI_SYMBOL_LISTS=" +android/abi_gki_aarch64_type_visibility android/abi_gki_aarch64_core +android/abi_gki_aarch64_exynos android/abi_gki_aarch64_fips140 android/abi_gki_aarch64_generic android/abi_gki_aarch64_virtual_device android/abi_gki_aarch64_db845c android/abi_gki_aarch64_hikey960 +android/abi_gki_aarch64_rockchip " FILES="${FILES} diff --git a/build.config.gki.x86_64 b/build.config.gki.x86_64 index 7ecd1dfe7dcb..3d81fea6aacb 100644 --- a/build.config.gki.x86_64 +++ b/build.config.gki.x86_64 @@ -5,5 +5,7 @@ BUILD_SYSTEM_DLKM=1 MODULES_LIST=${ROOT_DIR}/${KERNEL_DIR}/android/gki_system_dlkm_modules +BUILD_GKI_CERTIFICATION_TOOLS=1 + BUILD_GKI_ARTIFACTS=1 BUILD_GKI_BOOT_IMG_SIZE=67108864 diff --git a/build.config.gs101 b/build.config.gs101 index 60f0d1e5fe7c..8cae2069e1ca 100644 --- a/build.config.gs101 +++ b/build.config.gs101 @@ -37,11 +37,14 @@ ABI_DEFINITION=android/abi_gki_aarch64_generic.xml TIDY_ABI=1 KMI_SYMBOL_LIST=android/abi_gki_aarch64_generic ADDITIONAL_KMI_SYMBOL_LISTS=" +android/abi_gki_aarch64_type_visibility android/abi_gki_aarch64_core +android/abi_gki_aarch64_exynos android/abi_gki_aarch64_fips140 android/abi_gki_aarch64_virtual_device android/abi_gki_aarch64_db845c android/abi_gki_aarch64_hikey960 +android/abi_gki_aarch64_rockchip " TRIM_NONLISTED_KMI=${TRIM_NONLISTED_KMI:-1} KMI_SYMBOL_LIST_ADD_ONLY=1 @@ -53,6 +56,7 @@ BUILD_INITRAMFS=1 INITRAMFS_VENDOR_RAMDISK_FRAGMENT_NAME=dlkm LZ4_RAMDISK=1 BOOT_IMAGE_HEADER_VERSION=4 +TRIM_UNUSED_MODULES=1 VENDOR_DLKM_MODULES_LIST=${KERNEL_DIR}/vendor_dlkm_modules.slider VENDOR_DLKM_MODULES_BLOCKLIST=${KERNEL_DIR}/vendor_dlkm.blocklist.slider VENDOR_DLKM_PROPS=${KERNEL_DIR}/vendor_dlkm.props.slider diff --git a/build.config.gs201_emulator b/build.config.gs201_emulator new file mode 100644 index 000000000000..5f9347d4d6d5 --- /dev/null +++ b/build.config.gs201_emulator @@ -0,0 +1,61 @@ +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.aarch64 + +DEFCONFIG=gs201_emulator_defconfig +PRE_DEFCONFIG_CMDS="KCONFIG_CONFIG=${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/${DEFCONFIG} ${ROOT_DIR}/${KERNEL_DIR}/scripts/kconfig/merge_config.sh -m -r ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/gki_defconfig ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/gs201_emulator.fragment" +POST_DEFCONFIG_CMDS="rm ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/${DEFCONFIG}" + +LIBUFDT_PREBUILTS_BIN=prebuilts/misc/linux-x86/libufdt +DTC_OVERLAY_TEST_EXT=${ROOT_DIR}/prebuilts/kernel-build-tools/linux-x86/bin/ufdt_apply_overlay + +DIST_DIR=${ROOT_DIR}/out/mixed/dist +DIST_CMDS="${LIBUFDT_PREBUILTS_BIN}/ufdt_apply_overlay ${DIST_DIR}/gs201-a0.dtb ${DIST_DIR}/gs201-emulator.dtbo ${DIST_DIR}/gs201-out.dtb" + +KERNEL_BINARY=Image + +MAKE_GOALS=" +${KERNEL_BINARY} +modules +google/gs201-a0.dtb +google/gs201-emulator.dtbo +" + +FILES=" +arch/arm64/boot/dts/google/gs201-a0.dtb +arch/arm64/boot/dts/google/gs201-emulator.dtbo +" + +if [ -z "$MIXED_BUILD" ]; then +FILES="$FILES +.config +vmlinux +System.map +arch/arm64/boot/${KERNEL_BINARY} +" +fi + +ABI_DEFINITION=android/abi_gki_aarch64_common.xml +FULL_GKI_ABI=1 +GKI_MODULES_LIST=android/gki_aarch64_modules +KMI_ENFORCED=1 +KMI_SYMBOL_LIST=android/abi_gki_aarch64_common +KMI_SYMBOL_LIST_MODULE_GROUPING=0 + +DO_NOT_STRIP_MODULES= +BUILD_INITRAMFS=1 +LZ4_RAMDISK=1 +BUILD_BOOT_IMG=1 +GKI_RAMDISK_PREBUILT_BINARY=${ROOT_DIR}/prebuilts/boot-artifacts/ramdisks/ramdisk-slider.img +KERNEL_VENDOR_CMDLINE="androidboot.selinux=permissive androidboot.boot_devices=14700000.ufs buildvariant=userdebug" +VENDOR_FSTAB=${ROOT_DIR}/prebuilts/boot-artifacts/fstabs/fstab.gs101 + +EXT_MODULES="" + +if [ -z "${FAST_BUILD}" ]; then +COMPRESS_UNSTRIPPED_MODULES=1 +UNSTRIPPED_MODULES="" +fi + +if [ -n "${GKI_DEFCONFIG_FRAGMENT}" ]; then +source ${GKI_DEFCONFIG_FRAGMENT} +fi diff --git a/build.config.gs201_hybrid b/build.config.gs201_hybrid new file mode 100644 index 000000000000..de75c6aac69e --- /dev/null +++ b/build.config.gs201_hybrid @@ -0,0 +1,61 @@ +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.aarch64 + +DEFCONFIG=gs201_hybrid_defconfig +PRE_DEFCONFIG_CMDS="KCONFIG_CONFIG=${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/${DEFCONFIG} ${ROOT_DIR}/${KERNEL_DIR}/scripts/kconfig/merge_config.sh -m -r ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/gki_defconfig ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/gs201_hybrid.fragment" +POST_DEFCONFIG_CMDS="rm ${ROOT_DIR}/${KERNEL_DIR}/arch/arm64/configs/${DEFCONFIG}" + +LIBUFDT_PREBUILTS_BIN=prebuilts/misc/linux-x86/libufdt +DTC_OVERLAY_TEST_EXT=${ROOT_DIR}/prebuilts/kernel-build-tools/linux-x86/bin/ufdt_apply_overlay + +DIST_DIR=${ROOT_DIR}/out/mixed/dist +DIST_CMDS="${LIBUFDT_PREBUILTS_BIN}/ufdt_apply_overlay ${DIST_DIR}/gs201-a0.dtb ${DIST_DIR}/gs201-hybrid.dtbo ${DIST_DIR}/gs201-out.dtb" + +KERNEL_BINARY=Image + +MAKE_GOALS=" +${KERNEL_BINARY} +modules +google/gs201-a0.dtb +google/gs201-hybrid.dtbo +" + +FILES=" +arch/arm64/boot/dts/google/gs201-a0.dtb +arch/arm64/boot/dts/google/gs201-hybrid.dtbo +" + +if [ -z "$MIXED_BUILD" ]; then +FILES="$FILES +.config +vmlinux +System.map +arch/arm64/boot/${KERNEL_BINARY} +" +fi + +ABI_DEFINITION=android/abi_gki_aarch64_common.xml +FULL_GKI_ABI=1 +GKI_MODULES_LIST=android/gki_aarch64_modules +KMI_ENFORCED=1 +KMI_SYMBOL_LIST=android/abi_gki_aarch64_common +KMI_SYMBOL_LIST_MODULE_GROUPING=0 + +DO_NOT_STRIP_MODULES= +BUILD_INITRAMFS=1 +LZ4_RAMDISK=1 +BUILD_BOOT_IMG=1 +GKI_RAMDISK_PREBUILT_BINARY=${ROOT_DIR}/prebuilts/boot-artifacts/ramdisks/ramdisk-slider.img +KERNEL_VENDOR_CMDLINE="androidboot.selinux=permissive androidboot.boot_devices=14700000.ufs buildvariant=userdebug" +VENDOR_FSTAB=${ROOT_DIR}/prebuilts/boot-artifacts/fstabs/fstab.gs101 + +EXT_MODULES="" + +if [ -z "${FAST_BUILD}" ]; then +COMPRESS_UNSTRIPPED_MODULES=1 +UNSTRIPPED_MODULES="" +fi + +if [ -n "${GKI_DEFCONFIG_FRAGMENT}" ]; then +source ${GKI_DEFCONFIG_FRAGMENT} +fi diff --git a/build.config.rockchip b/build.config.rockchip new file mode 100644 index 000000000000..297c4c95a14b --- /dev/null +++ b/build.config.rockchip @@ -0,0 +1,8 @@ +. ${ROOT_DIR}/${KERNEL_DIR}/build.config.gki.aarch64 + + +DEFCONFIG=rockchip_aarch64_gki_defconfig +KMI_SYMBOL_LIST=android/abi_gki_aarch64_rockchip +PRE_DEFCONFIG_CMDS="KCONFIG_CONFIG=${ROOT_DIR}/common/arch/arm64/configs/${DEFCONFIG} ${ROOT_DIR}/common/scripts/kconfig/merge_config.sh -m -r ${ROOT_DIR}/common/arch/arm64/configs/gki_defconfig ${ROOT_DIR}/common/arch/arm64/configs/rockchip_gki.fragment" +POST_DEFCONFIG_CMDS="rm ${ROOT_DIR}/common/arch/arm64/configs/${DEFCONFIG}" + diff --git a/build.config.slider.kasan b/build.config.slider.kasan index 911bf262bb66..961a175237d1 100644 --- a/build.config.slider.kasan +++ b/build.config.slider.kasan @@ -11,6 +11,7 @@ function update_kasan_config() { -e CONFIG_KCOV \ -e CONFIG_DEBUG_INFO \ -d CONFIG_RANDOMIZE_BASE \ + -d CONFIG_SCSI_UFS_PIXEL_FIPS140 \ --set-val CONFIG_FRAME_WARN 0 (cd ${OUT_DIR} && \ make O=${OUT_DIR} "${TOOL_ARGS[@]}" ${MAKE_ARGS} olddefconfig) diff --git a/build.config.slider.khwasan b/build.config.slider.khwasan index 2a07c8ad4891..c0706eea1a08 100644 --- a/build.config.slider.khwasan +++ b/build.config.slider.khwasan @@ -11,6 +11,7 @@ function update_khwasan_config() { -e CONFIG_KCOV \ -e CONFIG_DEBUG_INFO \ -d CONFIG_RANDOMIZE_BASE \ + -d CONFIG_SCSI_UFS_PIXEL_FIPS140 \ --set-val CONFIG_FRAME_WARN 0 (cd ${OUT_DIR} && \ make O=${OUT_DIR} "${TOOL_ARGS[@]}" ${MAKE_ARGS} olddefconfig) diff --git a/build_cloudripper.sh b/build_cloudripper.sh new file mode 100755 index 000000000000..4f7b367d856b --- /dev/null +++ b/build_cloudripper.sh @@ -0,0 +1,4 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +DEVICE_KERNEL_BUILD_CONFIG=private/gs-google/build.config.cloudripper \ +private/gs-google/build_slider.sh "$@" diff --git a/build_gs201_zebu.sh b/build_gs201_zebu.sh new file mode 100755 index 000000000000..676f534e11b2 --- /dev/null +++ b/build_gs201_zebu.sh @@ -0,0 +1,48 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 + +if [ -n "${BUILD_CONFIG}" ]; then + echo "ERROR: setting BUILD_CONFIG is not supported for $0" >&2 + echo "usage: $0" + echo + echo "See build.sh for supported configs." + exit 1 +fi + +export MIXED_BUILD=1 +export SKIP_RM_DIST_DIR=1 + +BASE_OUT=${OUT_DIR:-out}/mixed/ +export OUT_DIR + +# share a common DIST_DIR +export DIST_DIR=${DIST_DIR:-${BASE_OUT}/dist/} + +OUT_DIR=${BASE_OUT}/android13-5.10-staging/ +# Now build the GKI kernel +SKIP_CP_KERNEL_HDR=1 \ + BUILD_CONFIG=common/build.config.gki.aarch64 \ + build/build.sh KCFLAGS=-Werror "$@" +error_code=$? +if [ $error_code -ne 0 ]; then + echo "ERROR: Failed to compile android13-5.10-staging. (ret=$error_code)" >&2 + exit "$error_code" +fi + +OUT_DIR=${BASE_OUT}/device-kernel/ +# build the zebu Kernel +BUILD_CONFIG=private/gs-google/build.config.gs201_hybrid \ + build/build.sh KCFLAGS=-Werror "$@" + +export UNPACK_BOOTIMG_PATH="tools/mkbootimg/unpack_bootimg.py" + +mkdir -p "${DIST_DIR}/zebu/" +python "$UNPACK_BOOTIMG_PATH" --boot_img "${DIST_DIR}/boot.img" --out "${DIST_DIR}/ext_bootimg" +python "$UNPACK_BOOTIMG_PATH" --boot_img "${DIST_DIR}/vendor_boot.img" --out "${DIST_DIR}/ext_vendor_bootimg" +cat "${DIST_DIR}/ext_vendor_bootimg/vendor_ramdisk" "${DIST_DIR}/ext_bootimg/ramdisk" > \ + "${DIST_DIR}/zebu/buildroot_v201105_r03_ttySAC0_debug.cramfs" +#cp -v "${DIST_DIR}/ext_bootimg/kernel" "${DIST_DIR}/zebu/Image" +cp -v "${OUT_DIR}/private/gs-google/arch/arm64/boot/Image" "${DIST_DIR}/zebu/Image" +#cp -v "${DIST_DIR}/ext_vendor_bootimg/dtb" "${DIST_DIR}/zebu/devicetree.dtb" +cp -v "${DIST_DIR}/gs201-out.dtb" "${DIST_DIR}/zebu/exynos9855-emulator9855.dtb" + diff --git a/build_slider.sh b/build_slider.sh index 33d3160c1d95..af9b6255580e 100755 --- a/build_slider.sh +++ b/build_slider.sh @@ -8,7 +8,7 @@ function exit_if_error { fi } -EXPERIMENTAL_BUILD=${EXPERIMENTAL_BUILD:-0} +BUILD_STAGING_KERNEL=0 TRIM_NONLISTED_KMI=${TRIM_NONLISTED_KMI:-1} LTO=${LTO:-thin} KMI_SYMBOL_LIST_STRICT_MODE=0 @@ -18,16 +18,16 @@ GKI_KERNEL_PREBUILTS_DIR= GKI_KERNEL_BUILD_CONFIG= GKI_KERNEL_OUT_DIR= CHECK_DIRTY_AOSP=0 -BUILD_KERNEL=1 +MAKE_CORE_KERNEL=1 -if [ "${BUILD_KERNEL}" = "0" ]; then +if [ "${MAKE_CORE_KERNEL}" = "0" ]; then USING_PREBUILTS=1 GKI_KERNEL_PREBUILTS_DIR=$(readlink -m "prebuilts/boot-artifacts/kernel/") else USING_PREBUILTS= - if [ "${EXPERIMENTAL_BUILD}" != "0" ]; then - GKI_KERNEL_OUT_DIR=android13-5.10-staging - GKI_KERNEL_BUILD_CONFIG=common/build.config.gki.aarch64 + if [ "${BUILD_STAGING_KERNEL}" = "1" ]; then + GKI_KERNEL_OUT_DIR=android13-5.10-pixel-staging + GKI_KERNEL_BUILD_CONFIG=aosp-staging/build.config.gki.aarch64 else GKI_KERNEL_OUT_DIR=android13-5.10 GKI_KERNEL_BUILD_CONFIG=aosp/build.config.gki.aarch64 @@ -45,17 +45,15 @@ if [ -n "${BUILD_ABI}" ]; then exit_if_error 1 "BUILD_ABI is deprecated" fi -if [ "${BUILD_KERNEL}" = "0" ]; then +if [ "${MAKE_CORE_KERNEL}" = "0" ]; then if [ "${LTO}" = "none" ]; then - echo "LTO=none requires BUILD_KERNEL=1, EXPERIMENTAL_BUILD=1, or" + echo "LTO=none requires BUILD_AOSP_KERNEL=1, BUILD_STAGING_KERNEL=1, or" echo " GKI_DEFCONFIG_FRAGMENT to be set." exit_if_error 1 "LTO=none requires building the kernel" - elif [ -n "${GKI_DEFCONFIG_FRAGMENT}" -o \ - "${EXPERIMENTAL_BUILD}" != "0" ]; then - echo "BUILD_KERNEL=0 is incompatible with EXPERIMENTAL_BUILD and" - echo " GKI_DEFCONFIG_FRAGMENT." - exit_if_error 1 "Flags incompatible with BUILD_KERNEL detected" fi +elif [ "${BUILD_AOSP_KERNEL}" = "1" -a "${BUILD_STAGING_KERNEL}" = "1" ]; then + echo "BUILD_AOSP_KERNEL=1 is incompatible with BUILD_STAGING_KERNEL." + exit_if_error 1 "Flags incompatible with BUILD_AOSP_KERNEL detected" fi # These are for build.sh, so they should be exported. @@ -81,8 +79,8 @@ else SHA_FILE=boot.img fi -# If BUILD_KERNEL is not explicitly set, be sure that there are no aosp/ -# changes not present in the prebuilt. +# If BUILD_AOSP_KERNEL and BUILD_STAGING_KERNEL is not explicitly set, +# be sure that there are no aosp/ changes not present in the prebuilt. if [ "${CHECK_DIRTY_AOSP}" != "0" ]; then PREBUILTS_SHA=$(strings ${GKI_KERNEL_PREBUILTS_DIR}/${SHA_FILE} | grep "Linux version 5.10" | @@ -94,12 +92,13 @@ if [ "${CHECK_DIRTY_AOSP}" != "0" ]; then "$(git --no-optional-locks status -uno --porcelain || git diff-index --name-only HEAD)" ]; then echo "WARNING: There are aosp/ changes which are not in the prebuilts." - echo " Because you did not specify BUILD_KERNEL=0 or 1, $0" - echo " defaulted to building with the prebuilts. Please be aware that" - echo " your changes to aosp/ will not be present in the final images. If" - echo " you have made changes to aosp/, it is recommended to explicitly" - echo " set BUILD_KERNEL=0 if you wish to use the prebuilts, or to 1 if" - echo " you wish to build any local changes you may have." + echo " Because you did not specify BUILD_AOSP_KERNEL/BUILD_STAGING_KERNEL=0" + echo " or 1, $0 defaulted to building with" + echo " the prebuilts. Please be aware that your changes to aosp/ will not" + echo " be present in the final images. If you have made changes to aosp/," + echo " it is recommended to explicitly set BUILD_AOSP_KERNEL/BUILD_STAGING_KERNEL=0" + echo " if you wish to use the prebuilts, or to 1 if you wish to build any" + echo " local changes you may have." fi popd > /dev/null fi diff --git a/crypto/jitterentropy.c b/crypto/jitterentropy.c index 37c4c308339e..423c55d0e165 100644 --- a/crypto/jitterentropy.c +++ b/crypto/jitterentropy.c @@ -117,6 +117,22 @@ struct rand_data { #define JENT_EHEALTH 9 /* Health test failed during initialization */ #define JENT_ERCT 10 /* RCT failed during initialization */ +/* + * The output n bits can receive more than n bits of min entropy, of course, + * but the fixed output of the conditioning function can only asymptotically + * approach the output size bits of min entropy, not attain that bound. Random + * maps will tend to have output collisions, which reduces the creditable + * output entropy (that is what SP 800-90B Section 3.1.5.1.2 attempts to bound). + * + * The value "64" is justified in Appendix A.4 of the current 90C draft, + * and aligns with NIST's in "epsilon" definition in this document, which is + * that a string can be considered "full entropy" if you can bound the min + * entropy in each bit of output to at least 1-epsilon, where epsilon is + * required to be <= 2^(-32). + */ +#define JENT_ENTROPY_SAFETY_FACTOR 64 + +#include #include "jitterentropy.h" /*************************************************************************** @@ -546,7 +562,10 @@ static int jent_measure_jitter(struct rand_data *ec) */ static void jent_gen_entropy(struct rand_data *ec) { - unsigned int k = 0; + unsigned int k = 0, safety_factor = 0; + + if (fips_enabled) + safety_factor = JENT_ENTROPY_SAFETY_FACTOR; /* priming of the ->prev_time value */ jent_measure_jitter(ec); @@ -560,7 +579,7 @@ static void jent_gen_entropy(struct rand_data *ec) * We multiply the loop value with ->osr to obtain the * oversampling rate requested by the caller */ - if (++k >= (DATA_SIZE_BITS * ec->osr)) + if (++k >= ((DATA_SIZE_BITS + safety_factor) * ec->osr)) break; } } diff --git a/download_gki.sh b/download_gki.sh index d66a22423557..9447a7d13e50 100755 --- a/download_gki.sh +++ b/download_gki.sh @@ -16,15 +16,16 @@ GKI_FILES=( vmlinux.symvers modules.builtin modules.builtin.modinfo - boot-5.10-lz4.img + boot-lz4.img + Image.lz4 ) GKI_PREBUILTS_DIR=${2:-${CUR_DIR}/prebuilts/boot-artifacts/kernel/} GKI_BUILD=$1 ALLOW_PREBUILTS_MISMATCH=${ALLOW_PREBUILTS_MISMATCH:-0} USE_UNSIGNED_USER_IMG=${USE_UNSIGNED_USER_IMG:-0} -BASE_TARGET="gki_arm64" +BASE_TARGET="kernel_aarch64" FETCH_ARTIFACT_CMD="/google/data/ro/projects/android/fetch_artifact" -IMG_ZIP_BASE="${BASE_TARGET}-img-${GKI_BUILD}" +IMG_TAR_FILE="certified-boot-img-${GKI_BUILD}.tar.gz" if [ -z "${GKI_BUILD}" ]; then echo "No GKI build number provided." @@ -37,55 +38,34 @@ TEMP_DIR=$(mktemp -d) cd ${TEMP_DIR} echo "Downloading GKI binaries from build ab/${GKI_BUILD} via fetch_artifact..." if [ "${USE_UNSIGNED_USER_IMG}" = "0" ]; then - file="signed/signed-${IMG_ZIP_BASE}.zip" - echo "Taking signed user image." -else - file="${IMG_ZIP_BASE}.zip" - echo "Taking unsigned user image." + file="signed/${IMG_TAR_FILE}" + echo "Downloading signed boot.img..." + ${FETCH_ARTIFACT_CMD} \ + --bid ${GKI_BUILD} \ + --target ${BASE_TARGET} ${file} + exit_and_clean_if_error $? "Unable to download signed boot image" fi -echo "Downloading -user variant boot.img..." -${FETCH_ARTIFACT_CMD} \ - --bid ${GKI_BUILD} \ - --target ${BASE_TARGET}-user ${file} -exit_and_clean_if_error $? "Unable to download -user boot image" -mv *${IMG_ZIP_BASE}.zip ${IMG_ZIP_BASE}-user.zip -echo "Downloading -userdebug prebuilts..." +echo "Downloading prebuilts..." for file in "${GKI_FILES[@]}"; do if grep -q "boot.*\.img" <<< ${file} ; then BOOT_IMG_NAME=${file} - file="${IMG_ZIP_BASE}.zip" - else - file="kernel/5.10/${file}" fi ${FETCH_ARTIFACT_CMD} \ --bid ${GKI_BUILD} \ - --target ${BASE_TARGET}-userdebug ${file} + --target ${BASE_TARGET} ${file} exit_and_clean_if_error $? "Error downloading ${file}" done -for file in $(ls ./*.zip); do - if grep -q "user" <<< ${file} ; then - USER_IMG_DIR=${TEMP_DIR}/user_images/ - mkdir ${USER_IMG_DIR} - unzip ${file} ${BOOT_IMG_NAME} -d ${USER_IMG_DIR} - else - unzip ${file} ${BOOT_IMG_NAME} - fi -done +if [ "${USE_UNSIGNED_USER_IMG}" = "0" ]; then + tar -zxvf ${IMG_TAR_FILE} + exit_and_clean_if_error $? "Failed to extract ${IMG_TAR_FILE}" +fi -if [ -f "${BOOT_IMG_NAME}" ]; then - UNPACKED_BOOT_DIR=${TEMP_DIR}/boot_img_unpacked/ - ${CUR_DIR}/tools/mkbootimg/unpack_bootimg.py --boot_img ${BOOT_IMG_NAME} \ - --out ${UNPACKED_BOOT_DIR} - exit_and_clean_if_error $? "Unable to unpack ${BOOT_IMG_NAME}" - mv ${UNPACKED_BOOT_DIR}/kernel ./Image.lz4 - lz4 -d ./Image.lz4 ./Image - SHA_FILE="Image" -elif [ -f "vmlinux" ]; then +if [ -f "vmlinux" ]; then SHA_FILE="vmlinux" else - exit_and_clean_if_error 1 "No vmlinux or boot image downloaded" + exit_and_clean_if_error 1 "No vmlinux downloaded" fi echo "Checking if GKI binaries match the current aosp/ revision..." @@ -107,17 +87,11 @@ fi echo "Copying GKI files to ${GKI_PREBUILTS_DIR}..." mv -v ${GKI_FILES[@]} ${GKI_PREBUILTS_DIR} exit_and_clean_if_error $? "Unable to copy all files" -if [ -f ${USER_IMG_DIR}/${BOOT_IMG_NAME} ]; then - mv ${USER_IMG_DIR}/${BOOT_IMG_NAME} ${GKI_PREBUILTS_DIR}/boot-user.img - echo "Copied user variant ${BOOT_IMG_NAME} to boot-user.img." -fi cd ${GKI_PREBUILTS_DIR} if [ -n "${BOOT_IMG_NAME}" -a -f "${BOOT_IMG_NAME}" ]; then mv ${BOOT_IMG_NAME} boot.img - echo "Copied userdebug variant ${BOOT_IMG_NAME} to boot.img." - mv ${TEMP_DIR}/Image.lz4 ./ - echo "Copied Image.lz4 unpacked from ${BOOT_IMG_NAME}." + echo "Copied ${BOOT_IMG_NAME} to boot.img." fi echo "Update the GKI binaries to ab/${GKI_BUILD} diff --git a/drivers/OWNERS b/drivers/OWNERS index 97c8346e1068..c984e8ffb653 100644 --- a/drivers/OWNERS +++ b/drivers/OWNERS @@ -22,8 +22,8 @@ per-file clk/clk-multiplier.c=saravanak@google.com per-file clk/clk-mux.c=saravanak@google.com per-file clk/Kconfig=saravanak@google.com per-file clk/Makefile=saravanak@google.com -per-file clk/samsung/clk-gs101.c=* -per-file clk/samsung/composite.*=* + +per-file clk/samsung/**=* per-file clocksource/exynos_mct.c=* @@ -46,6 +46,7 @@ per-file i2c/busses/i2c-exynos5.h=* per-file iio/power/odpm.c=* per-file input/fingerprint/**=* +per-file input/keyboard/s2mpg12-key.c=* per-file input/keycombo.c=* per-file input/keydebug-*=* per-file input/misc/vl53l1/**=* @@ -53,6 +54,7 @@ per-file input/touchscreen/heatmap.c=* per-file input/touchscreen/sec_ts/**=* per-file input/touchscreen/stm/**=* +per-file iommu/exynos-pcie-iommu*=* per-file iommu/samsung-iommu*=* per-file iommu/samsung-secure-iova.c=* @@ -61,6 +63,7 @@ per-file media/platform/exynos/**=* per-file mfd/s2mpg*=* per-file mfd/slg51000-core.c=* +per-file mfd/slg51002-core.c=* per-file misc/access_ramoops.c=* per-file misc/bbdpl/**=* @@ -82,6 +85,7 @@ per-file pci/controller/dwc/pcie-exynos*=* per-file phy/samsung/**=* per-file pinctrl/pinctrl-slg51000.c=* +per-file pinctrl/pinctrl-slg51002.c=* per-file pinctrl/samsung/pinctrl-exynos*=* per-file pinctrl/samsung/pinctrl-gs*=* per-file pinctrl/samsung/pinctrl-samsung.*=* @@ -107,12 +111,14 @@ per-file regulator/of_regulator.c=saravanak@google.com per-file regulator/pmic_class.c=* per-file regulator/s2mpg*=* per-file regulator/slg51000-regulator.c=* +per-file regulator/slg51002-regulator.c=* per-file regulator/userspace-consumer.c=saravanak@google.com per-file regulator/virtual.c=saravanak@google.com per-file rtc/rtc-s2mpg*=* per-file scsi/ufs/gs101/**=* +per-file scsi/ufs/gs201/**=* per-file scsi/ufs/ufs-cal*=* per-file scsi/ufs/ufs-exynos.c=* per-file scsi/ufs/ufs-exynos.h=* diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index d30267e08536..447342a878ff 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -213,7 +213,7 @@ static int binder_update_page_range(struct binder_alloc *alloc, int allocate, mm = alloc->vma_vm_mm; if (mm) { - mmap_read_lock(mm); + mmap_write_lock(mm); vma = alloc->vma; } @@ -271,7 +271,7 @@ static int binder_update_page_range(struct binder_alloc *alloc, int allocate, trace_binder_alloc_page_end(alloc, index); } if (mm) { - mmap_read_unlock(mm); + mmap_write_unlock(mm); mmput(mm); } return 0; @@ -304,7 +304,7 @@ static int binder_update_page_range(struct binder_alloc *alloc, int allocate, } err_no_vma: if (mm) { - mmap_read_unlock(mm); + mmap_write_unlock(mm); mmput(mm); } return vma ? -ENOMEM : -ESRCH; diff --git a/drivers/android/vendor_hooks.c b/drivers/android/vendor_hooks.c index 8ddb3f6664fc..bbcd6637148b 100644 --- a/drivers/android/vendor_hooks.c +++ b/drivers/android/vendor_hooks.c @@ -41,7 +41,6 @@ #include #include #include -#include #include #include #include @@ -62,8 +61,10 @@ #include #include #include -#include +#include +#ifdef __GENKSYMS__ #include +#endif #include #include #include @@ -105,7 +106,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_select_task_rq_fair); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_select_task_rq_rt); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_select_task_rq_dl); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_select_fallback_rq); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_refrigerator); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_scheduler_tick); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_enqueue_task); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_dequeue_task); @@ -148,7 +148,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cpu_idle_exit); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_mpam_set); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_find_busiest_group); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_gic_resume); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_wq_lockup_pool); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_ipi_stop); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_sysrq_crash); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_dump_throttled_rt_tasks); @@ -227,6 +226,7 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_calc_alloc_flags); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_mm_compaction_begin); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_mm_compaction_end); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_rmqueue); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_pagevec_drain); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_pagecache_get_page); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_filemap_fault_get_page); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_filemap_fault_cache_page); @@ -250,8 +250,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_uclamp_eff_get); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_uclamp_task_util); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_uclamp_rq_util_with); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_cpufreq_transition); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cgroup_set_task); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_cgroup_force_kthread_migration); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_syscall_prctl_finished); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_create_worker); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_check_preempt_tick); @@ -270,8 +268,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_selinux_avc_insert); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_selinux_avc_node_delete); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_selinux_avc_node_replace); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_selinux_avc_lookup); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_blk_alloc_rqs); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_blk_rq_ctx_init); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_commit_creds); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_exit_creds); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_override_creds); @@ -287,6 +283,15 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_get_from_fragment_pool); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_exclude_reserved_zone); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_include_reserved_zone); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_alloc_pages_slowpath); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_do_madvise_blk_plug); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_shrink_inactive_list_blk_plug); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_shrink_lruvec_blk_plug); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_reclaim_pages_plug); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_zap_pte_range_tlb_start); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_zap_pte_range_tlb_force_flush); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_zap_pte_range_tlb_end); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_bh_lru_install); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_skip_lru_disable); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cma_alloc_adjust); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_show_mem); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_print_slabinfo_header); @@ -318,7 +323,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_tune_swappiness); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_shrink_slab_bypass); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_psi_event); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_psi_group); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_cpuset_fork); EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_set_cpus_allowed_comm); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_sched_setaffinity_early); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_free_task); @@ -336,7 +340,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_selinux_is_initialized); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_tune_inactive_ratio); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_update_topology_flags_workfn); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_of_i2c_get_board_info); -EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cgroup_attach); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_mm_dirty_limits); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_oom_check_panic); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_check_uninterruptible_tasks); @@ -417,3 +420,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_mmput); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_early_resume_begin); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_alloc_pages_reclaim_bypass); EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_alloc_pages_failure_bypass); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_rebuild_root_domains_bypass); diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 579f6d38c35e..d13c257ba8b6 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -49,7 +49,6 @@ static const char *default_compressor = "lzo-rle"; static unsigned int num_devices = 1; static const struct block_device_operations zram_devops; -static const struct block_device_operations zram_wb_devops; static void zram_free_page(struct zram *zram, size_t index); static int zram_bvec_read(struct zram *zram, struct bio_vec *bvec, @@ -498,17 +497,6 @@ static ssize_t backing_dev_store(struct device *dev, zram->backing_dev = backing_dev; zram->bitmap = bitmap; zram->nr_pages = nr_pages; - /* - * With writeback feature, zram does asynchronous IO so it's no longer - * synchronous device so let's remove synchronous io flag. Othewise, - * upper layer(e.g., swap) could wait IO completion rather than - * (submit and return), which will cause system sluggish. - * Furthermore, when the IO function returns(e.g., swap_readpage), - * upper layer expects IO was done so it could deallocate the page - * freely but in fact, IO is going on so finally could cause - * use-after-free when the IO is really done. - */ - zram->disk->fops = &zram_wb_devops; up_write(&zram->init_lock); pr_info("setup backing device %s\n", file_name); @@ -1272,6 +1260,9 @@ static int __zram_bvec_read(struct zram *zram, struct page *page, u32 index, struct bio_vec bvec; zram_slot_unlock(zram, index); + /* A null bio means rw_page was used, we must fallback to bio */ + if (!bio) + return -EOPNOTSUPP; bvec.bv_page = page; bvec.bv_len = PAGE_SIZE; @@ -1748,13 +1739,6 @@ static const struct block_device_operations zram_devops = { .owner = THIS_MODULE }; -static const struct block_device_operations zram_wb_devops = { - .open = zram_open, - .submit_bio = zram_submit_bio, - .swap_slot_free_notify = zram_slot_free_notify, - .owner = THIS_MODULE -}; - static DEVICE_ATTR_WO(compact); static DEVICE_ATTR_RW(disksize); static DEVICE_ATTR_RO(initstate); diff --git a/drivers/bts/Makefile b/drivers/bts/Makefile index c31e35f5e36e..04fcbe88b17d 100644 --- a/drivers/bts/Makefile +++ b/drivers/bts/Makefile @@ -2,4 +2,5 @@ # Makefile for BTS device driver # -obj-$(CONFIG_EXYNOS_BTS) += exynos-bts.o exynos-btsopsgs101.o +obj-$(CONFIG_EXYNOS_BTS) += bts.o +bts-y += exynos-bts.o exynos-btsopsgs.o diff --git a/drivers/bts/bts.h b/drivers/bts/bts.h index 34015110a1ea..a7c1f8d3787e 100644 --- a/drivers/bts/bts.h +++ b/drivers/bts/bts.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include @@ -115,6 +115,8 @@ struct bts_ops { int (*get_urgent)(void __iomem *va, struct bts_stat *stat); int (*set_blocking)(void __iomem *va, struct bts_stat *stat); int (*get_blocking)(void __iomem *va, struct bts_stat *stat); + int (*set_vc)(void __iomem *va, unsigned int value); + int (*get_vc)(void __iomem *va, unsigned int *value); }; /** diff --git a/drivers/bts/exynos-bts.c b/drivers/bts/exynos-bts.c index d8245dcb210b..088c8c4594ae 100644 --- a/drivers/bts/exynos-bts.c +++ b/drivers/bts/exynos-bts.c @@ -21,8 +21,8 @@ #include #include #include -#include #include +#include #if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) #include #else @@ -42,6 +42,7 @@ } while (0) static bool btsdbg_log; +static unsigned int vc_num_total; #if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) static struct exynos_pm_qos_request exynos_mif_qos; @@ -1154,6 +1155,87 @@ static ssize_t exynos_bts_log_write(struct file *file, return buf_size; } +static int exynos_bts_vc_open_show(struct seq_file *buf, void *d) +{ + struct bts_info info; + int ret, i; + unsigned int value, vc_num = 0; + + for (i = 0; i < btsdev->num_bts; i++) { + info = btsdev->bts_list[i]; + if (!info.va_base || !info.ops->get_vc) + continue; + + spin_lock(&btsdev->lock); + ret = info.ops->get_vc(info.va_base, &value); + spin_unlock(&btsdev->lock); + + if (ret) { + pr_warn("%s: get_vc failed. err=(%d)\n", + __func__, ret); + continue; + } + + seq_printf(buf, "[%d] %s: \t0x%.8X\n", + vc_num, info.name, value); + vc_num++; + } + + return 0; +} + +static int exynos_bts_vc_open(struct inode *inode, struct file *file) +{ + return single_open(file, exynos_bts_vc_open_show, inode->i_private); +} + +static ssize_t exynos_bts_vc_write(struct file *file, + const char __user *user_buf, size_t count, + loff_t *ppos) +{ + struct bts_info info; + char buf[16]; + ssize_t buf_size; + + int i, ret; + unsigned int value, vc_num, cnt; + + buf_size = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, + count); + if (buf_size < 0) + return buf_size; + + buf[buf_size] = '\0'; + + ret = sscanf(buf, "%8X %d\n", &value, &vc_num); + if (ret != 2) { + pr_err("%s: sscanf failed. We need 2 input. count=(%d)\n", + __func__, ret); + return -EINVAL; + } + + if (vc_num >= vc_num_total) { + pr_err("%s: vc_num=%d out of range\n", __func__, vc_num); + return -EINVAL; + } + + cnt = 0; + for (i = 0; i < btsdev->num_bts; i++) { + info = btsdev->bts_list[i]; + if (!info.va_base) + continue; + if (!info.ops->set_vc) + continue; + if (cnt == vc_num) + break; + cnt++; + } + + info.ops->set_vc(info.va_base, value); + + return buf_size; +} + static const struct file_operations debug_bts_hwstatus_fops = { .open = exynos_bts_hwstatus_open, .read = seq_read, @@ -1223,6 +1305,14 @@ static const struct file_operations debug_bts_log_fops = { .release = single_release, }; +static const struct file_operations debug_bts_vc_fops = { + .open = exynos_bts_vc_open, + .read = seq_read, + .write = exynos_bts_vc_write, + .llseek = seq_lseek, + .release = single_release, +}; + int exynos_bts_debugfs_init(void) { struct dentry *den; @@ -1243,6 +1333,7 @@ int exynos_bts_debugfs_init(void) debugfs_create_file("log", 0440, den, NULL, &debug_bts_log_fops); debugfs_create_file("bw", 0440, den, NULL, &debug_bts_bw_fops); debugfs_create_file("bw_hist", 0440, den, NULL, &debug_bts_bw_hist_fops); + debugfs_create_file("vc", 0440, den, NULL, &debug_bts_vc_fops); return 0; } @@ -1523,7 +1614,6 @@ static int bts_parse_data(struct device_node *np, struct bts_device *data) } } - info[i].name = child_np->name; info[i].status = of_device_is_available(child_np); /* Parsing bts-type */ @@ -1534,6 +1624,16 @@ static int bts_parse_data(struct device_node *np, struct bts_device *data) goto err; } + if (info[i].type == INTERNAL_BTS) { + ret = of_property_read_string(child_np, "vc-string", &info[i].name); + if (ret) { + dev_err(data->dev, "failed to get vc-string\n"); + goto err; + } + vc_num_total++; + } else + info[i].name = child_np->name; + /* Register operation function */ ret = register_btsops(&info[i]); if (ret) diff --git a/drivers/bts/exynos-btsopsgs101.c b/drivers/bts/exynos-btsopsgs.c similarity index 95% rename from drivers/bts/exynos-btsopsgs101.c rename to drivers/bts/exynos-btsopsgs.c index a457d40d2b17..b7fd64b94a51 100644 --- a/drivers/bts/exynos-btsopsgs101.c +++ b/drivers/bts/exynos-btsopsgs.c @@ -12,9 +12,9 @@ */ #include -#include +#include -#include "regs-btsgs101.h" +#include "regs-btsgs.h" #include "bts.h" /**************************************************************** @@ -647,6 +647,30 @@ static int get_scibts(void __iomem *base, struct bts_stat *stat) return 0; } +/**************************************************************** + *› › › int bts ops functions› › › * + ****************************************************************/ +static int set_intvc(void __iomem *base, unsigned int value) +{ + if (!base) + return -ENODATA; + + __raw_writel(value, base); + + return 0; +} + +static int get_intvc(void __iomem *base, unsigned int *value) +{ + if (!base) + return -ENODATA; + + *value = __raw_readl(base); + + return 0; +} + + /**************************************************************** * register ops functions * ****************************************************************/ @@ -671,6 +695,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = get_ipbts_urgent; info->ops->set_blocking = set_ipbts_blocking; info->ops->get_blocking = get_ipbts_blocking; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case TREX_BTS: info->ops->init_bts = init_trexbts; @@ -684,6 +710,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case SCI_BTS: info->ops->init_bts = init_sciqfull; @@ -697,6 +725,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case SMC_BTS: info->ops->init_bts = init_smcqbusy; @@ -710,6 +740,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case BUSC_BTS: info->ops->init_bts = init_qmax; @@ -723,6 +755,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case DREX_BTS: info->ops->init_bts = NULL; @@ -736,6 +770,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = NULL; + info->ops->get_vc = NULL; break; case INTERNAL_BTS: info->ops->init_bts = NULL; @@ -749,6 +785,8 @@ int register_btsops(struct bts_info *info) info->ops->get_urgent = NULL; info->ops->set_blocking = NULL; info->ops->get_blocking = NULL; + info->ops->set_vc = set_intvc; + info->ops->get_vc = get_intvc; break; default: break; diff --git a/drivers/bts/regs-btsgs101.h b/drivers/bts/regs-btsgs.h similarity index 100% rename from drivers/bts/regs-btsgs101.h rename to drivers/bts/regs-btsgs.h diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index e97ff408bec4..e7cb291b0674 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -24,5 +24,6 @@ obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o obj-$(CONFIG_COMPOSITE_CLK_SAMSUNG) += clk_exynos.o -clk_exynos-$(CONFIG_COMPOSITE_CLK_SAMSUNG) += clk-gs101.o +clk_exynos-$(CONFIG_SOC_GS101) += clk-gs101.o +clk_exynos-$(CONFIG_SOC_GS201) += clk-gs201.o clk_exynos-$(CONFIG_COMPOSITE_CLK_SAMSUNG) += composite.o diff --git a/drivers/clk/samsung/clk-gs201.c b/drivers/clk/samsung/clk-gs201.c new file mode 100644 index 000000000000..2e17bc906447 --- /dev/null +++ b/drivers/clk/samsung/clk-gs201.c @@ -0,0 +1,1929 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Common Clock Framework support for GS201 SoC. + * + * Copyright (c) 2019-2021 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../soc/google/cal-if/gs201/cmucal-vclk.h" +#include "../../soc/google/cal-if/gs201/cmucal-node.h" +#include "../../soc/google/cal-if/gs201/cmucal-qch.h" +#include "../../soc/google/cal-if/gs201/clkout_gs201.h" +#include "composite.h" + +#ifdef CONFIG_DEBUG_FS +#include +#include + +#define PAD_CTRL_CLKOUT0 0x18063e80 +#define PAD_CTRL_CLKOUT1 0x18063e84 + +static const phys_addr_t clkout_addresses[] = { + 0x1a000810, + 0x18000810, + 0x25a00810, + 0x1ca00810, + 0x1E080810, + 0x20c00810, + 0x20C00814, + 0x20c10810, + 0x20c20810, + 0x1a400810, + 0x1c200810, + 0x1b000810, + 0x1c000818, + 0x17000810, + 0x1c600810, + 0x1a800810, + 0x27f00810, + 0x27f00814, + 0x1d000810, + 0x11000810, + 0x11800810, + 0x14400810, + 0x1ac00810, + 0x1b400810, + 0x1b700810, + 0x1c800810, + 0x20800810, + 0x10010810, + 0x1e000810, + 0x20000810, + 0x1e800810, + 0x1f000810, + 0x1aa00810, + 0x10800810, + 0x10c00810, + 0x1bc00810, + 0x1cc00810 +}; +#endif + +static struct samsung_clk_provider *gs201_clk_provider; +/* + * list of controller registers to be saved and restored during a + * suspend/resume cycle. + */ +/* fixed rate clocks generated outside the soc */ +static struct samsung_fixed_rate gs201_fixed_rate_ext_clks[] = { + FRATE(OSCCLK, + "fin_pll", + NULL, + 0, + 24576000), +}; + +/* HWACG VCLK */ +static struct init_vclk gs201_apm_hwacg_vclks[] = { + HWACG_VCLK(MUX_APM_FUNCSRC, + MUX_CLKCMU_APM_FUNCSRC, + "MUX_APM_FUNCSRC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_APM_FUNC, + MUX_CLKCMU_APM_FUNC, + "MUX_APM_FUNC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_aur_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_AUR_AURCTL, + MUX_CLKCMU_AUR_AURCTL_USER, + "UMUX_CLKCMU_AUR_AURCTL", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_AUR_NOC, + MUX_CLKCMU_AUR_NOC_USER, + "UMUX_CLKCMU_AUR_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_top_hwacg_vclks[] = { + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK0, + DFTMUX_CMU_QCH_CIS_CLK0, + "GATE_DFTMUX_CMU_CIS_CLK0", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK1, + DFTMUX_CMU_QCH_CIS_CLK1, + "GATE_DFTMUX_CMU_CIS_CLK1", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK2, + DFTMUX_CMU_QCH_CIS_CLK2, + "GATE_DFTMUX_CMU_CIS_CLK2", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK3, + DFTMUX_CMU_QCH_CIS_CLK3, + "GATE_DFTMUX_CMU_CIS_CLK3", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK4, + DFTMUX_CMU_QCH_CIS_CLK4, + "GATE_DFTMUX_CMU_CIS_CLK4", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK5, + DFTMUX_CMU_QCH_CIS_CLK5, + "GATE_DFTMUX_CMU_CIS_CLK5", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK6, + DFTMUX_CMU_QCH_CIS_CLK6, + "GATE_DFTMUX_CMU_CIS_CLK6", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), + HWACG_VCLK(GATE_DFTMUX_CMU_CIS_CLK7, + DFTMUX_CMU_QCH_CIS_CLK7, + "GATE_DFTMUX_CMU_CIS_CLK7", + NULL, + 0, + VCLK_GATE | VCLK_QCH_DIS, + NULL), +}; + +static struct init_vclk gs201_nocl0_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_NOCL0_NOC, + MUX_CLKCMU_NOCL0_NOC_USER, + "UMUX_CLKCMU_NOCL0_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_NOCL0_NOC_OPTION1, + MUX_CLK_NOCL0_NOC_OPTION1, + "MUX_NOCL0_NOC_OPTION1", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_nocl1a_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_NOCL1A_NOC, + MUX_CLKCMU_NOCL1A_NOC_USER, + "UMUX_CLKCMU_NOCL1A_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_nocl1b_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_NOCL1B_NOC, + MUX_CLKCMU_NOCL1B_NOC_USER, + "UMUX_CLKCMU_NOCL1B_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_nocl2a_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_NOCL2A_NOC, + MUX_CLKCMU_NOCL2A_NOC_USER, + "UMUX_CLKCMU_NOCL2A_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_eh_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_EH_NOC, + MUX_CLKCMU_EH_NOC_USER, + "UMUX_CLKCMU_EH_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_EH_PLL_NOCL0, + MUX_CLKCMU_EH_PLL_NOCL0_USER, + "UMUX_CLKCMU_EH_PLL_NOCL0", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_EH_NOC, + MUX_CLK_EH_NOC, + "MUX_EH_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_g3d_hwacg_vclks[] = { + HWACG_VCLK(GATE_GPU, + GPU_QCH, + "GATE_GPU", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_dpu_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_DPU_NOC, + MUX_CLKCMU_DPU_NOC_USER, + "UMUX_CLKCMU_DPU_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_DPUF_DMA, + DPUF_QCH_DPU_DMA, + "GATE_DPUF_DMA", + "UMUX_CLKCMU_DPU_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_DPUF_DPP, + DPUF_QCH_DPU_DPP, + "GATE_DPUF_DPP", + "UMUX_CLKCMU_DPU_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_disp_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_DISP_NOC, + MUX_CLKCMU_DISP_NOC_USER, + "UMUX_CLKCMU_DISP_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_DPUB, + DPUB_QCH, + "GATE_DPUB", + "UMUX_CLKCMU_DISP_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_g2d_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_G2D_G2D, + MUX_CLKCMU_G2D_G2D_USER, + "UMUX_CLKCMU_G2D_G2D", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_G2D_MSCL, + MUX_CLKCMU_G2D_MSCL_USER, + "UMUX_CLKCMU_G2D_MSCL", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_G2D, + G2D_QCH, + "GATE_G2D", + "UMUX_CLKCMU_G2D_G2D", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_JPEG, + JPEG_QCH, + "GATE_JPEG", + "UMUX_CLKCMU_G2D_MSCL", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_hsi0_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_HSI0_TCXO, + MUX_CLKCMU_HSI0_TCXO_USER, + "UMUX_CLKCMU_HSI0_TCXO", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_HSI0_USB20_REF, + MUX_CLK_HSI0_USB20_REF, + "MUX_HSI0_USB20_REF", + NULL, + 0, + 0, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI0_USB31DRD, + MUX_CLKCMU_HSI0_USB31DRD_USER, + "UMUX_CLKCMU_HSI0_USB31DRD", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI0_USB20, + MUX_CLKCMU_HSI0_USB20_USER, + "UMUX_CLKCMU_HSI0_USB20", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_HSI0_USB31DRD, + MUX_CLK_HSI0_USB31DRD, + "MUX_HSI0_USB31DRD", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI0_NOC, + MUX_CLKCMU_HSI0_NOC_USER, + "UMUX_CLKCMU_HSI0_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI0_ALT, + MUX_CLKCMU_HSI0_ALT_USER, + "UMUX_CLKCMU_HSI0_ALT", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_HSI0_NOC, + MUX_CLK_HSI0_NOC, + "MUX_HSI0_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI0_DPGTC, + MUX_CLKCMU_HSI0_DPGTC_USER, + "UMUX_CLKCMU_HSI0_DPGTC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_USB31DRD_SLV_LINK, + USB31DRD_QCH_SLV_LINK, + "GATE_USB31DRD_SLV_LINK", + "MUX_HSI0_USB31DRD", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_hsi1_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_HSI1_NOC, + MUX_CLKCMU_HSI1_NOC_USER, + "UMUX_CLKCMU_HSI1_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI1_PCIE, + MUX_CLKCMU_HSI1_PCIE_USER, + "UMUX_CLKCMU_HSI1_PCIE", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_DBG_1, + PCIE_GEN4_0_QCH_DBG_1, + "GATE_PCIE_GEN4_0_DBG_1", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_AXI_1, + PCIE_GEN4_0_QCH_AXI_1, + "GATE_PCIE_GEN4_0_AXI_1", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_APB_1, + PCIE_GEN4_0_QCH_APB_1, + "GATE_PCIE_GEN4_0_APB_1", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_SCLK_1, + PCIE_GEN4_0_QCH_SCLK_1, + "GATE_PCIE_GEN4_0_SCLK_1", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_PCS_APB, + PCIE_GEN4_0_QCH_PCS_APB, + "GATE_PCIE_GEN4_0_PCS_APB", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_PMA_APB, + PCIE_GEN4_0_QCH_PMA_APB, + "GATE_PCIE_GEN4_0_PMA_APB", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_DBG_2, + PCIE_GEN4_0_QCH_DBG_2, + "GATE_PCIE_GEN4_0_DBG_2", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_AXI_2, + PCIE_GEN4_0_QCH_AXI_2, + "GATE_PCIE_GEN4_0_AXI_2", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_APB_2, + PCIE_GEN4_0_QCH_APB_2, + "GATE_PCIE_GEN4_0_APB_2", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_0_UDBG, + PCIE_GEN4_0_QCH_UDBG, + "GATE_PCIE_GEN4_0_UDBG", + "UMUX_CLKCMU_HSI1_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_hsi2_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_HSI2_NOC, + MUX_CLKCMU_HSI2_NOC_USER, + "UMUX_CLKCMU_HSI2_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI2_PCIE, + MUX_CLKCMU_HSI2_PCIE_USER, + "UMUX_CLKCMU_HSI2_PCIE", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI2_UFS_EMBD, + MUX_CLKCMU_HSI2_UFS_EMBD_USER, + "UMUX_CLKCMU_HSI2_UFS_EMBD", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_HSI2_MMC_CARD, + MUX_CLKCMU_HSI2_MMC_CARD_USER, + "UMUX_CLKCMU_HSI2_MMC_CARD", + NULL, + 0, + VCLK_GATE, + NULL), + + HWACG_VCLK(GATE_MMC_CARD, + MMC_CARD_QCH, + "GATE_MMC_CARD", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_AXI_1, + PCIE_GEN4_1_QCH_AXI_1, + "GATE_PCIE_GEN4_1_AXI_1", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_APB_1, + PCIE_GEN4_1_QCH_APB_1, + "GATE_PCIE_GEN4_1_APB_1", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_DBG_1, + PCIE_GEN4_1_QCH_DBG_1, + "GATE_PCIE_GEN4_1_DBG_1", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_PCS_APB, + PCIE_GEN4_1_QCH_PCS_APB, + "GATE_PCIE_GEN4_1_PCS_APB", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_PMA_APB, + PCIE_GEN4_1_QCH_PMA_APB, + "GATE_PCIE_GEN4_1_PMA_APB", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_AXI_2, + PCIE_GEN4_1_QCH_AXI_2, + "GATE_PCIE_GEN4_1_AXI_2", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_DBG_2, + PCIE_GEN4_1_QCH_DBG_2, + "GATE_PCIE_GEN4_1_DBG_2", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_APB_2, + PCIE_GEN4_1_QCH_APB_2, + "GATE_PCIE_GEN4_1_APB_2", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PCIE_GEN4_1_UDBG, + PCIE_GEN4_1_QCH_UDBG, + "GATE_PCIE_GEN4_1_UDBG", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_UFS_EMBD, + UFS_EMBD_QCH, + "GATE_UFS_EMBD", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_UFS_EMBD_FMP, + UFS_EMBD_QCH_FMP, + "GATE_UFS_EMBD_FMP", + "UMUX_CLKCMU_HSI2_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_csis_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_CSIS_NOC, + MUX_CLKCMU_CSIS_NOC_USER, + "UMUX_CLKCMU_CSIS_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_pdp_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_PDP_NOC, + MUX_CLKCMU_PDP_NOC_USER, + "UMUX_CLKCMU_PDP_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_PDP_VRA, + MUX_CLKCMU_PDP_VRA_USER, + "UMUX_CLKCMU_PDP_VRA", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_ipp_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_IPP_NOC, + MUX_CLKCMU_IPP_NOC_USER, + "UMUX_CLKCMU_IPP_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_g3aa_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_G3AA_G3AA, + MUX_CLKCMU_G3AA_G3AA_USER, + "UMUX_CLKCMU_G3AA_G3AA", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_itp_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_ITP_NOC, + MUX_CLKCMU_ITP_NOC_USER, + "UMUX_CLKCMU_ITP_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_dns_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_DNS_NOC, + MUX_CLKCMU_DNS_NOC_USER, + "UMUX_CLKCMU_DNS_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_tnr_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_TNR_NOC, + MUX_CLKCMU_TNR_NOC_USER, + "UMUX_CLKCMU_TNR_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_mcsc_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_MCSC_ITSC, + MUX_CLKCMU_MCSC_ITSC_USER, + "UMUX_CLKCMU_MCSC_ITSC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_MCSC_MCSC, + MUX_CLKCMU_MCSC_MCSC_USER, + "UMUX_CLKCMU_MCSC_MCSC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_gdc_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_GDC_SCSC, + MUX_CLKCMU_GDC_SCSC_USER, + "UMUX_CLKCMU_GDC_SCSC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_GDC_GDC0, + MUX_CLKCMU_GDC_GDC0_USER, + "UMUX_CLKCMU_GDC_GDC0", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_GDC_GDC1, + MUX_CLKCMU_GDC_GDC1_USER, + "UMUX_CLKCMU_GDC_GDC1", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_mfc_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_MFC_MFC, + MUX_CLKCMU_MFC_MFC_USER, + "UMUX_CLKCMU_MFC_MFC", + NULL, + 0, + 0, + NULL), + HWACG_VCLK(GATE_MFC, + MFC_QCH, + "GATE_MFC", + "UMUX_CLKCMU_MFC_MFC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_mif_hwacg_vclks[] = { + HWACG_VCLK(UMUX_MIF_DDRPHY2X, + CLKMUX_MIF_DDRPHY2X, + "UMUX_MIF_DDRPHY2X", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_misc_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_MISC_NOC, + MUX_CLKCMU_MISC_NOC_USER, + "UMUX_CLKCMU_MISC_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_MISC_SSS, + MUX_CLKCMU_MISC_SSS_USER, + "UMUX_CLKCMU_MISC_SSS", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_MCT, + MCT_QCH, + "GATE_MCT", + "DOUT_CLK_MISC_NOCP", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_WDT_CL0, + WDT_CLUSTER0_QCH, + "GATE_WDT_CL0", + "DOUT_CLK_MISC_NOCP", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_WDT_CL1, + WDT_CLUSTER1_QCH, + "GATE_WDT_CL1", + "DOUT_CLK_MISC_NOCP", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PDMA0, + PDMA0_QCH, + "GATE0_PDMA", + "DOUT_CLK_MISC_NOCP", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PDMA1, + PDMA1_QCH, + "GATE1_PDMA", + "DOUT_CLK_MISC_NOCP", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK_QACTIVE(ATCLK, + "ATCLK", + "DOUT_CLK_MISC_BUSP", + 0, + VCLK_QACTIVE, + NULL, + 0x2b00c02c, + 0x1, + 0x1), +}; + +static struct init_vclk gs201_peric0_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_PERIC0_NOC, + MUX_CLKCMU_PERIC0_NOC_USER, + "UMUX_CLKCMU_PERIC0_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_PERIC0_USI0_UART, + MUX_CLKCMU_PERIC0_USI0_UART_USER, + "UMUX_CLKCMU_PERIC0_USI0_UART", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI1_USI, + USI1_USI_QCH, + "GATE_PERIC0_TOP0_USI1_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI2_USI, + USI2_USI_QCH, + "GATE_PERIC0_TOP0_USI2_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI3_USI, + USI3_USI_QCH, + "GATE_PERIC0_TOP0_USI3_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI4_USI, + USI4_USI_QCH, + "GATE_PERIC0_TOP0_USI4_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI5_USI, + USI5_USI_QCH, + "GATE_PERIC0_TOP0_USI5_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI6_USI, + USI6_USI_QCH, + "GATE_PERIC0_TOP0_USI6_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI7_USI, + USI7_USI_QCH, + "GATE_PERIC0_TOP0_USI7_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_USI8_USI, + USI8_USI_QCH, + "GATE_PERIC0_TOP0_USI8_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C1, + I3C1_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C1", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C2, + I3C2_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C2", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C3, + I3C3_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C3", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C4, + I3C4_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C4", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C5, + I3C5_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C5", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C6, + I3C6_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C6", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C7, + I3C7_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C7", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP0_I3C8, + I3C8_QCH_SCLK, + "GATE_PERIC0_TOP0_I3C8", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP1_USI0_UART, + USI0_UART_QCH, + "GATE_PERIC0_TOP1_USI0_UART", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC0_TOP1_USI14_USI, + USI14_USI_QCH, + "GATE_PERIC0_TOP1_USI14_USI", + "UMUX_CLKCMU_PERIC0_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_peric1_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_PERIC1_NOC, + MUX_CLKCMU_PERIC1_NOC_USER, + "UMUX_CLKCMU_PERIC1_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI0_USI, + USI0_USI_QCH, + "GATE_PERIC1_TOP0_USI0_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI9_USI, + USI9_USI_QCH, + "GATE_PERIC1_TOP0_USI9_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI10_USI, + USI10_USI_QCH, + "GATE_PERIC1_TOP0_USI10_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI11_USI, + USI11_USI_QCH, + "GATE_PERIC1_TOP0_USI11_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI12_USI, + USI12_USI_QCH, + "GATE_PERIC1_TOP0_USI12_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI13_USI, + USI13_USI_QCH, + "GATE_PERIC1_TOP0_USI13_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_I3C0, + I3C0_QCH_SCLK, + "GATE_PERIC1_TOP0_I3C0", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_PWM, + PWM_QCH, + "GATE_PERIC1_TOP0_PWM", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI15_USI, + USI15_USI_QCH, + "GATE_PERIC1_TOP0_USI15_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(GATE_PERIC1_TOP0_USI16_USI, + USI16_USI_QCH, + "GATE_PERIC1_TOP0_USI16_USI", + "UMUX_CLKCMU_PERIC1_NOC", + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_tpu_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_TPU_TPU, + MUX_CLKCMU_TPU_TPU_USER, + "UMUX_CLKCMU_TPU_TPU", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_TPU_TPUCTL, + MUX_CLKCMU_TPU_TPUCTL_USER, + "UMUX_CLKCMU_TPU_TPUCTL", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_TPU_NOC, + MUX_CLKCMU_TPU_NOC_USER, + "UMUX_CLKCMU_TPU_NOC", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(UMUX_CLKCMU_TPU_UART, + MUX_CLKCMU_TPU_UART_USER, + "UMUX_CLKCMU_TPU_UART", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_TPU_TPU, + MUX_CLK_TPU_TPU, + "MUX_TPU_TPU", + NULL, + 0, + VCLK_GATE, + NULL), + HWACG_VCLK(MUX_TPU_TPUCTL, + MUX_CLK_TPU_TPUCTL, + "MUX_TPU_TPUCTL", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +static struct init_vclk gs201_bo_hwacg_vclks[] = { + HWACG_VCLK(UMUX_CLKCMU_BO_NOC, + MUX_CLKCMU_BO_NOC_USER, + "UMUX_CLKCMU_BO_NOC", + NULL, + 0, + VCLK_GATE, + NULL), +}; + +/* Special VCLK */ +static struct init_vclk gs201_apm_vclks[] = { + VCLK(DOUT_CLK_APM_BOOST, + DIV_CLK_APM_BOOST, + "DOUT_CLK_APM_BOOST", + 0, + 0, + NULL), + VCLK(DOUT_CLK_APM_USI0_UART, + DIV_CLK_APM_USI0_UART, + "DOUT_CLK_APM_USI0_UART", + 0, + 0, + NULL), + VCLK(DOUT_CLK_APM_USI1_UART, + DIV_CLK_APM_USI1_UART, + "DOUT_CLK_APM_USI1_UART", + 0, + 0, + NULL), + VCLK(DOUT_CLK_APM_USI0_USI, + DIV_CLK_APM_USI0_USI, + "DOUT_CLK_APM_USI0_USI", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_aur_vclks[] = { + VCLK(DOUT_CLK_AUR_NOCP, + DIV_CLK_AUR_NOCP, + "DOUT_CLK_AUR_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_nocl0_vclks[] = { + VCLK(DOUT_CLK_NOCL0_NOCP, + DIV_CLK_NOCL0_NOCP, + "DOUT_CLK_NOCL0_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_nocl1a_vclks[] = { + VCLK(DOUT_CLK_NOCL1A_NOCP, + DIV_CLK_NOCL1A_NOCP, + "DOUT_CLK_NOCL1A_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_nocl1b_vclks[] = { + VCLK(DOUT_CLK_NOCL1B_NOCP, + DIV_CLK_NOCL1B_NOCP, + "DOUT_CLK_NOCL1B_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_nocl2a_vclks[] = { + VCLK(DOUT_CLK_NOCL2A_NOCP, + DIV_CLK_NOCL2A_NOCP, + "DOUT_CLK_NOCL2A_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_eh_vclks[] = { + VCLK(DOUT_CLK_EH_NOCP, + DIV_CLK_EH_NOCP, + "DOUT_CLK_EH_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_dpu_vclks[] = { + VCLK(DOUT_CLK_DPU_NOCP, + DIV_CLK_DPU_NOCP, + "DOUT_CLK_DPU_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_disp_vclks[] = { + VCLK(DOUT_CLK_DISP_NOCP, + DIV_CLK_DISP_NOCP, + "DOUT_CLK_DISP_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_g2d_vclks[] = { + VCLK(DOUT_CLK_G2D_NOCP, + DIV_CLK_G2D_NOCP, + "DOUT_CLK_G2D_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_hsi0_vclks[] = { + VCLK(DOUT_CLK_HSI0_USB31DRD, + DIV_CLK_HSI0_USB31DRD, + "DOUT_CLK_HSI0_USB31DRD", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_csis_vclks[] = { + VCLK(DOUT_CLK_CSIS_NOCP, + DIV_CLK_CSIS_NOCP, + "DOUT_CLK_CSIS_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_pdp_vclks[] = { + VCLK(DOUT_CLK_PDP_NOCP, + DIV_CLK_PDP_NOCP, + "DOUT_CLK_PDP_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_ipp_vclks[] = { + VCLK(DOUT_CLK_IPP_NOCP, + DIV_CLK_IPP_NOCP, + "DOUT_CLK_IPP_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_g3aa_vclks[] = { + VCLK(DOUT_CLK_G3AA_NOCP, + DIV_CLK_G3AA_NOCP, + "DOUT_CLK_G3AA_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_itp_vclks[] = { + VCLK(DOUT_CLK_ITP_NOCP, + DIV_CLK_ITP_NOCP, + "DOUT_CLK_ITP_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_dns_vclks[] = { + VCLK(DOUT_CLK_DNS_NOCP, + DIV_CLK_DNS_NOCP, + "DOUT_CLK_DNS_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_tnr_vclks[] = { + VCLK(DOUT_CLK_TNR_NOCP, + DIV_CLK_TNR_NOCP, + "DOUT_CLK_TNR_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_mcsc_vclks[] = { + VCLK(DOUT_CLK_MCSC_NOCP, + DIV_CLK_MCSC_NOCP, + "DOUT_CLK_MCSC_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_gdc_vclks[] = { + VCLK(DOUT_CLK_GDC_NOCP, + DIV_CLK_GDC_NOCP, + "DOUT_CLK_GDC_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_mfc_vclks[] = { + VCLK(DOUT_CLK_MFC_NOCP, + DIV_CLK_MFC_NOCP, + "DOUT_CLK_MFC_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_misc_vclks[] = { + VCLK(DOUT_CLK_MISC_NOCP, + DIV_CLK_MISC_NOCP, + "DOUT_CLK_MISC_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_top_vclks[] = { + VCLK(VDOUT_CLK_TOP_HSI0_NOC, + CLKCMU_HSI0_NOC, + "VDOUT_CLK_TOP_HSI0_NOC", + 0, + 0, + NULL), + VCLK(CIS_CLK0, + CLKCMU_CIS_CLK0, + "CIS_CLK0", + 0, + 0, + NULL), + VCLK(CIS_CLK1, + CLKCMU_CIS_CLK1, + "CIS_CLK1", + 0, + 0, + NULL), + VCLK(CIS_CLK2, + CLKCMU_CIS_CLK2, + "CIS_CLK2", + 0, + 0, + NULL), + VCLK(CIS_CLK3, + CLKCMU_CIS_CLK3, + "CIS_CLK3", + 0, + 0, + NULL), + VCLK(CIS_CLK4, + CLKCMU_CIS_CLK4, + "CIS_CLK4", + 0, + 0, + NULL), + VCLK(CIS_CLK5, + CLKCMU_CIS_CLK5, + "CIS_CLK5", + 0, + 0, + NULL), + VCLK(CIS_CLK6, + CLKCMU_CIS_CLK6, + "CIS_CLK6", + 0, + 0, + NULL), + VCLK(CIS_CLK7, + CLKCMU_CIS_CLK7, + "CIS_CLK7", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_hsi2_vclks[] = { + VCLK(DOUT_CLKCMU_HSI2_MMC_CARD, + CLKCMU_HSI2_MMC_CARD, + "DOUT_CLKCMU_HSI2_MMC_CARD", + 0, + 0, + NULL), + VCLK(UFS_EMBD, + CLKCMU_HSI2_UFS_EMBD, + "UFS_EMBD", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_peric0_vclks[] = { + VCLK(VDOUT_CLK_PERIC0_USI0_UART, + VCLK_DIV_CLK_PERIC0_USI0_UART, + "VDOUT_CLK_PERIC0_USI0_UART", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI1_USI, + VCLK_DIV_CLK_PERIC0_USI1_USI, + "VDOUT_CLK_PERIC0_USI1_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI2_USI, + VCLK_DIV_CLK_PERIC0_USI2_USI, + "VDOUT_CLK_PERIC0_USI2_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI3_USI, + VCLK_DIV_CLK_PERIC0_USI3_USI, + "VDOUT_CLK_PERIC0_USI3_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI4_USI, + VCLK_DIV_CLK_PERIC0_USI4_USI, + "VDOUT_CLK_PERIC0_USI4_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI5_USI, + VCLK_DIV_CLK_PERIC0_USI5_USI, + "VDOUT_CLK_PERIC0_USI5_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI6_USI, + VCLK_DIV_CLK_PERIC0_USI6_USI, + "VDOUT_CLK_PERIC0_USI6_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI7_USI, + VCLK_DIV_CLK_PERIC0_USI7_USI, + "VDOUT_CLK_PERIC0_USI7_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI8_USI, + VCLK_DIV_CLK_PERIC0_USI8_USI, + "VDOUT_CLK_PERIC0_USI8_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_USI14_USI, + VCLK_DIV_CLK_PERIC0_USI14_USI, + "VDOUT_CLK_PERIC0_USI14_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC0_I3C, + DIV_CLK_PERIC0_I3C, + "VDOUT_CLK_PERIC0_I3C", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_peric1_vclks[] = { + VCLK(VDOUT_CLK_PERIC1_USI0_USI, + VCLK_DIV_CLK_PERIC1_USI0_USI, + "VDOUT_CLK_PERIC1_USI0_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI9_USI, + VCLK_DIV_CLK_PERIC1_USI9_USI, + "VDOUT_CLK_PERIC1_USI9_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI10_USI, + VCLK_DIV_CLK_PERIC1_USI10_USI, + "VDOUT_CLK_PERIC1_USI10_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI11_USI, + VCLK_DIV_CLK_PERIC1_USI11_USI, + "VDOUT_CLK_PERIC1_USI11_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI12_USI, + VCLK_DIV_CLK_PERIC1_USI12_USI, + "VDOUT_CLK_PERIC1_USI12_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI13_USI, + VCLK_DIV_CLK_PERIC1_USI13_USI, + "VDOUT_CLK_PERIC1_USI13_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_I3C, + VCLK_DIV_CLK_PERIC1_I3C, + "VDOUT_CLK_PERIC1_I3C", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI15_USI, + VCLK_DIV_CLK_PERIC1_USI15_USI, + "VDOUT_CLK_PERIC1_USI15_USI", + 0, + 0, + NULL), + VCLK(VDOUT_CLK_PERIC1_USI16_USI, + VCLK_DIV_CLK_PERIC1_USI16_USI, + "VDOUT_CLK_PERIC1_USI16_USI", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_tpu_vclks[] = { + VCLK(DOUT_CLK_TPU_TPU, + DIV_CLK_TPU_TPU, + "DOUT_CLK_TPU_TPU", + 0, + 0, + NULL), + VCLK(DOUT_CLK_TPU_TPUCTL, + DIV_CLK_TPU_TPUCTL, + "DOUT_CLK_TPU_TPUCTL", + 0, + 0, + NULL), + VCLK(DOUT_CLK_TPU_NOCP, + DIV_CLK_TPU_NOCP, + "DOUT_CLK_TPU_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_bo_vclks[] = { + VCLK(DOUT_CLK_BO_NOCP, + DIV_CLK_BO_NOCP, + "DOUT_CLK_BO_NOCP", + 0, + 0, + NULL), +}; + +static struct init_vclk gs201_clkout_vclks[] = { + VCLK(CLKOUT1, + VCLK_CLKOUT1, + "CLKOUT1", + 0, + 0, + NULL), + VCLK(CLKOUT0, + VCLK_CLKOUT0, + "CLKOUT0", + 0, + 0, + NULL), +}; + +#ifdef CONFIG_DEBUG_FS +static int pad_clkout0_get(void *data, u64 *val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_PRIV_REG, PAD_CTRL_CLKOUT0, + PRIV_REG_OPTION_READ, 0, 0, 0, 0, 0, &res); + *val = (u64)(res.a0 & 0xFFFFFFFFUL); + + return 0; +} + +static int pad_clkout0_set(void *data, u64 val) +{ + int ret = 0; + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_PRIV_REG, PAD_CTRL_CLKOUT0, + PRIV_REG_OPTION_WRITE, val, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + pr_err("error writing to pad_clkout0 err=%lu\n", res.a0); + ret = res.a0; + } + + return ret; +} + +static int pad_clkout1_get(void *data, u64 *val) +{ + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_PRIV_REG, PAD_CTRL_CLKOUT1, + PRIV_REG_OPTION_READ, 0, 0, 0, 0, 0, &res); + *val = (u64)(res.a0 & 0xFFFFFFFFUL); + + return 0; +} + +static int pad_clkout1_set(void *data, u64 val) +{ + int ret = 0; + struct arm_smccc_res res; + + arm_smccc_smc(SMC_CMD_PRIV_REG, PAD_CTRL_CLKOUT1, + PRIV_REG_OPTION_WRITE, val, 0, 0, 0, 0, &res); + if (res.a0 != 0) { + pr_err("error writing to pad_clkout1 err=%lu\n", res.a0); + ret = res.a0; + } + + return ret; +} + +static int clkout_addr_get(void *data, u64 *val) +{ + struct samsung_clk_provider *scp = data; + *val = scp->clkout_addr; + return 0; +} + +static int clkout_addr_set(void *data, u64 val) +{ + int i; + struct samsung_clk_provider *scp = data; + + for (i = 0; i < ARRAY_SIZE(clkout_addresses); i++) + if (clkout_addresses[i] == val) + break; + + if (i >= ARRAY_SIZE(clkout_addresses)) { + pr_err("error address not found\n"); + return -ENODEV; + } + + scp->clkout_addr = val; + + return 0; +} + +static int clkout_val_get(void *data, u64 *val) +{ + u32 __iomem *addr; + struct samsung_clk_provider *scp = data; + + addr = ioremap(scp->clkout_addr, SZ_4); + *val = (u64)ioread32(addr); + + return 0; +} + +static int clkout_val_set(void *data, u64 val) +{ + u32 __iomem *addr; + struct samsung_clk_provider *scp = data; + + addr = ioremap(scp->clkout_addr, SZ_4); + iowrite32((u32)val, addr); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(pad_clkout0_fops, pad_clkout0_get, + pad_clkout0_set, "0x%08llx\n"); + +DEFINE_DEBUGFS_ATTRIBUTE(pad_clkout1_fops, pad_clkout1_get, + pad_clkout1_set, "0x%08llx\n"); + +DEFINE_DEBUGFS_ATTRIBUTE(clkout_addr_fops, clkout_addr_get, + clkout_addr_set, "0x%16llx\n"); + +DEFINE_DEBUGFS_ATTRIBUTE(clkout_val_fops, clkout_val_get, + clkout_val_set, "0x%08llx\n"); + +#endif + +static const struct of_device_id ext_clk_match[] = { + {.compatible = "samsung,gs201-oscclk", .data = (void *)0}, + {}, +}; + +static int gs201_clock_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + void __iomem *reg_base; +#ifdef CONFIG_DEBUG_FS + struct dentry *root; +#endif + + if (!np) + panic("%s: unable to determine soc\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + gs201_clk_provider = samsung_clk_init(np, reg_base, CLK_NR_CLKS); + if (!gs201_clk_provider) + panic("%s: unable to allocate context.\n", __func__); + + samsung_register_of_fixed_ext(gs201_clk_provider, + gs201_fixed_rate_ext_clks, + ARRAY_SIZE(gs201_fixed_rate_ext_clks), + ext_clk_match); + + /* register HWACG vclk */ + samsung_register_vclk(gs201_clk_provider, + gs201_apm_hwacg_vclks, + ARRAY_SIZE(gs201_apm_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_aur_hwacg_vclks, + ARRAY_SIZE(gs201_aur_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_top_hwacg_vclks, + ARRAY_SIZE(gs201_top_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl0_hwacg_vclks, + ARRAY_SIZE(gs201_nocl0_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl1a_hwacg_vclks, + ARRAY_SIZE(gs201_nocl1a_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl1b_hwacg_vclks, + ARRAY_SIZE(gs201_nocl1b_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl2a_hwacg_vclks, + ARRAY_SIZE(gs201_nocl2a_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_eh_hwacg_vclks, + ARRAY_SIZE(gs201_eh_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_g3d_hwacg_vclks, + ARRAY_SIZE(gs201_g3d_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_dpu_hwacg_vclks, + ARRAY_SIZE(gs201_dpu_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_disp_hwacg_vclks, + ARRAY_SIZE(gs201_disp_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_g2d_hwacg_vclks, + ARRAY_SIZE(gs201_g2d_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_hsi0_hwacg_vclks, + ARRAY_SIZE(gs201_hsi0_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_hsi1_hwacg_vclks, + ARRAY_SIZE(gs201_hsi1_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_hsi2_hwacg_vclks, + ARRAY_SIZE(gs201_hsi2_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_csis_hwacg_vclks, + ARRAY_SIZE(gs201_csis_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_pdp_hwacg_vclks, + ARRAY_SIZE(gs201_pdp_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_ipp_hwacg_vclks, + ARRAY_SIZE(gs201_ipp_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_g3aa_hwacg_vclks, + ARRAY_SIZE(gs201_g3aa_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_itp_hwacg_vclks, + ARRAY_SIZE(gs201_itp_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_dns_hwacg_vclks, + ARRAY_SIZE(gs201_dns_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_tnr_hwacg_vclks, + ARRAY_SIZE(gs201_tnr_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_mcsc_hwacg_vclks, + ARRAY_SIZE(gs201_mcsc_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_gdc_hwacg_vclks, + ARRAY_SIZE(gs201_gdc_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_mfc_hwacg_vclks, + ARRAY_SIZE(gs201_mfc_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_mif_hwacg_vclks, + ARRAY_SIZE(gs201_mif_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_misc_hwacg_vclks, + ARRAY_SIZE(gs201_misc_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_peric0_hwacg_vclks, + ARRAY_SIZE(gs201_peric0_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_peric1_hwacg_vclks, + ARRAY_SIZE(gs201_peric1_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_tpu_hwacg_vclks, + ARRAY_SIZE(gs201_tpu_hwacg_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_bo_hwacg_vclks, + ARRAY_SIZE(gs201_bo_hwacg_vclks)); + + /* register special vclk */ + samsung_register_vclk(gs201_clk_provider, + gs201_apm_vclks, + ARRAY_SIZE(gs201_apm_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_aur_vclks, + ARRAY_SIZE(gs201_aur_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl0_vclks, + ARRAY_SIZE(gs201_nocl0_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl1a_vclks, + ARRAY_SIZE(gs201_nocl1a_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl1b_vclks, + ARRAY_SIZE(gs201_nocl1b_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_nocl2a_vclks, + ARRAY_SIZE(gs201_nocl2a_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_eh_vclks, + ARRAY_SIZE(gs201_eh_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_dpu_vclks, + ARRAY_SIZE(gs201_dpu_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_disp_vclks, + ARRAY_SIZE(gs201_disp_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_g2d_vclks, + ARRAY_SIZE(gs201_g2d_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_hsi0_vclks, + ARRAY_SIZE(gs201_hsi0_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_csis_vclks, + ARRAY_SIZE(gs201_csis_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_pdp_vclks, + ARRAY_SIZE(gs201_pdp_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_ipp_vclks, + ARRAY_SIZE(gs201_ipp_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_g3aa_vclks, + ARRAY_SIZE(gs201_g3aa_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_itp_vclks, + ARRAY_SIZE(gs201_itp_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_dns_vclks, + ARRAY_SIZE(gs201_dns_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_tnr_vclks, + ARRAY_SIZE(gs201_tnr_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_mcsc_vclks, + ARRAY_SIZE(gs201_mcsc_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_gdc_vclks, + ARRAY_SIZE(gs201_gdc_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_mfc_vclks, + ARRAY_SIZE(gs201_mfc_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_misc_vclks, + ARRAY_SIZE(gs201_misc_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_top_vclks, + ARRAY_SIZE(gs201_top_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_hsi2_vclks, + ARRAY_SIZE(gs201_hsi2_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_peric0_vclks, + ARRAY_SIZE(gs201_peric0_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_peric1_vclks, + ARRAY_SIZE(gs201_peric1_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_tpu_vclks, + ARRAY_SIZE(gs201_tpu_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_bo_vclks, + ARRAY_SIZE(gs201_bo_vclks)); + samsung_register_vclk(gs201_clk_provider, + gs201_clkout_vclks, + ARRAY_SIZE(gs201_clkout_vclks)); + + clk_register_fixed_factor(NULL, + "pwm-clock", + "fin_pll", + CLK_SET_RATE_PARENT, + 1, + 1); + + samsung_clk_of_add_provider(np, gs201_clk_provider); + +#ifdef CONFIG_DEBUG_FS + root = debugfs_create_dir("xclkout", NULL); + debugfs_create_file("pad_clkout0", 0644, root, gs201_clk_provider, + &pad_clkout0_fops); + debugfs_create_file("pad_clkout1", 0644, root, gs201_clk_provider, + &pad_clkout1_fops); + debugfs_create_file("clkout_addr", 0644, root, gs201_clk_provider, + &clkout_addr_fops); + debugfs_create_file("clkout_val", 0644, root, gs201_clk_provider, + &clkout_val_fops); +#endif + + pr_info("GS201: Clock setup completed\n"); + + return 0; +} + +static const struct of_device_id of_exynos_clock_match[] = { + { .compatible = "samsung,gs201-clock", }, + { }, +}; +MODULE_DEVICE_TABLE(of, of_exynos_clock_match); + +static const struct platform_device_id exynos_clock_ids[] = { + { "gs201-clock", }, + { } +}; + +static struct platform_driver gs201_clock_driver = { + .driver = { + .name = "gs201_clock", + .of_match_table = of_exynos_clock_match, + }, + .probe = gs201_clock_probe, + .id_table = exynos_clock_ids, +}; + +module_platform_driver(gs201_clock_driver); + +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/samsung/composite.h b/drivers/clk/samsung/composite.h index 655a1fc2b92a..2072511c9a89 100644 --- a/drivers/clk/samsung/composite.h +++ b/drivers/clk/samsung/composite.h @@ -23,6 +23,9 @@ struct samsung_clk_provider { void __iomem *reg_base; struct clk_onecell_data clk_data; spinlock_t lock; +#ifdef CONFIG_DEBUG_FS + phys_addr_t clkout_addr; +#endif }; /* diff --git a/drivers/cpufreq/exynos-acme.c b/drivers/cpufreq/exynos-acme.c index 493408eb96bb..3d61705811ee 100644 --- a/drivers/cpufreq/exynos-acme.c +++ b/drivers/cpufreq/exynos-acme.c @@ -27,11 +27,19 @@ #include #include #include +#include #include #include "exynos-acme.h" #include "../soc/google/vh/kernel/systrace.h" + +#if IS_ENABLED(CONFIG_PIXEL_EM) +#include "../soc/google/vh/include/pixel_em.h" +struct pixel_em_profile **exynos_acme_pixel_em_profile; +EXPORT_SYMBOL_GPL(exynos_acme_pixel_em_profile); +#endif + /* * list head of cpufreq domain */ @@ -188,6 +196,81 @@ static int scale(struct exynos_cpufreq_domain *domain, return ret; } +/********************************************************************* + * THERMAL PRESSURE * + *********************************************************************/ +/* + * When device thermals throttle the CPUs, we notify the scheduler of + * capacity change using the thermal pressure APIs + */ +static void update_thermal_pressure(struct exynos_cpufreq_domain *domain, int dfs_count_change) +{ + cpumask_t *maskp = &domain->cpus; + struct cpufreq_policy *policy = cpufreq_cpu_get(cpumask_first(maskp)); + unsigned long max_capacity, min_capacity, capacity; +#if IS_ENABLED(CONFIG_PIXEL_EM) + struct pixel_em_profile **profile_ptr_snapshot, *profile = NULL; + struct pixel_em_cluster *em_cluster; + int i; +#endif + + if (!policy) + return; + + max_capacity = arch_scale_cpu_capacity(cpumask_first(maskp)); + min_capacity = (policy->cpuinfo.min_freq * max_capacity) / (policy->cpuinfo.max_freq); + capacity = (policy->max * max_capacity) / (policy->cpuinfo.max_freq); + + spin_lock(&domain->thermal_update_lock); + domain->dfs_throttle_count += dfs_count_change; + + BUG_ON(domain->dfs_throttle_count < 0); + BUG_ON(domain->dfs_throttle_count > domain->max_dfs_count); + +#if IS_ENABLED(CONFIG_PIXEL_EM) + profile_ptr_snapshot = READ_ONCE(exynos_acme_pixel_em_profile); + + if (profile_ptr_snapshot) + profile = READ_ONCE(*profile_ptr_snapshot); + + if (profile) { + em_cluster = profile->cpu_to_cluster[cpumask_first(maskp)]; + for (i = 0; i < em_cluster->num_opps - 1; i++) { + if (em_cluster->opps[i].freq >= policy->max) + break; + } + capacity = (domain->dfs_throttle_count > 0) ? + em_cluster->opps[0].capacity : em_cluster->opps[i].capacity; + } else { + capacity = (domain->dfs_throttle_count > 0) ? min_capacity : capacity; + } +#else + capacity = (domain->dfs_throttle_count > 0) ? min_capacity : capacity; +#endif + + arch_set_thermal_pressure(maskp, max_capacity - capacity); + spin_unlock(&domain->thermal_update_lock); + + cpufreq_cpu_put(policy); +} + +static void exynos_cpufreq_set_thermal_dfs_cb(cpumask_t *maskp, bool is_dfs_throttled) +{ + unsigned int cpu; + cpumask_t cpu_per_domain = CPU_MASK_NONE; + + /* create a mask with one cpu per domain */ + for_each_cpu_and(cpu, maskp, cpu_possible_mask) { + struct exynos_cpufreq_domain *domain = find_domain(cpu); + cpumask_set_cpu(cpumask_first(&domain->cpus), &cpu_per_domain); + } + + /* apply thermal pressure for each domain */ + for_each_cpu(cpu, &cpu_per_domain) { + update_thermal_pressure(find_domain(cpu), (is_dfs_throttled ? 1 : -1)); + } +} + /********************************************************************* * EXYNOS CPUFREQ DRIVER INTERFACE * *********************************************************************/ @@ -273,7 +356,6 @@ static int exynos_cpufreq_verify(struct cpufreq_policy_data *new_policy) struct cpufreq_policy policy; unsigned int min_freq, max_freq; int index, ret; - unsigned long max_capacity, capacity; if (!domain) return -EINVAL; @@ -306,12 +388,7 @@ static int exynos_cpufreq_verify(struct cpufreq_policy_data *new_policy) ret = cpufreq_frequency_table_verify(new_policy, domain->freq_table); if (!ret) { - max_capacity = arch_scale_cpu_capacity(cpumask_first(&domain->cpus)); - capacity = new_policy->max * max_capacity; - capacity /= new_policy->cpuinfo.max_freq; - arch_set_thermal_pressure(&domain->cpus, max_capacity - capacity); - pr_debug_ratelimited("thermal pressure: %lu, cpus: %*pbl\n", - max_capacity - capacity, cpumask_pr_args(&domain->cpus)); + update_thermal_pressure(domain, 0); } return ret; } @@ -578,8 +655,54 @@ static ssize_t freq_qos_max_store(struct device *dev, return count; } +static ssize_t min_freq_qos_list_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + int total_requests = 0; + struct exynos_cpufreq_domain *domain; + struct plist_node *min_freq_pos; + + list_for_each_entry(domain, &domains, list) { + total_requests = 0; + list_for_each_entry(min_freq_pos, + &domain->min_qos_req.qos->min_freq.list.node_list, node_list) { + total_requests += 1; + len += sysfs_emit_at(buf, len, "cpu%d: total_requests: %d," + " min_freq_qos: %d\n", + cpumask_first(&domain->cpus), + total_requests, min_freq_pos->prio); + } + } + return len; +} + +static ssize_t max_freq_qos_list_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + ssize_t len = 0; + int total_requests = 0; + struct exynos_cpufreq_domain *domain; + struct plist_node *max_freq_pos; + + list_for_each_entry(domain, &domains, list) { + total_requests = 0; + list_for_each_entry(max_freq_pos, + &domain->max_qos_req.qos->max_freq.list.node_list, node_list) { + total_requests += 1; + len += sysfs_emit_at(buf, len, "cpu%d: total_requests: %d," + " max_freq_qos: %d\n", + cpumask_first(&domain->cpus), + total_requests, max_freq_pos->prio); + } + } + return len; +} + static DEVICE_ATTR_RW(freq_qos_max); static DEVICE_ATTR_RW(freq_qos_min); +static DEVICE_ATTR_RO(min_freq_qos_list); +static DEVICE_ATTR_RO(max_freq_qos_list); /********************************************************************* * CPUFREQ DEV FOPS * @@ -927,6 +1050,19 @@ static void freq_qos_release(struct work_struct *work) freq_qos_update_request(&domain->max_qos_req, domain->max_freq); } +static int +init_user_freq_qos(struct exynos_cpufreq_domain *domain, struct cpufreq_policy *policy) +{ + int ret = freq_qos_add_request(&policy->constraints, &domain->user_min_qos_req, + FREQ_QOS_MIN, domain->min_freq); + if (ret < 0) + return ret; + + ret = freq_qos_add_request(&policy->constraints, &domain->user_max_qos_req, + FREQ_QOS_MAX, domain->soft_max_freq); + return ret; +} + static int init_freq_qos(struct exynos_cpufreq_domain *domain, struct cpufreq_policy *policy) { @@ -944,16 +1080,6 @@ init_freq_qos(struct exynos_cpufreq_domain *domain, struct cpufreq_policy *polic if (ret < 0) return ret; - ret = freq_qos_add_request(&policy->constraints, &domain->user_min_qos_req, - FREQ_QOS_MIN, domain->min_freq); - if (ret < 0) - return ret; - - ret = freq_qos_add_request(&policy->constraints, &domain->user_max_qos_req, - FREQ_QOS_MAX, domain->max_freq); - if (ret < 0) - return ret; - /* Skip pm_qos if setting exists in device tree */ if (of_property_read_bool(dn, "skip-boot-pmqos")) { pr_info("Skipping boot pm_qos domain%d\n", domain->id); @@ -1072,14 +1198,18 @@ static int init_domain(struct exynos_cpufreq_domain *domain, * to bigger one. */ domain->max_freq = cal_dfs_get_max_freq(domain->cal_id); + domain->soft_max_freq = domain->max_freq; domain->min_freq = cal_dfs_get_min_freq(domain->cal_id); if (!of_property_read_u32(dn, "max-freq", &val)) - domain->max_freq = min(domain->max_freq, val); + domain->max_freq = val; if (!of_property_read_u32(dn, "min-freq", &val)) domain->min_freq = max(domain->min_freq, val); if (!of_property_read_u32(dn, "resume-freq", &val)) resume_freq = max(domain->min_freq, val); + if (!of_property_read_u32(dn, "soft-max-freq", &val)) + domain->soft_max_freq = min(domain->max_freq, val); + domain->soft_max_freq = max(domain->soft_max_freq, domain->min_freq); domain->max_freq_qos = domain->max_freq; domain->min_freq_qos = domain->min_freq; @@ -1214,12 +1344,13 @@ static int init_domain(struct exynos_cpufreq_domain *domain, cal_dfs_get_resume_freq(domain->cal_id); domain->old = get_freq(domain); if (domain->old < domain->min_freq || domain->max_freq < domain->old) { - WARN(1, "Out-of-range freq(%dkhz) returned for domain%d in init time\n", + pr_info("Out-of-range freq(%dkhz) returned for domain%d in init time\n", domain->old, domain->id); domain->old = domain->boot_freq; } mutex_init(&domain->lock); + spin_lock_init(&domain->thermal_update_lock); /* * Initialize CPUFreq DVFS Manager @@ -1230,6 +1361,12 @@ static int init_domain(struct exynos_cpufreq_domain *domain, cpu_dev = get_cpu_device(cpumask_first(&domain->cpus)); dev_pm_opp_of_register_em(cpu_dev, &domain->cpus); + /* Get max-dfs-count per domain. Set to zero, if not configured*/ + if (of_property_read_u32(dn, "max-dfs-count", &domain->max_dfs_count)) { + pr_info("max-dfs-count not set for cpufreq-domain:%d, defaulting to 0\n", domain->id); + domain->max_dfs_count = 0; + } + pr_info("Complete to initialize cpufreq-domain%d\n", domain->id); return 0; @@ -1298,14 +1435,34 @@ static int exynos_cpufreq_probe(struct platform_device *pdev) return ret; } + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_min_freq_qos_list.attr); + if (ret) { + pr_err("failed to create min_freq_qos_list node\n"); + return ret; + } + + ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_max_freq_qos_list.attr); + if (ret) { + pr_err("failed to create max_freq_qos_list node\n"); + return ret; + } + list_for_each_entry(domain, &domains, list) { struct cpufreq_policy *policy; - enable_domain(domain); - policy = cpufreq_cpu_get_raw(cpumask_first(&domain->cpus)); - if (!policy) - continue; + if (!policy) { + pr_err("failed to find domain policy!\n"); + return -ENODEV; + } + + ret = init_user_freq_qos(domain, policy); + if (ret < 0) { + pr_err("Failed to set max user qos vote!\n"); + return ret; + } + + enable_domain(domain); #if IS_ENABLED(CONFIG_EXYNOS_CPU_THERMAL) exynos_cpufreq_cooling_register(domain->dn, policy); @@ -1323,6 +1480,7 @@ static int exynos_cpufreq_probe(struct platform_device *pdev) } register_pm_notifier(&exynos_cpufreq_pm); + register_dfs_throttle_cb(exynos_cpufreq_set_thermal_dfs_cb); pr_info("Initialized Exynos cpufreq driver\n"); diff --git a/drivers/cpufreq/exynos-acme.h b/drivers/cpufreq/exynos-acme.h index b6ac39c10c9f..f74b0a643f9a 100644 --- a/drivers/cpufreq/exynos-acme.h +++ b/drivers/cpufreq/exynos-acme.h @@ -66,6 +66,7 @@ struct exynos_cpufreq_domain { unsigned int boot_freq; unsigned int resume_freq; unsigned int old; + unsigned int soft_max_freq; /* freq qos */ struct freq_qos_request min_qos_req; @@ -84,6 +85,11 @@ struct exynos_cpufreq_domain { bool need_awake; struct thermal_cooling_device *cdev; + + /* Thermal pressure */ + int dfs_throttle_count; + unsigned int max_dfs_count; + spinlock_t thermal_update_lock; }; /* diff --git a/drivers/dma-buf/heaps/samsung/chunk_heap.c b/drivers/dma-buf/heaps/samsung/chunk_heap.c index 041c2088771a..debf126358d9 100644 --- a/drivers/dma-buf/heaps/samsung/chunk_heap.c +++ b/drivers/dma-buf/heaps/samsung/chunk_heap.c @@ -21,6 +21,7 @@ #include #include #include +#include #define GFP_CHUNK_HEAP_NORETRY_NOWARN (__GFP_NORETRY | __GFP_NOWARN) @@ -205,8 +206,10 @@ static struct dma_buf *chunk_heap_allocate(struct dma_heap *heap, unsigned long samsung_dma_buffer_free(buffer); err_buffer: if (!protret) { - for (pg = 0; pg < nr_chunks; pg++) + for (pg = 0; pg < nr_chunks; pg++) { cma_release(chunk_heap->cma, pages[pg], 1 << chunk_order); + dma_heap_dec_inuse(1 << chunk_order); + } } err_alloc: kvfree(pages); @@ -228,8 +231,10 @@ static void chunk_heap_release(struct samsung_dma_buffer *buffer) ret = chunk_heap_unprotect(buffer); if (!ret) { - for_each_sgtable_sg(table, sg, i) + for_each_sgtable_sg(table, sg, i) { cma_release(chunk_heap->cma, sg_page(sg), 1 << chunk_order); + dma_heap_dec_inuse(1 << chunk_order); + } } samsung_dma_buffer_free(buffer); } diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index bbf79a73a14a..b5d7e0932ef6 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -637,7 +637,7 @@ static void __iomem *of_dma_get_arwrapper_address(struct device_node *np, unsign if (!reg_list || num >= count) return NULL; - return ioremap(of_translate_address(np, reg_list + num), SZ_32); + return ioremap(be32_to_cpup(reg_list + num), SZ_32); } /** @@ -659,7 +659,7 @@ static void __iomem *of_dma_get_awwrapper_address(struct device_node *np, unsign if (!reg_list || num >= count) return NULL; - return ioremap(of_translate_address(np, reg_list + num), SZ_32); + return ioremap(be32_to_cpup(reg_list + num), SZ_32); } /** @@ -1834,7 +1834,7 @@ static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) if (desc->infiniteloop) pl330_tasklet((uintptr_t)pch); else - tasklet_schedule(&pch->task); + tasklet_hi_schedule(&pch->task); } static void pl330_dotask(unsigned long data) @@ -1982,6 +1982,7 @@ static int pl330_update(struct pl330_dmac *pl330) if (!descdone->infiniteloop) { thrd->req[active].desc = NULL; + thrd->req_running = -1; /* Get going again ASAP */ _start(thrd); @@ -2009,7 +2010,7 @@ static int pl330_update(struct pl330_dmac *pl330) || pl330->dmac_tbd.reset_mngr || pl330->dmac_tbd.reset_chan) { ret = 1; - tasklet_schedule(&pl330->tasks); + tasklet_hi_schedule(&pl330->tasks); } return ret; @@ -2362,7 +2363,7 @@ static inline void fill_queue(struct dma_pl330_chan *pch) desc->status = DONE; dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", __func__, __LINE__, desc->txd.cookie); - tasklet_schedule(&pch->task); + tasklet_hi_schedule(&pch->task); } } } diff --git a/drivers/gpu/exynos/g2d/g2d.h b/drivers/gpu/exynos/g2d/g2d.h index d266088fb111..79e4a3f7fa51 100644 --- a/drivers/gpu/exynos/g2d/g2d.h +++ b/drivers/gpu/exynos/g2d/g2d.h @@ -100,6 +100,8 @@ struct g2d_qos { #define G2D_DEVICE_CAPS_HDR10 BIT(7) /* Support HDR conversion for HDR10+ */ #define G2D_DEVICE_CAPS_HDR10PLUS BIT(8) +/*Support SBWC Lossy format */ +#define G2D_DEVICE_CAPS_SBWC_LOSSY BIT(9) struct g2d_device { unsigned long state; diff --git a/drivers/gpu/exynos/g2d/g2d_command.c b/drivers/gpu/exynos/g2d/g2d_command.c index 61272790925e..3d25a72b7b72 100644 --- a/drivers/gpu/exynos/g2d/g2d_command.c +++ b/drivers/gpu/exynos/g2d/g2d_command.c @@ -494,6 +494,9 @@ static inline bool is_afbc_aligned(u32 width, u32 height, bool dst, #define SBWC_HEADER_ALIGN 16 #define SBWC_PAYLOAD_ALIGN 32 +#define IS_SBWCL(sbwc) ((sbwc) & 1) +#define SBWCL_BLOCK_SIZE(sbwc) ((((sbwc) >> 4) & 0xF) << 5) + static u32 get_sbwc_stride(unsigned long caps, u32 stride, u32 align) { if (caps_has_align64(caps)) @@ -518,6 +521,49 @@ static u32 get_sbwc_stride_payload(unsigned long caps, u32 width, u32 bitdepth) return get_sbwc_stride(caps, stride, SBWC_PAYLOAD_ALIGN); } +static u32 get_sbwc_lossy_stride_payload(unsigned long caps, u32 width, u32 blocksize) +{ + u32 stride = (width / SBWC_BLOCK_WIDTH) * blocksize; + + return ALIGN(stride, SBWC_PAYLOAD_ALIGN); +} + +static u32 get_sbwc_lossy_payload_y_basis(unsigned long caps, u32 colormode, + u32 width, u32 height, u32 blocksize) +{ + u32 size = get_sbwc_lossy_stride_payload(caps, width, blocksize); + + return size * height / SBWC_BLOCK_HEIGHT; +} + +static u32 get_sbwc_lossy_payload_c_basis(unsigned long caps, u32 colormode, + u32 width, u32 height, u32 blocksize) +{ + u32 size = get_sbwc_lossy_stride_payload(caps, width, blocksize); + + if (IS_YUV420(colormode)) + height = ALIGN(height, 8); + return size * height / SBWC_BLOCK_HEIGHT; +} + +static u32 get_sbwc_lossy_y_size(unsigned long caps, u32 colormode, + u32 width, u32 height, u32 blocksize) +{ + u32 size = get_sbwc_lossy_payload_y_basis(caps, colormode, width, height, blocksize); + return size; +} + +static u32 get_sbwc_lossy_c_size(unsigned long caps, u32 colormode, + u32 width, u32 height, u32 blocksize) +{ + u32 size = get_sbwc_lossy_payload_c_basis(caps, colormode, width, height, blocksize); + + if (IS_YUV420(colormode)) + size = size / 2; + return size; +} + + /* * Buffer stride alignment and padding restriction of MFC * YCbCr semi-planar SBWC layout: @@ -618,7 +664,7 @@ static u32 get_sbwc_c_size(unsigned long caps, u32 colormode, unsigned int g2d_get_payload_index(struct g2d_reg cmd[], const struct g2d_fmt *fmt, unsigned int idx, unsigned int buffer_count, - unsigned long caps, u32 flags) + unsigned long caps, u32 flags, bool dst) { u32 width = cmd[G2DSFR_IMG_WIDTH].value; u32 height = cmd[G2DSFR_IMG_BOTTOM].value; @@ -628,8 +674,18 @@ unsigned int g2d_get_payload_index(struct g2d_reg cmd[], const struct g2d_fmt *f if (IS_SBWC(colormode)) { unsigned int dep = IS_YUV_P10(colormode, - caps & G2D_DEVICE_CAPS_YUV_BITDEPTH) ? 10 : 8; - + caps & G2D_DEVICE_CAPS_YUV_BITDEPTH) ? 10 : 8; + u32 sbwc = dst ? cmd[G2DSFR_DST_SBWCINFO].value : + cmd[G2DSFR_SRC_SBWCINFO].value; + unsigned int blocksize = SBWCL_BLOCK_SIZE(sbwc); + + if (IS_SBWCL(sbwc)) { + if (idx == 0) + return get_sbwc_lossy_y_size(caps, colormode, + width, height, blocksize); + return get_sbwc_lossy_c_size(caps, colormode, width, + height, blocksize); + } if (idx == 0) return get_sbwc_y_size(caps, colormode, width, height, dep); @@ -671,7 +727,7 @@ static size_t g2d_get_ycbcr_payload(const struct g2d_fmt *fmt, u32 flags, } size_t g2d_get_payload(struct g2d_reg cmd[], const struct g2d_fmt *fmt, - u32 flags, unsigned long cap) + u32 flags, unsigned long cap, bool dst) { size_t payload = 0; u32 mode = cmd[G2DSFR_IMG_COLORMODE].value; @@ -681,7 +737,16 @@ size_t g2d_get_payload(struct g2d_reg cmd[], const struct g2d_fmt *fmt, if (IS_SBWC(mode)) { unsigned int dep = IS_YUV_P10(mode, cap & G2D_DEVICE_CAPS_YUV_BITDEPTH) ? 10 : 8; - + u32 sbwc = dst ? cmd[G2DSFR_DST_SBWCINFO].value : + cmd[G2DSFR_SRC_SBWCINFO].value; + unsigned int blocksize = SBWCL_BLOCK_SIZE(sbwc); + + if (IS_SBWCL(sbwc)) { + return get_sbwc_lossy_y_size(cap, mode, + width, height, blocksize) + + get_sbwc_lossy_c_size(cap, mode, width, + height, blocksize); + } return get_sbwc_y_size(cap, mode, width, height, dep) + get_sbwc_c_size(cap, mode, width, height, dep); } else if (IS_AFBC(mode)) { @@ -825,6 +890,7 @@ static struct command_checker source_command_checker[G2DSFR_SRC_FIELD_COUNT] = { {"YPAYLOADSTRIDE", 0x00A4, 0x0000FFFF, NULL,}, {"CHEADERSTRIDE", 0x00A8, 0x00003FFF, NULL,}, {"CPAYLOADSTRIDE", 0x00AC, 0x0000FFFF, NULL,}, + {"SBWCINFO", 0x00B0, 0x000100F1, NULL,}, }; static struct command_checker target_command_checker[G2DSFR_DST_FIELD_COUNT] = { @@ -843,6 +909,7 @@ static struct command_checker target_command_checker[G2DSFR_DST_FIELD_COUNT] = { {"YPAYLOADSTRIDE", 0x0074, 0x0000FFFF, NULL,}, {"CHEADERSTRIDE", 0x0078, 0x00003FFF, NULL,}, {"CPAYLOADSTRIDE", 0x007C, 0x0000FFFF, NULL,}, + {"SBWCINFO", 0x0090, 0x000100F1, NULL,}, }; #define TARGET_OFFSET 0x120 @@ -1021,24 +1088,46 @@ static bool g2d_validate_image_format(struct g2d_device *g2d_dev, struct g2d_tas if (IS_SBWC(mode)) { int dep = IS_YUV_P10(mode, g2d_dev->caps & G2D_DEVICE_CAPS_YUV_BITDEPTH) ? 10 : 8; u32 offset = dst ? G2DSFR_DST_Y_HEADER_STRIDE : G2DSFR_SRC_Y_HEADER_STRIDE; - u32 hdr_strd = get_sbwc_stride_header(g2d_dev->caps, width); - u32 pld_strd = get_sbwc_stride_payload(g2d_dev->caps, width, dep); int i; - + u32 sbwc = dst ? commands[G2DSFR_DST_SBWCINFO].value : + commands[G2DSFR_SRC_SBWCINFO].value; + u32 hdr_strd; + u32 pld_strd; + unsigned int blocksize = SBWCL_BLOCK_SIZE(sbwc); + + if (IS_SBWCL(sbwc)) { + hdr_strd = 0; + pld_strd = get_sbwc_lossy_stride_payload(g2d_dev->caps, width, blocksize); + } else { + hdr_strd = get_sbwc_stride_header(g2d_dev->caps, width); + pld_strd = get_sbwc_stride_payload(g2d_dev->caps, width, dep); + } /* Stride is in the order : header, payload, header, payload */ for (i = 0; i < 4; i += 2) { if (commands[offset + i].value != hdr_strd || commands[offset + i + 1].value != pld_strd) { perrfndev(g2d_dev, - "Bad stride %u, %u for w %u mode %x", - commands[offset + i].value, - commands[offset + i + 1].value, - width, mode); + "Bad stride %u, %u for w %u mode %x", + commands[offset + i].value, + commands[offset + i + 1].value, + width, mode); return false; } } - + if (IS_SBWCL(sbwc)) { + if ((dep == 8) && (blocksize == 128)) { + perrfndev(g2d_dev, + "Bad SBWC Lossy (mode %x, info %x)", + mode, sbwc); + return false; + } + if (!(g2d_dev->caps & G2D_DEVICE_CAPS_SBWC_LOSSY)) { + perrfndev(g2d_dev, + "SBWC Lossy is not supported"); + return false; + } + } if (!(g2d_dev->caps & G2D_DEVICE_CAPS_SBWC)) { perrfndev(g2d_dev, "SBWC format is not supported"); return false; @@ -1373,6 +1462,18 @@ static u32 get_sbwc_c_base(unsigned long caps, struct g2d_layer *layer, get_sbwc_header_y_size(caps, mode, width, height); } +static u32 get_sbwc_lossy_c_base(unsigned long caps, struct g2d_layer *layer, + u32 blocksize, u32 mode) +{ + u32 width = layer_width(layer); + u32 height = layer_height(layer); + + if (layer->num_buffers == 2) + return layer->buffer[1].dma_addr; + return layer->buffer[0].dma_addr + + get_sbwc_lossy_y_size(caps, mode, width, height, blocksize); +} + /* * SBWC buffer layout: * Single buffer: luma payload, luma header, chroma payload, chroma header @@ -1386,6 +1487,11 @@ static unsigned int g2d_set_sbwc_buffer(struct g2d_task *task, struct g2d_reg *reg = (struct g2d_reg *)page_address(task->cmd_page); unsigned char *offsets = (base == TARGET_OFFSET) ? dst_sbwc_reg_offset : src_sbwc_reg_offset; + unsigned int sbwc = (base == TARGET_OFFSET) ? + layer->commands[G2DSFR_DST_SBWCINFO].value : + layer->commands[G2DSFR_SRC_SBWCINFO].value; + unsigned int blocksize = SBWCL_BLOCK_SIZE(sbwc); + u32 w = layer_width(layer); u32 h = layer_height(layer); u32 align = 32; @@ -1414,18 +1520,29 @@ static unsigned int g2d_set_sbwc_buffer(struct g2d_task *task, reg[cmd_cnt + 0].offset = BASE_REG_OFFSET(base, offsets, 0); reg[cmd_cnt + 0].value = layer->buffer[0].dma_addr; - reg[cmd_cnt + 1].offset = BASE_REG_OFFSET(base, offsets, 1); - reg[cmd_cnt + 1].value = reg[cmd_cnt + 0].value + - get_sbwc_payload_y_size(caps, colormode, - w, h, dep); + if (IS_SBWCL(sbwc)) { + reg[cmd_cnt + 1].offset = BASE_REG_OFFSET(base, offsets, 1); + reg[cmd_cnt + 1].value = reg[cmd_cnt + 0].value + 0; - reg[cmd_cnt + 2].offset = BASE_REG_OFFSET(base, offsets, 2); - reg[cmd_cnt + 2].value = get_sbwc_c_base(caps, layer, dep, colormode); + reg[cmd_cnt + 2].offset = BASE_REG_OFFSET(base, offsets, 2); + reg[cmd_cnt + 2].value = get_sbwc_lossy_c_base(caps, layer, blocksize, colormode); - reg[cmd_cnt + 3].offset = BASE_REG_OFFSET(base, offsets, 3); - reg[cmd_cnt + 3].value = reg[cmd_cnt + 2].value + - get_sbwc_payload_c_size(caps, colormode, - w, h, dep); + reg[cmd_cnt + 3].offset = BASE_REG_OFFSET(base, offsets, 3); + reg[cmd_cnt + 3].value = reg[cmd_cnt + 2].value + 0; + } else { + reg[cmd_cnt + 1].offset = BASE_REG_OFFSET(base, offsets, 1); + reg[cmd_cnt + 1].value = reg[cmd_cnt + 0].value + + get_sbwc_payload_y_size(caps, colormode, + w, h, dep); + + reg[cmd_cnt + 2].offset = BASE_REG_OFFSET(base, offsets, 2); + reg[cmd_cnt + 2].value = get_sbwc_c_base(caps, layer, dep, colormode); + + reg[cmd_cnt + 3].offset = BASE_REG_OFFSET(base, offsets, 3); + reg[cmd_cnt + 3].value = reg[cmd_cnt + 2].value + + get_sbwc_payload_c_size(caps, colormode, + w, h, dep); + } return cmd_cnt + 4; } diff --git a/drivers/gpu/exynos/g2d/g2d_command.h b/drivers/gpu/exynos/g2d/g2d_command.h index eb31edf66089..99993d23b93c 100644 --- a/drivers/gpu/exynos/g2d/g2d_command.h +++ b/drivers/gpu/exynos/g2d/g2d_command.h @@ -32,10 +32,10 @@ bool g2d_validate_source_commands(struct g2d_device *g2d_dev, bool g2d_validate_target_commands(struct g2d_device *g2d_dev, struct g2d_task *task); size_t g2d_get_payload(struct g2d_reg cmd[], const struct g2d_fmt *fmt, - u32 flags, unsigned long caps); + u32 flags, unsigned long caps, bool dst); unsigned int g2d_get_payload_index(struct g2d_reg cmd[], const struct g2d_fmt *fmt, unsigned int idx, unsigned int buffer_count, - unsigned long caps, u32 flags); + unsigned long caps, u32 flags, bool dst); bool g2d_prepare_source(struct g2d_task *task, struct g2d_layer *layer, int index); bool g2d_prepare_target(struct g2d_task *task); diff --git a/drivers/gpu/exynos/g2d/g2d_drv.c b/drivers/gpu/exynos/g2d/g2d_drv.c index eb297273975b..e65484c6eb49 100644 --- a/drivers/gpu/exynos/g2d/g2d_drv.c +++ b/drivers/gpu/exynos/g2d/g2d_drv.c @@ -943,6 +943,25 @@ const struct g2d_device_data g2d_gs101_data __initconst = { BIT(G2D_FMT_IDX_1010102), }; +const struct g2d_device_data g2d_gs201_data __initconst = { + .caps = G2D_DEVICE_CAPS_SELF_PROTECTION | G2D_DEVICE_CAPS_YUV_BITDEPTH | + G2D_DEVICE_CAPS_SBWC | G2D_DEVICE_CAPS_AFBC_V12 | + G2D_DEVICE_CAPS_POLYFILTER | G2D_DEVICE_CAPS_HDR10PLUS | G2D_DEVICE_CAPS_SBWC_LOSSY, + .max_layers = G2D_MAX_IMAGES_QUARTER, + .fmts_src = BIT(G2D_FMT_IDX_8888) | BIT(G2D_FMT_IDX_565) | + BIT(G2D_FMT_IDX_4444) | BIT(G2D_FMT_IDX_888) | + BIT(G2D_FMT_IDX_1555) | BIT(G2D_FMT_IDX_5551) | + BIT(G2D_FMT_IDX_YUV420SP) | BIT(G2D_FMT_IDX_YUV420P) | + BIT(G2D_FMT_IDX_YUV422SP) | BIT(G2D_FMT_IDX_2101010) | + BIT(G2D_FMT_IDX_1010102), + .fmts_dst = BIT(G2D_FMT_IDX_8888) | BIT(G2D_FMT_IDX_565) | + BIT(G2D_FMT_IDX_4444) | BIT(G2D_FMT_IDX_888) | + BIT(G2D_FMT_IDX_1555) | BIT(G2D_FMT_IDX_5551) | + BIT(G2D_FMT_IDX_YUV420SP) | BIT(G2D_FMT_IDX_YUV420P) | + BIT(G2D_FMT_IDX_YUV422SP) | BIT(G2D_FMT_IDX_2101010) | + BIT(G2D_FMT_IDX_1010102), +}; + static const struct of_device_id of_g2d_match[] __refconst = { { .compatible = "samsung,exynos9810-g2d", @@ -956,6 +975,9 @@ static const struct of_device_id of_g2d_match[] __refconst = { }, { .compatible = "samsung,gs101-g2d", .data = &g2d_gs101_data, + }, { + .compatible = "samsung,gs201-g2d", + .data = &g2d_gs201_data, }, {}, }; @@ -993,6 +1015,8 @@ static int g2d_probe(struct platform_device *pdev) return ret; } + dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + g2d_dev->clock = devm_clk_get(&pdev->dev, "gate"); if (PTR_ERR(g2d_dev->clock) == -ENOENT) { perrdev(g2d_dev, "'gate' not found. Ignoring clock gating..\n"); diff --git a/drivers/gpu/exynos/g2d/g2d_uapi.h b/drivers/gpu/exynos/g2d/g2d_uapi.h index e2b6b1794a75..e79d645b085d 100644 --- a/drivers/gpu/exynos/g2d/g2d_uapi.h +++ b/drivers/gpu/exynos/g2d/g2d_uapi.h @@ -41,6 +41,7 @@ enum g2dsfr_src_register { G2DSFR_SRC_Y_PAYLOAD_STRIDE, G2DSFR_SRC_C_HEADER_STRIDE, G2DSFR_SRC_C_PAYLOAD_STRIDE, + G2DSFR_SRC_SBWCINFO, G2DSFR_SRC_FIELD_COUNT }; @@ -52,6 +53,7 @@ enum g2dsfr_dst_register { G2DSFR_DST_Y_PAYLOAD_STRIDE, G2DSFR_DST_C_HEADER_STRIDE, G2DSFR_DST_C_PAYLOAD_STRIDE, + G2DSFR_DST_SBWCINFO, G2DSFR_DST_FIELD_COUNT, }; diff --git a/drivers/gpu/exynos/g2d/g2d_uapi_process.c b/drivers/gpu/exynos/g2d/g2d_uapi_process.c index 1a13fc00179b..a6243de7256c 100644 --- a/drivers/gpu/exynos/g2d/g2d_uapi_process.c +++ b/drivers/gpu/exynos/g2d/g2d_uapi_process.c @@ -27,7 +27,7 @@ perrfndev(dev, \ static int g2d_prepare_buffer(struct g2d_device *g2d_dev, struct g2d_layer *layer, - struct g2d_layer_data *data) + struct g2d_layer_data *data, bool dst) { const struct g2d_fmt *fmt = NULL; struct g2d_reg *cmd = layer->commands; @@ -56,7 +56,7 @@ static int g2d_prepare_buffer(struct g2d_device *g2d_dev, if (data->num_buffers > 1) { for (i = 0; i < data->num_buffers; i++) { payload = g2d_get_payload_index(cmd, fmt, i, data->num_buffers, - g2d_dev->caps, layer->flags); + g2d_dev->caps, layer->flags, dst); if (data->buffer[i].length < payload) { buferr_show(g2d_dev, i, payload, cmd[G2DSFR_IMG_WIDTH].value, @@ -71,7 +71,7 @@ static int g2d_prepare_buffer(struct g2d_device *g2d_dev, } } else { payload = (unsigned int)g2d_get_payload(cmd, fmt, layer->flags, - g2d_dev->caps); + g2d_dev->caps, dst); if (data->buffer[0].length < payload) { buferr_show(g2d_dev, 0, payload, cmd[G2DSFR_IMG_WIDTH].value, @@ -401,7 +401,7 @@ static int g2d_get_source(struct g2d_device *g2d_dev, struct g2d_task *task, return -EINVAL; } - ret = g2d_prepare_buffer(g2d_dev, layer, data); + ret = g2d_prepare_buffer(g2d_dev, layer, data, false); if (ret) return ret; @@ -548,7 +548,7 @@ static int g2d_get_target(struct g2d_device *g2d_dev, struct g2d_context *ctx, if (!g2d_validate_target_commands(g2d_dev, task)) return -EINVAL; - ret = g2d_prepare_buffer(g2d_dev, target, data); + ret = g2d_prepare_buffer(g2d_dev, target, data, true); if (ret) return ret; diff --git a/drivers/hid/hid-steam.c b/drivers/hid/hid-steam.c index a3b151b29bd7..fc616db4231b 100644 --- a/drivers/hid/hid-steam.c +++ b/drivers/hid/hid-steam.c @@ -134,6 +134,11 @@ static int steam_recv_report(struct steam_device *steam, int ret; r = steam->hdev->report_enum[HID_FEATURE_REPORT].report_id_hash[0]; + if (!r) { + hid_err(steam->hdev, "No HID_FEATURE_REPORT submitted - nothing to read\n"); + return -EINVAL; + } + if (hid_report_len(r) < 64) return -EINVAL; @@ -165,6 +170,11 @@ static int steam_send_report(struct steam_device *steam, int ret; r = steam->hdev->report_enum[HID_FEATURE_REPORT].report_id_hash[0]; + if (!r) { + hid_err(steam->hdev, "No HID_FEATURE_REPORT submitted - nothing to read\n"); + return -EINVAL; + } + if (hid_report_len(r) < 64) return -EINVAL; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index f2edee763223..74781eca790b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1421,7 +1421,7 @@ config I2C_FSI config I2C_ACPM tristate "I2C_ACPM driver" - depends on SOC_GS101 + depends on SOC_GS101 || SOC_GS201 help I2C ACPM driver on GS SoCs. diff --git a/drivers/iio/power/Kconfig b/drivers/iio/power/Kconfig index 18e52095fa53..7d6a76102983 100644 --- a/drivers/iio/power/Kconfig +++ b/drivers/iio/power/Kconfig @@ -7,9 +7,8 @@ menu "Power sensors" config ODPM tristate "ODPM driver for M/S PMICs" - depends on MFD_S2MPG10 - depends on MFD_S2MPG11 select DRV_SAMSUNG_PMIC + depends on (SOC_GS101 && MFD_S2MPG10 && MFD_S2MPG11) || (SOC_GS201 && MFD_S2MPG12 && MFD_S2MPG13) help Say Y here to enable the On-Device Power Monitor (ODPM) driver. The On-Device Power Monitor allows for rail-specific energy and power diff --git a/drivers/iio/power/odpm.c b/drivers/iio/power/odpm.c index 53b543daf6cc..3fb4d1d3097a 100644 --- a/drivers/iio/power/odpm.c +++ b/drivers/iio/power/odpm.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -26,11 +27,7 @@ #include #include -#include -#include -#include -#include -#include +#include #define ODPM_PRINT_ESTIMATED_CLOCK_SKEW 0 @@ -60,139 +57,40 @@ #define ODPM_FREQ_DECIMAL_UHZ_STR_LEN_MAX 6 #define ODPM_SAMPLING_FREQ_CHAR_LEN_MAX 20 -#define _SWITCH_METER_FUNC_VOID(info, func, args...) \ +#if IS_ENABLED(CONFIG_SOC_GS101) +#define _SWITCH_METER_FUNC(infop, ret, func, args...) \ do { \ - switch ((info)->chip.id) { \ - case ODPM_CHIP_S2MPG10: \ - s2mpg10_##func(args); \ - break; \ - case ODPM_CHIP_S2MPG11: \ - s2mpg11_##func(args); \ - break; \ - case ODPM_CHIP_COUNT: \ - break; \ - } \ - } while (0) - -#define _SWITCH_METER_FUNC(info, ret, func, args...) \ - do { \ - switch ((info)->chip.id) { \ - case ODPM_CHIP_S2MPG10: \ + switch ((info)->chip.hw_id) { \ + case ID_S2MPG10: \ ret = s2mpg10_##func(args); \ break; \ - case ODPM_CHIP_S2MPG11: \ + case ID_S2MPG11: \ ret = s2mpg11_##func(args); \ break; \ - case ODPM_CHIP_COUNT: \ + case ID_COUNT: \ break; \ } \ } while (0) +#endif + +#if IS_ENABLED(CONFIG_SOC_GS201) +#define _SWITCH_METER_FUNC(infop, ret, func, args...) \ + do { \ + switch ((infop)->chip.hw_id) { \ + case ID_S2MPG12: \ + ret = s2mpg12_##func(args); \ + break; \ + case ID_S2MPG13: \ + ret = s2mpg13_##func(args); \ + break; \ + case ID_COUNT: \ + break; \ + } \ + } while (0) +#endif #define SWITCH_METER_FUNC(info, ret, func, args...) \ _SWITCH_METER_FUNC(info, ret, func, info->meter, args) -#define SWITCH_METER_FUNC_VOID(info, func, args...) \ - _SWITCH_METER_FUNC_VOID(info, func, info->meter, args) - -/* At this moment, this driver supports a static 8 channels */ -#define ODPM_CHANNEL_MAX S2MPG1X_METER_CHANNEL_MAX -#define ODPM_BUCK_EN_BYTES S2MPG1X_METER_BUCKEN_BUF - -enum odpm_chip_id { - ODPM_CHIP_S2MPG10, - ODPM_CHIP_S2MPG11, - ODPM_CHIP_COUNT, -}; - -enum odpm_rail_type { - ODPM_RAIL_TYPE_REGULATOR_LDO, - ODPM_RAIL_TYPE_REGULATOR_BUCK, - ODPM_RAIL_TYPE_SHUNT, -}; - -enum odpm_sampling_rate_type { - ODPM_SAMPLING_RATE_INTERNAL, - ODPM_SAMPLING_RATE_EXTERNAL, - ODPM_SAMPLING_RATE_ALL, -}; - -struct odpm_rail_data { - /* Config */ - const char *name; - const char *schematic_name; - const char *subsys_name; - enum odpm_rail_type type; - u32 mux_select; - - /* Buck specific */ - int channel_en_byte_offset; - - /* External rail specific config */ - u32 shunt_uohms; - - /* Bucks and external rails */ - u8 channel_en_index; - - /* Data */ - u64 acc_power_uW_sec_cached; - u64 measurement_stop_ms; - u64 measurement_start_ms_cached; - - bool disable_in_sleep; -}; - -struct odpm_chip { - /* Config */ - const char *name; - enum odpm_chip_id id; - enum s2mpg1x_id hw_id; - int hw_rev; - u32 max_refresh_time_ms; - - int num_rails; - struct odpm_rail_data *rails; - - const u32 *sampling_rate_int_uhz; - int sampling_rate_int_count; - const u32 *sampling_rate_ext_uhz; - int sampling_rate_ext_count; - - s2mpg1x_int_samp_rate int_config_sampling_rate_i; - s2mpg1x_ext_samp_rate ext_config_sampling_rate_i; - - /* Data */ - u64 acc_timestamp_ms; - s2mpg1x_int_samp_rate int_sampling_rate_i; - s2mpg1x_ext_samp_rate ext_sampling_rate_i; - - bool rx_ext_config_confirmation; -}; - -struct odpm_channel_data { - int rail_i; - bool enabled; - - u64 measurement_start_ms; - u64 acc_power_uW_sec; -}; - -/** - * dynamic struct odpm_info - */ -struct odpm_info { - struct odpm_chip chip; - void *meter; /* Parent meter device data */ - struct i2c_client *i2c; - struct mutex lock; /* Global HW lock */ - - struct odpm_channel_data channels[ODPM_CHANNEL_MAX]; - - struct workqueue_struct *work_queue; - struct work_struct work_refresh; - struct timer_list timer_refresh; - - u64 last_poll_ktime_boot_ns; - bool sleeping; -}; /** * IIO driver specific channel configurations @@ -205,9 +103,14 @@ struct odpm_info { } static const struct iio_chan_spec s2mpg1x_single_channel[ODPM_CHANNEL_MAX] = { - ODPM_ACC_CHANNEL(0), ODPM_ACC_CHANNEL(1), ODPM_ACC_CHANNEL(2), - ODPM_ACC_CHANNEL(3), ODPM_ACC_CHANNEL(4), ODPM_ACC_CHANNEL(5), + ODPM_ACC_CHANNEL(0), ODPM_ACC_CHANNEL(1), + ODPM_ACC_CHANNEL(2), ODPM_ACC_CHANNEL(3), + ODPM_ACC_CHANNEL(4), ODPM_ACC_CHANNEL(5), ODPM_ACC_CHANNEL(6), ODPM_ACC_CHANNEL(7), +#if IS_ENABLED(CONFIG_SOC_GS201) + ODPM_ACC_CHANNEL(8), ODPM_ACC_CHANNEL(9), + ODPM_ACC_CHANNEL(10), ODPM_ACC_CHANNEL(11), +#endif }; static int odpm_take_snapshot(struct odpm_info *info); @@ -281,11 +184,13 @@ static int odpm_io_set_ext_channels_en(struct odpm_info *info, u8 channels) static int odpm_io_set_buck_channels_en(struct odpm_info *info, u8 *channels, int num_bytes) { +#if IS_ENABLED(CONFIG_SOC_GS101) /* Disable BUCK5M if necessary (A0-specific) */ if (info->chip.hw_id == ID_S2MPG10 && info->chip.hw_rev == S2MPG10_EVT0) { channels[0] &= ~0x10; } +#endif return s2mpg1x_meter_set_buck_channel_en(info->chip.hw_id, info->i2c, channels, num_bytes); @@ -295,7 +200,8 @@ static int odpm_io_send_blank_async(struct odpm_info *info, u64 *timestamp_capture) { return s2mpg1x_meter_set_async_blocking(info->chip.hw_id, info->i2c, - timestamp_capture); + timestamp_capture, + info->chip.int_sampling_rate_i); } static int odpm_io_update_ext_enable_bits(struct odpm_info *info) @@ -334,16 +240,20 @@ static int odpm_io_update_bucken_enable_bits(struct odpm_info *info, ODPM_BUCK_EN_BYTES); } -static void odpm_id_get_lpf_data(struct odpm_info *info, u32 *data) +static void odpm_io_set_lpf_mode(struct odpm_info *info, s2mpg1x_meter_mode mode) { - SWITCH_METER_FUNC_VOID(info, meter_read_lpf_data_reg, data); + s2mpg1x_meter_set_lpf_mode(info->chip.hw_id, info->i2c, mode); +} + +static void odpm_io_get_lpf_data(struct odpm_info *info, u32 *data) +{ + s2mpg1x_meter_read_lpf_data_reg(info->chip.hw_id, info->i2c, data); } static int odpm_io_write_lpf_reg(struct odpm_info *info, int ch, u8 data) { - return s2mpg1x_meter_set_lpf_coefficient(info->chip.hw_id, info->i2c, - ch, data); + return s2mpg1x_meter_set_lpf_coefficient(info->chip.hw_id, info->i2c, ch, data); } int odpm_configure_chip(struct odpm_info *info) @@ -354,6 +264,8 @@ int odpm_configure_chip(struct odpm_info *info) /* TODO(stayfan): b/156107234 * error conditions */ + pr_info("odpm: Configuring %s...\n", info->chip.name); + ret = odpm_io_set_int_sampling_rate(info, info->chip.int_config_sampling_rate_i); odpm_print_new_sampling_rate(info, ret, ODPM_SAMPLING_RATE_INTERNAL); @@ -374,9 +286,27 @@ int odpm_configure_chip(struct odpm_info *info) odpm_io_set_meter_on(info, true); odpm_io_set_ext_meter_on(info, true); + pr_info("odpm: Configuring %s...done\n", info->chip.name); + return 0; } +#if IS_ENABLED(CONFIG_SOC_GS201) +int odpm_meter_sw_reset(struct odpm_info *info) { + u8 mt_trim_reg = '\0'; + + if (info->chip.hw_id == ID_S2MPG12) + mt_trim_reg = S2MPG12_MT_TRIM_COMMON; + else if (info->chip.hw_id == ID_S2MPG13) + mt_trim_reg = S2MPG13_MT_TRIM_COMMON2; + + return s2mpg1x_meter_sw_reset(info->chip.hw_id, + info->i2c, + info->mt_trim, + mt_trim_reg); +} +#endif + int odpm_configure_start_measurement(struct odpm_info *info) { u64 timestamp_capture_ns = 0; @@ -387,7 +317,8 @@ int odpm_configure_start_measurement(struct odpm_info *info) info->last_poll_ktime_boot_ns = timestamp_capture_ns; - pr_info("odpm: Starting at timestamp (ms): %llu\n", + pr_info("odpm: %s: Starting at timestamp (ms): %llu\n", + info->chip.name, to_ms(timestamp_capture_ns)); /* Initialize boot measurement time to 0. This means that there will be @@ -409,19 +340,19 @@ int odpm_configure_start_measurement(struct odpm_info *info) return ret; } -void odpm_periodic_refresh_timeout(struct timer_list *t) +static enum alarmtimer_restart odpm_alarm_handler(struct alarm *alarm, ktime_t time) { - int ret; struct odpm_info *info = - container_of(t, struct odpm_info, timer_refresh); - ret = mod_timer(&info->timer_refresh, - jiffies + - msecs_to_jiffies(info->chip.max_refresh_time_ms)); - if (ret < 0) - pr_err("odpm: Refresh timer cannot be modified!\n"); + container_of(alarm, struct odpm_info, alarmtimer_refresh); + + __pm_stay_awake(info->ws); /* schedule the periodic reading from the chip */ queue_work(info->work_queue, &info->work_refresh); + alarm_start_relative(&info->alarmtimer_refresh, + ms_to_ktime(info->chip.max_refresh_time_ms)); + + return ALARMTIMER_NORESTART; } static void odpm_periodic_refresh_work(struct work_struct *work) @@ -434,6 +365,8 @@ static void odpm_periodic_refresh_work(struct work_struct *work) info->chip.name); else pr_info("odpm: Refreshed %s registers!\n", info->chip.name); + + __pm_relax(info->ws); } static void odpm_periodic_refresh_setup(struct odpm_info *info) @@ -443,14 +376,13 @@ static void odpm_periodic_refresh_setup(struct odpm_info *info) /* setup the latest moment for reading the regs before saturation */ /* register the timer */ - timer_setup(&info->timer_refresh, odpm_periodic_refresh_timeout, 0); - info->timer_refresh.expires = - jiffies + msecs_to_jiffies(info->chip.max_refresh_time_ms); - add_timer(&info->timer_refresh); + alarm_init(&info->alarmtimer_refresh, ALARM_BOOTTIME, odpm_alarm_handler); + alarm_start_relative(&info->alarmtimer_refresh, + ms_to_ktime(info->chip.max_refresh_time_ms)); } -static bool odpm_match_int_sampling_rate(struct odpm_info *info, u32 sampling_rate, - int *index) +static bool odpm_match_int_sampling_rate(struct odpm_info *info, + u32 sampling_rate, int *index) { bool success = false; int i; @@ -466,8 +398,8 @@ static bool odpm_match_int_sampling_rate(struct odpm_info *info, u32 sampling_ra return success; } -static bool odpm_match_ext_sampling_rate(struct odpm_info *info, u32 sampling_rate, - int *index) +static bool odpm_match_ext_sampling_rate(struct odpm_info *info, + u32 sampling_rate, int *index) { bool success = false; int i; @@ -715,7 +647,8 @@ static int odpm_parse_dt(struct device *dev, struct odpm_info *info) pr_err("odpm: cannot read sample rate value\n"); return -EINVAL; } - if (!odpm_match_int_sampling_rate(info, sampling_rate, &sampling_rate_i)) { + if (!odpm_match_int_sampling_rate(info, sampling_rate, + &sampling_rate_i)) { pr_err("odpm: cannot parse sample rate value %d\n", sampling_rate); return -EINVAL; @@ -727,7 +660,8 @@ static int odpm_parse_dt(struct device *dev, struct odpm_info *info) pr_err("odpm: cannot read external sample rate value\n"); return -EINVAL; } - if (!odpm_match_ext_sampling_rate(info, sampling_rate, &sampling_rate_i)) { + if (!odpm_match_ext_sampling_rate(info, sampling_rate, + &sampling_rate_i)) { pr_err("odpm: cannot parse external sample rate value %d\n", sampling_rate); return -EINVAL; @@ -748,43 +682,60 @@ static int odpm_parse_dt(struct device *dev, struct odpm_info *info) } /** - * @brief Return the specific rail's power/bit resolution + * @brief Return the specific rail's milli unit/bit resolution * - * @return u32 - the rail resolution in iq30 in mW/bit. Will return 0 if the - * resolution doesn't exist. + * @return u32 - the rail resolution in iq30 is in milli unit/bit. Will return 0 if + * the resolution doesn't exist. */ -static u32 odpm_get_resolution_mW_iq30(struct odpm_info *info, int rail_i) +static u32 odpm_get_resolution_milli_iq30(struct odpm_info *info, int rail_i, + s2mpg1x_meter_mode mode) { u32 ret = 0; switch (info->chip.rails[rail_i].type) { case ODPM_RAIL_TYPE_REGULATOR_BUCK: case ODPM_RAIL_TYPE_REGULATOR_LDO: - default: { - _SWITCH_METER_FUNC(info, ret, muxsel_to_power_resolution, - info->chip.rails[rail_i].mux_select); - - } break; - case ODPM_RAIL_TYPE_SHUNT: { - u64 resolution_W_iq60; - - /* Losing a fraction of resolution performing u64 divisions, - * as there is no support for 128 bit divisions - */ - resolution_W_iq60 = ((u64)EXTERNAL_RESOLUTION_VRAIL * - (u64)EXTERNAL_RESOLUTION_VSHUNT * - (u64)EXTERNAL_RESOLUTION_TRIM) / - info->chip.rails[rail_i].shunt_uohms; + default: + if (mode == S2MPG1X_METER_CURRENT) + _SWITCH_METER_FUNC(info, ret, + muxsel_to_current_resolution, + info->chip.rails[rail_i].mux_select); + else + _SWITCH_METER_FUNC(info, ret, + muxsel_to_power_resolution, + info->chip.rails[rail_i].mux_select); - /* Scale back to iq30 (with conversion to mW) */ - ret = _IQ30_to_int(resolution_W_iq60 * 1000); + break; + case ODPM_RAIL_TYPE_SHUNT: + { + u64 raw_unit_iq60; + + /* Losing a fraction of resolution performing u64 divisions, + * as there is no support for 128 bit divisions + */ + if (mode == S2MPG1X_METER_CURRENT) + raw_unit_iq60 = ((u64)EXTERNAL_RESOLUTION_VSHUNT) / + info->chip.rails[rail_i].shunt_uohms; + else + raw_unit_iq60 = ((u64)EXTERNAL_RESOLUTION_VRAIL * + (u64)EXTERNAL_RESOLUTION_VSHUNT * + (u64)EXTERNAL_RESOLUTION_TRIM) / + info->chip.rails[rail_i].shunt_uohms; - } break; + /* Scale back to iq30 (with conversion to milli) */ + ret = _IQ30_to_int(raw_unit_iq60 * 1000); + } + break; } return ret; } +static u32 odpm_get_resolution_mW_iq30(struct odpm_info *info, int rail_i) +{ + return odpm_get_resolution_milli_iq30(info, rail_i, S2MPG1X_METER_POWER); +} + static u64 odpm_calculate_uW_sec(struct odpm_info *info, int rail_i, u64 acc_data, u32 int_sampling_frequency_uhz) { @@ -824,10 +775,10 @@ static void odpm_print_clock_skew(struct odpm_info *info, u64 elapsed_ms, u64 ratio_u = (1000000 * uHz_estimated) / uHz; s64 pct_u = (((s64)ratio_u - (1 * 1000000)) * 100); - pr_info("odpm: %s: elapsed_ms: %d, acc_count: %d\n", info->chip.name, - elapsed_ms, acc_count); - pr_info("odpm: %s: internal clock skew: %d.%06d %%\n", info->chip.name, - pct_u / 1000000, abs(pct_u) % 1000000); + pr_info("odpm: %s: elapsed_ms: %lld, acc_count: %d\n", + info->chip.name, elapsed_ms, acc_count); + pr_info("odpm: %s: internal clock skew: %lld.%06lld %%\n", + info->chip.name, pct_u / 1000000, abs(pct_u) % 1000000); } #endif @@ -852,9 +803,8 @@ static u32 odpm_estimate_sampling_frequency(struct odpm_info *info, * otherwise we'd accumulate large quantization error. This may occur * nominally if two instantaneous requests are followed back-to-back. */ - if (acc_count < ODPM_MIN_INTERVAL_ACC_COUNT) { + if (acc_count < ODPM_MIN_INTERVAL_ACC_COUNT) return sampling_frequency_table_uhz; - } if (elapsed_ms == 0) { pr_err("odpm: %s: elapsed time is 0 ms\n", info->chip.name); @@ -924,9 +874,14 @@ static int odpm_refresh_registers(struct odpm_info *info, bool resume) timestamp_before_async = ktime_get_boottime_ns(); - SWITCH_METER_FUNC(info, ret, meter_load_measurement, - S2MPG1X_METER_POWER, acc_data, &acc_count, - ×tamp_after_async); + ret = s2mpg1x_meter_measure_acc(info->chip.hw_id, + info->i2c, + info->meter_lock, + S2MPG1X_METER_POWER, + acc_data, + &acc_count, + ×tamp_after_async, + info->chip.int_sampling_rate_i); if (ret < 0) { pr_err("odpm: %s: i2c error; count not measure interval\n", @@ -969,18 +924,16 @@ static int odpm_refresh_registers(struct odpm_info *info, bool resume) static int odpm_reset_timer(struct odpm_info *info) { - unsigned long future_timer = jiffies + - msecs_to_jiffies(info->chip.max_refresh_time_ms); - - /* re-schedule the work for the read registers timeout - * (to prevent chip regs saturation) - */ - int ret_timer = mod_timer(&info->timer_refresh, future_timer); - - if (ret_timer < 0) - pr_err("odpm: read timer can't be modified!\n"); - - return ret_timer; + int ret = alarm_cancel(&info->alarmtimer_refresh); + if (ret < 0) { + pr_err("odpm: cannot reset the refresh timer\n"); + return ret; + } else { + alarm_init(&info->alarmtimer_refresh, ALARM_BOOTTIME, odpm_alarm_handler); + alarm_start_relative(&info->alarmtimer_refresh, + ms_to_ktime(info->chip.max_refresh_time_ms)); + } + return ret; } static int odpm_take_snapshot(struct odpm_info *info) @@ -1182,8 +1135,8 @@ static void odpm_print_new_sampling_rate(struct odpm_info *info, int ret, static void odpm_set_sampling_rate(struct odpm_info *info, enum odpm_sampling_rate_type type, - s2mpg1x_int_samp_rate int_sampling_rate_i, - s2mpg1x_ext_samp_rate ext_sampling_rate_i) + s2mpg1x_int_samp_rate int_sampling_rate_i, + s2mpg1x_ext_samp_rate ext_sampling_rate_i) { int ret = 0; @@ -1195,20 +1148,31 @@ static void odpm_set_sampling_rate(struct odpm_info *info, goto sampling_rate_store_exit; } - if (type == ODPM_SAMPLING_RATE_INTERNAL || type == ODPM_SAMPLING_RATE_ALL) { + if (type == ODPM_SAMPLING_RATE_INTERNAL || + type == ODPM_SAMPLING_RATE_ALL) { ret = odpm_io_set_int_sampling_rate(info, int_sampling_rate_i); - odpm_print_new_sampling_rate(info, ret, ODPM_SAMPLING_RATE_INTERNAL); + odpm_print_new_sampling_rate(info, ret, + ODPM_SAMPLING_RATE_INTERNAL); } - if (type == ODPM_SAMPLING_RATE_EXTERNAL || type == ODPM_SAMPLING_RATE_ALL) { + if (type == ODPM_SAMPLING_RATE_EXTERNAL || + type == ODPM_SAMPLING_RATE_ALL) { ret = odpm_io_set_ext_sampling_rate(info, ext_sampling_rate_i); - odpm_print_new_sampling_rate(info, ret, ODPM_SAMPLING_RATE_EXTERNAL); + odpm_print_new_sampling_rate(info, ret, + ODPM_SAMPLING_RATE_EXTERNAL); } +#if IS_ENABLED(CONFIG_SOC_GS201) + if (odpm_meter_sw_reset(info) != 0) { + pr_err("odpm: meter_sw_reset failed\n"); + } +#endif + /* Send blank ASYNC, ignoring the latest set of data */ if (odpm_io_send_blank_async(info, &info->last_poll_ktime_boot_ns) < 0) pr_err("odpm: Could not send blank async when applying sampling rate\n"); sampling_rate_store_exit: + odpm_reset_timer(info); mutex_unlock(&info->lock); } @@ -1300,6 +1264,15 @@ static ssize_t energy_value_show(struct device *dev, ssize_t count = 0; int ch; +#if IS_ENABLED(CONFIG_SOC_GS201) + /* Disable ODPM for A0 (b/213412265) */ + if ((info->chip.hw_id == ID_S2MPG12 && + info->chip.hw_rev == S2MPG12_EVT0) || + (info->chip.hw_id == ID_S2MPG13 && + info->chip.hw_rev == S2MPG13_EVT0)) + return -1; +#endif + /* take snapshot */ mutex_lock(&info->lock); if (odpm_take_snapshot_locked(info) < 0) { @@ -1406,6 +1379,11 @@ static ssize_t enabled_rails_store(struct device *dev, if (!info->chip.rx_ext_config_confirmation) { info->chip.rx_ext_config_confirmation = true; odpm_reset_timer(info); +#if IS_ENABLED(CONFIG_SOC_GS201) + if (odpm_meter_sw_reset(info) != 0) { + pr_err("odpm: meter_sw_reset failed\n"); + } +#endif if (odpm_configure_start_measurement(info)) pr_err("odpm: Failed to start measurement\n"); else @@ -1451,6 +1429,8 @@ static ssize_t enabled_rails_store(struct device *dev, goto enabled_rails_store_exit; } + odpm_reset_timer(info); + /* Capture measurement time for current rail */ info->chip.rails[current_rail].measurement_start_ms_cached = info->channels[channel].measurement_start_ms; @@ -1542,48 +1522,77 @@ static ssize_t measurement_stop_show(struct device *dev, return count; } -static ssize_t power_lpf_show(struct device *dev, - struct device_attribute *attr, char *buf) +void odpm_get_lpf_values(struct odpm_info *info, s2mpg1x_meter_mode mode, + u64 micro_unit[ODPM_CHANNEL_MAX]) +{ + int ch; + u32 data[ODPM_CHANNEL_MAX]; + const int samp_rate = info->chip.int_sampling_rate_i; + u32 acquisition_time_us = s2mpg1x_meter_get_acquisition_time_us(samp_rate); + + odpm_io_set_lpf_mode(info, mode); + usleep_range(acquisition_time_us, acquisition_time_us + 100); + odpm_io_get_lpf_data(info, data); + + for (ch = 0; ch < ODPM_CHANNEL_MAX; ch++) { + + const int rail_i = info->channels[ch].rail_i; + + u32 milli_res_iq30 = odpm_get_resolution_milli_iq30(info, rail_i, mode); + u32 rail_data = data[ch]; /* 21-bits */ + + u64 milli_unit_iq30 = (u64)rail_data * milli_res_iq30; + /* + * As the data is max 21 bits, we can convert to micro without + * possible overflow (2^(32-21) = 2048, 2048 > 1000). + */ + u64 micro_unit_iq30 = milli_unit_iq30 * 1000; + + micro_unit[ch] = (u32)_IQ30_to_int(micro_unit_iq30); + } +} +EXPORT_SYMBOL_GPL(odpm_get_lpf_values); + +static ssize_t odpm_show_lpf_values(struct device *dev, + struct device_attribute *attr, char *buf, + s2mpg1x_meter_mode mode) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct odpm_info *info = iio_priv(indio_dev); ssize_t count = 0; int ch; - u32 data[ODPM_CHANNEL_MAX]; + u64 micro_unit[ODPM_CHANNEL_MAX]; mutex_lock(&info->lock); - odpm_id_get_lpf_data(info, data); + odpm_get_lpf_values(info, mode, micro_unit); - /** - * Output format: - * t= - * CH[], - */ count += scnprintf(buf + count, PAGE_SIZE - count, "t=%lld\n", to_ms(ktime_get_boottime_ns())); for (ch = 0; ch < ODPM_CHANNEL_MAX; ch++) { int rail_i = info->channels[ch].rail_i; - u32 reso_mW_iq30 = odpm_get_resolution_mW_iq30(info, rail_i); - u32 rail_data = data[ch]; /* 21-bits */ - - u64 mW_iq30 = (u64)rail_data * reso_mW_iq30; - /* As the data is max 21 bits, we can convert to uW without - * possible overflow (2^(32-21) = 2048, 2048 > 1000). - */ - u64 uW_iq30 = mW_iq30 * 1000; - count += scnprintf(buf + count, PAGE_SIZE - count, "CH%d[%s], %lld\n", ch, info->chip.rails[rail_i].schematic_name, - _IQ30_to_int(uW_iq30)); + micro_unit[ch]); } - mutex_unlock(&info->lock); + return count; } -static ssize_t power_lpf_store(struct device *dev, +/* + * Output format: + * t= + * CH[], + */ +static ssize_t lpf_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return odpm_show_lpf_values(dev, attr, buf, S2MPG1X_METER_POWER); +} + +static ssize_t lpf_power_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1608,6 +1617,24 @@ static ssize_t power_lpf_store(struct device *dev, return count; } +/* + * Output format: + * t= + * CH[], + */ +static ssize_t lpf_current_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return odpm_show_lpf_values(dev, attr, buf, S2MPG1X_METER_CURRENT); +} + +static ssize_t lpf_current_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return lpf_power_store(dev, attr, buf, count); +} + static IIO_DEVICE_ATTR_RW(ext_sampling_rate, 0); static IIO_DEVICE_ATTR_RW(sampling_rate, 0); static IIO_DEVICE_ATTR_RO(energy_value, 0); @@ -1615,7 +1642,8 @@ static IIO_DEVICE_ATTR_RO(available_rails, 0); static IIO_DEVICE_ATTR_RW(enabled_rails, 0); static IIO_DEVICE_ATTR_RO(measurement_start, 0); static IIO_DEVICE_ATTR_RO(measurement_stop, 0); -static IIO_DEVICE_ATTR_RW(power_lpf, 0); +static IIO_DEVICE_ATTR_RW(lpf_power, 0); +static IIO_DEVICE_ATTR_RW(lpf_current, 0); /** * TODO(stayfan): b/156109194 @@ -1633,7 +1661,8 @@ static struct attribute *odpm_custom_attributes[] = { ODPM_DEV_ATTR(sampling_rate), ODPM_DEV_ATTR(ext_sampling_rate), ODPM_DEV_ATTR(energy_value), ODPM_DEV_ATTR(available_rails), ODPM_DEV_ATTR(enabled_rails), ODPM_DEV_ATTR(measurement_start), - ODPM_DEV_ATTR(measurement_stop), ODPM_DEV_ATTR(power_lpf), + ODPM_DEV_ATTR(measurement_stop), ODPM_DEV_ATTR(lpf_power), + ODPM_DEV_ATTR(lpf_current), NULL }; @@ -1690,7 +1719,7 @@ static int odpm_remove(struct platform_device *pdev) struct odpm_info *info = iio_priv(indio_dev); int ret; - ret = try_to_del_timer_sync(&info->timer_refresh); + ret = alarm_cancel(&info->alarmtimer_refresh); if (ret < 0) { pr_err("odpm: cannot delete the refresh timer\n"); return ret; @@ -1706,43 +1735,72 @@ static int odpm_remove(struct platform_device *pdev) iio_device_unregister(indio_dev); + if (info->ws) + wakeup_source_unregister(info->ws); + return ret; } static void odpm_probe_init_device_specific(struct odpm_info *info, int id) { - /* s2mpg1x specific data */ - switch (id) { - case ODPM_CHIP_S2MPG10: - case ODPM_CHIP_S2MPG11: - info->chip.id = id; - - info->chip.sampling_rate_int_uhz = - s2mpg1x_meter_get_int_samping_rate_table(); - info->chip.sampling_rate_int_count = S2MPG1X_INT_FREQ_COUNT; - info->chip.sampling_rate_ext_uhz = - s2mpg1x_meter_get_ext_samping_rate_table(); - info->chip.sampling_rate_ext_count = S2MPG1X_EXT_FREQ_COUNT; - break; - } + info->chip.hw_id = id; + + info->chip.sampling_rate_int_uhz = + s2mpg1x_meter_get_int_samping_rate_table(); + info->chip.sampling_rate_int_count = S2MPG1X_INT_FREQ_COUNT; + info->chip.sampling_rate_ext_uhz = + s2mpg1x_meter_get_ext_samping_rate_table(); + info->chip.sampling_rate_ext_count = S2MPG1X_EXT_FREQ_COUNT; switch (id) { - case ODPM_CHIP_S2MPG10: { +#if IS_ENABLED(CONFIG_SOC_GS101) + case ID_S2MPG10: { struct s2mpg10_meter *meter = info->meter; struct s2mpg10_dev *pmic = dev_get_drvdata(meter->dev->parent); + struct s2mpg10_platform_data *pdata = dev_get_platdata(pmic->dev); - info->chip.hw_id = ID_S2MPG10; + pdata->meter = info; info->chip.hw_rev = pmic->pmic_rev; info->i2c = meter->i2c; + info->meter_lock = &meter->meter_lock; } break; - case ODPM_CHIP_S2MPG11: { + case ID_S2MPG11: { struct s2mpg11_meter *meter = info->meter; struct s2mpg11_dev *pmic = dev_get_drvdata(meter->dev->parent); + struct s2mpg11_platform_data *pdata = dev_get_platdata(pmic->dev); + + pdata->meter = info; + + info->chip.hw_rev = pmic->pmic_rev; + info->i2c = meter->i2c; + info->meter_lock = &meter->meter_lock; + } break; +#elif IS_ENABLED(CONFIG_SOC_GS201) + case ID_S2MPG12: { + struct s2mpg12_meter *meter = info->meter; + struct s2mpg12_dev *pmic = dev_get_drvdata(meter->dev->parent); + struct s2mpg12_platform_data *pdata = dev_get_platdata(pmic->dev); + + pdata->meter = info; + + info->chip.hw_rev = pmic->pmic_rev; + info->i2c = meter->i2c; + info->mt_trim = meter->iodev->mt_trim; + info->meter_lock = &meter->meter_lock; + } break; + case ID_S2MPG13: { + struct s2mpg13_meter *meter = info->meter; + struct s2mpg13_dev *pmic = dev_get_drvdata(meter->dev->parent); + struct s2mpg13_platform_data *pdata = dev_get_platdata(pmic->dev); + + pdata->meter = info; - info->chip.hw_id = ID_S2MPG11; info->chip.hw_rev = pmic->pmic_rev; info->i2c = meter->i2c; + info->mt_trim = meter->iodev->mt_trim; + info->meter_lock = &meter->meter_lock; } break; +#endif } info->chip.rx_ext_config_confirmation = false; @@ -1785,7 +1843,7 @@ static int odpm_probe(struct platform_device *pdev) return -ENODEV; } - if (pdev->id_entry->driver_data >= ODPM_CHIP_COUNT) { + if (pdev->id_entry->driver_data >= ID_COUNT) { pr_err("odpm: Could not identify driver!\n"); odpm_remove(pdev); return -ENODEV; @@ -1841,6 +1899,11 @@ static int odpm_probe(struct platform_device *pdev) } device_enable_async_suspend(&pdev->dev); + odpm_info->ws = wakeup_source_register(&pdev->dev, odpm_info->chip.name); + if (odpm_info->ws == NULL) { + pr_err("odpm: wakelock register fail\n"); + } + mutex_init(&odpm_info->lock); pr_info("odpm: %s: init completed\n", pdev->name); @@ -1869,8 +1932,13 @@ static int odpm_resume(struct platform_device *pdev) } static const struct platform_device_id odpm_id[] = { - { "s2mpg10-odpm", ODPM_CHIP_S2MPG10 }, - { "s2mpg11-odpm", ODPM_CHIP_S2MPG11 }, +#if IS_ENABLED(CONFIG_SOC_GS101) + { "s2mpg10-odpm", ID_S2MPG10 }, + { "s2mpg11-odpm", ID_S2MPG11 }, +#elif IS_ENABLED(CONFIG_SOC_GS201) + { "s2mpg12-odpm", ID_S2MPG12 }, + { "s2mpg13-odpm", ID_S2MPG13 }, +#endif {}, }; MODULE_DEVICE_TABLE(platform, odpm_id); diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index c21100b4ed81..68fa12772ce9 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -187,7 +187,7 @@ config INPUT_APMPOWER config INPUT_KEYDEBUG tristate "Long Press Key Debugging" - depends on INPUT + depends on INPUT && KERNEL_TOP select INPUT_KEYCOMBO help Say Y here if you want to hook debug function to dump information diff --git a/drivers/input/Makefile b/drivers/input/Makefile index cea9da7e7006..77d087b0399a 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -30,6 +30,6 @@ obj-$(CONFIG_GOODIX_FINGERPRINT)+= fingerprint/ obj-$(CONFIG_INPUT_APMPOWER) += apm-power.o obj-$(CONFIG_INPUT_KEYCOMBO) += keycombo.o obj-$(CONFIG_INPUT_KEYDEBUG) += keydebug.o -keydebug-y := keydebug-core.o keydebug-func.o +keydebug-y := keydebug-core.o obj-$(CONFIG_RMI4_CORE) += rmi4/ diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig index 3f7a5ff17a9a..5364e49e8b9e 100644 --- a/drivers/input/keyboard/Kconfig +++ b/drivers/input/keyboard/Kconfig @@ -779,6 +779,11 @@ config KEYBOARD_BCM To compile this driver as a module, choose M here: the module will be called bcm-keypad. +config KEYBOARD_S2MPG12 + tristate "Samsung Electronics S2MPG12 Powerkey Controller" + depends on I2C + depends on MFD_S2MPG12 + config KEYBOARD_MTK_PMIC tristate "MediaTek PMIC keys support" depends on MFD_MT6397 diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile index 1d689fdd5c00..6fbf33f1c0ce 100644 --- a/drivers/input/keyboard/Makefile +++ b/drivers/input/keyboard/Makefile @@ -70,3 +70,4 @@ obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY) += tm2-touchkey.o obj-$(CONFIG_KEYBOARD_TWL4030) += twl4030_keypad.o obj-$(CONFIG_KEYBOARD_XTKBD) += xtkbd.o +obj-$(CONFIG_KEYBOARD_S2MPG12) += s2mpg12-key.o diff --git a/drivers/input/keyboard/s2mpg12-key.c b/drivers/input/keyboard/s2mpg12-key.c new file mode 100644 index 000000000000..45109ec2ae7d --- /dev/null +++ b/drivers/input/keyboard/s2mpg12-key.c @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Driver for Power keys on s2mpg12 IC by PWRON rising, falling interrupts. + * + * s2mpg12-keys.c + * S2MPG12 Keyboard Driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WAKELOCK_TIME (HZ / 10) + +static int force_key_irq_en; + +struct power_button_data { + struct power_keys_button *button; + struct input_dev *input; + struct work_struct work; + struct delayed_work key_work; + struct workqueue_struct *irq_wqueue; + bool key_pressed; + bool suspended; +}; + +struct power_keys_drvdata { + struct device *dev; + struct s2mpg12_platform_data *s2mpg12_pdata; + const struct power_keys_platform_data *pdata; + struct input_dev *input; + + struct i2c_client *pmm_i2c; + int irq_pwronr; + int irq_pwronf; + struct power_button_data button_data[0]; +}; + +static int power_keys_wake_lock_timeout(struct device *dev, long timeout) +{ + struct wakeup_source *ws = NULL; + + if (!dev->power.wakeup) { + dev_err(dev, "Not register wakeup source\n"); + goto err; + } + + ws = dev->power.wakeup; + __pm_wakeup_event(ws, jiffies_to_msecs(timeout)); + + return 0; +err: + return -1; +} + +static void power_keys_power_report_event(struct power_button_data *bdata) +{ + const struct power_keys_button *button = bdata->button; + struct input_dev *input = bdata->input; + struct power_keys_drvdata *ddata = input_get_drvdata(input); + unsigned int type = button->type ?: EV_KEY; + int state = bdata->key_pressed; + + if (power_keys_wake_lock_timeout(ddata->dev, WAKELOCK_TIME) < 0) { + dev_err(ddata->dev, "power_keys_wake_lock_timeout fail\n"); + return; + } + + /* Report new key event */ + input_event(input, type, button->code, !!state); + + /* Sync new input event */ + input_sync(input); +} + +static void s2mpg12_keys_work_func(struct work_struct *work) +{ + struct power_button_data *bdata = container_of(work, + struct power_button_data, + key_work.work); + + power_keys_power_report_event(bdata); + + if (bdata->button->wakeup) + pm_relax(bdata->input->dev.parent); +} + +static irqreturn_t power_keys_rising_irq_handler(int irq, void *dev_id) +{ + struct power_keys_drvdata *ddata = dev_id; + int i = 0; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + bdata->key_pressed = true; + + if (bdata->button->wakeup) { + const struct power_keys_button *button = bdata->button; + + pm_stay_awake(bdata->input->dev.parent); + if (bdata->suspended && + (button->type == 0 || button->type == EV_KEY)) { + /* + * Simulate wakeup key press in case the key has + * already released by the time we got interrupt + * handler to run. + */ + input_report_key(bdata->input, button->code, 1); + } + } + + queue_delayed_work(bdata->irq_wqueue, &bdata->key_work, 0); + } + + return IRQ_HANDLED; +} + +static irqreturn_t power_keys_falling_irq_handler(int irq, void *dev_id) +{ + struct power_keys_drvdata *ddata = dev_id; + int i = 0; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + bdata->key_pressed = false; + queue_delayed_work(bdata->irq_wqueue, &bdata->key_work, 0); + } + + return IRQ_HANDLED; +} + +static void power_keys_report_state(struct power_keys_drvdata *ddata) +{ + struct input_dev *input = ddata->input; + int i; + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + bdata->key_pressed = false; + power_keys_power_report_event(bdata); + } + input_sync(input); +} + +static int power_keys_open(struct input_dev *input) +{ + struct power_keys_drvdata *ddata = input_get_drvdata(input); + + dev_info(ddata->dev, "%s()\n", __func__); + + power_keys_report_state(ddata); + + return 0; +} + +static void power_keys_close(struct input_dev *input) +{ + struct power_keys_drvdata *ddata = input_get_drvdata(input); + + dev_info(ddata->dev, "%s()\n", __func__); +} + +#if IS_ENABLED(CONFIG_OF) +static struct power_keys_platform_data * +power_keys_get_devtree_pdata(struct s2mpg12_dev *iodev) +{ + #define S2MPG12_SUPPORT_KEY_NUM (1) + struct device *dev = iodev->dev; + struct device_node *mfd_np, *key_np, *pp; + struct power_keys_platform_data *pdata; + struct power_keys_button *button; + int error, nbuttons, i; + size_t size; + + if (!iodev->dev->of_node) { + dev_err(dev, "could not find iodev node\n"); + error = -ENODEV; + goto err_out; + } + + mfd_np = iodev->dev->of_node; + if (!mfd_np) { + dev_err(dev, "could not find parent_node\n"); + error = -ENODEV; + goto err_out; + } + + key_np = of_find_node_by_name(mfd_np, "s2mpg12-keys"); + if (!key_np) { + dev_err(dev, "could not find current_node\n"); + error = -ENOENT; + goto err_out; + } + + nbuttons = of_get_child_count(key_np); + if (nbuttons > S2MPG12_SUPPORT_KEY_NUM || nbuttons == 0) { + dev_warn(dev, "it support only one button(%d)\n", + nbuttons); + error = -ENODEV; + goto err_out; + } + + size = sizeof(*pdata) + nbuttons * sizeof(*button); + pdata = devm_kzalloc(dev, size, GFP_KERNEL); + if (!pdata) { + error = -ENOMEM; + goto err_out; + } + + pdata->buttons = (struct power_keys_button *)(pdata + 1); + pdata->nbuttons = nbuttons; + + i = 0; + for_each_child_of_node(key_np, pp) { + button = &pdata->buttons[i++]; + if (of_property_read_u32(pp, "linux,code", &button->code)) { + error = -EINVAL; + goto err_out; + } + + button->desc = of_get_property(pp, "label", NULL); + + of_property_read_u32(pp, "wakeup", &button->wakeup); + + if (of_property_read_u32(pp, "linux,input-type", &button->type)) + button->type = EV_KEY; + if (of_property_read_u32(pp, "force_key_irq_en", &force_key_irq_en)) + force_key_irq_en = 0; + } + + return pdata; +err_out: + return ERR_PTR(error); +} + +static const struct of_device_id power_keys_of_match[] = { + { .compatible = "s2mpg12-power-keys", }, + { }, +}; +MODULE_DEVICE_TABLE(of, power_keys_of_match); +#else +static inline struct power_keys_platform_data * +power_keys_get_devtree_pdata(struct s2mpg12_dev *iodev) +{ + return ERR_PTR(-ENODEV); +} +#endif + +static void power_remove_key(struct power_button_data *bdata) +{ + pr_info("%s()\n", __func__); // it will be removed. + + cancel_delayed_work_sync(&bdata->key_work); +} + +static void power_keys_force_en_irq(struct power_keys_drvdata *ddata) +{ + if (!force_key_irq_en) + return; + + enable_irq(ddata->irq_pwronf); + enable_irq(ddata->irq_pwronr); +} + +static int power_keys_set_interrupt(struct power_keys_drvdata *ddata, int irq_base) +{ + struct device *dev = ddata->dev; + int ret = 0; + + ddata->irq_pwronr = irq_base + S2MPG12_IRQ_PWRONR_INT1; + ddata->irq_pwronf = irq_base + S2MPG12_IRQ_PWRONF_INT1; + + ret = devm_request_threaded_irq(dev, ddata->irq_pwronr, NULL, + power_keys_rising_irq_handler, 0, + "pwronr-irq", ddata); + if (ret < 0) { + dev_err(dev, "fail to request pwronr-irq: %d: %d\n", + ddata->irq_pwronr, ret); + goto err; + } + + ret = devm_request_threaded_irq(dev, ddata->irq_pwronf, NULL, + power_keys_falling_irq_handler, 0, + "pwronf-irq", ddata); + if (ret < 0) { + dev_err(dev, "fail to request pwronf-irq: %d: %d\n", + ddata->irq_pwronf, ret); + goto err; + } + + return 0; +err: + return -1; +} + +static int power_keys_set_buttondata(struct power_keys_drvdata *ddata, + struct input_dev *input, int *wakeup) +{ + int cnt = 0; + + for (cnt = 0; cnt < ddata->pdata->nbuttons; cnt++) { + struct power_keys_button *button = &ddata->pdata->buttons[cnt]; + struct power_button_data *bdata = &ddata->button_data[cnt]; + char device_name[32] = {0, }; + + bdata->input = input; + bdata->button = button; + + if (button->wakeup) + *wakeup = 1; + + /* Dynamic allocation for workqueue name */ + snprintf(device_name, sizeof(device_name) - 1, + "power-keys-wq%d@%s", cnt, dev_name(ddata->dev)); + + bdata->irq_wqueue = create_singlethread_workqueue(device_name); + if (!bdata->irq_wqueue) { + dev_err(ddata->dev, "fail to create workqueue\n"); + goto err; + } + INIT_DELAYED_WORK(&bdata->key_work, s2mpg12_keys_work_func); + + input_set_capability(input, button->type ?: EV_KEY, button->code); + } + + return cnt; +err: + return -1; +} + +static struct power_keys_drvdata * +power_keys_set_drvdata(struct platform_device *pdev, + struct power_keys_platform_data *pdata, + struct input_dev *input, struct s2mpg12_dev *iodev) +{ + struct power_keys_drvdata *ddata = NULL; + struct device *dev = &pdev->dev; + size_t size; + + size = sizeof(*ddata) + pdata->nbuttons * sizeof(struct power_button_data); + ddata = devm_kzalloc(dev, size, GFP_KERNEL); + if (!ddata) + return ERR_PTR(-ENOMEM); + + ddata->dev = dev; + ddata->pdata = pdata; + ddata->input = input; + ddata->pmm_i2c = iodev->pmic; + + platform_set_drvdata(pdev, ddata); + input_set_drvdata(input, ddata); + + return ddata; +} + +static int power_keys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct s2mpg12_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct power_keys_platform_data *pdata = NULL; + struct power_keys_drvdata *ddata = NULL; + struct input_dev *input; + int ret = 0, count = 0; + int wakeup = 0; + + pr_info("%s: start\n", __func__); // it will be removed. + + pdata = power_keys_get_devtree_pdata(iodev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + + input = devm_input_allocate_device(dev); + if (!input) { + dev_err(dev, "failed to allocate state\n"); + ret = -ENOMEM; + goto fail1; + } + + input->name = pdata->name ? : pdev->name; + input->phys = "s2mpg12-keys/input0"; + input->dev.parent = dev; + input->open = power_keys_open; + input->close = power_keys_close; + + input->id.bustype = BUS_I2C; + input->id.vendor = 0x0001; + input->id.product = 0x0001; + input->id.version = 0x0100; + + ddata = power_keys_set_drvdata(pdev, pdata, input, iodev); + if (IS_ERR(ddata)) { + dev_err(dev, "power_keys_set_drvdata fail\n"); + return PTR_ERR(ddata); + } + + ret = power_keys_set_buttondata(ddata, input, &wakeup); + if (ret < 0) { + dev_err(dev, "power_keys_set_buttondata fail\n"); + goto fail1; + } else { + count = ret; + } + + ret = device_init_wakeup(dev, wakeup); + if (ret < 0) { + dev_err(dev, "device_init_wakeup fail(%d)\n", ret); + goto fail1; + } + + ret = power_keys_set_interrupt(ddata, iodev->pdata->irq_base); + if (ret < 0) { + dev_err(dev, "power_keys_set_interrupt fail\n"); + goto fail1; + } + + ret = input_register_device(input); + if (ret) { + dev_err(dev, "unable to register input device(%d)\n", ret); + goto fail2; + } + + power_keys_force_en_irq(ddata); + + dev_info(dev, "S2MPG12 Key probe End\n"); + + return 0; + +fail2: + while (--count >= 0) { + struct power_button_data *bdata = &ddata->button_data[count]; + + if (bdata->irq_wqueue) + destroy_workqueue(bdata->irq_wqueue); + + power_remove_key(bdata); + } + + platform_set_drvdata(pdev, NULL); + +fail1: + return ret; +} + +static int power_keys_remove(struct platform_device *pdev) +{ + struct power_keys_drvdata *ddata = platform_get_drvdata(pdev); + struct input_dev *input = ddata->input; + int i; + + device_init_wakeup(&pdev->dev, 0); + + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + if (bdata->irq_wqueue) + destroy_workqueue(bdata->irq_wqueue); + + power_remove_key(bdata); + } + + input_unregister_device(input); + + return 0; +} + +#if IS_ENABLED(CONFIG_PM_SLEEP) +static int power_keys_suspend(struct device *dev) +{ + struct power_keys_drvdata *ddata = dev_get_drvdata(dev); + int i; + + if (device_may_wakeup(dev)) { + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + bdata->suspended = true; + } + } + + return 0; +} + +static int power_keys_resume(struct device *dev) +{ + struct power_keys_drvdata *ddata = dev_get_drvdata(dev); + int i; + + if (device_may_wakeup(dev)) { + for (i = 0; i < ddata->pdata->nbuttons; i++) { + struct power_button_data *bdata = &ddata->button_data[i]; + + bdata->suspended = false; + } + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(power_keys_pm_ops, power_keys_suspend, power_keys_resume); + +static struct platform_driver power_keys_device_driver = { + .probe = power_keys_probe, + .remove = power_keys_remove, + .driver = { + .name = "s2mpg12-power-keys", + .owner = THIS_MODULE, + .pm = &power_keys_pm_ops, + .of_match_table = of_match_ptr(power_keys_of_match), + } +}; + +static int __init power_keys_init(void) +{ + return platform_driver_register(&power_keys_device_driver); +} + +static void __exit power_keys_exit(void) +{ + platform_driver_unregister(&power_keys_device_driver); +} + +device_initcall(power_keys_init); +module_exit(power_keys_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_DESCRIPTION("Keyboard driver for s2mpg12"); +MODULE_ALIAS("platform:s2mpg12 Power key"); diff --git a/drivers/input/keydebug-core.c b/drivers/input/keydebug-core.c index ab5dcc3b6447..9e51ec1f4670 100644 --- a/drivers/input/keydebug-core.c +++ b/drivers/input/keydebug-core.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include /* @@ -90,8 +90,11 @@ void do_keydebug(struct work_struct *this) struct keydebug_platform_data *pdata = container_of(dwork, struct keydebug_platform_data, delayed_work); - if (kernel_top_enable) - kernel_top_monitor(); + if (pdata->ktop) { + kernel_top_print(pdata->ktop); + kernel_top_destroy(pdata->ktop); + pdata->ktop = NULL; + } if (show_dstate_enable) { pr_info("======= Show D state tasks++ =======\n"); @@ -126,7 +129,7 @@ static int s2d_state_xchg(int new, int *pold) static void keydebug_event_down(void *priv) { struct keydebug_platform_data *pdata = priv; - uint32_t msecs = DEFAULT_DBG_DELAY; + uint32_t msecs = pdata->dbg_fn_delay ?: DEFAULT_DBG_DELAY; if (bind_s2d) s2d_state_xchg(false, &pdata->s2d_state_backup); @@ -135,11 +138,11 @@ static void keydebug_event_down(void *priv) pr_info("%s: request is running\n", __func__); return; } else { - if (pdata->dbg_fn_delay) - msecs = pdata->dbg_fn_delay; - + WARN_ON(pdata->ktop); + pdata->ktop = NULL; if (kernel_top_enable) - kernel_top_init(); + WARN_ON(kernel_top_init(pdata->pdev_child->dev.parent, + &pdata->ktop)); queue_delayed_work(kdbg_wq, &pdata->delayed_work, msecs_to_jiffies(msecs)); @@ -305,8 +308,7 @@ static int keydebug_remove(struct platform_device *pdev) { struct keydebug_platform_data *pdata = dev_get_platdata(&pdev->dev); - if (kernel_top_enable) - kernel_top_exit(); + flush_delayed_work(&pdata->delayed_work); platform_device_put(pdata->pdev_child); if (kdbg_wq) diff --git a/drivers/input/misc/vl53l1/src/vl53l1_api.c b/drivers/input/misc/vl53l1/src/vl53l1_api.c index 148523946600..673ba933de59 100644 --- a/drivers/input/misc/vl53l1/src/vl53l1_api.c +++ b/drivers/input/misc/vl53l1/src/vl53l1_api.c @@ -378,7 +378,9 @@ VL53L1_Error VL53L1_GetUID(VL53L1_DEV Dev, uint64_t *pUid) (uint8_t)(0x1F8 >> 2), (uint8_t)(8 >> 2), fmtdata); - memcpy(pUid, fmtdata, sizeof(uint64_t)); + + if (Status == VL53L1_ERROR_NONE) + memcpy(pUid, fmtdata, sizeof(uint64_t)); LOG_FUNCTION_END(Status); return Status; @@ -3811,8 +3813,8 @@ VL53L1_Error VL53L1_PerformOffsetPerVcselCalibration(VL53L1_DEV Dev, VL53L1_DistanceModes currentDist; VL53L1_DistanceModes DistMode[3] = {VL53L1_DISTANCEMODE_SHORT, VL53L1_DISTANCEMODE_MEDIUM, VL53L1_DISTANCEMODE_LONG}; - int16_t offsetA[3]; - int16_t offsetB[3]; + int16_t offsetA[3] = {0}; + int16_t offsetB[3] = {0}; VL53L1_Error SmudgeStatus = VL53L1_ERROR_NONE; uint8_t smudge_corr_en, isc; diff --git a/drivers/input/misc/vl53l1/src/vl53l1_core_support.c b/drivers/input/misc/vl53l1/src/vl53l1_core_support.c index 50e3e0e3199a..8b3ec8d793aa 100644 --- a/drivers/input/misc/vl53l1/src/vl53l1_core_support.c +++ b/drivers/input/misc/vl53l1/src/vl53l1_core_support.c @@ -270,8 +270,8 @@ void VL53L1_hist_remove_ambient_bins( } } - if (pdata->number_of_ambient_bins > 0) { - + if (pdata->number_of_ambient_bins > 0 && + pdata->VL53L1_p_023 <= VL53L1_HISTOGRAM_BUFFER_SIZE) { for (bin = pdata->number_of_ambient_bins; bin < pdata->VL53L1_p_023; bin++) { diff --git a/drivers/input/misc/vl53l1/stmvl53l1.h b/drivers/input/misc/vl53l1/stmvl53l1.h index 49b299b2b649..8e4904968afa 100644 --- a/drivers/input/misc/vl53l1/stmvl53l1.h +++ b/drivers/input/misc/vl53l1/stmvl53l1.h @@ -197,7 +197,6 @@ struct stmvl53l1_data { /* autonomous config */ uint32_t auto_pollingTimeInMs; struct VL53L1_DetectionConfig_t auto_config; - }; diff --git a/drivers/input/misc/vl53l1/stmvl53l1_i2c.c b/drivers/input/misc/vl53l1/stmvl53l1_i2c.c index e014530a4d60..9fd46987eca1 100644 --- a/drivers/input/misc/vl53l1/stmvl53l1_i2c.c +++ b/drivers/input/misc/vl53l1/stmvl53l1_i2c.c @@ -199,11 +199,12 @@ VL53L1_Error VL53L1_WrWord(VL53L1_DEV pdev, uint16_t index, uint16_t data) VL53L1_Error VL53L1_RdWord(VL53L1_DEV pdev, uint16_t index, uint16_t *pdata) { VL53L1_Error status; - uint8_t buffer[2]; + uint16_t buffer; - status = VL53L1_ReadMulti(pdev, index, buffer, 2); + status = VL53L1_ReadMulti(pdev, index, (uint8_t *)&buffer, 2); - *pdata = ((uint16_t)buffer[0] << 8) + (uint16_t)buffer[1]; + if (status == VL53L1_ERROR_NONE) + *pdata = ntohs(buffer); return status; } @@ -227,12 +228,12 @@ VL53L1_Error VL53L1_WrDWord(VL53L1_DEV pdev, uint16_t index, uint32_t data) VL53L1_Error VL53L1_RdDWord(VL53L1_DEV pdev, uint16_t index, uint32_t *pdata) { VL53L1_Error status = VL53L1_ERROR_NONE; - uint8_t buffer[4]; + uint32_t buffer; - status = VL53L1_ReadMulti(pdev, index, buffer, 4); + status = VL53L1_ReadMulti(pdev, index, (uint8_t *)&buffer, 4); - *pdata = ((uint32_t)buffer[0] << 24) + ((uint32_t)buffer[1] << 16) + - ((uint32_t)buffer[2] << 8) + (uint32_t)buffer[3]; + if (status == VL53L1_ERROR_NONE) + *pdata = ntohl(buffer); return status; } @@ -250,6 +251,9 @@ VL53L1_Error VL53L1_WriteMulti(VL53L1_DEV pdev, uint16_t index, struct stmvl53l1_data, stdev); + if (count == 0) + return VL53L1_ERROR_INVALID_PARAMS; + for (i = 0; i < count; i += chunk_size) { status = (cci_write(dev, hostaddr, &pdata[i], min(chunk_size, (count - i))) ? diff --git a/drivers/input/misc/vl53l1/stmvl53l1_module-i2c.c b/drivers/input/misc/vl53l1/stmvl53l1_module-i2c.c index cbef318b9a62..fe93cf5ebe61 100644 --- a/drivers/input/misc/vl53l1/stmvl53l1_module-i2c.c +++ b/drivers/input/misc/vl53l1/stmvl53l1_module-i2c.c @@ -517,13 +517,13 @@ static int stmvl53l1_probe(struct i2c_client *client, rc = -ENOMEM; return rc; } - if (vl53l1_data) { - vl53l1_data->client_object = - kzalloc(sizeof(struct i2c_data), GFP_KERNEL); - if (!vl53l1_data) - goto done_freemem; - i2c_data = (struct i2c_data *)vl53l1_data->client_object; - } + + vl53l1_data->client_object = + kzalloc(sizeof(struct i2c_data), GFP_KERNEL); + if (!vl53l1_data->client_object) + goto done_freemem; + + i2c_data = vl53l1_data->client_object; i2c_data->client = client; i2c_data->vl53l1_data = vl53l1_data; i2c_data->irq = -1; /* init to no irq */ @@ -642,8 +642,10 @@ int stmvl53l1_power_up_i2c(void *object) struct i2c_data *data = (struct i2c_data *)object; struct device *dev = &data->client->dev; - if (data->vl53l1_data->is_power_up) - return rc; + if (data->vl53l1_data != NULL) { + if (data->vl53l1_data->is_power_up) + return rc; + } /* turn on power */ if (data->vio_gpio != -1) { @@ -709,8 +711,10 @@ int stmvl53l1_power_down_i2c(void *i2c_object) struct i2c_data *data = (struct i2c_data *)i2c_object; struct device *dev = &data->client->dev; - if (!data->vl53l1_data->is_power_up) - return rc; + if (data->vl53l1_data != NULL) { + if (!data->vl53l1_data->is_power_up) + return rc; + } /* turn off power */ if (data->pwren_gpio != -1) diff --git a/drivers/input/misc/vl53l1/stmvl53l1_module.c b/drivers/input/misc/vl53l1/stmvl53l1_module.c index b3e02869ce8c..6f6f06c5ef1b 100644 --- a/drivers/input/misc/vl53l1/stmvl53l1_module.c +++ b/drivers/input/misc/vl53l1/stmvl53l1_module.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * API includes @@ -2626,7 +2627,15 @@ static int sleep_for_data(struct stmvl53l1_data *data, pid_t pid, add_wait_queue(&data->waiter_for_data, &wait); while (!sleep_for_data_condition(data, pid, head)) { - wait_woken(&wait, TASK_KILLABLE, MAX_SCHEDULE_TIMEOUT); + /* + * b/243120064: The 1st data will arrive over 300 ms if tuning parameter + * is set and less than 100 ms without tuning. Hence, using a maximum 1000 + * ms for timeout is acceptable and sufficient to cover all use cases. + */ + if (wait_woken(&wait, TASK_KILLABLE, 1000) <= 0) { + rc = -ETIME; + break; + } if (fatal_signal_pending(current)) { rc = -ERESTARTSYS; break; @@ -3530,56 +3539,39 @@ static int stmvl53l1_ioctl_handler( void __user *p) { int rc = 0; - struct i2c_data *i2c_data = (struct i2c_data *)data->client_object; - struct device *dev = &i2c_data->client->dev; if (!data) return -EINVAL; switch (cmd) { case VL53L1_IOCTL_POWER_UP: - dev_dbg(dev, "VL53L1_IOCTL_POWER_UP\n"); rc = ctrl_power_up(data); break; - case VL53L1_IOCTL_POWER_DOWN: - dev_dbg(dev, "VL53L1_IOCTL_POWER_DOWN\n"); rc = ctrl_power_down(data); break; - case VL53L1_IOCTL_START: - dev_dbg(dev, "VL53L1_IOCTL_START\n"); rc = ctrl_start(data); break; - case VL53L1_IOCTL_STOP: - dev_dbg(dev, "VL53L1_IOCTL_STOP\n"); rc = ctrl_stop(data); break; - case VL53L1_IOCTL_GETDATAS: rc = ctrl_getdata(data, p); break; - case VL53L1_IOCTL_GETDATAS_BLOCKING: rc = ctrl_getdata_blocking(data, p); break; - /* Register tool */ case VL53L1_IOCTL_REGISTER: - dev_dbg(dev, "VL53L1_IOCTL_REGISTER\n"); reset_release(data); rc = ctrl_reg_access(data, p); reset_hold(data); break; - case VL53L1_IOCTL_PARAMETER: - dev_dbg(dev, "VL53L1_IOCTL_PARAMETER\n"); rc = ctrl_params(data, p); break; - case VL53L1_IOCTL_ROI: - dev_dbg(dev, "VL53L1_IOCTL_ROI\n"); rc = ctrl_roi(data, p); break; case VL53L1_IOCTL_MZ_DATA: @@ -3589,19 +3581,15 @@ static int stmvl53l1_ioctl_handler( rc = ctrl_mz_data_blocking(data, p); break; case VL53L1_IOCTL_CALIBRATION_DATA: - dev_dbg(dev, "VL53L1_IOCTL_CALIBRATION_DATA\n"); rc = ctrl_calibration_data(data, p); break; case VL53L1_IOCTL_PERFORM_CALIBRATION: - dev_dbg(dev, "VL53L1_IOCTL_PERFORM_CALIBRATION\n"); rc = ctrl_perform_calibration(data, p); break; case VL53L1_IOCTL_AUTONOMOUS_CONFIG: - dev_dbg(dev, "VL53L1_IOCTL_AUTONOMOUS_CONFIG\n"); rc = ctrl_autonomous_config(data, p); break; case VL53L1_IOCTL_ZONE_CALIBRATION_DATA: - dev_dbg(dev, "VL53L1_IOCTL_ZONE_CALIBRATION_DATA\n"); rc = ctrl_zone_calibration_data(data, p); break; case VL53L1_IOCTL_MZ_DATA_ADDITIONAL: @@ -4256,6 +4244,9 @@ int stmvl53l1_setup(struct stmvl53l1_data *data) struct VL53L1_DeviceInfo_t dev_info; struct i2c_data *i2c_data = data->client_object; struct device *dev = &i2c_data->client->dev; + struct sched_param param = {0}; + struct irq_desc *desc; + struct task_struct *irq_thread; /* acquire an id */ data->id = allocate_dev_id(); @@ -4418,6 +4409,20 @@ int stmvl53l1_setup(struct stmvl53l1_data *data) /* power down after probe done */ stmvl53l1_module_func_tbl.power_down(data->client_object); + /* adjust policy from SCHED_FIFO to SCHED_OTHER */ + if (i2c_data->irq > 0) { + desc = irq_to_desc(i2c_data->irq); + if (desc == NULL) { + dev_warn(dev, "get a null irq desc"); + return 0; + } + raw_spin_lock_irq(&desc->lock); + irq_thread = desc->action->thread; + raw_spin_unlock_irq(&desc->lock); + rc = sched_setscheduler_nocheck(irq_thread, SCHED_NORMAL, ¶m); + dev_info(dev, "VL53L1 setscheduler rc = %d", rc); + } + return 0; exit_unregister_dev_ps: diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig index 5b87102d2e0c..46504707896e 100644 --- a/drivers/iommu/Kconfig +++ b/drivers/iommu/Kconfig @@ -254,6 +254,26 @@ config EXYNOS_IOMMU_DEBUG Say N unless you need kernel log message for IOMMU debugging. +config EXYNOS_PCIE_IOMMU + tristate "Enable Exynos PCIe IOMMU" + depends on PCI_EXYNOS + help + Support for IOMMU feature for Exynos PCIe. Memory shared between the + PCIe Root Complex and the Endpoints is susceptible to attacks by + malicious firmware loaded into the Endpoints. Enabling this provides + secure access of memory shared between PCIe RC and the EPs. + +config PCIE_IOMMU_HISTORY_LOG + bool "Enable Exynos PCIe IOMMU Map/Unmap History" + depends on EXYNOS_PCIE_IOMMU + help + Support for saving map and unmap history of shared memory between the + Root Complex and Endpoints of the Exynos PCIe interface. This history + can be used for debugging purposes. + + Say Y to enable this feature. + + config IPMMU_VMSA bool "Renesas VMSA-compatible IPMMU" depends on ARCH_RENESAS || (COMPILE_TEST && !GENERIC_ATOMIC64) diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index c30882d132a8..b7f9b59b3769 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_SAMSUNG_IOMMU) += samsung_iommu.o samsung_iommu-objs += samsung-iommu.o samsung-iommu-fault.o obj-$(CONFIG_SAMSUNG_IOMMU_GROUP) += samsung-iommu-group.o obj-$(CONFIG_SAMSUNG_SECURE_IOVA) += samsung-secure-iova.o +obj-$(CONFIG_EXYNOS_PCIE_IOMMU) += exynos-pcie-iommu.o diff --git a/drivers/iommu/exynos-pcie-iommu-exp.h b/drivers/iommu/exynos-pcie-iommu-exp.h new file mode 100644 index 000000000000..9b92c4327bc9 --- /dev/null +++ b/drivers/iommu/exynos-pcie-iommu-exp.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PCIe Exynos IOMMU driver header file + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#ifndef _EXYNOS_PCIE_IOMMU_EXP_H_ +#define _EXYNOS_PCIE_IOMMU_EXP_H_ + +int pcie_iommu_map(unsigned long iova, phys_addr_t paddr, size_t size, + int prot, int hsi_block_num); +size_t pcie_iommu_unmap(unsigned long iova, size_t size, int hsi_block_num); + +void pcie_sysmmu_set_use_iocc(int hsi_block_num); +void pcie_sysmmu_enable(int hsi_block_num); +void pcie_sysmmu_disable(int hsi_block_num); +void pcie_sysmmu_all_buff_free(int hsi_block_num); +void print_pcie_sysmmu_tlb(int hsi_block_num); + +#endif /* _EXYNOS_PCIE_IOMMU_EXP_H_ */ diff --git a/drivers/iommu/exynos-pcie-iommu.c b/drivers/iommu/exynos-pcie-iommu.c new file mode 100644 index 000000000000..bfa3e1c7774c --- /dev/null +++ b/drivers/iommu/exynos-pcie-iommu.c @@ -0,0 +1,1559 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe Exynos IOMMU driver + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "exynos-pcie-iommu.h" +#include "exynos-pcie-iommu-exp.h" + +static struct kmem_cache *lv2table_kmem_cache; +#ifndef USE_DYNAMIC_MEM_ALLOC /* USE gen_pool */ +static struct gen_pool *lv2table_pool; +#endif + +#define MAX_HSI_BLOCK (3) +static struct sysmmu_drvdata *g_sysmmu_drvdata[MAX_HSI_BLOCK]; +static struct device *g_last_dev; +static u32 alloc_counter; +static u32 lv2table_counter; +static u32 max_req_cnt; +static u32 wrong_pf_cnt; +#if IS_ENABLED(CONFIG_PCIE_IOMMU_HISTORY_LOG) +static struct history_buff pcie_map_history, pcie_unmap_history; +#endif + +void pcie_iommu_tlb_invalidate_all(int hsi_block_num) +{ + int pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + + if (g_sysmmu_drvdata[hsi_block_num] == NULL) { + pr_err("[%s] PCIe SysMMU feature is disabled!!!\n", __func__); + return ; + } + + if (!is_sysmmu_active(g_sysmmu_drvdata[hsi_block_num])) /* SKIP invalidation */ + return; + + writel(0x1, g_sysmmu_drvdata[hsi_block_num]->sfrbase + REG_MMU_FLUSH_VID(pcie_vid)); +} +EXPORT_SYMBOL_GPL(pcie_iommu_tlb_invalidate_all); + +void pcie_iommu_tlb_invalidate_range(dma_addr_t iova, size_t size, int hsi_block_num) +{ + void * __iomem sfrbase = g_sysmmu_drvdata[hsi_block_num]->sfrbase; + int pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + u32 start_addr, end_addr; + + if (!is_sysmmu_active(g_sysmmu_drvdata[hsi_block_num])) /* SKIP invalidation */ + return; + + start_addr = (iova >> 4) & 0xffffff00; + writel_relaxed(start_addr, sfrbase + REG_FLUSH_RANGE_START_VID(pcie_vid)); + + end_addr = ((iova + size - 1) >> 4) & 0xffffff00; + writel_relaxed(end_addr, sfrbase + REG_FLUSH_RANGE_END_VID(pcie_vid)); + + writel(0x1, sfrbase + REG_MMU_FLUSH_RANGE_VID(pcie_vid)); +} +EXPORT_SYMBOL_GPL(pcie_iommu_tlb_invalidate_range); + +static inline void pgtable_flush(void *vastart, void *vaend) +{ + /* __dma_flush_area(vastart, vaend - vastart); */ + dma_sync_single_for_device(g_last_dev, + virt_to_phys(vastart), vaend - vastart, + DMA_TO_DEVICE); +} + +static void __sysmmu_tlb_invalidate_all(void __iomem *sfrbase, int pcie_vid) +{ + writel(0x1, sfrbase + REG_MMU_FLUSH_VID(pcie_vid)); +} + +static void __sysmmu_set_ptbase(void __iomem *sfrbase, + phys_addr_t pfn_pgtable, int pcie_vid) +{ + writel_relaxed(pfn_pgtable, sfrbase + REG_PT_BASE_PPN_VID(pcie_vid)); + + __sysmmu_tlb_invalidate_all(sfrbase, pcie_vid); +} + +static void __sysmmu_tlb_pinning(struct sysmmu_drvdata *drvdata) +{ +#if defined(USE_ADDRTYPE_TLP_PINNING) && defined(MULTI_TLB) + dma_addr_t mem_start_addr; + size_t mem_size; + u32 start_addr, end_addr; + u32 upper_addr, reg_val; + void __iomem *sfrbase = drvdata->sfrbase; + + /* Set TLB1 pinning address */ + get_atomic_pool_info(&mem_start_addr, &mem_size); + + upper_addr = (mem_start_addr >> 32) & 0xf; + start_addr = mem_start_addr & 0xffffffff; + end_addr = start_addr + mem_size; + + reg_val = readl_relaxed(sfrbase + REG_MMU_TLB_MATCH_CFG(1)); + + /* Clear EVA/SVA_UPPER */ + reg_val &= ~(0xff); + reg_val |= (upper_addr << 4) | (upper_addr << 0); + writel_relaxed(reg_val, sfrbase + REG_MMU_TLB_MATCH_CFG(1)); + + /* Set Start/End TLB MATCH */ + writel_relaxed(start_addr, sfrbase + REG_MMU_TLB_MATCH_SVA(1)); + writel_relaxed(end_addr, sfrbase + REG_MMU_TLB_MATCH_EVA(1)); + + pr_debug("Set TLB MATCH address for TLB1 Pinning : 0x%x_%x ~ 0x%x_%x\n", + readl_relaxed(sfrbase + REG_MMU_TLB_MATCH_CFG(1)) & 0xf, + readl_relaxed(sfrbase + REG_MMU_TLB_MATCH_SVA(1)), + upper_addr, + readl_relaxed(sfrbase + REG_MMU_TLB_MATCH_EVA(1))); +#else + pr_info("It doesn't support Address Base TLB pinning.\n"); + +#endif +} + +static void __sysmmu_init_config(struct sysmmu_drvdata *drvdata) +{ + /* Set TLB0 */ + writel_relaxed(0x0, drvdata->sfrbase + REG_MMU_TLB_CFG(0)); +#ifdef MULTI_TLB /* Pamir PCIe has only one TLB */ + /* Enable TLB1 to be used by both PCIe channel 0 and 1*/ + writel_relaxed(0x0, drvdata->sfrbase + REG_MMU_TLB_CFG(1)); + writel_relaxed(TLB_USED_ALL_PCIE_PORT | TLB_USED_RW_REQ, + drvdata->sfrbase + REG_MMU_TLB_MATCH_CFG(1)); +#endif + + if (drvdata->use_tlb_pinning) + __sysmmu_tlb_pinning(drvdata); +} + +static void __sysmmu_enable_nocount(struct sysmmu_drvdata *drvdata, int pcie_vid) +{ + u32 ctrl_val, cfg; + + __sysmmu_init_config(drvdata); + + __sysmmu_set_ptbase(drvdata->sfrbase, + drvdata->pgtable / PAGE_SIZE, pcie_vid); + + spin_lock(&drvdata->mmu_ctrl_lock); + if (!is_sysmmu_active(drvdata)) { + pr_debug("PCIE SysMMU Global Enable...\n"); + cfg = readl_relaxed(drvdata->sfrbase + REG_MMU_CFG); + + if (drvdata->qos != DEFAULT_QOS_VALUE) { + cfg &= ~CFG_QOS(0xF); + cfg |= CFG_QOS_OVRRIDE | CFG_QOS(drvdata->qos); + } + + writel_relaxed(cfg, drvdata->sfrbase + REG_MMU_CFG); + ctrl_val = readl_relaxed(drvdata->sfrbase + REG_MMU_CTRL); + writel(ctrl_val | CTRL_ENABLE, drvdata->sfrbase + REG_MMU_CTRL); + } + set_sysmmu_active(drvdata, pcie_vid); + spin_unlock(&drvdata->mmu_ctrl_lock); + + /* Set VID0 MMU_CTRL (Stall mode is default) */ + ctrl_val = readl_relaxed(drvdata->sfrbase + REG_MMU_CTRL_VID(pcie_vid)); + writel(ctrl_val | CTRL_MMU_ENABLE | CTRL_FAULT_STALL_MODE, + drvdata->sfrbase + REG_MMU_CTRL_VID(pcie_vid)); + + if (drvdata->pcie_use_iocc) { + ctrl_val = readl(drvdata->sfrbase + REG_MMU_CFG_VID(pcie_vid)); + ctrl_val |= VID_CFG_SHAREABLE | VID_CFG_SHAREABLE_OVRD; + writel(ctrl_val, drvdata->sfrbase + REG_MMU_CFG_VID(pcie_vid)); + } + __sysmmu_tlb_invalidate_all(drvdata->sfrbase, pcie_vid); +} + +static void __sysmmu_disable_nocount(struct sysmmu_drvdata *drvdata, int pcie_vid) +{ + /* Disable SysMMU for specific VID */ + writel(CTRL_DISABLE, drvdata->sfrbase + REG_MMU_CTRL_VID(pcie_vid)); + + spin_lock(&drvdata->mmu_ctrl_lock); + set_sysmmu_inactive(drvdata, pcie_vid); + if (!is_sysmmu_active(drvdata)) { + pr_debug("PCIE SysMMU Global Disable...\n"); + writel_relaxed(0, drvdata->sfrbase + REG_MMU_CFG); +#ifdef USE_BLOCK_DISABE + writel_relaxed(CTRL_BLOCK_DISABLE, drvdata->sfrbase + REG_MMU_CTRL); + BUG_ON(readl_relaxed(drvdata->sfrbase + REG_MMU_CTRL) + != CTRL_BLOCK_DISABLE); +#else + /* PCIe SysMMU use full disable(by pass) as default */ + writel_relaxed(CTRL_DISABLE, drvdata->sfrbase + REG_MMU_CTRL); +#endif + } + spin_unlock(&drvdata->mmu_ctrl_lock); +} + +void pcie_sysmmu_set_use_iocc(int hsi_block_num) +{ + if (g_sysmmu_drvdata[hsi_block_num]) { + pr_debug("Set PCIe use IOCC flag.\n"); + g_sysmmu_drvdata[hsi_block_num]->pcie_use_iocc = 1; + } +} +EXPORT_SYMBOL(pcie_sysmmu_set_use_iocc); + +void pcie_sysmmu_enable(int hsi_block_num) +{ + int pcie_vid; + + if (!g_sysmmu_drvdata[hsi_block_num]) { + pr_err("PCIe SysMMU feature is disabled!!!\n"); + return; + } + + pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + + __sysmmu_enable_nocount(g_sysmmu_drvdata[hsi_block_num], pcie_vid); +} +EXPORT_SYMBOL(pcie_sysmmu_enable); + +void pcie_sysmmu_disable(int hsi_block_num) +{ + int pcie_vid; + + if (!g_sysmmu_drvdata[hsi_block_num]) { + pr_err("PCIe SysMMU feature is disabled!!!\n"); + return; + } + pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + + __sysmmu_disable_nocount(g_sysmmu_drvdata[hsi_block_num], pcie_vid); + pr_debug("SysMMU alloc num : %d(Max:%d), lv2_alloc : %d, fault : %d\n", + alloc_counter, max_req_cnt, lv2table_counter, wrong_pf_cnt); +} +EXPORT_SYMBOL(pcie_sysmmu_disable); + +void pcie_sysmmu_all_buff_free(int hsi_block_num) +{ + struct exynos_iommu_domain *domain; + void __maybe_unused *virt_addr; + int i; + + if (!g_sysmmu_drvdata[hsi_block_num]) { + pr_err("PCIe SysMMU feature is disabled!!!\n"); + return; + } + + domain = g_sysmmu_drvdata[hsi_block_num]->domain; + + for (i = 0; i < NUM_LV1ENTRIES; i++) { + if (!lv1ent_page(domain->pgtable + i)) + continue; +#ifdef USE_DYNAMIC_MEM_ALLOC + virt_addr = phys_to_virt(lv2table_base(domain->pgtable + i)); + kmem_cache_free(lv2table_kmem_cache, virt_addr); +#else /* Use genpool */ + gen_pool_free(lv2table_pool, lv1ent_page(domain->pgtable + i), + LV2TABLE_AND_REFBUF_SZ); +#endif + } +} +EXPORT_SYMBOL(pcie_sysmmu_all_buff_free); + +static int get_hw_version(struct sysmmu_drvdata *drvdata, void __iomem *sfrbase) +{ + int ret; + + /* NEED TO CHECK : enable/disable is needed? */ + __sysmmu_enable_nocount(drvdata, drvdata->pcie_vid); + + ret = MMU_RAW_VER(__raw_readl(sfrbase + REG_MMU_VERSION)); + + __sysmmu_disable_nocount(drvdata, drvdata->pcie_vid); + + return ret; +} + +static const char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = { + "PTW ACCESS FAULT", + "PAGE FAULT", + "RESERVED", + "ACCESS FAULT", + "SECURITY FAULT", + "UNKNOWN FAULT" +}; + +static unsigned int dump_tlb_entry_port_type(void __iomem *sfrbase, + int idx_way, int idx_set) +{ + if (MMU_TLB_ENTRY_VALID(__raw_readl(sfrbase + REG_CAPA1_TLB_ATTR))) { + pr_err("[%02d][%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n", + idx_way, idx_set, + __raw_readl(sfrbase + REG_CAPA1_TLB_VPN), + __raw_readl(sfrbase + REG_CAPA1_TLB_PPN), + __raw_readl(sfrbase + REG_CAPA1_TLB_ATTR)); + return 1; + } + return 0; +} + +#define MMU_NUM_TLB_SUBLINE 4 +static void dump_sysmmu_tlb_port(struct sysmmu_drvdata *drvdata) +{ + int t, i, j, k; + u32 capa0, capa1, info; + unsigned int cnt; + int num_tlb, num_port, num_sbb; + void __iomem *sfrbase = drvdata->sfrbase; + + capa0 = __raw_readl(sfrbase + REG_MMU_CAPA0_V7); + capa1 = __raw_readl(sfrbase + REG_MMU_CAPA1_V7); + + num_tlb = MMU_CAPA1_NUM_TLB(capa1); + num_port = MMU_CAPA1_NUM_PORT(capa1); + num_sbb = 1 << MMU_CAPA_NUM_SBB_ENTRY(capa0); + + pr_err("SysMMU has %d TLBs, %d ports, %d sbb entries\n", + num_tlb, num_port, num_sbb); + + for (t = 0; t < num_tlb; t++) { + int num_set, num_way; + + info = __raw_readl(sfrbase + MMU_TLB_INFO(t)); + num_way = MMU_CAPA1_NUM_TLB_WAY(info); + num_set = MMU_CAPA1_NUM_TLB_SET(info); + + pr_err("TLB.%d has %d way, %d set.\n", t, num_way, num_set); + pr_err("------------- TLB[WAY][SET][ENTRY] -------------\n"); + for (i = 0, cnt = 0; i < num_way; i++) { + for (j = 0; j < num_set; j++) { + for (k = 0; k < MMU_NUM_TLB_SUBLINE; k++) { + __raw_writel(MMU_CAPA1_SET_TLB_READ_ENTRY(t, j, i, k), + sfrbase + REG_CAPA1_TLB_READ); + cnt += dump_tlb_entry_port_type(sfrbase, i, j); + } + } + } + } + if (!cnt) + pr_err(">> No Valid TLB Entries\n"); + + pr_err("--- SBB(Second-Level Page Table Base Address Buffer ---\n"); + for (i = 0, cnt = 0; i < num_sbb; i++) { + __raw_writel(i, sfrbase + REG_CAPA1_SBB_READ); + if (MMU_SBB_ENTRY_VALID(__raw_readl(sfrbase + REG_CAPA1_SBB_VPN))) { + pr_err("[%02d] VPN: %#010x, PPN: %#010x, ATTR: %#010x\n", + i, __raw_readl(sfrbase + REG_CAPA1_SBB_VPN), + __raw_readl(sfrbase + REG_CAPA1_SBB_LINK), + __raw_readl(sfrbase + REG_CAPA1_SBB_ATTR)); + cnt++; + } + } + if (!cnt) + pr_err(">> No Valid SBB Entries\n"); +} + +void print_pcie_sysmmu_tlb(int hsi_block_num) +{ + phys_addr_t pgtable; + int pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + + pgtable = __raw_readl(g_sysmmu_drvdata[hsi_block_num]->sfrbase + + REG_PT_BASE_PPN_VID(pcie_vid)); + pgtable <<= PAGE_SHIFT; + pr_info("Page Table Base Address : 0x%pap\n", &pgtable); + + dump_sysmmu_tlb_port(g_sysmmu_drvdata[hsi_block_num]); +} +EXPORT_SYMBOL(print_pcie_sysmmu_tlb); + +static int show_fault_information(struct sysmmu_drvdata *drvdata, int flags, + unsigned long fault_addr, int pcie_vid) +{ + unsigned int info; + phys_addr_t pgtable; + int fault_id = SYSMMU_FAULT_ID(flags); + const char *port_name = NULL; + int ret = 0; + + pgtable = __raw_readl(drvdata->sfrbase + REG_PT_BASE_PPN_VID(pcie_vid)); + pgtable <<= PAGE_SHIFT; + + if (MMU_MAJ_VER(drvdata->version) >= 7) { + info = __raw_readl(drvdata->sfrbase + REG_FAULT_INFO0); + } else { + /* TODO: Remove me later */ + info = __raw_readl(drvdata->sfrbase + + ((flags & IOMMU_FAULT_WRITE) ? + REG_FAULT_AW_TRANS_INFO : REG_FAULT_AR_TRANS_INFO)); + } + + of_property_read_string(drvdata->sysmmu->of_node, + "port-name", &port_name); + + pr_err("----------------------------------------------------------\n"); + pr_err("From [%s], SysMMU %s %s at %#010lx (page table @ %pa)\n", + port_name ? port_name : dev_name(drvdata->sysmmu), + (flags & IOMMU_FAULT_WRITE) ? "WRITE" : "READ", + sysmmu_fault_name[fault_id], fault_addr, &pgtable); + + if (fault_id == SYSMMU_FAULT_UNKNOWN) { + pr_err("The fault is not caused by this System MMU.\n"); + pr_err("Please check IRQ and SFR base address.\n"); + goto finish; + } + + pr_err("AxID: %#x, AxLEN: %#x\n", info & 0xFFFF, (info >> 16) & 0xF); + + if (pgtable != drvdata->pgtable) + pr_err("Page table base of driver: %pa\n", + &drvdata->pgtable); + + if (fault_id == SYSMMU_FAULT_PTW_ACCESS) + pr_err("System MMU has failed to access page table\n"); + + if (!pfn_valid(pgtable >> PAGE_SHIFT)) { + pr_err("Page table base is not in a valid memory region\n"); + } else { + sysmmu_pte_t *ent; + + ent = section_entry(phys_to_virt(pgtable), fault_addr); + pr_err("Lv1 entry: %#010x\n", *ent); + + if (lv1ent_page(ent)) { + u64 sft_ent_addr, sft_fault_addr; + + ent = page_entry(ent, fault_addr); + pr_err("Lv2 entry: %#010x\n", *ent); + + sft_ent_addr = (*ent) >> 8; + sft_fault_addr = fault_addr >> 12; + + if (sft_ent_addr == sft_fault_addr) { + pr_err("ent(%#llx) == faddr(%#llx)...\n", + sft_ent_addr, sft_fault_addr); + pr_err("Try to IGNORE Page fault panic...\n"); + ret = SYSMMU_NO_PANIC; + wrong_pf_cnt++; + } + } + } + + dump_sysmmu_tlb_port(drvdata); +finish: + pr_err("----------------------------------------------------------\n"); + + return ret; +} + +static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id) +{ + struct sysmmu_drvdata *drvdata = dev_id; + unsigned int itype; + unsigned long addr = ~0UL; + int flags = 0; + u32 info; + u32 int_status; + int ret; + int pcie_vid; + + dev_info(drvdata->sysmmu, "irq(%d) happened\n", irq); + + WARN(!is_sysmmu_active(drvdata), + "Fault occurred while System MMU %s is not enabled!\n", + dev_name(drvdata->sysmmu)); + + int_status = __raw_readl(drvdata->sfrbase + REG_INT_STATUS); + itype = __ffs(int_status); + pcie_vid = itype / 4; + itype %= 4; + /* We use only VID 0. */ + if (WARN_ON(!(itype < SYSMMU_FAULT_UNKNOWN))) + itype = SYSMMU_FAULT_UNKNOWN; + else { + addr = __raw_readl(drvdata->sfrbase + REG_FAULT_ADDR_VA); + /* It support 36bit address */ + addr |= (unsigned long)((__raw_readl(drvdata->sfrbase + + REG_FAULT_INFO0) >> 28) + & 0xf) << 32; + } + + info = __raw_readl(drvdata->sfrbase + REG_FAULT_INFO0); + flags = MMU_IS_READ_FAULT(info) ? + IOMMU_FAULT_READ : IOMMU_FAULT_WRITE; + flags |= SYSMMU_FAULT_FLAG(itype); + + /* Clear interrupts */ + writel_relaxed(int_status, drvdata->sfrbase + REG_INT_CLEAR); + + ret = show_fault_information(drvdata, flags, addr, pcie_vid); + if (ret == SYSMMU_NO_PANIC) + return IRQ_HANDLED; + + atomic_notifier_call_chain(&drvdata->fault_notifiers, addr, &flags); + + panic("Unrecoverable System MMU Fault!!"); + + return IRQ_HANDLED; +} + +static void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *drvdata, + dma_addr_t iova, size_t size, int pcie_vid) +{ + void * __iomem sfrbase = drvdata->sfrbase; + u32 start_addr, end_addr; + + start_addr = (iova >> 4) & 0xffffff00; + writel_relaxed(start_addr, sfrbase + REG_FLUSH_RANGE_START_VID(pcie_vid)); + + end_addr = ((iova + size - 1) >> 4) & 0xffffff00; + writel_relaxed(end_addr, sfrbase + REG_FLUSH_RANGE_END_VID(pcie_vid)); + + writel(0x1, sfrbase + REG_MMU_FLUSH_RANGE_VID(pcie_vid)); +} + +static void exynos_sysmmu_tlb_invalidate(dma_addr_t d_start, size_t size, + int pcie_vid, int hsi_block_num) +{ + struct sysmmu_drvdata *drvdata = g_sysmmu_drvdata[hsi_block_num]; + sysmmu_iova_t start = (sysmmu_iova_t)d_start; + + spin_lock(&drvdata->lock); + if (!is_sysmmu_active(drvdata)) { + spin_unlock(&drvdata->lock); + dev_dbg(drvdata->sysmmu, + "Skip TLB invalidation %#zx@%#llx\n", size, start); + return; + } + + dev_dbg(drvdata->sysmmu, + "TLB invalidation %#zx@%#llx\n", size, start); + + __sysmmu_tlb_invalidate(drvdata, start, size, pcie_vid); + + spin_unlock(&drvdata->lock); +} + +static void clear_lv2_page_table(sysmmu_pte_t *ent, int n) +{ + if (n > 0) + memset(ent, 0, sizeof(*ent) * n); +} + +static int lv1set_section(struct exynos_iommu_domain *domain, + sysmmu_pte_t *sent, sysmmu_iova_t iova, + phys_addr_t paddr, int prot, atomic_t *pgcnt) +{ + bool shareable = !!(prot & IOMMU_CACHE); + + if (lv1ent_section(sent)) { + WARN(1, "Trying mapping on 1MiB@%#09llx that is mapped", iova); + return -EADDRINUSE; + } + + if (lv1ent_page(sent)) { + if (WARN_ON(atomic_read(pgcnt) != NUM_LV2ENTRIES)) { + WARN(1, "Trying mapping on 1MiB@%#09llx that is mapped", + iova); + return -EADDRINUSE; + } + /* TODO: for v7, free lv2 page table */ + } + + *sent = mk_lv1ent_sect(paddr); + if (shareable) + set_lv1ent_shareable(sent); + pgtable_flush(sent, sent + 1); + + return 0; +} + +static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size, + int prot, atomic_t *pgcnt, int hsi_block_num) +{ + bool shareable = !!(prot & IOMMU_CACHE); + + if (size == SPAGE_SIZE) { + if (!lv2ent_fault(pent)) { + sysmmu_pte_t *refcnt_buf; + + if(hsi_block_num == 1) { + pr_err("sysmmu(CP) lv2set_page: paddr: 0x%llx, size: 0x%lx, pent: 0x%x\n", paddr, size, *pent); + } + + /* Duplicated IOMMU map 4KB */ + refcnt_buf = pent + NUM_LV2ENTRIES; + *refcnt_buf = *refcnt_buf + 1; + atomic_dec(pgcnt); + return 0; + } + + *pent = mk_lv2ent_spage(paddr); + if (shareable) + set_lv2ent_shareable(pent); + pgtable_flush(pent, pent + 1); + atomic_dec(pgcnt); + } else { /* size == LPAGE_SIZE */ + int i; + + pr_debug("Allocate LPAGE_SIZE!!!\n"); + for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) { + if (WARN_ON(!lv2ent_fault(pent))) { + clear_lv2_page_table(pent - i, i); + return -EADDRINUSE; + } + + *pent = mk_lv2ent_lpage(paddr); + if (shareable) + set_lv2ent_shareable(pent); + } + pgtable_flush(pent - SPAGES_PER_LPAGE, pent); + /* Need to add refcnt process */ + atomic_sub(SPAGES_PER_LPAGE, pgcnt); + } + + return 0; +} + +#ifdef USE_DYNAMIC_MEM_ALLOC +static sysmmu_pte_t *alloc_extend_buff(struct exynos_iommu_domain *domain) +{ + sysmmu_pte_t *alloc_buff = NULL; + int i; + + /* Find Empty buffer */ + for (i = 0; i < MAX_EXT_BUFF_NUM; i++) { + if (domain->ext_buff[i].used == 0) { + pr_debug("Use extend buffer index : %d...\n", i); + break; + } + } + + if (i == MAX_EXT_BUFF_NUM) { + pr_err("WARNNING - Extend buffers are full!!!\n"); + return NULL; + } + + domain->ext_buff[i].used = 1; + alloc_buff = domain->ext_buff[i].buff; + + return alloc_buff; +} +#endif + +static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *domain, + sysmmu_pte_t *sent, sysmmu_iova_t iova, + atomic_t *pgcounter, gfp_t gfpmask) +{ + sysmmu_pte_t *pent = NULL; + + if (lv1ent_section(sent)) { + WARN(1, "Trying mapping on %#09llx mapped with 1MiB page", + iova); + return ERR_PTR(-EADDRINUSE); + } + + if (lv1ent_fault(sent)) { + lv2table_counter++; + +#ifdef USE_DYNAMIC_MEM_ALLOC + pent = kmem_cache_zalloc(lv2table_kmem_cache, gfpmask); + if (!pent) { + /* Use extended Buffer */ + pent = alloc_extend_buff(domain); + + if (!pent) + return ERR_PTR(-ENOMEM); + } +#else /* USE gen_pool */ + if (gen_pool_avail(lv2table_pool) >= LV2TABLE_AND_REFBUF_SZ) { + pent = phys_to_virt(gen_pool_alloc(lv2table_pool, LV2TABLE_AND_REFBUF_SZ)); + } else { + pr_info("Gen_pool is full!! Try dynamic alloc\n"); + pent = kmem_cache_zalloc(lv2table_kmem_cache, gfpmask); + if (!pent) + return ERR_PTR(-ENOMEM); + } +#endif + + *sent = mk_lv1ent_page(virt_to_phys(pent)); + pgtable_flush(sent, sent + 1); + atomic_set(pgcounter, NUM_LV2ENTRIES); + kmemleak_ignore(pent); + } + + return page_entry(sent, iova); +} + +static size_t iommu_pgsize(unsigned long addr_merge, size_t size, + struct exynos_iommu_domain *domain) +{ + unsigned int pgsize_idx; + size_t pgsize; + + /* Max page size that still fits into 'size' */ + pgsize_idx = __fls(size); + + /* need to consider alignment requirements ? */ + if (likely(addr_merge)) { + /* Max page size allowed by address */ + unsigned int align_pgsize_idx = __ffs(addr_merge); + + pgsize_idx = min(pgsize_idx, align_pgsize_idx); + } + + /* build a mask of acceptable page sizes */ + pgsize = (1UL << (pgsize_idx + 1)) - 1; + + /* throw away page sizes not supported by the hardware */ + pgsize &= domain->pgsize_bitmap; + + if (WARN_ON(!pgsize)) + return 0; + + /* pick the biggest page */ + pgsize_idx = __fls(pgsize); + pgsize = 1UL << pgsize_idx; + + return pgsize; +} + +static int exynos_iommu_map(unsigned long l_iova, phys_addr_t paddr, + size_t size, int prot, + struct exynos_iommu_domain *domain, int hsi_block_num) +{ + sysmmu_pte_t *entry; + sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; + int ret = -ENOMEM; + + if (WARN_ON(!domain->pgtable)) + return -EINVAL; + + entry = section_entry(domain->pgtable, iova); + + if (size == SECT_SIZE) { + ret = lv1set_section(domain, entry, iova, paddr, prot, + &domain->lv2entcnt[lv1ent_offset(iova)]); + } else { + sysmmu_pte_t *pent; + + pent = alloc_lv2entry(domain, entry, iova, + &domain->lv2entcnt[lv1ent_offset(iova)], + GFP_ATOMIC); + + if (IS_ERR(pent)) + ret = PTR_ERR(pent); + else + ret = lv2set_page(pent, paddr, size, prot, + &domain->lv2entcnt[lv1ent_offset(iova)], hsi_block_num); + } + + if (ret) + pr_err("%s: Failed(%d) to map %#zx bytes @ %#llx\n", + __func__, ret, size, iova); + + return ret; +} + +static size_t exynos_iommu_unmap(unsigned long l_iova, size_t size, + struct exynos_iommu_domain *domain) +{ + sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; + sysmmu_pte_t *sent, *pent; + size_t err_pgsize; + atomic_t *lv2entcnt = &domain->lv2entcnt[lv1ent_offset(iova)]; + + if (WARN_ON(!domain->pgtable)) + return 0; + + sent = section_entry(domain->pgtable, iova); + + if (lv1ent_section(sent)) { + if (WARN_ON(size < SECT_SIZE)) { + err_pgsize = SECT_SIZE; + goto err; + } + + *sent = 0; + pgtable_flush(sent, sent + 1); + size = SECT_SIZE; + goto done; + } + + if (unlikely(lv1ent_fault(sent))) { + if (size > SECT_SIZE) + size = SECT_SIZE; + goto done; + } + + /* lv1ent_page(sent) == true here */ + + pent = page_entry(sent, iova); + + if (unlikely(lv2ent_fault(pent))) { + size = SPAGE_SIZE; + goto done; + } + + if (lv2ent_small(pent)) { + /* Check Duplicated IOMMU Unmp */ + sysmmu_pte_t *refcnt_buf; + + refcnt_buf = (pent + NUM_LV2ENTRIES); + if (*refcnt_buf != 0) { + *refcnt_buf = *refcnt_buf - 1; + atomic_inc(lv2entcnt); + goto done; + } + + *pent = 0; + size = SPAGE_SIZE; + pgtable_flush(pent, pent + 1); + atomic_inc(lv2entcnt); + goto unmap_flpd; + } + + /* lv1ent_large(pent) == true here */ + if (WARN_ON(size < LPAGE_SIZE)) { + err_pgsize = LPAGE_SIZE; + goto err; + } + + clear_lv2_page_table(pent, SPAGES_PER_LPAGE); + pgtable_flush(pent, pent + SPAGES_PER_LPAGE); + size = LPAGE_SIZE; + atomic_add(SPAGES_PER_LPAGE, lv2entcnt); + +unmap_flpd: + /* TODO: for v7, remove all */ + if (atomic_read(lv2entcnt) == NUM_LV2ENTRIES) { + sysmmu_pte_t *free_buff; + phys_addr_t __maybe_unused paddr; + + free_buff = page_entry(sent, 0); + paddr = virt_to_phys(free_buff); + lv2table_counter--; + + *sent = 0; + pgtable_flush(sent, sent + 1); + atomic_set(lv2entcnt, 0); + +#ifdef USE_DYNAMIC_MEM_ALLOC + if (free_buff >= domain->ext_buff[0].buff && + free_buff <= domain->ext_buff[MAX_EXT_BUFF_NUM - 1].buff) { + /* Allocated from extend buffer */ + u64 index = (u64)free_buff - (u64)domain->ext_buff[0].buff; + + index /= SZ_2K; + if (index < MAX_EXT_BUFF_NUM) { + pr_debug("Extend buffer %llu free...\n", index); + domain->ext_buff[index].used = 0; + } else { + pr_warn("WARN - Lv2table free ERR!!!\n"); + } + } else { + kmem_cache_free(lv2table_kmem_cache, free_buff); + } +#else /* USE gen_pool */ + if (gen_pool_has_addr(lv2table_pool, paddr, LV2TABLE_AND_REFBUF_SZ)) + gen_pool_free(lv2table_pool, paddr, LV2TABLE_AND_REFBUF_SZ); + else + kmem_cache_free(lv2table_kmem_cache, free_buff); +#endif + } + +done: + + return size; +err: + pr_err("%s: Failed: size(%#zx)@%#llx is smaller than page size %#zx\n", + __func__, size, iova, err_pgsize); + + return 0; +} + +#if IS_ENABLED(CONFIG_PCIE_IOMMU_HISTORY_LOG) +static inline void add_history_buff(struct history_buff *hbuff, + phys_addr_t addr, phys_addr_t orig_addr, + size_t size, size_t orig_size) +{ + hbuff->save_addr[hbuff->index] = (u32)((addr >> 0x4) & 0xffffffff); + hbuff->orig_addr[hbuff->index] = (u32)((orig_addr >> 0x4) & 0xffffffff); + hbuff->size[hbuff->index] = size; + hbuff->orig_size[hbuff->index] = orig_size; + hbuff->index++; + if (hbuff->index >= MAX_HISTORY_BUFF) + hbuff->index = 0; +} +#endif + +static inline int check_memory_validation(phys_addr_t paddr) +{ + int ret; + + ret = pfn_valid(paddr >> PAGE_SHIFT); + if (!ret) { + pr_err("Requested address 0x%pap is NOT in DRAM region!!\n", &paddr); + return -EINVAL; + } + + return 0; +} + +static int exynos_iommu_map_once(unsigned long l_iova, phys_addr_t paddr, + size_t size, int prot, struct exynos_iommu_domain *domain, + int hsi_block_num) +{ + struct sysmmu_drvdata *drvdata = g_sysmmu_drvdata[hsi_block_num]; + struct device *dev = drvdata->sysmmu; + sysmmu_pte_t *entry, *pent; + sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; + int i, cnt, ret = 0; + bool shareable = !!(prot & IOMMU_CACHE); + atomic_t *pgcnt = &domain->lv2entcnt[lv1ent_offset(iova)]; + + BUG_ON(domain->pgtable == NULL); + + /* Check it is over section size at one request. */ + if ((iova & ~SECT_MASK) + size > SECT_SIZE) { + dev_err_ratelimited(dev, + "%s: Don't allow address + size over is section size (0x%llx + 0x%zx)\n", + __func__, iova, size); + return -EINVAL; + } + + entry = section_entry(domain->pgtable, iova); + + pent = alloc_lv2entry(domain, entry, iova, + &domain->lv2entcnt[lv1ent_offset(iova)], + GFP_ATOMIC); + if (IS_ERR(pent)) { + ret = PTR_ERR(pent); + dev_err_ratelimited(dev, "%s: Can't alloc LV2 table!\n", __func__); + return ret; + } + + cnt = size / SZ_4K; + for (i = 0; i < cnt; i++, pent++) { + if (!lv2ent_fault(pent)) { + sysmmu_pte_t *refcnt_buf; + + dev_err_ratelimited(dev, + "%s: Duplicated Memory Allocation : PTE will be overwritten!\n", + __func__); + /* Duplicated IOMMU map 4KB */ + refcnt_buf = pent + NUM_LV2ENTRIES; + *refcnt_buf = *refcnt_buf + 1; + } + + *pent = mk_lv2ent_spage(paddr); + if (shareable) + set_lv2ent_shareable(pent); + paddr += SZ_4K; + } + pgtable_flush(pent - cnt, pent); + atomic_sub(cnt, pgcnt); + + return ret; +} + +int pcie_iommu_map(unsigned long iova, phys_addr_t paddr, size_t size, + int prot, int hsi_block_num) +{ + struct exynos_iommu_domain *domain = + g_sysmmu_drvdata[hsi_block_num]->domain; + unsigned long orig_iova = iova; + unsigned int min_pagesz; + size_t orig_size = size; + phys_addr_t __maybe_unused orig_paddr = paddr; + int ret = 0; + unsigned long changed_iova, changed_size; + unsigned long flags; + int pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + +#ifdef ENABLE_DRAM_REGION_VALIDATION + if (check_memory_validation(paddr) != 0) { + pr_warn("WARN - Unexpected address request : 0x%pap\n", &paddr); + return -EINVAL; + } +#endif + + /* Make sure start address align least 4KB */ + if ((iova & SYSMMU_4KB_MASK) != 0) { + size += iova & SYSMMU_4KB_MASK; + iova &= ~(SYSMMU_4KB_MASK); + paddr &= ~(SYSMMU_4KB_MASK); + } + /* Make sure size align least 4KB */ + if ((size & SYSMMU_4KB_MASK) != 0) { + size &= ~(SYSMMU_4KB_MASK); + size += SZ_4K; + } + + /* Check for debugging */ + changed_iova = iova; + changed_size = size; + + /* find out the minimum page size supported */ + min_pagesz = 1 << __ffs(domain->pgsize_bitmap); + + /* + * both the virtual address and the physical one, as well as + * the size of the mapping, must be aligned (at least) to the + * size of the smallest page supported by the hardware + */ + if (!IS_ALIGNED(iova | paddr | size, min_pagesz)) { + pr_err("unaligned: iova 0x%lx pa 0x%pap sz 0x%zx min_pagesz 0x%x\n", + iova, &paddr, size, min_pagesz); + return -EINVAL; + } + + spin_lock_irqsave(&domain->pgtablelock, flags); + + if (g_sysmmu_drvdata[hsi_block_num]->use_map_once) { + if (size < SZ_64K) { /* This code assume that there is no LARGE Pages(64KB) */ + ret = exynos_iommu_map_once( + iova, paddr, size, prot, domain, hsi_block_num); + if (ret == 0) + goto end_map; + } + } + + while (size) { + size_t pgsize = iommu_pgsize(iova | paddr, size, domain); + + if (!pgsize) { + ret = -EINVAL; + break; + } + + pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx\n", + iova, &paddr, pgsize); + + alloc_counter++; + if (alloc_counter > max_req_cnt) + max_req_cnt = alloc_counter; + ret = exynos_iommu_map(iova, paddr, pgsize, prot, domain, hsi_block_num); +#if IS_ENABLED(CONFIG_PCIE_IOMMU_HISTORY_LOG) + add_history_buff(&pcie_map_history, paddr, orig_paddr, + changed_size, orig_size); +#endif + if (ret) + break; + + iova += pgsize; + paddr += pgsize; + size -= pgsize; + } +end_map: + if (!g_sysmmu_drvdata[hsi_block_num]->ignore_tlb_inval) { + exynos_sysmmu_tlb_invalidate(orig_iova, orig_size, pcie_vid, + hsi_block_num); + } + spin_unlock_irqrestore(&domain->pgtablelock, flags); + + /* unroll mapping in case something went wrong */ + if (ret) { + pr_err("PCIe SysMMU mapping Error!\n"); + pcie_iommu_unmap(orig_iova, orig_size - size, hsi_block_num); + } + + pr_debug("mapped: req 0x%lx(org : 0x%lx) size 0x%zx(0x%zx)\n", + changed_iova, orig_iova, changed_size, orig_size); + + return ret; +} +EXPORT_SYMBOL_GPL(pcie_iommu_map); + +static size_t exynos_iommu_unmap_once(unsigned long l_iova, size_t size, + struct exynos_iommu_domain *domain, int hsi_block_num) +{ + struct sysmmu_drvdata *drvdata = g_sysmmu_drvdata[hsi_block_num]; + struct device *dev = drvdata->sysmmu; + sysmmu_iova_t iova = (sysmmu_iova_t)l_iova; + sysmmu_pte_t *sent, *pent; + atomic_t *lv2entcnt = &domain->lv2entcnt[lv1ent_offset(iova)]; + int cnt, i; + + BUG_ON(domain->pgtable == NULL); + + /* Check it is over section size at one request. */ + if ((iova & ~SECT_MASK) + size > SECT_SIZE) { + dev_err_ratelimited(dev, + "%s: Don't allow address + size over is section size (0x%llx + 0x%zx)\n", + __func__, iova, size); + return 0; + } + + sent = section_entry(domain->pgtable, iova); + + if (unlikely(lv1ent_fault(sent))) { + dev_err_ratelimited(dev, "%s : LV1 entry fault!\n", __func__); + return 0; + } + + /* lv1ent_page(sent) == true here */ + + pent = page_entry(sent, iova); + + /* If it is large page, return err and try to do normal unmap!! */ + if (lv2ent_large(pent)) { + return 0; + } + + cnt = size / SZ_4K; + + for (i = 0; i < cnt; i++, pent++) { + /* Check Duplicated IOMMU Unmp */ + sysmmu_pte_t *refcnt_buf; + + refcnt_buf = (pent + NUM_LV2ENTRIES); + if (*refcnt_buf != 0) { + dev_err_ratelimited(dev, + "%s: VA: 0x%llx's ref conunt is not 0 - SKIP unmap\n", + __func__, iova); + *refcnt_buf = *refcnt_buf - 1; + atomic_inc(lv2entcnt); + continue; + } + + *pent = 0; + } + pgtable_flush(pent - cnt, pent); + atomic_add(cnt, lv2entcnt); + + /* Ignore Free LV2 table at here. */ + + return size; +} + +size_t pcie_iommu_unmap(unsigned long iova, size_t size, int hsi_block_num) +{ + struct exynos_iommu_domain *domain = + g_sysmmu_drvdata[hsi_block_num]->domain; + size_t unmapped_page, unmapped = 0; + unsigned int min_pagesz; + unsigned long __maybe_unused orig_iova = iova; + unsigned long __maybe_unused changed_iova; + size_t __maybe_unused orig_size = size; + unsigned long flags; + int pcie_vid = g_sysmmu_drvdata[hsi_block_num]->pcie_vid; + + /* Make sure start address align least 4KB */ + if ((iova & SYSMMU_4KB_MASK) != 0) { + size += iova & SYSMMU_4KB_MASK; + iova &= ~(SYSMMU_4KB_MASK); + } + /* Make sure size align least 4KB */ + if ((size & SYSMMU_4KB_MASK) != 0) { + size &= ~(SYSMMU_4KB_MASK); + size += SZ_4K; + } + + changed_iova = iova; + + /* find out the minimum page size supported */ + min_pagesz = 1 << __ffs(domain->pgsize_bitmap); + + /* + * The virtual address, as well as the size of the mapping, must be + * aligned (at least) to the size of the smallest page supported + * by the hardware + */ + if (!IS_ALIGNED(iova | size, min_pagesz)) { + pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n", + iova, size, min_pagesz); + return -EINVAL; + } + + pr_debug("unmap this: iova 0x%lx size 0x%zx\n", iova, size); + + spin_lock_irqsave(&domain->pgtablelock, flags); + + if (g_sysmmu_drvdata[hsi_block_num]->use_map_once) { + if (size < SZ_64K) { /* This code assume that there is no LARGE Pages(64KB) */ + unmapped = exynos_iommu_unmap_once(iova, size, domain, hsi_block_num); + if (unmapped == size) + goto end_unmap; + } + } + + /* + * Keep iterating until we either unmap 'size' bytes (or more) + * or we hit an area that isn't mapped. + */ + while (unmapped < size) { + size_t pgsize = iommu_pgsize(iova, size - unmapped, domain); + + if (!pgsize) { + pr_err("pgsize err: iova 0x%lx size 0x%zx unmapped 0x%zx\n", + iova, size, unmapped); + break; + } + + alloc_counter--; + unmapped_page = exynos_iommu_unmap(iova, pgsize, domain); +#if IS_ENABLED(CONFIG_PCIE_IOMMU_HISTORY_LOG) + add_history_buff(&pcie_unmap_history, iova, orig_iova, + size, orig_size); +#endif + if (!unmapped_page) + break; + + pr_debug("unmapped: iova 0x%lx size 0x%zx\n", + iova, unmapped_page); + + iova += unmapped_page; + unmapped += unmapped_page; + } +end_unmap: + if (!g_sysmmu_drvdata[hsi_block_num]->ignore_tlb_inval) { + exynos_sysmmu_tlb_invalidate(orig_iova, orig_size, pcie_vid, + hsi_block_num); + } + spin_unlock_irqrestore(&domain->pgtablelock, flags); + + pr_debug("UNMAPPED : req 0x%lx(0x%lx) size 0x%zx(0x%zx)\n", + changed_iova, orig_iova, size, orig_size); + + return unmapped; +} +EXPORT_SYMBOL_GPL(pcie_iommu_unmap); + +static int __init sysmmu_parse_dt(struct device *sysmmu, + struct sysmmu_drvdata *drvdata) +{ + unsigned int qos = DEFAULT_QOS_VALUE, val; + const char *use_tlb_pinning; + const char *use_map_once; + int ret = 0; + + /* Parsing QoS */ + ret = of_property_read_u32_index(sysmmu->of_node, "qos", 0, &qos); + if (!ret && qos > 15) { + dev_err(sysmmu, "Invalid QoS value %d, use default.\n", qos); + qos = DEFAULT_QOS_VALUE; + } + drvdata->qos = qos; + + /* Set HSI block number */ + if (of_property_read_u32(sysmmu->of_node, "hsi-block-num", &val)) { + dev_err(sysmmu, "WARNNING : There is NO HSI block!!!\n"); + ret = -EINVAL; + } + drvdata->hsi_block_num = val; + + /* Set PCIe VID number */ + if (of_property_read_u32(sysmmu->of_node, "pcie-vid-num", &val)) { + dev_err(sysmmu, "WARNNING : There is NO PCIe VID!!!\n"); + ret = -EINVAL; + } + drvdata->pcie_vid = val; + + if (of_property_read_bool(sysmmu->of_node, "sysmmu,no-suspend")) + dev_pm_syscore_device(sysmmu, true); + + if (!of_property_read_string(sysmmu->of_node, + "use-tlb-pinning", &use_tlb_pinning)) { + if (!strcmp(use_tlb_pinning, "true")) { + dev_err(sysmmu, "Enable TLB Pinning.\n"); + drvdata->use_tlb_pinning = true; + } else if (!strcmp(use_tlb_pinning, "false")) { + drvdata->use_tlb_pinning = false; + } else { + dev_err(sysmmu, "Invalid TLB pinning value (set to default -> false)\n"); + drvdata->use_tlb_pinning = false; + } + } else { + drvdata->use_tlb_pinning = false; + } + + /* Set ignore tlb inval */ + if (of_property_read_u32(sysmmu->of_node, "ignore-tlb-inval", &val)) { + dev_info(sysmmu, "There is NO ignore tlb inval, so set default value(0)\n"); + drvdata->ignore_tlb_inval = 0; + } + else { + drvdata->ignore_tlb_inval = val; + } + + if (!of_property_read_string(sysmmu->of_node, + "use-map-once", &use_map_once)) { + if (!strcmp(use_map_once, "true")) { + dev_err(sysmmu, "Enable map once.\n"); + drvdata->use_map_once = true; + } else if (!strcmp(use_map_once, "false")) { + drvdata->use_map_once = false; + } else { + dev_err(sysmmu, "Invalid map once value (set to default -> false)\n"); + drvdata->use_map_once = false; + } + } else { + drvdata->use_map_once = false; + } + + return 0; +} + +static struct exynos_iommu_domain *exynos_iommu_domain_alloc(struct device *dev) +{ + struct exynos_iommu_domain *domain; + int __maybe_unused i; + + domain = devm_kzalloc(dev, sizeof(*domain), GFP_KERNEL); + if (!domain) + return NULL; + + /* 36bit VA FLPD must be aligned in 256KB */ + domain->pgtable = + (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 6); + if (!domain->pgtable) + goto err_pgtable; + + domain->lv2entcnt = (atomic_t *) + __get_free_pages(GFP_KERNEL | __GFP_ZERO, 6); + if (!domain->lv2entcnt) + goto err_counter; + + pgtable_flush(domain->pgtable, domain->pgtable + NUM_LV1ENTRIES); + + spin_lock_init(&domain->lock); + spin_lock_init(&domain->pgtablelock); + INIT_LIST_HEAD(&domain->clients_list); + + /* TODO: get geometry from device tree */ + domain->domain.geometry.aperture_start = 0; + domain->domain.geometry.aperture_end = ~0UL; + domain->domain.geometry.force_aperture = true; + + domain->pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE; + +#ifdef USE_DYNAMIC_MEM_ALLOC + domain->ext_buff[0].buff = + devm_kzalloc(dev, SZ_2K * MAX_EXT_BUFF_NUM, GFP_KERNEL); + + if (!domain->ext_buff[0].buff) + goto err_ext_buff; + + /* ext_buff[0] is already initialized */ + for (i = 1; i < MAX_EXT_BUFF_NUM; i++) { + domain->ext_buff[i].index = i; + domain->ext_buff[i].used = 0; + domain->ext_buff[i].buff = + domain->ext_buff[i - 1].buff + + (SZ_2K / sizeof(sysmmu_pte_t)); + } +#endif + + return domain; + +#ifdef USE_DYNAMIC_MEM_ALLOC +err_ext_buff: + free_pages((unsigned long)domain->lv2entcnt, 6); +#endif + +err_counter: + free_pages((unsigned long)domain->pgtable, 6); +err_pgtable: + kfree(domain); + return NULL; +} + +static int __init exynos_sysmmu_probe(struct platform_device *pdev) +{ + int irq, ret; + struct device *dev = &pdev->dev; + struct sysmmu_drvdata *data; + struct resource *res; + int __maybe_unused i; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "Failed to get resource info\n"); + return -ENOENT; + } + + data->sfrbase = devm_ioremap_resource(dev, res); + if (IS_ERR(data->sfrbase)) + return PTR_ERR(data->sfrbase); + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) { + dev_err(dev, "Unable to find IRQ resource\n"); + return irq; + } + + ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0, dev_name(dev), + data); + if (ret) { + dev_err(dev, "Unable to register handler of irq %d\n", irq); + return ret; + } + + data->sysmmu = dev; + g_last_dev = dev; + spin_lock_init(&data->lock); + ATOMIC_INIT_NOTIFIER_HEAD(&data->fault_notifiers); + + platform_set_drvdata(pdev, data); + + data->qos = DEFAULT_QOS_VALUE; + spin_lock_init(&data->mmu_ctrl_lock); + + data->version = get_hw_version(data, data->sfrbase); + + ret = sysmmu_parse_dt(data->sysmmu, data); + if (ret) { + dev_err(dev, "Failed to parse DT\n"); + return ret; + } + g_sysmmu_drvdata[data->hsi_block_num] = data; + + /* Create PCIe Channel0/1 domains */ + data->domain = exynos_iommu_domain_alloc(dev); + if (!data->domain) + return -ENOMEM; + + data->pgtable = virt_to_phys(data->domain->pgtable); + + dev_info(dev, "Probe HSI%d block, PCIe VID : %d\n", + data->hsi_block_num, data->pcie_vid); + dev_info(dev, "L1Page Table Address : 0x%pap(phys)\n", &data->pgtable); + + dev_info(dev, "is probed. Version %d.%d.%d\n", + MMU_MAJ_VER(data->version), + MMU_MIN_VER(data->version), + MMU_REV_VER(data->version)); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int exynos_sysmmu_suspend(struct device *dev) +{ + unsigned long flags; + struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev); + + spin_lock_irqsave(&drvdata->lock, flags); + drvdata->is_suspended = true; + spin_unlock_irqrestore(&drvdata->lock, flags); + + return 0; +} + +static int exynos_sysmmu_resume(struct device *dev) +{ + unsigned long flags; + struct sysmmu_drvdata *drvdata = dev_get_drvdata(dev); + + spin_lock_irqsave(&drvdata->lock, flags); + drvdata->is_suspended = false; + spin_unlock_irqrestore(&drvdata->lock, flags); + + return 0; +} +#endif + +static const struct dev_pm_ops sysmmu_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_sysmmu_suspend, + exynos_sysmmu_resume) +}; + +static const struct of_device_id sysmmu_of_match[] = { + { .compatible = "samsung,pcie-sysmmu", }, + { }, +}; + +static struct platform_driver exynos_sysmmu_driver __refdata = { + .probe = exynos_sysmmu_probe, + .driver = { + .name = "pcie-sysmmu", + .of_match_table = sysmmu_of_match, + .pm = &sysmmu_pm_ops, + } +}; + +static int __init pcie_iommu_init(void) +{ +#ifndef USE_DYNAMIC_MEM_ALLOC /* USE gen_pool */ + u8 *gen_buff; +#endif + phys_addr_t buff_paddr; + int ret; + + if (lv2table_kmem_cache) + return 0; + + lv2table_kmem_cache = kmem_cache_create("pcie-iommu-lv2table", + LV2TABLE_AND_REFBUF_SZ, + LV2TABLE_AND_REFBUF_SZ, + 0, NULL); + if (!lv2table_kmem_cache) { + pr_err("%s: Failed to create kmem cache\n", __func__); + return -ENOMEM; + } + +#ifndef USE_DYNAMIC_MEM_ALLOC /* USE gen_pool */ + gen_buff = kzalloc(LV2_GENPOOL_SZIE, GFP_KERNEL); + if (!gen_buff) + return -ENOMEM; + + buff_paddr = virt_to_phys(gen_buff); + lv2table_pool = gen_pool_create(ilog2(LV2TABLE_AND_REFBUF_SZ), -1); + if (!lv2table_pool) { + pr_err("Failed to allocate lv2table gen pool\n"); + return -ENOMEM; + } + + ret = gen_pool_add(lv2table_pool, (unsigned long)buff_paddr, + LV2_GENPOOL_SZIE, -1); + if (ret) + return -ENOMEM; +#endif + + ret = platform_driver_probe(&exynos_sysmmu_driver, exynos_sysmmu_probe); + if (ret != 0) { + kmem_cache_destroy(lv2table_kmem_cache); +#ifndef USE_DYNAMIC_MEM_ALLOC /* USE gen_pool */ + gen_pool_destroy(lv2table_pool); +#endif + } + + return ret; +} +device_initcall(pcie_iommu_init); + +MODULE_AUTHOR("Kisang Lee "); +MODULE_DESCRIPTION("Exynos PCIe SysMMU driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iommu/exynos-pcie-iommu.h b/drivers/iommu/exynos-pcie-iommu.h new file mode 100644 index 000000000000..851603ed4f05 --- /dev/null +++ b/drivers/iommu/exynos-pcie-iommu.h @@ -0,0 +1,508 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * PCIe Exynos IOMMU driver header file + * + * Copyright (C) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + +#ifndef _EXYNOS_PCIE_IOMMU_H_ +#define _EXYNOS_PCIE_IOMMU_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef u64 sysmmu_iova_t; +typedef u32 sysmmu_pte_t; + +#define IOVM_NUM_PAGES(vmsize) ((vmsize) / PAGE_SIZE) +#define IOVM_BITMAP_SIZE(vmsize) \ + ((IOVM_NUM_PAGES(vmsize) + BITS_PER_BYTE) / BITS_PER_BYTE) + +#define SECT_ORDER 20 +#define LPAGE_ORDER 16 +#define SPAGE_ORDER 12 + +#define SECT_SIZE BIT(SECT_ORDER) +#define LPAGE_SIZE BIT(LPAGE_ORDER) +#define SPAGE_SIZE BIT(SPAGE_ORDER) + +#define SECT_MASK (~(SECT_SIZE - 1)) +#define LPAGE_MASK (~(LPAGE_SIZE - 1)) +#define SPAGE_MASK (~(SPAGE_SIZE - 1)) + +#define SECT_ENT_MASK ~((SECT_SIZE >> PG_ENT_SHIFT) - 1) +#define LPAGE_ENT_MASK ~((LPAGE_SIZE >> PG_ENT_SHIFT) - 1) +#define SPAGE_ENT_MASK ~((SPAGE_SIZE >> PG_ENT_SHIFT) - 1) + +#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) + +#define PGBASE_TO_PHYS(pgent) ((phys_addr_t)(pgent) << PG_ENT_SHIFT) + +/* NUM_LV1ENTRIES = 2^36 / 1MB */ +#define NUM_LV1ENTRIES 65536 +#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) +#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) + +#define lv1ent_offset(iova) ((iova) >> SECT_ORDER) +#define lv2ent_offset(iova) (((iova) & ~SECT_MASK) >> SPAGE_ORDER) + +#define PG_ENT_SHIFT 4 +#define lv1ent_fault(sent) ((*(sent) & 7) == 0) +#define lv1ent_page(sent) ((*(sent) & 7) == 1) + +#define FLPD_FLAG_MASK 7 +#define SLPD_FLAG_MASK 3 + +#define SECT_FLAG 2 +#define SLPD_FLAG 1 + +#define LPAGE_FLAG 1 +#define SPAGE_FLAG 2 + +#define ENT_TO_PHYS(ent) ((phys_addr_t)(*(ent))) +#define section_phys(sent) PGBASE_TO_PHYS(ENT_TO_PHYS(sent) & SECT_ENT_MASK) +#define section_offs(iova) ((iova) & (SECT_SIZE - 1)) +#define lpage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & LPAGE_ENT_MASK) +#define lpage_offs(iova) ((iova) & (LPAGE_SIZE - 1)) +#define spage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & SPAGE_ENT_MASK) +#define spage_offs(iova) ((iova) & (SPAGE_SIZE - 1)) + +#define lv1ent_section(sent) ((*(sent) & FLPD_FLAG_MASK) == SECT_FLAG) +#define lv2table_base(sent) ((phys_addr_t)(*(sent) & ~0x3FU) << PG_ENT_SHIFT) +#define lv2ent_fault(pent) ((*(pent) & SLPD_FLAG_MASK) == 0) +#define lv2ent_small(pent) ((*(pent) & SLPD_FLAG_MASK) == SPAGE_FLAG) +#define lv2ent_large(pent) ((*(pent) & SLPD_FLAG_MASK) == LPAGE_FLAG) + +#define mk_lv1ent_sect(pa) ((sysmmu_pte_t)((pa) >> PG_ENT_SHIFT) | 2) +#define mk_lv1ent_page(pa) ((sysmmu_pte_t)((pa) >> PG_ENT_SHIFT) | 1) +#define mk_lv2ent_lpage(pa) ((sysmmu_pte_t)((pa) >> PG_ENT_SHIFT) | 1) +#define mk_lv2ent_spage(pa) ((sysmmu_pte_t)((pa) >> PG_ENT_SHIFT) | 2) +#define set_lv1ent_shareable(sent) (*(sent) |= (1 << 6)) +#define set_lv2ent_shareable(sent) (*(sent) |= (1 << 4)) +#define mk_lv2ent_pfnmap(pent) (*(pent) |= (1 << 5)) /* unused field */ +#define lv2ent_pfnmap(pent) ((*(pent) & (1 << 5)) == (1 << 5)) + +#define SYSMMU_BLOCK_POLLING_COUNT 4096 + +#define REG_MMU_CTRL 0x000 +#define REG_MMU_CFG 0x004 +#define REG_MMU_STATUS 0x008 +#define REG_MMU_VERSION 0x034 + +#define CTRL_ENABLE 0x5 +#define CTRL_BLOCK 0x7 +#define CTRL_DISABLE 0x0 +#define CTRL_BLOCK_DISABLE 0x3 + +#define CTRL_MMU_ENABLE BIT(0) +#define CTRL_FAULT_STALL_MODE BIT(3) + +#define CFG_MASK 0x301F1F8C /* Bit 29-28, 20-16, 12-7, 3-2 */ +#define CFG_ACGEN BIT(24) +#define CFG_FLPDCACHE BIT(20) +#define CFG_QOS_OVRRIDE BIT(11) +#define CFG_QOS(n) (((n) & 0xF) << 7) + +#define MMU_WAY_CFG_MASK_PREFETCH BIT(1) +#define MMU_WAY_CFG_MASK_PREFETCH_DIR (3 << 2) +#define MMU_WAY_CFG_MASK_MATCH_METHOD BIT(4) +#define MMU_WAY_CFG_MASK_FETCH_SIZE (7 << 5) +#define MMU_WAY_CFG_MASK_TARGET_CH (3 << 8) + +#define MMU_WAY_CFG_ID_MATCHING BIT(4) +#define MMU_WAY_CFG_ADDR_MATCHING (0 << 4) +#define MMU_WAY_CFG_PRIVATE_ENABLE BIT(0) + +#define MMU_PUBLIC_WAY_MASK (MMU_WAY_CFG_MASK_PREFETCH | \ + MMU_WAY_CFG_MASK_PREFETCH_DIR | MMU_WAY_CFG_MASK_FETCH_SIZE) +#define MMU_PRIVATE_WAY_MASK (MMU_PUBLIC_WAY_MASK | \ + MMU_WAY_CFG_MASK_MATCH_METHOD | MMU_WAY_CFG_MASK_TARGET_CH) + +#define REG_MMU_CAPA 0x030 +#define REG_MMU_CAPA_1 0x038 +#define REG_INT_STATUS 0x060 +#define REG_INT_CLEAR 0x064 +#define REG_MMU_CTRL_VID(n) (0x8000 + ((n) * 0x1000)) +#define REG_MMU_CFG_VID(n) (0x8004 + ((n) * 0x1000)) +#define REG_PT_BASE_PPN_VID(n) (0x800C + ((n) * 0x1000)) +#define REG_MMU_FLUSH_VID(n) (0x8010 + ((n) * 0x1000)) +#define REG_MMU_FLUSH_ENTRY_VID(n) (0x8014 + ((n) * 0x1000)) +#define REG_MMU_FLUSH_RANGE_VID(n) (0x8018 + ((n) * 0x1000)) +#define REG_FLUSH_RANGE_START_VID(n) (0x8020 + ((n) * 0x1000)) +#define REG_FLUSH_RANGE_END_VID(n) (0x8024 + ((n) * 0x1000)) + +#define VID_CFG_SHAREABLE BIT(29) +#define VID_CFG_SHAREABLE_OVRD BIT(28) + +#define REG_FAULT_AR_ADDR 0x070 +#define REG_FAULT_AR_TRANS_INFO 0x078 +#define REG_FAULT_AW_ADDR 0x080 +#define REG_FAULT_AW_TRANS_INFO 0x088 + +#define REG_L2TLB_CFG 0x200 + +/* For SysMMU v7.x */ +#define REG_MMU_CAPA_V7 0x870 +#define REG_PUBLIC_WAY_CFG 0x120 +#define REG_PRIVATE_WAY_CFG(n) (0x200 + ((n) * 0x10)) +#define REG_PRIVATE_ADDR_START(n) (0x204 + ((n) * 0x10)) +#define REG_PRIVATE_ADDR_END(n) (0x208 + ((n) * 0x10)) +#define REG_PRIVATE_ID(n) (0x20C + ((n) * 0x10)) +#define REG_FAULT_ADDR_VA 0x1010 +#define REG_FAULT_INFO0 0x1014 +#define REG_FAULT_INFO1 0x1018 +/* + * #define REG_TLB_READ 0x1000 + * #define REG_TLB_VPN 0x1004 + * #define REG_TLB_PPN 0x1008 + * #define REG_TLB_ATTR 0x100C + * #define REG_SBB_READ 0x1100 + * #define REG_SBB_VPN 0x1104 + * #define REG_SBB_LINK 0x1108 + * #define REG_SBB_ATTR 0x110C + */ + +#define MMU_CAPA_NUM_SBB_ENTRY(reg) (((reg) >> 12) & 0xF) +#define MMU_CAPA_NUM_TLB_SET(reg) (((reg) >> 8) & 0xF) +#define MMU_CAPA_NUM_TLB_WAY(reg) ((reg) & 0xFF) +#define MMU_SET_TLB_READ_ENTRY(set, way, line) \ + ((set) | ((way) << 8) | ((line) << 16)) +#define MMU_TLB_ENTRY_VALID(reg) ((reg) >> 28) +#define MMU_SBB_ENTRY_VALID(reg) ((reg) >> 28) + +#define MMU_FAULT_INFO_READ_REQUEST 0 +#define MMU_FAULT_INFO_WRITE_REQUEST 1 +#define MMU_IS_READ_FAULT(reg) \ + ((((reg) >> 20) & 0x1) == MMU_FAULT_INFO_READ_REQUEST) + +#define MMU_HAVE_PB(reg) (!!(((reg) >> 20) & 0xF)) +#define MMU_IS_TLB_CONFIGURABLE(reg) (!!(((reg) >> 16) & 0xFF)) + +#define MMU_MASK_LINE_SIZE 0x7 +#define MMU_DEFAULT_LINE_SIZE (0x2 << 4) + +#define MMU_MAJ_VER(val) ((val) >> 11) +#define MMU_MIN_VER(val) (((val) >> 4) & 0x7F) +#define MMU_REV_VER(val) ((val) & 0xF) +#define MMU_RAW_VER(reg) (((reg) >> 17) & 0x7FFF) /* upper 15 bits */ + +#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 11) | \ + (((min) & 0x7F) << 4)) + +#define DEFAULT_QOS_VALUE -1 + +#define SYSMMU_FAULT_BITS 4 +#define SYSMMU_FAULT_SHIFT 16 +#define SYSMMU_FAULT_MASK ((1 << SYSMMU_FAULT_BITS) - 1) +#define SYSMMU_FAULT_FLAG(id) (((id) & SYSMMU_FAULT_MASK) << SYSMMU_FAULT_SHIFT) +#define SYSMMU_FAULT_ID(fg) (((fg) >> SYSMMU_FAULT_SHIFT) & SYSMMU_FAULT_MASK) + +#define SYSMMU_FAULT_PTW_ACCESS 0 +#define SYSMMU_FAULT_PAGE_FAULT 1 +#define SYSMMU_FAULT_TLB_MULTIHIT 2 +#define SYSMMU_FAULT_ACCESS 3 +#define SYSMMU_FAULT_SECURITY 4 +#define SYSMMU_FAULT_UNKNOWN 5 + +#define SYSMMU_4KB_MASK 0xfffUL + +#define SYSMMU_FAULTS_NUM (SYSMMU_FAULT_UNKNOWN + 1) + +#define DUPLMEM_ENTRY_NUM 4096 + +/* For SysMMU v7.1 */ +#define REG_MMU_CAPA0_V7 0x870 +#define REG_MMU_CAPA1_V7 0x874 +#define MMU_CAPA1_NUM_TLB(reg) (((reg) >> 4) & 0xFF) +#define MMU_CAPA1_NUM_PORT(reg) ((reg) & 0xF) +#define MMU_TLB_INFO(n) (0x2000 + ((n) * 0x20)) +#define MMU_CAPA1_NUM_TLB_SET(reg) (((reg) >> 16) & 0xFF) +#define MMU_CAPA1_NUM_TLB_WAY(reg) ((reg) & 0xFF) +#define REG_MMU_TLB_CFG(n) (0x2000 + ((n) * 0x20) + 0x4) +#define REG_MMU_TLB_MATCH_CFG(n) (0x2000 + ((n) * 0x20) + 0x8) +#define REG_MMU_TLB_MATCH_SVA(n) (0x2000 + ((n) * 0x20) + 0xC) +#define REG_MMU_TLB_MATCH_EVA(n) (0x2000 + ((n) * 0x20) + 0x10) +#define REG_MMU_TLB_MATCH_ID(n) (0x2000 + ((n) * 0x20) + 0x14) +#define REG_CAPA1_TLB_READ 0x3000 +#define REG_CAPA1_TLB_VPN 0x3004 +#define REG_CAPA1_TLB_PPN 0x3008 +#define REG_CAPA1_TLB_ATTR 0x300C +#define REG_CAPA1_SBB_READ 0x3020 +#define REG_CAPA1_SBB_VPN 0x3024 +#define REG_CAPA1_SBB_LINK 0x3028 +#define REG_CAPA1_SBB_ATTR 0x302C +#define REG_SLOT_RSV(n) (0x4000 + ((n) * 0x20)) +#define MMU_CAPA1_SET_TLB_READ_ENTRY(tid, set, way, line) \ + ((set) | ((way) << 8) | ((line) << 16) | ((tid) << 20)) +#define MMU_TLB_CFG_MASK(reg) ((reg) & ((0x7 << 5) | (0x3 << 2) | (0x1 << 1))) +#define MMU_TLB_MATCH_CFG_MASK(reg) ((reg) & ((0xFFFF << 16) | (0x3 << 8))) + +#define TLB_USED_ALL_PCIE_PORT (0x3 << 16) +#define TLB_USED_RW_REQ (0x3 << 8) + +#define MAX_EXT_BUFF_NUM (400) +#define LV2_GENPOOL_SZIE (SZ_1M * 3) +/* Level2 table size + reference counter region */ +#define LV2TABLE_AND_REFBUF_SZ (LV2TABLE_SIZE * 2) +#define NUM_DRAM_REGION (10) +#define SYSMMU_NO_PANIC (1) + +#define SYSMMU_PCIE_CH0 (0) +#define SYSMMU_PCIE_CH1 (1) + +struct ext_buff { + int index; + int used; + sysmmu_pte_t *buff; +}; + +struct dram_region { + phys_addr_t start; + phys_addr_t end; +}; + +#if IS_ENABLED(CONFIG_PCIE_IOMMU_HISTORY_LOG) +#define MAX_HISTORY_BUFF (2048) + +struct history_buff { + u32 index; + u32 save_addr[MAX_HISTORY_BUFF]; + u32 orig_addr[MAX_HISTORY_BUFF]; + u32 size[MAX_HISTORY_BUFF]; + u32 orig_size[MAX_HISTORY_BUFF]; +}; +#endif + +/* + * This structure exynos specific generalization of struct iommu_domain. + * It contains list of all master devices represented by owner, which has + * been attached to this domain and page tables of IO address space defined by + * it. It is usually referenced by 'domain' pointer. + */ +struct exynos_iommu_domain { + struct iommu_domain domain; /* generic domain data structure */ + sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */ + spinlock_t pgtablelock; /* lock for modifying page table */ + struct list_head clients_list; /* list of exynos_iommu_owner.client */ + atomic_t *lv2entcnt; /* free lv2 entry counter for each section */ + spinlock_t lock; /* lock for modifying clients_list */ + unsigned long pgsize_bitmap; +#ifdef USE_DYNAMIC_MEM_ALLOC + struct ext_buff ext_buff[MAX_EXT_BUFF_NUM]; +#endif +}; + +/* + * This structure is attached to dev.archdata.iommu of the master device + * on device add, contains a list of SYSMMU controllers defined by device tree, + * which are bound to given master device. It is usually referenced by 'owner' + * pointer. + */ +struct exynos_iommu_owner { + struct exynos_iommu_owner *next; + struct list_head sysmmu_list; /* list of sysmmu_drvdata */ + spinlock_t lock; /* lock for modifying sysmmu_list */ + struct iommu_domain *domain; /* domain of owner */ + struct device *master; /* master device */ + struct list_head client; /* node for owner clients_list */ + struct exynos_iovmm *vmm_data; + iommu_fault_handler_t fault_handler; + void *token; +}; + +struct tlb_priv_addr { + unsigned int cfg; +}; + +struct tlb_priv_id { + unsigned int cfg; + unsigned int id; +}; + +#define TLB_WAY_PRIVATE_ID BIT(0) +#define TLB_WAY_PRIVATE_ADDR BIT(1) +#define TLB_WAY_PUBLIC BIT(2) +struct tlb_props { + int flags; + int priv_id_cnt; + int priv_addr_cnt; + unsigned int public_cfg; + struct tlb_priv_id *priv_id_cfg; + struct tlb_priv_addr *priv_addr_cfg; +}; + +/* + * This structure hold all data of a single SYSMMU controller, this includes + * hw resources like registers and clocks, pointers and list nodes to connect + * it to all other structures, internal state and parameters read from device + * tree. It is usually referenced by 'data' pointer. + */ +struct sysmmu_drvdata { + struct sysmmu_drvdata *next; + struct device *sysmmu; /* SYSMMU controller device */ + void __iomem *sfrbase; /* our registers */ + struct clk *clk; /* SYSMMU's clock */ + u32 activations; /* SysMMU activation for each VID */ + int runtime_active; /* Runtime PM activated count from master */ + spinlock_t lock; /* lock for modyfying state */ + phys_addr_t pgtable; /* assigned page table structure */ + int version; /* our version */ + int qos; + int securebase; + struct atomic_notifier_head fault_notifiers; + struct tlb_props tlb_props; + bool is_suspended; + bool use_map_once; + + struct exynos_iommu_domain *domain; /* iommu domain for this iovmm */ + int use_tlb_pinning; + int pcie_use_iocc; + int ignore_tlb_inval; + + spinlock_t mmu_ctrl_lock; /* Global Register Control lock */ + int hsi_block_num; + int pcie_vid; /* PCIe VID number */ +}; + +struct exynos_vm_region { + struct list_head node; + u32 start; + u32 size; + u32 section_off; + u32 dummy_size; +}; + +struct exynos_iovmm { + struct iommu_domain *domain; /* iommu domain for this iovmm */ + size_t iovm_size; /* iovm bitmap size per plane */ + u32 iova_start; /* iovm start address per plane */ + unsigned long *vm_map; /* iovm biatmap per plane */ + struct list_head regions_list; /* list of exynos_vm_region */ + spinlock_t vmlist_lock; /* lock for updating regions_list */ + spinlock_t bitmap_lock; /* lock for manipulating bitmaps */ + struct device *dev; /* peripheral device that has this iovmm */ + size_t allocated_size; + int num_areas; + unsigned int num_map; + unsigned int num_unmap; + const char *domain_name; + struct iommu_group *group; +}; + +static void exynos_sysmmu_tlb_invalidate(dma_addr_t d_start, size_t size, + int pcie_vid, int hsi_block_num); +int exynos_iommu_add_fault_handler(struct device *dev, + iommu_fault_handler_t handler, void *token); + +static inline bool set_sysmmu_active(struct sysmmu_drvdata *data, int pcie_vid) +{ + /* return true if the System MMU was not active previously + * and it needs to be initialized + */ + + data->activations |= (0x1 << pcie_vid); + + return 1; +} + +static inline bool set_sysmmu_inactive(struct sysmmu_drvdata *data, int pcie_vid) +{ + /* return true if the System MMU is needed to be disabled */ + data->activations &= ~(0x1 << pcie_vid); + + return 0; +} + +static inline bool is_sysmmu_active(struct sysmmu_drvdata *data) +{ + return data->activations > 0; +} + +static inline void __raw_sysmmu_enable(void __iomem *sfrbase) +{ + __raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL); +} + +#define sysmmu_unblock __raw_sysmmu_enable + +void dump_sysmmu_tlb_pb(void __iomem *sfrbase); + +static inline bool sysmmu_block(void __iomem *sfrbase) +{ + int i = SYSMMU_BLOCK_POLLING_COUNT; + + __raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL); + while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) + --i; + + if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) { + /* + * TODO: dump_sysmmu_tlb_pb(sfrbase); + */ + panic("Failed to block System MMU!"); + sysmmu_unblock(sfrbase); + return false; + } + + return true; +} + +static inline sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova) +{ + return (sysmmu_pte_t *)(phys_to_virt(lv2table_base(sent))) + + lv2ent_offset(iova); +} + +static inline sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, + sysmmu_iova_t iova) +{ + return (sysmmu_pte_t *)(pgtable + lv1ent_offset(iova)); +} + +#if IS_ENABLED(CONFIG_EXYNOS_IOVMM) +static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev) +{ + if (!dev->archdata.iommu) { + dev_err(dev, "%s: System MMU is not configured\n", __func__); + return NULL; + } + + return ((struct exynos_iommu_owner *)dev->archdata.iommu)->vmm_data; +} + +struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm, + dma_addr_t iova); + +struct exynos_iovmm *exynos_create_single_iovmm(const char *name, + unsigned int start, + unsigned int end); +#else +static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev) +{ + return NULL; +} + +struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm, + dma_addr_t iova) +{ + return NULL; +} + +static inline struct exynos_iovmm *exynos_create_single_iovmm(const char *name, + unsigned int start, + unsigned int end) +{ + return NULL; +} +#endif /* CONFIG_EXYNOS_IOVMM */ + +#endif /* _EXYNOS_PCIE_IOMMU_H_ */ diff --git a/drivers/iommu/samsung-iommu.c b/drivers/iommu/samsung-iommu.c index 628d05074e8d..06897e37bdc2 100644 --- a/drivers/iommu/samsung-iommu.c +++ b/drivers/iommu/samsung-iommu.c @@ -14,6 +14,8 @@ #include #include +#include + #include "samsung-iommu.h" #define FLPD_SHAREABLE_FLAG BIT(6) @@ -73,8 +75,6 @@ static struct platform_driver samsung_sysmmu_driver; struct samsung_sysmmu_domain { struct iommu_domain domain; struct iommu_group *group; - struct sysmmu_drvdata *vm_sysmmu; /* valid only if vid != 0 */ - /* if vid != 0, domain is aux domain attached to only one device and sysmmu */ unsigned int vid; sysmmu_pte_t *page_table; atomic_t *lv2entcnt; @@ -324,11 +324,11 @@ static inline void samsung_sysmmu_detach_drvdata(struct sysmmu_drvdata *data) unsigned long flags; spin_lock_irqsave(&data->lock, flags); - if (--data->attached_count == 0) { + if (--data->attached_count[0] == 0) { if (pm_runtime_active(data->dev)) __sysmmu_disable(data); - list_del(&data->list); + list_del(&data->list[0]); data->pgtable[0] = 0; data->group = NULL; } @@ -405,7 +405,7 @@ static struct samsung_sysmmu_domain *attach_helper(struct iommu_domain *dom, str } domain = to_sysmmu_domain(dom); - if (domain->vm_sysmmu) { + if (domain->vid) { dev_err(dev, "IOMMU domain is already used as AUX domain\n"); return ERR_PTR(-EBUSY); } @@ -418,7 +418,7 @@ static int samsung_sysmmu_attach_dev(struct iommu_domain *dom, { struct sysmmu_clientdata *client; struct samsung_sysmmu_domain *domain; - struct list_head *group_list; + struct sysmmu_groupdata *groupdata; struct sysmmu_drvdata *drvdata; struct iommu_group *group = dev->iommu_group; unsigned long flags; @@ -430,16 +430,18 @@ static int samsung_sysmmu_attach_dev(struct iommu_domain *dom, return (int)PTR_ERR(domain); domain->group = group; - group_list = iommu_group_get_iommudata(group); + groupdata = iommu_group_get_iommudata(group); page_table = virt_to_phys(domain->page_table); + spin_lock_irqsave(&groupdata->sysmmu_list_lock[0], flags); client = dev_iommu_priv_get(dev); for (i = 0; i < (int)client->sysmmu_count; i++) { drvdata = client->sysmmus[i]; - spin_lock_irqsave(&drvdata->lock, flags); - if (drvdata->attached_count++ == 0) { - list_add(&drvdata->list, group_list); + spin_lock(&drvdata->lock); + if (drvdata->attached_count[0]++ == 0) { + list_add(&drvdata->list[0], &groupdata->sysmmu_list[0]); + groupdata->has_vcr &= drvdata->has_vcr; drvdata->group = group; drvdata->pgtable[0] = page_table; @@ -448,11 +450,13 @@ static int samsung_sysmmu_attach_dev(struct iommu_domain *dom, } else if (drvdata->pgtable[0] != page_table) { dev_err(dev, "%s is already attached to other domain\n", dev_name(drvdata->dev)); - spin_unlock_irqrestore(&drvdata->lock, flags); + spin_unlock(&drvdata->lock); + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[0], flags); goto err_drvdata_add; } - spin_unlock_irqrestore(&drvdata->lock, flags); + spin_unlock(&drvdata->lock); } + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[0], flags); ret = samsung_sysmmu_set_domain_range(dom, dev); if (ret) @@ -476,22 +480,27 @@ static void samsung_sysmmu_detach_dev(struct iommu_domain *dom, struct device *dev) { struct sysmmu_clientdata *client; - struct samsung_sysmmu_domain *domain; - struct list_head *group_list; + struct samsung_sysmmu_domain *domain = to_sysmmu_domain(dom); + struct iommu_group *group = domain->group; + struct sysmmu_groupdata *groupdata; struct sysmmu_drvdata *drvdata; - struct iommu_group *group = dev->iommu_group; + unsigned long flags; phys_addr_t page_table; unsigned int i; - domain = to_sysmmu_domain(dom); - group_list = iommu_group_get_iommudata(group); + if (WARN_ON(!group)) + return; + groupdata = iommu_group_get_iommudata(group); + domain = to_sysmmu_domain(dom); client = dev_iommu_priv_get(dev); + spin_lock_irqsave(&groupdata->sysmmu_list_lock[0], flags); for (i = 0; i < client->sysmmu_count; i++) { drvdata = client->sysmmus[i]; samsung_sysmmu_detach_drvdata(drvdata); } + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[0], flags); page_table = virt_to_phys(domain->page_table); dev_info(dev, "detached from pgtable %pap\n", &page_table); @@ -803,29 +812,21 @@ static void samsung_sysmmu_flush_iotlb_all(struct iommu_domain *dom) unsigned long flags; struct samsung_sysmmu_domain *domain = to_sysmmu_domain(dom); struct sysmmu_drvdata *drvdata; + struct iommu_group *group = domain->group; + struct sysmmu_groupdata *groupdata; - if (domain->vm_sysmmu) { - /* Domain is used as AUX domain */ - drvdata = domain->vm_sysmmu; - spin_lock_irqsave(&drvdata->lock, flags); - if (drvdata->attached_count && drvdata->rpm_resume) + if (!group) + return; + smp_rmb(); /* Ensure domain->group is read before domain->vid */ + groupdata = iommu_group_get_iommudata(group); + spin_lock_irqsave(&groupdata->sysmmu_list_lock[domain->vid], flags); + list_for_each_entry(drvdata, &groupdata->sysmmu_list[domain->vid], list[domain->vid]) { + spin_lock(&drvdata->lock); + if (drvdata->attached_count[0] && drvdata->rpm_resume) __sysmmu_tlb_invalidate_all(drvdata, domain->vid); - spin_unlock_irqrestore(&drvdata->lock, flags); - } else if (domain->group) { - /* Domain is used as regular domain */ - /* - * domain->group might be NULL if flush_iotlb_all is called - * before attach_dev. Just ignore it. - */ - struct list_head *sysmmu_list = iommu_group_get_iommudata(domain->group); - - list_for_each_entry(drvdata, sysmmu_list, list) { - spin_lock_irqsave(&drvdata->lock, flags); - if (drvdata->attached_count && drvdata->rpm_resume) - __sysmmu_tlb_invalidate_all(drvdata, 0); - spin_unlock_irqrestore(&drvdata->lock, flags); - } + spin_unlock(&drvdata->lock); } + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[domain->vid], flags); } static void samsung_sysmmu_iotlb_sync_map(struct iommu_domain *dom, @@ -862,29 +863,21 @@ static void samsung_sysmmu_iotlb_sync(struct iommu_domain *dom, unsigned long flags; struct samsung_sysmmu_domain *domain = to_sysmmu_domain(dom); struct sysmmu_drvdata *drvdata; + struct iommu_group *group = domain->group; + struct sysmmu_groupdata *groupdata; - if (domain->vm_sysmmu) { - /* Domain is used as AUX domain */ - drvdata = domain->vm_sysmmu; - spin_lock_irqsave(&drvdata->lock, flags); - if (drvdata->attached_count && drvdata->rpm_resume) + if (!group) + return; + smp_rmb(); /* Ensure domain->group is read before domain->vid */ + groupdata = iommu_group_get_iommudata(group); + spin_lock_irqsave(&groupdata->sysmmu_list_lock[domain->vid], flags); + list_for_each_entry(drvdata, &groupdata->sysmmu_list[domain->vid], list[domain->vid]) { + spin_lock(&drvdata->lock); + if (drvdata->attached_count[0] && drvdata->rpm_resume) __sysmmu_tlb_invalidate(drvdata, domain->vid, gather->start, gather->end); - spin_unlock_irqrestore(&drvdata->lock, flags); - } else if (domain->group) { - /* Domain is used as regular domain */ - /* - * domain->group might be NULL if iotlb_sync is called - * before attach_dev. Just ignore it. - */ - struct list_head *sysmmu_list = iommu_group_get_iommudata(domain->group); - - list_for_each_entry(drvdata, sysmmu_list, list) { - spin_lock_irqsave(&drvdata->lock, flags); - if (drvdata->attached_count && drvdata->rpm_resume) - __sysmmu_tlb_invalidate(drvdata, 0, gather->start, gather->end); - spin_unlock_irqrestore(&drvdata->lock, flags); - } + spin_unlock(&drvdata->lock); } + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[domain->vid], flags); } static phys_addr_t samsung_sysmmu_iova_to_phys(struct iommu_domain *dom, @@ -979,7 +972,8 @@ static struct iommu_group *samsung_sysmmu_device_group(struct device *dev) struct iommu_group *group; struct device_node *np; struct platform_device *pdev; - struct list_head *list; + struct sysmmu_groupdata *groupdata; + unsigned int i; bool need_unmanaged_domain = false; if (device_iommu_mapped(dev)) @@ -1012,12 +1006,19 @@ static struct iommu_group *samsung_sysmmu_device_group(struct device *dev) if (iommu_group_get_iommudata(group)) return group; - list = kzalloc(sizeof(*list), GFP_KERNEL); - if (!list) + groupdata = kzalloc(sizeof(*groupdata), GFP_KERNEL); + if (!groupdata) return ERR_PTR(-ENOMEM); - INIT_LIST_HEAD(list); - iommu_group_set_iommudata(group, list, + for (i = 0; i < MAX_VIDS; i++) { + INIT_LIST_HEAD(&groupdata->sysmmu_list[i]); + spin_lock_init(&groupdata->sysmmu_list_lock[i]); + } + + groupdata->vid_map = BIT(0); /* Block vid 0 which is not available for AUX domains. */ + /* has_vcr will be set to false if any SysMMU with no vcr support is added to this group. */ + groupdata->has_vcr = true; + iommu_group_set_iommudata(group, groupdata, samsung_sysmmu_group_data_release); if (need_unmanaged_domain) { @@ -1090,74 +1091,138 @@ static int samsung_sysmmu_aux_attach_dev(struct iommu_domain *dom, struct device { struct sysmmu_clientdata *client; struct samsung_sysmmu_domain *domain; + struct iommu_group *group; + struct sysmmu_groupdata *groupdata; struct sysmmu_drvdata *drvdata; + phys_addr_t page_table; unsigned long flags; + unsigned long vid_map; + unsigned long map; unsigned int vid; + int i; + int ret = 0; domain = attach_helper(dom, dev); if (IS_ERR(domain)) return (int)PTR_ERR(domain); if (domain->group) { - dev_err(dev, "IOMMU domain is already in use as vid 0 domain\n"); + dev_err(dev, "IOMMU domain is already in use\n"); return -EBUSY; } - client = (struct sysmmu_clientdata *) dev_iommu_priv_get(dev); - if (client->sysmmu_count != 1) { - dev_err(dev, "IOMMU AUX domains not supported for devices served by more than one IOMMU\n"); - return -ENXIO; + group = iommu_group_get(dev); + groupdata = iommu_group_get_iommudata(group); + + if (!groupdata->has_vcr) { + dev_err(dev, "SysMMU group does not support IOMMU AUX domains\n"); + ret = -ENODEV; + goto group_put; } - drvdata = client->sysmmus[0]; - if (!drvdata->has_vcr) { - dev_err(dev, "SysMMU does not support IOMMU AUX domains\n"); - return -ENXIO; + + client = (struct sysmmu_clientdata *)dev_iommu_priv_get(dev); + + for (i = 0; i < (int)client->sysmmu_count; i++) { + drvdata = client->sysmmus[i]; + if (!drvdata->attached_count[0]) { + dev_err(dev, "SysMMU %s needs to be enabled to attach AUX domain\n", + dev_name(drvdata->dev)); + ret = -ENODEV; + goto group_put; + } } - spin_lock_irqsave(&drvdata->lock, flags); - if (!drvdata->attached_count) { - dev_err(dev, "IOMMU needs to be enabled to attach AUX domain\n"); - spin_unlock_irqrestore(&drvdata->lock, flags); - return -ENXIO; + + /* Allocate VID */ + vid_map = groupdata->vid_map; + do { + map = vid_map; + vid = ffz(map); + if (vid >= MAX_VIDS) { + dev_err(dev, "Unable to allocate vid for AUX domain\n"); + ret = -EBUSY; + goto group_put; + } + cpu_relax(); + } while ((vid_map = cmpxchg(&groupdata->vid_map, map, map | BIT(vid))) != map); + if (WARN_ON(vid == 0)) { + ret = -EINVAL; + goto group_put; } - for (vid = 1; vid < MAX_VIDS; vid++) - if (!drvdata->pgtable[vid]) - break; - if (vid == MAX_VIDS) { - dev_err(dev, "Unable to allocate vid for AUX domain\n"); - spin_unlock_irqrestore(&drvdata->lock, flags); - return -EBUSY; + + page_table = virt_to_phys(domain->page_table); + spin_lock_irqsave(&groupdata->sysmmu_list_lock[vid], flags); + for (i = 0; i < (int)client->sysmmu_count; i++) { + drvdata = client->sysmmus[i]; + spin_lock(&drvdata->lock); + if (drvdata->attached_count[vid]++ == 0) { + list_add(&drvdata->list[vid], &groupdata->sysmmu_list[vid]); + drvdata->pgtable[vid] = page_table; + + if (pm_runtime_active(drvdata->dev)) + __sysmmu_enable_vid(drvdata, vid); + } else if (drvdata->pgtable[vid] != page_table) { + dev_err(dev, "%s vid %u is already attached to other domain\n", + dev_name(drvdata->dev), vid); + } + spin_unlock(&drvdata->lock); } - drvdata->pgtable[vid] = virt_to_phys(domain->page_table); - if (pm_runtime_active(drvdata->dev)) - __sysmmu_enable_vid(drvdata, vid); - spin_unlock_irqrestore(&drvdata->lock, flags); - domain->vm_sysmmu = drvdata; + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[vid], flags); + domain->vid = vid; - return 0; + smp_wmb(); /* Ensure domain->vid is visible before domain->group */ + domain->group = group; + +group_put: + iommu_group_put(group); + return ret; } static void samsung_sysmmu_aux_detach_dev(struct iommu_domain *dom, struct device *dev) { + struct sysmmu_clientdata *client; struct samsung_sysmmu_domain *domain; + struct iommu_group *group; + struct sysmmu_groupdata *groupdata; struct sysmmu_drvdata *drvdata; unsigned long flags; + unsigned long vid_map; + unsigned long map; unsigned int vid; + unsigned int i; domain = to_sysmmu_domain(dom); - - if (WARN_ON(!domain->vm_sysmmu || !domain->vid)) + client = (struct sysmmu_clientdata *)dev_iommu_priv_get(dev); + if (WARN_ON(!domain->vid)) return; - - drvdata = domain->vm_sysmmu; vid = domain->vid; + group = iommu_group_get(dev); + groupdata = iommu_group_get_iommudata(group); - spin_lock_irqsave(&drvdata->lock, flags); - drvdata->pgtable[vid] = 0; - if (pm_runtime_active(drvdata->dev)) - __sysmmu_disable_vid(drvdata, vid); - spin_unlock_irqrestore(&drvdata->lock, flags); - - domain->vm_sysmmu = NULL; + spin_lock_irqsave(&groupdata->sysmmu_list_lock[vid], flags); + for (i = 0; i < client->sysmmu_count; i++) { + drvdata = client->sysmmus[i]; + if (!drvdata->has_vcr) + continue; + spin_lock(&drvdata->lock); + if (--drvdata->attached_count[vid] == 0) { + list_del(&drvdata->list[vid]); + drvdata->pgtable[vid] = 0; + if (pm_runtime_active(drvdata->dev)) + __sysmmu_disable_vid(drvdata, vid); + } + spin_unlock(&drvdata->lock); + } + spin_unlock_irqrestore(&groupdata->sysmmu_list_lock[vid], flags); + + /* De-allocate VID */ + vid_map = groupdata->vid_map; + do { + map = vid_map; + cpu_relax(); + } while ((vid_map = cmpxchg(&groupdata->vid_map, map, map & ~BIT(vid))) != map); + domain->group = NULL; + smp_wmb(); /* Ensure domain->group is visible before domain->vid */ domain->vid = 0; + iommu_group_put(group); } static int samsung_sysmmu_aux_get_pasid(struct iommu_domain *dom, struct device *dev) @@ -1166,9 +1231,6 @@ static int samsung_sysmmu_aux_get_pasid(struct iommu_domain *dom, struct device domain = to_sysmmu_domain(dom); - if (!domain->vm_sysmmu) - return -EINVAL; - return (int)domain->vid; } @@ -1177,6 +1239,7 @@ static bool samsung_sysmmu_dev_has_feat(struct device *dev, enum iommu_dev_featu struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); struct sysmmu_clientdata *client; struct sysmmu_drvdata *drvdata; + unsigned int i; if (f != IOMMU_DEV_FEAT_AUX) return false; @@ -1184,11 +1247,14 @@ static bool samsung_sysmmu_dev_has_feat(struct device *dev, enum iommu_dev_featu client = (struct sysmmu_clientdata *) dev_iommu_priv_get(dev); if (!fwspec || !client || fwspec->ops != &samsung_sysmmu_ops) return false; - - if (client->sysmmu_count != 1) + if (client->sysmmu_count == 0) return false; - drvdata = client->sysmmus[0]; - return !!drvdata->has_vcr; + for (i = 0; i < client->sysmmu_count; i++) { + drvdata = client->sysmmus[i]; + if (!drvdata->has_vcr) + return false; + } + return true; } static bool samsung_sysmmu_dev_feat_enabled(struct device *dev, enum iommu_dev_features f) @@ -1461,6 +1527,15 @@ static int samsung_sysmmu_device_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *res; int irq, ret, err = 0; + unsigned int i; + + if (IS_ENABLED(CONFIG_PKVM_S2MPU)) { + ret = pkvm_s2mpu_of_link(dev); + if (ret == -EAGAIN) + return -EPROBE_DEFER; + else if (ret) + return ret; + } data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -1502,7 +1577,8 @@ static int samsung_sysmmu_device_probe(struct platform_device *pdev) return ret; } - INIT_LIST_HEAD(&data->list); + for (i = 0; i < MAX_VIDS; i++) + INIT_LIST_HEAD(&data->list[i]); spin_lock_init(&data->lock); data->dev = dev; @@ -1562,7 +1638,7 @@ static int __maybe_unused samsung_sysmmu_runtime_suspend(struct device *sysmmu) spin_lock_irqsave(&drvdata->lock, flags); drvdata->rpm_resume = false; - if (drvdata->attached_count > 0) + if (drvdata->attached_count[0] > 0) __sysmmu_disable(drvdata); spin_unlock_irqrestore(&drvdata->lock, flags); @@ -1576,7 +1652,7 @@ static int __maybe_unused samsung_sysmmu_runtime_resume(struct device *sysmmu) spin_lock_irqsave(&drvdata->lock, flags); drvdata->rpm_resume = true; - if (drvdata->attached_count > 0) + if (drvdata->attached_count[0] > 0) __sysmmu_enable(drvdata); spin_unlock_irqrestore(&drvdata->lock, flags); diff --git a/drivers/iommu/samsung-iommu.h b/drivers/iommu/samsung-iommu.h index c6162740b296..de3e54ab482a 100644 --- a/drivers/iommu/samsung-iommu.h +++ b/drivers/iommu/samsung-iommu.h @@ -29,7 +29,7 @@ struct tlb_props { }; struct sysmmu_drvdata { - struct list_head list; + struct list_head list[MAX_VIDS]; struct iommu_device iommu; struct device *dev; struct iommu_group *group; @@ -40,7 +40,7 @@ struct sysmmu_drvdata { u32 version; unsigned int num_tlb; int qos; - int attached_count; + int attached_count[MAX_VIDS]; int secure_irq; unsigned int secure_base; const unsigned int *reg_set; @@ -59,6 +59,13 @@ struct sysmmu_clientdata { unsigned int sysmmu_count; }; +struct sysmmu_groupdata { + struct list_head sysmmu_list[MAX_VIDS]; + spinlock_t sysmmu_list_lock[MAX_VIDS]; /* Protects .sysmmu_list */ + unsigned long vid_map; + bool has_vcr; +}; + enum { REG_IDX_DEFAULT = 0, @@ -128,7 +135,7 @@ typedef u32 sysmmu_pte_t; #define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE) -#define NUM_LV1ENTRIES 4096 +#define NUM_LV1ENTRIES 65536 #define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE) #define LV1TABLE_SIZE (NUM_LV1ENTRIES * sizeof(sysmmu_pte_t)) #define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t)) diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 416d8dcaa6c3..1557e2923a76 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -596,5 +596,3 @@ config VIDEO_RCAR_DRIF will be called rcar_drif. endif # SDR_PLATFORM_DRIVERS - -source "drivers/media/platform/bigocean/Kconfig" diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index e7d5d7e09414..b98909e5928d 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -83,6 +83,4 @@ obj-y += sunxi/ obj-$(CONFIG_VIDEO_EXYNOS) += exynos/ -obj-$(CONFIG_BIGOCEAN) += bigocean/ - obj-$(CONFIG_VIDEO_EXYNOS_SMFC) += exynos/smfc/ diff --git a/drivers/media/platform/bigocean/Kconfig b/drivers/media/platform/bigocean/Kconfig deleted file mode 100644 index a1bf3c72927f..000000000000 --- a/drivers/media/platform/bigocean/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Big Ocean configuration -# - -comment "BigOcean video codec" - -config BIGOCEAN - tristate "BigOcean video codec" - depends on EXYNOS_BTS - default n - select PM - help - Driver for BigOcean video codec diff --git a/drivers/media/platform/bigocean/Makefile b/drivers/media/platform/bigocean/Makefile deleted file mode 100644 index cbac244dbd83..000000000000 --- a/drivers/media/platform/bigocean/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -obj-$(CONFIG_BIGOCEAN) += bigocean.o -bigocean-$(CONFIG_BIGOCEAN) += bigo.o bigo_pm.o bigo_io.o bigo_of.o bigo_iommu.o bigo_prioq.o -bigocean-$(CONFIG_SLC_PARTITION_MANAGER) += bigo_slc.o -bigocean-$(CONFIG_DEBUG_FS) += bigo_debug.o diff --git a/drivers/media/platform/bigocean/bigo.c b/drivers/media/platform/bigocean/bigo.c deleted file mode 100644 index 2b75d3e37c39..000000000000 --- a/drivers/media/platform/bigocean/bigo.c +++ /dev/null @@ -1,754 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for BigOcean video accelerator - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "bigo_io.h" -#include "bigo_iommu.h" -#include "bigo_of.h" -#include "bigo_pm.h" -#include "bigo_priv.h" -#include "bigo_slc.h" -#include "bigo_debug.h" -#include "bigo_prioq.h" - -#define BIGO_DEVCLASS_NAME "video_codec" -#define BIGO_CHRDEV_NAME "bigocean" - -#define DEFAULT_WIDTH 3840 -#define DEFAULT_HEIGHT 2160 -#define DEFAULT_FPS 60 -#define BIGO_SMC_ID 0xd -#define BIGO_MAX_INST_NUM 16 - -#define BIGO_IDLE_TIMEOUT_MS 1000 - -static int bigo_worker_thread(void *data); - -static struct sscd_platform_data bigo_sscd_platdata; - -static void bigo_sscd_release(struct device *dev) -{ - pr_debug("sscd release\n"); -} - -static struct platform_device bigo_sscd_dev = { - .name = BIGO_CHRDEV_NAME, - .driver_override = SSCD_NAME, - .id = -1, - .dev = { - .platform_data = &bigo_sscd_platdata, - .release = bigo_sscd_release, - }, -}; - -static void bigo_coredump(struct bigo_core *core, const char *crash_info) -{ - struct sscd_platform_data *sscd_platdata = &bigo_sscd_platdata; - struct sscd_segment seg; - - if (!sscd_platdata->sscd_report) - return; - - memset(&seg, 0, sizeof(seg)); - seg.addr = (void *)core->base; - seg.size = core->regs_size; - seg.flags = 0; - seg.paddr = (void *)core->paddr; - seg.vaddr = (void *)core->base; - - sscd_platdata->sscd_report(&bigo_sscd_dev, &seg, 1, - SSCD_FLAGS_ELFARM64HDR, crash_info); -} - -static inline int on_first_instance_open(struct bigo_core *core) -{ - int rc; - - core->worker_thread = kthread_run(bigo_worker_thread, (void *)core, - "bigo_worker_thread"); - if (IS_ERR(core->worker_thread)) { - rc = PTR_ERR(core->worker_thread); - core->worker_thread = NULL; - pr_err("failed to create worker thread rc = %d\n", rc); - goto exit; - } - - rc = bigo_pt_client_enable(core); - if (rc) { - pr_info("failed to enable SLC"); - kthread_stop(core->worker_thread); - goto exit; - } -#if IS_ENABLED(CONFIG_PM) - rc = pm_runtime_get_sync(core->dev); - if (rc) { - pr_err("failed to resume: %d\n", rc); - kthread_stop(core->worker_thread); - } -#endif - -exit: - return rc; -} - -static inline void on_last_inst_close(struct bigo_core *core) -{ -#if IS_ENABLED(CONFIG_PM) - if (pm_runtime_put_sync_suspend(core->dev)) - pr_warn("failed to suspend\n"); -#endif - bigo_pt_client_disable(core); -} - -static inline int bigo_count_inst(struct bigo_core *core) -{ - int count = 0; - struct list_head *pos; - - list_for_each(pos, &core->instances) - count++; - - return count; -} - -static int bigo_open(struct inode *inode, struct file *file) -{ - int rc = 0; - struct bigo_core *core = container_of(inode->i_cdev, struct bigo_core, cdev); - struct bigo_inst *inst; - - inst = kzalloc(sizeof(*inst), GFP_KERNEL); - if (!inst) { - rc = -ENOMEM; - pr_err("Failed to create instance\n"); - goto err; - } - INIT_LIST_HEAD(&inst->list); - INIT_LIST_HEAD(&inst->buffers); - kref_init(&inst->refcount); - mutex_init(&inst->lock); - init_completion(&inst->job_comp); - file->private_data = inst; - inst->height = DEFAULT_WIDTH; - inst->width = DEFAULT_HEIGHT; - inst->fps = DEFAULT_FPS; - inst->core = core; - inst->idle = true; - inst->job.regs_size = core->regs_size; - inst->job.regs = kzalloc(core->regs_size, GFP_KERNEL); - if (!inst->job.regs) { - rc = -ENOMEM; - pr_err("Failed to alloc job regs\n"); - goto err_first_inst; - } - mutex_lock(&core->lock); - if (bigo_count_inst(core) >= BIGO_MAX_INST_NUM) { - rc = -ENOMEM; - pr_err("Reaches max number of supported instances\n"); - mutex_unlock(&core->lock); - goto err_inst_open; - } - if (list_empty(&core->instances)) { - rc = on_first_instance_open(core); - if (rc) { - pr_err("failed to setup first instance"); - mutex_unlock(&core->lock); - goto err_inst_open; - } - } - list_add_tail(&inst->list, &core->instances); - mutex_unlock(&core->lock); - bigo_mark_qos_dirty(core); - pr_info("opened instance\n"); - return rc; - -err_inst_open: - kfree(inst->job.regs); -err_first_inst: - kfree(inst); -err: - return rc; -} - -static void bigo_close(struct kref *ref) -{ - struct bigo_inst *inst = container_of(ref, struct bigo_inst, refcount); - - if (inst && inst->core) { - clear_job_from_prioq(inst->core, inst); - bigo_unmap_all(inst); - bigo_mark_qos_dirty(inst->core); - bigo_update_qos(inst->core); - kfree(inst->job.regs); - kfree(inst); - pr_info("closed instance\n"); - } -} - -static int bigo_release(struct inode *inode, struct file *file) -{ - struct bigo_inst *inst = file->private_data; - struct bigo_core *core = inst->core; - - if (!inst || !core) - return -EINVAL; - - mutex_lock(&core->lock); - list_del(&inst->list); - if (list_empty(&core->instances)) { - kthread_stop(core->worker_thread); - on_last_inst_close(core); - } - mutex_unlock(&core->lock); - - kref_put(&inst->refcount, bigo_close); - return 0; -} - -static int bigo_run_job(struct bigo_core *core, struct bigo_job *job) -{ - long ret = 0; - int rc = 0; - u32 status = 0; - unsigned long flags; - - bigo_bypass_ssmt_pid(core); - bigo_push_regs(core, job->regs); - bigo_core_enable(core); - ret = wait_for_completion_timeout(&core->frame_done, - msecs_to_jiffies(JOB_COMPLETE_TIMEOUT_MS)); - if (!ret) { - pr_err("timed out waiting for HW\n"); - - spin_lock_irqsave(&core->status_lock, flags); - core->stat_with_irq = bigo_core_readl(core, BIGO_REG_STAT); - spin_unlock_irqrestore(&core->status_lock, flags); - - bigo_core_disable(core); - rc = -ETIMEDOUT; - } else { - rc = 0; - } - - status = bigo_check_status(core); - ret = bigo_wait_disabled(core, BIGO_DISABLE_TIMEOUT_MS); - if (rc || ret || core->debugfs.trigger_ssr) { - if(core->debugfs.trigger_ssr) - rc = -EFAULT; - pr_err("timed out or failed to disable hw: %d, %ld, status: 0x%x\n", - rc, ret, status); - bigo_coredump(core, "bigo_timeout"); - } - - bigo_pull_regs(core, job->regs); - *(u32 *)(job->regs + BIGO_REG_STAT) = status; - if (rc || ret) - rc = -ETIMEDOUT; - return rc; -} - -inline void bigo_config_frmrate(struct bigo_inst *inst, __u32 frmrate) -{ - mutex_lock(&inst->lock); - inst->fps = frmrate; - mutex_unlock(&inst->lock); - bigo_mark_qos_dirty(inst->core); -} - -inline void bigo_config_frmsize(struct bigo_inst *inst, - struct bigo_ioc_frmsize *frmsize) -{ - mutex_lock(&inst->lock); - inst->height = frmsize->height; - inst->width = frmsize->width; - mutex_unlock(&inst->lock); - bigo_mark_qos_dirty(inst->core); -} - -inline void bigo_config_secure(struct bigo_inst *inst, __u32 is_secure) -{ - mutex_lock(&inst->lock); - inst->is_secure = is_secure; - mutex_unlock(&inst->lock); -} - -static int copy_regs_from_user(struct bigo_core *core, - struct bigo_ioc_regs *desc, - void __user *user_desc, - struct bigo_job *job) -{ - if (!core || !desc || !user_desc || !job) - return -EINVAL; - - if (copy_from_user(desc, user_desc, sizeof(*desc))) - return -EFAULT; - - if (desc->regs_size != core->regs_size) { - pr_err("Reg size of userspace(%u) is different(%u)\n", - (unsigned int)desc->regs_size, core->regs_size); - return -EINVAL; - } - - if (copy_from_user(job->regs, (void *)desc->regs, desc->regs_size)) - return -EFAULT; - - return 0; -} - -static int copy_regs_to_user(struct bigo_ioc_regs *desc, - struct bigo_job *job) -{ - if (!desc || !job) - return -EINVAL; - - if (copy_to_user((void *)desc->regs, job->regs, desc->regs_size)) - return -EFAULT; - - return 0; -} - -static long bigo_unlocked_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct bigo_inst *inst = file->private_data; - struct bigo_core *core = - container_of(file->f_inode->i_cdev, struct bigo_core, cdev); - void __user *user_desc = (void __user *)arg; - struct bigo_ioc_mapping mapping; - struct bigo_ioc_frmsize frmsize; - struct bigo_cache_info cinfo; - struct bigo_inst *curr_inst; - bool found = false; - int rc = 0; - - if (_IOC_TYPE(cmd) != BIGO_IOC_MAGIC) { - pr_err("Bad IOCTL\n"); - return -EINVAL; - } - if (_IOC_NR(cmd) > BIGO_CMD_MAXNR) { - pr_err("Bad IOCTL\n"); - return -EINVAL; - } - if (!inst || !core) { - pr_err("No instance or core\n"); - return -EINVAL; - } - mutex_lock(&core->lock); - list_for_each_entry(curr_inst, &core->instances, list) { - if (curr_inst == inst) { - found = true; - break; - } - } - - if (!found) { - mutex_unlock(&core->lock); - pr_err("this instance is invalid"); - return -EINVAL; - } - kref_get(&inst->refcount); - mutex_unlock(&core->lock); - switch (cmd) { - case BIGO_IOCX_PROCESS: - { - struct bigo_ioc_regs desc; - struct bigo_job *job = &inst->job; - long ret; - - if (copy_regs_from_user(core, &desc, user_desc, job)) { - pr_err("Failed to copy regs from user\n"); - return -EFAULT; - } - - if(enqueue_prioq(core, inst)) { - pr_err("Failed enqueue frame\n"); - return -EFAULT; - } - - ret = wait_for_completion_timeout( - &inst->job_comp, - msecs_to_jiffies(JOB_COMPLETE_TIMEOUT_MS * 16)); - if (!ret) { - pr_err("timed out waiting for HW: %d\n", rc); - clear_job_from_prioq(core, inst); - rc = -ETIMEDOUT; - } else { - rc = (ret > 0) ? 0 : ret; - } - - if (rc) - break; - - rc = job->status; - if(copy_regs_to_user(&desc, job)) { - pr_err("Failed to copy regs to user\n"); - rc = -EFAULT; - } - break; - } - case BIGO_IOCX_MAP: - if (copy_from_user(&mapping, user_desc, sizeof(mapping))) { - pr_err("Failed to copy from user\n"); - return -EFAULT; - } - rc = bigo_map(core, inst, &mapping); - if (rc) - pr_err("Error mapping: %d\n", mapping.fd); - if (copy_to_user(user_desc, &mapping, sizeof(mapping))) { - pr_err("Failed to copy to user\n"); - rc = -EFAULT; - } - break; - case BIGO_IOCX_UNMAP: - if (copy_from_user(&mapping, user_desc, sizeof(mapping))) { - pr_err("Failed to copy from user\n"); - return -EFAULT; - } - rc = bigo_unmap(inst, &mapping); - if (rc) - pr_err("Error un-mapping: %d\n", mapping.fd); - break; - case BIGO_IOCX_CONFIG_FRMRATE: { - u32 frmrate = (u32)arg; - - bigo_config_frmrate(inst, frmrate); - break; - } - case BIGO_IOCX_CONFIG_FRMSIZE: - if (copy_from_user(&frmsize, user_desc, sizeof(frmsize))) { - pr_err("Failed to copy from user\n"); - return -EFAULT; - } - bigo_config_frmsize(inst, &frmsize); - break; - case BIGO_IOCX_GET_CACHE_INFO: - bigo_get_cache_info(inst->core, &cinfo); - if (copy_to_user(user_desc, &cinfo, sizeof(cinfo))) { - pr_err("Failed to copy to user\n"); - rc = -EFAULT; - } - break; - case BIGO_IOCX_CONFIG_SECURE: { - u32 is_secure = (u32)arg; - bigo_config_secure(inst, is_secure); - break; - } - case BIGO_IOCX_ABORT: - break; - default: - rc = -EINVAL; - break; - } - - kref_put(&inst->refcount, bigo_close); - return rc; -} - -static irqreturn_t bigo_isr(int irq, void *arg) -{ - struct bigo_core *core = (struct bigo_core *)arg; - u32 bigo_stat; - unsigned long flags; - - bigo_stat = bigo_core_readl(core, BIGO_REG_STAT); - - if (!(bigo_stat & BIGO_STAT_IRQ)) - return IRQ_NONE; - - spin_lock_irqsave(&core->status_lock, flags); - core->stat_with_irq = bigo_stat; - spin_unlock_irqrestore(&core->status_lock, flags); - bigo_stat &= ~BIGO_STAT_IRQMASK; - bigo_core_writel(core, BIGO_REG_STAT, bigo_stat); - complete(&core->frame_done); - return IRQ_HANDLED; -} - -#if IS_ENABLED(CONFIG_PM) -static const struct dev_pm_ops bigo_pm_ops = { - SET_RUNTIME_PM_OPS(bigo_runtime_suspend, bigo_runtime_resume, NULL) -}; -#endif - -static const struct file_operations bigo_fops = { - .owner = THIS_MODULE, - .open = bigo_open, - .release = bigo_release, - .unlocked_ioctl = bigo_unlocked_ioctl, - .compat_ioctl = bigo_unlocked_ioctl, -}; - -static int init_chardev(struct bigo_core *core) -{ - int rc; - - cdev_init(&core->cdev, &bigo_fops); - core->cdev.owner = THIS_MODULE; - rc = alloc_chrdev_region(&core->devno, 0, 1, BIGO_CHRDEV_NAME); - if (rc < 0) { - pr_err("Failed to alloc chrdev region\n"); - goto err; - } - rc = cdev_add(&core->cdev, core->devno, 1); - if (rc) { - pr_err("Failed to register chrdev\n"); - goto err_cdev_add; - } - - core->_class = class_create(THIS_MODULE, BIGO_DEVCLASS_NAME); - if (IS_ERR(core->_class)) { - rc = PTR_ERR(core->_class); - goto err_class_create; - } - - core->svc_dev = device_create(core->_class, NULL, core->cdev.dev, core, - BIGO_CHRDEV_NAME); - if (IS_ERR(core->svc_dev)) { - pr_err("device_create err\n"); - rc = PTR_ERR(core->svc_dev); - goto err_device_create; - } - return rc; - -err_device_create: - class_destroy(core->_class); -err_class_create: - cdev_del(&core->cdev); -err_cdev_add: - unregister_chrdev_region(core->devno, 1); -err: - return rc; -} - -static void deinit_chardev(struct bigo_core *core) -{ - if (!core) - return; - - device_destroy(core->_class, core->devno); - class_destroy(core->_class); - cdev_del(&core->cdev); - unregister_chrdev_region(core->devno, 1); -} - -static inline void mark_instances_idle(struct bigo_core *core) -{ - struct bigo_inst *curr_inst; - mutex_lock(&core->lock); - list_for_each_entry(curr_inst, &core->instances, list) - curr_inst->idle = true; - mutex_unlock(&core->lock); -} - -static int bigo_worker_thread(void *data) -{ - struct bigo_core *core = (struct bigo_core *)data; - struct bigo_inst *inst; - struct bigo_job *job = NULL; - bool should_stop; - int rc; - - if (!core) - return -ENOMEM; - - while(1) { - rc = wait_event_timeout(core->worker, - dequeue_prioq(core, &job, &should_stop), - msecs_to_jiffies(BIGO_IDLE_TIMEOUT_MS)); - if (!rc && !should_stop) { - /* Mark all instances as IDLE since none of these - * instances queued a job for BIGO_IDLE_TIMEOUT_MS - */ - mark_instances_idle(core); - bigo_clocks_off(core); - bigo_mark_qos_dirty(core); - pr_info("bigocean entered idle state\n"); - wait_event(core->worker, - dequeue_prioq(core, &job, &should_stop)); - pr_info("bigocean resumed to work\n"); - } - if(should_stop) { - pr_info("worker thread received stop signal, exit\n"); - return 0; - } - if (!job) - continue; - - inst = container_of(job, struct bigo_inst, job); - - if (inst->idle) { - inst->idle = false; - bigo_mark_qos_dirty(core); - } - - bigo_update_qos(core); - if (inst->is_secure) { - rc = exynos_smc(SMC_PROTECTION_SET, 0, BIGO_SMC_ID, - SMC_PROTECTION_ENABLE); - if (rc) { - pr_err("failed to enable SMC_PROTECTION_SET: %d\n", rc); - goto done; - } - } - - rc = bigo_run_job(core, job); - if (rc) { - pr_err("Error running job\n"); - goto done; - } - - if (inst->is_secure) { - rc = exynos_smc(SMC_PROTECTION_SET, 0, BIGO_SMC_ID, - SMC_PROTECTION_DISABLE); - if (rc) - pr_err("failed to disable SMC_PROTECTION_SET: %d\n", rc); - } - - done: - job->status = rc; - complete(&inst->job_comp); - } - return 0; -} - -static int bigo_probe(struct platform_device *pdev) -{ - int rc = 0; - int i; - struct bigo_core *core; - - core = devm_kzalloc(&pdev->dev, sizeof(struct bigo_core), GFP_KERNEL); - if (!core) { - rc = -ENOMEM; - goto err; - } - - mutex_init(&core->lock); - mutex_init(&core->prioq.lock); - INIT_LIST_HEAD(&core->instances); - INIT_LIST_HEAD(&core->pm.opps); - INIT_LIST_HEAD(&core->pm.bw); - for(i = 0; i < BO_MAX_PRIO; ++i) - INIT_LIST_HEAD(&core->prioq.queue[i]); - spin_lock_init(&core->status_lock); - init_completion(&core->frame_done); - init_waitqueue_head(&core->worker); - core->dev = &pdev->dev; - platform_set_drvdata(pdev, core); - - rc = init_chardev(core); - if (rc) { - pr_err("Failed to initialize chardev for bigocean: %d\n", rc); - goto err_init_chardev; - } - - rc = bigo_of_dt_parse(core); - if (rc) { - pr_err("Failed to parse DT node\n"); - goto err_dt_parse; - } - - rc = bigo_init_io(core, bigo_isr); - if (rc < 0) { - pr_err("failed to request irq\n"); - goto err_io; - } - - /* TODO(vinaykalia@): Move pm_runtime_enable call somewhere else? */ - pm_runtime_enable(&pdev->dev); - rc = bigo_pm_init(core); - if (rc) { - pr_err("Failed to initialize power management\n"); - goto err_io; - } - - rc = iommu_register_device_fault_handler(&pdev->dev, bigo_iommu_fault_handler, core); - if (rc) { - pr_err("failed to register iommu fault handler: %d\n", rc); - goto err_fault_handler; - } - - rc = bigo_pt_client_register(pdev->dev.of_node, core); - if (rc == -EPROBE_DEFER) { - pr_warn("pt_client returns -EPROBE_DEFER, try again later\n"); - goto err_pt_client; - } else { - rc = 0; - } - - if(platform_device_register(&bigo_sscd_dev)) - pr_warn("Failed to register bigo_sscd_dev.\n"); - - bigo_init_debugfs(core); - - return rc; - -err_pt_client: - iommu_unregister_device_fault_handler(&pdev->dev); -err_fault_handler: - pm_runtime_disable(&pdev->dev); -err_io: - bigo_of_dt_release(core); -err_dt_parse: - deinit_chardev(core); -err_init_chardev: - platform_set_drvdata(pdev, NULL); -err: - return rc; -} - -static int bigo_remove(struct platform_device *pdev) -{ - struct bigo_core *core = (struct bigo_core *)platform_get_drvdata(pdev); - - bigo_uninit_debugfs(core); - platform_device_unregister(&bigo_sscd_dev); - bigo_pt_client_unregister(core); - iommu_unregister_device_fault_handler(&pdev->dev); - pm_runtime_disable(&pdev->dev); - bigo_of_dt_release(core); - deinit_chardev(core); - platform_set_drvdata(pdev, NULL); - return 0; -} - -static const struct of_device_id bigo_dt_match[] = { - { .compatible = "google,bigocean" }, - {} -}; - -static struct platform_driver bigo_driver = { - .probe = bigo_probe, - .remove = bigo_remove, - .driver = { - .name = "bigocean", - .owner = THIS_MODULE, - .of_match_table = bigo_dt_match, -#ifdef CONFIG_PM - .pm = &bigo_pm_ops, -#endif - }, -}; - -module_platform_driver(bigo_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); -MODULE_DESCRIPTION("BigOcean driver"); diff --git a/drivers/media/platform/bigocean/bigo_debug.c b/drivers/media/platform/bigocean/bigo_debug.c deleted file mode 100644 index a8c539d594df..000000000000 --- a/drivers/media/platform/bigocean/bigo_debug.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Driver for BigOcean video accelerator - * - * Copyright 2021 Google LLC. - * - * Author: Ruofei Ma - */ - -#include -#include -#include - -#include "bigo_debug.h" - -static int avail_freq_show(struct seq_file *s, void *unused) -{ - struct bigo_core *core = s->private; - struct bigo_opp *opp; - - list_for_each_entry (opp, &core->pm.opps, list) - seq_printf(s, "%d\n", opp->freq_khz); - - return 0; -} - -static int avail_freqs_open(struct inode *inode, struct file *file) -{ - return single_open(file, avail_freq_show, inode->i_private); -} - -static const struct file_operations avail_freqs_fops = { - .open = avail_freqs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -void bigo_init_debugfs(struct bigo_core *core) -{ - struct bigo_debugfs *debugfs = &core->debugfs; - - debugfs->set_freq = 0; - debugfs->trigger_ssr = 0; - - debugfs->root = debugfs_create_dir("bigo", NULL); - debugfs_create_file("avail_freqs", 0400, debugfs->root, core, - &avail_freqs_fops); - debugfs_create_u32("set_freq", 0200, debugfs->root, &debugfs->set_freq); - debugfs_create_u32("trigger_ssr", 0600, debugfs->root, - &debugfs->trigger_ssr); -} - -void bigo_uninit_debugfs(struct bigo_core *core) -{ - debugfs_remove_recursive(core->debugfs.root); -} \ No newline at end of file diff --git a/drivers/media/platform/bigocean/bigo_debug.h b/drivers/media/platform/bigocean/bigo_debug.h deleted file mode 100644 index 42ddfce3663e..000000000000 --- a/drivers/media/platform/bigocean/bigo_debug.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2021 Google LLC. - * - * Author: Ruofei Ma - */ - -#ifndef _BIGO_DEBUG_H_ -#define _BIGO_DEBUG_H_ - -#include "bigo_priv.h" - -#if IS_ENABLED(CONFIG_DEBUG_FS) -void bigo_init_debugfs(struct bigo_core *core); -void bigo_uninit_debugfs(struct bigo_core *core); -#else -static inline void bigo_init_debugfs(struct bigo_core *core) { } -static inline void bigo_uninit_debugfs(struct bigo_core *core) { } -#endif - -#endif /* _BIGO_DEBUG_H_ */ diff --git a/drivers/media/platform/bigocean/bigo_io.c b/drivers/media/platform/bigocean/bigo_io.c deleted file mode 100644 index c866f8de1014..000000000000 --- a/drivers/media/platform/bigocean/bigo_io.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * I/O methods for communication with BigOcean - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include - -#include "bigo_io.h" - -int bigo_init_io(struct bigo_core *core, irq_handler_t handler) -{ - struct platform_device *pdev = to_platform_device(core->dev); - int rc; - - rc = devm_request_irq(&pdev->dev, core->irq, handler, IRQF_SHARED, - dev_name(&pdev->dev), core); - if (rc < 0) - pr_err("failed to request irq: %d\n", rc); - return rc; -} - -u32 bigo_core_readl(struct bigo_core *core, ptrdiff_t offset) -{ - return readl(core->base + offset); -} - -void bigo_core_writel(struct bigo_core *core, ptrdiff_t offset, u32 val) -{ - writel(val, core->base + offset); -} - -void bigo_push_regs(struct bigo_core *core, void *regs) -{ - memcpy_toio(core->base, regs, core->regs_size); -} - -void bigo_pull_regs(struct bigo_core *core, void *regs) -{ - memcpy_fromio(regs, core->base, core->regs_size); -} - -void bigo_core_enable(struct bigo_core *core) -{ - u32 bigo_stat = bigo_core_readl(core, BIGO_REG_STAT); - - bigo_stat |= BIGO_STAT_ENABLE; - bigo_core_writel(core, BIGO_REG_STAT, bigo_stat); - pr_debug("core enable\n"); -} - -void bigo_core_disable(struct bigo_core *core) -{ - u32 bigo_stat = bigo_core_readl(core, BIGO_REG_STAT); - - bigo_stat &= ~BIGO_STAT_ENABLE; - bigo_core_writel(core, BIGO_REG_STAT, bigo_stat); - pr_debug("core disable\n"); -} - -inline bool bigo_core_is_enabled(struct bigo_core *core) -{ - return bigo_core_readl(core, BIGO_REG_STAT) & BIGO_STAT_ENABLE; -} - -inline int bigo_wait_disabled(struct bigo_core *core, int timeout_ms) -{ - int i; - - for (i = 0; i < timeout_ms; ++i) { - if (!bigo_core_is_enabled(core)) - break; - usleep_range(900, 1100); - } - if (i >= timeout_ms) { - pr_err("Failed to disable the core in %d ms\n", i); - return -ETIMEDOUT; - } - - return 0; -} - -u32 bigo_check_status(struct bigo_core *core) -{ - u32 status; - unsigned long flags; - - spin_lock_irqsave(&core->status_lock, flags); - status = core->stat_with_irq; - spin_unlock_irqrestore(&core->status_lock, flags); - - if (status & BIGO_STAT_IRQ_TIMEOUT) - pr_err("hw timedout: 0x%x\n", status); - if (status & BIGO_STAT_IRQ_BUS_ERROR) - pr_err("bus error: 0x%x\n", status); - if (status & BIGO_STAT_IRQ_DEC_ERROR) - pr_err("decoding error: 0x%x\n", status); - if (status & BIGO_STAT_AXI_RD_OVERFLOW) { - pr_err("axi read overflow, status: 0x%x, id: %lu\n", status, - status & BIG_STAT_AXI_OVERFLOW_ID); - } - if (status & BIGO_STAT_AXI_WR_OVERFLOW) { - pr_err("axi write undererflow, status: 0x%x, id: %lu\n", status, - status & BIG_STAT_AXI_OVERFLOW_ID); - } - if (status & BIGO_STAT_AXI_RD_PENDING) - pr_err("axi read pending: 0x%x\n", status); - if (status & BIGO_STAT_AXI_WR_PENDING) - pr_err("axi write pending: 0x%x\n", status); - - return status; -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); diff --git a/drivers/media/platform/bigocean/bigo_io.h b/drivers/media/platform/bigocean/bigo_io.h deleted file mode 100644 index 040680e00460..000000000000 --- a/drivers/media/platform/bigocean/bigo_io.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_IO_H_ -#define _BIGO_IO_H_ - -#include - -#include "bigo_priv.h" - -#define BIGO_REG_PRODUCT 0x00 -#define BIGO_REG_CFG 0x04 -#define BIGO_REG_STAT 0x08 - -#define BIGO_CFG_H264 BIT(2) -#define BIGO_CFG_VP9D BIT(3) -#define BIGO_CFG_VP9E BIT(4) -#define BIGO_CFG_AV1 BIT(5) - -#define BIGO_STAT_ENABLE BIT(0) -#define BIGO_STAT_MODE BIT(1) -#define BIGO_STAT_IRQ_TIMEOUT BIT(2) -#define BIGO_STAT_IRQ_BUS_ERROR BIT(3) -#define BIGO_STAT_IRQ_FRAME_READY BIT(4) -#define BIGO_STAT_IRQ_DEC_ERROR BIT(5) -#define BIGO_STAT_IRQ BIT(6) -#define BIGO_STAT_AXI_RD_OVERFLOW BIT(9) -#define BIGO_STAT_AXI_WR_OVERFLOW BIT(10) -#define BIGO_STAT_AXI_RD_PENDING BIT(19) -#define BIGO_STAT_AXI_WR_PENDING BIT(20) -#define BIG_STAT_AXI_OVERFLOW_ID GENMASK(30, 23) - -#define BIGO_STAT_IRQMASK GENMASK(6, 2) - -#define BIGO_DISABLE_TIMEOUT_MS 10 -/* - * 1. This timeout should be more than the max time HW takes to - * process max resolution frame at min frequency (usecase: - * non-realtime scenarios) - * 2. This timeout is not for catching bigocean hardware hangs - * because if hardware is really hung, it should trigger an IRQ with - * BIGO_STAT_IRQ_TIMEOUT_BIT so HW hang should be caught there. - * 3. This timeout is to catch any other issues with the system. - */ -#define JOB_COMPLETE_TIMEOUT_MS 500 - -int bigo_init_io(struct bigo_core *core, irq_handler_t handler); -u32 bigo_core_readl(struct bigo_core *core, ptrdiff_t offset); -void bigo_core_writel(struct bigo_core *core, ptrdiff_t offset, u32 val); -void bigo_push_regs(struct bigo_core *core, void *regs); -void bigo_pull_regs(struct bigo_core *core, void *regs); -void bigo_core_enable(struct bigo_core *core); -void bigo_core_disable(struct bigo_core *core); -bool bigo_core_is_enabled(struct bigo_core *core); -int bigo_wait_disabled(struct bigo_core *core, int timeout_ms); -u32 bigo_check_status(struct bigo_core *core); - -#endif //_BIGO_REGS_H_ diff --git a/drivers/media/platform/bigocean/bigo_iommu.c b/drivers/media/platform/bigocean/bigo_iommu.c deleted file mode 100644 index f59d279ff07e..000000000000 --- a/drivers/media/platform/bigocean/bigo_iommu.c +++ /dev/null @@ -1,150 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * IOMMU operations for BigOcean - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include - -#include "bigo_iommu.h" - -static void bigo_unmap_one(struct bigo_core *core, struct bufinfo *binfo) -{ - /* This lock is needed to unmap. Look @ b/180443732 */ - mutex_lock(&core->lock); - binfo->attachment->dma_map_attrs |= DMA_ATTR_SKIP_LAZY_UNMAP; - dma_buf_unmap_attachment(binfo->attachment, binfo->sgt, - DMA_BIDIRECTIONAL); - dma_buf_detach(binfo->dmabuf, binfo->attachment); - dma_buf_put(binfo->dmabuf); - mutex_unlock(&core->lock); -} - -void bigo_unmap_all(struct bigo_inst *inst) -{ - struct bufinfo *curr, *next; - - mutex_lock(&inst->lock); - list_for_each_entry_safe(curr, next, &inst->buffers, list) { - list_del(&curr->list); - bigo_unmap_one(inst->core, curr); - kfree(curr); - } - mutex_unlock(&inst->lock); -} - -static int check_mapped_list(struct bigo_core *core, struct bigo_inst *inst, - struct bigo_ioc_mapping *mapping) -{ - int found = -1; - struct bufinfo *binfo; - - mutex_lock(&inst->lock); - list_for_each_entry(binfo, &inst->buffers, list) { - /* - * TODO(vinaykalia@): Do we need to check for size, - * offset, etc? - */ - if (binfo->fd == mapping->fd) { - mapping->iova = binfo->iova; - found = 0; - break; - } - } - mutex_unlock(&inst->lock); - return found; -} - -static int add_to_mapped_list(struct bigo_core *core, struct bigo_inst *inst, - struct bigo_ioc_mapping *mapping) -{ - int rc = 0; - struct bufinfo *binfo; - - binfo = kzalloc(sizeof(*binfo), GFP_KERNEL); - if (!binfo) - return -ENOMEM; - binfo->dmabuf = dma_buf_get(mapping->fd); - if (IS_ERR(binfo->dmabuf)) { - rc = PTR_ERR(binfo->dmabuf); - pr_err("failed to get dma buf(%d): %d\n", mapping->fd, rc); - goto fail_buf_get; - } - - binfo->attachment = dma_buf_attach(binfo->dmabuf, core->dev); - if (IS_ERR(binfo->attachment)) { - rc = PTR_ERR(binfo->attachment); - pr_err("failed to dma_buf_attach: %d\n", rc); - goto fail_attach; - } - - binfo->sgt = dma_buf_map_attachment(binfo->attachment, DMA_BIDIRECTIONAL); - if (IS_ERR(binfo->sgt)) { - rc = PTR_ERR(binfo->sgt); - pr_err("failed to dma_buf_map_attachment: %d\n", rc); - goto fail_map_attachment; - } - binfo->iova = sg_dma_address(binfo->sgt->sgl); - binfo->fd = mapping->fd; - binfo->size = mapping->size; - binfo->offset = mapping->offset; - mutex_lock(&inst->lock); - list_add_tail(&binfo->list, &inst->buffers); - mutex_unlock(&inst->lock); - mapping->iova = binfo->iova; - return rc; - -fail_map_attachment: - dma_buf_detach(binfo->dmabuf, binfo->attachment); -fail_attach: - dma_buf_put(binfo->dmabuf); -fail_buf_get: - kfree(binfo); - return rc; -} - -int bigo_map(struct bigo_core *core, struct bigo_inst *inst, - struct bigo_ioc_mapping *mapping) -{ - if (!check_mapped_list(core, inst, mapping)) - return 0; - - return add_to_mapped_list(core, inst, mapping); -} - -int bigo_unmap(struct bigo_inst *inst, struct bigo_ioc_mapping *mapping) -{ - struct bufinfo *curr, *next; - struct bufinfo *found = NULL; - - mutex_lock(&inst->lock); - list_for_each_entry_safe(curr, next, &inst->buffers, list) { - if (curr->fd == mapping->fd) { - list_del(&curr->list); - found = curr; - break; - } - } - mutex_unlock(&inst->lock); - if (!found) - return -ENOENT; - - bigo_unmap_one(inst->core, found); - kfree(found); - return 0; -} - -int bigo_iommu_fault_handler(struct iommu_fault *fault, void *param) -{ - return NOTIFY_OK; -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); diff --git a/drivers/media/platform/bigocean/bigo_iommu.h b/drivers/media/platform/bigocean/bigo_iommu.h deleted file mode 100644 index 79da419afc76..000000000000 --- a/drivers/media/platform/bigocean/bigo_iommu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_IOMMU_H_ -#define _BIGO_IOMMU_H_ - -#include -#include - -#include "bigo_priv.h" - -void bigo_unmap_all(struct bigo_inst *inst); -int bigo_map(struct bigo_core *core, struct bigo_inst *inst, - struct bigo_ioc_mapping *mapping); -int bigo_unmap(struct bigo_inst *inst, struct bigo_ioc_mapping *mapping); -int bigo_iommu_fault_handler(struct iommu_fault *fault, void *param); - -#endif //_BIGO_IOMMU_H_ diff --git a/drivers/media/platform/bigocean/bigo_of.c b/drivers/media/platform/bigocean/bigo_of.c deleted file mode 100644 index c7ed5e5afe77..000000000000 --- a/drivers/media/platform/bigocean/bigo_of.c +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Parses BigOcean device tree node - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include -#include - -#include "bigo_of.h" - -static int bigo_of_get_resource(struct bigo_core *core) -{ - struct platform_device *pdev = to_platform_device(core->dev); - struct resource *res; - int rc = 0; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bo"); - if (IS_ERR_OR_NULL(res)) { - rc = PTR_ERR(res); - pr_err("Failed to find bo register base: %d\n", rc); - goto err; - } - core->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR_OR_NULL(core->base)) { - rc = PTR_ERR(core->base); - if (rc == 0) - rc = -EIO; - pr_err("Failed to map bo register base: %d\n", rc); - core->base = NULL; - goto err; - } - core->regs_size = res->end - res->start + 1; - core->paddr = (phys_addr_t)res->start; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ssmt_bo_pid"); - if (IS_ERR_OR_NULL(res)) { - rc = PTR_ERR(res); - pr_err("Failed to find ssmt_bo register base: %d\n", rc); - goto err; - } - core->slc.ssmt_pid_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR_OR_NULL(core->slc.ssmt_pid_base)) { - pr_warn("Failed to map ssmt_bo register base: %ld\n", - PTR_ERR(core->slc.ssmt_pid_base)); - core->slc.ssmt_pid_base = NULL; - } - - core->irq = platform_get_irq(pdev, 0); - - if (core->irq < 0) { - rc = core->irq; - pr_err("platform_get_irq failed: %d\n", rc); - goto err; - } - -err: - return rc; -} - -static void bigo_of_remove_opp_table(struct bigo_core *core) -{ - struct bigo_opp *opp, *tmp; - - list_for_each_entry_safe(opp, tmp, &core->pm.opps, list) { - list_del(&opp->list); - kfree(opp); - } -} - -static void bigo_of_remove_bw_table(struct bigo_core *core) -{ - struct bigo_bw *bw, *tmp; - - list_for_each_entry_safe(bw, tmp, &core->pm.bw, list) { - list_del(&bw->list); - kfree(bw); - } -} - -static int bigo_of_parse_opp_table(struct bigo_core *core) -{ - int rc = 0; - struct device_node *np; - struct bigo_opp *opp; - - struct device_node *opp_np = - of_parse_phandle(core->dev->of_node, "bigo-opp-table", 0); - if (!opp_np) { - return -ENOENT; - goto err_add_table; - } - for_each_available_child_of_node(opp_np, np) { - opp = kmalloc(sizeof(*opp), GFP_KERNEL); - if (!opp) { - rc = -ENOMEM; - goto err_entry; - } - rc = of_property_read_u32(np, "load-pps", &opp->load_pps); - if (rc < 0) { - kfree(opp); - goto err_entry; - } - core->pm.max_load = opp->load_pps; - rc = of_property_read_u32(np, "freq-khz", &opp->freq_khz); - if (rc < 0) { - kfree(opp); - goto err_entry; - } - - list_add_tail(&opp->list, &core->pm.opps); - } - return rc; -err_entry: - bigo_of_remove_opp_table(core); -err_add_table: - return rc; -} - -static int bigo_of_parse_bw_table(struct bigo_core *core) -{ - int rc = 0; - struct device_node *np; - struct bigo_bw *bw; - - struct device_node *bw_np = - of_parse_phandle(core->dev->of_node, "bigo-bw-table", 0); - if (!bw_np) { - return -ENOENT; - goto err_add_table; - } - for_each_available_child_of_node(bw_np, np) { - bw = kmalloc(sizeof(*bw), GFP_KERNEL); - if (!bw) { - rc = -ENOMEM; - goto err_entry; - } - rc = of_property_read_u32(np, "load-pps", &bw->load_pps); - if (rc < 0) { - kfree(bw); - goto err_entry; - } - rc = of_property_read_u32(np, "rd-bw", &bw->rd_bw); - if (rc < 0) { - kfree(bw); - goto err_entry; - } - rc = of_property_read_u32(np, "wr-bw", &bw->wr_bw); - if (rc < 0) { - kfree(bw); - goto err_entry; - } - rc = of_property_read_u32(np, "pk-bw", &bw->pk_bw); - if (rc < 0) { - kfree(bw); - goto err_entry; - } - list_add_tail(&bw->list, &core->pm.bw); - } - return rc; -err_entry: - bigo_of_remove_bw_table(core); -err_add_table: - return rc; -} - -int bigo_of_dt_parse(struct bigo_core *core) -{ - int rc = 0; - - rc = bigo_of_get_resource(core); - if (rc < 0) { - pr_err("failed to get respource: %d\n", rc); - goto err_get_res; - } - - rc = bigo_of_parse_opp_table(core); - if (rc < 0) { - pr_err("failed to parse bigocean OPP table\n"); - goto err_parse_opp_table; - } - - rc = bigo_of_parse_bw_table(core); - if (rc < 0) { - pr_err("failed to parse bigocean bandwidth table\n"); - goto err_parse_bw_table; - } - - core->pm.bwindex = bts_get_bwindex("bo"); - if (core->pm.bwindex < 0) { - rc = core->pm.bwindex; - goto err_bwindex; - } - - return rc; -err_bwindex: - bigo_of_remove_bw_table(core); -err_parse_bw_table: - bigo_of_remove_opp_table(core); -err_parse_opp_table: -err_get_res: - return rc; -} - -void bigo_of_dt_release(struct bigo_core *core) -{ - if (!core) - return; - bigo_of_remove_opp_table(core); -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); diff --git a/drivers/media/platform/bigocean/bigo_of.h b/drivers/media/platform/bigocean/bigo_of.h deleted file mode 100644 index 70e0fd4076b7..000000000000 --- a/drivers/media/platform/bigocean/bigo_of.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_OF_H_ -#define _BIGO_OF_H_ - -#include "bigo_priv.h" - -int bigo_of_dt_parse(struct bigo_core *core); -void bigo_of_dt_release(struct bigo_core *core); - -#endif //_BIGO_OF_H_ diff --git a/drivers/media/platform/bigocean/bigo_pm.c b/drivers/media/platform/bigocean/bigo_pm.c deleted file mode 100644 index 60c52996e592..000000000000 --- a/drivers/media/platform/bigocean/bigo_pm.c +++ /dev/null @@ -1,166 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * BigOcean power management - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include -#include -#include - -#include "bigo_pm.h" -#include "bigo_io.h" - -static inline u32 bigo_get_total_load(struct bigo_core *core) -{ - struct bigo_inst *inst; - u32 load = 0; - u32 curr_load = 0; - - if (list_empty(&core->instances)) - return 0; - - list_for_each_entry(inst, &core->instances, list) { - if (inst->idle) - continue; - curr_load = inst->width * inst->height * inst->fps / 1024; - if (curr_load < core->pm.max_load - load) { - load += curr_load; - } else { - load = core->pm.max_load; - break; - } - } - /* 1 <= load <= core->pm.max_load */ - load = max(1U, load); - load = min(load, core->pm.max_load); - return load; -} - -static inline u32 bigo_get_target_freq(struct bigo_core *core, u32 load) -{ - struct bigo_opp *opp; - - list_for_each_entry(opp, &core->pm.opps, list) { - if (opp->load_pps >= load) - break; - } - return opp->freq_khz; -} - -static inline struct bigo_bw *bigo_get_target_bw(struct bigo_core *core, u32 load) -{ - struct bigo_bw *bw; - - list_for_each_entry(bw, &core->pm.bw, list) { - if (bw->load_pps >= load) - break; - } - return bw; -} - -static inline void bigo_set_freq(struct bigo_core *core, u32 freq) -{ - if (core->debugfs.set_freq) - freq = core->debugfs.set_freq; - - if (!exynos_pm_qos_request_active(&core->pm.qos_bigo)) - exynos_pm_qos_add_request(&core->pm.qos_bigo, PM_QOS_BO_THROUGHPUT, freq); - else - exynos_pm_qos_update_request(&core->pm.qos_bigo, freq); -} - -static void bigo_scale_freq(struct bigo_core *core) -{ - u32 load = bigo_get_total_load(core); - u32 freq = bigo_get_target_freq(core, load); - - bigo_set_freq(core, freq); -} - -static void bigo_get_bw(struct bigo_core *core, struct bts_bw *bw) -{ - u32 load = bigo_get_total_load(core); - if (load) { - struct bigo_bw *bandwidth = bigo_get_target_bw(core, load); - bw->read = bandwidth->rd_bw; - bw->write = bandwidth->wr_bw; - bw->peak = bandwidth->pk_bw; - } else { - memset(bw, 0, sizeof(*bw)); - } - pr_debug("BW: load: %u, rd: %u, wr: %u, pk: %u", load, bw->read, bw->write, bw->peak); -} - -static int bigo_scale_bw(struct bigo_core *core) -{ - struct bts_bw bw; - - bigo_get_bw(core, &bw); - return bts_update_bw(core->pm.bwindex, bw); -} - -void bigo_mark_qos_dirty(struct bigo_core *core) -{ - mutex_lock(&core->lock); - core->qos_dirty = true; - mutex_unlock(&core->lock); -} - -void bigo_update_qos(struct bigo_core *core) -{ - int rc; - - mutex_lock(&core->lock); - if (core->qos_dirty) { - rc = bigo_scale_bw(core); - if (rc) - pr_warn("%s: failed to scale bandwidth: %d\n", __func__, rc); - - bigo_scale_freq(core); - core->qos_dirty = false; - } - mutex_unlock(&core->lock); -} - -void bigo_clocks_off(struct bigo_core *core) -{ - struct bts_bw bw; - - memset(&bw, 0, sizeof(struct bts_bw)); - - mutex_lock(&core->lock); - bts_update_bw(core->pm.bwindex, bw); - bigo_set_freq(core, bigo_get_target_freq(core, 0)); - mutex_unlock(&core->lock); -} - -/* - * bigo_pm_init(): Initializes power management for bigocean. - * @core: the bigocean core - */ -int bigo_pm_init(struct bigo_core *core) -{ - return 0; -} - -#if IS_ENABLED(CONFIG_PM) -int bigo_runtime_suspend(struct device *dev) -{ - return 0; -} - -int bigo_runtime_resume(struct device *dev) -{ - return 0; -} -#endif - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); diff --git a/drivers/media/platform/bigocean/bigo_pm.h b/drivers/media/platform/bigocean/bigo_pm.h deleted file mode 100644 index 50064a5538fd..000000000000 --- a/drivers/media/platform/bigocean/bigo_pm.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_PM_H_ -#define _BIGO_PM_H_ - -#include -#include -#include - -#include "bigo_priv.h" - -int bigo_pm_init(struct bigo_core *core); - -#if IS_ENABLED(CONFIG_PM) -int bigo_runtime_suspend(struct device *dev); -int bigo_runtime_resume(struct device *dev); -#endif -void bigo_update_qos(struct bigo_core *core); -void bigo_clocks_off(struct bigo_core *core); -void bigo_mark_qos_dirty(struct bigo_core *core); - -#endif //_BIGO_PM_H_ diff --git a/drivers/media/platform/bigocean/bigo_prioq.c b/drivers/media/platform/bigocean/bigo_prioq.c deleted file mode 100644 index c6e36ef7b484..000000000000 --- a/drivers/media/platform/bigocean/bigo_prioq.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Priority queue impletation with BigOcean - * - * Copyright 2021 Google LLC. - * - * Author: Ruofei Ma - */ - -#include -#include - -#include "bigo_prioq.h" - -int enqueue_prioq(struct bigo_core *core, struct bigo_inst *inst) -{ - struct bigo_job *job = &inst->job; - - if(!core || !inst) - return -EINVAL; - - mutex_lock(&core->prioq.lock); - list_add_tail(&job->list, &core->prioq.queue[inst->priority]); - set_bit(inst->priority, &core->prioq.bitmap); - mutex_unlock(&core->prioq.lock); - - wake_up(&core->worker); - return 0; -} - -bool dequeue_prioq(struct bigo_core *core, struct bigo_job **job, - bool *should_stop) -{ - int high_prio; - struct bigo_job *j = NULL; - struct list_head *queue; - if (!core || !job || !should_stop) - return false; - - *should_stop = false; - if(kthread_should_stop()) { - *should_stop = true; - return true; - } - - mutex_lock(&core->prioq.lock); - high_prio = ffs(core->prioq.bitmap) - 1; - if (high_prio < 0) - goto exit; - - queue = &core->prioq.queue[high_prio]; - j = list_first_entry_or_null(queue, struct bigo_job, list); - if (j) { - list_del(&j->list); - if (list_empty(queue)) - clear_bit(high_prio, &core->prioq.bitmap); - } - -exit: - mutex_unlock(&core->prioq.lock); - *job = j; - return *job != NULL; -} - -void clear_job_from_prioq(struct bigo_core *core, struct bigo_inst *inst) -{ - int i; - struct bigo_job *curr, *next; - struct bigo_inst *curr_inst; - mutex_lock(&core->prioq.lock); - for (i = 0; i < BO_MAX_PRIO; i++) { - list_for_each_entry_safe(curr, next, &core->prioq.queue[i], list) { - curr_inst = container_of(curr, struct bigo_inst, job); - if (inst == curr_inst) - list_del(&curr->list); - } - } - mutex_unlock(&core->prioq.lock); -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Ruofei Ma "); diff --git a/drivers/media/platform/bigocean/bigo_prioq.h b/drivers/media/platform/bigocean/bigo_prioq.h deleted file mode 100644 index dcd100c9e508..000000000000 --- a/drivers/media/platform/bigocean/bigo_prioq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2021 Google LLC. - * - * Author: Ruofei Ma - */ - -#ifndef _BIGO_PRIOQ_H_ -#define _BIGO_PRIOQ_H_ - -#include "bigo_priv.h" - -bool dequeue_prioq(struct bigo_core *core, struct bigo_job **job, - bool *should_stop); -int enqueue_prioq(struct bigo_core *core, struct bigo_inst *inst); - -void clear_job_from_prioq(struct bigo_core *core, struct bigo_inst *inst); - -#endif //_BIGO_PRIOQ_H_ diff --git a/drivers/media/platform/bigocean/bigo_priv.h b/drivers/media/platform/bigocean/bigo_priv.h deleted file mode 100644 index 6d07cf10e556..000000000000 --- a/drivers/media/platform/bigocean/bigo_priv.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_PRIV_H_ -#define _BIGO_PRIV_H_ - -#include -#include -#include -#include -#include -#include - -#include "uapi/linux/bigo.h" - -#if IS_ENABLED(CONFIG_SLC_PARTITION_MANAGER) -#include -#endif - - -#define AVG_CNT 30 -#define PEAK_CNT 5 -#define BUS_WIDTH 16 -#define BO_MAX_PRIO 2 - -struct bufinfo { - struct list_head list; - struct dma_buf *dmabuf; - struct sg_table *sgt; - struct dma_buf_attachment *attachment; - size_t size; - off_t offset; - int fd; - dma_addr_t iova; -}; - -struct bigo_opp { - struct list_head list; - u32 freq_khz; - u32 load_pps; -}; - -struct bigo_bw { - struct list_head list; - u32 load_pps; - u32 rd_bw; - u32 wr_bw; - u32 pk_bw; -}; - -struct power_manager { - int bwindex; - struct exynos_pm_qos_request qos_bigo; - struct list_head opps; - struct list_head bw; - u32 max_load; -}; - -struct slc_manager { -#if IS_ENABLED(CONFIG_SLC_PARTITION_MANAGER) - struct pt_handle *pt_hnd; - ptid_t pid; -#endif - void __iomem *ssmt_pid_base; - size_t size; -}; - -struct bigo_job { - struct list_head list; - void *regs; - size_t regs_size; - int status; -}; - -struct bigo_debugfs { - struct dentry *root; - u32 set_freq; - u32 trigger_ssr; -}; - -struct bigo_prio_array { - struct mutex lock; - unsigned long bitmap; - struct list_head queue[BO_MAX_PRIO]; -}; - -struct bigo_core { - struct class *_class; - struct cdev cdev; - struct device *svc_dev; - struct device *dev; - dev_t devno; - /* mutex protecting this data structure */ - struct mutex lock; - void __iomem *base; - int irq; - struct completion frame_done; - struct list_head instances; - struct ion_client *mem_client; - u32 stat_with_irq; - struct power_manager pm; - struct slc_manager slc; - unsigned int regs_size; - struct bigo_inst *curr_inst; - phys_addr_t paddr; - struct bigo_debugfs debugfs; - spinlock_t status_lock; - struct task_struct *worker_thread; - wait_queue_head_t worker; - struct bigo_prio_array prioq; - u32 qos_dirty; -}; - -struct bigo_inst { - struct list_head list; - struct list_head buffers; - /* mutex protecting this data structure */ - struct mutex lock; - struct kref refcount; - struct bigo_core *core; - u32 height; - u32 width; - u32 fps; - u32 is_secure; - int priority; - struct bigo_bw avg_bw[AVG_CNT]; - struct bigo_bw pk_bw[AVG_CNT]; - int job_cnt; - u32 hw_cycles[AVG_CNT]; - struct completion job_comp; - struct bigo_job job; - bool idle; -}; - -inline void set_curr_inst(struct bigo_core *core, struct bigo_inst *inst); -inline struct bigo_inst *get_curr_inst(struct bigo_core *core); - -#endif //_BIGO_PRIV_H_ diff --git a/drivers/media/platform/bigocean/bigo_slc.c b/drivers/media/platform/bigocean/bigo_slc.c deleted file mode 100644 index 61d8c19e6a81..000000000000 --- a/drivers/media/platform/bigocean/bigo_slc.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * SLC operations for BigOcean - * - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt - -#include -#include - -#include "bigo_slc.h" - -#define SID_S3_TEMPORAL 3 -#define SID_COMP_INFO 6 -#define SID_S4_SECONDARY_COLBUF 19 -#define SID_S4_COMP_TILE_COL 20 -#define SID_S4_CDEC_TILE_COL 21 - -void bigo_bypass_ssmt_pid(struct bigo_core *core) -{ - int sid; - unsigned int offset; - const int cache_off = 0x400; - const int rd_alloc_off = 0x600; - const int wr_alloc_off = 0x800; - - if (!core->slc.ssmt_pid_base) - return; - - for (sid = 0; sid < 32; sid++) { - offset = sid * 4; - if (sid == SID_S3_TEMPORAL || sid == SID_COMP_INFO || - sid == SID_S4_SECONDARY_COLBUF || sid == SID_S4_COMP_TILE_COL || - sid == SID_S4_CDEC_TILE_COL) { - writel(core->slc.pid, core->slc.ssmt_pid_base + offset); - } - writel(0xe, core->slc.ssmt_pid_base + cache_off + offset); - writel(0x80000000, core->slc.ssmt_pid_base + rd_alloc_off + offset); - writel(0x80000000, core->slc.ssmt_pid_base + wr_alloc_off + offset); - } -} - -int bigo_pt_client_enable(struct bigo_core *core) -{ - int rc = 0; - - if (!core->slc.pt_hnd) - return 0; - - core->slc.pid = pt_client_enable_size(core->slc.pt_hnd, 0, &core->slc.size); - if (core->slc.pid < 0) { - pr_warn("Failed to get BO pid\n"); - rc = core->slc.pid; - } - return rc; -} - -void bigo_pt_client_disable(struct bigo_core *core) -{ - if (core->slc.pt_hnd) - pt_client_disable(core->slc.pt_hnd, 0); -} - -void bigo_get_cache_info(struct bigo_core *core, struct bigo_cache_info *cinfo) -{ - cinfo->size = core->slc.size; - cinfo->pid = core->slc.pid; -} - -static void bigo_pt_resize_cb(void *data, int id, size_t size_allocated) -{ - struct bigo_core *core = (struct bigo_core *)data; - - pr_debug("Received SLC resize callback, id: %d, size: %zu\n", id, size_allocated); - core->slc.size = size_allocated; -} - -int bigo_pt_client_register(struct device_node *node, struct bigo_core *core) -{ - int rc = 0; - core->slc.pt_hnd = pt_client_register(node, (void *)core, bigo_pt_resize_cb); - if (IS_ERR(core->slc.pt_hnd)) { - rc = PTR_ERR(core->slc.pt_hnd); - core->slc.pt_hnd = NULL; - pr_warn("Failed to register pt_client.\n"); - return rc; - } - return rc; -} - -void bigo_pt_client_unregister(struct bigo_core *core) -{ - pt_client_unregister(core->slc.pt_hnd); -} - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Vinay Kalia "); diff --git a/drivers/media/platform/bigocean/bigo_slc.h b/drivers/media/platform/bigocean/bigo_slc.h deleted file mode 100644 index 16e41104d6d2..000000000000 --- a/drivers/media/platform/bigocean/bigo_slc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _BIGO_SLC_H_ -#define _BIGO_SLC_H_ - -#include "bigo_priv.h" - -#if IS_ENABLED(CONFIG_SLC_PARTITION_MANAGER) -#include -int bigo_pt_client_register(struct device_node *node, struct bigo_core *core); -void bigo_pt_client_unregister(struct bigo_core *core); -int bigo_pt_client_enable(struct bigo_core *core); -void bigo_pt_client_disable(struct bigo_core *core); -void bigo_get_cache_info(struct bigo_core *core, struct bigo_cache_info *cinfo); -void bigo_bypass_ssmt_pid(struct bigo_core *core); -#else -static inline int bigo_pt_client_register(struct device_node *node, struct bigo_core *core) { } -static inline void bigo_pt_client_unregister(struct bigo_core *core) { } -static inline int bigo_pt_client_enable(struct bigo_core *core) { return -EINVAL; } -static inline void bigo_pt_client_disable(struct bigo_core *core) { } -static inline void bigo_get_cache_info(struct bigo_core *core, struct bigo_cache_info *cinfo) { } -static inline void bigo_bypass_ssmt_pid(struct bigo_core *core) { } -#endif - -#endif //_BIGO_SLC_H_ diff --git a/drivers/media/platform/exynos/mfc/mfc.c b/drivers/media/platform/exynos/mfc/mfc.c index 12cb0fe749a0..cc21dadf409c 100644 --- a/drivers/media/platform/exynos/mfc/mfc.c +++ b/drivers/media/platform/exynos/mfc/mfc.c @@ -943,6 +943,9 @@ static int __mfc_parse_dt(struct device_node *np, struct mfc_dev *mfc) /* MFC IOVA threshold */ of_property_read_u32(np, "idle_clk_ctrl", &pdata->idle_clk_ctrl); + /* Encoder RGB CSC formula by VUI from F/W */ + of_property_read_u32(np, "enc_rgb_csc_by_fw", &pdata->enc_rgb_csc_by_fw); + return 0; } diff --git a/drivers/media/platform/exynos/mfc/mfc_buf.c b/drivers/media/platform/exynos/mfc/mfc_buf.c index 881e13efec4b..979abbc59946 100644 --- a/drivers/media/platform/exynos/mfc/mfc_buf.c +++ b/drivers/media/platform/exynos/mfc/mfc_buf.c @@ -23,6 +23,8 @@ #include "mfc_mem.h" +#include "mfc_utils.h" + static int __mfc_alloc_common_context(struct mfc_core *core, enum mfc_buf_usage_type buf_type) { @@ -81,13 +83,16 @@ int mfc_alloc_common_context(struct mfc_core *core) ret = __mfc_alloc_common_context(core, MFCBUF_NORMAL); if (ret) return ret; + mfc_core_change_fw_state(core, 0, MFC_CTX_ALLOC, 1); #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - if (core->fw.drm_status) { - ret = __mfc_alloc_common_context(core, MFCBUF_DRM); - if (ret) - return ret; + ret = __mfc_alloc_common_context(core, MFCBUF_DRM); + if (ret) { + mfc_core_change_fw_state(core, 0, MFC_CTX_ALLOC, 0); + return ret; } + + mfc_core_change_fw_state(core, 1, MFC_CTX_ALLOC, 1); #endif return ret; @@ -118,9 +123,11 @@ static void __mfc_release_common_context(struct mfc_core *core, void mfc_release_common_context(struct mfc_core *core) { __mfc_release_common_context(core, MFCBUF_NORMAL); + mfc_core_change_fw_state(core, 0, MFC_CTX_ALLOC, 0); #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) __mfc_release_common_context(core, MFCBUF_DRM); + mfc_core_change_fw_state(core, 1, MFC_CTX_ALLOC, 0); #endif } @@ -723,25 +730,19 @@ int mfc_alloc_firmware(struct mfc_core *core) if (mfc_iommu_map_firmware(core, fw_buf)) goto err_reserve_iova; + mfc_core_change_fw_state(core, 0, MFC_FW_ALLOC, 1); MFC_TRACE_CORE("Normal F/W base %pad\n", &core->fw_buf.daddr); mfc_core_info("[MEMINFO][F/W] MFC-%d FW normal: %pad(vaddr: %pK, paddr:%pap), size: %08zu\n", core->id, &core->fw_buf.daddr, core->fw_buf.vaddr, &core->fw_buf.paddr, core->fw_buf.size); #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - core->drm_fw_buf.buftype = MFCBUF_DRM_FW; - core->drm_fw_buf.size = core->fw_buf.size; - if (mfc_mem_special_buf_alloc(dev, &core->drm_fw_buf)) { - mfc_core_err("[F/W] Allocating DRM firmware buffer failed\n"); - goto err_reserve_iova; - } - if (!core->drm_fw_buf.daddr) { - core->drm_fw_buf.daddr = secure_iova_alloc(core->drm_fw_buf.size, - EXYNOS_SECBUF_PROT_ALIGNMENTS); - if (!core->drm_fw_buf.daddr) { - mfc_core_err("DRM F/W buffer can not get IOVA!\n"); - goto err_reserve_iova_secure; + core->drm_fw_buf.buftype = MFCBUF_DRM_FW; + core->drm_fw_buf.size = core->fw_buf.size; + if (mfc_mem_special_buf_alloc(dev, &core->drm_fw_buf)) { + mfc_core_err("[F/W] Allocating DRM firmware buffer failed\n"); + goto err_reserve_iova; } } @@ -752,12 +753,11 @@ int mfc_alloc_firmware(struct mfc_core *core) &core->drm_fw_buf.daddr); mfc_core_err("%s", core->crash_info); MFC_TRACE_CORE("%s", core->crash_info); - secure_iova_free(core->drm_fw_buf.daddr, core->drm_fw_buf.size); - core->drm_fw_buf.daddr = 0; call_dop(core, dump_and_stop_debug_mode, core); goto err_reserve_iova_secure; } + mfc_core_change_fw_state(core, 1, MFC_FW_ALLOC, 1); mfc_core_info("[MEMINFO][F/W] MFC-%d FW DRM: %pad(vaddr: %pK paddr:%pap), size: %08zu\n", core->id, &core->drm_fw_buf.daddr, core->drm_fw_buf.vaddr, &core->drm_fw_buf.paddr, @@ -773,77 +773,75 @@ int mfc_alloc_firmware(struct mfc_core *core) mfc_mem_special_buf_free(dev, &core->drm_fw_buf); #endif err_reserve_iova: + mfc_core_change_fw_state(core, 0, MFC_FW_ALLOC, 0); iommu_unmap(core->domain, fw_buf->daddr, fw_buf->map_size); mfc_mem_special_buf_free(dev, &core->fw_buf); return -ENOMEM; } /* Load firmware to MFC */ -int mfc_load_firmware(struct mfc_core *core, const u8 *fw_data, size_t fw_size) +int mfc_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf, + const u8 *fw_data, size_t fw_size) { - mfc_core_debug(2, "[MEMINFO][F/W] loaded F/W Size: %zu\n", fw_size); + mfc_core_debug(2, "[MEMINFO][F/W] loaded %s F/W Size: %zu\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure", fw_size); - if (fw_size > core->fw_buf.size) { + if (fw_size > fw_buf->size) { mfc_core_err("[MEMINFO][F/W] MFC firmware(%zu) is too big to be loaded in memory(%zu)\n", - fw_size, core->fw_buf.size); + fw_size, fw_buf->size); return -ENOMEM; } core->fw.fw_size = fw_size; - if (core->fw_buf.sgt == NULL || core->fw_buf.daddr == 0) { + if (fw_buf->sgt == NULL || fw_buf->daddr == 0) { mfc_core_err("[F/W] MFC firmware is not allocated or was not mapped correctly\n"); return -EINVAL; } /* This adds to clear with '0' for firmware memory except code region. */ - mfc_core_debug(4, "[F/W] memset before memcpy for normal fw\n"); - memset((core->fw_buf.vaddr + fw_size), 0, (core->fw_buf.size - fw_size)); - memcpy(core->fw_buf.vaddr, fw_data, fw_size); + mfc_core_debug(4, "[F/W] memset before memcpy for %s fw\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); - /* cache flush for memcpy by CPU */ - dma_sync_sgtable_for_device(core->device, core->fw_buf.sgt, DMA_TO_DEVICE); - - if (core->drm_fw_buf.vaddr) { - mfc_core_debug(4, "[F/W] memset before memcpy for secure fw\n"); - memset((core->drm_fw_buf.vaddr + fw_size), 0, (core->drm_fw_buf.size - fw_size)); - memcpy(core->drm_fw_buf.vaddr, fw_data, fw_size); - mfc_core_debug(4, "[F/W] copy firmware to secure region\n"); + /* + * In MFCBUF_DRM_FW case, FW is loaded by LDFW. Morever, memory region + * is protected, i.e. can't be accessed by Linux. + */ + if (fw_buf->buftype == MFCBUF_NORMAL_FW) { + memset((fw_buf->vaddr + fw_size), 0, (fw_buf->size - fw_size)); + memcpy(fw_buf->vaddr, fw_data, fw_size); /* cache flush for memcpy by CPU */ - dma_sync_sgtable_for_device(core->device, core->drm_fw_buf.sgt, DMA_TO_DEVICE); - mfc_core_debug(4, "[F/W] cache flush for secure region\n"); + dma_sync_sgtable_for_device(core->device, fw_buf->sgt, + DMA_TO_DEVICE); } + mfc_core_debug(4, "[F/W] cache flush for %s FW region\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); + + if (fw_buf->buftype == MFCBUF_NORMAL_FW) + mfc_core_change_fw_state(core, 0, MFC_FW_LOADED, 1); + else + mfc_core_change_fw_state(core, 1, MFC_FW_LOADED, 1); + return 0; } -/* Request and load firmware to MFC */ -int mfc_request_load_firmware(struct mfc_core *core) +int __mfc_request_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf) { -#if !IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) const struct firmware *fw_blob; -#endif int ret; - mfc_core_debug_enter(); -#if IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) - mfc_core_debug(4, "[F/W] Requesting imgloader boot for F/W\n"); + mfc_core_debug(4, "[F/W] Requesting %s F/W\n", + fw_buf->buftype == MFCBUF_NORMAL_FW ? "normal" : "secure"); - ret = imgloader_boot(&core->mfc_imgloader_desc); - if (ret) { - mfc_core_err("[F/W] imgloader boot failed.\n"); - return -EINVAL; - } -#else - mfc_core_debug(4, "[F/W] Requesting F/W\n"); ret = request_firmware(&fw_blob, MFC_FW_NAME, core->dev->v4l2_dev.dev); if (ret != 0) { mfc_core_err("[F/W] Couldn't find the F/W invalid path\n"); return ret; } - ret = mfc_load_firmware(core, fw_blob->data, fw_blob->size); + ret = mfc_load_firmware(core, fw_buf, fw_blob->data, fw_blob->size); if (ret) { mfc_core_err("[F/W] Failed to load the MFC F/W\n"); release_firmware(fw_blob); @@ -851,8 +849,42 @@ int mfc_request_load_firmware(struct mfc_core *core) } release_firmware(fw_blob); + + return 0; +} + +/* Request and load firmware to MFC */ +int mfc_request_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf) +{ + int ret; + + mfc_core_debug_enter(); + +#if IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) + if (fw_buf->buftype == MFCBUF_NORMAL_FW) { + mfc_core_debug(4, "[F/W] Requesting imgloader boot for F/W\n"); + + ret = imgloader_boot(&core->mfc_imgloader_desc); + if (ret) { + mfc_core_err("[F/W] imgloader boot failed.\n"); + return -EINVAL; + } + /* Imageloader verifies the FW directly after mem_setup() */ + mfc_core_change_fw_state(core, 0, MFC_FW_VERIFIED, 1); + } else if (fw_buf->buftype == MFCBUF_DRM_FW) { + ret = __mfc_request_load_firmware(core, fw_buf); + if (ret) + return ret; + } else { + mfc_core_err("[F/W] not supported FW buftype: %d\n", fw_buf->buftype); + return -EINVAL; + } +#else + ret = __mfc_request_load_firmware(core, fw_buf); + if (ret) + return ret; #endif - trace_mfc_loadfw_end(core->fw_buf.size, core->fw_buf.size); + mfc_core_debug_leave(); return 0; @@ -874,9 +906,6 @@ int mfc_release_firmware(struct mfc_core *core) #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) /* free Secure-DVA region */ - if (core->drm_fw_buf.daddr) - secure_iova_free(core->drm_fw_buf.daddr, core->drm_fw_buf.size); - core->drm_fw_buf.daddr = 0; mfc_mem_special_buf_free(core->dev, &core->drm_fw_buf); #endif diff --git a/drivers/media/platform/exynos/mfc/mfc_buf.h b/drivers/media/platform/exynos/mfc/mfc_buf.h index 9a12c1955313..5c20ab18be78 100644 --- a/drivers/media/platform/exynos/mfc/mfc_buf.h +++ b/drivers/media/platform/exynos/mfc/mfc_buf.h @@ -36,8 +36,9 @@ int mfc_otf_alloc_stream_buf(struct mfc_ctx *ctx); void mfc_otf_release_stream_buf(struct mfc_ctx *ctx); int mfc_alloc_firmware(struct mfc_core *core); -int mfc_load_firmware(struct mfc_core *core, const u8 *fw_data, size_t fw_size); -int mfc_request_load_firmware(struct mfc_core *core); +int mfc_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf, + const u8 *fw_data, size_t fw_size); +int mfc_request_load_firmware(struct mfc_core *core, struct mfc_special_buf *fw_buf); int mfc_release_firmware(struct mfc_core *core); int mfc_alloc_dbg_info_buffer(struct mfc_core *core); diff --git a/drivers/media/platform/exynos/mfc/mfc_common.h b/drivers/media/platform/exynos/mfc/mfc_common.h index 567e83fd759a..2afb38a2d0dd 100644 --- a/drivers/media/platform/exynos/mfc/mfc_common.h +++ b/drivers/media/platform/exynos/mfc/mfc_common.h @@ -18,10 +18,11 @@ #include #include #include +#include #include "mfc_data_struct.h" #include "mfc_regs.h" -#include +#include "mfc_macros.h" #include "mfc_debug.h" #include "mfc_media.h" diff --git a/drivers/media/platform/exynos/mfc/mfc_core.c b/drivers/media/platform/exynos/mfc/mfc_core.c index 85778ae5946a..691ae36d1328 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core.c +++ b/drivers/media/platform/exynos/mfc/mfc_core.c @@ -686,12 +686,14 @@ static int mfc_core_probe(struct platform_device *pdev) goto err_sysmmu_fault_handler; } +#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) /* allocate Secure-DVA region */ + core->drm_fw_buf.buftype = MFCBUF_DRM_FW; core->drm_fw_buf.size = dev->variant->buf_size->firmware_code; - core->drm_fw_buf.daddr = secure_iova_alloc(core->drm_fw_buf.size, - EXYNOS_SECBUF_PROT_ALIGNMENTS); - if (!core->drm_fw_buf.daddr) - mfc_core_err("DRM F/W buffer can not get IOVA!\n"); + if (mfc_mem_special_buf_alloc(dev, &core->drm_fw_buf)) { + mfc_core_err("[F/W] Allocating DRM firmware buffer failed\n"); + } +#endif /* vOTF 1:1 mapping */ core->domain = iommu_get_domain_for_dev(core->device); @@ -744,7 +746,9 @@ static int mfc_core_probe(struct platform_device *pdev) return 0; err_alloc_debug: - secure_iova_free(core->drm_fw_buf.daddr, core->drm_fw_buf.size); +#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) + mfc_mem_special_buf_free(dev, &core->drm_fw_buf); +#endif iommu_unregister_device_fault_handler(&pdev->dev); err_sysmmu_fault_handler: destroy_workqueue(core->butler_wq); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_enc_param.c b/drivers/media/platform/exynos/mfc/mfc_core_enc_param.c index 0086f9257f82..585e78016106 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_enc_param.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_enc_param.c @@ -188,9 +188,15 @@ static int __mfc_get_rgb_format_ctrl(struct mfc_ctx *ctx, struct mfc_enc_params * Return value * 0: ITU-R BT.601 * 1: ITU-R BT.709 + * If Set to 3, use the coefficients of CSC formula determined by firmware + * on COLOR_SPACE and COLOUR_PRIMARIES of E_VIDEO_SIGNAL_TYPE. + * 3: Determined by firmware */ - if (IS_VP9_ENC(ctx)) { + if (ctx->dev->pdata->enc_rgb_csc_by_fw) { + ret = 3; + mfc_debug(2, "[RGB] coefficients of CSC formula using VUI by F/W\n"); + } else if (IS_VP9_ENC(ctx)) { ret = mfc_colorspace_to_rgb_format_ctrl[p->colour_primaries][1]; mfc_debug(2, "[RGB] VP9 color space %d converts to RGB format ctrl %s\n", p->colour_primaries, ret ? "BT.709" : "BT.601"); @@ -204,6 +210,50 @@ static int __mfc_get_rgb_format_ctrl(struct mfc_ctx *ctx, struct mfc_enc_params return ret; } +void __mfc_set_video_signal_type(struct mfc_core *core, struct mfc_ctx *ctx) +{ + struct mfc_dev *dev = ctx->dev; + struct mfc_enc *enc = ctx->enc_priv; + struct mfc_enc_params *p = &enc->params; + unsigned int reg = 0; + + if ((ctx->src_fmt->type & MFC_FMT_RGB) && !dev->pdata->enc_rgb_csc_by_fw) { + /* VIDEO_SIGNAL_TYPE_FLAG */ + mfc_set_bits(reg, 0x1, 31, 0x1); + /* COLOUR_DESCRIPTION_PRESENT_FLAG */ + if (!IS_VP9_ENC(ctx)) + mfc_set_bits(reg, 0x1, 24, 0x1); + } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { + /* VIDEO_SIGNAL_TYPE_FLAG */ + mfc_set_bits(reg, 0x1, 31, 0x1); + /* COLOR_RANGE */ + if (!(ctx->src_fmt->type & MFC_FMT_RGB)) + mfc_set_bits(reg, 0x1, 25, p->color_range); + if (IS_VP9_ENC(ctx)) { + /* COLOR_SPACE: VP9 uses colour_primaries interface for color space */ + mfc_set_bits(reg, 0x1F, 26, p->colour_primaries); + mfc_debug(2, "[HDR] VP9 ENC Color aspect: range(%s), space(%d)\n", + p->color_range ? "Full" : "Limited", p->colour_primaries); + } else { + if ((p->colour_primaries != 0) && (p->transfer_characteristics != 0) && + (p->matrix_coefficients != 3)) { + /* COLOUR_DESCRIPTION_PRESENT_FLAG */ + mfc_set_bits(reg, 0x1, 24, 0x1); + /* COLOUR_PRIMARIES */ + mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); + /* TRANSFER_CHARACTERISTICS */ + mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); + /* MATRIX_COEFFICIENTS */ + mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); + } + mfc_debug(2, "[HDR] ENC VUI Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", + p->color_range ? "Full" : "Limited", p->colour_primaries, + p->transfer_characteristics, p->matrix_coefficients); + } + } + MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); +} + static void __mfc_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) { struct mfc_dev *dev = ctx->dev; @@ -287,7 +337,10 @@ static void __mfc_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) mfc_clear_set_bits(reg, 0x3, 24, 1); else if (ctx->sbwcl_ratio == 75 || ctx->sbwcl_ratio == 80) mfc_clear_set_bits(reg, 0x3, 24, 2); + } else { + mfc_clear_set_bits(reg, 0x3, 24, 0); } + /* GDC-MFC vOTF enable */ mfc_clear_bits(reg, 0x1, 26); if (ctx->gdc_votf && core->has_gdc_votf && core->has_mfc_votf) { @@ -404,6 +457,9 @@ static void __mfc_set_enc_params(struct mfc_core *core, struct mfc_ctx *ctx) mfc_set_bits(reg, 0xFF, 0, p->vbv_buf_size); MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VBV_BUFFER_SIZE); + /* Video signal type */ + __mfc_set_video_signal_type(core, ctx); + mfc_debug_leave(); } @@ -518,7 +574,6 @@ static void __mfc_set_fmo_slice_map_h264(struct mfc_core *core, static void __mfc_set_enc_params_h264(struct mfc_core *core, struct mfc_ctx *ctx) { - struct mfc_dev *dev = ctx->dev; struct mfc_enc *enc = ctx->enc_priv; struct mfc_enc_params *p = &enc->params; struct mfc_h264_enc_params *p_264 = &p->codec.h264; @@ -720,35 +775,6 @@ static void __mfc_set_enc_params_h264(struct mfc_core *core, MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_H264_FRAME_PACKING_SEI_INFO); } - /* Video signal type */ - reg = 0; - if (ctx->src_fmt->type & MFC_FMT_RGB) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); - } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - /* COLOR_RANGE */ - mfc_set_bits(reg, 0x1, 25, p->color_range); - if ((p->colour_primaries != 0) && (p->transfer_characteristics != 0) && - (p->matrix_coefficients != 3)) { - /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); - /* COLOUR_PRIMARIES */ - mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); - /* TRANSFER_CHARACTERISTICS */ - mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); - /* MATRIX_COEFFICIENTS */ - mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); - } - mfc_debug(2, "[HDR] H264 ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", - p->color_range ? "Full" : "Limited", p->colour_primaries, - p->transfer_characteristics, p->matrix_coefficients); - } - MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); - __mfc_set_fmo_slice_map_h264(core, ctx, p_264); mfc_debug_leave(); @@ -1019,7 +1045,6 @@ static void __mfc_enc_check_vp9_profile(struct mfc_ctx *ctx) static void __mfc_set_enc_params_vp9(struct mfc_core *core, struct mfc_ctx *ctx) { - struct mfc_dev *dev = ctx->dev; struct mfc_enc *enc = ctx->enc_priv; struct mfc_enc_params *p = &enc->params; struct mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; @@ -1118,23 +1143,6 @@ static void __mfc_set_enc_params_vp9(struct mfc_core *core, struct mfc_ctx *ctx) mfc_clear_set_bits(reg, 0xFF, 0, p_vp9->rc_min_qp_p); MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_QP_BOUND_PB); - /* Video signal type */ - reg = 0; - if (ctx->src_fmt->type & MFC_FMT_RGB) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - /* COLOR_SPACE: VP9 uses colour_primaries interface for color space */ - mfc_set_bits(reg, 0x1F, 26, p->colour_primaries); - /* COLOR_RANGE */ - mfc_set_bits(reg, 0x1, 25, p->color_range); - mfc_debug(2, "[HDR] VP9 ENC Color aspect: range(%s), space(%d)\n", - p->color_range ? "Full" : "Limited", p->colour_primaries); - } - MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); - mfc_debug_leave(); } @@ -1361,35 +1369,6 @@ static void __mfc_set_enc_params_hevc(struct mfc_core *core, MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_RC_ROI_CTRL); mfc_debug(3, "[ROI] HEVC ROI enable\n"); - /* Video signal type */ - reg = 0; - if (ctx->src_fmt->type & MFC_FMT_RGB) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); - } else if (MFC_FEATURE_SUPPORT(dev, dev->pdata->color_aspect_enc) && p->check_color_range) { - /* VIDEO_SIGNAL_TYPE_FLAG */ - mfc_set_bits(reg, 0x1, 31, 0x1); - /* COLOR_RANGE */ - mfc_set_bits(reg, 0x1, 25, p->color_range); - if ((p->colour_primaries != 0) && (p->transfer_characteristics != 0) && - (p->matrix_coefficients != 3)) { - /* COLOUR_DESCRIPTION_PRESENT_FLAG */ - mfc_set_bits(reg, 0x1, 24, 0x1); - /* COLOUR_PRIMARIES */ - mfc_set_bits(reg, 0xFF, 16, p->colour_primaries); - /* TRANSFER_CHARACTERISTICS */ - mfc_set_bits(reg, 0xFF, 8, p->transfer_characteristics); - /* MATRIX_COEFFICIENTS */ - mfc_set_bits(reg, 0xFF, 0, p->matrix_coefficients); - } - mfc_debug(2, "[HDR] HEVC ENC Color aspect: range(%s), pri(%d), trans(%d), mat(%d)\n", - p->color_range ? "Full" : "Limited", p->colour_primaries, - p->transfer_characteristics, p->matrix_coefficients); - } - MFC_CORE_RAW_WRITEL(reg, MFC_REG_E_VIDEO_SIGNAL_TYPE); - if (MFC_FEATURE_SUPPORT(dev, dev->pdata->static_info_enc) && p->static_info_enable && ctx->is_10bit) { reg = MFC_CORE_RAW_READL(MFC_REG_E_HEVC_OPTIONS_2); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_hw_reg_api.h b/drivers/media/platform/exynos/mfc/mfc_core_hw_reg_api.h index e4e3c20fe83e..4f358d0c8be8 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_hw_reg_api.h +++ b/drivers/media/platform/exynos/mfc/mfc_core_hw_reg_api.h @@ -147,8 +147,8 @@ static inline void mfc_core_risc_on(struct mfc_core *core) { mfc_core_clean_dev_int_flags(core); - MFC_CORE_WRITEL(0x1, MFC_REG_RISC_ON); MFC_CORE_WRITEL(0x0, MFC_REG_MFC_OFF); + MFC_CORE_WRITEL(0x1, MFC_REG_RISC_ON); mfc_core_debug(1, "RISC_ON\n"); MFC_TRACE_CORE(">> RISC ON\n"); } diff --git a/drivers/media/platform/exynos/mfc/mfc_core_hwlock.c b/drivers/media/platform/exynos/mfc/mfc_core_hwlock.c index 5cc025585a07..5caba557830d 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_hwlock.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_hwlock.c @@ -611,22 +611,45 @@ void mfc_core_cleanup_work_bit_and_try_run(struct mfc_core_ctx *core_ctx) } void mfc_core_cache_flush(struct mfc_core *core, int is_drm, - enum mfc_do_cache_flush do_cache_flush, int drm_switch) + enum mfc_do_cache_flush do_cache_flush, int drm_switch, int reg_clear) { + enum mfc_fw_status fw_status; + + /* + * Even if it is determined that the attribute of the previous instance + * and the current instance have been changed, (= drm_switch) + * there is no need to cache flush if the F/W of the previous instance is unloaded. + */ + if (drm_switch) { + if (is_drm) + fw_status = core->fw.status; + else + fw_status = core->fw.drm_status; + + if (!(fw_status & MFC_FW_LOADED)) { + mfc_core_debug(2, "F/W has already un-loaded\n"); + do_cache_flush = MFC_NO_CACHEFLUSH; + } + } + if (do_cache_flush == MFC_CACHEFLUSH) { mfc_core_cmd_cache_flush(core); - if (mfc_wait_for_done_core(core, - MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { + if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { mfc_core_err("Failed to CACHE_FLUSH\n"); - core->logging_data->cause |= - (1 << MFC_CAUSE_FAIL_CACHE_FLUSH); + core->logging_data->cause |= (1 << MFC_CAUSE_FAIL_CACHE_FLUSH); call_dop(core, dump_and_stop_always, core); } } else if (do_cache_flush == MFC_NO_CACHEFLUSH) { mfc_core_debug(2, "F/W has already done cache flush with prediction\n"); } - core->curr_core_ctx_is_drm = is_drm; + /* When init_hw(), reg_clear is required between cache flush and (un)protection */ + if (reg_clear) { + mfc_core_reg_clear(core); + mfc_core_debug(2, "Done register clear\n"); + } + + mfc_core_change_attribute(core, is_drm); /* drm_switch may not occur when cache flush is required during migration. */ if (!drm_switch) @@ -638,7 +661,7 @@ void mfc_core_cache_flush(struct mfc_core *core, int is_drm, mfc_core_protection_on(core); } else { MFC_TRACE_CORE("DRM -> Normal\n"); - mfc_core_debug(2, "Normal -> DRM\n"); + mfc_core_debug(2, "DRM -> Normal need un-protection\n"); mfc_core_protection_off(core); } } @@ -668,7 +691,8 @@ static int __mfc_nal_q_just_run(struct mfc_core *core, struct mfc_core_ctx *core /* enable NAL QUEUE */ if (drm_switch) - mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, drm_switch); + mfc_core_cache_flush( + core, ctx->is_drm, MFC_CACHEFLUSH, drm_switch, 0); mfc_ctx_info("[NALQ] start NAL QUEUE\n"); mfc_core_nal_q_start(core, nal_q_handle); @@ -899,7 +923,7 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) if (core->curr_core_ctx_is_drm != ctx->is_drm) drm_switch = 1; else - core->curr_core_ctx_is_drm = ctx->is_drm; + mfc_core_change_attribute(core, ctx->is_drm); mfc_debug(2, "drm_switch = %d, is_drm = %d\n", drm_switch, ctx->is_drm); @@ -926,7 +950,7 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) if (!MFC_FEATURE_SUPPORT(dev, dev->pdata->drm_switch_predict) || drm_predict_disable) { if (drm_switch) - mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, drm_switch); + mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, drm_switch, 0); } else { /* If Normal <-> Secure switch, check if cache flush was done */ if (drm_switch) { @@ -936,7 +960,7 @@ int mfc_core_just_run(struct mfc_core *core, int new_ctx_index) mfc_core_cache_flush(core, ctx->is_drm, core->last_cmd_has_cache_flush ? MFC_NO_CACHEFLUSH : MFC_CACHEFLUSH, - drm_switch); + drm_switch, 0); } /* diff --git a/drivers/media/platform/exynos/mfc/mfc_core_hwlock.h b/drivers/media/platform/exynos/mfc/mfc_core_hwlock.h index 0801bf456018..0d45fe741358 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_hwlock.h +++ b/drivers/media/platform/exynos/mfc/mfc_core_hwlock.h @@ -79,7 +79,7 @@ void mfc_core_move_hwlock_ctx(struct mfc_core *to_core, struct mfc_core *from_co void mfc_core_try_run(struct mfc_core *core); void mfc_core_cleanup_work_bit_and_try_run(struct mfc_core_ctx *core_ctx); void mfc_core_cache_flush(struct mfc_core *core, int is_drm, - enum mfc_do_cache_flush do_cache_flush, int drm_switch); + enum mfc_do_cache_flush do_cache_flush, int drm_switch, int reg_clear); int mfc_core_just_run(struct mfc_core *core, int new_ctx_index); void mfc_core_hwlock_handler_irq(struct mfc_core *core, struct mfc_ctx *ctx, unsigned int reason, unsigned int err); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_isr.c b/drivers/media/platform/exynos/mfc/mfc_core_isr.c index a213f201f3fc..d78d3162a05e 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_isr.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_isr.c @@ -449,6 +449,11 @@ static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, mfc_debug(2, "[QoS] framerate changed\n"); } + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_MULTIFRAME); + mfc_debug(2, "[MULTIFRAME] multiframe detected\n"); + } + if (ctx->dst_fmt->mem_planes == 1) { vb2_set_plane_payload(&dst_mb->vb.vb2_buf, 0, raw->total_plane_size); @@ -460,6 +465,7 @@ static struct mfc_buf *__mfc_handle_frame_output_del(struct mfc_core *core, raw->plane_size[i]); } } + dst_mb->vb.flags &= ~(V4L2_BUF_FLAG_KEYFRAME | V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | @@ -848,11 +854,14 @@ static void __mfc_handle_frame_input(struct mfc_core *core, &ctx->src_ctrls[index]) < 0) mfc_err("failed in core_recover_buf_ctrls_val\n"); - dec->consumed = 0; - dec->remained_size = 0; - mfc_clear_mb_flag(src_mb); + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe && + (mfc_core_get_disp_status() == MFC_REG_DEC_STATUS_DECODING_ONLY)) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[STREAM][MULTIFRAME] last frame is decoding only\n"); + } + /* * VP8 decoder has decoding only frame, * it will be used for reference frame only not displayed. @@ -897,6 +906,11 @@ static void __mfc_handle_frame_input(struct mfc_core *core, &ctx->src_ctrls[index]) < 0) mfc_err("failed in core_get_buf_ctrls_val\n"); + dec->consumed = 0; + if (IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) + dec->has_multiframe = 0; + dec->remained_size = 0; + vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); } @@ -1031,6 +1045,10 @@ static void __mfc_handle_frame(struct mfc_core *core, struct mfc_ctx *ctx, __mfc_handle_frame_copy_timestamp(core_ctx, mfc_core_get_dec_y_addr()); + /* Mark source buffer as complete */ + if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) + __mfc_handle_frame_input(core, ctx, err); + /* A frame has been decoded and is in the buffer */ if (mfc_dec_status_display(dst_frame_status)) mfc_buf = __mfc_handle_frame_output(core, ctx, err); @@ -1061,10 +1079,6 @@ static void __mfc_handle_frame(struct mfc_core *core, struct mfc_ctx *ctx, dec->ref_buf[i].fd[0]); } - /* Mark source buffer as complete */ - if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) - __mfc_handle_frame_input(core, ctx, err); - if (regression_option & MFC_TEST_DEC_PER_FRAME) mfc_core_dec_save_regression_result(core); @@ -1334,6 +1348,7 @@ static int __mfc_handle_stream(struct mfc_core *core, struct mfc_ctx *ctx, unsig int slice_type, consumed_only = 0; unsigned int strm_size; unsigned int pic_count; + unsigned int sbwc_err; slice_type = mfc_core_get_enc_slice_type(); strm_size = mfc_core_get_enc_strm_size(); @@ -1369,6 +1384,17 @@ static int __mfc_handle_stream(struct mfc_core *core, struct mfc_ctx *ctx, unsig consumed_only = 1; } + sbwc_err = mfc_core_get_enc_comp_err(); + if (sbwc_err) { + mfc_ctx_err("[SBWC] Compressor error detected (Source: %d, DPB: %d)\n", + (sbwc_err >> 1) & 0x1, sbwc_err & 0x1); + mfc_ctx_err("[SBWC] sbwc: %d, lossy: %d(%d), option: %d, FORMAT: %#x, OPTIONS: %#x\n", + ctx->is_sbwc, ctx->is_sbwc_lossy, + ctx->sbwcl_ratio, enc->sbwc_option, + MFC_CORE_READL(MFC_REG_PIXEL_FORMAT), + MFC_CORE_READL(MFC_REG_E_ENC_OPTIONS)); + } + /* handle source buffer */ __mfc_handle_stream_input(core, ctx, consumed_only); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c b/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c index 199961138135..1f2f5928c54a 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_meerkat.c @@ -378,11 +378,11 @@ void __mfc_core_dump_state(struct mfc_core *core, int curr_ctx) dev_err(core->device, "-----------dumping MFC core info-----------\n"); dev_err(core->device, "has llc:%d, slc: %d, itmon_notified:%d\n", core->has_llc, core->has_slc, core->itmon_notified); - dev_err(core->device, "power:%d, clock:%d, continue_clock_on:%d, num_inst:%d, num_drm_inst:%d, fw_status:%d\n", + dev_err(core->device, "power:%d, clock:%d, continue_clock_on:%d, num_inst:%d, num_drm_inst:%d, fw_status normal: %#x, drm: %#x\n", mfc_core_pm_get_pwr_ref_cnt(core), mfc_core_pm_get_clk_ref_cnt(core), core->continue_clock_on, core->num_inst, - core->num_drm_inst, core->fw.status); + core->num_drm_inst, core->fw.status, core->fw.drm_status); dev_err(core->device, "hwlock bits:%#lx / core:%#lx, curr_ctx:%d (is_drm:%d)," " preempt_ctx:%d, work_bits:%#lx\n", core->hwlock.bits, core->hwlock.dev, diff --git a/drivers/media/platform/exynos/mfc/mfc_core_nal_q.c b/drivers/media/platform/exynos/mfc/mfc_core_nal_q.c index c526f74cba0d..6df4a4987999 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_nal_q.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_nal_q.c @@ -1496,6 +1496,7 @@ static void __mfc_core_nal_q_handle_stream(struct mfc_core *core, struct mfc_cor int slice_type, consumed_only = 0; unsigned int strm_size; unsigned int pic_count; + unsigned int sbwc_err; mfc_debug_enter(); @@ -1515,10 +1516,22 @@ static void __mfc_core_nal_q_handle_stream(struct mfc_core *core, struct mfc_cor ctx->sequence++; if (strm_size == 0) { - mfc_debug(2, "[FRAME] dst buffer is not returned\n"); + mfc_debug(2, "[NALQ][STREAM] dst buffer is not returned\n"); consumed_only = 1; } + sbwc_err = ((pOutStr->NalDoneInfo >> MFC_REG_E_NAL_DONE_INFO_COMP_ERR_SHIFT) + & MFC_REG_E_NAL_DONE_INFO_COMP_ERR_MASK); + if (sbwc_err) { + mfc_ctx_err("[NALQ][SBWC] Compressor error detected (Source: %d, DPB: %d)\n", + (sbwc_err >> 1) & 0x1, sbwc_err & 0x1); + mfc_ctx_err("[SBWC] sbwc: %d, lossy: %d(%d), option: %d, FORMAT: %#x, OPTIONS: %#x\n", + ctx->is_sbwc, ctx->is_sbwc_lossy, + ctx->sbwcl_ratio, enc->sbwc_option, + MFC_CORE_READL(MFC_REG_PIXEL_FORMAT), + MFC_CORE_READL(MFC_REG_E_ENC_OPTIONS)); + } + /* handle input buffer */ __mfc_core_nal_q_handle_stream_input(core_ctx, pOutStr, consumed_only); @@ -1682,6 +1695,8 @@ static void __mfc_core_nal_q_handle_frame_copy_timestamp(struct mfc_ctx *ctx, } dst_mb = mfc_find_buf(ctx, &ctx->dst_buf_nal_queue, dec_y_addr); + if (!dst_mb) + dst_mb = mfc_find_buf(ctx, &ctx->dst_buf_queue, dec_y_addr); if (dst_mb) dst_mb->vb.vb2_buf.timestamp = src_mb->vb.vb2_buf.timestamp; @@ -1893,6 +1908,11 @@ static struct mfc_buf *__mfc_core_nal_q_handle_frame_output_del(struct mfc_core mfc_debug(2, "[NALQ][QoS] framerate changed\n"); } + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe) { + mfc_set_mb_flag(dst_mb, MFC_FLAG_MULTIFRAME); + mfc_debug(2, "[MULTIFRAME] multiframe detected\n"); + } + for (i = 0; i < raw->num_planes; i++) vb2_set_plane_payload(&dst_mb->vb.vb2_buf, i, raw->plane_size[i]); @@ -2158,13 +2178,20 @@ static void __mfc_core_nal_q_handle_frame_input(struct mfc_core *core, struct mf mfc_clear_mb_flag(src_mb); + dst_frame_status = pOutStr->DisplayStatus + & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK; + + if ((IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) && dec->has_multiframe && + (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY)) { + mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); + mfc_debug(2, "[NALQ][STREAM][MULTIFRAME] last frame is decoding only\n"); + } + /* * VP8/VP9 decoder has decoding only frame, * it will be used for reference frame only not displayed. * So, driver inform to user this input has no destination. */ - dst_frame_status = pOutStr->DisplayStatus - & MFC_REG_DISP_STATUS_DISPLAY_STATUS_MASK; if ((IS_VP8_DEC(ctx) || IS_VP9_DEC(ctx)) && (dst_frame_status == MFC_REG_DEC_STATUS_DECODING_ONLY)) { mfc_set_mb_flag(src_mb, MFC_FLAG_CONSUMED_ONLY); @@ -2204,6 +2231,8 @@ static void __mfc_core_nal_q_handle_frame_input(struct mfc_core *core, struct mf mfc_ctx_err("[NALQ] failed in get_buf_ctrls_val\n"); dec->consumed = 0; + if (IS_VP9_DEC(ctx) || IS_AV1_DEC(ctx)) + dec->has_multiframe = 0; dec->remained_size = 0; vb2_buffer_done(&src_mb->vb.vb2_buf, VB2_BUF_STATE_DONE); @@ -2345,6 +2374,13 @@ void __mfc_core_nal_q_handle_frame(struct mfc_core *core, struct mfc_core_ctx *c break; } + /* Mark source buffer as complete */ + if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) + __mfc_core_nal_q_handle_frame_input(core, ctx, err, pOutStr); + else + mfc_debug(2, "[NALQ][DPB] can't support display only in NAL-Q, is_dpb_full: %d\n", + dec->is_dpb_full); + /* A frame has been decoded and is in the buffer */ if (mfc_dec_status_display(dst_frame_status)) mfc_buf = __mfc_core_nal_q_handle_frame_output(core, ctx, pOutStr); @@ -2375,13 +2411,6 @@ void __mfc_core_nal_q_handle_frame(struct mfc_core *core, struct mfc_core_ctx *c dec->ref_buf[i].fd[0]); } - /* Mark source buffer as complete */ - if (dst_frame_status != MFC_REG_DEC_STATUS_DISPLAY_ONLY) - __mfc_core_nal_q_handle_frame_input(core, ctx, err, pOutStr); - else - mfc_debug(2, "[NALQ][DPB] can't support display only in NAL-Q, is_dpb_full: %d\n", - dec->is_dpb_full); - #ifdef CONFIG_MFC_USE_COREDUMP if (sscd_report && (ctx->frame_cnt == 200)) { snprintf(core->crash_info, MFC_CRASH_INFO_LEN, "Manual trgger MFC SSR\n"); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_ops.c b/drivers/media/platform/exynos/mfc/mfc_core_ops.c index 3046ecf64526..9ae9fa5520bf 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_ops.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_ops.c @@ -42,49 +42,13 @@ #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) static int __mfc_core_prot_firmware(struct mfc_core *core, struct mfc_ctx *ctx) { - phys_addr_t protdesc_phys; - dma_addr_t protdesc_daddr; int ret = 0; mfc_core_debug_enter(); if (!core->drm_fw_buf.sgt) { mfc_core_err("DRM F/W buffer is not allocated\n"); - core->fw.drm_status = 0; } else { - core->drm_fw_prot = kzalloc(sizeof(struct buffer_smc_prot_info), GFP_KERNEL); - if (!core->drm_fw_prot) { - mfc_core_err("no memory for drm_fw_prot\n"); - core->fw.drm_status = 0; - return -ENOMEM; - } - - /* Request buffer Secure-DVA set */ - core->drm_fw_prot->chunk_count = core->drm_fw_buf.sgt->orig_nents; - core->drm_fw_prot->dma_addr = core->drm_fw_buf.daddr; - core->drm_fw_prot->protect_id = EXYNOS_SECBUF_VIDEO_FW_PROT_ID; - core->drm_fw_prot->chunk_size = core->drm_fw_buf.size; - core->drm_fw_prot->paddr = core->drm_fw_buf.paddr; - - /* We must cache flush for secure world cache */ - protdesc_phys = virt_to_phys(core->drm_fw_prot); - protdesc_daddr = phys_to_dma(core->dev->cache_op_dev, protdesc_phys); - - dma_sync_single_for_device(core->dev->cache_op_dev, protdesc_daddr, - sizeof(struct buffer_smc_prot_info), DMA_TO_DEVICE); - - ret = exynos_smc(SMC_DRM_PPMP_PROT, protdesc_phys, 0, 0); - if (ret != DRMDRV_OK) { - snprintf(core->crash_info, MFC_CRASH_INFO_LEN, - "failed MFC DRM F/W prot region setting(%#x)\n", ret); - mfc_core_err("%s", core->crash_info); - call_dop(core, dump_and_stop_debug_mode, core); - core->fw.drm_status = 0; - kfree(core->drm_fw_prot); - core->drm_fw_prot = NULL; - return -EACCES; - } - /* Request buffer protection for DRM F/W */ ret = exynos_smc(SMC_DRM_PPMP_MFCFW_PROT, core->drm_fw_buf.daddr, 0, 0); if (ret != DRMDRV_OK) { @@ -92,16 +56,15 @@ static int __mfc_core_prot_firmware(struct mfc_core *core, struct mfc_ctx *ctx) "failed MFC DRM F/W prot(%#x)\n", ret); mfc_core_err("%s", core->crash_info); call_dop(core, dump_and_stop_debug_mode, core); - core->fw.drm_status = 0; kfree(core->drm_fw_prot); core->drm_fw_prot = NULL; return -EACCES; } else { mfc_debug(2, "DRM F/W region protected\n"); - core->fw.drm_status = 1; } } + mfc_core_change_fw_state(core, 1, MFC_FW_VERIFIED, 1); mfc_core_debug_leave(); return 0; @@ -109,17 +72,15 @@ static int __mfc_core_prot_firmware(struct mfc_core *core, struct mfc_ctx *ctx) static void __mfc_core_unprot_firmware(struct mfc_core *core, struct mfc_ctx *ctx) { - phys_addr_t protdesc_phys; int ret = 0; mfc_core_debug_enter(); - if (!core->fw.drm_status) { + if (!(core->fw.drm_status & MFC_FW_VERIFIED)) { mfc_ctx_info("DRM F/W region already unprotected\n"); return; } - core->fw.drm_status = 0; /* Request buffer unprotection for DRM F/W */ ret = exynos_smc(SMC_DRM_PPMP_MFCFW_UNPROT, core->drm_fw_buf.daddr, 0, 0); if (ret != DRMDRV_OK) { @@ -130,18 +91,7 @@ static void __mfc_core_unprot_firmware(struct mfc_core *core, struct mfc_ctx *ct call_dop(core, dump_and_stop_debug_mode, core); } - /* Request buffer Secure-DVA unset */ - protdesc_phys = virt_to_phys(core->drm_fw_prot); - ret = exynos_smc(SMC_DRM_PPMP_UNPROT, protdesc_phys, 0, 0); - if (ret != DRMDRV_OK) { - snprintf(core->crash_info, MFC_CRASH_INFO_LEN, - "failed MFC DRM F/W prot region unset(%#x)\n", ret); - mfc_core_err("%s", core->crash_info); - call_dop(core, dump_and_stop_debug_mode, core); - } - - kfree(core->drm_fw_prot); - core->drm_fw_prot = NULL; + mfc_core_change_fw_state(core, 1, MFC_FW_VERIFIED, 0); mfc_core_debug_leave(); } @@ -167,14 +117,15 @@ int __mfc_verify_fw(struct mfc_core *core, unsigned int fw_id, return -EIO; } + mfc_core_change_fw_state(core, 0, MFC_FW_VERIFIED, 1); + return 0; } #endif -static int __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) +static void __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) { struct mfc_dev *dev = core->dev; - int ret = 0; /* set meerkat timer */ mod_timer(&core->meerkat_timer, jiffies + msecs_to_jiffies(MEERKAT_TICK_INTERVAL)); @@ -183,25 +134,6 @@ static int __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) atomic_set(&core->hw_run_cnt, 0); mfc_core_change_idle_mode(core, MFC_IDLE_MODE_NONE); - ret = mfc_alloc_common_context(core); - if (ret < 0) { - mfc_core_err("Failed to alloc common context\n"); - goto err_common_ctx; - } - - if (dbg_enable) - mfc_alloc_dbg_info_buffer(core); - - core->curr_core_ctx = ctx->num; - core->preempt_core_ctx = MFC_NO_INSTANCE_SET; - core->curr_core_ctx_is_drm = ctx->is_drm; - - ret = mfc_core_run_init_hw(core); - if (ret) { - mfc_core_err("Failed to init mfc h/w\n"); - goto err_hw_init; - } - if (core->has_llc && (core->llc_on_status == 0)) mfc_llc_enable(core); @@ -214,17 +146,15 @@ static int __mfc_core_init(struct mfc_core *core, struct mfc_ctx *ctx) mfc_core_err("[NALQ] Can't create nal q\n"); } - return ret; - -err_hw_init: - mfc_release_common_context(core); + if (perf_boost_mode) + mfc_core_perf_boost_enable(core); -err_common_ctx: - del_timer(&core->meerkat_timer); - del_timer(&core->mfc_idle_timer); + if (!dev->fw_date) + dev->fw_date = core->fw.date; + else if (dev->fw_date > core->fw.date) + dev->fw_date = core->fw.date; - mfc_core_err("failed to init first instance\n"); - return ret; + mfc_perf_init(core); } static int __mfc_wait_close_inst(struct mfc_core *core, struct mfc_ctx *ctx) @@ -299,6 +229,52 @@ static int __mfc_core_deinit(struct mfc_core *core, struct mfc_ctx *ctx) core->num_drm_inst--; core->num_inst--; + /* Last normal instance */ + if (!ctx->is_drm && ((core->num_inst - core->num_drm_inst) == 0)) { + /* + * When if open and close directly without HW operation, + * curr_core_ctx_is_drm can be true by other DRM instance. + * At that time, do not cache flush about DRM firmware. + * This is to cache flush the normal FW that will disappear(un-load) + * for the next DRM operation after normal FW + HW operation. + */ + if (!core->curr_core_ctx_is_drm) { + core->curr_core_ctx = ctx->num; + mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, 0, 0); + } + mfc_core_change_fw_state(core, 0, MFC_FW_INITIALIZED, 0); +#if IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) + imgloader_shutdown(&core->mfc_imgloader_desc); +#else +#if IS_ENABLED(CONFIG_EXYNOS_S2MPU) + mfc_release_verify_fw(core); +#endif +#endif + mfc_core_change_fw_state(core, 0, MFC_FW_LOADED, 0); + } + + /* Last DRM instance */ + if (ctx->is_drm && (core->num_drm_inst == 0)) { + /* + * When if open and close directly without HW operation, + * curr_core_ctx_is_drm can be true by other normal instance. + * At that time, do not cache flush about normal firmware. + * This is to cache flush the DRM FW that will disappear(un-load) + * for the next normal operation after DRM FW + HW operation. + */ + if (core->curr_core_ctx_is_drm) { + core->curr_core_ctx = ctx->num; + mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, 0, 0); + mfc_core_protection_off(core); + } + mfc_core_change_fw_state(core, 1, MFC_FW_INITIALIZED, 0); +#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) + __mfc_core_unprot_firmware(core, ctx); +#endif + mfc_core_change_attribute(core, 0); + mfc_core_change_fw_state(core, 1, MFC_FW_LOADED, 0); + } + if (core->num_inst == 0) { mfc_core_run_deinit_hw(core); @@ -316,12 +292,6 @@ static int __mfc_core_deinit(struct mfc_core *core, struct mfc_ctx *ctx) if (dbg_enable) mfc_release_dbg_info_buffer(core); - mfc_release_common_context(core); - -#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - __mfc_core_unprot_firmware(core, ctx); -#endif - if (core->nal_q_handle) mfc_core_nal_q_destroy(core, core->nal_q_handle); @@ -383,9 +353,10 @@ static int __mfc_force_close_inst(struct mfc_core *core, struct mfc_ctx *ctx) int __mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx) { - struct mfc_dev *dev = core->dev; struct mfc_core_ctx *core_ctx = NULL; int ret = 0; + enum mfc_fw_status fw_status; + struct mfc_special_buf *fw_buf; core->num_inst++; if (ctx->is_drm) @@ -418,61 +389,92 @@ int __mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx) if (core->num_inst == 1) { mfc_debug(2, "it is first instance in to core-%d\n", core->id); - /* Load the FW */ - ret = mfc_request_load_firmware(core); + mfc_core_debug(2, "power on\n"); + ret = mfc_core_pm_power_on(core); + if (ret) { + mfc_core_err("Failed block power on, ret=%d\n", ret); + goto err_power_on; + } + + if (dbg_enable) + mfc_alloc_dbg_info_buffer(core); + } + + /* Load and verify the FW */ + if (ctx->is_drm) { + fw_buf = &core->drm_fw_buf; + fw_status = core->fw.drm_status; + } else { + fw_buf = &core->fw_buf; + fw_status = core->fw.status; + } + + if (!(fw_status & MFC_FW_LOADED)) { + ret = mfc_request_load_firmware(core, fw_buf); if (ret) goto err_fw_load; + } #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) + if (ctx->is_drm && !(fw_status & MFC_FW_VERIFIED)) { ret = __mfc_core_prot_firmware(core, ctx); if (ret) - goto err_fw_load; + goto err_fw_prot; + } #endif #if !IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) - mfc_core_debug(2, "power on\n"); - ret = mfc_core_pm_power_on(core); - if (ret) { - mfc_core_err("Failed block power on, ret=%d\n", ret); - goto err_power_on; - } - #if IS_ENABLED(CONFIG_EXYNOS_S2MPU) + if (!ctx->is_drm && !(fw_status & MFC_FW_VERIFIED)) { ret = __mfc_verify_fw(core, 0, core->fw_buf.paddr, core->fw.fw_size, core->fw_buf.size); if (ret < 0) - goto err_init_core; + goto err_verify_fw; + } #endif #endif - ret = __mfc_core_init(core, ctx); - if (ret) - goto err_init_core; - if (perf_boost_mode) - mfc_core_perf_boost_enable(core); - - if (!dev->fw_date) - dev->fw_date = core->fw.date; - else if (dev->fw_date > core->fw.date) - dev->fw_date = core->fw.date; + if (!(fw_status & MFC_FW_INITIALIZED)) { + core->curr_core_ctx = ctx->num; + core->preempt_core_ctx = MFC_NO_INSTANCE_SET; - mfc_perf_init(core); + ret = mfc_core_run_init_hw(core, ctx->is_drm); + if (ret) + goto err_init_hw; } + if (core->num_inst == 1) + __mfc_core_init(core, ctx); + return 0; -err_init_core: +err_init_hw: #if !IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) - mfc_core_pm_power_off(core); +#if IS_ENABLED(CONFIG_EXYNOS_S2MPU) + mfc_release_verify_fw(core); -err_power_on: +err_verify_fw: +#endif #endif #if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - __mfc_core_unprot_firmware(core, ctx); + if (ctx->is_drm) + __mfc_core_unprot_firmware(core, ctx); + +err_fw_prot: #endif +#if IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) + if (!ctx->is_drm) + imgloader_shutdown(&core->mfc_imgloader_desc); +#endif + mfc_core_change_fw_state(core, ctx->is_drm, MFC_FW_LOADED, 0); err_fw_load: + if (dbg_enable) + mfc_release_dbg_info_buffer(core); + mfc_core_pm_power_off(core); + +err_power_on: core->core_ctx[ctx->num] = 0; kfree(core->core_ctx[ctx->num]); @@ -702,9 +704,23 @@ int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx) return ret; } -int mfc_core_instance_move_to(struct mfc_core *core, struct mfc_ctx *ctx) +void mfc_core_instance_cache_flush(struct mfc_core *core, struct mfc_ctx *ctx) { int drm_switch = 0; + + if (core->curr_core_ctx_is_drm != ctx->is_drm) + drm_switch = 1; + + core->curr_core_ctx = ctx->num; + mfc_core_pm_clock_on(core); + mfc_core_cache_flush(core, ctx->is_drm, + core->last_cmd_has_cache_flush ? MFC_NO_CACHEFLUSH : MFC_CACHEFLUSH, + drm_switch, 0); + mfc_core_pm_clock_off(core); +} + +int mfc_core_instance_move_to(struct mfc_core *core, struct mfc_ctx *ctx) +{ int ret; ret = __mfc_core_instance_init(core, ctx); @@ -715,14 +731,7 @@ int mfc_core_instance_move_to(struct mfc_core *core, struct mfc_ctx *ctx) if (core->num_inst > 1) { mfc_debug(2, "to core-%d already working, send cache_flush only\n", core->id); - - if (core->curr_core_ctx_is_drm != ctx->is_drm) - drm_switch = 1; - - core->curr_core_ctx = ctx->num; - mfc_core_pm_clock_on(core); - mfc_core_cache_flush(core, ctx->is_drm, MFC_CACHEFLUSH, drm_switch); - mfc_core_pm_clock_off(core); + mfc_core_instance_cache_flush(core, ctx); } mfc_ctx_info("to core-%d is ready to move\n", core->id); @@ -1180,7 +1189,7 @@ int mfc_imgloader_mem_setup(struct imgloader_desc *desc, const u8 *fw_data, size mfc_core_debug_enter(); - ret = mfc_load_firmware(core, fw_data, fw_size); + ret = mfc_load_firmware(core, &core->fw_buf, fw_data, fw_size); if (ret) return ret; @@ -1201,14 +1210,18 @@ int mfc_imgloader_verify_fw(struct imgloader_desc *desc, phys_addr_t fw_phys_bas mfc_core_debug_enter(); - mfc_core_debug(2, "power on\n"); - ret = mfc_core_pm_power_on(core); - if (ret) { - mfc_core_err("failed block power on, ret=%d\n", ret); - return ret; + if (!mfc_core_pm_get_pwr_ref_cnt(core)) { + mfc_core_debug(2, "power on\n"); + ret = mfc_core_pm_power_on(core); + if (ret) { + mfc_core_err("failed block power on, ret=%d\n", ret); + return ret; + } } +#if IS_ENABLED(CONFIG_EXYNOS_S2MPU) ret = __mfc_verify_fw(core, desc->fw_id, fw_phys_base, fw_bin_size, fw_mem_size); +#endif if (ret) mfc_core_pm_power_off(core); @@ -1224,11 +1237,13 @@ int mfc_imgloader_blk_pwron(struct imgloader_desc *desc) mfc_core_debug_enter(); - mfc_core_debug(2, "power on\n"); - ret = mfc_core_pm_power_on(core); - if (ret) { - mfc_core_err("Failed %s block power on, ret=%d\n", ret); - return ret; + if (!mfc_core_pm_get_pwr_ref_cnt(core)) { + mfc_core_debug(2, "power on\n"); + ret = mfc_core_pm_power_on(core); + if (ret) { + mfc_core_err("Failed %s block power on, ret=%d\n", ret); + return ret; + } } mfc_core_debug_leave(); @@ -1252,10 +1267,38 @@ int mfc_imgloader_deinit_image(struct imgloader_desc *desc) return 0; } +int mfc_imgloader_shutdown(struct imgloader_desc *desc) +{ + struct mfc_core *core = (struct mfc_core *)desc->dev->driver_data; + + mfc_core_debug(2, "[F/W] release verify fw\n"); + mfc_core_change_fw_state(core, 0, MFC_FW_VERIFIED, 0); + + return 0; +} + struct imgloader_ops mfc_imgloader_ops = { .mem_setup = mfc_imgloader_mem_setup, .verify_fw = mfc_imgloader_verify_fw, .blk_pwron = mfc_imgloader_blk_pwron, .deinit_image = mfc_imgloader_deinit_image, + .shutdown = mfc_imgloader_shutdown, }; + +#else +#if IS_ENABLED(CONFIG_EXYNOS_S2MPU) +int mfc_release_verify_fw(struct mfc_core *core) +{ + struct imgloader_desc *desc; + + /* release the permission for fw region */ + desc = &core->mfc_imgloader_desc; + exynos_release_subsystem_fw_stage2_ap(core->name, desc->fw_id); + mfc_core_change_fw_state(core, 0, MFC_FW_VERIFIED, 0); + + mfc_core_debug(2, "[F/W] release verify fw\n"); + + return 0; +} +#endif #endif diff --git a/drivers/media/platform/exynos/mfc/mfc_core_ops.h b/drivers/media/platform/exynos/mfc/mfc_core_ops.h index dd95b920c340..c679a33fa5bb 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_ops.h +++ b/drivers/media/platform/exynos/mfc/mfc_core_ops.h @@ -14,6 +14,7 @@ int mfc_core_instance_init(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_instance_deinit(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_instance_open(struct mfc_core *core, struct mfc_ctx *ctx); +void mfc_core_instance_cache_flush(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_instance_move_to(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_instance_move_from(struct mfc_core *core, struct mfc_ctx *ctx); void mfc_core_instance_csd_parsing(struct mfc_core *core, struct mfc_ctx *ctx); @@ -23,3 +24,6 @@ void mfc_core_instance_q_flush(struct mfc_core *core, struct mfc_ctx *ctx); void mfc_core_instance_finishing(struct mfc_core *core, struct mfc_ctx *ctx); int mfc_core_request_work(struct mfc_core *core, enum mfc_request_work work, struct mfc_ctx *ctx); +#if !IS_ENABLED(CONFIG_EXYNOS_IMGLOADER) +int mfc_release_verify_fw(struct mfc_core *core); +#endif diff --git a/drivers/media/platform/exynos/mfc/mfc_core_pm.c b/drivers/media/platform/exynos/mfc/mfc_core_pm.c index a7b8be4d21f5..36f1f7999098 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_pm.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_pm.c @@ -25,6 +25,7 @@ void mfc_core_pm_init(struct mfc_core *core) { spin_lock_init(&core->pm.clklock); atomic_set(&core->pm.pwr_ref, 0); + atomic_set(&core->pm.protect_ref, 0); atomic_set(&core->clk_ref, 0); core->pm.device = core->device; @@ -46,6 +47,14 @@ void mfc_core_protection_on(struct mfc_core *core) spin_lock_irqsave(&core->pm.clklock, flags); mfc_core_debug(3, "Begin: enable protection\n"); + + if (atomic_read(&core->pm.protect_ref)) { + mfc_core_err("IP protection is already enabled\n"); + MFC_TRACE_CORE("already protected\n"); + spin_unlock_irqrestore(&core->pm.clklock, flags); + return; + } + ret = exynos_smc(SMC_PROTECTION_SET, 0, core->id * PROT_MFC1, SMC_PROTECTION_ENABLE); if (ret != DRMDRV_OK) { @@ -56,6 +65,8 @@ void mfc_core_protection_on(struct mfc_core *core) spin_unlock_irqrestore(&core->pm.clklock, flags); return; } + + atomic_inc(&core->pm.protect_ref); MFC_TRACE_CORE("protection\n"); mfc_core_debug(3, "End: enable protection\n"); spin_unlock_irqrestore(&core->pm.clklock, flags); @@ -86,6 +97,14 @@ void mfc_core_protection_off(struct mfc_core *core) */ mfc_core_debug(3, "Begin: disable protection\n"); spin_lock_irqsave(&core->pm.clklock, flags); + + if (!atomic_read(&core->pm.protect_ref)) { + mfc_core_err("IP protection is already disabled\n"); + MFC_TRACE_CORE("already un-protected\n"); + spin_unlock_irqrestore(&core->pm.clklock, flags); + return; + } + ret = exynos_smc(SMC_PROTECTION_SET, 0, core->id * PROT_MFC1, SMC_PROTECTION_DISABLE); if (ret != DRMDRV_OK) { @@ -96,6 +115,8 @@ void mfc_core_protection_off(struct mfc_core *core) spin_unlock_irqrestore(&core->pm.clklock, flags); return; } + + atomic_dec(&core->pm.protect_ref); mfc_core_debug(3, "End: disable protection\n"); MFC_TRACE_CORE("un-protection\n"); spin_unlock_irqrestore(&core->pm.clklock, flags); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_reg_api.c b/drivers/media/platform/exynos/mfc/mfc_core_reg_api.c index 4914164c533b..948678aed633 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_reg_api.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_reg_api.c @@ -645,7 +645,7 @@ void mfc_core_set_pixel_format(struct mfc_core *core, struct mfc_ctx *ctx, struct mfc_dev *dev = ctx->dev; unsigned int reg = 0; unsigned int pix_val; - unsigned int sbwc = 0; + unsigned int sbwc = 0, align = 0; if (dev->pdata->P010_decoding) ctx->mem_type_10bit = 1; @@ -713,13 +713,17 @@ void mfc_core_set_pixel_format(struct mfc_core *core, struct mfc_ctx *ctx, case V4L2_PIX_FMT_NV12N_SBWC_8B: case V4L2_PIX_FMT_NV12M_SBWCL_8B: case V4L2_PIX_FMT_NV12N_SBWCL_8B: - case V4L2_PIX_FMT_NV12M_SBWC_10B: - case V4L2_PIX_FMT_NV12N_SBWC_10B: case V4L2_PIX_FMT_NV12M_SBWCL_10B: case V4L2_PIX_FMT_NV12N_SBWCL_10B: pix_val = 0; sbwc = 1; break; + case V4L2_PIX_FMT_NV12M_SBWC_10B: + case V4L2_PIX_FMT_NV12N_SBWC_10B: + pix_val = 0; + sbwc = 1; + align = 1; + break; default: pix_val = 0; break; @@ -736,11 +740,12 @@ void mfc_core_set_pixel_format(struct mfc_core *core, struct mfc_ctx *ctx, __mfc_enc_check_sbwc_option(ctx, &sbwc); mfc_set_bits(reg, 0x1, 9, sbwc); + mfc_set_bits(reg, 0x1, 10, align); } MFC_CORE_WRITEL(reg, MFC_REG_PIXEL_FORMAT); - mfc_debug(2, "[FRAME] pix format: %d, mem_type_10bit: %d, sbwc: %d (reg: %#x)\n", - pix_val, ctx->mem_type_10bit, sbwc, reg); + mfc_debug(2, "[FRAME] pix format: %d, mem_type_10bit: %d, sbwc: %d, align: %d,(reg: %#x)\n", + pix_val, ctx->mem_type_10bit, sbwc, align, reg); } void mfc_core_print_hdr_plus_info(struct mfc_core *core, struct mfc_ctx *ctx, diff --git a/drivers/media/platform/exynos/mfc/mfc_core_reg_api.h b/drivers/media/platform/exynos/mfc/mfc_core_reg_api.h index f2bbbf6206ef..9c7bc8130def 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_reg_api.h +++ b/drivers/media/platform/exynos/mfc/mfc_core_reg_api.h @@ -217,6 +217,10 @@ ((MFC_CORE_READL(MFC_REG_E_NAL_DONE_INFO) \ >> MFC_REG_E_NAL_DONE_INFO_IDR_SHIFT) \ & MFC_REG_E_NAL_DONE_INFO_IDR_MASK) +#define mfc_core_get_enc_comp_err() \ + ((MFC_CORE_READL(MFC_REG_E_NAL_DONE_INFO) \ + >> MFC_REG_E_NAL_DONE_INFO_COMP_ERR_SHIFT) \ + & MFC_REG_E_NAL_DONE_INFO_COMP_ERR_MASK) #define mfc_core_get_chroma_format() (MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ & MFC_REG_D_CHROMA_FORMAT_MASK) #define mfc_core_get_color_range() ((MFC_CORE_READL(MFC_REG_D_CHROMA_FORMAT) \ diff --git a/drivers/media/platform/exynos/mfc/mfc_core_run.c b/drivers/media/platform/exynos/mfc/mfc_core_run.c index 1b04975e2bf9..230a8c5c4b2b 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_run.c +++ b/drivers/media/platform/exynos/mfc/mfc_core_run.c @@ -25,37 +25,37 @@ #include "mfc_mem.h" /* Initialize hardware */ -static int __mfc_init_hw(struct mfc_core *core, enum mfc_buf_usage_type buf_type) +int mfc_core_run_init_hw(struct mfc_core *core, int is_drm) { - int fw_ver; + enum mfc_buf_usage_type buf_type; + enum mfc_do_cache_flush do_cache_flush; + int fw_ver, drm_switch; int ret = 0; - int curr_ctx_is_drm_backup; - - mfc_core_debug_enter(); - curr_ctx_is_drm_backup = core->curr_core_ctx_is_drm; - - if (!core->fw_buf.sgt) - return -EINVAL; + if (is_drm) + buf_type = MFCBUF_DRM; + else + buf_type = MFCBUF_NORMAL; - /* At init time, do not call secure API */ - if (buf_type == MFCBUF_NORMAL) - core->curr_core_ctx_is_drm = 0; - else if (buf_type == MFCBUF_DRM) - core->curr_core_ctx_is_drm = 1; + mfc_core_debug(2, "%s F/W initialize start\n", is_drm ? "secure" : "normal"); /* 0. MFC reset */ ret = mfc_core_pm_clock_on(core); if (ret) { mfc_core_err("Failed to enable clock before reset(%d)\n", ret); - core->curr_core_ctx_is_drm = curr_ctx_is_drm_backup; return ret; } - mfc_core_reg_clear(core); - mfc_core_debug(2, "Done register clear\n"); - if (core->curr_core_ctx_is_drm) - mfc_core_protection_on(core); + /* cache flush for previous FW */ + if (core->curr_core_ctx_is_drm != is_drm) { + do_cache_flush = MFC_CACHEFLUSH; + drm_switch = 1; + } else { + do_cache_flush = MFC_NO_CACHEFLUSH; + drm_switch = 0; + } + + mfc_core_cache_flush(core, is_drm, do_cache_flush, drm_switch, 1); mfc_core_reset_mfc(core, buf_type); mfc_core_debug(2, "Done MFC reset\n"); @@ -64,7 +64,7 @@ static int __mfc_init_hw(struct mfc_core *core, enum mfc_buf_usage_type buf_type mfc_core_set_risc_base_addr(core, buf_type); /* 2. Release reset signal to the RISC */ - if (!(core->dev->pdata->security_ctrl && (buf_type == MFCBUF_DRM))) { + if (!(core->dev->pdata->security_ctrl && is_drm)) { mfc_core_risc_on(core); mfc_core_debug(2, "Will now wait for completion of firmware transfer\n"); @@ -100,12 +100,13 @@ static int __mfc_init_hw(struct mfc_core *core, enum mfc_buf_usage_type buf_type if (core->fw.fimv_info != 'D' && core->fw.fimv_info != 'E') core->fw.fimv_info = 'N'; - mfc_core_info("[F/W] MFC v%x, %02xyy %02xmm %02xdd (%c)\n", - core->core_pdata->ip_ver, - mfc_core_get_fw_ver_year(), - mfc_core_get_fw_ver_month(), - mfc_core_get_fw_ver_date(), - core->fw.fimv_info); + mfc_core_info("[F/W] MFC %s v%x, %02xyy %02xmm %02xdd (%c)\n", + is_drm ? "secure" : "normal", + core->core_pdata->ip_ver, + mfc_core_get_fw_ver_year(), + mfc_core_get_fw_ver_month(), + mfc_core_get_fw_ver_date(), + core->fw.fimv_info); core->fw.date = mfc_core_get_fw_ver_all(); /* Check MFC version and F/W version */ @@ -117,46 +118,18 @@ static int __mfc_init_hw(struct mfc_core *core, enum mfc_buf_usage_type buf_type goto err_init_hw; } -#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - mfc_core_cmd_cache_flush(core); - if (mfc_wait_for_done_core(core, MFC_REG_R2H_CMD_CACHE_FLUSH_RET)) { - mfc_core_err("Failed to CACHE_FLUSH\n"); - mfc_core_clean_dev_int_flags(core); - ret = -EIO; - goto err_init_hw; - } - - if (buf_type == MFCBUF_DRM && !curr_ctx_is_drm_backup) { - core->curr_core_ctx_is_drm = curr_ctx_is_drm_backup; - mfc_core_protection_off(core); - } -#endif + if (is_drm) + mfc_core_change_fw_state(core, 1, MFC_FW_INITIALIZED, 1); + else + mfc_core_change_fw_state(core, 0, MFC_FW_INITIALIZED, 1); err_init_hw: mfc_core_pm_clock_off(core); - core->curr_core_ctx_is_drm = curr_ctx_is_drm_backup; mfc_core_debug_leave(); return ret; } -/* Wrapper : Initialize hardware */ -int mfc_core_run_init_hw(struct mfc_core *core) -{ - int ret; - - ret = __mfc_init_hw(core, MFCBUF_NORMAL); - if (ret) - return ret; - -#if IS_ENABLED(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION) - if (core->fw.drm_status) - ret = __mfc_init_hw(core, MFCBUF_DRM); -#endif - - return ret; -} - /* Deinitialize hardware */ void mfc_core_run_deinit_hw(struct mfc_core *core) { @@ -174,9 +147,6 @@ void mfc_core_run_deinit_hw(struct mfc_core *core) mfc_core_pm_clock_off(core); - if (core->curr_core_ctx_is_drm) - mfc_core_protection_off(core); - mfc_core_debug(2, "mfc deinit completed\n"); } @@ -216,7 +186,7 @@ int mfc_core_run_sleep(struct mfc_core *core) mfc_core_pm_clock_on(core); if (drm_switch) - mfc_core_cache_flush(core, core_ctx->is_drm, MFC_CACHEFLUSH, drm_switch); + mfc_core_cache_flush(core, core_ctx->is_drm, MFC_CACHEFLUSH, drm_switch, 0); mfc_core_cmd_sleep(core); diff --git a/drivers/media/platform/exynos/mfc/mfc_core_run.h b/drivers/media/platform/exynos/mfc/mfc_core_run.h index e17280b904f5..c27af89e9513 100644 --- a/drivers/media/platform/exynos/mfc/mfc_core_run.h +++ b/drivers/media/platform/exynos/mfc/mfc_core_run.h @@ -15,7 +15,7 @@ #include "mfc_common.h" -int mfc_core_run_init_hw(struct mfc_core *core); +int mfc_core_run_init_hw(struct mfc_core *core, int is_drm); void mfc_core_run_deinit_hw(struct mfc_core *core); int mfc_core_run_sleep(struct mfc_core *core); diff --git a/drivers/media/platform/exynos/mfc/mfc_data_struct.h b/drivers/media/platform/exynos/mfc/mfc_data_struct.h index 0e4f1deb280a..cddcfccdfb7b 100644 --- a/drivers/media/platform/exynos/mfc/mfc_data_struct.h +++ b/drivers/media/platform/exynos/mfc/mfc_data_struct.h @@ -260,6 +260,7 @@ enum mfc_mb_flag { MFC_FLAG_FRAMERATE_CH = 9, MFC_FLAG_SYNC_FRAME = 10, MFC_FLAG_AV1_FILM_GRAIN = 11, + MFC_FLAG_MULTIFRAME = 12, /* Driver set to user when SRC DQbuf */ MFC_FLAG_CONSUMED_ONLY = 15, /* User set to driver when SRC Qbuf */ @@ -522,6 +523,7 @@ struct mfc_core_lock { struct mfc_pm { struct clk *clock; atomic_t pwr_ref; + atomic_t protect_ref; struct device *device; spinlock_t clklock; @@ -530,12 +532,21 @@ struct mfc_pm { enum mfc_buf_usage_type base_type; }; +enum mfc_fw_status { + MFC_FW_NONE = 0, + MFC_FW_ALLOC = (1 << 0), // 0x1 + MFC_CTX_ALLOC = (1 << 1), // 0x2 + MFC_FW_LOADED = (1 << 2), // 0x4 + MFC_FW_VERIFIED = (1 << 3), // 0x8 + MFC_FW_INITIALIZED = (1 << 4), // 0x10 +}; + struct mfc_fw { - int date; - int fimv_info; - size_t fw_size; - int status; - int drm_status; + int date; + int fimv_info; + size_t fw_size; + enum mfc_fw_status status; + enum mfc_fw_status drm_status; }; struct mfc_ctx_buf_size { @@ -849,6 +860,8 @@ struct mfc_platdata { unsigned int core_balance; unsigned int iova_threshold; unsigned int idle_clk_ctrl; + + unsigned int enc_rgb_csc_by_fw; }; struct mfc_core_platdata { @@ -1246,6 +1259,8 @@ struct mfc_core_ops { struct mfc_ctx *ctx); int (*instance_open)(struct mfc_core *core, struct mfc_ctx *ctx); + int (*instance_cache_flush)(struct mfc_core *core, + struct mfc_ctx *ctx); int (*instance_move_to)(struct mfc_core *core, struct mfc_ctx *ctx); int (*instance_move_from)(struct mfc_core *core, diff --git a/drivers/media/platform/exynos/mfc/mfc_debugfs.c b/drivers/media/platform/exynos/mfc/mfc_debugfs.c index 1f90d8696934..657c8e01e778 100644 --- a/drivers/media/platform/exynos/mfc/mfc_debugfs.c +++ b/drivers/media/platform/exynos/mfc/mfc_debugfs.c @@ -89,9 +89,9 @@ static int __mfc_info_show(struct seq_file *s, void *unused) continue; } seq_printf(s, ">>> MFC core-%d device information\n", j); - seq_printf(s, " [VERSION] H/W: v%x, F/W: %06x(%c), DRV: %d\n", - core->core_pdata->ip_ver, core->fw.date, - core->fw.fimv_info, MFC_DRIVER_INFO); + seq_printf(s, " [VERSION] H/W: v%x, F/W: %06x(%c, normal: %#x, drm: %#x), DRV: %d\n", + core->core_pdata->ip_ver, core->fw.date, core->fw.fimv_info, + core->fw.status, core->fw.drm_status, MFC_DRIVER_INFO); seq_printf(s, " [PM] power: %d, clock: %d, clk_get %s, QoS level: %d\n", mfc_core_pm_get_pwr_ref_cnt(core), mfc_core_pm_get_clk_ref_cnt(core), diff --git a/drivers/media/platform/exynos/mfc/mfc_macros.h b/drivers/media/platform/exynos/mfc/mfc_macros.h new file mode 100644 index 000000000000..45ed3487796b --- /dev/null +++ b/drivers/media/platform/exynos/mfc/mfc_macros.h @@ -0,0 +1,117 @@ +/* + * drivers/media/platform/exynos/mfc/mfc_macros.h + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __MFC_MACROS_H +#define __MFC_MACROS_H __FILE__ + +#define WIDTH_MB(x_size) (((x_size) + 15) / 16) +#define HEIGHT_MB(y_size) (((y_size) + 15) / 16) + +/* + * Note that lcu_width and lcu_height are defined as follows : + * lcu_width = (frame_width + lcu_size - 1)/lcu_size + * lcu_height = (frame_height + lcu_size - 1)/lcu_size. + * (lcu_size is 32(encoder) or 64(decoder)) + * + * Note that ctb_width and ctb_height are defined as follows : + * ctb_width = (frame_width + ctb_size - 1)/ctb_size + * ctb_height = (frame_hegiht + ctb_size - 1)/ctb_size + * (ctb_size is 128(AV1 decoder)) + * + */ +#define DEC_LCU_WIDTH(x_size) (((x_size) + 63) / 64) +#define ENC_LCU_WIDTH(x_size) (((x_size) + 31) / 32) +#define DEC_LCU_HEIGHT(y_size) (((y_size) + 63) / 64) +#define ENC_LCU_HEIGHT(y_size) (((y_size) + 31) / 32) + +#define DEC_CTB_WIDTH(x_size) (((x_size) + 127) / 128) +#define DEC_CTB_HEIGHT(y_size) (((y_size) + 127) / 128) + +#define STREAM_BUF_ALIGN 512 +#define MFC_LINEAR_BUF_SIZE 256 + +#define DEC_STATIC_BUFFER_SIZE 20480 +/* STATIC buffer for AV1 will be aligned by 32 */ +#define DEC_AV1_STATIC_BUFFER_SIZE(x_size, y_size) \ + __ALIGN_UP((440192 + (DEC_LCU_WIDTH(x_size) * DEC_LCU_HEIGHT(y_size) * 8192)), 32) + +#define DEC_MV_SIZE_MB(x, y) (WIDTH_MB(x) * (((HEIGHT_MB(y)+1)/2)*2) * 64 + 1024) +#define DEC_HEVC_MV_SIZE(x, y) (DEC_LCU_WIDTH(x) * DEC_LCU_HEIGHT(y) * 256 + 512) +#define DEC_AV1_MV_SIZE(x, y) ((DEC_CTB_WIDTH(x) * DEC_CTB_HEIGHT(y) * 1536) * 10) + +/* helper macros */ +#ifndef __ALIGN_UP +#define __ALIGN_UP(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) +#endif + +#define ENC_HEVC_LUMA_DPB_10B_SIZE(x, y) \ + ((((x) + 63) / 64) * 64 * (((y) + 31) / 32) * 32 + \ + (((((ENC_LCU_WIDTH(x) * 32 + 3) / 4) + 15) / 16) * 16) * \ + (((y) + 31) / 32) * 32 + 64) +#define ENC_HEVC_CHROMA_DPB_10B_SIZE(x, y) \ + ((((x) + 63) / 64) * 64 * (((y) + 31) / 32) * 32 + \ + (((((ENC_LCU_WIDTH(x) * 32 + 3) / 4) + 15) / 16) * 16) * \ + (((y) + 31) / 32) * 32 + 64) +#define ENC_VP9_LUMA_DPB_10B_SIZE(x, y) \ + (((((x) * 2 + 127) / 128) * 128) * \ + (((y) + 31) / 32) * 32 + 64) +#define ENC_VP9_CHROMA_DPB_10B_SIZE(x, y) \ + (((((x) * 2 + 127) / 128) * 128) * \ + (((y) + 31) / 32) * 32 + 64) +#define ENC_LUMA_DPB_SIZE(x, y) \ + ((((x) + 63) / 64) * 64 * (((y) + 31) / 32) * 32 + 64) +#define ENC_CHROMA_DPB_SIZE(x, y) \ + ((((x) + 63) / 64) * 64 * (((((y) + 31) / 32) * 32) / 2) + 64) + +#define ENC_SBWC_LUMA_8B_SIZE(x, y) \ + ((128 * (((x) + 31) / 32) * ((__ALIGN_UP((y), 32) + 3) / 4)) + 64) +#define ENC_SBWC_LUMA_10B_SIZE(x, y) \ + ((192 * (((x) + 31) / 32) * ((__ALIGN_UP((y), 32) + 3) / 4)) + 64) +#define ENC_SBWC_LUMA_HEADER_SIZE(x, y) \ + (((((((x) + 63) / 64) + 15) / 16) * 16) * \ + ((__ALIGN_UP((y), 32) + 3) / 4) + 256) + +#define ENC_SBWC_CHROMA_8B_SIZE(x, y) \ + ((128 * (((x) + 31) / 32) * (((__ALIGN_UP((y), 32) / 2) + 3) / 4)) + 64) +#define ENC_SBWC_CHROMA_10B_SIZE(x, y) \ + ((192 * (((x) + 31) / 32) * (((__ALIGN_UP((y), 32) / 2) + 3) / 4)) + 64) +#define ENC_SBWC_CHROMA_HEADER_SIZE(x, y) \ + (((((((x) + 63) / 64) + 15) / 16) * 16) * \ + (((__ALIGN_UP((y), 32) / 2) + 3) / 4) + 128) + +#define ENC_SBWC_LUMA_8B_DPB_SIZE(x, y) \ + (ENC_SBWC_LUMA_8B_SIZE(x, y) + ENC_SBWC_LUMA_HEADER_SIZE(x, y)) +#define ENC_SBWC_LUMA_10B_DPB_SIZE(x, y) \ + (ENC_SBWC_LUMA_10B_SIZE(x, y) + ENC_SBWC_LUMA_HEADER_SIZE(x, y)) +#define ENC_SBWC_CHROMA_8B_DPB_SIZE(x, y) \ + (ENC_SBWC_CHROMA_8B_SIZE(x, y) + ENC_SBWC_CHROMA_HEADER_SIZE(x, y)) +#define ENC_SBWC_CHROMA_10B_DPB_SIZE(x, y) \ + (ENC_SBWC_CHROMA_10B_SIZE(x, y) + ENC_SBWC_CHROMA_HEADER_SIZE(x, y)) + +#define ENC_V100_H264_ME_SIZE(x, y) \ + ((((x) + 3) * ((y) + 3) * 8) + \ + (((((x) * (y)) + 63) / 64) * 32) + \ + ((((y) * 64) + 2304) * ((x) + 7) / 8)) +#define ENC_V100_MPEG4_ME_SIZE(x, y) \ + ((((x) + 3) * ((y) + 3) * 8) + \ + (((((x) * (y)) + 127) / 128) * 16) + \ + ((((y) * 64) + 2304) * ((x) + 7) / 8)) +#define ENC_V100_VP8_ME_SIZE(x, y) \ + ((((x) + 3) * ((y) + 3) * 8) + \ + ((((y) * 64) + 2304) * ((x) + 7) / 8)) +#define ENC_V100_VP9_ME_SIZE(x, y) \ + (((((x) * 2) + 3) * (((y) * 2) + 3) * 128) + \ + ((((y) * 256) + 2304) * ((x) + 1) / 2)) +#define ENC_V100_HEVC_ME_SIZE(x, y) \ + ((((x) + 3) * ((y) + 3) * 32) + \ + ((((y) * 128) + 2304) * ((x) + 3) / 4)) +#endif /* __MFC_MACROS_H */ diff --git a/drivers/media/platform/exynos/mfc/mfc_mem.c b/drivers/media/platform/exynos/mfc/mfc_mem.c index 8a17a5c357df..c52900351557 100644 --- a/drivers/media/platform/exynos/mfc/mfc_mem.c +++ b/drivers/media/platform/exynos/mfc/mfc_mem.c @@ -68,86 +68,6 @@ void mfc_mem_cleanup_user_shared_handle(struct mfc_ctx *ctx, handle->fd = -1; } -static int mfc_mem_fw_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf) -{ - struct device_node *rmem_np; - struct reserved_mem *rmem; - struct page *fw_pages; - phys_addr_t fw_paddr; - int ret; - - rmem_np = of_parse_phandle(dev->device->of_node, "memory-region", 0); - if (!rmem_np) { - mfc_dev_err("memory-region node not found"); - goto err_reserved_mem_lookup; - } - - rmem = of_reserved_mem_lookup(rmem_np); - of_node_put(rmem_np); - if (!rmem) { - mfc_dev_err("reserved mem lookup handle not found"); - goto err_reserved_mem_lookup; - } - - special_buf->sgt = kmalloc(sizeof(struct sg_table), GFP_KERNEL); - if (!special_buf->sgt) { - mfc_dev_err("Failed to allocate with kmalloc\n"); - goto err_kmalloc; - } - - ret = sg_alloc_table(special_buf->sgt, 1, GFP_KERNEL); - if (ret) { - mfc_dev_err("Failed to allocate sg_table\n"); - goto err_sg_alloc; - } - - if (special_buf->size > rmem->size - dev->fw_rmem_offset) { - mfc_dev_err("No space left in memory region reserved for firmware\n"); - goto err_no_space; - } - - /* calculate physical address for each MFC F/W */ - fw_paddr = rmem->base + dev->fw_rmem_offset; - fw_pages = phys_to_page(fw_paddr); - sg_set_page(special_buf->sgt->sgl, fw_pages, special_buf->size, 0); - - /* Next physical address for new F/W */ - dev->fw_rmem_offset += special_buf->size; - - /* update physical address to special_buf struct */ - special_buf->paddr = fw_paddr; - - /* get the kernel virtual address */ - special_buf->vaddr = phys_to_virt(special_buf->paddr); - - return 0; - -err_no_space: - sg_free_table(special_buf->sgt); -err_sg_alloc: - kfree(special_buf->sgt); - special_buf->sgt = NULL; -err_kmalloc: -err_reserved_mem_lookup: - return -ENOMEM; - -} - -static void mfc_mem_fw_free(struct mfc_dev *dev, struct mfc_special_buf *special_buf) -{ - if (dev->fw_rmem_offset >= special_buf->size) - dev->fw_rmem_offset -= special_buf->size; - - if (special_buf->sgt) { - sg_free_table(special_buf->sgt); - kfree(special_buf->sgt); - } - special_buf->sgt = NULL; - special_buf->dma_buf = NULL; - special_buf->attachment = NULL; - special_buf->vaddr = NULL; -} - static int mfc_mem_dma_heap_alloc(struct mfc_dev *dev, struct mfc_special_buf *special_buf) { @@ -155,6 +75,9 @@ static int mfc_mem_dma_heap_alloc(struct mfc_dev *dev, const char *heapname; switch (special_buf->buftype) { + case MFCBUF_DRM_FW: + heapname = "mfc_fw-secure"; + break; case MFCBUF_NORMAL_FW: case MFCBUF_NORMAL: heapname = "system-uncached"; @@ -205,7 +128,9 @@ static int mfc_mem_dma_heap_alloc(struct mfc_dev *dev, goto err_daddr; } - if (special_buf->buftype != MFCBUF_DRM) { + /* Can't map secure memory */ + if ((special_buf->buftype != MFCBUF_DRM) && + (special_buf->buftype != MFCBUF_DRM_FW)) { special_buf->vaddr = dma_buf_vmap(special_buf->dma_buf); if (IS_ERR(special_buf->vaddr)) { mfc_dev_err("Failed to get vaddr (err 0x%p)\n", @@ -265,8 +190,6 @@ int mfc_mem_special_buf_alloc(struct mfc_dev *dev, switch (special_buf->buftype) { case MFCBUF_DRM_FW: - ret = mfc_mem_fw_alloc(dev, special_buf); - break; case MFCBUF_NORMAL_FW: case MFCBUF_DRM: case MFCBUF_NORMAL: @@ -284,8 +207,6 @@ void mfc_mem_special_buf_free(struct mfc_dev *dev, struct mfc_special_buf *speci { switch (special_buf->buftype) { case MFCBUF_DRM_FW: - mfc_mem_fw_free(dev, special_buf); - break; case MFCBUF_NORMAL_FW: case MFCBUF_DRM: case MFCBUF_NORMAL: diff --git a/drivers/media/platform/exynos/mfc/mfc_regs.h b/drivers/media/platform/exynos/mfc/mfc_regs.h index 96ccb14a2887..4919af3b9f80 100644 --- a/drivers/media/platform/exynos/mfc/mfc_regs.h +++ b/drivers/media/platform/exynos/mfc/mfc_regs.h @@ -959,6 +959,8 @@ #define MFC_REG_E_SLICE_TYPE_SKIPPED 4 /* 0xFAEC: MFC_REG_E_NAL_DONE_INFO */ +#define MFC_REG_E_NAL_DONE_INFO_COMP_ERR_MASK 0x3 +#define MFC_REG_E_NAL_DONE_INFO_COMP_ERR_SHIFT 7 #define MFC_REG_E_NAL_DONE_INFO_IDR_MASK 0x1 #define MFC_REG_E_NAL_DONE_INFO_IDR_SHIFT 20 diff --git a/drivers/media/platform/exynos/mfc/mfc_rm.c b/drivers/media/platform/exynos/mfc/mfc_rm.c index 9271f56de5c2..84a1676e5a26 100644 --- a/drivers/media/platform/exynos/mfc/mfc_rm.c +++ b/drivers/media/platform/exynos/mfc/mfc_rm.c @@ -15,7 +15,6 @@ #include "mfc_core_hwlock.h" #include "mfc_core_qos.h" -#include "mfc_core_pm.h" #include "mfc_core_reg_api.h" #include "mfc_buf.h" @@ -551,6 +550,17 @@ static void __mfc_rm_guarantee_init_buf(struct mfc_ctx *ctx) return; } + /* + * If Normal <-> Secure switch, + * subcore core need to cache flush without other command. + */ + if (IS_TWO_MODE1(ctx)) { + if (subcore->curr_core_ctx_is_drm != ctx->is_drm) { + mfc_debug(2, "[RM] subcore need to cache flush for op_mode 1\n"); + subcore->core_ops->instance_cache_flush(subcore, ctx); + } + } + MFC_TRACE_RM("[c:%d] mode2 try INIT_BUFFER\n", ctx->num); mfc_debug(3, "[RM] mode2 try INIT_BUFFER\n"); ret = maincore->core_ops->instance_init_buf(maincore, ctx); @@ -954,11 +964,16 @@ int mfc_rm_instance_init(struct mfc_dev *dev, struct mfc_ctx *ctx) continue; } - if (!core->fw.status) { + if (!(core->fw.status & MFC_FW_ALLOC)) { ret = mfc_alloc_firmware(core); if (ret) goto err_inst_init; - core->fw.status = 1; + } + + if (!(core->fw.status & MFC_CTX_ALLOC)) { + ret = mfc_alloc_common_context(core); + if (ret) + goto err_inst_init; } } diff --git a/drivers/media/platform/exynos/mfc/mfc_utils.h b/drivers/media/platform/exynos/mfc/mfc_utils.h index ebe195bea4b8..ae217e9413d0 100644 --- a/drivers/media/platform/exynos/mfc/mfc_utils.h +++ b/drivers/media/platform/exynos/mfc/mfc_utils.h @@ -59,6 +59,43 @@ static inline void mfc_core_change_state(struct mfc_core *core, enum mfc_core_st core->state = state; } +static inline void mfc_core_change_attribute(struct mfc_core *core, int is_drm) +{ + MFC_TRACE_CORE("** ctx_is_drm %d -> %d\n", + core->curr_core_ctx_is_drm, is_drm); + mfc_core_debug(3, "curr_core_ctx_is_drm %d -> %d\n", + core->curr_core_ctx_is_drm, is_drm); + core->curr_core_ctx_is_drm = is_drm; +} + +static inline void mfc_core_change_fw_state(struct mfc_core *core, int is_drm, + enum mfc_fw_status state, int set) +{ + enum mfc_fw_status prev_stat; + + if (is_drm) { + prev_stat = core->fw.drm_status; + if (set) + core->fw.drm_status |= state; + else + core->fw.drm_status &= ~state; + MFC_TRACE_CORE("** DRM FW status %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.drm_status, set ? "set" : "clear", state); + mfc_core_debug(2, "[F/W] DRM status: %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.drm_status, set ? "set" : "clear", state); + } else { + prev_stat = core->fw.status; + if (set) + core->fw.status |= state; + else + core->fw.status &= ~state; + MFC_TRACE_CORE("** normal FW status %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.status, set ? "set" : "clear", state); + mfc_core_debug(2, "[F/W] normal status: %#x -> %#x (%s: %#x)\n", + prev_stat, core->fw.status, set ? "set" : "clear", state); + } +} + static inline enum mfc_node_type mfc_get_node_type(struct file *file) { struct video_device *vdev = video_devdata(file); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3773964def9e..8867a5fa09ed 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1188,6 +1188,23 @@ config MFD_S2MPG11 additional drivers must be enabled in order to use the functionality of the device +config MFD_S2MPG12 + tristate "SAMSUNG Electronics S2MPG12 PMIC Series Support" + depends on I2C=y + select MFD_CORE + select REGULATOR + help + Support for the Samsung Electronics MFD series. + This driver provides common support for accessing the device, + additional drivers must be enabled in order to use the functionality + of the device + +config MFD_S2MPG13 + tristate "SAMSUNG Electronics S2MPG13 PMIC Series Support" + depends on I2C=y + select MFD_CORE + select REGULATOR + config MFD_S2MPG1X_GPIO tristate "SAMSUNG Electronics S2MPG1X PMIC GPIO Support" depends on I2C=y @@ -2213,5 +2230,14 @@ config MFD_SLG51000 Say y here to support for the Dialog Semiconductor SLG51000. The SLG51000 is seven compact and customizable low dropout regulators. +config MFD_SLG51002 + tristate "Dialog Semiconductor SLG51002 core driver" + depends on I2C + select MFD_CORE + select REGMAP_I2C + help + Say y here to support for the Dialog Semiconductor SLG51002. + The SLG51002 is eight compact and customizable low dropout regulators. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 5cbe3ab7c0cc..bc7c49d861ef 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -268,10 +268,19 @@ obj-$(CONFIG_MFD_S2MPG10) += s2mpg10-mfd.o s2mpg10-mfd-$(CONFIG_MFD_S2MPG10) += s2mpg10-core.o s2mpg10-irq.o obj-$(CONFIG_MFD_S2MPG11) += s2mpg11-mfd.o s2mpg11-mfd-$(CONFIG_MFD_S2MPG11) += s2mpg11-core.o s2mpg11-irq.o -obj-$(CONFIG_MFD_S2MPG1X_GPIO) += s2mpg1x-gpio.o +ifeq ($(CONFIG_SOC_GS101),y) +obj-$(CONFIG_MFD_S2MPG1X_GPIO) += s2mpg1x-gpio-gs101.o +else +obj-$(CONFIG_MFD_S2MPG1X_GPIO) += s2mpg1x-gpio-gs201.o +endif +obj-$(CONFIG_MFD_S2MPG12) += s2mpg12-mfd.o +s2mpg12-mfd-$(CONFIG_MFD_S2MPG12) += s2mpg12-core.o s2mpg12-irq.o +obj-$(CONFIG_MFD_S2MPG13) += s2mpg13-mfd.o +s2mpg13-mfd-$(CONFIG_MFD_S2MPG13) += s2mpg13-core.o s2mpg13-notifier.o obj-$(CONFIG_SGI_MFD_IOC3) += ioc3.o obj-$(CONFIG_MFD_SIMPLE_MFD_I2C) += simple-mfd-i2c.o obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o obj-$(CONFIG_MFD_SLG51000) += slg51000-core.o +obj-$(CONFIG_MFD_SLG51002) += slg51002-core.o diff --git a/drivers/mfd/s2mpg12-core.c b/drivers/mfd/s2mpg12-core.c new file mode 100644 index 000000000000..f485d679e9f2 --- /dev/null +++ b/drivers/mfd/s2mpg12-core.c @@ -0,0 +1,608 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg12-core.c + * + * Copyright (C) 2016 Samsung Electronics + * + * mfd core driver for the s2mpg12 + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_OF) +#include +#include +#endif /* CONFIG_OF */ + +#define I2C_ADDR_TOP 0x00 +#define I2C_ADDR_PMIC 0x01 +#define I2C_ADDR_RTC 0x02 +#define I2C_ADDR_METER 0x0A +#define I2C_ADDR_WLWP 0x0B +#define I2C_ADDR_GPIO 0x0C +#define I2C_ADDR_MT_TRIM 0x0E +#define I2C_ADDR_TRIM 0x0F + +static struct device_node *acpm_mfd_node; + +static struct mfd_cell s2mpg12_devs[] = { + { + .name = "s2mpg12-regulator", + }, + { + .name = "s2mpg12-rtc", + }, + { + .name = "s2mpg12-meter", + }, + { + .name = "s2mpg12_gpio", + }, + { + .name = "s2mpg12-power-keys", + }, +}; + +static u8 s2mpg12_pmic_rev; + +int s2mpg12_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + u8 channel = 0; + int ret; + + mutex_lock(&s2mpg12->i2c_lock); + ret = exynos_acpm_read_reg(acpm_mfd_node, channel, i2c->addr, + reg, dest); + mutex_unlock(&s2mpg12->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_read_reg); + +int s2mpg12_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + u8 channel = 0; + int ret; + + mutex_lock(&s2mpg12->i2c_lock); + ret = exynos_acpm_bulk_read(acpm_mfd_node, channel, i2c->addr, + reg, count, buf); + mutex_unlock(&s2mpg12->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_bulk_read); + +int s2mpg12_write_reg(struct i2c_client *i2c, u8 reg, u8 value) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + u8 channel = 0; + int ret; + + mutex_lock(&s2mpg12->i2c_lock); + ret = exynos_acpm_write_reg(acpm_mfd_node, channel, + i2c->addr, reg, value); + mutex_unlock(&s2mpg12->i2c_lock); + if (ret) { + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; + } + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_write_reg); + +int s2mpg12_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + u8 channel = 0; + int ret; + + mutex_lock(&s2mpg12->i2c_lock); + ret = exynos_acpm_bulk_write(acpm_mfd_node, channel, + i2c->addr, reg, count, buf); + mutex_unlock(&s2mpg12->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_bulk_write); + +int s2mpg12_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + u8 channel = 0; + int ret; + + mutex_lock(&s2mpg12->i2c_lock); + ret = exynos_acpm_update_reg(acpm_mfd_node, channel, + i2c->addr, reg, val, mask); + mutex_unlock(&s2mpg12->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_update_reg); + +u8 s2mpg12_get_rev_id(void) +{ + return s2mpg12_pmic_rev; +} +EXPORT_SYMBOL_GPL(s2mpg12_get_rev_id); + +struct i2c_client *s2mpg12_get_i2c_client(struct s2mpg12_dev *dev, + unsigned int reg) +{ + struct i2c_client *client = NULL; + + if (reg >> 8 == I2C_ADDR_TOP) + client = dev->i2c; + else if (reg >> 8 == I2C_ADDR_PMIC) + client = dev->pmic; + else if (reg >> 8 == I2C_ADDR_RTC) + client = dev->rtc; + else if (reg >> 8 == I2C_ADDR_METER) + client = dev->meter; + else if (reg >> 8 == I2C_ADDR_GPIO) + client = dev->gpio; + + return client; +} + +int s2mpg12_regmap_read_reg(void *context, unsigned int reg, + unsigned int *dest) +{ + u8 ureg = reg; + u8 *udest = (u8 *)dest; + struct s2mpg12_dev *dev = context; + struct i2c_client *client = s2mpg12_get_i2c_client(dev, reg); + + if (!client) + return -EFAULT; + + *dest = 0; + return s2mpg12_read_reg(client, ureg, udest); +} + +int s2mpg12_regmap_write_reg(void *context, unsigned int reg, + unsigned int value) +{ + u8 ureg = reg; + u8 uvalue = value; + struct s2mpg12_dev *dev = context; + struct i2c_client *client = s2mpg12_get_i2c_client(dev, reg); + + if (!client) + return -EFAULT; + + return s2mpg12_write_reg(client, ureg, uvalue); +} + +static const struct regmap_range s2mpg12_valid_regs[] = { + regmap_reg_range(0x000, 0x003), /* Common Block - VGPIO */ + regmap_reg_range(0x004, 0x029), /* Common Block */ + regmap_reg_range(0x100, 0x1EC), /* Power Management Block */ + regmap_reg_range(0x200, 0x230), /* RTC (real-time clock) */ + regmap_reg_range(0xA00, 0xA5A), /* Meter config */ + regmap_reg_range(0xA63, 0xAD3), /* Meter data */ + regmap_reg_range(0xC05, 0xC10), /* GPIO */ +}; + +static const struct regmap_range s2mpg12_read_only_regs[] = { + regmap_reg_range(0x000, 0x00B), /* Common Block */ + regmap_reg_range(0x020, 0x023), /* Common Block */ + regmap_reg_range(0x027, 0x029), /* Common Block */ + regmap_reg_range(0x100, 0x104), /* INT1~5 */ + regmap_reg_range(0x10A, 0x10B), /* STATUS */ + regmap_reg_range(0xA63, 0xAD3), /* Meter data */ +}; + +const struct regmap_access_table s2mpg12_read_register_set = { + .yes_ranges = s2mpg12_valid_regs, + .n_yes_ranges = ARRAY_SIZE(s2mpg12_valid_regs), +}; + +const struct regmap_access_table s2mpg12_write_register_set = { + .yes_ranges = s2mpg12_valid_regs, + .n_yes_ranges = ARRAY_SIZE(s2mpg12_valid_regs), + .no_ranges = s2mpg12_read_only_regs, + .n_no_ranges = ARRAY_SIZE(s2mpg12_read_only_regs), +}; + +static struct regmap_config s2mpg12_regmap_config = { + .name = "s2mpg12", + .reg_bits = 12, + .val_bits = 8, + .reg_stride = 1, + .max_register = 0xC10, + .reg_read = s2mpg12_regmap_read_reg, + .reg_write = s2mpg12_regmap_write_reg, + .rd_table = &s2mpg12_read_register_set, + .wr_table = &s2mpg12_write_register_set, +}; + +#if IS_ENABLED(CONFIG_OF) +static int of_s2mpg12_dt(struct device *dev, + struct s2mpg12_platform_data *pdata, + struct s2mpg12_dev *s2mpg12) +{ + struct device_node *np = dev->of_node; + int ret; + const char *status; + u32 val; + + if (!np) + return -EINVAL; + + acpm_mfd_node = np; + + status = of_get_property(np, "s2mpg12,wakeup", NULL); + if (!status) + return -EINVAL; + pdata->wakeup = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + /* WTSR, SMPL */ + pdata->wtsr_smpl = + devm_kzalloc(dev, sizeof(*pdata->wtsr_smpl), GFP_KERNEL); + if (!pdata->wtsr_smpl) + return -ENOMEM; + + status = of_get_property(np, "wtsr_en", NULL); + if (!status) + return -EINVAL; + pdata->wtsr_smpl->wtsr_en = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + status = of_get_property(np, "smpl_en", NULL); + if (!status) + return -EINVAL; + pdata->wtsr_smpl->smpl_en = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + ret = of_property_read_u32(np, "wtsr_timer_val", + &pdata->wtsr_smpl->wtsr_timer_val); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "smpl_timer_val", + &pdata->wtsr_smpl->smpl_timer_val); + if (ret) + return -EINVAL; + + status = of_get_property(np, "coldrst_en", NULL); + if (!status) + return -EINVAL; + pdata->wtsr_smpl->coldrst_en = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + ret = of_property_read_u32(np, "coldrst_timer_val", + &pdata->wtsr_smpl->coldrst_timer_val); + if (ret) + return -EINVAL; + + status = of_get_property(np, "sub_smpl_en", NULL); + if (!status) + return -EINVAL; + pdata->wtsr_smpl->sub_smpl_en = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + ret = of_property_read_u32(np, "check_jigon", &val); + if (ret) + return -EINVAL; + pdata->wtsr_smpl->check_jigon = !!val; + + /* init time */ + pdata->init_time = + devm_kzalloc(dev, sizeof(*pdata->init_time), GFP_KERNEL); + if (!pdata->init_time) + return -ENOMEM; + + ret = of_property_read_u32(np, "init_time,sec", + &pdata->init_time->tm_sec); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,min", + &pdata->init_time->tm_min); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,hour", + &pdata->init_time->tm_hour); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,mday", + &pdata->init_time->tm_mday); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,mon", + &pdata->init_time->tm_mon); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,year", + &pdata->init_time->tm_year); + if (ret) + return -EINVAL; + + ret = of_property_read_u32(np, "init_time,wday", + &pdata->init_time->tm_wday); + if (ret) + return -EINVAL; + + /* rtc optimize */ + ret = of_property_read_u32(np, "osc-bias-up", &val); + if (!ret) + pdata->osc_bias_up = val; + else + pdata->osc_bias_up = -1; + + ret = of_property_read_u32(np, "rtc_cap_sel", &val); + if (!ret) + pdata->cap_sel = val; + else + pdata->cap_sel = -1; + + ret = of_property_read_u32(np, "rtc_osc_xin", &val); + if (!ret) + pdata->osc_xin = val; + else + pdata->osc_xin = -1; + + ret = of_property_read_u32(np, "rtc_osc_xout", &val); + if (!ret) + pdata->osc_xout = val; + else + pdata->osc_xout = -1; + + return 0; +} +#else +static int of_s2mpg12_dt(struct device *dev, + struct s2mpg12_platform_data *pdata) +{ + return 0; +} +#endif /* CONFIG_OF */ + +static void s2mpg12_set_rev_id(struct s2mpg12_dev *s2mpg12, int id) +{ + if (id == 0x0 || id == 0x1 || id == 0x2) + s2mpg12->pmic_rev = S2MPG12_EVT0; + else + s2mpg12->pmic_rev = S2MPG12_EVT1; +} + +static int s2mpg12_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *dev_id) +{ + struct s2mpg12_dev *s2mpg12; + struct s2mpg12_platform_data *pdata = i2c->dev.platform_data; + u8 reg_data; + int ret = 0; + + dev_info(&i2c->dev, "%s i2c probe\n", S2MPG12_MFD_DEV_NAME); + + s2mpg12 = kzalloc(sizeof(*s2mpg12), GFP_KERNEL); + if (!s2mpg12) + return -ENOMEM; + + if (i2c->dev.of_node) { + pdata = devm_kzalloc(&i2c->dev, + sizeof(struct s2mpg12_platform_data), + GFP_KERNEL); + if (!pdata) { + ret = -ENOMEM; + goto err; + } + + ret = of_s2mpg12_dt(&i2c->dev, pdata, s2mpg12); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to get device of_node\n"); + goto err; + } + + i2c->dev.platform_data = pdata; + } else { + pdata = i2c->dev.platform_data; + } + + s2mpg12->dev = &i2c->dev; + i2c->addr = I2C_ADDR_TOP; + s2mpg12->i2c = i2c; + s2mpg12->irq = i2c->irq; + s2mpg12->device_type = S2MPG12X; + + if (pdata) { + s2mpg12->pdata = pdata; + + pdata->irq_base = irq_alloc_descs(-1, 0, S2MPG12_IRQ_NR, -1); + if (pdata->irq_base < 0) { + pr_err("%s:%s irq_alloc_descs Fail! ret(%d)\n", + S2MPG12_MFD_DEV_NAME, __func__, pdata->irq_base); + ret = -EINVAL; + goto err; + } else { + s2mpg12->irq_base = pdata->irq_base; + } + + s2mpg12->wakeup = pdata->wakeup; + } else { + ret = -EINVAL; + goto err; + } + mutex_init(&s2mpg12->i2c_lock); + + i2c_set_clientdata(i2c, s2mpg12); + + if (s2mpg12_read_reg(i2c, S2MPG12_COMMON_CHIPID, ®_data) < 0) { + dev_err(s2mpg12->dev, + "device not found on this channel (this is not an error)\n"); + ret = -ENODEV; + goto err_w_lock; + } else { + s2mpg12_set_rev_id(s2mpg12, reg_data & 0x7); + } + + s2mpg12->pmic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_PMIC); + s2mpg12->rtc = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_RTC); + s2mpg12->meter = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_METER); + s2mpg12->wlwp = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_WLWP); + s2mpg12->gpio = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_GPIO); + s2mpg12->mt_trim = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MT_TRIM); + s2mpg12->trim = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_TRIM); + s2mpg12_pmic_rev = s2mpg12->pmic_rev; + + i2c_set_clientdata(s2mpg12->pmic, s2mpg12); + i2c_set_clientdata(s2mpg12->rtc, s2mpg12); + i2c_set_clientdata(s2mpg12->meter, s2mpg12); + i2c_set_clientdata(s2mpg12->wlwp, s2mpg12); + i2c_set_clientdata(s2mpg12->gpio, s2mpg12); + i2c_set_clientdata(s2mpg12->mt_trim, s2mpg12); + i2c_set_clientdata(s2mpg12->trim, s2mpg12); + + pr_info("%s device found: rev.0x%02x\n", __func__, s2mpg12->pmic_rev); + + s2mpg12->regmap = devm_regmap_init(s2mpg12->dev, NULL, s2mpg12, + &s2mpg12_regmap_config); + if (IS_ERR(s2mpg12->regmap)) { + dev_err(s2mpg12->dev, "regmap_init failed!\n"); + ret = PTR_ERR(s2mpg12->regmap); + goto err_w_lock; + } + + ret = s2mpg12_irq_init(s2mpg12); + if (ret < 0) + goto err_irq_init; + + ret = mfd_add_devices(s2mpg12->dev, -1, s2mpg12_devs, + ARRAY_SIZE(s2mpg12_devs), NULL, 0, NULL); + if (ret < 0) + goto err_mfd; + + device_init_wakeup(s2mpg12->dev, pdata->wakeup); + + return ret; + +err_mfd: + mfd_remove_devices(s2mpg12->dev); +err_irq_init: + i2c_unregister_device(s2mpg12->i2c); +err_w_lock: + mutex_destroy(&s2mpg12->i2c_lock); +err: + kfree(s2mpg12); + return ret; +} + +static int s2mpg12_i2c_remove(struct i2c_client *i2c) +{ + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + + mfd_remove_devices(s2mpg12->dev); + i2c_unregister_device(s2mpg12->i2c); + kfree(s2mpg12); + + return 0; +} + +static const struct i2c_device_id s2mpg12_i2c_id[] = { + { S2MPG12_MFD_DEV_NAME, TYPE_S2MPG12 }, {} }; + +MODULE_DEVICE_TABLE(i2c, s2mpg12_i2c_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id s2mpg12_i2c_dt_ids[] = { + { .compatible = "samsung,s2mpg12mfd" }, + {}, +}; +#endif /* CONFIG_OF */ + +#if IS_ENABLED(CONFIG_PM) +static int s2mpg12_suspend(struct device *dev) +{ + struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + + if (device_may_wakeup(dev)) + enable_irq_wake(s2mpg12->irq); + + disable_irq(s2mpg12->irq); + + return 0; +} + +static int s2mpg12_resume(struct device *dev) +{ + struct i2c_client *i2c = container_of(dev, struct i2c_client, dev); + struct s2mpg12_dev *s2mpg12 = i2c_get_clientdata(i2c); + +#if !IS_ENABLED(CONFIG_SAMSUNG_PRODUCT_SHIP) + pr_info("%s:%s\n", S2MPG12_MFD_DEV_NAME, __func__); // it will be removed. +#endif /* CONFIG_SAMSUNG_PRODUCT_SHIP */ + + if (device_may_wakeup(dev)) + disable_irq_wake(s2mpg12->irq); + + enable_irq(s2mpg12->irq); + + return 0; +} +#else +#define s2mpg12_suspend NULL +#define s2mpg12_resume NULL +#endif /* CONFIG_PM */ + +const struct dev_pm_ops s2mpg12_pm = { + .suspend_late = s2mpg12_suspend, + .resume_early = s2mpg12_resume, +}; + +static struct i2c_driver s2mpg12_i2c_driver = { + .driver = { + .name = S2MPG12_MFD_DEV_NAME, + .owner = THIS_MODULE, +#if IS_ENABLED(CONFIG_PM) + .pm = &s2mpg12_pm, +#endif /* CONFIG_PM */ +#if IS_ENABLED(CONFIG_OF) + .of_match_table = s2mpg12_i2c_dt_ids, +#endif /* CONFIG_OF */ + .suppress_bind_attrs = true, + }, + .probe = s2mpg12_i2c_probe, + .remove = s2mpg12_i2c_remove, + .id_table = s2mpg12_i2c_id, +}; + +static int __init s2mpg12_i2c_init(void) +{ + return i2c_add_driver(&s2mpg12_i2c_driver); +} + +/* init early so consumer devices can complete system boot */ +subsys_initcall(s2mpg12_i2c_init); + +static void __exit s2mpg12_i2c_exit(void) +{ + i2c_del_driver(&s2mpg12_i2c_driver); +} + +module_exit(s2mpg12_i2c_exit); + +MODULE_DESCRIPTION("s2mpg12 multi-function core driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/s2mpg12-irq.c b/drivers/mfd/s2mpg12-irq.c new file mode 100644 index 000000000000..44fb527f116b --- /dev/null +++ b/drivers/mfd/s2mpg12-irq.c @@ -0,0 +1,422 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg12-irq.c - Interrupt controller support for S2MPG12 + * + * Copyright (C) 2020 Samsung Electronics Co.Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define S2MPG12_IBI_CNT 4 + +static u8 irq_reg[S2MPG12_IRQ_GROUP_NR] = {0}; + +static const u8 s2mpg12_mask_reg[] = { + /* TODO: Need to check other INTMASK */ + [S2MPG12_IRQS_PMIC_INT1] = S2MPG12_PM_INT1M, + [S2MPG12_IRQS_PMIC_INT2] = S2MPG12_PM_INT2M, + [S2MPG12_IRQS_PMIC_INT3] = S2MPG12_PM_INT3M, + [S2MPG12_IRQS_PMIC_INT4] = S2MPG12_PM_INT4M, + [S2MPG12_IRQS_PMIC_INT5] = S2MPG12_PM_INT5M, + [S2MPG12_IRQS_METER_INT1] = S2MPG12_METER_INT1M, + [S2MPG12_IRQS_METER_INT2] = S2MPG12_METER_INT2M, +}; + +static struct i2c_client *get_i2c(struct s2mpg12_dev *s2mpg12, + enum s2mpg12_irq_source src) +{ + switch (src) { + case S2MPG12_IRQS_PMIC_INT1 ... S2MPG12_IRQS_PMIC_INT5: + return s2mpg12->pmic; + case S2MPG12_IRQS_METER_INT1 ... S2MPG12_IRQS_METER_INT2: + return s2mpg12->meter; + default: + return ERR_PTR(-EINVAL); + } +} + +struct s2mpg12_irq_data { + int mask; + enum s2mpg12_irq_source group; +}; + +#define DECLARE_IRQ(idx, _group, _mask) \ + [(idx)] = { .group = (_group), .mask = (_mask) } + +static const struct s2mpg12_irq_data s2mpg12_irqs[] = { + DECLARE_IRQ(S2MPG12_IRQ_PWRONF_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_PWRONR_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_JIGONBF_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_JIGONBR_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_ACOKBF_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 4), + DECLARE_IRQ(S2MPG12_IRQ_ACOKBR_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 5), + DECLARE_IRQ(S2MPG12_IRQ_PWRON1S_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 6), + DECLARE_IRQ(S2MPG12_IRQ_MRB_INT1, S2MPG12_IRQS_PMIC_INT1, 1 << 7), + + DECLARE_IRQ(S2MPG12_IRQ_RTC60S_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_RTCA1_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_RTCA0_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_RTC1S_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_WTSR_COLDRST_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 4), + DECLARE_IRQ(S2MPG12_IRQ_WTSR_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 5), + DECLARE_IRQ(S2MPG12_IRQ_WRST_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 6), + DECLARE_IRQ(S2MPG12_IRQ_SMPL_INT2, S2MPG12_IRQS_PMIC_INT2, 1 << 7), + + DECLARE_IRQ(S2MPG12_IRQ_120C_INT3, S2MPG12_IRQS_PMIC_INT3, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_140C_INT3, S2MPG12_IRQS_PMIC_INT3, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_TSD_INT3, S2MPG12_IRQS_PMIC_INT3, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_SCL_SOFTRST_INT3, S2MPG12_IRQS_PMIC_INT3, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_WLWP_ACC_INT3, S2MPG12_IRQS_PMIC_INT3, 1 << 7), + + DECLARE_IRQ(S2MPG12_IRQ_OCP_B1M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B2M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B3M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B4M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B5M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 4), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B6M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 5), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B7M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 6), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B8M_INT4, S2MPG12_IRQS_PMIC_INT4, 1 << 7), + + DECLARE_IRQ(S2MPG12_IRQ_OCP_B9M_INT5, S2MPG12_IRQS_PMIC_INT5, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_OCP_B10M_INT5, S2MPG12_IRQS_PMIC_INT5, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_SMPL_TIMEOUT_INT5, S2MPG12_IRQS_PMIC_INT5, 1 << 5), + DECLARE_IRQ(S2MPG12_IRQ_WTSR_TIMEOUT_INT5, S2MPG12_IRQS_PMIC_INT5, 1 << 6), + + DECLARE_IRQ(S2MPG12_IRQ_PMETER_OVERF_INT6, S2MPG12_IRQS_METER_INT1, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH0_INT6, S2MPG12_IRQS_METER_INT1, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH1_INT6, S2MPG12_IRQS_METER_INT1, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH2_INT6, S2MPG12_IRQS_METER_INT1, 1 << 4), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH3_INT6, S2MPG12_IRQS_METER_INT1, 1 << 5), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH4_INT6, S2MPG12_IRQS_METER_INT1, 1 << 6), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH5_INT6, S2MPG12_IRQS_METER_INT1, 1 << 7), + + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH6_INT7, S2MPG12_IRQS_METER_INT2, 1 << 0), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH7_INT7, S2MPG12_IRQS_METER_INT2, 1 << 1), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH8_INT7, S2MPG12_IRQS_METER_INT2, 1 << 2), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH9_INT7, S2MPG12_IRQS_METER_INT2, 1 << 3), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH10_INT7, S2MPG12_IRQS_METER_INT2, 1 << 4), + DECLARE_IRQ(S2MPG12_IRQ_PWR_WARN_CH11_INT7, S2MPG12_IRQS_METER_INT2, 1 << 5), +}; + +static void s2mpg12_irq_lock(struct irq_data *data) +{ + struct s2mpg12_dev *s2mpg12 = irq_get_chip_data(data->irq); + + mutex_lock(&s2mpg12->irqlock); +} + +static void s2mpg12_irq_sync_unlock(struct irq_data *data) +{ + struct s2mpg12_dev *s2mpg12 = irq_get_chip_data(data->irq); + int i; + + for (i = 0; i < S2MPG12_IRQ_GROUP_NR; i++) { + u8 mask_reg = s2mpg12_mask_reg[i]; + struct i2c_client *i2c = get_i2c(s2mpg12, i); + + if (mask_reg == S2MPG12_REG_INVALID || IS_ERR_OR_NULL(i2c)) + continue; + s2mpg12->irq_masks_cache[i] = s2mpg12->irq_masks_cur[i]; + + s2mpg12_write_reg(i2c, s2mpg12_mask_reg[i], + s2mpg12->irq_masks_cur[i]); + } + + mutex_unlock(&s2mpg12->irqlock); +} + +static const inline struct s2mpg12_irq_data * +irq_to_s2mpg12_irq(struct s2mpg12_dev *s2mpg12, int irq) +{ + return &s2mpg12_irqs[irq - s2mpg12->irq_base]; +} + +static void s2mpg12_irq_mask(struct irq_data *data) +{ + struct s2mpg12_dev *s2mpg12 = irq_get_chip_data(data->irq); + const struct s2mpg12_irq_data *irq_data = + irq_to_s2mpg12_irq(s2mpg12, data->irq); + + if (irq_data->group >= S2MPG12_IRQ_GROUP_NR) + return; + + s2mpg12->irq_masks_cur[irq_data->group] |= irq_data->mask; +} + +static void s2mpg12_irq_unmask(struct irq_data *data) +{ + struct s2mpg12_dev *s2mpg12 = irq_get_chip_data(data->irq); + const struct s2mpg12_irq_data *irq_data = + irq_to_s2mpg12_irq(s2mpg12, data->irq); + + if (irq_data->group >= S2MPG12_IRQ_GROUP_NR) + return; + + s2mpg12->irq_masks_cur[irq_data->group] &= ~irq_data->mask; +} + +static struct irq_chip s2mpg12_irq_chip = { + .name = S2MPG12_MFD_DEV_NAME, + .irq_bus_lock = s2mpg12_irq_lock, + .irq_bus_sync_unlock = s2mpg12_irq_sync_unlock, + .irq_mask = s2mpg12_irq_mask, + .irq_unmask = s2mpg12_irq_unmask, +}; + +static void s2mpg12_report_irq(struct s2mpg12_dev *s2mpg12) +{ + int i; + + /* Apply masking */ + for (i = 0; i < S2MPG12_IRQ_GROUP_NR; i++) + irq_reg[i] &= ~s2mpg12->irq_masks_cur[i]; + + /* Report */ + for (i = 0; i < S2MPG12_IRQ_NR; i++) { + if (irq_reg[s2mpg12_irqs[i].group] & s2mpg12_irqs[i].mask) { + handle_nested_irq(s2mpg12->irq_base + i); + log_threaded_irq_wakeup_reason(s2mpg12->irq_base + i, + s2mpg12->irq); + } + } +} + +static int s2mpg12_power_key_detection(struct s2mpg12_dev *s2mpg12) +{ + int ret, i; + u8 val; + + /* Determine falling/rising edge for PWR_ON key */ + if ((irq_reg[S2MPG12_IRQS_PMIC_INT1] & 0x3) != 0x3) + return 0; + + ret = s2mpg12_read_reg(s2mpg12->pmic, S2MPG12_PM_STATUS1, &val); + if (ret) { + pr_err("%s: fail to read register\n", __func__); + return 1; + } + irq_reg[S2MPG12_IRQS_PMIC_INT1] &= 0xFC; + + if (val & S2MPG12_STATUS1_PWRON) { + irq_reg[S2MPG12_IRQS_PMIC_INT1] = S2MPG12_RISING_EDGE; + s2mpg12_report_irq(s2mpg12); + + /* clear irq */ + for (i = 0; i < S2MPG12_IRQ_GROUP_NR; i++) + irq_reg[i] &= 0x00; + + irq_reg[S2MPG12_IRQS_PMIC_INT1] = S2MPG12_FALLING_EDGE; + } else { + irq_reg[S2MPG12_IRQS_PMIC_INT1] = S2MPG12_FALLING_EDGE; + s2mpg12_report_irq(s2mpg12); + + /* clear irq */ + for (i = 0; i < S2MPG12_IRQ_GROUP_NR; i++) + irq_reg[i] &= 0x00; + + irq_reg[S2MPG12_IRQS_PMIC_INT1] = S2MPG12_RISING_EDGE; + } + + return 0; +} + +static void s2mpg12_irq_work_func(struct work_struct *work) +{ + pr_info("%s: main pmic interrupt(0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx)\n", + __func__, irq_reg[S2MPG12_IRQS_PMIC_INT1], irq_reg[S2MPG12_IRQS_PMIC_INT2], + irq_reg[S2MPG12_IRQS_PMIC_INT3], irq_reg[S2MPG12_IRQS_PMIC_INT4], + irq_reg[S2MPG12_IRQS_PMIC_INT5], irq_reg[S2MPG12_IRQS_METER_INT1], + irq_reg[S2MPG12_IRQS_METER_INT2]); +} + +static irqreturn_t s2mpg12_irq_thread(int irq, void *data) +{ + struct s2mpg12_dev *s2mpg12 = data; + u8 ibi_src[S2MPG12_IBI_CNT] = { 0 }; + u32 val; + int i, ret; + + /* Clear interrupt pending bit */ + val = readl(s2mpg12->sysreg_pending); + writel(val, s2mpg12->sysreg_pending); + + /* Read VGPIO_RX_MONITOR */ + val = readl(s2mpg12->mem_base); + + for (i = 0; i < S2MPG12_IBI_CNT; i++) { + ibi_src[i] = val & 0xFF; + val = (val >> 8); + } + + /* notify Main PMIC */ + if (ibi_src[0] & S2MPG12_PMIC_M_MASK) { + /* Read PMIC INT1 ~ INT5 */ + ret = s2mpg12_bulk_read(s2mpg12->pmic, S2MPG12_PM_INT1, + S2MPG12_NUM_IRQ_PMIC_REGS, + &irq_reg[S2MPG12_IRQS_PMIC_INT1]); + if (ret) { + dev_err(s2mpg12->dev, "%s Failed to read pmic interrupt: %d\n", + S2MPG12_MFD_DEV_NAME, ret); + return IRQ_HANDLED; + } + + /* Read METER INT1 ~ INT2 */ + ret = s2mpg12_bulk_read(s2mpg12->meter, S2MPG12_METER_INT1, + S2MPG12_NUM_IRQ_METER_REGS, + &irq_reg[S2MPG12_IRQS_METER_INT1]); + if (ret) { + dev_err(s2mpg12->dev, "%s Failed to read pmic interrupt: %d\n", + S2MPG12_MFD_DEV_NAME, ret); + return IRQ_HANDLED; + } + + queue_delayed_work(s2mpg12->irq_wqueue, &s2mpg12->irq_work, 0); + + /* Power-key W/A */ + ret = s2mpg12_power_key_detection(s2mpg12); + if (ret) + dev_err(s2mpg12->dev, "POWER-KEY detection error\n"); + + /* Report IRQ */ + s2mpg12_report_irq(s2mpg12); + } + + /* notify SUB PMIC */ + if (ibi_src[0] & S2MPG12_PMIC_S_MASK) { + s2mpg13_call_notifier(); + } + + return IRQ_HANDLED; +} + +static int s2mpg12_set_wqueue(struct s2mpg12_dev *s2mpg12) +{ + s2mpg12->irq_wqueue = create_singlethread_workqueue("s2mpg12-wqueue"); + if (!s2mpg12->irq_wqueue) { + pr_err("%s: fail to create workqueue\n", __func__); + return 1; + } + + INIT_DELAYED_WORK(&s2mpg12->irq_work, s2mpg12_irq_work_func); + + return 0; +} + +int s2mpg12_irq_init(struct s2mpg12_dev *s2mpg12) +{ + int i; + int ret; + u8 i2c_data; + int cur_irq; + + if (!s2mpg12->irq_base) { + dev_err(s2mpg12->dev, "No interrupt base specified.\n"); + return 0; + } + + mutex_init(&s2mpg12->irqlock); + + /* Set VGPIO Monitor */ + s2mpg12->mem_base = ioremap(VGPIO_I3C_BASE + VGPIO_MONITOR_ADDR, SZ_32); + if (!s2mpg12->mem_base) + pr_err("%s: fail to allocate VGPIO_MONITOR memory\n", __func__); + + /* Set VGPIO Monitor */ + s2mpg12->sysreg_pending = ioremap(SYSREG_VGPIO2AP + INTC0_IPEND, SZ_32); + if (!s2mpg12->sysreg_pending) + pr_err("%s: fail to allocate INTC0_IPEND memory\n", __func__); + + /* Set workqueue */ + s2mpg12_set_wqueue(s2mpg12); + + /* Mask individual interrupt sources */ + for (i = 0; i < S2MPG12_IRQ_GROUP_NR; i++) { + struct i2c_client *i2c; + + s2mpg12->irq_masks_cur[i] = 0xff; + s2mpg12->irq_masks_cache[i] = 0xff; + + i2c = get_i2c(s2mpg12, i); + + if (IS_ERR_OR_NULL(i2c)) + continue; + if (s2mpg12_mask_reg[i] == S2MPG12_REG_INVALID) + continue; + + s2mpg12_write_reg(i2c, s2mpg12_mask_reg[i], 0xff); + } + + /* Register with genirq */ + for (i = 0; i < S2MPG12_IRQ_NR; i++) { + cur_irq = i + s2mpg12->irq_base; + irq_set_chip_data(cur_irq, s2mpg12); + irq_set_chip_and_handler(cur_irq, &s2mpg12_irq_chip, + handle_level_irq); + irq_set_nested_thread(cur_irq, 1); +#if IS_ENABLED(CONFIG_ARM) + set_irq_flags(cur_irq, IRQF_VALID); +#else + irq_set_noprobe(cur_irq); +#endif + } + + s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_COMMON_IBIM1, 0xff); + /* Unmask s2mpg12 interrupt */ + ret = s2mpg12_read_reg(s2mpg12->i2c, S2MPG12_COMMON_IBIM1, + &i2c_data); + if (ret) { + dev_err(s2mpg12->dev, "%s fail to read intsrc mask reg\n", + S2MPG12_MFD_DEV_NAME); + return ret; + } + + i2c_data &= ~(S2MPG12_IRQSRC_MASK); /* Unmask pmic interrupt */ + s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_COMMON_IBIM1, i2c_data); + + dev_info(s2mpg12->dev, "%s S2MPG12_COMMON_IBIM1=0x%02x\n", + S2MPG12_MFD_DEV_NAME, i2c_data); + + s2mpg12->irq = irq_of_parse_and_map(s2mpg12->dev->of_node, 0); + ret = request_threaded_irq(s2mpg12->irq, NULL, s2mpg12_irq_thread, + IRQF_ONESHOT, + "s2mpg12-irq", s2mpg12); + + if (ret) { + dev_err(s2mpg12->dev, "Failed to request IRQ %d: %d\n", + s2mpg12->irq, ret); + destroy_workqueue(s2mpg12->irq_wqueue); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(s2mpg12_irq_init); + +void s2mpg12_irq_exit(struct s2mpg12_dev *s2mpg12) +{ + if (s2mpg12->irq) + free_irq(s2mpg12->irq, s2mpg12); + + iounmap(s2mpg12->mem_base); + + cancel_delayed_work_sync(&s2mpg12->irq_work); + destroy_workqueue(s2mpg12->irq_wqueue); +} +EXPORT_SYMBOL_GPL(s2mpg12_irq_exit); diff --git a/drivers/mfd/s2mpg13-core.c b/drivers/mfd/s2mpg13-core.c new file mode 100644 index 000000000000..95ca17dd9a8c --- /dev/null +++ b/drivers/mfd/s2mpg13-core.c @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg13.c + * + * Copyright (C) 2016 Samsung Electronics + * + * mfd core driver for the s2mpg13 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_OF) +#include +#include +#endif /* CONFIG_OF */ + +#define I2C_ADDR_TOP 0x00 +#define I2C_ADDR_PMIC 0x01 +#define I2C_ADDR_METER 0x0A +#define I2C_ADDR_WLWP 0x0B +#define I2C_ADDR_GPIO 0x0C +#define I2C_ADDR_MT_TRIM 0x0E +#define I2C_ADDR_TRIM 0x0F + +static struct device_node *acpm_mfd_node; + +static struct mfd_cell s2mpg13_devs[] = { + { + .name = "s2mpg13-regulator", + }, + { + .name = "s2mpg13-meter", + }, + { + .name = "s2mpg13_gpio", + }, + { + .name = "s2mpg13-spmic-thermal", + .of_compatible = "google,s2mpg13-spmic-thermal", + }, +}; + +int s2mpg13_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + u8 channel = 1; + int ret; + + mutex_lock(&s2mpg13->i2c_lock); + ret = exynos_acpm_read_reg(acpm_mfd_node, channel, + i2c->addr, reg, dest); + mutex_unlock(&s2mpg13->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_read_reg); + +int s2mpg13_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + u8 channel = 1; + int ret; + + mutex_lock(&s2mpg13->i2c_lock); + ret = exynos_acpm_bulk_read(acpm_mfd_node, channel, + i2c->addr, reg, count, buf); + mutex_unlock(&s2mpg13->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_bulk_read); + +int s2mpg13_write_reg(struct i2c_client *i2c, u8 reg, u8 value) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + u8 channel = 1; + int ret; + + mutex_lock(&s2mpg13->i2c_lock); + ret = exynos_acpm_write_reg(acpm_mfd_node, channel, + i2c->addr, reg, value); + mutex_unlock(&s2mpg13->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_write_reg); + +int s2mpg13_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + u8 channel = 1; + int ret; + + mutex_lock(&s2mpg13->i2c_lock); + ret = exynos_acpm_bulk_write(acpm_mfd_node, channel, + i2c->addr, reg, count, buf); + mutex_unlock(&s2mpg13->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_bulk_write); + +int s2mpg13_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + u8 channel = 1; + int ret; + + mutex_lock(&s2mpg13->i2c_lock); + ret = exynos_acpm_update_reg(acpm_mfd_node, channel, + i2c->addr, reg, val, mask); + mutex_unlock(&s2mpg13->i2c_lock); + if (ret) + pr_err("[%s] acpm ipc fail!\n", __func__); + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_update_reg); + +struct i2c_client *s2mpg13_get_i2c_client(struct s2mpg13_dev *dev, + unsigned int reg) +{ + struct i2c_client *client = NULL; + + if (reg >> 8 == I2C_ADDR_TOP) + client = dev->i2c; + else if (reg >> 8 == I2C_ADDR_PMIC) + client = dev->pmic; + else if (reg >> 8 == I2C_ADDR_METER) + client = dev->meter; + else if (reg >> 8 == I2C_ADDR_GPIO) + client = dev->gpio; + + return client; +} + +int s2mpg13_regmap_read_reg(void *context, unsigned int reg, + unsigned int *dest) +{ + u8 ureg = reg; + u8 *udest = (u8 *)dest; + struct s2mpg13_dev *dev = context; + struct i2c_client *client = s2mpg13_get_i2c_client(dev, reg); + + if (!client) + return -EFAULT; + + *dest = 0; + return s2mpg13_read_reg(client, ureg, udest); +} + +int s2mpg13_regmap_write_reg(void *context, unsigned int reg, + unsigned int value) +{ + u8 ureg = reg; + u8 uvalue = value; + struct s2mpg13_dev *dev = context; + struct i2c_client *client = s2mpg13_get_i2c_client(dev, reg); + + if (!client) + return -EFAULT; + + return s2mpg13_write_reg(client, ureg, uvalue); +} + +static const struct regmap_range s2mpg13_valid_regs[] = { + regmap_reg_range(0x000, 0x003), /* Common Block - VGPIO */ + regmap_reg_range(0x004, 0x029), /* Common Block */ + regmap_reg_range(0x100, 0x1D7), /* Power Management Block */ + regmap_reg_range(0xA00, 0xA62), /* Meter config, NTC */ + regmap_reg_range(0xA63, 0xAE5), /* Meter data */ + regmap_reg_range(0xC05, 0xC14), /* GPIO */ +}; + +static const struct regmap_range s2mpg13_read_only_regs[] = { + regmap_reg_range(0x000, 0x00B), /* Common Block */ + regmap_reg_range(0x020, 0x023), /* Common Block */ + regmap_reg_range(0x027, 0x029), /* Common Block */ + regmap_reg_range(0x100, 0x103), /* INT1~4 */ + regmap_reg_range(0x10A, 0x10A), /* OFFSRC */ + regmap_reg_range(0xA63, 0xAE5), /* Meter data */ +}; + +const struct regmap_access_table s2mpg13_read_register_set = { + .yes_ranges = s2mpg13_valid_regs, + .n_yes_ranges = ARRAY_SIZE(s2mpg13_valid_regs), +}; + +const struct regmap_access_table s2mpg13_write_register_set = { + .yes_ranges = s2mpg13_valid_regs, + .n_yes_ranges = ARRAY_SIZE(s2mpg13_valid_regs), + .no_ranges = s2mpg13_read_only_regs, + .n_no_ranges = ARRAY_SIZE(s2mpg13_read_only_regs), +}; + +static struct regmap_config s2mpg13_regmap_config = { + .name = "s2mpg13", + .reg_bits = 12, + .val_bits = 8, + .reg_stride = 1, + .max_register = 0xC14, + .reg_read = s2mpg13_regmap_read_reg, + .reg_write = s2mpg13_regmap_write_reg, + .rd_table = &s2mpg13_read_register_set, + .wr_table = &s2mpg13_write_register_set, +}; + +#if IS_ENABLED(CONFIG_OF) +static int of_s2mpg13_dt(struct device *dev, + struct s2mpg13_platform_data *pdata, + struct s2mpg13_dev *s2mpg13) +{ + struct device_node *np = dev->of_node; + const char *status; + + if (!np) + return -EINVAL; + + acpm_mfd_node = np; + + status = of_get_property(np, "s2mpg13,wakeup", NULL); + if (!status) + return -EINVAL; + pdata->wakeup = !strcmp(status, "enabled") || !strcmp(status, "okay"); + + return 0; +} +#else +static int of_s2mpg13_dt(struct device *dev, + struct s2mpg13_platform_data *pdata) +{ + return 0; +} +#endif /* CONFIG_OF */ + +static void s2mpg13_get_rev_id(struct s2mpg13_dev *s2mpg13, int id) +{ + if (id == 0x0 || id == 0x1 || id == 0x2) + s2mpg13->pmic_rev = S2MPG13_EVT0; + else + s2mpg13->pmic_rev = S2MPG13_EVT1; +} + +static int s2mpg13_i2c_probe(struct i2c_client *i2c, + const struct i2c_device_id *dev_id) +{ + struct s2mpg13_dev *s2mpg13; + struct s2mpg13_platform_data *pdata = i2c->dev.platform_data; + u8 reg_data; + int ret = 0; + + dev_info(&i2c->dev, "%s i2c probe\n", S2MPG13_MFD_DEV_NAME); + + s2mpg13 = kzalloc(sizeof(*s2mpg13), GFP_KERNEL); + if (!s2mpg13) + return -ENOMEM; + + if (i2c->dev.of_node) { + pdata = devm_kzalloc(&i2c->dev, + sizeof(struct s2mpg13_platform_data), + GFP_KERNEL); + if (!pdata) { + ret = -ENOMEM; + goto err; + } + + ret = of_s2mpg13_dt(&i2c->dev, pdata, s2mpg13); + if (ret < 0) { + dev_err(&i2c->dev, "Failed to get device of_node\n"); + goto err; + } + + i2c->dev.platform_data = pdata; + } else { + pdata = i2c->dev.platform_data; + } + + s2mpg13->dev = &i2c->dev; + i2c->addr = I2C_ADDR_TOP; + s2mpg13->i2c = i2c; + s2mpg13->device_type = S2MPG13X; + + if (pdata) { + s2mpg13->pdata = pdata; + + pdata->irq_base = irq_alloc_descs(-1, 0, S2MPG13_IRQ_NR, -1); + if (pdata->irq_base < 0) { + pr_err("%s:%s devm_irq_alloc_descs Fail! ret(%d)\n", + S2MPG13_MFD_DEV_NAME, __func__, pdata->irq_base); + ret = pdata->irq_base; + goto err; + } + + s2mpg13->irq_base = pdata->irq_base; + s2mpg13->wakeup = pdata->wakeup; + } else { + ret = -EINVAL; + goto err; + } + mutex_init(&s2mpg13->i2c_lock); + + i2c_set_clientdata(i2c, s2mpg13); + + if (s2mpg13_read_reg(i2c, S2MPG13_COMMON_CHIPID, ®_data) < 0) { + dev_warn(s2mpg13->dev, + "device not found on this channel\n"); + ret = -ENODEV; + goto err_w_lock; + } + s2mpg13_get_rev_id(s2mpg13, reg_data & 0x7); + + s2mpg13->pmic = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_PMIC); + s2mpg13->meter = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_METER); + s2mpg13->wlwp = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_WLWP); + s2mpg13->gpio = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_GPIO); + s2mpg13->mt_trim = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_MT_TRIM); + s2mpg13->trim = i2c_new_dummy_device(i2c->adapter, I2C_ADDR_TRIM); + + i2c_set_clientdata(s2mpg13->pmic, s2mpg13); + i2c_set_clientdata(s2mpg13->meter, s2mpg13); + i2c_set_clientdata(s2mpg13->wlwp, s2mpg13); + i2c_set_clientdata(s2mpg13->gpio, s2mpg13); + i2c_set_clientdata(s2mpg13->mt_trim, s2mpg13); + i2c_set_clientdata(s2mpg13->trim, s2mpg13); + + dev_info(s2mpg13->dev, "device found: rev.0x%02x\n", s2mpg13->pmic_rev); + + s2mpg13->regmap = devm_regmap_init(s2mpg13->dev, NULL, s2mpg13, + &s2mpg13_regmap_config); + if (IS_ERR(s2mpg13->regmap)) { + dev_err(s2mpg13->dev, "regmap_init failed!\n"); + ret = PTR_ERR(s2mpg13->regmap); + goto err_w_lock; + } + + ret = s2mpg13_notifier_init(s2mpg13); + if (ret) { + dev_err(s2mpg13->dev, "s2mpg13_notifier_init fail\n"); + goto err_w_lock; + } + + ret = mfd_add_devices(s2mpg13->dev, -1, s2mpg13_devs, + ARRAY_SIZE(s2mpg13_devs), NULL, 0, NULL); + if (ret) + goto err_mfd; + + ret = device_init_wakeup(s2mpg13->dev, pdata->wakeup); + if (ret) { + dev_err(s2mpg13->dev, "device_init_wakeup fail(%d)\n", ret); + goto err_mfd; + } + + return ret; + +err_mfd: + mfd_remove_devices(s2mpg13->dev); +err_w_lock: + mutex_destroy(&s2mpg13->i2c_lock); +err: + kfree(s2mpg13); + return ret; +} + +static int s2mpg13_i2c_remove(struct i2c_client *i2c) +{ + struct s2mpg13_dev *s2mpg13 = i2c_get_clientdata(i2c); + + if (s2mpg13->pdata->wakeup) + device_init_wakeup(s2mpg13->dev, false); + mfd_remove_devices(s2mpg13->dev); + i2c_unregister_device(s2mpg13->i2c); + kfree(s2mpg13); + + return 0; +} + +static const struct i2c_device_id s2mpg13_i2c_id[] = { + { S2MPG13_MFD_DEV_NAME, TYPE_S2MPG13 }, {} }; + +MODULE_DEVICE_TABLE(i2c, s2mpg13_i2c_id); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_device_id s2mpg13_i2c_dt_ids[] = { + { .compatible = "samsung,s2mpg13mfd" }, + {}, +}; +#endif /* CONFIG_OF */ + +#if IS_ENABLED(CONFIG_PM) +static int s2mpg13_suspend(struct device *dev) +{ + return 0; +} + +static int s2mpg13_resume(struct device *dev) +{ + return 0; +} +#else +#define s2mpg13_suspend NULL +#define s2mpg13_resume NULL +#endif /* CONFIG_PM */ + +const struct dev_pm_ops s2mpg13_pm = { + .suspend_late = s2mpg13_suspend, + .resume_early = s2mpg13_resume, +}; + +static struct i2c_driver s2mpg13_i2c_driver = { + .driver = { + .name = S2MPG13_MFD_DEV_NAME, + .owner = THIS_MODULE, +#if IS_ENABLED(CONFIG_PM) + .pm = &s2mpg13_pm, +#endif /* CONFIG_PM */ +#if IS_ENABLED(CONFIG_OF) + .of_match_table = s2mpg13_i2c_dt_ids, +#endif /* CONFIG_OF */ + .suppress_bind_attrs = true, + }, + .probe = s2mpg13_i2c_probe, + .remove = s2mpg13_i2c_remove, + .id_table = s2mpg13_i2c_id, +}; + +static int __init s2mpg13_i2c_init(void) +{ + return i2c_add_driver(&s2mpg13_i2c_driver); +} + +/* init early so consumer devices can complete system boot */ +subsys_initcall(s2mpg13_i2c_init); + +static void __exit s2mpg13_i2c_exit(void) +{ + i2c_del_driver(&s2mpg13_i2c_driver); +} + +module_exit(s2mpg13_i2c_exit); + +MODULE_DESCRIPTION("s2mpg13 multi-function core driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/s2mpg13-notifier.c b/drivers/mfd/s2mpg13-notifier.c new file mode 100644 index 000000000000..b18e00addbbe --- /dev/null +++ b/drivers/mfd/s2mpg13-notifier.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg13-notifier.c - Interrupt controller support for S2MPG13 + * + * Copyright (C) 2020 Samsung Electronics Co.Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef TEST_DBG +#define TEST_DBG 0 +#endif + +static struct notifier_block sub_pmic_notifier; +static struct s2mpg13_dev *s2mpg13_global; + +static u8 irq_reg_sub[S2MPG13_IRQ_GROUP_NR] = {0}; + +static const u8 s2mpg13_mask_reg[] = { + [S2MPG13_IRQS_PMIC_INT1] = S2MPG13_PM_INT1M, + [S2MPG13_IRQS_PMIC_INT2] = S2MPG13_PM_INT2M, + [S2MPG13_IRQS_PMIC_INT3] = S2MPG13_PM_INT3M, + [S2MPG13_IRQS_PMIC_INT4] = S2MPG13_PM_INT4M, + [S2MPG13_IRQS_METER_INT1] = S2MPG13_METER_INT1M, + [S2MPG13_IRQS_METER_INT2] = S2MPG13_METER_INT2M, + [S2MPG13_IRQS_METER_INT3] = S2MPG13_METER_INT3M, + [S2MPG13_IRQS_METER_INT4] = S2MPG13_METER_INT4M, +}; + +static struct i2c_client *get_i2c(struct s2mpg13_dev *s2mpg13, + enum s2mpg13_irq_source src) +{ + switch (src) { + case S2MPG13_IRQS_PMIC_INT1 ... S2MPG13_IRQS_PMIC_INT4: + return s2mpg13->pmic; + case S2MPG13_IRQS_METER_INT1 ... S2MPG13_IRQS_METER_INT4: + return s2mpg13->meter; + default: + return ERR_PTR(-EINVAL); + } +} + +struct s2mpg13_irq_data { + u8 mask; + enum s2mpg13_irq_source group; +}; + +#define DECLARE_IRQ(idx, _group, _mask) \ + [(idx)] = { .group = (_group), .mask = (_mask) } + +static const struct s2mpg13_irq_data s2mpg13_irqs[] = { + DECLARE_IRQ(S2MPG13_IRQ_PWRONF_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_PWRONR_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_INT120C_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_INT140C_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_TSD_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 5), + DECLARE_IRQ(S2MPG13_IRQ_WRST_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 6), + DECLARE_IRQ(S2MPG13_IRQ_WTSR_INT1, S2MPG13_IRQS_PMIC_INT1, 1 << 7), + + DECLARE_IRQ(S2MPG13_IRQ_SCL_SOFTRST_INT2, S2MPG13_IRQS_PMIC_INT2, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_WLWP_ACC_INT2, S2MPG13_IRQS_PMIC_INT2, 1 << 7), + + DECLARE_IRQ(S2MPG13_IRQ_OCP_B1S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B2S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B3S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B4S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B5S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B6S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 5), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B7S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 6), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B8S_INT3, S2MPG13_IRQS_PMIC_INT3, 1 << 7), + + DECLARE_IRQ(S2MPG13_IRQ_OCP_B9S_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_OCP_B10S_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_OCP_BDS_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_OCP_BAS_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_OCP_BCS_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_OCP_BBS_INT4, S2MPG13_IRQS_PMIC_INT4, 1 << 5), + + DECLARE_IRQ(S2MPG13_IRQ_PMETER_OVERF_INT5, S2MPG13_IRQS_METER_INT1, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_NTC_CYCLE_DONE_INT5, S2MPG13_IRQS_METER_INT1, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH0_INT5, S2MPG13_IRQS_METER_INT1, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH1_INT5, S2MPG13_IRQS_METER_INT1, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH2_INT5, S2MPG13_IRQS_METER_INT1, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH3_INT5, S2MPG13_IRQS_METER_INT1, 1 << 5), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH4_INT5, S2MPG13_IRQS_METER_INT1, 1 << 6), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH5_INT5, S2MPG13_IRQS_METER_INT1, 1 << 7), + + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH6_INT6, S2MPG13_IRQS_METER_INT2, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH7_INT6, S2MPG13_IRQS_METER_INT2, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH8_INT6, S2MPG13_IRQS_METER_INT2, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH9_INT6, S2MPG13_IRQS_METER_INT2, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH10_INT6, S2MPG13_IRQS_METER_INT2, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_PWR_WARN_CH11_INT6, S2MPG13_IRQS_METER_INT2, 1 << 5), + + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH1_INT7, S2MPG13_IRQS_METER_INT3, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH2_INT7, S2MPG13_IRQS_METER_INT3, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH3_INT7, S2MPG13_IRQS_METER_INT3, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH4_INT7, S2MPG13_IRQS_METER_INT3, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH5_INT7, S2MPG13_IRQS_METER_INT3, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH6_INT7, S2MPG13_IRQS_METER_INT3, 1 << 5), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH7_INT7, S2MPG13_IRQS_METER_INT3, 1 << 6), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_OT_CH8_INT7, S2MPG13_IRQS_METER_INT3, 1 << 7), + + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH1_INT8, S2MPG13_IRQS_METER_INT4, 1 << 0), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH2_INT8, S2MPG13_IRQS_METER_INT4, 1 << 1), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH3_INT8, S2MPG13_IRQS_METER_INT4, 1 << 2), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH4_INT8, S2MPG13_IRQS_METER_INT4, 1 << 3), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH5_INT8, S2MPG13_IRQS_METER_INT4, 1 << 4), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH6_INT8, S2MPG13_IRQS_METER_INT4, 1 << 5), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH7_INT8, S2MPG13_IRQS_METER_INT4, 1 << 6), + DECLARE_IRQ(S2MPG13_IRQ_NTC_WARN_UT_CH8_INT8, S2MPG13_IRQS_METER_INT4, 1 << 7), + +}; + +static int +s2mpg13_mask_ibi_region(struct s2mpg13_dev *s2mpg13, u8 reg, u8 region) +{ + int ret; + u8 mask = (0x01 << region); + + ret = s2mpg13_update_reg(s2mpg13->i2c, reg, mask, mask); + if (ret) { + dev_err(s2mpg13->dev, + "Failed to mask ibi region:0x%02x in reg:0x%02x", region, reg); + return ret; + } + + return 0; +} + +static int +s2mpg13_unmask_ibi_region(struct s2mpg13_dev *s2mpg13, u8 reg, u8 region) +{ + int ret; + u8 mask = (0x01 << region); + + ret = s2mpg13_update_reg(s2mpg13->i2c, reg, 0x00, mask); + if (ret) { + dev_err(s2mpg13->dev, + "Failed to unmask ibi region:0x%02x in reg:0x%02x", region, reg); + return ret; + } + + return 0; +} + +static int s2mpg13_update_ibi_regions(struct s2mpg13_dev *s2mpg13) +{ + /* Unmask PM region, if at least one PM interrupt is enabled */ + if ((s2mpg13->irq_masks_cur[S2MPG13_IRQS_PMIC_INT1] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_PMIC_INT2] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_PMIC_INT3] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_PMIC_INT4]) != 0xff) { + s2mpg13_unmask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM1, + S2MPG13_IBIM1_PM_REGION); + } else { + s2mpg13_mask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM1, + S2MPG13_IBIM1_PM_REGION); + } + + /* Unmask PMETER region, if at least one PMETER interrupt is enabled */ + if ((s2mpg13->irq_masks_cur[S2MPG13_IRQS_METER_INT1] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_METER_INT2] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_METER_INT3] & + s2mpg13->irq_masks_cur[S2MPG13_IRQS_METER_INT4]) != 0xff) { + s2mpg13_unmask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM1, + S2MPG13_IBIM1_PMETER_REGION); + } else { + s2mpg13_mask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM1, + S2MPG13_IBIM1_PMETER_REGION); + } + + return 0; +} + +static void s2mpg13_irq_lock(struct irq_data *data) +{ + struct s2mpg13_dev *s2mpg13 = irq_get_chip_data(data->irq); + mutex_lock(&s2mpg13->irqlock); +} + +static void s2mpg13_irq_sync_unlock(struct irq_data *data) +{ + struct s2mpg13_dev *s2mpg13 = irq_get_chip_data(data->irq); + int i; + + for (i = 0; i < S2MPG13_IRQ_GROUP_NR; i++) { + u8 mask_reg = s2mpg13_mask_reg[i]; + struct i2c_client *i2c = get_i2c(s2mpg13, i); + + if (mask_reg == S2MPG13_REG_INVALID || IS_ERR_OR_NULL(i2c)) + continue; + s2mpg13->irq_masks_cache[i] = s2mpg13->irq_masks_cur[i]; + + s2mpg13_write_reg(i2c, s2mpg13_mask_reg[i], + s2mpg13->irq_masks_cur[i]); + } + + s2mpg13_update_ibi_regions(s2mpg13); + + mutex_unlock(&s2mpg13->irqlock); +} + +static const inline struct s2mpg13_irq_data * +irq_to_s2mpg13_irq(struct s2mpg13_dev *s2mpg13, int irq) +{ + return &s2mpg13_irqs[irq - s2mpg13->irq_base]; +} + +static void s2mpg13_irq_mask(struct irq_data *data) +{ + struct s2mpg13_dev *s2mpg13 = irq_get_chip_data(data->irq); + const struct s2mpg13_irq_data *irq_data = + irq_to_s2mpg13_irq(s2mpg13, data->irq); + + if (irq_data->group >= S2MPG13_IRQ_GROUP_NR) + return; + + s2mpg13->irq_masks_cur[irq_data->group] |= irq_data->mask; +} + +static void s2mpg13_irq_unmask(struct irq_data *data) +{ + struct s2mpg13_dev *s2mpg13 = irq_get_chip_data(data->irq); + const struct s2mpg13_irq_data *irq_data = + irq_to_s2mpg13_irq(s2mpg13, data->irq); + + if (irq_data->group >= S2MPG13_IRQ_GROUP_NR) + return; + + s2mpg13->irq_masks_cur[irq_data->group] &= ~irq_data->mask; +} + +static struct irq_chip s2mpg13_irq_chip = { + .name = S2MPG13_MFD_DEV_NAME, + .irq_bus_lock = s2mpg13_irq_lock, + .irq_bus_sync_unlock = s2mpg13_irq_sync_unlock, + .irq_mask = s2mpg13_irq_mask, + .irq_unmask = s2mpg13_irq_unmask, +}; + + +/* BUCK 1~10, BUCK D, BUCK A, BUCK C */ +static int s2mpg13_buck_ocp_cnt[S2MPG13_BUCK_MAX]; + +static void s2mpg13_buck_ocp_irq(struct s2mpg13_dev *s2mpg13, int buck) +{ + s2mpg13_buck_ocp_cnt[buck]++; + + dev_info(s2mpg13->dev, "%s: S2MPG13 BUCK[%d] OCP IRQ: %d\n", + __func__, buck + 1, s2mpg13_buck_ocp_cnt[buck]); +} + +static const u8 s2mpg13_get_irq_mask[] = { + /* OCP */ + [S2MPG13_IRQ_OCP_B1S_INT3] = S2MPG13_IRQ_OCP_B1S_MASK, + [S2MPG13_IRQ_OCP_B2S_INT3] = S2MPG13_IRQ_OCP_B2S_MASK, + [S2MPG13_IRQ_OCP_B3S_INT3] = S2MPG13_IRQ_OCP_B3S_MASK, + [S2MPG13_IRQ_OCP_B4S_INT3] = S2MPG13_IRQ_OCP_B4S_MASK, + [S2MPG13_IRQ_OCP_B5S_INT3] = S2MPG13_IRQ_OCP_B5S_MASK, + [S2MPG13_IRQ_OCP_B6S_INT3] = S2MPG13_IRQ_OCP_B6S_MASK, + [S2MPG13_IRQ_OCP_B7S_INT3] = S2MPG13_IRQ_OCP_B7S_MASK, + [S2MPG13_IRQ_OCP_B8S_INT3] = S2MPG13_IRQ_OCP_B8S_MASK, + [S2MPG13_IRQ_OCP_B9S_INT4] = S2MPG13_IRQ_OCP_B9S_MASK, + [S2MPG13_IRQ_OCP_B10S_INT4] = S2MPG13_IRQ_OCP_B10S_MASK, + [S2MPG13_IRQ_OCP_BDS_INT4] = S2MPG13_IRQ_OCP_BDS_MASK, + [S2MPG13_IRQ_OCP_BAS_INT4] = S2MPG13_IRQ_OCP_BAS_MASK, + [S2MPG13_IRQ_OCP_BCS_INT4] = S2MPG13_IRQ_OCP_BCS_MASK, + [S2MPG13_IRQ_OCP_BBS_INT4] = S2MPG13_IRQ_OCP_BBS_MASK, +}; + +static void s2mpg13_call_interrupt(struct s2mpg13_dev *s2mpg13, + u8 pm_int1, u8 pm_int2, u8 pm_int3, u8 pm_int4, + u8 meter_int1, u8 meter_int2, u8 meter_int3, u8 meter_int4) +{ + size_t i; + u8 reg = 0; + + /* BUCK OCP interrupt */ + for (i = 0; i < S2MPG13_BUCK_MAX; i++) { + reg = S2MPG13_IRQ_OCP_B1S_INT3 + i; + + if ((pm_int3 & s2mpg13_get_irq_mask[reg]) || + (pm_int4 & s2mpg13_get_irq_mask[reg])) + s2mpg13_buck_ocp_irq(s2mpg13, i); + } + +#if IS_ENABLED(TEST_DBG) + /* BUCK-BOOST OCP interrupt */ + if (int4 & s2mpg13_get_irq_mask[S2MPG13_IRQ_OCP_BBS_INT4]) + s2mpg13_bb_ocp_irq(s2mpg13); +#endif +} + +static void s2mpg13_irq_work_func(struct work_struct *work) +{ + pr_info("%s: sub pmic interrupt(0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx, 0x%02hhx)\n", + __func__, irq_reg_sub[S2MPG13_IRQS_PMIC_INT1], irq_reg_sub[S2MPG13_IRQS_PMIC_INT2], + irq_reg_sub[S2MPG13_IRQS_PMIC_INT3], irq_reg_sub[S2MPG13_IRQS_PMIC_INT4], + irq_reg_sub[S2MPG13_IRQS_METER_INT1], irq_reg_sub[S2MPG13_IRQS_METER_INT2], + irq_reg_sub[S2MPG13_IRQS_METER_INT3], irq_reg_sub[S2MPG13_IRQS_METER_INT4]); +} + +static int s2mpg13_notifier_handler(struct notifier_block *nb, + unsigned long action, + void *data) +{ + struct s2mpg13_dev *s2mpg13 = data; + int i, ret; + + if (!s2mpg13) { + pr_err("[%s] s2mpg13 is not valid\n",__func__); + return NOTIFY_DONE; + } + + mutex_lock(&s2mpg13->irqlock); + + ret = s2mpg13_bulk_read(s2mpg13->pmic, S2MPG13_PM_INT1, + S2MPG13_NUM_IRQ_PMIC_REGS, + &irq_reg_sub[S2MPG13_IRQS_PMIC_INT1]); + if (ret) { + dev_err(s2mpg13->dev, "fail to read INT sources\n"); + mutex_unlock(&s2mpg13->irqlock); + + return NOTIFY_DONE; + } + + ret = s2mpg13_bulk_read(s2mpg13->meter, S2MPG13_METER_INT1, + S2MPG13_NUM_IRQ_METER_REGS, + &irq_reg_sub[S2MPG13_IRQS_METER_INT1]); + if (ret) { + dev_err(s2mpg13->dev, "fail to read INT sources\n"); + mutex_unlock(&s2mpg13->irqlock); + + return NOTIFY_DONE; + } + + s2mpg13_call_interrupt(s2mpg13, irq_reg_sub[S2MPG13_IRQS_PMIC_INT1], + irq_reg_sub[S2MPG13_IRQS_PMIC_INT2], irq_reg_sub[S2MPG13_IRQS_PMIC_INT3], + irq_reg_sub[S2MPG13_IRQS_PMIC_INT4], irq_reg_sub[S2MPG13_IRQS_METER_INT1], + irq_reg_sub[S2MPG13_IRQS_METER_INT2], irq_reg_sub[S2MPG13_IRQS_METER_INT3], + irq_reg_sub[S2MPG13_IRQS_METER_INT4]); + + for (i = 0; i < S2MPG13_IRQ_GROUP_NR; i++) + irq_reg_sub[i] &= ~s2mpg13->irq_masks_cur[i]; + + for (i = 0; i < S2MPG13_IRQ_NR; i++) { + if (irq_reg_sub[s2mpg13_irqs[i].group] & s2mpg13_irqs[i].mask) { + handle_nested_irq(s2mpg13->irq_base + i); + log_threaded_irq_wakeup_reason(s2mpg13->irq_base + i, + s2mpg13->irq); + } + } + + mutex_unlock(&s2mpg13->irqlock); + + return NOTIFY_DONE; +} + +static BLOCKING_NOTIFIER_HEAD(s2mpg13_notifier); + +static int s2mpg13_register_notifier(struct notifier_block *nb, + struct s2mpg13_dev *s2mpg13) +{ + int ret; + + ret = blocking_notifier_chain_register(&s2mpg13_notifier, nb); + if (ret < 0) + dev_err(s2mpg13->dev, "fail to register notifier\n"); + + return ret; +} + +void s2mpg13_call_notifier(void) +{ + blocking_notifier_call_chain(&s2mpg13_notifier, 0, s2mpg13_global); +} +EXPORT_SYMBOL(s2mpg13_call_notifier); + +static int s2mpg13_set_interrupt(struct s2mpg13_dev *s2mpg13) +{ + int i; + int ret = 0; + + /* mask individual interrupt sources */ + for (i = 0; i < S2MPG13_IRQ_GROUP_NR; i++) { + u8 mask_reg = s2mpg13_mask_reg[i]; + struct i2c_client *i2c = get_i2c(s2mpg13, i); + + if (mask_reg == S2MPG13_REG_INVALID || IS_ERR_OR_NULL(i2c)) { + ret = -ENODEV; + goto err; + } + + ret = s2mpg13_write_reg(i2c, s2mpg13_mask_reg[i], 0xff); + if (ret) + goto err; + + s2mpg13->irq_masks_cur[i] = 0xff; + s2mpg13->irq_masks_cache[i] = 0xff; + } + + /* Mask all inband interrupts during init*/ + for (i = 0; i < S2MPG13_IBIM1_REGION_MAX; i++) { + ret = s2mpg13_mask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM1, i); + if (ret) + goto err; + } + + for (i = 0; i < S2MPG13_IBIM2_REGION_MAX; i++) { + ret = s2mpg13_mask_ibi_region(s2mpg13, S2MPG13_COMMON_IBIM2, i); + if (ret) + goto err; + } + + return 0; + +err: + return ret; +} + +static int s2mpg13_set_wqueue(struct s2mpg13_dev *s2mpg13) +{ + s2mpg13->irq_wqueue = create_singlethread_workqueue("s2mpg13-wqueue"); + if (!s2mpg13->irq_wqueue) { + dev_err(s2mpg13->dev, "fail to create workqueue\n"); + return -1; + } + + INIT_DELAYED_WORK(&s2mpg13->irq_work, s2mpg13_irq_work_func); + + return 0; +} + +static void s2mpg13_set_notifier(struct s2mpg13_dev *s2mpg13) +{ + sub_pmic_notifier.notifier_call = s2mpg13_notifier_handler; + s2mpg13_register_notifier(&sub_pmic_notifier, s2mpg13); +} + +int s2mpg13_notifier_init(struct s2mpg13_dev *s2mpg13) +{ + int i; + int ret, cur_irq; + + if (!s2mpg13->irq_base) { + dev_err(s2mpg13->dev, "No interrupt base specified.\n"); + return -ENODEV; + } + + s2mpg13_global = s2mpg13; + mutex_init(&s2mpg13->irqlock); + + /* Register notifier */ + s2mpg13_set_notifier(s2mpg13); + + /* Set workqueue */ + ret = s2mpg13_set_wqueue(s2mpg13); + if (ret < 0) { + dev_err(s2mpg13->dev, "s2mpg13_set_wqueue fail\n"); + return ret; + } + + /* Set interrupt */ + ret = s2mpg13_set_interrupt(s2mpg13); + if (ret) { + dev_err(s2mpg13->dev, "s2mpg13_set_interrupt fail\n"); + return ret; + } + + /* Register with genirq */ + for (i = 0; i < S2MPG13_IRQ_NR; i++) { + cur_irq = i + s2mpg13->irq_base; + irq_set_chip_data(cur_irq, s2mpg13); + irq_set_chip_and_handler(cur_irq, &s2mpg13_irq_chip, + handle_level_irq); + irq_set_nested_thread(cur_irq, 1); +#if IS_ENABLED(CONFIG_ARM) + set_irq_flags(cur_irq, IRQF_VALID); +#else + irq_set_noprobe(cur_irq); +#endif + } + + return 0; +} +EXPORT_SYMBOL_GPL(s2mpg13_notifier_init); diff --git a/drivers/mfd/s2mpg1x-gpio.c b/drivers/mfd/s2mpg1x-gpio-gs101.c similarity index 100% rename from drivers/mfd/s2mpg1x-gpio.c rename to drivers/mfd/s2mpg1x-gpio-gs101.c diff --git a/drivers/mfd/s2mpg1x-gpio-gs201.c b/drivers/mfd/s2mpg1x-gpio-gs201.c new file mode 100644 index 000000000000..5ca9e54f5b75 --- /dev/null +++ b/drivers/mfd/s2mpg1x-gpio-gs201.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const struct pinctrl_pin_desc s2mpgM_pins[] = { + PINCTRL_PIN(0, "gpio0"), PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), PINCTRL_PIN(5, "gpio5"), +}; + +const struct pinctrl_pin_desc s2mpgS_pins[] = { + PINCTRL_PIN(0, "gpio6"), PINCTRL_PIN(1, "gpio7"), + PINCTRL_PIN(2, "gpio8"), PINCTRL_PIN(3, "gpio9"), + PINCTRL_PIN(4, "gpio10"), PINCTRL_PIN(5, "gpio11"), + PINCTRL_PIN(6, "gpio12"), PINCTRL_PIN(7, "gpio13"), +}; + +struct s2mpg1x_gpio { + struct gpio_chip gc; + struct pinctrl_ops pctrl_ops; + struct pinmux_ops pmux_ops; + struct pinconf_ops pconf_ops; + struct pinctrl_desc pctrl; + enum s2mpg1x_id id; + struct i2c_client *i2c; +}; + +int GPIO_STATUS[] = { S2MPG12_GPIO_STATUS, S2MPG13_GPIO_STATUS }; +int GPIO_CTRL_BASE[] = { S2MPG12_GPIO_0_SET, S2MPG13_GPIO_0_SET }; + +#define GPIO_MODE_SHIFT 0 /* Remote GPIO BIT */ +#define GPIO_DRV_STR_SHIFT 2 /* Drive strength selection (x2 when 1) BIT */ +#define GPIO_PD_SHIFT 3 /* Pull-Down enable BIT */ +#define GPIO_PU_SHIFT 4 /* Pull-Up enable BIT */ +#define GPIO_OUT_SHIFT 5 /* output data BIT */ +#define GPIO_OEN_SHIFT 6 /* output enabled BIT */ + +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) /* Remote GPIO */ +#define GPIO_DRV_STR_MASK BIT(GPIO_DRV_STR_SHIFT) /* Drive strength selection (x2 when 1) */ +#define GPIO_PD_MASK BIT(GPIO_PD_SHIFT) /* Pull-Down enable */ +#define GPIO_PU_MASK BIT(GPIO_PU_SHIFT) /* Pull-Up enable */ +#define GPIO_OUT_MASK BIT(GPIO_OUT_SHIFT) /* output data */ +#define GPIO_OEN_MASK BIT(GPIO_OEN_SHIFT) /* output enabled */ +#define GPIO_RSV_MASK BIT(GPIO_RSV_SHIFT) /* reserved */ + +static int s2mpg1x_read_gpio_ctrl_reg(struct s2mpg1x_gpio *gc, + unsigned int offset) +{ + int ret; + u8 val; + + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + offset, &val); + + if (ret < 0) { + dev_err(&gc->i2c->dev, "Error: %s %d", gc->gc.label, offset); + return ret; + } + + return val; +} + +static int s2mpg1x_read_gpio_status_reg(struct s2mpg1x_gpio *gc) +{ + int ret; + u8 val; + + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_STATUS[gc->id], &val); + + if (ret < 0) { + dev_err(&gc->i2c->dev, "Error: %s", gc->gc.label); + return ret; + } + + return val; +} + +static int s2mpg1x_read_gpio_ctrl_bit(struct s2mpg1x_gpio *gc, + unsigned int offset, + unsigned int bit_mask) +{ + return s2mpg1x_read_gpio_ctrl_reg(gc, offset) & bit_mask; +} + +static int s2mpg1x_update_gpio_ctrl_reg(struct s2mpg1x_gpio *gc, + unsigned int offset, u8 val, u8 mask) +{ + int ret; + + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + offset, val, + mask); + + if (ret < 0) + dev_err(&gc->i2c->dev, "Error: %s %d", gc->gc.label, offset); + + return ret; +} + +static int s2mpg1x_write_gpio_ctrl_bit(struct s2mpg1x_gpio *gc, + unsigned int offset, + unsigned int bit_mask, int value) +{ + return s2mpg1x_update_gpio_ctrl_reg(gc, offset, value, bit_mask); +} + +static int s2mpg1x_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct s2mpg1x_gpio *data = gpiochip_get_data(chip); + + return !s2mpg1x_read_gpio_ctrl_bit(data, offset, GPIO_OEN_MASK); +} + +static int s2mpg1x_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct s2mpg1x_gpio *data = gpiochip_get_data(chip); + + if (s2mpg1x_gpio_get_direction(chip, offset)) + return (s2mpg1x_read_gpio_status_reg(data) >> offset) & 0x1; + else + return s2mpg1x_read_gpio_ctrl_bit(data, offset, + GPIO_OUT_MASK); +} + +static void s2mpg1x_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct s2mpg1x_gpio *data = gpiochip_get_data(chip); + + if (!s2mpg1x_gpio_get_direction(chip, offset)) + s2mpg1x_write_gpio_ctrl_bit(data, offset, GPIO_OUT_MASK, + (value & 0x1) << GPIO_OUT_SHIFT); +} + +static int s2mpg1x_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct s2mpg1x_gpio *data = gpiochip_get_data(chip); + + return s2mpg1x_write_gpio_ctrl_bit(data, offset, GPIO_OEN_MASK, + 0 << GPIO_OEN_SHIFT); +} + +static int s2mpg1x_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s2mpg1x_gpio *data = gpiochip_get_data(chip); + int ret; + + ret = s2mpg1x_write_gpio_ctrl_bit(data, offset, GPIO_OUT_MASK, + (value & 0x1) << GPIO_OUT_SHIFT); + if (ret == 0) + ret = s2mpg1x_write_gpio_ctrl_bit(data, offset, GPIO_OEN_MASK, + 1 << GPIO_OEN_SHIFT); + + return ret; +} + +static int s2mpg1x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct s2mpg1x_gpio *gc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + u8 data; + u32 argument = 0; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + if (data & GPIO_PD_MASK) + return -EINVAL; + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + if (data & GPIO_PU_MASK) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + if (!(data & GPIO_PD_MASK)) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_UP: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + if (!(data & GPIO_PU_MASK)) + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + // do nothing + break; + case PIN_CONFIG_DRIVE_STRENGTH: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + argument = (data & GPIO_DRV_STR_MASK) ? 4 : 2; + break; + case PIN_CONFIG_INPUT_ENABLE: + // do nothing + break; + case PIN_CONFIG_OUTPUT: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + argument = !!(data & GPIO_OUT_MASK); + break; + case PIN_CONFIG_OUTPUT_ENABLE: + ret = s2mpg1x_read_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + &data); + if (ret) + return ret; + if (!(data & GPIO_OEN_MASK)) + return -EINVAL; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, argument); + + return 0; +} + +static int s2mpg1x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct s2mpg1x_gpio *gc = pinctrl_dev_get_drvdata(pctldev); + u8 data; + unsigned int i; + int ret; + + for (i = 0; i < num_configs; i++) { + enum pin_config_param param = + pinconf_to_config_param(configs[i]); + + u32 argument = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + 0, GPIO_PD_MASK); + if (ret) + return ret; + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + 0, GPIO_PU_MASK); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + GPIO_PD_MASK, GPIO_PD_MASK); + if (ret) + return ret; + break; + case PIN_CONFIG_BIAS_PULL_UP: + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + GPIO_PU_MASK, GPIO_PU_MASK); + if (ret) + return ret; + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + // do nothing + break; + case PIN_CONFIG_DRIVE_STRENGTH: + switch (argument) { + case 2: + data = 0; + break; + case 4: + data = GPIO_DRV_STR_MASK; + break; + default: + pr_err("Drive-strength %umA not supported\n", + argument); + return -ENOTSUPP; + } + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + data, GPIO_DRV_STR_MASK); + if (ret) + return ret; + break; + case PIN_CONFIG_INPUT_ENABLE: + if (!argument) + return -EINVAL; + break; + case PIN_CONFIG_OUTPUT: + data = argument ? GPIO_OUT_MASK : 0; + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + data, GPIO_OUT_MASK); + if (ret) + return ret; + argument = 1; + fallthrough; + case PIN_CONFIG_OUTPUT_ENABLE: + data = argument ? GPIO_OEN_MASK : 0; + ret = s2mpg1x_update_reg(gc->id, gc->i2c, + GPIO_CTRL_BASE[gc->id] + pin, + data, GPIO_OEN_MASK); + if (ret) + return ret; + break; + default: + return -ENOTSUPP; + } + } + + return 0; +} + +static int pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return NULL; +} + +static int pinmux_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char *const **groups, + unsigned int *const num_groups) +{ + return -ENOTSUPP; +} + +static int pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, + unsigned int group) +{ + return -ENOTSUPP; +} + +static int pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + unsigned long config = + pinconf_to_config_packed(PIN_CONFIG_OUTPUT_ENABLE, !input); + return s2mpg1x_pinconf_set(pctldev, offset, &config, 1); +} + +static int pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return NULL; +} + +static int s2mpg1x_gpio_probe(struct platform_device *pdev) +{ + int ret; + struct s2mpg1x_gpio *s2mpg1x_gpio = + devm_kzalloc(&pdev->dev, + sizeof(struct s2mpg1x_gpio), GFP_KERNEL); + struct pinctrl_dev *pctl; + u32 ngpios; + const char *pinctrl_of_name = NULL; + struct kbase_device *kbdev_parent = dev_get_drvdata(pdev->dev.parent); + + if (!s2mpg1x_gpio) + return -ENOMEM; + + s2mpg1x_gpio->id = pdev->id_entry->driver_data; + switch (s2mpg1x_gpio->id) { +#if defined(CONFIG_SOC_GS101) + case ID_S2MPG10: + s2mpg1x_gpio->i2c = ((struct s2mpg10_dev *)kbdev_parent)->pmic; + pinctrl_of_name = "s2mpg10_pinctrl"; + s2mpg1x_gpio->pctrl.pins = s2mpgM_pins; + s2mpg1x_gpio->pctrl.npins = ARRAY_SIZE(s2mpgM_pins); + break; + case ID_S2MPG11: + s2mpg1x_gpio->i2c = ((struct s2mpg11_dev *)kbdev_parent)->pmic; + pinctrl_of_name = "s2mpg11_pinctrl"; + s2mpg1x_gpio->pctrl.pins = s2mpgS_pins; + // For slider gpio12,13 are not there (common structure array) + s2mpg1x_gpio->pctrl.npins = ARRAY_SIZE(s2mpgS_pins) - 2; + break; +#endif +#if defined(CONFIG_SOC_GS201) + case ID_S2MPG12: + s2mpg1x_gpio->i2c = ((struct s2mpg12_dev *)kbdev_parent)->gpio; + pinctrl_of_name = "s2mpg12_pinctrl"; + s2mpg1x_gpio->pctrl.pins = s2mpgM_pins; + s2mpg1x_gpio->pctrl.npins = ARRAY_SIZE(s2mpgM_pins); + break; + case ID_S2MPG13: + s2mpg1x_gpio->i2c = ((struct s2mpg13_dev *)kbdev_parent)->gpio; + pinctrl_of_name = "s2mpg13_pinctrl"; + s2mpg1x_gpio->pctrl.pins = s2mpgS_pins; + s2mpg1x_gpio->pctrl.npins = ARRAY_SIZE(s2mpgS_pins); + break; +#endif + default: + return -EINVAL; + } + + /* GPIO config */ + s2mpg1x_gpio->gc.label = pdev->name; + s2mpg1x_gpio->gc.parent = &pdev->dev; + s2mpg1x_gpio->gc.get_direction = s2mpg1x_gpio_get_direction; + s2mpg1x_gpio->gc.get = s2mpg1x_gpio_get; + s2mpg1x_gpio->gc.set = s2mpg1x_gpio_set; + s2mpg1x_gpio->gc.direction_input = s2mpg1x_gpio_direction_input; + s2mpg1x_gpio->gc.direction_output = s2mpg1x_gpio_direction_output; + s2mpg1x_gpio->gc.base = -1; + s2mpg1x_gpio->gc.can_sleep = true; + s2mpg1x_gpio->gc.of_node = + of_find_node_by_name(pdev->dev.parent->of_node, pdev->name); + s2mpg1x_gpio->gc.set_config = gpiochip_generic_config; + s2mpg1x_gpio->gc.request = gpiochip_generic_request; + s2mpg1x_gpio->gc.free = gpiochip_generic_free; + + if (!s2mpg1x_gpio->gc.of_node) { + dev_err(&pdev->dev, "Failed to find %s DT node\n", pdev->name); + return -EINVAL; + } + if (of_property_read_u32(s2mpg1x_gpio->gc.of_node, "ngpios", &ngpios)) { + dev_err(&pdev->dev, "Failed to get ngpios from %s DT node\n", + pdev->name); + return -EINVAL; + } + s2mpg1x_gpio->gc.ngpio = ngpios; + + /* pinctrl config */ + s2mpg1x_gpio->pctrl_ops.get_groups_count = pinctrl_get_groups_count; + s2mpg1x_gpio->pctrl_ops.get_group_name = pinctrl_get_group_name; + s2mpg1x_gpio->pctrl_ops.dt_node_to_map = + pinconf_generic_dt_node_to_map_pin; + s2mpg1x_gpio->pctrl_ops.dt_free_map = pinconf_generic_dt_free_map; + + s2mpg1x_gpio->pmux_ops.get_functions_count = pinmux_get_funcs_count; + s2mpg1x_gpio->pmux_ops.get_function_name = pinmux_get_func_name; + s2mpg1x_gpio->pmux_ops.get_function_groups = pinmux_get_func_groups; + s2mpg1x_gpio->pmux_ops.set_mux = pinmux_set_mux; + s2mpg1x_gpio->pmux_ops.gpio_set_direction = pinmux_gpio_set_direction; + + s2mpg1x_gpio->pconf_ops.is_generic = true; + s2mpg1x_gpio->pconf_ops.pin_config_get = s2mpg1x_pinconf_get; + s2mpg1x_gpio->pconf_ops.pin_config_set = s2mpg1x_pinconf_set; + + /* pins defined in chip id switch statement */ + s2mpg1x_gpio->pctrl.pctlops = &s2mpg1x_gpio->pctrl_ops; + s2mpg1x_gpio->pctrl.pmxops = &s2mpg1x_gpio->pmux_ops; + s2mpg1x_gpio->pctrl.confops = &s2mpg1x_gpio->pconf_ops; + s2mpg1x_gpio->pctrl.owner = THIS_MODULE; + s2mpg1x_gpio->pctrl.name = dev_name(&pdev->dev); + + pdev->dev.of_node = of_find_node_by_name(pdev->dev.parent->of_node, + pinctrl_of_name); + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Failed to find %s DT node\n", + pinctrl_of_name); + return -EINVAL; + } + + ret = devm_pinctrl_register_and_init(&pdev->dev, &s2mpg1x_gpio->pctrl, + s2mpg1x_gpio, &pctl); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register pin_ctrl: %d\n", ret); + return ret; + } + + ret = pinctrl_enable(pctl); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enable pin_ctrl: %d\n", ret); + return ret; + } + + ret = devm_gpiochip_add_data(&pdev->dev, &s2mpg1x_gpio->gc, + s2mpg1x_gpio); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register gpio_chip: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, s2mpg1x_gpio); + + return 0; +} + +static int s2mpg1x_gpio_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct platform_device_id s2mpg1x_gpio_id[] = { +#if defined(CONFIG_SOC_GS101) + { "s2mpg10_gpio", ID_S2MPG10 }, + { "s2mpg11_gpio", ID_S2MPG11 }, +#endif +#if defined(CONFIG_SOC_GS201) + { "s2mpg12_gpio", ID_S2MPG12 }, + { "s2mpg13_gpio", ID_S2MPG13 }, +#endif + {}, +}; +MODULE_DEVICE_TABLE(platform, s2mpg1x_gpio_id); + +static struct platform_driver s2mpg1x_gpio_driver = { + .driver = { + .name = "s2mpg1x_gpio", + .owner = THIS_MODULE, + }, + .probe = s2mpg1x_gpio_probe, + .remove = s2mpg1x_gpio_remove, + .id_table = s2mpg1x_gpio_id, +}; + +static int __init s2mpg1x_gpio_init(void) +{ + return platform_driver_register(&s2mpg1x_gpio_driver); +} +subsys_initcall(s2mpg1x_gpio_init); + +static void __exit s2mpg1x_gpio_exit(void) +{ + platform_driver_unregister(&s2mpg1x_gpio_driver); +} +module_exit(s2mpg1x_gpio_exit); + +MODULE_DESCRIPTION("S2MPG10 S2MPG11 S2MPG12 S2MPG13 GPIO Driver"); +MODULE_AUTHOR("Thierry Strudel "); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/slg51002-core.c b/drivers/mfd/slg51002-core.c new file mode 100644 index 000000000000..c68ad49e0078 --- /dev/null +++ b/drivers/mfd/slg51002-core.c @@ -0,0 +1,835 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * slg51002 core driver + * + * Copyright (C) 2021 Google, LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLG51002_CHIP_ID_LEN 3 +#define TIMER_EXPIRED_MSEC 500 + +static const struct mfd_cell slg51002_devs[] = { + { + .name = "slg51002-regulator", + }, + { + .name = "slg51002_gpio", + }, +}; + +static const struct regmap_range slg51002_writeable_ranges[] = { + regmap_reg_range(SLG51002_SYSCTL_MATRIX_CONF_A, + SLG51002_SYSCTL_MATRIX_CONF_A), + regmap_reg_range(SLG51002_LDO_HP_STARTUP_ILIM, + SLG51002_LDO_HP_STARTUP_ILIM), + regmap_reg_range(SLG51002_LDO1_VSEL, SLG51002_LDO1_VSEL), + regmap_reg_range(SLG51002_LDO1_MINV, SLG51002_LDO1_MAXV), + regmap_reg_range(SLG51002_LDO1_IRQ_MASK, SLG51002_LDO1_IRQ_MASK), + regmap_reg_range(SLG51002_LDO2_VSEL, SLG51002_LDO2_VSEL), + regmap_reg_range(SLG51002_LDO2_MINV, SLG51002_LDO2_MAXV), + regmap_reg_range(SLG51002_LDO2_IRQ_MASK, SLG51002_LDO2_IRQ_MASK), + regmap_reg_range(SLG51002_LDO3_VSEL, SLG51002_LDO3_VSEL), + regmap_reg_range(SLG51002_LDO3_MINV, SLG51002_LDO3_MAXV), + regmap_reg_range(SLG51002_LDO3_CONF1, SLG51002_LDO3_CONF1), + regmap_reg_range(SLG51002_LDO3_IRQ_MASK, SLG51002_LDO3_IRQ_MASK), + regmap_reg_range(SLG51002_LDO4_VSEL, SLG51002_LDO4_VSEL), + regmap_reg_range(SLG51002_LDO4_MINV, SLG51002_LDO4_MAXV), + regmap_reg_range(SLG51002_LDO4_IRQ_MASK, SLG51002_LDO4_IRQ_MASK), + regmap_reg_range(SLG51002_LDO5_VSEL, SLG51002_LDO5_VSEL), + regmap_reg_range(SLG51002_LDO5_MINV, SLG51002_LDO5_MAXV), + regmap_reg_range(SLG51002_LDO5_IRQ_MASK, SLG51002_LDO5_IRQ_MASK), + regmap_reg_range(SLG51002_LDO6_VSEL, SLG51002_LDO6_VSEL), + regmap_reg_range(SLG51002_LDO6_MINV, SLG51002_LDO6_MAXV), + regmap_reg_range(SLG51002_LDO6_TRIM2, SLG51002_LDO6_TRIM2), + regmap_reg_range(SLG51002_LDO6_IRQ_MASK, SLG51002_LDO6_IRQ_MASK), + regmap_reg_range(SLG51002_LDO7_VSEL, SLG51002_LDO7_VSEL), + regmap_reg_range(SLG51002_LDO7_MINV, SLG51002_LDO7_MAXV), + regmap_reg_range(SLG51002_LDO7_TRIM2, SLG51002_LDO7_TRIM2), + regmap_reg_range(SLG51002_LDO7_IRQ_MASK, SLG51002_LDO7_IRQ_MASK), + regmap_reg_range(SLG51002_LDO8_VSEL, SLG51002_LDO8_VSEL), + regmap_reg_range(SLG51002_LDO8_MINV, SLG51002_LDO8_MAXV), + regmap_reg_range(SLG51002_LDO8_TRIM2, SLG51002_LDO8_TRIM2), + regmap_reg_range(SLG51002_LDO8_IRQ_MASK, SLG51002_LDO8_IRQ_MASK), + regmap_reg_range(SLG51002_OTP_IRQ_MASK, SLG51002_OTP_IRQ_MASK), + regmap_reg_range(SLG51002_SW_TEST_MODE_1, SLG51002_SW_TEST_MODE_4), + regmap_reg_range(SLG51002_MUXARRAY_INPUT_SEL_39, + SLG51002_MUXARRAY_INPUT_SEL_39), + regmap_reg_range(SLG51002_LUTARRAY_LUT_VAL_3, + SLG51002_LUTARRAY_LUT_VAL_3), + /* For GPIO and sequence control */ + regmap_reg_range(0x1101, 0x800F), +}; + +static const struct regmap_range slg51002_readable_ranges[] = { + regmap_reg_range(SLG51002_SYSCTL_PATN_ID_B0, + SLG51002_SYSCTL_PATN_ID_B2), + regmap_reg_range(SLG51002_SYSCTL_SYS_CONF_A, + SLG51002_SYSCTL_SYS_CONF_A), + regmap_reg_range(SLG51002_SYSCTL_SYS_CONF_D, + SLG51002_SYSCTL_MATRIX_CONF_B), + regmap_reg_range(SLG51002_SYSCTL_REFGEN_CONF_C, + SLG51002_SYSCTL_UVLO_CONF_A), + regmap_reg_range(SLG51002_SYSCTL_FAULT_LOG1, SLG51002_SYSCTL_IRQ_MASK), + regmap_reg_range(SLG51002_LDO_HP_STARTUP_ILIM, + SLG51002_LDO_HP_STARTUP_ILIM), + regmap_reg_range(SLG51002_IO_GPIO1_CONF, SLG51002_IO_GPIO_STATUS), + regmap_reg_range(SLG51002_LUTARRAY_LUT_VAL_0, + SLG51002_LUTARRAY_LUT_VAL_11), + regmap_reg_range(SLG51002_MUXARRAY_INPUT_SEL_0, + SLG51002_MUXARRAY_INPUT_SEL_63), + regmap_reg_range(SLG51002_PWRSEQ_RESOURCE_EN_0, + SLG51002_PWRSEQ_INPUT_SENSE_CONF_B), + regmap_reg_range(SLG51002_LDO1_VSEL, SLG51002_LDO1_VSEL), + regmap_reg_range(SLG51002_LDO1_MINV, SLG51002_LDO1_MAXV), + regmap_reg_range(SLG51002_LDO1_TRIM2, SLG51002_LDO1_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO1_EVENT, SLG51002_LDO1_IRQ_MASK), + regmap_reg_range(SLG51002_LDO2_VSEL, SLG51002_LDO2_VSEL), + regmap_reg_range(SLG51002_LDO2_MINV, SLG51002_LDO2_MAXV), + regmap_reg_range(SLG51002_LDO2_TRIM2, SLG51002_LDO2_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO2_EVENT, SLG51002_LDO2_IRQ_MASK), + regmap_reg_range(SLG51002_LDO3_VSEL, SLG51002_LDO3_VSEL), + regmap_reg_range(SLG51002_LDO3_MINV, SLG51002_LDO3_MAXV), + regmap_reg_range(SLG51002_LDO3_TRIM2, SLG51002_LDO3_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO3_EVENT, SLG51002_LDO3_IRQ_MASK), + regmap_reg_range(SLG51002_LDO4_VSEL, SLG51002_LDO4_VSEL), + regmap_reg_range(SLG51002_LDO4_MINV, SLG51002_LDO4_MAXV), + regmap_reg_range(SLG51002_LDO4_TRIM2, SLG51002_LDO4_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO4_EVENT, SLG51002_LDO4_IRQ_MASK), + regmap_reg_range(SLG51002_LDO5_VSEL, SLG51002_LDO5_VSEL), + regmap_reg_range(SLG51002_LDO5_MINV, SLG51002_LDO5_MAXV), + regmap_reg_range(SLG51002_LDO5_TRIM2, SLG51002_LDO5_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO5_EVENT, SLG51002_LDO5_IRQ_MASK), + regmap_reg_range(SLG51002_LDO6_VSEL, SLG51002_LDO6_VSEL), + regmap_reg_range(SLG51002_LDO6_MINV, SLG51002_LDO6_MAXV), + regmap_reg_range(SLG51002_LDO6_TRIM2, SLG51002_LDO6_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO6_EVENT, SLG51002_LDO6_IRQ_MASK), + regmap_reg_range(SLG51002_LDO7_VSEL, SLG51002_LDO7_VSEL), + regmap_reg_range(SLG51002_LDO7_MINV, SLG51002_LDO7_MAXV), + regmap_reg_range(SLG51002_LDO7_TRIM2, SLG51002_LDO7_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO7_EVENT, SLG51002_LDO7_IRQ_MASK), + regmap_reg_range(SLG51002_LDO8_VSEL, SLG51002_LDO8_VSEL), + regmap_reg_range(SLG51002_LDO8_MINV, SLG51002_LDO8_MAXV), + regmap_reg_range(SLG51002_LDO8_TRIM2, SLG51002_LDO8_VSEL_ACTUAL), + regmap_reg_range(SLG51002_LDO8_EVENT, SLG51002_LDO8_IRQ_MASK), + regmap_reg_range(SLG51002_OTP_EVENT, SLG51002_OTP_EVENT), + regmap_reg_range(SLG51002_OTP_IRQ_MASK, SLG51002_OTP_IRQ_MASK), + regmap_reg_range(SLG51002_LOCK_GLOBAL_LOCK_CTRL1, + SLG51002_LOCK_GLOBAL_LOCK_CTRL1), + regmap_reg_range(SLG51002_SYSCTL_TEST_EN, SLG51002_SYSCTL_TEST_EN), +}; + +static const struct regmap_range slg51002_volatile_ranges[] = { + regmap_reg_range(SLG51002_SYSCTL_FAULT_LOG1, SLG51002_SYSCTL_STATUS), + regmap_reg_range(SLG51002_IO_GPIO_STATUS, SLG51002_IO_GPIO_STATUS), + regmap_reg_range(SLG51002_LDO1_EVENT, SLG51002_LDO1_STATUS), + regmap_reg_range(SLG51002_LDO2_EVENT, SLG51002_LDO2_STATUS), + regmap_reg_range(SLG51002_LDO3_EVENT, SLG51002_LDO3_STATUS), + regmap_reg_range(SLG51002_LDO4_EVENT, SLG51002_LDO4_STATUS), + regmap_reg_range(SLG51002_LDO5_EVENT, SLG51002_LDO5_STATUS), + regmap_reg_range(SLG51002_LDO6_EVENT, SLG51002_LDO6_STATUS), + regmap_reg_range(SLG51002_LDO7_EVENT, SLG51002_LDO7_STATUS), + regmap_reg_range(SLG51002_LDO8_EVENT, SLG51002_LDO8_STATUS), + regmap_reg_range(SLG51002_OTP_EVENT, SLG51002_OTP_EVENT), +}; + +static const struct regmap_access_table slg51002_writeable_table = { + .yes_ranges = slg51002_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(slg51002_writeable_ranges), +}; + +static const struct regmap_access_table slg51002_readable_table = { + .yes_ranges = slg51002_readable_ranges, + .n_yes_ranges = ARRAY_SIZE(slg51002_readable_ranges), +}; + +static const struct regmap_access_table slg51002_volatile_table = { + .yes_ranges = slg51002_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(slg51002_volatile_ranges), +}; + +static int slg51002_set_revision_specific_regs(struct slg51002_dev *chip) +{ + int ret = 0; + size_t i; + static const struct slg51002_register_setting regs_aa[] = { + /* Startup current limit */ + {SLG51002_LDO1_CONF1, 0x0A}, {SLG51002_LDO2_CONF1, 0x0A}, + {SLG51002_LDO3_CONF1, 0x0A}, {SLG51002_LDO4_CONF1, 0x0A}, + {SLG51002_LDO5_CONF1, 0x0A}, {SLG51002_LDO6_CONF1, 0x0A}, + {SLG51002_LDO7_CONF1, 0x0A}, {SLG51002_LDO8_CONF1, 0x0A}, + /* Functional current limit */ + {SLG51002_LDO1_CONF2, 0x2D}, {SLG51002_LDO2_CONF2, 0x2D}, + {SLG51002_LDO3_CONF2, 0x2D}, {SLG51002_LDO4_CONF2, 0x2D}, + {SLG51002_LDO5_CONF2, 0x2D}, {SLG51002_LDO6_CONF2, 0x2A}, + {SLG51002_LDO7_CONF2, 0x2A}, {SLG51002_LDO8_CONF2, 0x32}, + /* LDO mode */ + {SLG51002_LDO6_TRIM2, 0x00}, {SLG51002_LDO7_TRIM2, 0x00}, + {SLG51002_LDO8_TRIM2, 0x00}, + }; + + if (chip->chip_id != REVISION_AA) + return ret; + + for (i = 0; i < ARRAY_SIZE(regs_aa); i++) { + ret = regmap_write(chip->i2c_regmap, regs_aa[i].addr, regs_aa[i].val); + if (ret < 0) { + dev_err(chip->dev, "Failed to set registers for revision AA: " + "addr 0x%02x\n", regs_aa[i].addr); + return ret; + } + } + + return ret; +} + +static int slg51002_init_regs(struct slg51002_dev *chip) +{ + int ret; + size_t i; + int offset; + u32 tmp; + int num_output; + u32 num_cells; + struct slg51002_register_setting *regs; + + ret = of_property_read_u32(chip->dev->of_node, + "dlg,reg-init-cells", &num_cells); + if (ret) + return -EINVAL; + + if (num_cells != 2) + return -EINVAL; + + if (!of_get_property(chip->dev->of_node, "dlg,reg-init", &tmp)) + return -EINVAL; + + num_output = tmp / (sizeof(u32) * num_cells); + + regs = kcalloc(num_output, sizeof(struct slg51002_register_setting), + GFP_KERNEL); + if (!regs) { + ret = -ENOMEM; + goto out; + } + + /* Apply the settings */ + for (i = 0; i < num_output; i++) { + offset = i * num_cells; + if (of_property_read_u32_index(chip->dev->of_node, + "dlg,reg-init", offset, &tmp)) + goto out; + regs[i].addr = tmp; + + if (of_property_read_u32_index(chip->dev->of_node, + "dlg,reg-init", offset + 1, &tmp)) + goto out; + regs[i].val = tmp; + + ret = regmap_write(chip->i2c_regmap, regs[i].addr, regs[i].val); + if (ret < 0) { + dev_err(chip->dev, "Failed to set addr 0x%02x\n", + regs[i].addr); + goto out; + } + } + +out: + kfree(regs); + return ret; +} + +static int slg51002_enter_sw_test_mode(struct regmap *map) +{ + unsigned int val = 0; + int ret; + const u8 sw_test_mode_on_vals[] = { + SLG51002_SW_TEST_MODE_1_ON, + SLG51002_SW_TEST_MODE_2_ON, + SLG51002_SW_TEST_MODE_3_ON, + SLG51002_SW_TEST_MODE_4_ON, + }; + + if (!map) + return -EINVAL; + + ret = regmap_bulk_write(map, SLG51002_SW_TEST_MODE_1, + sw_test_mode_on_vals, ARRAY_SIZE(sw_test_mode_on_vals)); + if (ret < 0) { + dev_err(regmap_get_device(map), + "Failed to write regs for sw test mode\n"); + return ret; + } + + ret = regmap_read(map, SLG51002_SYSCTL_TEST_EN, &val); + if (ret < 0) { + dev_err(regmap_get_device(map), + "Failed to read SLG51002_SYSCTL_TEST_EN\n"); + return ret; + } + + /* Check if software test mode already enabled */ + if (val & SLG51002_TEST_EN_ON_MASK) + return 0; + + return ret; +} + +static int slg51002_exit_sw_test_mode(struct regmap *map) +{ + if (!map) + return -EINVAL; + + return regmap_write(map, SLG51002_SYSCTL_TEST_EN, + SLG51002_TEST_EN_OFF); +} + +static int slg51002_config_tuning(struct slg51002_dev *chip) +{ + int ret; + + if (chip == NULL) { + pr_err("[%s] Invalid arguments\n", __func__); + return -EINVAL; + } + + ret = slg51002_enter_sw_test_mode(chip->i2c_regmap); + if (ret < 0) + return ret; + + /* Overwrite OTP revision related registers */ + ret = slg51002_set_revision_specific_regs(chip); + if (ret < 0) + dev_warn(chip->dev, "HW may not work as expected\n"); + + /* Initialize register settings */ + ret = slg51002_init_regs(chip); + if (ret < 0) + dev_info(chip->dev, "No init registers are overridden\n"); + + ret = slg51002_exit_sw_test_mode(chip->i2c_regmap); + if (ret < 0) + return ret; + + return ret; +} + +static void slg51002_clear_fault_log(struct slg51002_dev *chip) +{ + unsigned int val = 0; + int ret = 0; + + ret = regmap_read(chip->regmap, SLG51002_SYSCTL_FAULT_LOG1, &val); + if (ret < 0) { + dev_err(chip->dev, "Failed to read Fault log register\n"); + return; + } + + if (val & SLG51002_FLT_OVER_TEMP_MASK) + dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n"); + if (val & SLG51002_FLT_POWER_SEQ_CRASH_REQ_MASK) + dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n"); + if (val & SLG51002_FLT_RST_MASK) + dev_dbg(chip->dev, "Fault log: FLT_RST\n"); + if (val & SLG51002_FLT_POR_MASK) + dev_dbg(chip->dev, "Fault log: FLT_POR\n"); +} + +static int slg51002_power_on(struct slg51002_dev *chip) +{ + if (chip == NULL) + return -EINVAL; + + mutex_lock(&chip->pwr_lock); + if (chip->is_power_on) + goto out; + + if (gpio_is_valid(chip->chip_bb_pin)) { + gpio_set_value_cansleep(chip->chip_bb_pin, 1); + usleep_range(2000, 2020); + } + + if (gpio_is_valid(chip->chip_buck_pin)) { + gpio_set_value_cansleep(chip->chip_buck_pin, 1); + usleep_range(2000, 2020); + } + + chip->is_power_on = true; + dev_dbg(chip->dev, "power on\n"); + + slg51002_config_tuning(chip); + + if (gpio_is_valid(chip->chip_pu_pin)) { + gpio_set_value_cansleep(chip->chip_pu_pin, 1); + usleep_range(1000, 1020); + } + +out: + mutex_unlock(&chip->pwr_lock); + return 0; +} + +static int slg51002_power_off(struct slg51002_dev *chip) +{ + unsigned int val = 0; + int ret, idx; + uint8_t gpio_vals[SLG51002_PHYSICAL_GPIO_NR]; + + if (chip == NULL) + return -EINVAL; + + mutex_lock(&chip->pwr_lock); + if (!chip->is_power_on || chip->chip_always_on) { + ret = 0; + goto out; + } + + /* Check control register */ + ret = regmap_read(chip->i2c_regmap, SLG51002_SYSCTL_MATRIX_CONF_A, &val); + if (ret < 0) + goto out; + if (val) { + ret = 0; + goto out; + } + + /* + * Need to check GPIO control registers for mode + * SLG51002_OP_MODE_LDO_GPIO + */ + if (chip->op_mode == SLG51002_OP_MODE_LDO_GPIO) { + ret = regmap_bulk_read(chip->i2c_regmap, + GPIO1_CTRL, gpio_vals, ARRAY_SIZE(gpio_vals)); + if (ret < 0) + goto out; + + for (idx = 0; idx < ARRAY_SIZE(gpio_vals); idx++) { + if (gpio_vals[idx] != 0) { + ret = 0; + goto out; + } + } + } + + /* power off */ + if (gpio_is_valid(chip->chip_pu_pin)) { + gpio_set_value_cansleep(chip->chip_pu_pin, 0); + usleep_range(1000, 1020); + } + + if (gpio_is_valid(chip->chip_buck_pin)) { + gpio_set_value_cansleep(chip->chip_buck_pin, 0); + usleep_range(1000, 1020); + } + + if (gpio_is_valid(chip->chip_bb_pin)) { + gpio_set_value_cansleep(chip->chip_bb_pin, 0); + usleep_range(1000, 1020); + } + + + chip->is_power_on = false; + dev_dbg(chip->dev, "power off\n"); + +out: + mutex_unlock(&chip->pwr_lock); + return ret; +} + +static void slg51002_timeout_work(struct work_struct *work) +{ + struct slg51002_dev *slg51002 = + container_of(work, struct slg51002_dev, timeout_work); + slg51002_power_off(slg51002); +} + +static void slg51002_timer_trigger(struct timer_list *t) +{ + struct slg51002_dev *slg51002 = from_timer(slg51002, t, timer); + schedule_work(&slg51002->timeout_work); +} + +static int slg51002_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + int ret; + struct i2c_client *client = context; + struct slg51002_dev *slg51002 = i2c_get_clientdata(client); + + slg51002_power_on(slg51002); + ret = regmap_read(slg51002->i2c_regmap, reg, val); + mod_timer(&slg51002->timer, + jiffies + msecs_to_jiffies(TIMER_EXPIRED_MSEC)); + return ret; +} + +static int slg51002_reg_write(void *context, unsigned int reg, unsigned int val) +{ + int ret; + struct i2c_client *client = context; + struct slg51002_dev *slg51002 = i2c_get_clientdata(client); + + slg51002_power_on(slg51002); + ret = regmap_write(slg51002->i2c_regmap, reg, val); + mod_timer(&slg51002->timer, + jiffies + msecs_to_jiffies(TIMER_EXPIRED_MSEC)); + return ret; +} + +static int read_chip_id(struct slg51002_dev *chip) +{ + int ret; + uint8_t val[SLG51002_CHIP_ID_LEN]; + + if (chip == NULL) + return -EINVAL; + + ret = regmap_bulk_read(chip->regmap, + SLG51002_SYSCTL_PATN_ID_B0, val, ARRAY_SIZE(val)); + if (ret < 0) { + dev_err(chip->dev, "Failed to read chip id registers(%d)\n", + ret); + return ret; + } + + /* Format chip id */ + chip->chip_id = ((val[2] << 16) | (val[1] << 8) | val[0]); + dev_info(chip->dev, "chip_id: 0x%x\n", chip->chip_id); + + return ret; +} + +static ssize_t chip_id_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct slg51002_dev *chip; + + chip = dev_get_drvdata(dev); + if (chip == NULL) + return -EINVAL; + + return sysfs_emit(buf, "0x%x\n", chip->chip_id); +} +static DEVICE_ATTR_RO(chip_id); + +static ssize_t chip_always_on_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct slg51002_dev *chip; + + chip = dev_get_drvdata(dev); + if (chip == NULL) + return -EINVAL; + + return sysfs_emit(buf, "%d\n", chip->chip_always_on); +} + +static ssize_t chip_always_on_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct slg51002_dev *chip; + unsigned long val; + int ret; + + chip = dev_get_drvdata(dev); + + ret = kstrtoul(buf, 0, &val); + if (ret < 0) + return ret; + + chip->chip_always_on = val; + + if (chip->chip_always_on) { + slg51002_power_on(chip); + } else { + slg51002_power_off(chip); + } + + return count; +} +static DEVICE_ATTR_RW(chip_always_on); + +static struct attribute *slg51002_attrs[] = { + &dev_attr_chip_id.attr, + &dev_attr_chip_always_on.attr, + NULL, +}; +ATTRIBUTE_GROUPS(slg51002); + +static const struct regmap_config slg51002_i2c_regmap_config = { + .name = "i2c", + .reg_bits = 16, + .val_bits = 8, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_config slg51002_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x800F, + .wr_table = &slg51002_writeable_table, + .rd_table = &slg51002_readable_table, + .volatile_table = &slg51002_volatile_table, + .reg_read = slg51002_reg_read, + .reg_write = slg51002_reg_write, +}; + +static int slg51002_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct slg51002_dev *slg51002; + int gpio, ret; + struct pinctrl *pinctrl; + struct pinctrl_state *state; + + slg51002 = devm_kzalloc(&client->dev, + sizeof(struct slg51002_dev), GFP_KERNEL); + if (!slg51002) + return -ENOMEM; + + if (of_property_count_strings(client->dev.of_node, + "pinctrl-names") <= 0) { + dev_dbg(&client->dev, "no pinctrl defined\n"); + } else { + pinctrl = devm_pinctrl_get(&client->dev); + if (IS_ERR(pinctrl)) { + dev_err(&client->dev, "Cannot allocate pinctrl\n"); + return PTR_ERR(pinctrl); + } + + state = pinctrl_lookup_state(pinctrl, "active"); + if (IS_ERR(state)) { + dev_err(&client->dev, + "Cannot find pinctrl state: active\n"); + devm_pinctrl_put(pinctrl); + return PTR_ERR(state); + } + + ret = pinctrl_select_state(pinctrl, state); + if (ret) { + dev_err(&client->dev, "Cannot select state: active\n"); + return ret; + } + } + + /* optional property */ + gpio = of_get_named_gpio(client->dev.of_node, "dlg,bb-gpios", 0); + if (gpio_is_valid(gpio)) { + ret = devm_gpio_request_one(&client->dev, gpio, + GPIOF_OUT_INIT_HIGH, "slg51002_bb_pin"); + if (ret) { + dev_err(&client->dev, "GPIO(%d) request failed(%d)\n", + gpio, ret); + return ret; + } + + dev_dbg(&client->dev, "GPIO(%d) request (%d)\n", gpio, ret); + + slg51002->chip_bb_pin = gpio; + usleep_range(2000, 2020); + } + + /* optional property */ + gpio = of_get_named_gpio(client->dev.of_node, "dlg,buck-gpios", 0); + if (gpio_is_valid(gpio)) { + ret = devm_gpio_request_one(&client->dev, gpio, + GPIOF_OUT_INIT_HIGH, "slg51002_buck_pin"); + if (ret) { + dev_err(&client->dev, "GPIO(%d) request failed(%d)\n", + gpio, ret); + return ret; + } + + dev_dbg(&client->dev, "GPIO(%d) request (%d)\n", gpio, ret); + + slg51002->chip_buck_pin = gpio; + usleep_range(2000, 2020); + } + + /* mandatory property. It wakes the chip from low-power reset state */ + gpio = of_get_named_gpio(client->dev.of_node, "dlg,cs-gpios", 0); + if (gpio_is_valid(gpio)) { + ret = devm_gpio_request_one(&client->dev, gpio, + GPIOF_OUT_INIT_HIGH, "slg51002_cs_pin"); + if (ret) { + dev_err(&client->dev, "GPIO(%d) request failed(%d)\n", + gpio, ret); + return ret; + } + + slg51002->chip_cs_pin = gpio; + + /* + * According to datasheet, turn-on time from CS HIGH to Ready + * state is ~10ms + */ + usleep_range(SLEEP_10000_USEC, + SLEEP_10000_USEC + SLEEP_RANGE_USEC); + } else { + return gpio; + } + + i2c_set_clientdata(client, slg51002); + + slg51002->chip_always_on = false; + slg51002->is_power_on = true; + INIT_WORK(&slg51002->timeout_work, slg51002_timeout_work); + timer_setup(&slg51002->timer, slg51002_timer_trigger, 0); + mutex_init(&slg51002->pwr_lock); + + slg51002->chip_irq = client->irq; + slg51002->dev = &client->dev; + slg51002->chip_id = 0; + + slg51002->i2c_regmap = devm_regmap_init_i2c(client, &slg51002_i2c_regmap_config); + if (IS_ERR(slg51002->i2c_regmap)) { + ret = PTR_ERR(slg51002->i2c_regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + goto out; + } + + slg51002->regmap = devm_regmap_init(&client->dev, NULL, client, &slg51002_regmap_config); + if (IS_ERR(slg51002->regmap)) { + ret = PTR_ERR(slg51002->regmap); + dev_err(&client->dev, "Failed to allocate register map: %d\n", + ret); + goto out; + } + + ret = of_property_read_u32(slg51002->dev->of_node, + "dlg,op-mode", &slg51002->op_mode); + if (ret < 0) + slg51002->op_mode = SLG51002_OP_MODE_LDO_GPIO; + + dev_dbg(slg51002->dev, "op_mode: %d\n", slg51002->op_mode); + + slg51002->enter_sw_test_mode = slg51002_enter_sw_test_mode; + slg51002->exit_sw_test_mode = slg51002_exit_sw_test_mode; + + ret = slg51002_config_tuning(slg51002); + if (ret < 0) { + dev_info(slg51002->dev, "No config tuning(%d)\n", ret); + } + + /* optional property */ + gpio = of_get_named_gpio(client->dev.of_node, "dlg,pu-gpios", 0); + if (gpio_is_valid(gpio)) { + ret = devm_gpio_request_one(&client->dev, gpio, + GPIOF_OUT_INIT_HIGH, "slg51002_pu_pin"); + if (ret) { + dev_err(&client->dev, "GPIO(%d) request failed(%d)\n", + gpio, ret); + goto out; + } + + dev_dbg(&client->dev, "GPIO(%d) request (%d)\n", gpio, ret); + + slg51002->chip_pu_pin = gpio; + usleep_range(1000, 1020); + } + + slg51002_clear_fault_log(slg51002); + + ret = read_chip_id(slg51002); + if (ret < 0) + goto out; + + slg51002->gpio_op_on_sw_test_mode = !(slg51002->chip_id == REVISION_AB); + + return devm_mfd_add_devices(slg51002->dev, -1, slg51002_devs, + ARRAY_SIZE(slg51002_devs), NULL, 0, NULL); + +out: + mutex_destroy(&slg51002->pwr_lock); + del_timer_sync(&slg51002->timer); + return ret; +} + +static int slg51002_i2c_remove(struct i2c_client *client) +{ + struct slg51002_dev *slg51002 = i2c_get_clientdata(client); + struct gpio_desc *desc; + int ret = 0; + + mfd_remove_devices(slg51002->dev); + mutex_destroy(&slg51002->pwr_lock); + del_timer_sync(&slg51002->timer); + + if (gpio_is_valid(slg51002->chip_pu_pin)) { + desc = gpio_to_desc(slg51002->chip_pu_pin); + ret |= gpiod_direction_output_raw(desc, GPIOF_INIT_LOW); + usleep_range(1000, 1020); + } + if (gpio_is_valid(slg51002->chip_cs_pin)) { + desc = gpio_to_desc(slg51002->chip_cs_pin); + ret |= gpiod_direction_output_raw(desc, GPIOF_INIT_LOW); + /* Put SLG51002 back to Reset state */ + usleep_range(SLEEP_10000_USEC, + SLEEP_10000_USEC + SLEEP_RANGE_USEC); + } + if (gpio_is_valid(slg51002->chip_buck_pin)) { + desc = gpio_to_desc(slg51002->chip_buck_pin); + ret |= gpiod_direction_output_raw(desc, GPIOF_INIT_LOW); + usleep_range(1000, 1020); + } + if (gpio_is_valid(slg51002->chip_bb_pin)) { + desc = gpio_to_desc(slg51002->chip_bb_pin); + ret |= gpiod_direction_output_raw(desc, GPIOF_INIT_LOW); + usleep_range(1000, 1020); + } + + return ret ? -EIO : 0; +} + +static const struct i2c_device_id slg51002_i2c_id[] = { + { "slg51002", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, slg51002_i2c_id); + +#if defined(CONFIG_OF) +static const struct of_device_id slg51002_of_match[] = { + { .compatible = "dlg,slg51002", }, + { }, +}; +MODULE_DEVICE_TABLE(of, slg51002_of_match); +#endif /* CONFIG_OF */ + +static struct i2c_driver slg51002_i2c_driver = { + .driver = { + .name = "slg51002", + .dev_groups = slg51002_groups, +#if defined(CONFIG_OF) + .of_match_table = of_match_ptr(slg51002_of_match), +#endif /* CONFIG_OF */ + }, + .probe = slg51002_i2c_probe, + .remove = slg51002_i2c_remove, + .id_table = slg51002_i2c_id, +}; + +static int __init slg51002_i2c_init(void) +{ + return i2c_add_driver(&slg51002_i2c_driver); +} +/* init early so consumer devices can complete system boot */ +subsys_initcall(slg51002_i2c_init); + +static void __exit slg51002_i2c_exit(void) +{ + i2c_del_driver(&slg51002_i2c_driver); +} +module_exit(slg51002_i2c_exit); + +MODULE_DESCRIPTION("slg51002 multi-function core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index acb1d6fa771b..1ae24bdc2794 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -65,4 +65,4 @@ obj-$(CONFIG_GOOGLE_VOTABLE) += gvotable.o obj-$(CONFIG_SBB_MUX) += sbb-mux/ obj-$(CONFIG_SUBSYSTEM_COREDUMP) += sscoredump/ obj-$(CONFIG_ACCESS_RAMOOPS) += access_ramoops.o -obj-$(CONFIG_SENSORS_SSP_BBD) += bbdpl/ +obj-$(CONFIG_BCM_GPS_SPI_DRIVER) += bbdpl/ diff --git a/drivers/misc/bbdpl/Kconfig b/drivers/misc/bbdpl/Kconfig index a706e668c003..e8bd67cc22cb 100644 --- a/drivers/misc/bbdpl/Kconfig +++ b/drivers/misc/bbdpl/Kconfig @@ -1,16 +1,6 @@ -config SENSORS_SSP_BBD - tristate "SSP Driver for sensor hub" - depends on SPI - help - ssp driver for sensor hub. - If you say yes here you get ssp support for - sensor hub. - To compile this driver as a module, choose M here: the - module will be called bbd. - config BCM_GPS_SPI_DRIVER tristate "BRCM GPS SPI driver" - depends on SPI && SENSORS_SSP_BBD + depends on SPI help Support for BRCM GPS SPI driver. diff --git a/drivers/misc/bbdpl/Makefile b/drivers/misc/bbdpl/Makefile index 2beddfeb18af..954e940f6b82 100644 --- a/drivers/misc/bbdpl/Makefile +++ b/drivers/misc/bbdpl/Makefile @@ -1,5 +1,2 @@ - obj-$(CONFIG_BCM_GPS_SPI_DRIVER) += bcm47765.o -bcm47765-objs+= bcm_gps_regs.o bcm_gps_spi.o - -obj-$(CONFIG_SENSORS_SSP_BBD) += bbd.o +bcm47765-objs+= bcm_gps_regs.o bcm_gps_spi.o bbd.o diff --git a/drivers/misc/bbdpl/bbd.c b/drivers/misc/bbdpl/bbd.c index 51e817955d34..9d62f37f7e07 100644 --- a/drivers/misc/bbdpl/bbd.c +++ b/drivers/misc/bbdpl/bbd.c @@ -10,25 +10,19 @@ #include #include -#include -#include #include #include #include #include -#include #include #include #include #include #include "bbd.h" -#ifdef CONFIG_SENSORS_SSP +#if IS_ENABLED(CONFIG_SENSORS_SSP) #include /* Needs because SSP is tightly coupled with SPI */ - extern struct spi_driver *pssp_driver; -extern bool ssp_dbg; -extern bool ssp_pkt_dbg; static const struct spi_device dummy_spi = { .dev = { @@ -37,58 +31,6 @@ static const struct spi_device dummy_spi = { }; #endif -#if IS_ENABLED(CONFIG_BCM_GPS_SPI_DRIVER) -bool ssi_dbg; -EXPORT_SYMBOL_GPL(ssi_dbg); -bool ssi_dbg_pzc = true; /* SHOULD BE TRUE */ -EXPORT_SYMBOL_GPL(ssi_dbg_pzc); -bool ssi_dbg_rng; -EXPORT_SYMBOL_GPL(ssi_dbg_rng); -#endif /* IS_ENABLED(CONFIG_BCM_GPS_SPI_DRIVER) */ - - -#ifdef BBD_PWR_STATUS -struct gnss_pwrstats { - bool gps_stat; - u64 gps_on_cnt; - u64 gps_on_duration; - u64 gps_on_entry; - u64 gps_on_exit; - u64 gps_off_cnt; - u64 gps_off_duration; - u64 gps_off_entry; - u64 gps_off_exit; -}; -#endif /* BBD_PWR_STATUS */ - -#define BBD_BUFF_SIZE (PAGE_SIZE*2) -struct bbd_cdev_priv { - const char *name; - struct cdev dev; /* char device */ - bool busy; - struct circ_buf read_buf; /* LHD reads from BBD */ - struct mutex lock; /* Lock for read_buf */ - char _read_buf[BBD_BUFF_SIZE]; /* LHD reads from BBD */ - char write_buf[BBD_BUFF_SIZE]; /* LHD writes into BBD */ - wait_queue_head_t poll_wait; /* for poll */ -#ifdef BBD_PWR_STATUS - struct gnss_pwrstats pwrstats; /* GNSS power state */ -#endif /* BBD_PWR_STATUS */ -}; - -struct bbd_device { - struct class *class; /* for device_create */ - - struct bbd_cdev_priv priv[BBD_DEVICE_INDEX];/* individual structures */ - bool db; /* debug flag */ - - void *ssp_priv; /* private data pointer */ - struct bbd_callbacks *ssp_cb; /* callbacks for SSP */ - - bool legacy_patch; /* check for using legacy_bbd_patch */ - dev_t dev_num; /* device number */ -}; - /* Character device names of BBD */ static const char *bbd_dev_name[BBD_DEVICE_INDEX] = { "bbd_shmd", @@ -100,28 +42,23 @@ static const char *bbd_dev_name[BBD_DEVICE_INDEX] = { #endif /* BBD_PWR_STATUS */ }; -/* - * The global BBD device which has all necessary information. - * It's not beautiful but useful when we debug by Trace32. - */ -static struct bbd_device bbd; /* TODO(b/170369951): remove global variable */ - /* Embedded patch file provided as /dev/bbd_patch */ -static unsigned char bbd_patch[] = { +static const unsigned char bbd_patch[] = { }; #ifdef CONFIG_SENSORS_BBD_LEGACY_PATCH -static unsigned char legacy_bbd_patch[] = { +static const unsigned char legacy_bbd_patch[] = { #include "legacy_bbd_patch_file.h" }; #else -static unsigned char legacy_bbd_patch[] = { +static const unsigned char legacy_bbd_patch[] = { "mock", }; #endif /* Function to push read data into any bbd device's read buf */ -ssize_t bbd_on_read(unsigned int minor, const unsigned char *buf, size_t size); +ssize_t bbd_on_read(struct bbd_device *bbd, unsigned int minor, + const unsigned char *buf, size_t size); #ifdef DEBUG_1HZ_STAT @@ -138,28 +75,31 @@ static const char *bbd_stat_name[STAT_MAX] = { "rx@lhd" }; -struct bbd_stat stat1hz; /* TODO remove global variable */ - /* * BBD 1hz Statistics Functions */ -static void bbd_init_stat(void) +static void bbd_init_stat(struct bbd_device *bbd) { - memset(&stat1hz, 0, sizeof(stat1hz)); + struct bbd_stat *stat1hz = &bbd->stat1hz; + + memset(stat1hz, 0, sizeof(*stat1hz)); - stat1hz.min_rx_lat = (u64)-1; - stat1hz.min_rx_dur = (u64)-1; - stat1hz.workq = create_singlethread_workqueue("BBD_1HZ_TICK"); + stat1hz->bbd = bbd; + stat1hz->min_rx_lat = (u64)-1; + stat1hz->min_rx_dur = (u64)-1; + stat1hz->workq = create_singlethread_workqueue("BBD_1HZ_TICK"); } -static void bbd_exit_stat(void) +static void bbd_exit_stat(struct bbd_device *bbd) { - bbd_disable_stat(); - if (stat1hz.workq) { - flush_workqueue(stat1hz.workq); - destroy_workqueue(stat1hz.workq); - stat1hz.workq = 0; + struct bbd_stat *stat1hz = &bbd->stat1hz; + + bbd_disable_stat(bbd); + if (stat1hz->workq) { + flush_workqueue(stat1hz->workq); + destroy_workqueue(stat1hz->workq); + stat1hz->workq = 0; } } @@ -169,6 +109,7 @@ static void bbd_report_stat(struct work_struct *work) char *buf; int i; int count = 0; + struct bbd_stat *stat1hz = container_of(work, struct bbd_stat, work); buf = kvmalloc_array(MAX_SIZE, sizeof(char), GFP_KERNEL); if (!buf) @@ -177,73 +118,80 @@ static void bbd_report_stat(struct work_struct *work) count += scnprintf(buf + count, MAX_SIZE - count, "BBD:"); for (i = 0; i < STAT_MAX; i++) { count += scnprintf(buf + count, MAX_SIZE - count, " %s=%llu", - bbd_stat_name[i], stat1hz.stat[i]); + bbd_stat_name[i], stat1hz->stat[i]); } count += scnprintf(buf + count, MAX_SIZE - count, " rxlat_min=%llu rxlat_max=%llu", - stat1hz.min_rx_lat, stat1hz.max_rx_lat); + stat1hz->min_rx_lat, stat1hz->max_rx_lat); count += scnprintf(buf + count, MAX_SIZE - count, " rxdur_min=%llu rxdur_max=%llu", - stat1hz.min_rx_dur, stat1hz.max_rx_dur); + stat1hz->min_rx_dur, stat1hz->max_rx_dur); /* report only in case we had SSI traffic */ - if (stat1hz.stat[STAT_TX_SSI] || stat1hz.stat[STAT_RX_SSI]) - bbd_on_read(BBD_MINOR_CONTROL, buf, strlen(buf) + 1); + if (stat1hz->stat[STAT_TX_SSI] || stat1hz->stat[STAT_RX_SSI]) + bbd_on_read(stat1hz->bbd, BBD_MINOR_CONTROL, buf, count); for (i = 0; i < STAT_MAX; i++) - stat1hz.stat[i] = 0; + stat1hz->stat[i] = 0; - stat1hz.min_rx_lat = (u64)-1; - stat1hz.min_rx_dur = (u64)-1; - stat1hz.max_rx_lat = 0; - stat1hz.max_rx_dur = 0; + stat1hz->min_rx_lat = (u64)-1; + stat1hz->min_rx_dur = (u64)-1; + stat1hz->max_rx_lat = 0; + stat1hz->max_rx_dur = 0; kvfree(buf); } -static void bbd_stat_timer_func(unsigned long p) +static void bbd_stat_timer_func(struct timer_list *t) { - if (stat1hz.workq) - queue_work(stat1hz.workq, &stat1hz.work); - mod_timer(&stat1hz.timer, jiffies + HZ); + struct bbd_stat *stat1hz = container_of(t, struct bbd_stat, timer); + if (stat1hz->workq) + queue_work(stat1hz->workq, &stat1hz->work); + mod_timer(&stat1hz->timer, jiffies + HZ); } -void bbd_update_stat(int idx, unsigned int count) +void bbd_update_stat(struct bbd_device *bbd, + int idx, unsigned int count) { - stat1hz.stat[idx] += count; + struct bbd_stat *stat1hz = &bbd->stat1hz; + stat1hz->stat[idx] += count; } +EXPORT_SYMBOL_GPL(bbd_update_stat); -void bbd_enable_stat(void) +void bbd_enable_stat(struct bbd_device *bbd) { - if (stat1hz.enabled) { - pr_info("1HZ stat already enable. skipping.\n"); + struct bbd_stat *stat1hz = &bbd->stat1hz; + if (stat1hz->enabled) { + pr_debug("1HZ stat already enable. skipping.\n"); return; } - INIT_WORK(&stat1hz.work, bbd_report_stat); - setup_timer(&stat1hz.timer, bbd_stat_timer_func, 0); - mod_timer(&stat1hz.timer, jiffies + HZ); - stat1hz.enabled = true; + INIT_WORK(&stat1hz->work, bbd_report_stat); + timer_setup(&stat1hz->timer, bbd_stat_timer_func, 0); + mod_timer(&stat1hz->timer, jiffies + HZ); + stat1hz->enabled = true; } +EXPORT_SYMBOL_GPL(bbd_enable_stat); -void bbd_disable_stat(void) +void bbd_disable_stat(struct bbd_device *bbd) { - if (!stat1hz.enabled) { - pr_info("1HZ stat already disabled. skipping.\n"); + struct bbd_stat *stat1hz = &bbd->stat1hz; + if (!stat1hz->enabled) { + pr_debug("1HZ stat already disabled. skipping.\n"); return; } - del_timer_sync(&stat1hz.timer); - cancel_work_sync(&stat1hz.work); - stat1hz.enabled = false; + del_timer_sync(&stat1hz->timer); + cancel_work_sync(&stat1hz->work); + stat1hz->enabled = false; } +EXPORT_SYMBOL_GPL(bbd_disable_stat); #endif /* DEBUG_1HZ_STAT */ -static void bbd_log_hex(const char *prefix_str, - const unsigned char *buf, - size_t len) +static void bbd_log_hex(bool log_enabled, const char *prefix_str, + const unsigned char *buf, size_t len) { - if (likely(!bbd.db)) + if (likely(!log_enabled)) return; if (!prefix_str) @@ -256,90 +204,90 @@ static void bbd_log_hex(const char *prefix_str, /** * bbd_control - Handles command string from lhd */ -ssize_t bbd_control(const char *buf, ssize_t len) +static ssize_t bbd_control(struct bbd_device *bbd, const char *buf, ssize_t len) { #ifdef DEBUG_1HZ_STAT pr_info("%s\n", buf); #endif - if (!strcmp(buf, ESW_CTRL_READY)) { - if (bbd.ssp_cb && bbd.ssp_cb->on_mcu_ready) - bbd.ssp_cb->on_mcu_ready(bbd.ssp_priv, true); - } else if (!strcmp(buf, ESW_CTRL_NOTREADY)) { - struct circ_buf *circ = &bbd.priv[BBD_MINOR_SENSOR].read_buf; + if (strstr(buf, ESW_CTRL_READY)) { + if (bbd->ssp_cb && bbd->ssp_cb->on_mcu_ready) + bbd->ssp_cb->on_mcu_ready(bbd->ssp_priv, true); + } else if (strstr(buf, ESW_CTRL_NOTREADY)) { + struct circ_buf *circ = &bbd->priv[BBD_MINOR_SENSOR].read_buf; circ->head = circ->tail = 0; - if (bbd.ssp_cb && bbd.ssp_cb->on_mcu_ready) - bbd.ssp_cb->on_mcu_ready(bbd.ssp_priv, false); - } else if (!strcmp(buf, ESW_CTRL_CRASHED)) { - struct circ_buf *circ = &bbd.priv[BBD_MINOR_SENSOR].read_buf; + if (bbd->ssp_cb && bbd->ssp_cb->on_mcu_ready) + bbd->ssp_cb->on_mcu_ready(bbd->ssp_priv, false); + } else if (strstr(buf, ESW_CTRL_CRASHED)) { + struct circ_buf *circ = &bbd->priv[BBD_MINOR_SENSOR].read_buf; circ->head = circ->tail = 0; - if (bbd.ssp_cb && bbd.ssp_cb->on_mcu_ready) - bbd.ssp_cb->on_mcu_ready(bbd.ssp_priv, false); - - if (bbd.ssp_cb && bbd.ssp_cb->on_control) - bbd.ssp_cb->on_control(bbd.ssp_priv, buf); - } else if (!strcmp(buf, BBD_CTRL_DEBUG_OFF)) { - bbd.db = false; -#ifdef CONFIG_SENSORS_SSP - } else if (!strcmp(buf, SSP_DEBUG_ON)) { - ssp_dbg = true; - ssp_pkt_dbg = true; - } else if (!strstr(buf, SSP_DEBUG_OFF)) { - ssp_dbg = false; - ssp_pkt_dbg = false; + if (bbd->ssp_cb && bbd->ssp_cb->on_mcu_ready) + bbd->ssp_cb->on_mcu_ready(bbd->ssp_priv, false); + + if (bbd->ssp_cb && bbd->ssp_cb->on_control) + bbd->ssp_cb->on_control(bbd->ssp_priv, buf); + } else if (strstr(buf, BBD_CTRL_DEBUG_ON)) { + bbd->db = true; + } else if (strstr(buf, BBD_CTRL_DEBUG_OFF)) { + bbd->db = false; +#if IS_ENABLED(CONFIG_SENSORS_SSP) + } else if (strstr(buf, SSP_DEBUG_ON)) { + bbd->ssp_dbg = true; + bbd->ssp_pkt_dbg = true; + } else if (strstr(buf, SSP_DEBUG_OFF)) { + bbd->ssp_dbg = false; + bbd->ssp_pkt_dbg = false; #endif -#if IS_ENABLED(CONFIG_BCM_GPS_SPI_DRIVER) - } else if (!strcmp(buf, SSI_DEBUG_ON)) { - ssi_dbg = true; - } else if (!strcmp(buf, SSI_DEBUG_OFF)) { - ssi_dbg = false; - } else if (!strcmp(buf, PZC_DEBUG_ON)) { - ssi_dbg_pzc = true; - } else if (!strcmp(buf, PZC_DEBUG_OFF)) { - ssi_dbg_pzc = false; - } else if (!strcmp(buf, RNG_DEBUG_ON)) { - ssi_dbg_rng = true; - } else if (!strcmp(buf, RNG_DEBUG_OFF)) { - ssi_dbg_rng = false; -#endif /* IS_ENABLED(CONFIG_BCM_GPS_SPI_DRIVER) */ + } else if (strstr(buf, SSI_DEBUG_ON)) { + bbd->ssi_dbg = true; + } else if (strstr(buf, SSI_DEBUG_OFF)) { + bbd->ssi_dbg = false; + } else if (strstr(buf, PZC_DEBUG_ON)) { + bbd->ssi_dbg_pzc = true; + } else if (strstr(buf, PZC_DEBUG_OFF)) { + bbd->ssi_dbg_pzc = false; + } else if (strstr(buf, RNG_DEBUG_ON)) { + bbd->ssi_dbg_rng = true; + } else if (strstr(buf, RNG_DEBUG_OFF)) { + bbd->ssi_dbg_rng = false; #ifdef BBD_PWR_STATUS - } else if (!strcmp(buf, GPSD_CORE_ON)) { + } else if (strstr(buf, GPSD_CORE_ON)) { u64 now = ktime_to_us(ktime_get_boottime()); struct gnss_pwrstats *pwrstats = - &bbd.priv[BBD_MINOR_PWRSTAT].pwrstats; + &bbd->priv[BBD_MINOR_PWRSTAT].pwrstats; - mutex_lock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); + mutex_lock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); pwrstats->gps_stat = STAT_GPS_ON; pwrstats->gps_on_cnt++; pwrstats->gps_on_entry = now; pwrstats->gps_off_exit = now; pwrstats->gps_off_duration += - pwrstats->gps_off_exit - pwrstats->gps_off_entry; + pwrstats->gps_off_exit - pwrstats->gps_off_entry; - mutex_unlock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); - } else if (!strcmp(buf, GPSD_CORE_OFF)) { + mutex_unlock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); + } else if (strstr(buf, GPSD_CORE_OFF)) { u64 now = ktime_to_us(ktime_get_boottime()); struct gnss_pwrstats *pwrstats = - &bbd.priv[BBD_MINOR_PWRSTAT].pwrstats; + &bbd->priv[BBD_MINOR_PWRSTAT].pwrstats; - mutex_lock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); + mutex_lock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); pwrstats->gps_stat = STAT_GPS_OFF; pwrstats->gps_off_cnt++; pwrstats->gps_off_entry = now; pwrstats->gps_on_exit = now; pwrstats->gps_on_duration += - pwrstats->gps_on_exit - pwrstats->gps_on_entry; + pwrstats->gps_on_exit - pwrstats->gps_on_entry; - mutex_unlock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); + mutex_unlock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); #endif /* BBD_PWR_STATUS */ - } else if (bbd.ssp_cb && bbd.ssp_cb->on_control) { + } else if (bbd->ssp_cb && bbd->ssp_cb->on_control) { /* Tell SHMD about the unknown control string */ - bbd.ssp_cb->on_control(bbd.ssp_priv, buf); + bbd->ssp_cb->on_control(bbd->ssp_priv, buf); } return len; @@ -352,23 +300,27 @@ ssize_t bbd_control(const char *buf, ssize_t len) /** * bbd_common_open - Common open function for BBD devices */ -int bbd_common_open(struct inode *inode, struct file *filp) +static int bbd_common_open(struct inode *inode, struct file *filp) { + struct cdev *cdev = inode->i_cdev; + struct bbd_cdev_priv *bbd_cdev = + container_of(cdev, struct bbd_cdev_priv, cdev); + unsigned int minor = iminor(inode); - struct circ_buf *circ = &bbd.priv[minor].read_buf; + struct circ_buf *circ = &bbd_cdev->read_buf; if (minor >= BBD_DEVICE_INDEX) return -ENODEV; - if (bbd.priv[minor].busy && minor != BBD_MINOR_CONTROL) + if (bbd_cdev->busy && minor != BBD_MINOR_CONTROL) return -EBUSY; - bbd.priv[minor].busy = true; + bbd_cdev->busy = true; /* Reset circ buffer */ circ->head = circ->tail = 0; - filp->private_data = &bbd; + filp->private_data = bbd_cdev->bbd; return 0; } @@ -378,6 +330,7 @@ int bbd_common_open(struct inode *inode, struct file *filp) */ static int bbd_common_release(struct inode *inode, struct file *filp) { + struct bbd_device *bbd = filp->private_data; unsigned int minor = iminor(inode); if (minor >= BBD_DEVICE_INDEX) { @@ -385,10 +338,10 @@ static int bbd_common_release(struct inode *inode, struct file *filp) return 0; } #ifdef DEBUG_1HZ_STAT - pr_info("%s", bbd.priv[minor].name); + pr_info("%s", bbd_dev_name[minor]); #endif - bbd.priv[minor].busy = false; + bbd->priv[minor].busy = false; return 0; } @@ -402,8 +355,9 @@ static int bbd_common_release(struct inode *inode, struct file *filp) static ssize_t bbd_common_read( struct file *filp, char __user *buf, size_t size, loff_t *ppos) { + struct bbd_device *bbd = filp->private_data; unsigned int minor = iminor(filp->f_path.dentry->d_inode); - struct circ_buf *circ = &bbd.priv[minor].read_buf; + struct circ_buf *circ = &bbd->priv[minor].read_buf; size_t rd_size = 0; if (minor >= BBD_DEVICE_INDEX) { @@ -411,7 +365,7 @@ static ssize_t bbd_common_read( goto out; } - mutex_lock(&bbd.priv[minor].lock); + mutex_lock(&bbd->priv[minor].lock); /* * Copy from circ buffer to lhd @@ -425,7 +379,7 @@ static ssize_t bbd_common_read( if (copy_to_user(buf + rd_size, (void *) circ->buf + circ->tail, copied)) { - mutex_unlock(&bbd.priv[minor].lock); + mutex_unlock(&bbd->priv[minor].lock); rd_size = -EFAULT; goto out; } @@ -436,12 +390,12 @@ static ssize_t bbd_common_read( } while (size > 0 && CIRC_CNT(circ->head, circ->tail, BBD_BUFF_SIZE)); - mutex_unlock(&bbd.priv[minor].lock); + mutex_unlock(&bbd->priv[minor].lock); - bbd_log_hex(bbd_dev_name[minor], buf, rd_size); + bbd_log_hex(bbd->db, bbd_dev_name[minor], buf, rd_size); #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_RX_LHD, rd_size); + bbd_update_stat(bbd, STAT_RX_LHD, rd_size); #endif out: return rd_size; @@ -454,18 +408,19 @@ static ssize_t bbd_common_read( static ssize_t bbd_common_write( struct file *filp, const char __user *buf, size_t size, loff_t *ppos) { + struct bbd_device *bbd = filp->private_data; unsigned int minor = iminor(filp->f_path.dentry->d_inode); if (size >= BBD_BUFF_SIZE) return -EFAULT; - if (copy_from_user(bbd.priv[minor].write_buf, buf, size)) { + if (copy_from_user(bbd->priv[minor].write_buf, buf, size)) { pr_err("failed to copy from user.\n"); return -EFAULT; } #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_TX_LHD, size); + bbd_update_stat(bbd, STAT_TX_LHD, size); #endif return size; } @@ -475,14 +430,15 @@ static ssize_t bbd_common_write( */ static unsigned int bbd_common_poll(struct file *filp, poll_table *wait) { + struct bbd_device *bbd = filp->private_data; unsigned int minor = iminor(filp->f_path.dentry->d_inode); - struct circ_buf *circ = &bbd.priv[minor].read_buf; + struct circ_buf *circ = &bbd->priv[minor].read_buf; unsigned int mask = 0; if (minor >= BBD_DEVICE_INDEX) return POLLNVAL; - poll_wait(filp, &bbd.priv[minor].poll_wait, wait); + poll_wait(filp, &bbd->priv[minor].poll_wait, wait); if (CIRC_CNT(circ->head, circ->tail, BBD_BUFF_SIZE)) mask |= POLLIN; @@ -494,36 +450,6 @@ static unsigned int bbd_common_poll(struct file *filp, poll_table *wait) * BBD Device Specific File Functions */ -/** - * bbd_sensor_write - BBD's RPC calls this function to send sensor packet - * - * @buf: contains sensor packet coming from gpsd/lhd - * - */ -ssize_t bbd_sensor_write(const char *buf, size_t size) -{ - /* - * Copies into /dev/bbd_shmd. If SHMD was sleeping in poll_wait, - * bbd_on_read() wakes it up also - */ - bbd_on_read(BBD_MINOR_SHMD, buf, size); - -#ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_RX_SSP, size); -#endif - /* OK. Now call pre-registered SHMD callbacks */ - if (bbd.ssp_cb->on_packet) - bbd.ssp_cb->on_packet(bbd.ssp_priv, - bbd.priv[BBD_MINOR_SHMD].write_buf, size); - else if (bbd.ssp_cb->on_packet_alarm) - bbd.ssp_cb->on_packet_alarm(bbd.ssp_priv); - else - pr_err("no SSP on_packet callback registered. Dropped %zd bytes\n", - size); - - /* TODO why return size without modified */ - return size; -} /** * bbd_control_write - Write function for BBD control (/dev/bbd_control) @@ -534,6 +460,7 @@ ssize_t bbd_sensor_write(const char *buf, size_t size) ssize_t bbd_control_write( struct file *filp, const char __user *buf, size_t size, loff_t *ppos) { + struct bbd_device *bbd = filp->private_data; unsigned int minor = iminor(filp->f_path.dentry->d_inode); /* get command string first */ @@ -543,7 +470,7 @@ ssize_t bbd_control_write( return len; /* Process received command string */ - return bbd_control(bbd.priv[minor].write_buf, len); + return bbd_control(bbd, bbd->priv[minor].write_buf, len); } ssize_t bbd_patch_read( @@ -552,7 +479,7 @@ ssize_t bbd_patch_read( ssize_t rd_size = size; size_t offset = filp->f_pos; struct bbd_device *bbd = filp->private_data; - unsigned char *curr_bbd_patch; + const unsigned char *curr_bbd_patch; size_t bbd_patch_sz; if (bbd->legacy_patch) { @@ -587,9 +514,10 @@ ssize_t bbd_pwrstat_read( char buf2[BBD_MAX_PWRSTAT_SIZE]; int ret = 0; u64 now, gps_on_dur, gps_off_dur; - struct gnss_pwrstats *pwrstats = &bbd.priv[BBD_MINOR_PWRSTAT].pwrstats; + struct bbd_device *bbd = filp->private_data; + struct gnss_pwrstats *pwrstats = &bbd->priv[BBD_MINOR_PWRSTAT].pwrstats; - mutex_lock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); + mutex_lock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); now = ktime_to_us(ktime_get_boottime()); if (pwrstats->gps_stat == STAT_GPS_ON) { @@ -626,40 +554,11 @@ ssize_t bbd_pwrstat_read( "last_exit_timestamp_usec: 0x%0llx\n", pwrstats->gps_off_exit); - mutex_unlock(&bbd.priv[BBD_MINOR_PWRSTAT].lock); + mutex_unlock(&bbd->priv[BBD_MINOR_PWRSTAT].lock); return simple_read_from_buffer(buf, size, ppos, buf2, ret); } #endif /* BBD_PWR_STATUS */ - -static ssize_t bbd_store( - struct device *dev, struct device_attribute *attr, - const char *buf, size_t len) -{ - bbd_control(buf, strlen(buf) + 1); - return len; -} - -static ssize_t pl_show( - struct device *dev, struct device_attribute *attr, char *buf) -{ - - return 0; -} - -static DEVICE_ATTR_WO(bbd); -static DEVICE_ATTR_RO(pl); - -static struct attribute *bbd_attributes[] = { - &dev_attr_bbd.attr, - &dev_attr_pl.attr, - NULL -}; - -static const struct attribute_group bbd_group = { - .attrs = bbd_attributes, -}; - /** * * bbd_on_read - Push data into read buffer of specified char device. @@ -667,14 +566,15 @@ static const struct attribute_group bbd_group = { * * @buf: linear buffer */ -ssize_t bbd_on_read(unsigned int minor, const unsigned char *buf, size_t size) +ssize_t bbd_on_read(struct bbd_device *bbd, unsigned int minor, + const unsigned char *buf, size_t size) { - struct circ_buf *circ = &bbd.priv[minor].read_buf; + struct circ_buf *circ = &bbd->priv[minor].read_buf; size_t wr_size = 0; - bbd_log_hex(bbd_dev_name[minor], buf, size); + bbd_log_hex(bbd->db, bbd_dev_name[minor], buf, size); - mutex_lock(&bbd.priv[minor].lock); + mutex_lock(&bbd->priv[minor].lock); /* If there's not enough speace, drop it but try waking up reader */ if (CIRC_SPACE(circ->head, circ->tail, BBD_BUFF_SIZE) < size) { @@ -699,11 +599,10 @@ ssize_t bbd_on_read(unsigned int minor, const unsigned char *buf, size_t size) } while (size > 0 && CIRC_SPACE(circ->head, circ->tail, BBD_BUFF_SIZE)); skip: - mutex_unlock(&bbd.priv[minor].lock); + mutex_unlock(&bbd->priv[minor].lock); /* Wake up reader */ - wake_up(&bbd.priv[minor].poll_wait); - + wake_up(&bbd->priv[minor].poll_wait); return wr_size; } @@ -712,13 +611,13 @@ ssize_t bbd_on_read(unsigned int minor, const unsigned char *buf, size_t size) * PM Operation Functions */ -static int bbd_suspend(pm_message_t state) +static int bbd_suspend(struct bbd_device *bbd, pm_message_t state) { #ifdef DEBUG_1HZ_STAT - bbd_disable_stat(); + bbd_disable_stat(bbd); #endif -#ifdef CONFIG_SENSORS_SSP +#if IS_ENABLED(CONFIG_SENSORS_SSP) /* Call SSP suspend */ if (pssp_driver->driver.pm && pssp_driver->driver.pm->suspend) pssp_driver->driver.pm->suspend(&dummy_spi.dev); @@ -733,15 +632,15 @@ static int bbd_suspend(pm_message_t state) return 0; } -static int bbd_resume(void) +static int bbd_resume(struct bbd_device *bbd) { -#ifdef CONFIG_SENSORS_SSP +#if IS_ENABLED(CONFIG_SENSORS_SSP) /* Call SSP resume */ if (pssp_driver->driver.pm && pssp_driver->driver.pm->suspend) pssp_driver->driver.pm->resume(&dummy_spi.dev); #endif #ifdef DEBUG_1HZ_STAT - bbd_enable_stat(); + bbd_enable_stat(bbd); #endif return 0; } @@ -749,24 +648,21 @@ static int bbd_resume(void) static int bbd_notifier( struct notifier_block *nb, unsigned long event, void *data) { + struct bbd_device *bbd = container_of(nb, struct bbd_device, notifier); pm_message_t state = {0}; switch (event) { case PM_SUSPEND_PREPARE: state.event = event; - bbd_suspend(state); + bbd_suspend(bbd, state); break; case PM_POST_SUSPEND: - bbd_resume(); + bbd_resume(bbd); break; } return NOTIFY_OK; } -static struct notifier_block bbd_notifier_block = { - .notifier_call = bbd_notifier, -}; - /* * BBD Device Init and Exit Functions */ @@ -817,56 +713,58 @@ static const struct file_operations bbd_fops[BBD_DEVICE_INDEX] = { }; -int bbd_init(struct device *dev, bool legacy_patch) +struct bbd_device *bbd_init(struct device *dev, bool legacy_patch) { int minor, ret = -ENOMEM; struct timespec64 ts1; unsigned long start, elapsed; - + struct bbd_device *bbd; ts1 = ktime_to_timespec64(ktime_get_boottime()); start = ts1.tv_sec * 1000000000ULL + ts1.tv_nsec; /* Initialize BBD device */ - memset(&bbd, 0, sizeof(bbd)); /* TODO don't use global */ + bbd = kvzalloc(sizeof(struct bbd_device), GFP_KERNEL); + if (!bbd) { + ret = -ENOMEM; + goto exit; + } - bbd.legacy_patch = legacy_patch; + bbd->legacy_patch = legacy_patch; /* * Allocate device major number for this BBD device * Starts minor number from 1 to ignore BBD SHMD device */ - ret = alloc_chrdev_region(&bbd.dev_num, 1, BBD_DEVICE_INDEX, "bbd"); + ret = alloc_chrdev_region(&bbd->dev_num, 1, BBD_DEVICE_INDEX, "bbd"); if (ret) { pr_err("failed to alloc_chrdev_region(), ret=%d", ret); goto exit; } /* Create class which is required for device_create() */ - bbd.class = class_create(THIS_MODULE, "bbd"); - if (IS_ERR(bbd.class)) { + bbd->class = class_create(THIS_MODULE, "bbd"); + if (IS_ERR(bbd->class)) { pr_err("failed to create class bbd\n"); goto exit; } /* Create BBD char devices */ for (minor = 0; minor < BBD_DEVICE_INDEX; minor++) { - dev_t devno = MKDEV(MAJOR(bbd.dev_num), minor); - struct cdev *cdev = &bbd.priv[minor].dev; - const char *name = bbd_dev_name[minor]; - struct device *dev; + struct bbd_cdev_priv *bbd_cdev = &bbd->priv[minor]; /* Init buf, waitqueue, mutex, etc. */ - bbd.priv[minor].name = bbd_dev_name[minor]; - bbd.priv[minor].read_buf.buf = bbd.priv[minor]._read_buf; + bbd_cdev->bbd = bbd; + bbd_cdev->devno = MKDEV(MAJOR(bbd->dev_num), minor); + bbd_cdev->read_buf.buf = bbd_cdev->_read_buf; - init_waitqueue_head(&bbd.priv[minor].poll_wait); - mutex_init(&bbd.priv[minor].lock); + init_waitqueue_head(&bbd_cdev->poll_wait); + mutex_init(&bbd_cdev->lock); #ifdef BBD_PWR_STATUS /* Initial power stats */ - memset(&bbd.priv[minor].pwrstats, 0, sizeof(struct gnss_pwrstats)); - bbd.priv[minor].pwrstats.gps_off_cnt = 1; + memset(&bbd->priv[minor].pwrstats, 0, sizeof(struct gnss_pwrstats)); + bbd->priv[minor].pwrstats.gps_off_cnt = 1; #endif /* BBD_PWR_STATUS */ /* Don't register /dev/bbd_shmd */ @@ -877,40 +775,41 @@ int bbd_init(struct device *dev, bool legacy_patch) * Register cdev which relates above * device number with this BBD device */ - cdev_init(cdev, &bbd_fops[minor]); - cdev->owner = THIS_MODULE; - cdev->ops = &bbd_fops[minor]; - ret = cdev_add(cdev, devno, 1); + cdev_init(&bbd_cdev->cdev, &bbd_fops[minor]); + bbd_cdev->cdev.owner = THIS_MODULE; + bbd_cdev->cdev.ops = &bbd_fops[minor]; + ret = cdev_add(&bbd_cdev->cdev, bbd_cdev->devno, 1); if (ret) { pr_err("failed to cdev_add() \"%s\", ret=%d", - name, ret); - unregister_chrdev_region(devno, 1); + bbd_dev_name[minor], ret); + unregister_chrdev_region(bbd_cdev->devno, 1); goto free_class; } /* Let it show in FS */ - dev = device_create(bbd.class, NULL, devno, NULL, "%s", name); + bbd_cdev->dev = device_create(bbd->class, NULL, + bbd_cdev->devno, bbd, "%s", bbd_dev_name[minor]); if (IS_ERR_OR_NULL(dev)) { pr_err("failed to device_create() \"%s\", ret = %d", - name, ret); - unregister_chrdev_region(devno, 1); - cdev_del(&bbd.priv[minor].dev); + bbd_dev_name[minor], ret); + unregister_chrdev_region(bbd_cdev->devno, 1); + cdev_del(&bbd_cdev->cdev); goto free_class; } /* Done. Put success log and init BBD specific fields */ pr_info("(%d,%d) registered /dev/%s\n", - MAJOR(bbd.dev_num), minor, name); - + MAJOR(bbd->dev_num), minor, bbd_dev_name[minor]); } + bbd->notifier.notifier_call = bbd_notifier; /* Register PM */ - ret = register_pm_notifier(&bbd_notifier_block); + ret = register_pm_notifier(&bbd->notifier); if (ret) goto free_class; -#ifdef CONFIG_SENSORS_SSP +#if IS_ENABLED(CONFIG_SENSORS_SSP) /* Now, we can initialize SSP */ if (device_register(&dummy_spi.dev)) goto free_class; @@ -929,55 +828,57 @@ int bbd_init(struct device *dev, bool legacy_patch) pr_info("%lu nsec elapsed\n", elapsed); #ifdef DEBUG_1HZ_STAT - bbd_init_stat(); + bbd_init_stat(bbd); #endif - return 0; + return bbd; free_class: while (--minor > BBD_MINOR_SHMD) { - dev_t devno = MKDEV(MAJOR(bbd.dev_num), minor); - struct cdev *cdev = &bbd.priv[minor].dev; + dev_t devno = MKDEV(MAJOR(bbd->dev_num), minor); + struct cdev *cdev = &bbd->priv[minor].cdev; - device_destroy(bbd.class, devno); + device_destroy(bbd->class, devno); cdev_del(cdev); unregister_chrdev_region(devno, 1); } - class_destroy(bbd.class); + class_destroy(bbd->class); exit: - return ret; + kvfree(bbd); + return NULL; } EXPORT_SYMBOL_GPL(bbd_init); -void bbd_exit(void) +void bbd_exit(struct device *dev) { + struct bbd_device *bbd = dev_get_drvdata(dev); int minor; -#ifdef CONFIG_SENSORS_SSP +#if IS_ENABLED(CONFIG_SENSORS_SSP) /* Shutdown SSP first*/ pssp_driver->shutdown(&dummy_spi); #endif /* Remove BBD char devices */ for (minor = BBD_MINOR_SENSOR; minor < BBD_DEVICE_INDEX; minor++) { - dev_t devno = MKDEV(MAJOR(bbd.dev_num), minor); - struct cdev *cdev = &bbd.priv[minor].dev; - const char *name = bbd_dev_name[minor]; + struct bbd_cdev_priv *bbd_cdev = &bbd->priv[minor]; - device_destroy(bbd.class, devno); - cdev_del(cdev); - unregister_chrdev_region(devno, 1); + device_destroy(bbd->class, bbd_cdev->devno); + cdev_del(&bbd_cdev->cdev); + unregister_chrdev_region(bbd_cdev->devno, 1); pr_info("(%d,%d) unregistered /dev/%s\n", - MAJOR(bbd.dev_num), minor, name); + MAJOR(bbd->dev_num), minor, bbd_dev_name[minor]); } #ifdef DEBUG_1HZ_STAT - bbd_exit_stat(); + bbd_exit_stat(bbd); #endif /* Remove class */ - class_destroy(bbd.class); + class_destroy(bbd->class); + kvfree(bbd); } + EXPORT_SYMBOL_GPL(bbd_exit); MODULE_AUTHOR("Broadcom"); diff --git a/drivers/misc/bbdpl/bbd.h b/drivers/misc/bbdpl/bbd.h index f35b3f234e7d..977fbd674a61 100644 --- a/drivers/misc/bbdpl/bbd.h +++ b/drivers/misc/bbdpl/bbd.h @@ -8,6 +8,10 @@ #ifndef __BBD_H__ #define __BBD_H__ +#include +#include +#include + #define BBD_PWR_STATUS union long_union_t { @@ -55,7 +59,7 @@ enum { #define GPSD_CORE_ON "GPSD:CORE_ON" #define GPSD_CORE_OFF "GPSD:CORE_OFF" -/* #define DEBUG_1HZ_STAT */ +#define DEBUG_1HZ_STAT #define HSI_ERROR_STATUS 0x2C #define HSI_ERROR_STATUS_LPBK_ERROR 0x01 @@ -77,8 +81,11 @@ enum { #define HSI_STRM_FIFO_STATUS 0x40104100 #define HSI_CMND_FIFO_STATUS 0x40104104 -#ifdef DEBUG_1HZ_STAT +#define BBD_BUFF_SIZE (PAGE_SIZE * 2) + +struct bbd_device; +#ifdef DEBUG_1HZ_STAT enum { STAT_TX_LHD = 0, STAT_TX_SSP, @@ -95,8 +102,8 @@ enum { STAT_MAX }; - struct bbd_stat { + struct bbd_device *bbd; bool enabled; u64 ts_irq; @@ -114,11 +121,9 @@ struct bbd_stat { struct workqueue_struct *workq; }; -extern struct bbd_stat stat1hz; - -void bbd_update_stat(int index, unsigned int count); -void bbd_enable_stat(void); -void bbd_disable_stat(void); +void bbd_update_stat(struct bbd_device *bbd, int index, unsigned int count); +void bbd_enable_stat(struct bbd_device *bbd); +void bbd_disable_stat(struct bbd_device *bbd); #endif #ifdef BBD_PWR_STATUS @@ -127,7 +132,61 @@ enum { STAT_GPS_ON, STAT_GPS_MAX }; + +struct gnss_pwrstats { + bool gps_stat; + u64 gps_on_cnt; + u64 gps_on_duration; + u64 gps_on_entry; + u64 gps_on_exit; + u64 gps_off_cnt; + u64 gps_off_duration; + u64 gps_off_entry; + u64 gps_off_exit; +}; +#endif /* BBD_PWR_STATUS */ + +struct bbd_cdev_priv { + struct bbd_device *bbd; + struct cdev cdev; /* char device */ + struct device *dev; + dev_t devno; + bool busy; + struct circ_buf read_buf; /* LHD reads from BBD */ + struct mutex lock; /* Lock for read_buf */ + char _read_buf[BBD_BUFF_SIZE]; /* LHD reads from BBD */ + char write_buf[BBD_BUFF_SIZE]; /* LHD writes into BBD */ + wait_queue_head_t poll_wait; /* for poll */ +#ifdef BBD_PWR_STATUS + struct gnss_pwrstats pwrstats; /* GNSS power state */ #endif /* BBD_PWR_STATUS */ +}; + +struct bbd_device { + struct class *class; /* for device_create */ + +#ifdef DEBUG_1HZ_STAT + struct bbd_stat stat1hz; +#endif + struct notifier_block notifier; + + struct bbd_cdev_priv priv[BBD_DEVICE_INDEX];/* individual structures */ + + bool db; /* debug flag */ + bool ssi_dbg; + bool ssi_dbg_pzc; + bool ssi_dbg_rng; +#ifdef CONFIG_SENSORS_SSP + bool ssp_dbg; + bool ssp_pkt_dbg; +#endif + void *ssp_priv; /* private data pointer */ + struct bbd_callbacks *ssp_cb; /* callbacks for SSP */ + + bool legacy_patch; /* check for using legacy_bbd_patch */ + dev_t dev_num; /* device number */ +}; + /** callback for incoming data from 477x to senser hub driver **/ struct bbd_callbacks { @@ -138,10 +197,8 @@ struct bbd_callbacks { }; extern void bbd_register(void *ext_data, struct bbd_callbacks *pcallbacks); -extern ssize_t bbd_send_packet(unsigned char *buf, size_t size); -extern ssize_t bbd_pull_packet( - unsigned char *buf, size_t size, unsigned int timeout_ms); extern int bbd_mcu_reset(void); -extern int bbd_init(struct device *dev, bool legacy_patch); +extern struct bbd_device *bbd_init(struct device *dev, bool legacy_patch); +extern void bbd_exit(struct device *dev); #endif /* __BBD_H__ */ diff --git a/drivers/misc/bbdpl/bcm_gps_spi.c b/drivers/misc/bbdpl/bcm_gps_spi.c index 1c76bc90ed0d..bb53c92e22ff 100644 --- a/drivers/misc/bbdpl/bcm_gps_spi.c +++ b/drivers/misc/bbdpl/bcm_gps_spi.c @@ -38,45 +38,20 @@ #include "bbd.h" #include "bcm_gps_spi.h" -void bcm_on_packet_received( - void *_priv, unsigned char *data, unsigned int size); -extern void bbd_parse_asic_data(unsigned char *pucData, unsigned short usLen, - void (*to_gpsd)(unsigned char *packet, unsigned short len, - void *priv), void *priv); +/* 0 - Half Duplex, 1 - Full Duplex */ +#define SSI_MODE 1 -/* TODO remove global variables */ -extern bool ssi_dbg; -extern bool ssi_dbg_pzc; -extern bool ssi_dbg_rng; +/* 1 = 1B, 2 = 2B */ +#define SSI_LEN 2 -/* SPI Streaming Protocol Control */ -int g_bcm_bitrate = 12000; /* * TODO: Need to read bitrate from bus driver spi.c. * Just for startup info notification. */ +#define BCM_BITRATE 12000 -/* 0 - Half Duplex, 1 - Full Duplex (not supported yet) */ -int ssi_mode = 1; -/* 1 = 1B, 2 = 2B */ -int ssi_len = 2; -/* - * 0 - Flow Control Disabled, >0 - - * Flow Control Enabled and number of retries, 3 is preferred - */ -int ssi_fc = 3; -/* - * Calculating TX transfer failure operation in bus driver, - * reset in bcm_ssi_open() - */ -int ssi_tx_fail; -/* Calculating TX pzc retries, reset in bcm_ssi_open() */ -int ssi_tx_pzc_retries; -/* Calculating TX pzc retry delays, reset in bcm_ssi_open() */ -int ssi_tx_pzc_retry_delays; - -static unsigned long g_rx_buffer_avail_bytes = HSI_PZC_MAX_RX_BUFFER; -/* Should be more MAX_SPI_FRAME_LEN. See below */ +static void bcm_on_packet_received( + void *_priv, unsigned char *data, unsigned int size); static ssize_t nstandby_show( @@ -97,7 +72,7 @@ static ssize_t nstandby_store(struct device *dev, struct bcm_spi_priv *priv = spi_get_drvdata(spi); #ifdef DEBUG_1HZ_STAT - pr_info("nstandby, buf is %s\n", buf); + dev_dbg(dev, "nstandby, buf is %s\n", buf); #endif if (buf[0] == '0') @@ -127,7 +102,7 @@ static ssize_t sspmcureq_store(struct device *dev, struct spi_device *spi = to_spi_device(dev); struct bcm_spi_priv *priv = spi_get_drvdata(spi); - pr_debug("sspmcureq, buf is %s\n", buf); + dev_dbg(dev, "sspmcureq, buf is %s\n", buf); if (buf[0] == '0') gpio_set_value(priv->mcu_req, 0); @@ -149,21 +124,21 @@ void bcm_ssi_print_trans_stat(struct bcm_spi_priv *priv) { struct bcm_spi_transfer_stat *trans = &priv->trans_stat[0]; - pr_info("DBG SPI @ TX: <255B = %d, <1K = %d, <2K = %d, <4K = %d, <8K = %d, <16K = %d, <32K = %d, <64K = %d, total = %ld, min = %ld, max = %ld", + dev_info(&priv->spi->dev, "DBG SPI @ TX: <255B = %d, <1K = %d, <2K = %d, <4K = %d, <8K = %d, <16K = %d, <32K = %d, <64K = %d, total = %ld, min = %ld, max = %ld", trans->len_255, trans->len_1K, trans->len_2K, trans->len_4K, trans->len_8K, trans->len_16K, trans->len_32K, trans->len_64K, trans->len_total, trans->len_min, trans->len_max); trans = &priv->trans_stat[1]; - pr_info("DBG SPI @ RX: <255B = %d, <1K = %d, <2K = %d, <4K = %d, <8K = %d, <16K = %d, <32K = %d, <64K = %d, total = %ld, min = %ld, max = %ld", + dev_info(&priv->spi->dev, "DBG SPI @ RX: <255B = %d, <1K = %d, <2K = %d, <4K = %d, <8K = %d, <16K = %d, <32K = %d, <64K = %d, total = %ld, min = %ld, max = %ld", trans->len_255, trans->len_1K, trans->len_2K, trans->len_4K, trans->len_8K, trans->len_16K, trans->len_32K, trans->len_64K, trans->len_total, trans->len_min, trans->len_max); - pr_info("DBG SPI @ PZC: retries = %d, delays = %d", - ssi_tx_pzc_retries, ssi_tx_pzc_retry_delays); + dev_info(&priv->spi->dev, "DBG SPI @ PZC: retries = %d, delays = %d", + priv->ssi_tx_pzc_retries, priv->ssi_tx_pzc_retry_delays); } static void bcm_ssi_calc_trans_stat( @@ -201,7 +176,7 @@ static const unsigned long m_ulRxBufferBlockSize[4] = {32, 256, 1024 * 2, 1024 * static unsigned long bcm_ssi_chk_pzc(struct bcm_spi_priv *priv, unsigned char stat_byte, bool bprint) { - unsigned long rx_buffer_blk_bytes = + unsigned long rx_buffer_blk_bytes = m_ulRxBufferBlockSize[( stat_byte & HSI_F_MOSI_CTRL_SZE_MASK) >> HSI_F_MOSI_CTRL_SZE_SHIFT]; @@ -209,16 +184,16 @@ static unsigned long bcm_ssi_chk_pzc(struct bcm_spi_priv *priv, (unsigned long)((stat_byte & HSI_F_MOSI_CTRL_CNT_MASK) >> HSI_F_MOSI_CTRL_CNT_SHIFT); - g_rx_buffer_avail_bytes = rx_buffer_blk_bytes * rx_buffer_blk_counts; + priv->rx_buffer_avail_bytes = rx_buffer_blk_bytes * rx_buffer_blk_counts; if (!bprint) - return g_rx_buffer_avail_bytes; + return priv->rx_buffer_avail_bytes; if (stat_byte & HSI_F_MOSI_CTRL_PE_MASK) { - pr_debug("DBG SPI @ PZC: rx stat 0x%02x%s avail %lu", + dev_dbg(&priv->spi->dev, "DBG SPI @ PZC: rx stat 0x%02x%s avail %lu", stat_byte, stat_byte & HSI_F_MOSI_CTRL_PE_MASK ? "(PE)" : " ", - g_rx_buffer_avail_bytes); + priv->rx_buffer_avail_bytes); } #ifdef CONFIG_REG_IO @@ -229,7 +204,7 @@ static unsigned long bcm_ssi_chk_pzc(struct bcm_spi_priv *priv, HSI_ERROR_STATUS, ®val, 1); if (regval & HSI_ERROR_STATUS_STRM_FIFO_OVFL) - pr_err("(rx_strm_fifo_ovfl)"); + dev_err(&priv->spi->dev, "(rx_strm_fifo_ovfl)"); regval = HSI_ERROR_STATUS_ALL_ERRORS; bcm_dreg_write(priv, "HSI_ERROR_STATUS(W) ", @@ -237,7 +212,7 @@ static unsigned long bcm_ssi_chk_pzc(struct bcm_spi_priv *priv, } #endif /* CONFIG_REG_IO */ - return g_rx_buffer_avail_bytes; + return priv->rx_buffer_avail_bytes; } @@ -285,56 +260,54 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) filp->private_data = priv; #ifdef DEBUG_1HZ_STAT - bbd_enable_stat(); + bbd_enable_stat(priv->bbd); #endif strm = &priv->tx_strm; - strm->pckt_len = ssi_len == 2 ? 2 : 1; - len_mask = ssi_len == 2 ? SSI_PCKT_2B_LENGTH : SSI_PCKT_1B_LENGTH; - duplex_mask = - ssi_mode != 0 ? SSI_MODE_FULL_DUPLEX : SSI_MODE_HALF_DUPLEX; + strm->pckt_len = SSI_LEN == 2 ? 2 : 1; + len_mask = SSI_LEN == 2 ? SSI_PCKT_2B_LENGTH : SSI_PCKT_1B_LENGTH; + duplex_mask = SSI_MODE != 0 ? SSI_MODE_FULL_DUPLEX : SSI_MODE_HALF_DUPLEX; fc_mask = SSI_FLOW_CONTROL_DISABLED; strm->fc_len = 0; - if (ssi_mode == 0) { + if (SSI_MODE == 0) { /* SSI_MODE_HALF_DUPLEX; */ strm->pckt_len = 0; } /* 1 for tx cmd byte */ strm->ctrl_len = strm->pckt_len + strm->fc_len + 1; - strm->frame_len = ssi_len == 2 ? MAX_SPI_FRAME_LEN : MAX_SPI_DREG_FRAME_LEN; + strm->frame_len = SSI_LEN == 2 ? MAX_SPI_FRAME_LEN : MAX_SPI_DREG_FRAME_LEN; strm->ctrl_byte = duplex_mask | SSI_MODE_STREAM | len_mask | SSI_WRITE_TRANS | fc_mask; /* TX SPI Streaming Protocol in details */ #ifdef DEBUG_1HZ_STAT - pr_info("tx ctrl %02X: total %d = len %d + fc %d + cmd 1", + dev_info(&priv->spi->dev, "tx ctrl %02X: total %d = len %d + fc %d + cmd 1", strm->ctrl_byte, strm->ctrl_len, strm->pckt_len, strm->fc_len); #endif strm = &priv->rx_strm; - strm->pckt_len = ssi_len == 2 ? 2 : 1; + strm->pckt_len = SSI_LEN == 2 ? 2 : 1; strm->fc_len = 0; /* 1 for rx stat byte */ strm->ctrl_len = strm->pckt_len + strm->fc_len + 1; - strm->frame_len = ssi_len == 2 ? MAX_SPI_FRAME_LEN : MAX_SPI_DREG_FRAME_LEN; + strm->frame_len = SSI_LEN == 2 ? MAX_SPI_FRAME_LEN : MAX_SPI_DREG_FRAME_LEN; strm->ctrl_byte = duplex_mask | SSI_MODE_STREAM | len_mask | - (ssi_mode == SSI_MODE_FULL_DUPLEX ? + (SSI_MODE == SSI_MODE_FULL_DUPLEX ? SSI_WRITE_TRANS : SSI_READ_TRANS); /* RX SPI Streaming Protocol in details */ #ifdef DEBUG_1HZ_STAT - pr_info("rx ctrl %02X: total %d = len %d + fc %d + stat 1\n", + dev_info(&priv->spi->dev, "rx ctrl %02X: total %d = len %d + fc %d + stat 1\n", strm->ctrl_byte, strm->ctrl_len, strm->pckt_len, strm->fc_len); - pr_info("SPI @ %d: %s Duplex Strm mode, %dB Len, %s FC, Frame Len %u : tx ctrl %02X, rx ctrl %02X\n", - g_bcm_bitrate, - ssi_mode != 0 ? "Full" : "Half", - ssi_len == 2 ? 2:1, - "w/o", + dev_info(&priv->spi->dev, "SPI @ %d: %s Duplex Strm mode, %dB Len, w/o FC, Frame Len %u : tx ctrl %02X, rx ctrl %02X\n", + BCM_BITRATE, + SSI_MODE != 0 ? "Full" : "Half", + SSI_LEN == 2 ? 2 : 1, strm->frame_len, priv->tx_strm.ctrl_byte, priv->rx_strm.ctrl_byte); @@ -365,11 +338,11 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) bcm_ssi_print_trans_stat(priv); bcm_ssi_clear_trans_stat(priv); #endif - ssi_tx_fail = 0; - ssi_tx_pzc_retries = 0; - ssi_tx_pzc_retry_delays = 0; + priv->ssi_tx_fail = 0; + priv->ssi_tx_pzc_retries = 0; + priv->ssi_tx_pzc_retry_delays = 0; priv->ssi_pm_semaphore = 0; - g_rx_buffer_avail_bytes = HSI_PZC_MAX_RX_BUFFER; + priv->rx_buffer_avail_bytes = HSI_PZC_MAX_RX_BUFFER; return 0; } @@ -387,7 +360,7 @@ static int bcm_spi_release(struct inode *inode, struct file *filp) #ifdef DEBUG_1HZ_STAT - bbd_disable_stat(); + bbd_disable_stat(priv->bbd); #endif /* Disable irq */ spin_lock_irqsave(&priv->irq_lock, flags); @@ -422,7 +395,7 @@ static ssize_t bcm_spi_read( if (copy_to_user(buf + rd_size, circ->buf + circ->tail, copied)){ - pr_err("failed to copy to user.\n"); + dev_err(&priv->spi->dev, "failed to copy to user.\n"); mutex_unlock(&priv->rlock); return -EFAULT; } @@ -435,7 +408,7 @@ static ssize_t bcm_spi_read( mutex_unlock(&priv->rlock); #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_RX_LHD, rd_size); + bbd_update_stat(priv->bbd, STAT_RX_LHD, rd_size); #endif return rd_size; @@ -461,7 +434,7 @@ static ssize_t bcm_spi_write( if (copy_from_user(circ->buf + circ->head, buf + wr_size, copied)){ - pr_err("failed to copy from user.\n"); + dev_err(&priv->spi->dev, "failed to copy from user.\n"); mutex_unlock(&priv->wlock); return -EFAULT; } @@ -482,7 +455,7 @@ static ssize_t bcm_spi_write( (struct work_struct *)&priv->rxtx_work); #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_TX_LHD, wr_size); + bbd_update_stat(priv->bbd, STAT_TX_LHD, wr_size); #endif return wr_size; } @@ -559,7 +532,7 @@ static bool bcm477x_hello(struct bcm_spi_priv *priv) if (count++ > MAX_RESP_CHECK_COUNT) { gpio_set_value(priv->mcu_req, 0); #ifdef DEBUG_1HZ_STAT - pr_info(" MCU_REQ_RESP timeout. MCU_RESP(gpio%d) not responding to MCU_REQ(gpio%d)\n", + dev_err(&priv->spi->dev, " MCU_REQ_RESP timeout. MCU_RESP(gpio%d) not responding to MCU_REQ(gpio%d)\n", priv->mcu_resp, priv->mcu_req); #endif return false; @@ -582,7 +555,7 @@ static bool bcm477x_hello(struct bcm_spi_priv *priv) delta = bcm_clock_get_ms() - start_time; if (count > 100) - pr_info(" hello consumed %lu = clock_get_ms() - start_time; msec", + dev_err(&priv->spi->dev, "hello consumed %lu = clock_get_ms() - start_time; msec", delta); return true; @@ -597,11 +570,12 @@ static void bcm477x_bye(struct bcm_spi_priv *priv) gpio_set_value(priv->mcu_req, 0); } -static void pk_log(char *dir, unsigned char *data, int len) +static void pk_log(struct bcm_spi_priv *priv, char *dir, + unsigned char *data, int len) { const char ic = 'D'; - if (likely(!ssi_dbg)) + if (likely(!priv->bbd->ssi_dbg)) return; /* @@ -615,15 +589,13 @@ static void pk_log(char *dir, unsigned char *data, int len) * #1000001D w 0x68, 1: A1 * #1000001D r 0x68, 1: 00 */ - pr_info("#%06ld%c %2s, %5d: ", + dev_info(&priv->spi->dev, "#%06ld%c %2s,\t %5d: ", bcm_clock_get_ms() % 1000000, ic, dir, len); print_hex_dump(KERN_INFO, dir[0] == 'r' ? "r " : "w ", DUMP_PREFIX_NONE, 32, 1, data, len, false); } - - /* SSI tx/rx functions */ static unsigned short bcm_ssi_get_len( @@ -670,15 +642,15 @@ int bcm_spi_sync(struct bcm_spi_priv *priv, void *tx_buf, xfer.len = len; xfer.tx_buf = tx_buf; xfer.rx_buf = rx_buf; - xfer.bits_per_word = 8; /* bits_per_word; */ + xfer.bits_per_word = bits_per_word; /* Sync */ - pk_log("w", (unsigned char *)xfer.tx_buf, len); + pk_log(priv, "w", (unsigned char *)xfer.tx_buf, len); ret = spi_sync(msg.spi, &msg); - pk_log("r", (unsigned char *)xfer.rx_buf, len); + pk_log(priv, "r", (unsigned char *)xfer.rx_buf, len); if (ret) - pr_err(" spi_sync error for cmd:0x%x, return=%d\n", + dev_err(&priv->spi->dev, "spi_sync error for cmd:0x%x, return=%d\n", ((struct bcm_ssi_tx_frame *)xfer.tx_buf)->cmd, ret); return ret; @@ -713,7 +685,7 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) strm->ctrl_len, bits_per_word); if (ret) { - ssi_tx_fail++; + priv->ssi_tx_fail++; return ret; /* TODO: failure, operation should gets 0 to continue */ } @@ -724,7 +696,7 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) /* Just for understanding SPI Streaming Protocol */ if (m_write > frame_data_size) { /* The h/w malfunctioned ? */ - pr_err("@ TX m_write %d is h/w overflowed of frame %d...Fail\n", + dev_err(&priv->spi->dev, "@ TX m_write %d is h/w overflowed of frame %d...Fail\n", m_write, frame_data_size); } } @@ -734,7 +706,7 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) n_read = bcm_ssi_get_len(strm->ctrl_byte, rx->data); if (n_read > frame_data_size) { - pr_err("@ FD n_read %d is h/w overflowed of frame %d...Fail\n", + dev_err(&priv->spi->dev, "@ FD n_read %d is h/w overflowed of frame %d...Fail\n", n_read, frame_data_size); n_read = frame_data_size; } @@ -746,10 +718,6 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) n_read -= m_write; bytes_to_write -= m_write; data_p += (m_write + strm->fc_len); -#ifdef CONFIG_TRANSFER_STAT - bcm_ssi_calc_trans_stat(&priv->trans_stat[1], - m_write); -#endif } else { bytes_to_write = n_read; /* No data available next time */ @@ -760,10 +728,6 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) if (bytes_to_write != 0) { bcm_on_packet_received( priv, data_p, bytes_to_write); -#ifdef CONFIG_TRANSFER_STAT - bcm_ssi_calc_trans_stat(&priv->trans_stat[1], - bytes_to_write); -#endif } } @@ -773,12 +737,12 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) bcm_ssi_calc_trans_stat(&priv->trans_stat[0], bytes_written); #endif - bcm_ssi_chk_pzc(priv, rx->status, ssi_dbg_pzc); + bcm_ssi_chk_pzc(priv, rx->status, priv->bbd->ssi_dbg_pzc); return ret; } -int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) +static int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) { struct bcm_ssi_tx_frame *tx = priv->tx_buf; struct bcm_ssi_rx_frame *rx = priv->rx_buf; @@ -790,7 +754,7 @@ int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) size_t sz_to_recv = 0; #ifdef CONFIG_REG_IO - if (likely(ssi_dbg_rng) && + if (likely(priv->bbd->ssi_dbg_rng) && (priv->packet_received > CONFIG_PACKET_RECEIVED)) { u32 regval32[8]; @@ -810,7 +774,7 @@ int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) if (bcm_spi_sync(priv, tx, rx, ctrl_len, 8)) return -1; - bcm_ssi_chk_pzc(priv, rx->status, ssi_dbg_pzc); + bcm_ssi_chk_pzc(priv, rx->status, priv->bbd->ssi_dbg_pzc); payload_len = bcm_ssi_get_len(strm->ctrl_byte, rx->data); @@ -820,7 +784,7 @@ int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) * Needn't to use MAX_SPI_FRAME_LEN because don't * know how many bytes is ready to really read */ - pr_err("@ RX length is still read to 0. Set %d\n", payload_len); + dev_err(&priv->spi->dev, "@ RX length is still read to 0. Set %d\n", payload_len); return -1; } @@ -850,18 +814,10 @@ int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) if (payload_len < *length) *length = payload_len; -#ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_RX_SSI, *length); -#endif - -#ifdef CONFIG_TRANSFER_STAT - bcm_ssi_calc_trans_stat(&priv->trans_stat[1], *length); -#endif - return 0; } -void bcm_check_overrun(struct bcm_spi_priv *priv, size_t avail) +static void bcm_check_overrun(struct bcm_spi_priv *priv, size_t avail) { const long THRESHOLD_MS = 100; unsigned long curr_tick = bcm_clock_get_ms(); @@ -875,20 +831,28 @@ void bcm_check_overrun(struct bcm_spi_priv *priv, size_t avail) } if (priv->skip_count) - pr_err("%ld messages are skipped!\n", priv->skip_count); + dev_err(&priv->spi->dev, "%ld messages are skipped!\n", priv->skip_count); - pr_err("input overrun error by %zu bytes.\n", avail); + dev_err(&priv->spi->dev, "input overrun error by %zu bytes.\n", avail); priv->skip_count = 0; priv->last_tick = curr_tick; } -void bcm_on_packet_received(void *_priv, unsigned char *data, unsigned int size) +static void bcm_on_packet_received(void *_priv, unsigned char *data, + unsigned int size) { struct bcm_spi_priv *priv = (struct bcm_spi_priv *)_priv; struct circ_buf *rd_circ = &priv->read_buf; size_t written = 0, avail = size; +#ifdef DEBUG_1HZ_STAT + bbd_update_stat(priv->bbd, STAT_RX_SSI, size); +#endif +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_calc_trans_stat(&priv->trans_stat[1], size); +#endif + /* Copy into circ buffer */ mutex_lock(&priv->rlock); do { @@ -907,6 +871,7 @@ void bcm_on_packet_received(void *_priv, unsigned char *data, unsigned int size) priv->packet_received += size; mutex_unlock(&priv->rlock); + wake_up(&priv->poll_wait); bcm_check_overrun(priv, avail); } @@ -914,7 +879,7 @@ void bcm_on_packet_received(void *_priv, unsigned char *data, unsigned int size) void bcm477x_debug_info(struct bcm_spi_priv *priv) { int pin_ttyBCM, pin_MCU_REQ, pin_MCU_RESP; - int irq_enabled, irq_count; + int irq_enabled; if (!priv) return; @@ -924,21 +889,15 @@ void bcm477x_debug_info(struct bcm_spi_priv *priv) pin_MCU_RESP = gpio_get_value(priv->mcu_resp); irq_enabled = atomic_read(&priv->irq_enabled); - irq_count = kstat_irqs_cpu(priv->spi->irq, 0); - pr_info("pin_ttyBCM:%d, pin_MCU_REQ:%d, pin_MCU_RESP:%d\n", + dev_info(&priv->spi->dev, "pin_ttyBCM:%d, pin_MCU_REQ:%d, pin_MCU_RESP:%d\n", pin_ttyBCM, pin_MCU_REQ, pin_MCU_RESP); - pr_info("irq_enabled:%d, irq_count:%d\n", irq_enabled, irq_count); + dev_info(&priv->spi->dev, "irq_enabled:%d\n", irq_enabled); } #endif static void bcm_rxtx_work_func(struct work_struct *work) { -#ifdef DEBUG_1HZ_STAT - u64 ts_rx_start = 0; - u64 ts_rx_end = 0; - struct timespec64 ts; -#endif struct bcm_spi_priv *priv = container_of(work, struct bcm_spi_priv, rxtx_work); struct circ_buf *rd_circ = &priv->read_buf; @@ -948,10 +907,17 @@ static void bcm_rxtx_work_func(struct work_struct *work) int wait_for_pzc = 0; unsigned long flags; +#ifdef DEBUG_1HZ_STAT + u64 ts_rx_start = 0; + u64 ts_rx_end = 0; + struct timespec64 ts; + struct bbd_device *bbd = priv->bbd; +#endif + #ifdef CONFIG_MCU_WAKEUP if (!bcm477x_hello(priv)) { #ifdef DEBUG_1HZ_STAT - pr_err("hello timeout!!\n"); + dev_err(&priv->spi->dev, "hello timeout!!\n"); bcm477x_debug_info(priv); #endif return; @@ -966,7 +932,7 @@ static void bcm_rxtx_work_func(struct work_struct *work) /* Read first */ if (!gpio_is_valid(priv->host_req)) { - pr_err("gpio host_req is invalid, return\n"); + dev_err(&priv->spi->dev, "gpio host_req is invalid, return\n"); return; } ret = gpio_get_value(priv->host_req); @@ -974,7 +940,7 @@ static void bcm_rxtx_work_func(struct work_struct *work) if (ret || wait_for_pzc) { wait_for_pzc = 0; #ifdef DEBUG_1HZ_STAT - if (stat1hz.ts_irq) { + if (bbd->stat1hz.ts_irq) { ts = ktime_to_timespec64(ktime_get_boottime()); ts_rx_start = ts.tv_sec * 1000000000ULL + ts.tv_nsec; @@ -986,7 +952,6 @@ static void bcm_rxtx_work_func(struct work_struct *work) break; #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_RX_SSI, avail); if (ts_rx_start && !gpio_get_value(priv->host_req)) { ts = ktime_to_timespec64(ktime_get_boottime()); ts_rx_end = ts.tv_sec * 1000000000ULL @@ -1022,32 +987,30 @@ static void bcm_rxtx_work_func(struct work_struct *work) * SWGNSSGLL-15521 : Sometimes LHD does not write data * because the following code blocks sending data to MCU * Code is commented out because - * 'g_rx_buffer_avail_bytes'(PZC) is calculated in + * 'rx_buffer_avail_bytes'(PZC) is calculated in * bcm_ssi_tx() inside loop in work queue * (bcm_rxtx_work_func) below this code. - * It means 'g_rx_buffer_avail_bytes' doesn't reflect + * It means 'rx_buffer_avail_bytes' doesn't reflect * real available bytes in RX DMA RING buffer when * work queue will be restarted * because MCU is working independently from host. - * The 'g_rx_buffer_avail_bytes' can be tested inside + * The 'rx_buffer_avail_bytes' can be tested inside * bcm_ssi_tx but it may not guarantee correct * condition also. * SWGNSSGLL-16290 : FC detecting was broken when buffer * is overflow Using PZC for a software workaround to * not get into fifo overflow condition. */ - if (avail > g_rx_buffer_avail_bytes) { - g_rx_buffer_avail_bytes ? ssi_tx_pzc_retries++ : - ssi_tx_pzc_retry_delays++; - pr_debug("%d PZC %s, wr CIRC_CNT %lu, RNGDMA_RX %lu\n", - g_rx_buffer_avail_bytes ? - ssi_tx_pzc_retries : - ssi_tx_pzc_retry_delays, - g_rx_buffer_avail_bytes ? - "writes":"delays", + if (avail > priv->rx_buffer_avail_bytes) { + priv->rx_buffer_avail_bytes ? priv->ssi_tx_pzc_retries++ : + priv->ssi_tx_pzc_retry_delays++; + dev_dbg(&priv->spi->dev, "%d PZC %s, wr CIRC_CNT %lu, RNGDMA_RX %lu\n", + priv->rx_buffer_avail_bytes ? + priv->ssi_tx_pzc_retries : priv->ssi_tx_pzc_retry_delays, + priv->rx_buffer_avail_bytes ? "writes":"delays", avail, - g_rx_buffer_avail_bytes); - if (g_rx_buffer_avail_bytes == 0) { + priv->rx_buffer_avail_bytes); + if (priv->rx_buffer_avail_bytes == 0) { /* *RNGDMA_RX is full ? * If it's YES keep reading @@ -1058,7 +1021,7 @@ static void bcm_rxtx_work_func(struct work_struct *work) HSI_RNGDMA_RX_SW_ADDR_OFFSET, regval32, 3); } - avail = g_rx_buffer_avail_bytes; + avail = priv->rx_buffer_avail_bytes; usleep_range(1000, 2000); /* * TODO: increase delay for waiting for @@ -1111,7 +1074,7 @@ static void bcm_rxtx_work_func(struct work_struct *work) wake_up(&priv->poll_wait); } #ifdef DEBUG_1HZ_STAT - bbd_update_stat(STAT_TX_SSI, written); + bbd_update_stat(bbd, STAT_TX_SSI, written); #endif } while (!atomic_read(&priv->suspending) && @@ -1133,19 +1096,19 @@ static void bcm_rxtx_work_func(struct work_struct *work) spin_unlock_irqrestore(&priv->irq_lock, flags); #ifdef DEBUG_1HZ_STAT - if (stat1hz.ts_irq && ts_rx_start && ts_rx_end) { - u64 lat = ts_rx_start - stat1hz.ts_irq; + if (bbd->stat1hz.ts_irq && ts_rx_start && ts_rx_end) { + u64 lat = ts_rx_start - bbd->stat1hz.ts_irq; u64 dur = ts_rx_end - ts_rx_start; - stat1hz.min_rx_lat = (lat < stat1hz.min_rx_lat) ? - lat : stat1hz.min_rx_lat; - stat1hz.max_rx_lat = (lat > stat1hz.max_rx_lat) ? - lat : stat1hz.max_rx_lat; - stat1hz.min_rx_dur = (dur < stat1hz.min_rx_dur) ? - dur : stat1hz.min_rx_dur; - stat1hz.max_rx_dur = (dur > stat1hz.max_rx_dur) ? - dur : stat1hz.max_rx_dur; - stat1hz.ts_irq = 0; + bbd->stat1hz.min_rx_lat = (lat < bbd->stat1hz.min_rx_lat) ? + lat : bbd->stat1hz.min_rx_lat; + bbd->stat1hz.max_rx_lat = (lat > bbd->stat1hz.max_rx_lat) ? + lat : bbd->stat1hz.max_rx_lat; + bbd->stat1hz.min_rx_dur = (dur < bbd->stat1hz.min_rx_dur) ? + dur : bbd->stat1hz.min_rx_dur; + bbd->stat1hz.max_rx_dur = (dur > bbd->stat1hz.max_rx_dur) ? + dur : bbd->stat1hz.max_rx_dur; + bbd->stat1hz.ts_irq = 0; } #endif } @@ -1160,10 +1123,12 @@ static irqreturn_t bcm_irq_handler(int irq, void *pdata) return IRQ_HANDLED; #ifdef DEBUG_1HZ_STAT { - struct timespec ts; + struct bbd_device *bbd = priv->bbd; + + struct timespec64 ts; ts = ktime_to_timespec64(ktime_get_boottime()); - stat1hz.ts_irq = ts.tv_sec * 1000000000ULL + ts.tv_nsec; + bbd->stat1hz.ts_irq = ts.tv_sec * 1000000000ULL + ts.tv_nsec; } #endif /* Disable irq */ @@ -1189,7 +1154,7 @@ static int gps_initialize_pinctrl(struct bcm_spi_priv *data) /* Get pinctrl if target uses pinctrl */ data->ts_pinctrl = devm_pinctrl_get(dev); if (IS_ERR_OR_NULL(data->ts_pinctrl)) { - pr_err("Target does not use pinctrl\n"); + dev_err(&data->spi->dev, "Target does not use pinctrl\n"); ret = PTR_ERR(data->ts_pinctrl); data->ts_pinctrl = NULL; return ret; @@ -1198,7 +1163,7 @@ static int gps_initialize_pinctrl(struct bcm_spi_priv *data) data->gpio_state_active = pinctrl_lookup_state(data->ts_pinctrl, "gps_active"); if (IS_ERR_OR_NULL(data->gpio_state_active)) { - pr_err("Can not get ts default pinstate\n"); + dev_err(&data->spi->dev, "Can not get ts default pinstate\n"); ret = PTR_ERR(data->gpio_state_active); data->ts_pinctrl = NULL; return ret; @@ -1207,7 +1172,7 @@ static int gps_initialize_pinctrl(struct bcm_spi_priv *data) data->gpio_state_suspend = pinctrl_lookup_state(data->ts_pinctrl, "gps_suspend"); if (IS_ERR_OR_NULL(data->gpio_state_suspend)) { - pr_err("Can not get ts sleep pinstate\n"); + dev_err(&data->spi->dev, "Can not get ts sleep pinstate\n"); ret = PTR_ERR(data->gpio_state_suspend); data->ts_pinctrl = NULL; return ret; @@ -1225,12 +1190,12 @@ static int gps_pinctrl_select(struct bcm_spi_priv *data, bool on) if (!IS_ERR_OR_NULL(pins_state)) { ret = pinctrl_select_state(data->ts_pinctrl, pins_state); if (ret) { - pr_err("can not set %s pins\n", + dev_err(&data->spi->dev, "can not set %s pins\n", on ? "gps_active" : "gps_suspend"); return ret; } } else { - pr_err("not a valid '%s' pinstate\n", + dev_err(&data->spi->dev, "not a valid '%s' pinstate\n", on ? "gps_active" : "gps_suspend"); } @@ -1300,11 +1265,9 @@ static void bcm_spi_shutdown(struct spi_device *spi) spin_unlock_irqrestore(&priv->irq_lock, flags); - flush_workqueue(priv->serial_wq); destroy_workqueue(priv->serial_wq); priv->serial_wq = NULL; - } static int bcm_spi_probe(struct spi_device *spi) @@ -1320,10 +1283,10 @@ static int bcm_spi_probe(struct spi_device *spi) /* Check GPIO# */ #ifndef CONFIG_OF - pr_err("Check platform_data for bcm device\n"); + dev_err(&spi->dev, "Check platform_data for bcm device\n"); #else if (!spi->dev.of_node) { - pr_err("Failed to find of_node\n"); + dev_err(&spi->dev, "Failed to find of_node\n"); goto err_exit; } #endif @@ -1339,22 +1302,22 @@ static int bcm_spi_probe(struct spi_device *spi) "ssp-legacy-patch"); #endif - pr_info("ssp-host-req=%d, ssp-mcu_req=%d, ssp-mcu-resp=%d nstandby=%d \n", + dev_info(&spi->dev, "ssp-host-req=%d, ssp-mcu_req=%d, ssp-mcu-resp=%d nstandby=%d \n", host_req, mcu_req, mcu_resp, nstandby); if (host_req < 0 || mcu_req < 0 || mcu_resp < 0 || nstandby < 0) { - pr_err("GPIO value not correct\n"); + dev_err(&spi->dev, "GPIO value not correct\n"); goto err_exit; } /* Check IRQ# */ ret = gpio_request(host_req, "HOST REQ"); if (ret) { - pr_err("failed to request HOST REQ, ret:%d", ret); + dev_err(&spi->dev, "failed to request HOST REQ, ret:%d", ret); goto err_exit; } spi->irq = gpio_to_irq(host_req); if (spi->irq < 0) { - pr_err("irq=%d for host_req=%d not correct\n", + dev_err(&spi->dev, "irq=%d for host_req=%d not correct\n", spi->irq, host_req); goto err_exit; } @@ -1362,35 +1325,35 @@ static int bcm_spi_probe(struct spi_device *spi) /* Config GPIO */ ret = gpio_request(mcu_req, "MCU REQ"); if (ret) { - pr_err("failed to request MCU REQ, ret:%d", ret); + dev_err(&spi->dev, "failed to request MCU REQ, ret:%d", ret); goto err_exit; } ret = gpio_direction_output(mcu_req, 0); if (ret) { - pr_err("failed set MCU REQ as input mode, ret:%d", + dev_err(&spi->dev, "failed set MCU REQ as input mode, ret:%d", ret); goto err_exit; } ret = gpio_request(mcu_resp, "MCU RESP"); if (ret) { - pr_err("failed to request MCU RESP, ret:%d", ret); + dev_err(&spi->dev, "failed to request MCU RESP, ret:%d", ret); goto err_exit; } ret = gpio_direction_input(mcu_resp); if (ret) { - pr_err("failed set MCU RESP as input mode, ret:%d", + dev_err(&spi->dev, "failed set MCU RESP as input mode, ret:%d", ret); goto err_exit; } ret = gpio_request(nstandby, "GPS NSTANDBY"); if (ret) { - pr_err("failed to request GPS NSTANDBY, ret:%d", ret); + dev_err(&spi->dev, "failed to request GPS NSTANDBY, ret:%d", ret); goto err_exit; } ret = gpio_direction_output(nstandby, 0); if (ret) { - pr_err("failed set GPS NSTANDBY as out mode, ret:%d", + dev_err(&spi->dev, "failed set GPS NSTANDBY as out mode, ret:%d", ret); goto err_exit; } @@ -1400,12 +1363,12 @@ static int bcm_spi_probe(struct spi_device *spi) if (gps_power >= 0) { ret = gpio_request(gps_power, "GPS POWER"); if (ret) { - pr_err("failed to request GPS POWER, ret:%d", ret); + dev_err(&spi->dev, "failed to request GPS POWER, ret:%d", ret); goto err_exit; } ret = gpio_direction_output(gps_power, 1); if (ret) { - pr_err("failed set GPS POWER as out mode, ret:%d", ret); + dev_err(&spi->dev, "failed set GPS POWER as out mode, ret:%d", ret); goto err_exit; } } @@ -1417,18 +1380,17 @@ static int bcm_spi_probe(struct spi_device *spi) priv->skip_validity_check = skip_validity_check; priv->spi = spi; - priv->tx_buf = devm_kmalloc(&spi->dev, sizeof(struct bcm_ssi_tx_frame), GFP_KERNEL); - priv->rx_buf = devm_kmalloc(&spi->dev, sizeof(struct bcm_ssi_rx_frame), GFP_KERNEL); - if (!priv->tx_buf || !priv->rx_buf) { - pr_err("Failed to allocate xfer buffer. tx_buf=%p, rx_buf=%p\n", - priv->tx_buf, priv->rx_buf); + priv->tx_buf = devm_kmalloc(&spi->dev, + sizeof(struct bcm_ssi_tx_frame), GFP_KERNEL); + priv->rx_buf = devm_kmalloc(&spi->dev, + sizeof(struct bcm_ssi_rx_frame), GFP_KERNEL); + if (!priv->tx_buf || !priv->rx_buf) goto err_exit; - } priv->serial_wq = alloc_workqueue("bcm477x_wq", WQ_HIGHPRI|WQ_UNBOUND|WQ_MEM_RECLAIM, 1); if (!priv->serial_wq) { - pr_err("Failed to allocate workqueue\n"); + dev_err(&spi->dev, "Failed to allocate workqueue\n"); goto err_exit; } /* Init - pinctrl */ @@ -1438,14 +1400,14 @@ static int bcm_spi_probe(struct spi_device *spi) ret = devm_request_irq(&spi->dev, spi->irq, bcm_irq_handler, IRQF_TRIGGER_HIGH, "ttyBCM", priv); if (ret) { - pr_err("Failed to register BCM477x SPI TTY IRQ %d.\n", + dev_err(&spi->dev, "Failed to register BCM477x SPI TTY IRQ %d.\n", spi->irq); goto free_wq; } disable_irq(spi->irq); - pr_notice("Probe OK. ssp-host-req=%d, irq=%d, priv=0x%p\n", + dev_info(&spi->dev, "Probe OK. ssp-host-req=%d, irq=%d, priv=0x%pK\n", host_req, spi->irq, priv); /* Register misc device */ @@ -1455,7 +1417,7 @@ static int bcm_spi_probe(struct spi_device *spi) ret = misc_register(&priv->misc); if (ret) { - pr_err("Failed to register bcm_gps_spi's misc dev. err=%d\n", ret); + dev_err(&spi->dev, "Failed to register bcm_gps_spi's misc dev. err=%d\n", ret); goto free_wq; } @@ -1485,12 +1447,15 @@ static int bcm_spi_probe(struct spi_device *spi) priv->nstandby = nstandby; /* Init BBD & SSP */ - bbd_init(&spi->dev, legacy_patch); + priv->bbd = bbd_init(&spi->dev, legacy_patch); + if (priv->bbd == NULL) + goto free_wq; + if (device_create_file(&priv->spi->dev, &dev_attr_nstandby)) - pr_err("Unable to create sysfs 4775 nstandby entry"); + dev_err(&spi->dev, "Unable to create sysfs 4775 nstandby entry"); if (device_create_file(&priv->spi->dev, &dev_attr_sspmcureq)) - pr_err("Unable to create sysfs 4775 sspmcureq entry"); + dev_err(&spi->dev, "Unable to create sysfs 4775 sspmcureq entry"); return 0; @@ -1521,14 +1486,14 @@ static int bcm_spi_remove(struct spi_device *spi) destroy_workqueue(priv->serial_wq); if (priv->ts_pinctrl) { if (gps_pinctrl_select(priv, false) < 0) - pr_err("Cannot get idle pinctrl state\n"); + dev_err(&priv->spi->dev, "Cannot get idle pinctrl state\n"); } /* Free everything */ - device_remove_file(&priv->spi->dev, &dev_attr_nstandby); + bbd_exit(&spi->dev); + device_remove_file(&priv->spi->dev, &dev_attr_nstandby); device_remove_file(&priv->spi->dev, &dev_attr_sspmcureq); - return 0; } @@ -1581,5 +1546,3 @@ module_init(bcm_spi_init); module_exit(bcm_spi_exit); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("BCM SPI/SSI Driver"); - - diff --git a/drivers/misc/bbdpl/bcm_gps_spi.h b/drivers/misc/bbdpl/bcm_gps_spi.h index f40d4e7f690f..f2869c230217 100644 --- a/drivers/misc/bbdpl/bcm_gps_spi.h +++ b/drivers/misc/bbdpl/bcm_gps_spi.h @@ -139,6 +139,8 @@ struct bcm_ssi_rx_frame { unsigned char data[MAX_SPI_FRAME_LEN-1]; } __attribute__((__packed__)); +struct bbd_device; + struct bcm_spi_priv { struct spi_device *spi; @@ -198,6 +200,20 @@ struct bcm_spi_priv { /* Overrun counter */ unsigned long skip_count; unsigned long last_tick; + + /* + * Calculating TX transfer failure operation in bus driver, + * reset in bcm_ssi_open() + */ + int ssi_tx_fail; + /* Calculating TX pzc retries, reset in bcm_ssi_open() */ + int ssi_tx_pzc_retries; + /* Calculating TX pzc retry delays, reset in bcm_ssi_open() */ + int ssi_tx_pzc_retry_delays; + + unsigned long rx_buffer_avail_bytes;// = HSI_PZC_MAX_RX_BUFFER; + /* Should be more MAX_SPI_FRAME_LEN. See below */ + struct bbd_device *bbd; }; /* bcm_gps_regs.cpp */ @@ -211,12 +227,7 @@ int bcm_ireg_read(struct bcm_spi_priv *priv, char *id, unsigned int regaddr, unsigned int *regval, int n); /* bcm_gps_spi.cpp */ -struct bcm_spi_priv *bcm_get_bcm_gps(void); -void bcm_ssi_print_trans_stat(struct bcm_spi_priv *priv); -void bcm_ssi_clear_trans_stat(struct bcm_spi_priv *priv); -int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length); int bcm_spi_sync(struct bcm_spi_priv *priv, void *tx_buf, void *rx_buf, int len, int bits_per_word); -unsigned long bcm_clock_get_ms(void); #endif /* __BBD_H__ */ diff --git a/drivers/misc/logbuffer.c b/drivers/misc/logbuffer.c index 49538cff3a62..c200592ded7a 100644 --- a/drivers/misc/logbuffer.c +++ b/drivers/misc/logbuffer.c @@ -32,10 +32,11 @@ struct logbuffer { struct miscdevice misc; char name[50]; + uint suspend_count; }; -/* Device suspended since last logged. */ -static bool suspend_since_last_logged; +/* Driver suspended count. */ +static uint driver_suspended_count; /* Log index for logbuffer_logk */ static atomic_t log_index = ATOMIC_INIT(0); @@ -102,9 +103,9 @@ void logbuffer_vlog(struct logbuffer *instance, const char *fmt, instance->logbuffer_head == LOG_BUFFER_ENTRIES - 1) { __logbuffer_log(instance, tmpbuffer, true); /* Print UTC when logging after suspend */ - } else if (suspend_since_last_logged) { + } else if (driver_suspended_count != instance->suspend_count) { __logbuffer_log(instance, tmpbuffer, true); - suspend_since_last_logged = false; + instance->suspend_count = driver_suspended_count; } else if (!fmt) { goto abort; } @@ -239,7 +240,7 @@ EXPORT_SYMBOL_GPL(logbuffer_unregister); int logbuffer_suspend(void) { - suspend_since_last_logged = true; + driver_suspended_count += 1; return 0; } @@ -250,7 +251,7 @@ static struct syscore_ops logbuffer_ops = { static int __init logbuffer_dev_init(void) { register_syscore_ops(&logbuffer_ops); - + driver_suspended_count = 0; return 0; } diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c index 6911e588e578..94ac50ea6956 100644 --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c @@ -597,7 +597,7 @@ struct mac80211_hwsim_data { bool ps_poll_pending; struct dentry *debugfs; - uintptr_t pending_cookie; + atomic_t pending_cookie; struct sk_buff_head pending; /* packets pending */ /* * Only radios in the same group can communicate together (the @@ -1273,8 +1273,7 @@ static void mac80211_hwsim_tx_frame_nl(struct ieee80211_hw *hw, goto nla_put_failure; /* We create a cookie to identify this skb */ - data->pending_cookie++; - cookie = data->pending_cookie; + cookie = atomic_inc_return(&data->pending_cookie); info->rate_driver_data[0] = (void *)cookie; if (nla_put_u64_64bit(skb, HWSIM_ATTR_COOKIE, cookie, HWSIM_ATTR_PAD)) goto nla_put_failure; @@ -3511,6 +3510,7 @@ static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2, const u8 *src; unsigned int hwsim_flags; int i; + unsigned long flags; bool found = false; if (!info->attrs[HWSIM_ATTR_ADDR_TRANSMITTER] || @@ -3538,18 +3538,20 @@ static int hwsim_tx_info_frame_received_nl(struct sk_buff *skb_2, } /* look for the skb matching the cookie passed back from user */ + spin_lock_irqsave(&data2->pending.lock, flags); skb_queue_walk_safe(&data2->pending, skb, tmp) { - u64 skb_cookie; + uintptr_t skb_cookie; txi = IEEE80211_SKB_CB(skb); - skb_cookie = (u64)(uintptr_t)txi->rate_driver_data[0]; + skb_cookie = (uintptr_t)txi->rate_driver_data[0]; if (skb_cookie == ret_skb_cookie) { - skb_unlink(skb, &data2->pending); + __skb_unlink(skb, &data2->pending); found = true; break; } } + spin_unlock_irqrestore(&data2->pending.lock, flags); /* not found */ if (!found) @@ -3676,6 +3678,8 @@ static int hwsim_cloned_frame_received_nl(struct sk_buff *skb_2, rx_status.band = channel->band; rx_status.rate_idx = nla_get_u32(info->attrs[HWSIM_ATTR_RX_RATE]); + if (rx_status.rate_idx >= data2->hw->wiphy->bands[rx_status.band]->n_bitrates) + goto out; rx_status.signal = nla_get_u32(info->attrs[HWSIM_ATTR_SIGNAL]); hdr = (void *)skb->data; diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 76ee868bf7c7..66ff05942d21 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -90,6 +90,13 @@ config PCI_EXYNOS select PCIEPORTBUS select PCIE_DW_HOST +config PCI_EXYNOS_CAL_GS201 + tristate "Samsung Exynos PCIe PHY CAL for GS201" + depends on PCI + depends on OF + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + config PCI_EXYNOS_CAL_GS101 tristate "Samsung Exynos PCIe PHY CAL for GS101" depends on PCI diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 9997eb03421a..29b12d1d07df 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pcie-exynos-core.o pcie-exynos-core-objs += pcie-exynos-rc.o pcie-exynos-dbg.o obj-$(CONFIG_PCI_EXYNOS_CAL_GS101) += pcie-exynos-gs101-rc-cal.o +obj-$(CONFIG_PCI_EXYNOS_CAL_GS201) += pcie-exynos-gs201-rc-cal.o obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o diff --git a/drivers/pci/controller/dwc/pcie-exynos-common.h b/drivers/pci/controller/dwc/pcie-exynos-common.h index c94b9cb424ca..a01083a3059f 100644 --- a/drivers/pci/controller/dwc/pcie-exynos-common.h +++ b/drivers/pci/controller/dwc/pcie-exynos-common.h @@ -220,10 +220,10 @@ struct exynos_pcie_ops { struct exynos_pcie { struct dw_pcie *pci; #if IS_ENABLED(CONFIG_GS_S2MPU) - struct s2mpu_info *s2mpu; - struct pci_dev *ep_pci_dev; struct list_head phys_mem_list; #endif + struct s2mpu_info *s2mpu; + struct pci_dev *ep_pci_dev; void __iomem *elbi_base; void __iomem *phy_base; void __iomem *sysreg_base; @@ -233,6 +233,10 @@ struct exynos_pcie { u32 elbi_base_physical_addr; u32 phy_base_physical_addr; u32 ia_base_physical_addr; + u32 ep_l1ss_cap_off; + u32 ep_link_ctrl_off; + u32 ep_l1ss_ctrl1_off; + u32 ep_l1ss_ctrl2_off; unsigned int pci_cap[48]; unsigned int pci_ext_cap[48]; struct regmap *pmureg; @@ -248,6 +252,7 @@ struct exynos_pcie { int l1ss_enable; int linkdown_cnt; int idle_ip_index; + int separated_msi; bool use_msi; bool use_cache_coherency; bool use_sicd; @@ -256,7 +261,10 @@ struct exynos_pcie { bool use_sysmmu; bool use_ia; bool use_l1ss; + bool use_secure_atu; bool use_nclkoff_en; + bool cpl_timeout_recovery; + bool sudden_linkdown; spinlock_t conf_lock; /* pcie config - link status change */ spinlock_t reg_lock; /* pcie config - reg_lock(reserved) */ spinlock_t pcie_l1_exit_lock; /* pcie l1.2 exit - ctrl_id_state */ @@ -308,6 +316,24 @@ struct exynos_pcie { bool use_phy_isol_con; int phy_control; + struct logbuffer *log; + + bool pcie_must_resume; + int pcieon_sleep_enable_cnt; +}; + +#define PCIE_MAX_MSI_NUM (8) +#define PCIE_MAX_SEPA_IRQ_NUM (5) +#define PCIE_START_SEP_MSI_VEC (1) +#define PCIE_MSI_MAX_VEC_NUM (32) +#define PCIE_DOMAIN_MAX_IRQ (256) + +struct separated_msi_vector { + int is_used; + int irq; + void *context; + irq_handler_t msi_irq_handler; + int flags; }; #define PCIE_EXYNOS_OP_READ(base, type) \ diff --git a/drivers/pci/controller/dwc/pcie-exynos-gs201-rc-cal.c b/drivers/pci/controller/dwc/pcie-exynos-gs201-rc-cal.c new file mode 100644 index 000000000000..5a072594f42f --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-exynos-gs201-rc-cal.c @@ -0,0 +1,529 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe phy driver for gs201 SoC + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-exynos-common.h" +#include "pcie-exynos-rc.h" + +#if IS_ENABLED(CONFIG_EXYNOS_OTP) +#include +#endif + +/* avoid checking rx elecidle when access DBI */ +void exynos_pcie_rc_phy_check_rx_elecidle(void *phy_pcs_base_regs, int val, int ch_num) +{ + /* + * Todo: need guide + */ +} + +/* PHY all power down */ +void exynos_pcie_rc_phy_all_pwrdn(struct exynos_pcie *exynos_pcie, int ch_num) +{ + void __iomem *phy_base_regs = exynos_pcie->phy_base; + u32 val; + + dev_dbg(exynos_pcie->pci->dev, "[CAL: %s]\n", __func__); + writel(0xA8, phy_base_regs + 0x404); + writel(0x20, phy_base_regs + 0x408); + writel(0x0A, phy_base_regs + 0x40C); + + writel(0x0A, phy_base_regs + 0x800); + writel(0xBF, phy_base_regs + 0x804); + writel(0x02, phy_base_regs + 0xA40); + writel(0x2A, phy_base_regs + 0xA44); + writel(0xAA, phy_base_regs + 0xA48); + writel(0xA8, phy_base_regs + 0xA4C); + writel(0x80, phy_base_regs + 0xA50); + + writel(0x0A, phy_base_regs + 0x1000); + writel(0xBF, phy_base_regs + 0x1004); + writel(0x02, phy_base_regs + 0x1240); + writel(0x2A, phy_base_regs + 0x1244); + writel(0xAA, phy_base_regs + 0x1248); + writel(0xA8, phy_base_regs + 0x124C); + writel(0x80, phy_base_regs + 0x1250); + + /* Disable PHY PMA */ + val = readl(phy_base_regs + 0x400); + val &= ~(0x1 << 7); + writel(val, phy_base_regs + 0x400); +} + +/* PHY all power down clear */ +void exynos_pcie_rc_phy_all_pwrdn_clear(struct exynos_pcie *exynos_pcie, int ch_num) +{ + void __iomem *phy_base_regs = exynos_pcie->phy_base; + + dev_dbg(exynos_pcie->pci->dev, "[CAL: %s]\n", __func__); + writel(0x28, phy_base_regs + 0xD8); + mdelay(1); + + writel(0x00, phy_base_regs + 0x404); + writel(0x00, phy_base_regs + 0x408); + writel(0x00, phy_base_regs + 0x40C); + + writel(0x00, phy_base_regs + 0x800); + writel(0x00, phy_base_regs + 0x804); + writel(0x00, phy_base_regs + 0xA40); + writel(0x00, phy_base_regs + 0xA44); + writel(0x00, phy_base_regs + 0xA48); + writel(0x00, phy_base_regs + 0xA4C); + writel(0x00, phy_base_regs + 0xA50); + + writel(0x00, phy_base_regs + 0x1000); + writel(0x00, phy_base_regs + 0x1004); + writel(0x00, phy_base_regs + 0x1240); + writel(0x00, phy_base_regs + 0x1244); + writel(0x00, phy_base_regs + 0x1248); + writel(0x00, phy_base_regs + 0x124C); + writel(0x00, phy_base_regs + 0x1250); +} + +#if IS_ENABLED(CONFIG_EXYNOS_OTP) +void exynos_pcie_rc_pcie_phy_otp_config(void *phy_base_regs, int ch_num) +{ + /* To be updated */ +} +#endif + +#define LCPLL_REF_CLK_SEL (0x3 << 4) + +void exynos_pcie_rc_pcie_phy_config(struct exynos_pcie *exynos_pcie, int ch_num) +{ + void __iomem *elbi_base_regs = exynos_pcie->elbi_base; + void __iomem *phy_base_regs = exynos_pcie->phy_base; + void __iomem *phy_pcs_base_regs = exynos_pcie->phy_pcs_base; + int num_lanes = exynos_pcie->num_lanes; + u32 val; + u32 i; + + dev_dbg(exynos_pcie->pci->dev, "[CAL: %s] CAL ver 210802\n", __func__); + + /* init. input clk path */ + writel(0x28, phy_base_regs + 0xD8); + + /* PCS MUX glitch W/A */ + val = readl(exynos_pcie->phy_pcs_base + 0x008); + val |= (1 << 7); + writel(val, phy_pcs_base_regs + 0x008); + if (num_lanes == 2) { + val = readl(exynos_pcie->phy_pcs_base + 0x808); + val |= (1 << 7); + writel(val, phy_pcs_base_regs + 0x808); + } + + /* PHY CMN_RST, INIT_RST, PORT_RST Assert */ + writel(0x1, elbi_base_regs + 0x1404); + writel(0x1, elbi_base_regs + 0x1408); + writel(0x1, elbi_base_regs + 0x1400); + writel(0x0, elbi_base_regs + 0x1404); + writel(0x0, elbi_base_regs + 0x1408); + writel(0x0, elbi_base_regs + 0x1400); + udelay(10); + + writel(0x1, elbi_base_regs + 0x1404); + udelay(10); + + /* pma_setting */ + /* Common */ + writel(0x50, phy_base_regs + 0x018); + writel(0x33, phy_base_regs + 0x048); + writel(0x01, phy_base_regs + 0x068); + writel(0x12, phy_base_regs + 0x070); + writel(0x00, phy_base_regs + 0x08C); + writel(0x21, phy_base_regs + 0x090); + writel(0x14, phy_base_regs + 0x0B0); + writel(0x50, phy_base_regs + 0x0B8); + writel(0x51, phy_base_regs + 0x0E0); + writel(0x00, phy_base_regs + 0x100); + writel(0x80, phy_base_regs + 0x104); + writel(0x38, phy_base_regs + 0x140); + writel(0xA4, phy_base_regs + 0x180); + writel(0x03, phy_base_regs + 0x188); /* LCPLL 100MHz no divide */ + writel(0x38, phy_base_regs + 0x2A8); + writel(0x12, phy_base_regs + 0x2E4); + /* PMA enable and aggregation mode(bifurcation mode: 0xC0) */ + writel(0x80, phy_base_regs + 0x400); + writel(0x20, phy_base_regs + 0x408); + writel(0x00, phy_base_regs + 0x550); + writel(0x00, phy_base_regs + 0x5A8); + writel(0xFF, phy_base_regs + 0x5EC); + + /* PCIe_TYPE: RC */ + writel(0x02, phy_base_regs + 0x458); /* 100MHz CLK on */ + writel(0x34, phy_base_regs + 0x5B0); /* diff,control REFCLK source */ + writel(0x20, phy_base_regs + 0x450); /* when entering L1.2, add delay */ + + /* PHY INPUT CLK 38.4 */ + writel(0x34, phy_base_regs + 0xAC); + writel(0x34, phy_base_regs + 0xB4); + writel(0x50, phy_base_regs + 0xE0); + writel(0x00, phy_base_regs + 0xF4); + writel(0x08, phy_base_regs + 0xF8); + writel(0xA0, phy_base_regs + 0x104); + writel(0x19, phy_base_regs + 0x11C); + writel(0x17, phy_base_regs + 0x124); + writel(0x41, phy_base_regs + 0x220); + + for (i = 0; i < num_lanes; i++) { + phy_base_regs += (i * 0x800); + + writel(0x08, phy_base_regs + 0x82C); + writel(0x24, phy_base_regs + 0x830); + writel(0x80, phy_base_regs + 0x878); + writel(0x40, phy_base_regs + 0x894); + writel(0x00, phy_base_regs + 0x8C0); + writel(0x30, phy_base_regs + 0x8F4); + writel(0x05, phy_base_regs + 0x908); + writel(0xE0, phy_base_regs + 0x90C); + writel(0xD4, phy_base_regs + 0x914); + writel(0xD3, phy_base_regs + 0x91C); + writel(0xCE, phy_base_regs + 0x920); + writel(0x01, phy_base_regs + 0x924); + writel(0x35, phy_base_regs + 0x928); + writel(0xBA, phy_base_regs + 0x92C); + writel(0x41, phy_base_regs + 0x930); + writel(0x15, phy_base_regs + 0x934); + writel(0x13, phy_base_regs + 0x938); + writel(0x4E, phy_base_regs + 0x93C); + writel(0x43, phy_base_regs + 0x948); + writel(0xFC, phy_base_regs + 0x94C); + writel(0x10, phy_base_regs + 0x954); + writel(0x69, phy_base_regs + 0x958); + writel(0x40, phy_base_regs + 0x964); + writel(0xF6, phy_base_regs + 0x9B4); + writel(0x2D, phy_base_regs + 0x9C0); + writel(0xB7, phy_base_regs + 0x9C4); + writel(0x3C, phy_base_regs + 0x9CC); + writel(0x7E, phy_base_regs + 0x9DC); + writel(0x02, phy_base_regs + 0xA40); + writel(0x26, phy_base_regs + 0xA70); + writel(0x00, phy_base_regs + 0xA74); + writel(0x06, phy_base_regs + 0xB40); /* hf_init */ + writel(0x06, phy_base_regs + 0xB44); + writel(0x04, phy_base_regs + 0xB48); /* value changed: 0x06 -> 0x04 */ + writel(0x03, phy_base_regs + 0xB4C); /* value changed: 0x04 -> 0x03 */ + writel(0x03, phy_base_regs + 0xB50); /* mf_init */ + writel(0x03, phy_base_regs + 0xB54); + writel(0x03, phy_base_regs + 0xB58); + writel(0x03, phy_base_regs + 0xB5C); + writel(0x1B, phy_base_regs + 0xC10); + writel(0x10, phy_base_regs + 0xC44); + writel(0x10, phy_base_regs + 0xC48); + writel(0x10, phy_base_regs + 0xC4C); + writel(0x10, phy_base_regs + 0xC50); + writel(0x02, phy_base_regs + 0xC54); + writel(0x02, phy_base_regs + 0xC58); + writel(0x02, phy_base_regs + 0xC5C); + writel(0x02, phy_base_regs + 0xC60); + writel(0x02, phy_base_regs + 0xC6C); + writel(0x02, phy_base_regs + 0xC70); + writel(0xE7, phy_base_regs + 0xCA8); + writel(0x00, phy_base_regs + 0xCAC); + writel(0x0E, phy_base_regs + 0xCB0); + writel(0x1C, phy_base_regs + 0xCCC); + writel(0x05, phy_base_regs + 0xCD4); + writel(0x77, phy_base_regs + 0xCD8); + writel(0x7A, phy_base_regs + 0xCDC); + writel(0x2F, phy_base_regs + 0xDB4); + + /* RX tuning */ + writel(0x80, phy_base_regs + 0x8FC); + writel(0xF4, phy_base_regs + 0x914); + writel(0xD3, phy_base_regs + 0x91C); + writel(0xCA, phy_base_regs + 0x920); + writel(0x3D, phy_base_regs + 0x928); + writel(0xB8, phy_base_regs + 0x92C); + writel(0x41, phy_base_regs + 0x930); + writel(0x17, phy_base_regs + 0x934); + writel(0x4C, phy_base_regs + 0x93C); + writel(0x73, phy_base_regs + 0x948); + writel(0xFC, phy_base_regs + 0x94C); + writel(0x55, phy_base_regs + 0x96C); + writel(0x78, phy_base_regs + 0x988); + writel(0x3B, phy_base_regs + 0x994); + writel(0xF6, phy_base_regs + 0x9B4); + writel(0xFF, phy_base_regs + 0x9C4); + writel(0x20, phy_base_regs + 0x9C8); + writel(0x2F, phy_base_regs + 0xA08); + writel(0x3F, phy_base_regs + 0xB9C); + + /* for GEN4 TX termination resistor? */ + writel(0x00, phy_base_regs + 0x9CC); + writel(0xFF, phy_base_regs + 0xCD8); + writel(0x6E, phy_base_regs + 0xCDC); + + /* TX idrv for termination resistor */ + writel(0x0F, phy_base_regs + 0x82C); + writel(0x60, phy_base_regs + 0x830); + writel(0x7E, phy_base_regs + 0x834); + + /* Auto FBB */ + writel(0x00, phy_base_regs + 0xC08); + writel(0x09, phy_base_regs + 0xC10); + writel(0x04, phy_base_regs + 0xC40); + writel(0x00, phy_base_regs + 0xC70); + /* DFE */ + writel(0x76, phy_base_regs + 0x9B4); + } + + phy_base_regs = exynos_pcie->phy_base; + for (i = 0; i < 2; i++) { + phy_base_regs += (i * 0x800); + + /* PHY INPUT CLK 38.4 */ + writel(0x41, phy_base_regs + 0xBCC); + writel(0x41, phy_base_regs + 0xBD4); + writel(0x68, phy_base_regs + 0xBDC); + writel(0x00, phy_base_regs + 0xBE0); + writel(0xD0, phy_base_regs + 0xBE4); + } + + /* PCS setting: pcie_pcs_setting() in F/W code */ + + /* aggregation mdoe(bifurcation disabled) */ + writel(0x00, phy_pcs_base_regs + 0x004); + if (num_lanes == 2) + writel(0x00, phy_pcs_base_regs + 0x804); + + /* if RC */ + writel(0x700D5, phy_pcs_base_regs + 0x154); + if (num_lanes == 2) + writel(0x700D5, phy_pcs_base_regs + 0x954); + + /* add for L2 entry and power */ + writel(0x300FF, phy_pcs_base_regs + 0x150); + if (num_lanes == 2) + writel(0x300FF, phy_pcs_base_regs + 0x950); + + /* add L2 power down delay */ + writel(0x40, phy_pcs_base_regs + 0x170); + if (num_lanes == 2) + writel(0x40, phy_pcs_base_regs + 0x970); + + /* when entring L1.2, ERIO CLK gating */ + val = readl(exynos_pcie->phy_pcs_base + 0x008); + val &= ~((1 << 4) | (1 << 5)); + val |= (1 << 4); + writel(val, phy_pcs_base_regs + 0x008); + if (num_lanes == 2) { + val = readl(exynos_pcie->phy_pcs_base + 0x808); + val &= ~((1 << 4) | (1 << 5)); + val |= (1 << 4); + writel(val, phy_pcs_base_regs + 0x808); + } + + /* PLL & BIAS EN off delay */ + writel(0x100B0808, phy_pcs_base_regs + 0x190); + + /* PHY CMN_RST, PORT_RST Release */ + writel(0x1, elbi_base_regs + 0x1400); + writel(0x1, elbi_base_regs + 0x1408); + + /* Additional PMA Configurations */ + phy_base_regs = exynos_pcie->phy_base; + val = readl(phy_base_regs + 0x5D0); + val |= (0x1 << 4); + val &= ~(0x1 << 3); + writel(val, phy_base_regs + 0x5D0); + dev_dbg(exynos_pcie->pci->dev, "[%s] XO clock configuration : 0x%x\n", + __func__, readl(phy_base_regs + 0x5D0)); + + /* AFC cal mode by default uses the calibrated value from a previous + * run. However on some devices this causes a CDR failure because + * the AFC done status is set prematurely. Setting the cal mode to + * always start from an initial value (determined through simulation) + * ensures that AFC has enough time to complete. + */ + dev_dbg(exynos_pcie->pci->dev, "AFC cal mode set to restart\n"); + writel(0x4, phy_base_regs + 0xBF4); +} +EXPORT_SYMBOL_GPL(exynos_pcie_rc_pcie_phy_config); + +int exynos_pcie_rc_eom(struct device *dev, void *phy_base_regs) +{ + struct exynos_pcie *exynos_pcie = dev_get_drvdata(dev); + struct exynos_pcie_ops *pcie_ops = &exynos_pcie->exynos_pcie_ops; + struct dw_pcie *pci = exynos_pcie->pci; + struct pcie_port *pp = &pci->pp; + struct device_node *np = dev->of_node; + unsigned int val; + unsigned int speed_rate, num_of_smpl; + unsigned int lane_width = 1; + int i, ret; + int test_cnt = 0; + struct pcie_eom_result **eom_result; + + u32 phase_sweep = 0; + u32 phase_step = 1; + u32 phase_loop = 1; + u32 vref_sweep = 0; + u32 vref_step = 1; + u32 err_cnt = 0; + u32 cdr_value = 0; + u32 eom_done = 0; + u32 err_cnt_13_8; + u32 err_cnt_7_0; + + dev_info(dev, "[%s] START!\n", __func__); + + ret = of_property_read_u32(np, "num-lanes", &lane_width); + if (ret) { + dev_err(dev, "[%s] failed to get num of lane(lane width=0\n", __func__); + lane_width = 0; + } else { + dev_info(dev, "[%s] num-lanes : %d\n", __func__, lane_width); + } + + /* eom_result[lane_num][test_cnt] */ + eom_result = kcalloc(1, sizeof(struct pcie_eom_result *) * lane_width, GFP_KERNEL); + for (i = 0; i < lane_width; i++) { + eom_result[i] = devm_kzalloc(dev, sizeof(*eom_result[i]) * + EOM_PH_SEL_MAX * EOM_DEF_VREF_MAX, GFP_KERNEL); + } + for (i = 0; i < lane_width; i++) { + if (!eom_result[i]) { + dev_err(dev, "[%s] failed to alloc 'eom_result[%d]\n", + __func__, i); + return -ENOMEM; + } + } + + exynos_pcie->eom_result = eom_result; + + pcie_ops->rd_own_conf(pp, PCIE_LINK_CTRL_STAT, 4, &val); + speed_rate = (val >> 16) & 0xf; + + if (speed_rate == 1 || speed_rate == 2) { + dev_err(dev, "[%s] speed_rate(GEN%d) is not GEN3 or GEN4\n", __func__, speed_rate); + /* memory free 'eom_result' */ + for (i = 0; i < lane_width; i++) + devm_kfree(dev, eom_result[i]); + + return -EINVAL; + } + + num_of_smpl = 13; + + for (i = 0; i < lane_width; i++) { + writel(0xE7, phy_base_regs + RX_EFOM_BIT_WIDTH_SEL); + + val = readl(phy_base_regs + ANA_RX_DFE_EOM_PI_STR_CTRL); + val |= 0xF; + writel(val, phy_base_regs + ANA_RX_DFE_EOM_PI_STR_CTRL); + + val = readl(phy_base_regs + ANA_RX_DFE_EOM_PI_DIVSEL_G12); + val |= (0x4 | 0x10); + writel(val, phy_base_regs + ANA_RX_DFE_EOM_PI_DIVSEL_G12); + + val = readl(phy_base_regs + ANA_RX_DFE_EOM_PI_DIVSEL_G34); + val |= (0x4 | 0x20); /* target sfr changed: ANA_RC_...DIVSEL_G32 -> G34 */ + writel(val, phy_base_regs + ANA_RX_DFE_EOM_PI_DIVSEL_G34); + + val = readl(phy_base_regs + RX_CDR_LOCK) >> 2; + cdr_value = val & 0x1; + eom_done = readl(phy_base_regs + RX_EFOM_DONE) & 0x1; + dev_info(dev, "eom_done 0x%x , cdr_value : 0x%x\n", eom_done, cdr_value); + + writel(0x0, phy_base_regs + RX_EFOM_NUMOF_SMPL_13_8); + writel(num_of_smpl, phy_base_regs + RX_EFOM_NUMOF_SMPL_7_0); + + for (phase_sweep = 0; phase_sweep <= 0x47 * phase_loop; + phase_sweep = phase_sweep + phase_step) { + val = (phase_sweep % 72) << 1; + writel(val, phy_base_regs + RX_EFOM_EOM_PH_SEL); + + for (vref_sweep = 0; vref_sweep <= 255; + vref_sweep = vref_sweep + vref_step) { + /* malfunction code: writel(0x12, phy_base_regs + RX_EFOM_MODE); */ + val = readl(phy_base_regs + RX_EFOM_MODE); + val &= ~(0x1f); + val |= (0x2 | 0x10); + writel(val, phy_base_regs + RX_EFOM_MODE); + + writel(vref_sweep, phy_base_regs + RX_EFOM_DFE_VREF_CTRL); + + /* malfunction code: writel(0x13, phy_base_regs + RX_EFOM_MODE); */ + val = readl(phy_base_regs + RX_EFOM_MODE); + val |= 0x1; /* value changed: 0x13 -> 0x1 */ + writel(val, phy_base_regs + RX_EFOM_MODE); + + val = readl(phy_base_regs + RX_EFOM_DONE) & 0x1; + while (val != 0x1) { + udelay(1); + val = readl(phy_base_regs + + RX_EFOM_DONE) & 0x1; + } + + err_cnt_13_8 = readl(phy_base_regs + + MON_RX_EFOM_ERR_CNT_13_8) << 8; + err_cnt_7_0 = readl(phy_base_regs + + MON_RX_EFOM_ERR_CNT_7_0); + err_cnt = err_cnt_13_8 + err_cnt_7_0; + + if (vref_sweep == 128) + dev_info(dev, "%d,%d : %d %d %d\n", i, test_cnt, + phase_sweep, vref_sweep, err_cnt); + + /* save result */ + eom_result[i][test_cnt].phase = phase_sweep; + eom_result[i][test_cnt].vref = vref_sweep; + eom_result[i][test_cnt].err_cnt = err_cnt; + + test_cnt++; + } + } + writel(0x21, phy_base_regs + 0xBA0); /* 0xBA0 */ + writel(0x00, phy_base_regs + 0xCA0); /* RX_EFOM_MODE = 0xCA0 */ + + /* goto next lane */ + phy_base_regs += 0x800; + test_cnt = 0; + } + + return 0; +} + +void exynos_pcie_rc_phy_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + + dev_info(pci->dev, "Initialize PHY functions.\n"); + + exynos_pcie->phy_ops.phy_check_rx_elecidle = + exynos_pcie_rc_phy_check_rx_elecidle; + exynos_pcie->phy_ops.phy_all_pwrdn = exynos_pcie_rc_phy_all_pwrdn; + exynos_pcie->phy_ops.phy_all_pwrdn_clear = + exynos_pcie_rc_phy_all_pwrdn_clear; + exynos_pcie->phy_ops.phy_config = exynos_pcie_rc_pcie_phy_config; + exynos_pcie->phy_ops.phy_eom = exynos_pcie_rc_eom; +} +EXPORT_SYMBOL_GPL(exynos_pcie_rc_phy_init); + +static void exynos_pcie_quirks(struct pci_dev *dev) +{ + device_disable_async_suspend(&dev->dev); + pr_info("[%s] async suspend disabled\n", __func__); +} +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, exynos_pcie_quirks); + +MODULE_AUTHOR("Hongseock Kim "); +MODULE_DESCRIPTION("PCIe phy driver for gs201 SoC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pci/controller/dwc/pcie-exynos-rc.c b/drivers/pci/controller/dwc/pcie-exynos-rc.c index 40701b950b13..3ffb12de35f2 100644 --- a/drivers/pci/controller/dwc/pcie-exynos-rc.c +++ b/drivers/pci/controller/dwc/pcie-exynos-rc.c @@ -27,6 +27,7 @@ #include #include #include +#include #if IS_ENABLED(CONFIG_EXYNOS_ITMON) #include #endif @@ -35,6 +36,7 @@ #include #include #include +#include #if IS_ENABLED(CONFIG_CPU_IDLE) #include @@ -45,11 +47,12 @@ #include #endif -#include /* to get Exynos Modem - MSI target addr. */ +#include /* to get Exynos Modem - MSI target addr. */ #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) #define MODIFY_MSI_ADDR #endif /* CONFIG_LINK_DEVICE_PCIE */ +#include #include "pcie-designware.h" #include "pcie-exynos-common.h" #include "pcie-exynos-rc.h" @@ -57,6 +60,7 @@ #include #include +#include "../../../iommu/exynos-pcie-iommu-exp.h" #include #undef pr_info @@ -71,6 +75,7 @@ struct exynos_pcie g_pcie_rc[MAX_RC_NUM]; int pcie_is_linkup; /* checkpatch: do not initialise globals to 0 */ +static struct separated_msi_vector sep_msi_vec[MAX_RC_NUM][PCIE_MAX_SEPA_IRQ_NUM]; /* currnet_cnt & current_cnt2 for EOM test */ static int current_cnt; static int current_cnt2; @@ -82,11 +87,22 @@ static struct pci_dev *exynos_pcie_get_pci_dev(struct pcie_port *pp); static struct exynos_pm_qos_request exynos_pcie_int_qos[MAX_RC_NUM]; #endif +/* + * PCIe channel0 is in the HSI1 block. + * PCIe channel1 is in the HSI2 block. + */ +#define pcie_ch_to_hsi(ch_num) ((ch_num) + 1) +#if IS_ENABLED(CONFIG_GS_S2MPU) || IS_ENABLED(CONFIG_EXYNOS_PCIE_IOMMU) +static const struct dma_map_ops pcie_dma_ops; +static struct device fake_dma_dev; +#define to_pci_dev_from_dev(dev) container_of((dev), struct pci_dev, dev) static void exynos_d3_sleep_hook(void *unused, struct pci_dev *dev, unsigned int *delay); -#if IS_ENABLED(CONFIG_GS_S2MPU) +#define MODEM_CH_NUM 0 +#define WIFI_CH_NUM 1 +#if IS_ENABLED(CONFIG_GS_S2MPU) struct phys_mem { struct list_head list; phys_addr_t start; @@ -94,10 +110,6 @@ struct phys_mem { unsigned char *refcnt_array; }; -static const struct dma_map_ops gs101_pcie_dma_ops; -static struct device fake_dma_dev; - -#define WIFI_CH_NUM 1 #define ALIGN_SIZE 0x1000UL #define REF_COUNT_UNDERFLOW 255 @@ -221,55 +233,109 @@ void s2mpu_update_refcnt(struct device *dev, } spin_unlock_irqrestore(&exynos_pcie->s2mpu_refcnt_lock, flags); } +#endif + +static int get_ch_num(struct pci_dev *epdev) +{ + int ch_num = WIFI_CH_NUM; + if (epdev->vendor == PCI_VENDOR_ID_SAMSUNG) + ch_num = MODEM_CH_NUM; + + return ch_num; +} -static void *gs101_pcie_dma_alloc_attrs(struct device *dev, size_t size, - dma_addr_t *dma_handle, gfp_t flag, - unsigned long attrs) +static void *pcie_dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + unsigned long attrs) { void *cpu_addr; + struct pci_dev *epdev = to_pci_dev_from_dev(dev); + int ch_num = get_ch_num(epdev); + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + int ret; cpu_addr = dma_alloc_attrs(&fake_dma_dev, size, dma_handle, flag, attrs); - s2mpu_update_refcnt(dev, *dma_handle, size, true, DMA_BIDIRECTIONAL); + if (exynos_pcie->s2mpu) { + s2mpu_update_refcnt(dev, *dma_handle, size, true, DMA_BIDIRECTIONAL); + } else if (exynos_pcie->use_sysmmu) { + ret = pcie_iommu_map(*dma_handle, *dma_handle, size, + DMA_BIDIRECTIONAL, pcie_ch_to_hsi(ch_num)); + if (ret != 0) { + pr_err("Can't map PCIe SysMMU table!\n"); + dma_free_attrs(&fake_dma_dev, size, + cpu_addr, *dma_handle, attrs); + return NULL; + } + } + return cpu_addr; } -static void gs101_pcie_dma_free_attrs(struct device *dev, size_t size, - void *cpu_addr, dma_addr_t dma_addr, - unsigned long attrs) +static void pcie_dma_free_attrs(struct device *dev, size_t size, + void *cpu_addr, dma_addr_t dma_addr, + unsigned long attrs) { + struct pci_dev *epdev = to_pci_dev_from_dev(dev); + int ch_num = get_ch_num(epdev); + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + dma_free_attrs(&fake_dma_dev, size, cpu_addr, dma_addr, attrs); - s2mpu_update_refcnt(dev, dma_addr, size, false, DMA_BIDIRECTIONAL); + if (exynos_pcie->s2mpu) + s2mpu_update_refcnt(dev, dma_addr, size, false, DMA_BIDIRECTIONAL); + else if (exynos_pcie->use_sysmmu) + pcie_iommu_unmap(dma_addr, size, pcie_ch_to_hsi(ch_num)); } -static dma_addr_t gs101_pcie_dma_map_page(struct device *dev, struct page *page, - size_t offset, size_t size, - enum dma_data_direction dir, - unsigned long attrs) +static dma_addr_t pcie_dma_map_page(struct device *dev, struct page *page, + size_t offset, size_t size, + enum dma_data_direction dir, + unsigned long attrs) { + struct pci_dev *epdev = to_pci_dev_from_dev(dev); + int ch_num = get_ch_num(epdev); + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; dma_addr_t dma_addr; + int ret; dma_addr = dma_map_page_attrs(&fake_dma_dev, page, offset, size, dir, attrs); - s2mpu_update_refcnt(dev, dma_addr, size, true, dir); + if (exynos_pcie->s2mpu) { + s2mpu_update_refcnt(dev, dma_addr, size, true, dir); + } else if (exynos_pcie->use_sysmmu) { + ret = pcie_iommu_map(dma_addr, dma_addr, size, + dir, pcie_ch_to_hsi(ch_num)); + if (ret != 0) { + pr_err("DMA map - Can't map PCIe SysMMU table!!!\n"); + return 0; + } + } return dma_addr; } -static void gs101_pcie_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction dir, - unsigned long attrs) +static void pcie_dma_unmap_page(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction dir, + unsigned long attrs) { + struct pci_dev *epdev = to_pci_dev_from_dev(dev); + int ch_num = get_ch_num(epdev); + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + dma_unmap_page_attrs(&fake_dma_dev, dma_addr, size, dir, attrs); - s2mpu_update_refcnt(dev, dma_addr, size, false, dir); + + if (exynos_pcie->s2mpu) + s2mpu_update_refcnt(dev, dma_addr, size, false, dir); + else if (exynos_pcie->use_sysmmu) + pcie_iommu_unmap(dma_addr, size, pcie_ch_to_hsi(ch_num)); } -static const struct dma_map_ops gs101_pcie_dma_ops = { - .alloc = gs101_pcie_dma_alloc_attrs, - .free = gs101_pcie_dma_free_attrs, +static const struct dma_map_ops pcie_dma_ops = { + .alloc = pcie_dma_alloc_attrs, + .free = pcie_dma_free_attrs, .mmap = NULL, .get_sgtable = NULL, - .map_page = gs101_pcie_dma_map_page, - .unmap_page = gs101_pcie_dma_unmap_page, + .map_page = pcie_dma_map_page, + .unmap_page = pcie_dma_unmap_page, .map_sg = NULL, .unmap_sg = NULL, .map_resource = NULL, @@ -304,20 +370,38 @@ void exynos_pcie_set_perst_gpio(int ch_num, bool on) struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; if (exynos_pcie->ep_device_type == EP_SAMSUNG_MODEM) { - pr_info("%s: force settig for abnormal state\n", __func__); + pr_debug("%s: force setting for abnormal state\n", __func__); if (on) { gpio_set_value(exynos_pcie->perst_gpio, 1); - pr_info("%s: Set PERST to HIGH, gpio val = %d\n", - __func__, gpio_get_value(exynos_pcie->perst_gpio)); + pr_debug("%s: Set PERST to HIGH, gpio val = %d\n", + __func__, gpio_get_value(exynos_pcie->perst_gpio)); } else { gpio_set_value(exynos_pcie->perst_gpio, 0); - pr_info("%s: Set PERST to LOW, gpio val = %d\n", - __func__, gpio_get_value(exynos_pcie->perst_gpio)); + pr_debug("%s: Set PERST to LOW, gpio val = %d\n", + __func__, gpio_get_value(exynos_pcie->perst_gpio)); } } } EXPORT_SYMBOL_GPL(exynos_pcie_set_perst_gpio); +void exynos_pcie_set_ready_cto_recovery(int ch_num) +{ + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + struct dw_pcie *pci = exynos_pcie->pci; + struct pcie_port *pp = &pci->pp; + + pr_info("[%s] ch_num:%d\n", __func__, ch_num); + + disable_irq(pp->irq); + + exynos_pcie_set_perst_gpio(ch_num, 0); + + /* LTSSM disable */ + exynos_elbi_write(exynos_pcie, PCIE_ELBI_LTSSM_DISABLE, + PCIE_APP_LTSSM_ENABLE); +} +EXPORT_SYMBOL(exynos_pcie_set_ready_cto_recovery); + static ssize_t exynos_pcie_rc_show(struct device *dev, struct device_attribute *attr, char *buf) { int ret = 0; @@ -933,7 +1017,11 @@ static int exynos_pcie_rc_wr_own_conf(struct pcie_port *pp, int where, int size, exynos_pcie->ch_num); } - ret = dw_pcie_write(exynos_pcie->rc_dbi_base + (where), size, val); + /* If secure ATU then make SMC call, since only TFA has write access */ + if (exynos_pcie->use_secure_atu && where == SECURE_ATU_ENABLE) + ret = exynos_smc(SMC_SECURE_ATU_SETUP, 0, 0, 0); + else + ret = dw_pcie_write(exynos_pcie->rc_dbi_base + (where), size, val); if (is_linked == 0) { if (exynos_pcie->phy_ops.phy_check_rx_elecidle) @@ -954,6 +1042,18 @@ static void exynos_pcie_rc_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + /* ATU needs to be written just once during establish link */ + + if (exynos_pcie->atu_ok) + return; + + exynos_pcie->atu_ok = 1; + + if (exynos_pcie->use_secure_atu) { + exynos_pcie_rc_wr_own_conf(pp, SECURE_ATU_ENABLE, 0, 0); + return; + } + /* Program viewport 0 : OUTBOUND : CFG0 */ exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_LOWER_BASE_OUTBOUND0, 4, pp->cfg0_base); exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_UPPER_BASE_OUTBOUND0, 4, (pp->cfg0_base >> 32)); @@ -963,13 +1063,18 @@ static void exynos_pcie_rc_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_UPPER_TARGET_OUTBOUND0, 4, 0); exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_CR1_OUTBOUND0, 4, PCIE_ATU_TYPE_CFG0); exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_CR2_OUTBOUND0, 4, EXYNOS_PCIE_ATU_ENABLE); - exynos_pcie->atu_ok = 1; } static void exynos_pcie_rc_prog_viewport_mem_outbound(struct pcie_port *pp) { struct resource_entry *entry = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + + /* Secure ATU is already setup by prog_viewport_cfg0, so skip it here */ + if (exynos_pcie->use_secure_atu) + return; /* Program viewport 0 : OUTBOUND : MEM */ exynos_pcie_rc_wr_own_conf(pp, PCIE_ATU_CR1_OUTBOUND1, 4, EXYNOS_PCIE_ATU_TYPE_MEM); @@ -1272,6 +1377,10 @@ static void exynos_pcie_rc_set_iocc(struct pcie_port *pp, int enable) exynos_sysreg_write(exynos_pcie, val, sysreg_sharability); } +#if IS_ENABLED(CONFIG_EXYNOS_PCIE_IOMMU) + pcie_sysmmu_set_use_iocc(pcie_ch_to_hsi(exynos_pcie->ch_num)); +#endif + exynos_pcie_rc_rd_own_conf(pp, PCIE_COHERENCY_CONTROL_3_OFF, 4, &val); dev_dbg(pci->dev, "PCIe Axcache[1] = 0x%x\n", val); @@ -1290,6 +1399,7 @@ static int exynos_pcie_rc_parse_dt(struct device *dev, struct exynos_pcie *exyno const char *use_sysmmu; const char *use_ia; const char *use_l1ss; + const char *use_secure_atu; const char *use_nclkoff_en; const char *use_pcieon_sleep; const char *use_phy_isol_con; @@ -1341,6 +1451,13 @@ static int exynos_pcie_rc_parse_dt(struct device *dev, struct exynos_pcie *exyno dev_info(dev, "parse the number of lanes: %d\n", exynos_pcie->num_lanes); } + if (of_property_read_u32(np, "separated-msi", &exynos_pcie->separated_msi)) { + dev_info(dev, "Unset separated-msi value, default '0'\n"); + exynos_pcie->separated_msi = 0; + } else { + dev_info(dev, "parse the separated msi: %d\n", exynos_pcie->separated_msi); + } + if (!of_property_read_string(np, "use-cache-coherency", &use_cache_coherency)) { if (!strcmp(use_cache_coherency, "true")) { dev_info(dev, "Cache Coherency unit is ENABLED.\n"); @@ -1445,6 +1562,17 @@ static int exynos_pcie_rc_parse_dt(struct device *dev, struct exynos_pcie *exyno exynos_pcie->use_l1ss = false; } + exynos_pcie->use_secure_atu = false; + if (!of_property_read_string(np, "use-secure-atu", &use_secure_atu)) { + if (!strcmp(use_secure_atu, "true")) { + dev_info(dev, "PCIe Secure ATU is ENABLED.\n"); + exynos_pcie->use_secure_atu = true; + } else if (!strcmp(use_secure_atu, "false")) + dev_info(dev, "PCIe Secure ATU is DISABLED.\n"); + else + dev_err(dev, "Invalid use-secure-atu value(default=false)\n"); + } + if (!of_property_read_string(np, "use-nclkoff-en", &use_nclkoff_en)) { if (!strcmp(use_nclkoff_en, "true")) { dev_info(dev, "PCIe NCLKOFF is ENABLED.\n"); @@ -1751,6 +1879,40 @@ static void __maybe_unused exynos_pcie_notify_callback(struct pcie_port *pp, int } } +void exynos_pcie_rc_print_msi_register(int ch_num) +{ + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + struct dw_pcie *pci = exynos_pcie->pci; + struct pcie_port *pp = &pci->pp; + u32 val; + int ctrl; + + val = exynos_elbi_read(exynos_pcie, PCIE_IRQ2_EN); + dev_info(pci->dev, "PCIE_IRQ2_EN: 0x%x\n", val); + + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_ADDR_LO, 4, &val); + dev_info(pci->dev, "PCIE_MSI_ADDR_LO: 0x%x\n", val); + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_ADDR_HI, 4, &val); + dev_info(pci->dev, "PCIE_MSI_ADDR_HI: 0x%x\n", val); + + for (ctrl = 0; ctrl < PCIE_MAX_MSI_NUM; ctrl++) { + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 4, &val); + dev_info(pci->dev, "PCIE_MSI_INTR0_MASK(0x%x):0x%x\n", PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), val); + + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 4, &val); + dev_info(pci->dev, "PCIE_MSI_INTR0_ENABLE(0x%x):0x%x\n", PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), val); + + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 4, &val); + dev_info(pci->dev, "PCIE_MSI_INTR0_STATUS: 0x%x\n", val); + } +} +EXPORT_SYMBOL_GPL(exynos_pcie_rc_print_msi_register); + void exynos_pcie_rc_register_dump(int ch_num) { struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; @@ -1812,6 +1974,10 @@ void exynos_pcie_rc_register_dump(int ch_num) } pr_err("PHY 0x17C0 : 0x%08x\n", exynos_phy_read(exynos_pcie, 0xFC0 + 0x800)); + + pr_err("PHY 0x760 : %#08x, 0x764 : %#08x\n", + exynos_phy_read(exynos_pcie, 0x760), + exynos_phy_read(exynos_pcie, 0x764)); pr_err("\n"); /* ---------------------- */ @@ -1882,76 +2048,16 @@ void exynos_pcie_rc_cpl_timeout_work(struct work_struct *work) container_of(work, struct exynos_pcie, cpl_timeout_work.work); struct dw_pcie *pci = exynos_pcie->pci; struct pcie_port *pp = &pci->pp; - u32 afc_code_lane0, afc_code_lane1, cdr_mon_lane0, cdr_mon_lane1; - u32 i, val, lane_num = 0, count = 0; - - - /* dump phy monitor registers */ - /* common */ - pr_err("PHY PMA 0x3F0 : 0x%08x\n", exynos_phy_read(exynos_pcie, 0x3F0)); - /* lane0 */ - for (i = 0xE00; i < 0xE50; i += 4) - pr_err("PHY PMA 0x%04x : 0x%08x\n", i, exynos_phy_read(exynos_pcie, i)); - - pr_err("PHY PMA 0xE74: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xE74)); - pr_err("PHY PMA 0xE78: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xE78)); - pr_err("PHY PMA 0xE7C: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xE7C)); - pr_err("PHY PMA 0xEC4: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xEC4)); - pr_err("PHY PMA 0xEC8: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xEC8)); - pr_err("PHY PMA 0xFC0: 0x%08x\n", exynos_phy_read(exynos_pcie, 0xFC0)); - /* lane1 */ - for (i = 0x1600; i < 0x1650; i += 4) - pr_err("PHY PMA 0x%04x : 0x%08x\n", i, exynos_phy_read(exynos_pcie, i)); - - pr_err("PHY PMA 0x1674: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x1674)); - pr_err("PHY PMA 0x1678: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x1678)); - pr_err("PHY PMA 0x167C: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x167C)); - pr_err("PHY PMA 0x16C4: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x16C4)); - pr_err("PHY PMA 0x16C8: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x16C8)); - pr_err("PHY PMA 0x17C0: 0x%08x\n", exynos_phy_read(exynos_pcie, 0x17C0)); - - /* PMA sfr dump for debegging */ - /* PHY PMA lane0 */ - afc_code_lane0 = exynos_phy_read(exynos_pcie, 0xE38); - pr_err("PHY PMA(0x%04x afc_code0): 0x%08x\n", 0xE38, afc_code_lane0); - afc_code_lane0 &= (0x3f); - cdr_mon_lane0 = exynos_phy_read(exynos_pcie, 0xFC0); - pr_err("PHY PMA(0x%04x cdr_mon0): 0x%08x\n", 0xFC0, cdr_mon_lane0); - cdr_mon_lane0 = (cdr_mon_lane0 >> 4) & 0xf; - /* PHY PMA lane1 */ - afc_code_lane1 = exynos_phy_read(exynos_pcie, 0x1638); - pr_err("PHY PMA(0x%04x afc_code1): 0x%08x\n", 0x1638, afc_code_lane1); - afc_code_lane1 &= (0x3f); - cdr_mon_lane1 = exynos_phy_read(exynos_pcie, 0x17C0); - pr_err("PHY PMA(0x%04x cdr_mon1): 0x%08x\n", 0x17C0, cdr_mon_lane1); - cdr_mon_lane1 = (cdr_mon_lane1 >> 4) & 0xf; - - /* check lane number */ - exynos_pcie_rc_rd_own_conf(pp, PCIE_LINK_CTRL_STAT, 4, &lane_num); - lane_num = lane_num >> 20; - lane_num &= PCIE_CAP_NEGO_LINK_WIDTH_MASK; - - /* check LTSSM */ - count = 0; - while (count < LNKRCVYWAIT_TIMEOUT) { - val = exynos_elbi_read(exynos_pcie, PCIE_ELBI_RDLH_LINKUP) - & PCIE_ELBI_LTSSM_STATE_MASK; - if (val >= S_L0 && val <= S_L1_IDLE) { - return; - } + struct device *dev = pci->dev; - count++; - usleep_range(10, 12); - } - exynos_pcie->state = STATE_LINK_DOWN_TRY; - exynos_pcie_rc_dump_link_down_status(exynos_pcie->ch_num); - exynos_pcie_rc_register_dump(exynos_pcie->ch_num); + if (exynos_pcie->state == STATE_LINK_DOWN) + return; if (exynos_pcie->use_pcieon_sleep) { pcie_is_linkup = 0; } - exynos_pcie_notify_callback(pp, EXYNOS_PCIE_EVENT_LINKDOWN); + exynos_pcie_notify_callback(pp, EXYNOS_PCIE_EVENT_CPL_TIMEOUT); } static void exynos_pcie_rc_use_ia(struct exynos_pcie *exynos_pcie) @@ -2205,6 +2311,25 @@ static struct dw_pcie_host_ops exynos_pcie_rc_ops = { .host_init = exynos_pcie_rc_init, }; +void exynos_pcie_msi_post_process(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + int ctrl, num_ctrls; + + if (exynos_pcie->separated_msi) + return; + + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + /* clear MSI register because of edge */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 4, 0xffffffff); + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x0); + } +} + static irqreturn_t exynos_pcie_rc_irq_handler(int irq, void *arg) { struct pcie_port *pp = arg; @@ -2229,23 +2354,45 @@ static irqreturn_t exynos_pcie_rc_irq_handler(int irq, void *arg) dev_info(dev, "! PCIE LINK DOWN-irq1_state: 0x%x !\n", val_irq1); dev_info(dev, "(irq0 = 0x%x, irq1 = 0x%x, irq2 = 0x%x)\n", val_irq0, val_irq1, val_irq2); - exynos_pcie->state = STATE_LINK_DOWN_TRY; - queue_work(exynos_pcie->pcie_wq, &exynos_pcie->dislink_work.work); + + if (exynos_pcie->cpl_timeout_recovery) { + dev_err(dev, "already in cpl recovery\n"); + } else { + exynos_pcie->sudden_linkdown = 1; + exynos_pcie->state = STATE_LINK_DOWN_TRY; + queue_work(exynos_pcie->pcie_wq, &exynos_pcie->dislink_work.work); + } } if (val_irq2 & IRQ_RADM_CPL_TIMEOUT_ASSERT) { dev_info(dev, "!! PCIE_CPL_TIMEOUT-irq2_state: 0x%x !!\n", val_irq2); dev_info(dev, "(irq0 = 0x%x, irq1 = 0x%x, irq2 = 0x%x)\n", - val_irq0, val_irq1, val_irq2); + val_irq0, val_irq1, val_irq2); val_irq2 = exynos_elbi_read(exynos_pcie, PCIE_IRQ2); dev_info(dev, "check irq22 pending clear: irq2_state = 0x%x\n", val_irq2); - exynos_pcie->state = STATE_LINK_DOWN_TRY; + if (exynos_pcie->sudden_linkdown) { + dev_err(dev, "in linkdown recovery\n"); + } else { + if (exynos_pcie->cpl_timeout_recovery) { + dev_err(dev, "in cpl recovery\n"); + } else { + exynos_pcie->cpl_timeout_recovery = 1; + exynos_pcie->state = STATE_LINK_DOWN_TRY; + queue_work(exynos_pcie->pcie_wq, + &exynos_pcie->cpl_timeout_work.work); + } + } } #if IS_ENABLED(CONFIG_PCI_MSI) if (val_irq2 & IRQ_MSI_RISING_ASSERT && exynos_pcie->use_msi) { + if (exynos_pcie->separated_msi && exynos_pcie->use_pcieon_sleep) { + dev_info(dev, "MSI: separated msi & pcieonsleep\n"); + return IRQ_HANDLED; + } + dw_handle_msi_irq(pp); /* Mask & Clear MSI to pend MSI interrupt. @@ -2253,8 +2400,7 @@ static irqreturn_t exynos_pcie_rc_irq_handler(int irq, void *arg) * lower MSI status bit is set while processing upper bit. * Through the Mask/Unmask, ignored interrupts will be pended. */ - exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK, 4, 0xffffffff); - exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK, 4, 0x0); + exynos_pcie_msi_post_process(pp); } #endif @@ -2263,7 +2409,7 @@ static irqreturn_t exynos_pcie_rc_irq_handler(int irq, void *arg) static int exynos_pcie_rc_msi_init(struct pcie_port *pp) { - u32 val, mask_val; + u32 val, mask_val, i; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); struct pci_bus *ep_pci_bus; @@ -2304,7 +2450,10 @@ static int exynos_pcie_rc_msi_init(struct pcie_port *pp) exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, upper_32_bits(pp->msi_data)); val = exynos_elbi_read(exynos_pcie, PCIE_IRQ2_EN); - val |= IRQ_MSI_CTRL_EN_RISING_EDG; + if (exynos_pcie->separated_msi) + val &= ~IRQ_MSI_CTRL_EN_RISING_EDG; + else + val |= IRQ_MSI_CTRL_EN_RISING_EDG; exynos_elbi_write(exynos_pcie, val, PCIE_IRQ2_EN); /* Enable MSI interrupt after PCIe reset */ @@ -2312,15 +2461,31 @@ static int exynos_pcie_rc_msi_init(struct pcie_port *pp) exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, val); exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &val); exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_MASK, 4, &mask_val); + + if (exynos_pcie->separated_msi) { + pr_debug("Enable Separated MSI IRQs.\n"); + for (i = PCIE_START_SEP_MSI_VEC; i < PCIE_MAX_SEPA_IRQ_NUM; i++) { + if (sep_msi_vec[exynos_pcie->ch_num][i].is_used) { + /* Enable MSI interrupt for separated MSI. */ + pr_debug("Separated MSI%d is Enabled.\n", i); + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, ~(0x1)); + } + } + } #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) dev_dbg(dev, "MSI INIT: check MSI_INTR0_ENABLE(0x%x): 0x%x\n", PCIE_MSI_INTR0_ENABLE, val); - if (val != 0xf1) { - exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, 0xf1); - exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &val); + if (exynos_pcie->ep_device_type != EP_QC_WIFI) { + if (val != 0xf1) { + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, 0xf1); + exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &val); + } } dev_dbg(dev, "MSI INIT: check MSI_INTR0_MASK(0x%x): 0x%x\n", PCIE_MSI_INTR0_MASK, mask_val); - mask_val &= ~(0xf1); + mask_val &= ~(val); exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK, 4, mask_val); udelay(1); exynos_pcie_rc_rd_own_conf(pp, PCIE_MSI_INTR0_MASK, 4, &mask_val); @@ -2399,6 +2564,8 @@ static int exynos_pcie_rc_establish_link(struct pcie_port *pp) if (pll_lock != 0 && cdr_lock != 0) break; } + if ((pll_lock == 0) || (cdr_lock == 0)) + dev_info(dev, "PLL & CDR lock check!\n"); /* check offset calibration */ for (i = 0; i < 2000; i++) { @@ -2511,6 +2678,10 @@ static int exynos_pcie_rc_establish_link(struct pcie_port *pp) goto retry; } else { //exynos_pcie_host_v1_print_link_history(pp); + exynos_pcie_rc_print_link_history(pp); + exynos_pcie_rc_dump_link_down_status(exynos_pcie->ch_num); + exynos_pcie_rc_register_dump(exynos_pcie->ch_num); + if (exynos_pcie->ip_ver >= 0x889000 && exynos_pcie->ep_device_type == EP_BCM_WIFI) { return -EPIPE; @@ -2621,7 +2792,7 @@ int exynos_pcie_rc_poweron(int ch_num) #endif /* Enable SysMMU */ if (exynos_pcie->use_sysmmu) - pcie_sysmmu_enable(ch_num); + pcie_sysmmu_enable(pcie_ch_to_hsi(ch_num)); pinctrl_select_state(exynos_pcie->pcie_pinctrl, exynos_pcie->pin_state[PCIE_PIN_ACTIVE]); @@ -2639,6 +2810,9 @@ int exynos_pcie_rc_poweron(int ch_num) exynos_pcie->state = STATE_LINK_UP_TRY; spin_unlock_irqrestore(&exynos_pcie->reg_lock, flags); + exynos_pcie->sudden_linkdown = 0; + exynos_pcie->cpl_timeout_recovery = 0; + enable_irq(pp->irq); if (exynos_pcie_rc_establish_link(pp)) { @@ -2696,11 +2870,16 @@ int exynos_pcie_rc_poweron(int ch_num) exynos_pcie->pci_saved_configs = pci_store_saved_state(exynos_pcie->pci_dev); -#if IS_ENABLED(CONFIG_GS_S2MPU) - if (exynos_pcie->s2mpu) { - exynos_pcie->ep_pci_dev = exynos_pcie_get_pci_dev(&pci->pp); - set_dma_ops(&exynos_pcie->ep_pci_dev->dev, &gs101_pcie_dma_ops); - dev_info(dev, "Wifi DMA operations are changed\n"); + exynos_pcie->ep_pci_dev = exynos_pcie_get_pci_dev(&pci->pp); + +#if IS_ENABLED(CONFIG_GS_S2MPU) || IS_ENABLED(CONFIG_EXYNOS_PCIE_IOMMU) + if (exynos_pcie->s2mpu || exynos_pcie->use_sysmmu) { + if (exynos_pcie->ep_device_type == EP_BCM_WIFI) { + set_dma_ops(&exynos_pcie->ep_pci_dev->dev, &pcie_dma_ops); + dev_info(dev, "Wifi DMA operations are changed\n"); + memcpy(&fake_dma_dev, exynos_pcie->pci->dev, + sizeof(fake_dma_dev)); + } } #endif @@ -2778,13 +2957,13 @@ void exynos_pcie_rc_poweroff(int ch_num) } spin_lock_irqsave(&exynos_pcie->conf_lock, flags); - exynos_pcie_rc_send_pme_turn_off(exynos_pcie); exynos_pcie->state = STATE_LINK_DOWN; + exynos_pcie_rc_send_pme_turn_off(exynos_pcie); power_stats_update_down(exynos_pcie); /* Disable SysMMU */ if (exynos_pcie->use_sysmmu) - pcie_sysmmu_disable(ch_num); + pcie_sysmmu_disable(pcie_ch_to_hsi(ch_num)); /* Disable history buffer */ val = exynos_elbi_read(exynos_pcie, PCIE_STATE_HISTORY_CHECK); @@ -2870,18 +3049,35 @@ int exynos_pcie_pm_resume(int ch_num) } EXPORT_SYMBOL_GPL(exynos_pcie_pm_resume); +bool exynos_pcie_rc_get_cpl_timeout_state(int ch_num) +{ + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + + return exynos_pcie->cpl_timeout_recovery; +} +EXPORT_SYMBOL(exynos_pcie_rc_get_cpl_timeout_state); + +void exynos_pcie_rc_set_cpl_timeout_state(int ch_num, bool recovery) +{ + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + + pr_err("set cpl_timeout_recovery to %d for ch_num:%d\n", recovery, ch_num); + exynos_pcie->cpl_timeout_recovery = recovery; +} +EXPORT_SYMBOL(exynos_pcie_rc_set_cpl_timeout_state); + /* get EP pci_dev structure of BUS */ static struct pci_dev *exynos_pcie_get_pci_dev(struct pcie_port *pp) { int domain_num; struct pci_bus *ep_pci_bus; - static struct pci_dev *ep_pci_dev; + struct pci_dev *ep_pci_dev; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); u32 val; - if (ep_pci_dev) - return ep_pci_dev; + if (exynos_pcie->ep_pci_dev) + return exynos_pcie->ep_pci_dev; /* Get EP vendor/device ID to get pci_dev structure */ domain_num = exynos_pcie->pci_dev->bus->domain_nr; @@ -2960,7 +3156,8 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) /* This function is only working with the devices which support L1SS */ if (exynos_pcie->ep_device_type != EP_SAMSUNG_MODEM && - exynos_pcie->ep_device_type != EP_BCM_WIFI) { + exynos_pcie->ep_device_type != EP_BCM_WIFI && + exynos_pcie->ep_device_type != EP_QC_WIFI) { return -EINVAL; } @@ -2975,6 +3172,12 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) spin_unlock_irqrestore(&exynos_pcie->conf_lock, flags); return -1; + } else { + exynos_pcie->ep_l1ss_cap_off = + pci_find_ext_capability(exynos_pcie->ep_pci_dev, PCI_EXT_CAP_ID_L1SS); + exynos_pcie->ep_link_ctrl_off = exynos_pcie->ep_pci_dev->pcie_cap + PCI_EXP_LNKCTL; + exynos_pcie->ep_l1ss_ctrl1_off = exynos_pcie->ep_l1ss_cap_off + PCI_L1SS_CTL1; + exynos_pcie->ep_l1ss_ctrl2_off = exynos_pcie->ep_l1ss_cap_off + PCI_L1SS_CTL2; } /* get the domain_num & ep_pci_bus of EP device */ @@ -2997,9 +3200,9 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, val); /* [RC] set TPOWERON */ - /* Set TPOWERON value for RC: 90->130 usec */ + /* Set TPOWERON value for RC: 90->200 usec */ exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL2, 4, - PORT_LINK_TPOWERON_130US); + PORT_LINK_TPOWERON_200US); /* exynos_pcie_rc_wr_own_conf(pp, * PCIE_L1_SUBSTATES_OFF, 4, @@ -3019,10 +3222,10 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) exp_cap_off + PCI_EXP_DEVCTL2, 4, val); /* [EP] set TPOWERON */ - /* Set TPOWERON value for EP: 90->130 usec */ + /* Set TPOWERON value for EP: 90->200 usec */ exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_L1SS_CONTROL2, 4, - PORT_LINK_TPOWERON_130US); + exynos_pcie->ep_l1ss_ctrl2_off, 4, + PORT_LINK_TPOWERON_200US); /* [EP] set Entrance latency */ /* Set L1.2 Enterance Latency for EP: 64 usec */ @@ -3035,10 +3238,10 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) /* 2) [EP] enable L1SS */ exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_L1SS_CONTROL, 4, &val); + exynos_pcie->ep_l1ss_ctrl1_off, 4, &val); val |= PORT_LINK_L1SS_ENABLE; exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_L1SS_CONTROL, 4, val); + exynos_pcie->ep_l1ss_ctrl1_off, 4, val); /* 3) [RC] enable ASPM */ exynos_pcie_rc_rd_own_conf(pp, exp_cap_off + @@ -3050,11 +3253,11 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) /* 4) [EP] enable ASPM */ exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_CTRL_STAT, 4, &val); + exynos_pcie->ep_link_ctrl_off, 4, &val); val |= PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_CLKREQ_EN | PCI_EXP_LNKCTL_ASPM_L1; exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_CTRL_STAT, 4, val); + exynos_pcie->ep_link_ctrl_off, 4, val); } else if (exynos_pcie->ep_device_type == EP_BCM_WIFI) { /* enable sequence: @@ -3136,6 +3339,87 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) WIFI_ASPM_L1_ENTRY_EN; exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, WIFI_L1SS_LINKCTRL, 4, val); + } else if (exynos_pcie->ep_device_type == EP_QC_WIFI) { + /* enable sequence: + * 1. PCIPM RC + * 2. PCIPM EP + * 3. ASPM RC + * 4. ASPM EP + */ + + /* 1. to enable PCIPM RC */ + /* [RC:set value] TPowerOn(10 usec) */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL2, 4, + PORT_LINK_TPOWERON_10US); + + /* [RC:set enable bit] LTR Mechanism Enable */ + exynos_pcie_rc_rd_own_conf(pp, exp_cap_off + PCI_EXP_DEVCTL2, + 4, &val); + val |= PCI_EXP_DEVCTL2_LTR_EN; + exynos_pcie_rc_wr_own_conf(pp, exp_cap_off + PCI_EXP_DEVCTL2, + 4, val); + + /* [RC:set value] LTR_L1.2_Threshold(150(0x96) us) + * and TCommon is 42usec (val = (0xa | 0x20) << 8) + * [RC:enable] L1SS_ENABLE(0xf) + */ + exynos_pcie_rc_rd_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, &val); + val |= WIFI_QC_L12_LTR_THRESHOLD | PORT_LINK_TCOMMON_32US | + PORT_LINK_L1SS_ENABLE; + exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, val); + dev_dbg(dev, "%s: WIFIen:1RC:L1SS_CTRL(0x19C)=0x%x\n", + __func__, val); + + /* 2. to enable PCIPM EP */ + /* [EP:set value] TPowerOn(10 usec) */ + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exynos_pcie->ep_l1ss_ctrl2_off, + 4, PORT_LINK_TPOWERON_10US); + dev_dbg(dev, "%s: WIFIen:2EP:L1SS_CTRL2(0x%x)=0x%x\n", + __func__, exynos_pcie->ep_l1ss_ctrl2_off, + PORT_LINK_TPOWERON_10US); + + /* [EP:set enable bit] LTR Mechanism Enable */ + exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_DEVCTL2, 4, &val); + val |= PCI_EXP_DEVCTL2_LTR_EN; + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_DEVCTL2, 4, val); + dev_dbg(dev, "%s: WIFIen:2EP:EXP_DEVCTL2(0x%x)=0x%x\n", + __func__, exp_cap_off+PCI_EXP_DEVCTL2, val); + + /* [EP:set values] LTR_L1.2_Threshold(150 us) and TCommon(0 us) + * [EP:enable] WIFI_PM_ENALKBE(0xf) + */ + exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, + exynos_pcie->ep_l1ss_ctrl1_off, 4, &val); + val |= WIFI_QC_L12_LTR_THRESHOLD | PORT_LINK_L1SS_ENABLE; + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exynos_pcie->ep_l1ss_ctrl1_off, 4, val); + dev_dbg(dev, "%s: WIFIen:2EP:L1SS_CTRL(0x%x)=0x%x\n", + __func__, exynos_pcie->ep_l1ss_ctrl1_off, val); + + /* 3. to enable ASPM RC */ + exynos_pcie_rc_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, + 4, &val); + val &= ~PCI_EXP_LNKCTL_ASPMC; + /* PCI_EXP_LNKCTL_CCC: Common Clock Configuration */ + val |= PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ASPM_L1; + exynos_pcie_rc_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, + 4, val); + dev_dbg(dev, "%s: WIFIen:3RC:ASPM(0x70+16)=0x%x\n", __func__, val); + + /* 4. to enable ASPM EP */ + exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_LNKCTL, 4, &val); + val |= PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_CLKREQ_EN | + PCI_EXP_LNKCTL_ASPM_L1; + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_LNKCTL, 4, val); + dev_dbg(dev, "%s: WIFIen:4EP:ASPM(0x%x)=0x%x\n", + __func__,exp_cap_off+PCI_EXP_LNKCTL, val); + } else { + dev_err(dev, "[ERR] EP: L1SS not supported\n"); } } } else { /* enable == 0 */ @@ -3147,10 +3431,10 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) if (exynos_pcie->ep_device_type == EP_SAMSUNG_MODEM) { /* 1) [EP] disable ASPM */ exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_CTRL_STAT, 4, &val); + exynos_pcie->ep_link_ctrl_off, 4, &val); val &= ~(PCI_EXP_LNKCTL_ASPMC); exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_CTRL_STAT, 4, val); + exynos_pcie->ep_link_ctrl_off, 4, val); /* 2) [RC] disable ASPM */ exynos_pcie_rc_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, 4, &val); @@ -3160,10 +3444,10 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) /* 3) [EP] disable L1SS */ exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_L1SS_CONTROL, 4, &val); + exynos_pcie->ep_l1ss_ctrl1_off, 4, &val); val &= ~(PORT_LINK_L1SS_ENABLE); exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, - PCIE_LINK_L1SS_CONTROL, 4, val); + exynos_pcie->ep_l1ss_ctrl1_off, 4, val); /* 4) [RC] disable L1SS */ exynos_pcie_rc_rd_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, &val); @@ -3203,6 +3487,49 @@ static int exynos_pcie_rc_set_l1ss(int enable, struct pcie_port *pp, int id) exynos_pcie_rc_rd_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, &val); val &= ~(PORT_LINK_L1SS_ENABLE); exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, val); + } else if (exynos_pcie->ep_device_type == EP_QC_WIFI) { + /* disable sequence: + * 1. ASPM EP + * 2. ASPM RC + * 3. PCIPM EP + * 4. PCIPM RC + */ + /* 1) [EP] disable ASPM */ + exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_LNKCTL, 4, &val); + val &= ~(PCI_EXP_LNKCTL_ASPMC); + /* val |= WIFI_CLK_REQ_EN | WIFI_USE_SAME_REF_CLK; */ + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exp_cap_off+PCI_EXP_LNKCTL, 4, val); + dev_dbg(pci->dev, "%s: WIFIdis:1EP:ASPM(0x%x)=0x%x\n", + __func__,exp_cap_off+PCI_EXP_LNKCTL,val); + + /* 2) [RC] disable ASPM */ + exynos_pcie_rc_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, + 4, &val); + val &= ~PCI_EXP_LNKCTL_ASPMC; + exynos_pcie_rc_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, + 4, val); + dev_dbg(pci->dev, "%s: WIFIdis:2RC:ASPM(0x70+16)=0x%x\n", + __func__, val); + + /* 3) [EP] disable L1SS */ + exynos_pcie_rc_rd_other_conf(pp, ep_pci_bus, 0, + exynos_pcie->ep_l1ss_ctrl1_off, 4, &val); + val &= ~(PORT_LINK_L1SS_ENABLE); + exynos_pcie_rc_wr_other_conf(pp, ep_pci_bus, 0, + exynos_pcie->ep_l1ss_ctrl1_off, 4, val); + dev_dbg(pci->dev, "%s: WIFIdis:3EP:L1SS_CTRL(0x%x)=0x%x\n", + __func__, exynos_pcie->ep_l1ss_ctrl1_off,val); + + /* 4) [RC] disable L1SS */ + exynos_pcie_rc_rd_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, &val); + val &= ~(PORT_LINK_L1SS_ENABLE); + exynos_pcie_rc_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, val); + dev_dbg(pci->dev, "%s: WIFIdis:4RC:L1SS_CTRL(0x19C)=0x%x\n", + __func__, val); + } else { + dev_err(dev, "[ERR] EP: L1SS not supported\n"); } } } @@ -3232,8 +3559,14 @@ int exynos_pcie_rc_l1ss_ctrl(int enable, int id, int ch_num) EXPORT_SYMBOL_GPL(exynos_pcie_rc_l1ss_ctrl); /* to support CP driver */ -int exynos_pcie_poweron(int ch_num) +int exynos_pcie_poweron(int ch_num, int spd) { + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + struct dw_pcie *pci = exynos_pcie->pci; + + dev_dbg(pci->dev, "%s requested with link speed GEN%d\n", __func__, spd); + exynos_pcie->max_link_speed = spd; + return exynos_pcie_rc_poweron(ch_num); } EXPORT_SYMBOL_GPL(exynos_pcie_poweron); @@ -3250,6 +3583,7 @@ int exynos_pcie_rc_chk_link_status(int ch_num) struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; struct dw_pcie *pci; struct device *dev; + unsigned long flags; u32 val; int link_status; @@ -3265,6 +3599,13 @@ int exynos_pcie_rc_chk_link_status(int ch_num) if (exynos_pcie->state == STATE_LINK_DOWN) return 0; + if (exynos_pcie->cpl_timeout_recovery) { + spin_lock_irqsave(&exynos_pcie->reg_lock, flags); + exynos_pcie->state = STATE_LINK_DOWN; + spin_unlock_irqrestore(&exynos_pcie->reg_lock, flags); + return 0; + } + if (exynos_pcie->ep_device_type == EP_SAMSUNG_MODEM) { val = exynos_elbi_read(exynos_pcie, PCIE_ELBI_RDLH_LINKUP) & PCIE_ELBI_LTSSM_STATE_MASK; @@ -3273,6 +3614,9 @@ int exynos_pcie_rc_chk_link_status(int ch_num) } else { dev_err(dev, "Check unexpected state - H/W:0x%x, S/W:%d\n", val, exynos_pcie->state); + spin_lock_irqsave(&exynos_pcie->reg_lock, flags); + exynos_pcie->state = STATE_LINK_DOWN; + spin_unlock_irqrestore(&exynos_pcie->reg_lock, flags); link_status = 0; } @@ -3480,6 +3824,26 @@ int exynos_pcie_rc_set_affinity(int ch_num, int affinity) } EXPORT_SYMBOL_GPL(exynos_pcie_rc_set_affinity); +int exynos_pcie_rc_set_enable_wake(struct irq_data *data, unsigned int enable) +{ + int ret = 0; + struct pcie_port *pp = data->parent_data->domain->host_data; + + pr_debug("%s: enable = %d\n", __func__, enable); + + if (pp == NULL) { + pr_err("Warning: exynos_pcie_rc_set_enable_wake: not exist pp\n"); + return -EINVAL; + } + + if (enable) + ret = enable_irq_wake(pp->irq); + else + ret = disable_irq_wake(pp->irq); + + return ret; +} + #if IS_ENABLED(CONFIG_CPU_IDLE) static void __maybe_unused exynos_pcie_rc_set_tpoweron(struct pcie_port *pp, int max) { @@ -3518,61 +3882,20 @@ static void __maybe_unused exynos_pcie_rc_set_tpoweron(struct pcie_port *pp, int val |= WIFI_ALL_PM_ENABEL; writel(val, ep_dbi_base + WIFI_L1SS_CONTROL); } +#endif -#if IS_ENABLED(CONFIG_EXYNOS_PCIE_SICD) -static int exynos_pcie_rc_power_mode_event(struct notifier_block *nb, unsigned long event, - void *data) +static int exynos_pcie_msi_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, + bool force) { - int ret = NOTIFY_DONE; - struct exynos_pcie *exynos_pcie = container_of(nb, struct exynos_pcie, power_mode_nb); - u32 val; - struct dw_pcie *pci = exynos_pcie->pci; - struct pcie_port *pp = &pci->pp; + struct pcie_port *pp = irq_data->parent_data->domain->host_data; - dev_info(pci->dev, "[%s] event: %lx\n", __func__, event); - switch (event) { - case SICD_ENTER: - if (exynos_pcie->use_sicd) { - if (exynos_pcie->ip_ver >= 0x889500) { - if (exynos_pcie->state != STATE_LINK_DOWN) { - val = exynos_elbi_read(exynos_pcie, PCIE_ELBI_RDLH_LINKUP) - & PCIE_ELBI_LTSSM_STATE_MASK - if (val == S_L1_IDLE || val == S_L2_IDLE) { - ret = NOTIFY_DONE; - /* Change tpower on time to - * value - */ - exynos_pcie_rc_set_tpoweron(pp, 1); - } else { - ret = NOTIFY_BAD; - } - } - } - } - - break; - case SICD_EXIT: - if (exynos_pcie->use_sicd) { - if (exynos_pcie->ip_ver >= 0x889500) { - if (exynos_pcie->state != STATE_LINK_DOWN) { - /* Change tpower on time to NORMAL value */ - exynos_pcie_rc_set_tpoweron(pp, 0); - } - } - } - - break; - default: - ret = NOTIFY_DONE; + if (pp == NULL) { + pr_err("Warning: exynos_pcie_msi_set_affinity: not exist pp\n"); + return -EINVAL; } - return notifier_from_errno(ret); -} -#endif -#endif -static int exynos_pcie_msi_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, - bool force) -{ + irq_set_affinity_hint(pp->irq, mask); + return 0; } @@ -3610,11 +3933,226 @@ int exynos_pcie_rc_itmon_notifier(struct notifier_block *nb, unsigned long actio } #endif -static int exynos_pcie_rc_add_port(struct platform_device *pdev, struct pcie_port *pp) +static const char *sep_irq_name[PCIE_MAX_SEPA_IRQ_NUM] = { + "exynos-pcie-msi0", "exynos-pcie-msi1", "exynos-pcie-msi2", + "exynos-pcie-msi3", "exynos-pcie-msi4" }; + +static irqreturn_t exynos_pcie_msi0_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + struct device *dev = pci->dev; + int ch_num = exynos_pcie->ch_num; + struct separated_msi_vector *msi_vec = &sep_msi_vec[ch_num][0]; + + if (!msi_vec->is_used) { + dev_err(dev, "Unexpected separated MSI0 interrupt!"); + return IRQ_HANDLED; + } + + dw_handle_msi_irq(pp); + + if (!msi_vec->flags) { + /* To set as handle_level_irq, get virq, mapped_irq, irq_data. */ + struct irq_data *irq_data; + int i, virq, mapped_irq, changed_irq = 0; + + virq = irq_find_mapping(pp->irq_domain, 0); + mapped_irq = pp->irq_domain->mapcount; + + dev_dbg(dev, "Start virq = %d, Total mapped irq = %d\n", + virq, mapped_irq); + + for (i = 0; i < PCIE_DOMAIN_MAX_IRQ; i++) { + irq_data = irq_domain_get_irq_data(pp->irq_domain, virq); + if (irq_data == NULL) { + virq++; + continue; + } + + dev_dbg(dev, "Change flow interrupt for virq(%d)\n", virq); + irq_domain_set_info(pp->irq_domain, virq, irq_data->hwirq, + pp->msi_irq_chip, + pp, handle_level_irq, + NULL, NULL); + + virq++; + changed_irq++; + + if (changed_irq == mapped_irq) + break; + } + msi_vec->flags = 1; + } + exynos_pcie_msi_post_process(pp); + + return IRQ_HANDLED; +} + +static irqreturn_t exynos_pcie_msi1_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + struct device *dev = pci->dev; + int ch_num = exynos_pcie->ch_num; + struct separated_msi_vector *msi_vec = &sep_msi_vec[ch_num][1]; + int vec_num = 1; + + /* Clear MSI interrupt */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (vec_num * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + + if (!msi_vec->is_used) { + dev_err(dev, "Unexpected separated MSI1 interrupt!"); + return IRQ_HANDLED; + } + + if (msi_vec->msi_irq_handler != NULL) + msi_vec->msi_irq_handler(irq, msi_vec->context); + + exynos_pcie_msi_post_process(pp); + + return IRQ_HANDLED; +} + +static irqreturn_t exynos_pcie_msi2_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + struct device *dev = pci->dev; + int ch_num = exynos_pcie->ch_num; + struct separated_msi_vector *msi_vec = &sep_msi_vec[ch_num][2]; + int vec_num = 2; + + /* Clear MSI interrupt */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (vec_num * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + + if (!msi_vec->is_used) { + dev_err(dev, "Unexpected separated MSI2 interrupt!"); + return IRQ_HANDLED; + } + + if (msi_vec->msi_irq_handler != NULL) + msi_vec->msi_irq_handler(irq, msi_vec->context); + + exynos_pcie_msi_post_process(pp); + + return IRQ_HANDLED; +} + +static irqreturn_t exynos_pcie_msi3_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + struct device *dev = pci->dev; + int ch_num = exynos_pcie->ch_num; + struct separated_msi_vector *msi_vec = &sep_msi_vec[ch_num][3]; + int vec_num = 3; + + /* Clear MSI interrupt */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (vec_num * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + + if (!msi_vec->is_used) { + dev_err(dev, "Unexpected separated MSI3 interrupt!"); + return IRQ_HANDLED; + } + + if (msi_vec->msi_irq_handler != NULL) + msi_vec->msi_irq_handler(irq, msi_vec->context); + + exynos_pcie_msi_post_process(pp); + + return IRQ_HANDLED; +} + +static irqreturn_t exynos_pcie_msi4_handler(int irq, void *arg) +{ + struct pcie_port *pp = arg; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); + struct device *dev = pci->dev; + int ch_num = exynos_pcie->ch_num; + struct separated_msi_vector *msi_vec = &sep_msi_vec[ch_num][4]; + int vec_num = 4; + + /* Clear MSI interrupt */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + + (vec_num * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + + if (!msi_vec->is_used) { + dev_err(dev, "Unexpected separated MSI4 interrupt!"); + return IRQ_HANDLED; + } + + if (msi_vec->msi_irq_handler != NULL) + msi_vec->msi_irq_handler(irq, msi_vec->context); + + exynos_pcie_msi_post_process(pp); + + return IRQ_HANDLED; +} + +irqreturn_t (*msi_handler[PCIE_MAX_SEPA_IRQ_NUM])(int , void *) = { + exynos_pcie_msi0_handler, exynos_pcie_msi1_handler, exynos_pcie_msi2_handler, + exynos_pcie_msi3_handler, exynos_pcie_msi4_handler }; + +int register_separated_msi_vector(int ch_num, irq_handler_t handler, void *context, + int *irq_num) +{ + struct exynos_pcie *exynos_pcie = &g_pcie_rc[ch_num]; + struct dw_pcie *pci = exynos_pcie->pci; + struct pcie_port *pp = &pci->pp; + int i, ret; + + for (i = 1; i < PCIE_MAX_SEPA_IRQ_NUM; i++) { + if (!sep_msi_vec[ch_num][i].is_used) + break; + } + + if (i == PCIE_MAX_SEPA_IRQ_NUM) { + dev_info(pci->dev, "PCIe Ch%d : There is no empty MSI vector!\n", ch_num); + return -EBUSY; + } + + pr_info("PCIe Ch%d MSI%d vector is registered!\n", ch_num, i); + sep_msi_vec[ch_num][i].is_used = true; + sep_msi_vec[ch_num][i].context = context; + sep_msi_vec[ch_num][i].msi_irq_handler = handler; + *irq_num = sep_msi_vec[ch_num][i].irq; + + /* Enable MSI interrupt for separated MSI. */ + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, 0x1); + exynos_pcie_rc_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (i * MSI_REG_CTRL_BLOCK_SIZE), 4, ~(0x1)); + + ret = devm_request_irq(pci->dev, sep_msi_vec[ch_num][i].irq, + msi_handler[i], + IRQF_SHARED | IRQF_TRIGGER_HIGH, + sep_irq_name[i], pp); + if (ret) { + pr_err("failed to request MSI%d irq\n", i); + + return ret; + } + + return i * PCIE_MSI_MAX_VEC_NUM; +} +EXPORT_SYMBOL_GPL(register_separated_msi_vector); + +static int exynos_pcie_rc_add_port(struct platform_device *pdev, struct pcie_port *pp, int ch_num) { struct irq_domain *msi_domain; struct msi_domain_info *msi_domain_info; - int ret; + int ret, i, sep_irq; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct exynos_pcie *exynos_pcie = to_exynos_pcie(pci); pp->irq = platform_get_irq(pdev, 0); if (!pp->irq) { @@ -3629,8 +4167,45 @@ static int exynos_pcie_rc_add_port(struct platform_device *pdev, struct pcie_por return ret; } + if (exynos_pcie->separated_msi) { + for (i = 0; i < PCIE_MAX_SEPA_IRQ_NUM; i++) { + sep_irq = platform_get_irq(pdev, i + 1); + if (sep_irq < 0) + goto skip_sep_request_irq; + + dev_info(&pdev->dev, "%d separated MSI irq is defined.\n", sep_irq); + sep_msi_vec[ch_num][i].irq = sep_irq; + + /* MSI vector 0 will used by default MSI */ + if (i == 0) { + sep_msi_vec[ch_num][0].is_used = true; + ret = devm_request_irq(pci->dev, sep_msi_vec[ch_num][0].irq, + msi_handler[0], + IRQF_SHARED | IRQF_TRIGGER_HIGH, + sep_irq_name[0], pp); + if (ret) { + dev_err(&pdev->dev, "failed to request MSI%d irq\n", i); + return ret; + } + continue; + } + } + } + +skip_sep_request_irq: exynos_pcie_setup_rc(pp); + if (exynos_pcie->ep_device_type == EP_QC_WIFI) { + /* + * Set DMA mask to 32-bit because + * devices only work with 32-bit MSI. + */ + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); + if (ret) { + dev_err(&pdev->dev, "Failed to set DMA mask to 32-bit."); + } + } + ret = dw_pcie_host_init(pp); if (ret) { dev_err(&pdev->dev, "failed to dw pcie host init\n"); @@ -3642,6 +4217,12 @@ static int exynos_pcie_rc_add_port(struct platform_device *pdev, struct pcie_por msi_domain = pp->msi_domain; msi_domain_info = (struct msi_domain_info *)msi_domain->host_data; msi_domain_info->chip->irq_set_affinity = exynos_pcie_msi_set_affinity; + msi_domain_info->chip->irq_set_wake = exynos_pcie_rc_set_enable_wake; + if (exynos_pcie->ep_device_type == EP_QC_WIFI || + exynos_pcie->ep_device_type == EP_SAMSUNG_MODEM) { + msi_domain_info->chip->irq_mask = pci_msi_mask_irq; + msi_domain_info->chip->irq_unmask = pci_msi_unmask_irq; + } } return 0; @@ -3872,6 +4453,8 @@ static int exynos_pcie_rc_probe(struct platform_device *pdev) exynos_pcie->state = STATE_LINK_DOWN; exynos_pcie->linkdown_cnt = 0; + exynos_pcie->sudden_linkdown = 0; + exynos_pcie->cpl_timeout_recovery = 0; exynos_pcie->l1ss_ctrl_id_state = 0; exynos_pcie->atu_ok = 0; @@ -3879,6 +4462,16 @@ static int exynos_pcie_rc_probe(struct platform_device *pdev) exynos_pcie->app_req_exit_l1_mode = PCIE_APP_REQ_EXIT_L1_MODE; exynos_pcie->linkup_offset = PCIE_ELBI_RDLH_LINKUP; + exynos_pcie->log = NULL; + if (ch_num == 0) + exynos_pcie->log = logbuffer_register("pcie0"); + else if (ch_num == 1) + exynos_pcie->log = logbuffer_register("pcie1"); + else + dev_err(&pdev->dev, "invalid ch_num=%d for logbuffer registry\n", ch_num); + if (IS_ERR_OR_NULL(exynos_pcie->log)) + dev_err(&pdev->dev, "logbuffer register failed\n"); + pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); device_enable_async_suspend(&pdev->dev); @@ -3949,7 +4542,7 @@ static int exynos_pcie_rc_probe(struct platform_device *pdev) if (ret) goto probe_fail; - ret = exynos_pcie_rc_add_port(pdev, pp); + ret = exynos_pcie_rc_add_port(pdev, pp, ch_num); if (ret) goto probe_fail; @@ -3969,20 +4562,6 @@ static int exynos_pcie_rc_probe(struct platform_device *pdev) exynos_update_ip_idle_status(exynos_pcie->idle_ip_index, PCIE_IS_IDLE); dev_info(&pdev->dev, "%s, ip idle status : %d, idle_ip_index: %d\n", __func__, PCIE_IS_IDLE, exynos_pcie->idle_ip_index); - -/* Temporary remove: Need to enable to use sicd powermode */ -#if IS_ENABLED(CONFIG_EXYNOS_PCIE_SICD) - exynos_pcie->power_mode_nb.notifier_call = exynos_pcie_rc_power_mode_event; - exynos_pcie->power_mode_nb.next = NULL; - exynos_pcie->power_mode_nb.priority = 0; - - ret = exynos_cpupm_notifier_register(&exynos_pcie->power_mode_nb); - if (ret) { - dev_err(&pdev->dev, "Failed to register lpa notifier\n"); - - goto probe_fail; - } -#endif #endif exynos_pcie->pcie_wq = create_freezable_workqueue("pcie_wq"); @@ -4012,10 +4591,13 @@ static int exynos_pcie_rc_probe(struct platform_device *pdev) if (exynos_pcie->use_phy_isol_con) exynos_pcie_phy_isolation(exynos_pcie, PCIE_PHY_ISOLATION); - if (ret) + if (ret) { dev_err(&pdev->dev, "## %s: PCIe probe failed\n", __func__); - else + logbuffer_log(exynos_pcie->log, "PCIe %d: probe failed", ch_num); + } else { dev_info(&pdev->dev, "## %s: PCIe probe success\n", __func__); + logbuffer_log(exynos_pcie->log, "PCIe %d: probe done", ch_num); + } return ret; } @@ -4031,10 +4613,46 @@ static int __exit exynos_pcie_rc_remove(struct platform_device *pdev) static int exynos_pcie_rc_suspend_noirq(struct device *dev) { struct exynos_pcie *exynos_pcie = dev_get_drvdata(dev); + u32 val, val_irq0, val_irq1, val_irq2; if (exynos_pcie->state == STATE_LINK_DOWN) { - dev_dbg(dev, "PCIe PMU ISOLATION\n"); + dev_info(dev, "PCIe PMU ISOLATION\n"); exynos_pcie_phy_isolation(exynos_pcie, PCIE_PHY_ISOLATION); + + return 0; + } else if (exynos_pcie->separated_msi && exynos_pcie->use_pcieon_sleep) { + dev_info(dev, "PCIe on sleep... suspend\n"); + + /* handle IRQ0 interrupt */ + val_irq0 = exynos_elbi_read(exynos_pcie, PCIE_IRQ0); + exynos_elbi_write(exynos_pcie, val_irq0, PCIE_IRQ0); + dev_info(dev, "IRQ0 0x%x\n", val_irq0); + + /* handle IRQ1 interrupt */ + val_irq1 = exynos_elbi_read(exynos_pcie, PCIE_IRQ1); + exynos_elbi_write(exynos_pcie, val_irq1, PCIE_IRQ1); + dev_info(dev, "IRQ1 0x%x\n", val_irq1); + + /* handle IRQ2 interrupt */ + val_irq2 = exynos_elbi_read(exynos_pcie, PCIE_IRQ2); + exynos_elbi_write(exynos_pcie, val_irq2, PCIE_IRQ2); + dev_info(dev, "IRQ2 0x%x\n", val_irq2); + + val = exynos_elbi_read(exynos_pcie, PCIE_IRQ2_EN); + val |= IRQ_MSI_CTRL_EN_RISING_EDG; + exynos_elbi_write(exynos_pcie, val, PCIE_IRQ2_EN); + } + + if (exynos_pcie->use_pcieon_sleep && exynos_pcie->ep_pci_dev) { + dev_info(dev, "Default must_resume value : %d\n", + exynos_pcie->ep_pci_dev->dev.power.must_resume); + exynos_pcie->pcie_must_resume = exynos_pcie->ep_pci_dev->dev.power.must_resume; + if (exynos_pcie->ep_pci_dev->dev.power.must_resume) + exynos_pcie->ep_pci_dev->dev.power.must_resume = false; + + dev_info(dev, "restore enable cnt = %d\n", exynos_pcie->pcieon_sleep_enable_cnt); + atomic_set(&exynos_pcie->ep_pci_dev->enable_cnt, + exynos_pcie->pcieon_sleep_enable_cnt); } return 0; @@ -4044,12 +4662,18 @@ static int exynos_pcie_rc_resume_noirq(struct device *dev) { struct exynos_pcie *exynos_pcie = dev_get_drvdata(dev); struct dw_pcie *pci = exynos_pcie->pci; + u32 val; dev_dbg(dev, "## RESUME[%s] pcie_is_linkup: %d)\n", __func__, pcie_is_linkup); if (exynos_pcie->state == STATE_LINK_DOWN) { dev_dbg(dev, "[%s] dislink state after resume -> phy pwr off\n", __func__); exynos_pcie_rc_resumed_phydown(&pci->pp); + } else if (exynos_pcie->separated_msi && exynos_pcie->use_pcieon_sleep) { + dev_info(dev, "PCIe on sleep resume...\n"); + val = exynos_elbi_read(exynos_pcie, PCIE_IRQ2_EN); + val &= ~IRQ_MSI_CTRL_EN_RISING_EDG; + exynos_elbi_write(exynos_pcie, val, PCIE_IRQ2_EN); } return 0; @@ -4062,6 +4686,14 @@ static int exynos_pcie_suspend_prepare(struct device *dev) if (exynos_pcie->use_phy_isol_con) exynos_pcie_phy_isolation(exynos_pcie, PCIE_PHY_BYPASS); + if (exynos_pcie->use_pcieon_sleep && exynos_pcie->ep_pci_dev) { + exynos_pcie->pcieon_sleep_enable_cnt = + atomic_read(&exynos_pcie->ep_pci_dev->enable_cnt); + dev_info(dev, "remove enable cnt to fake enable = %d\n", + exynos_pcie->pcieon_sleep_enable_cnt); + atomic_set(&exynos_pcie->ep_pci_dev->enable_cnt, 0); + } + return 0; } @@ -4072,6 +4704,11 @@ static void exynos_pcie_resume_complete(struct device *dev) if (exynos_pcie->use_phy_isol_con && exynos_pcie->state == STATE_LINK_DOWN) exynos_pcie_phy_isolation(exynos_pcie, PCIE_PHY_ISOLATION); + else if (exynos_pcie->use_pcieon_sleep && exynos_pcie->ep_pci_dev) { + exynos_pcie->ep_pci_dev->dev.power.must_resume = exynos_pcie->pcie_must_resume; + dev_info(dev, "Default must_resume value : %d\n", + exynos_pcie->ep_pci_dev->dev.power.must_resume); + } } #endif diff --git a/drivers/pci/controller/dwc/pcie-exynos-rc.h b/drivers/pci/controller/dwc/pcie-exynos-rc.h index 05759c4dfcee..1ef65b09f34c 100644 --- a/drivers/pci/controller/dwc/pcie-exynos-rc.h +++ b/drivers/pci/controller/dwc/pcie-exynos-rc.h @@ -147,8 +147,11 @@ #define PORT_LINK_L12_LTR_THRESHOLD (0x40a0 << 16) #define PCIE_LINK_L1SS_CONTROL2 0x1A0 #define PORT_LINK_L1SS_ENABLE (0xf << 0) +#define PORT_LINK_TPOWERON_10US (0x28 << 0) #define PORT_LINK_TPOWERON_90US (0x49 << 0) #define PORT_LINK_TPOWERON_130US (0x69 << 0) +#define PORT_LINK_TPOWERON_180US (0x89 << 0) +#define PORT_LINK_TPOWERON_200US (0xA1 << 0) #define PORT_LINK_TPOWERON_3100US (0xfa << 0) #define PORT_LINK_L1SS_T_PCLKACK (0x3 << 6) #define PORT_LINK_L1SS_T_L1_2 (0x4 << 2) @@ -257,6 +260,7 @@ #define WIFI_ASPM_L12_EN (0x1 << 2) #define WIFI_ASPM_L11_EN (0x1 << 3) #define WIFI_COMMON_RESTORE_TIME (0xa << 8) /* Default Value */ +#define WIFI_QC_L12_LTR_THRESHOLD (0x4096 << 16) /* L1SS LTR Latency Register */ #define MAX_NO_SNOOP_LAT_VALUE_3 (3 << 16) @@ -309,6 +313,9 @@ #define PCIE_ATU_LOWER_TARGET_OUTBOUND2 0x300414 #define PCIE_ATU_UPPER_TARGET_OUTBOUND2 0x300418 +#define SECURE_ATU_ENABLE 0x5a5a5a5a +#define SMC_SECURE_ATU_SETUP 0x820020D8 + #define EXYNOS_IP_VER_OF_WHI 0x984500 #define EOM_PH_SEL_MAX 72 @@ -336,38 +343,45 @@ struct pcie_eom_result { void exynos_pcie_rc_phy_init(struct pcie_port *pp); -#if IS_ENABLED(CONFIG_EXYNOS_PCIE_IOMMU) -void pcie_sysmmu_enable(int ch_num); -void pcie_sysmmu_disable(int ch_num); -int pcie_iommu_map(int ch_num, unsigned long iova, phys_addr_t paddr, size_t size, int prot); -size_t pcie_iommu_unmap(int ch_num, unsigned long iova, size_t size); - -#else +#if !IS_ENABLED(CONFIG_EXYNOS_PCIE_IOMMU) extern struct dma_map_ops exynos_pcie_dma_ops; -static void __maybe_unused pcie_sysmmu_enable(int ch_num) +static void __maybe_unused pcie_sysmmu_enable(int hsi_block_num) { pr_err("PCIe SysMMU is NOT Enabled!!!\n"); } -static void __maybe_unused pcie_sysmmu_disable(int ch_num) +static void __maybe_unused pcie_sysmmu_disable(int hsi_block_num) { pr_err("PCIe SysMMU is NOT Enabled!!!\n"); } -static int __maybe_unused pcie_iommu_map(int ch_num, unsigned long iova, phys_addr_t paddr, - size_t size, int prot) +static int __maybe_unused pcie_iommu_map(unsigned long iova, phys_addr_t paddr, + size_t size, int prot, int hsi_block_num) { pr_err("PCIe SysMMU is NOT Enabled!!!\n"); - return -ENODEV; } -static size_t __maybe_unused pcie_iommu_unmap(int ch_num, unsigned long iova, size_t size) +static size_t __maybe_unused pcie_iommu_unmap(unsigned long iova, size_t size, + int hsi_block_num) { pr_err("PCIe SysMMU is NOT Enabled!!!\n"); + return 0; +} - return -ENODEV; +static void __maybe_unused pcie_sysmmu_set_use_iocc(int hsi_block_num) +{ + pr_err("PCIe SysMMU is NOT Enabled!!!\n"); +} +#endif + +#if !IS_ENABLED(CONFIG_GS_S2MPU) +static void __maybe_unused s2mpu_update_refcnt(struct device *dev, + dma_addr_t dma_addr, size_t size, + bool incr, enum dma_data_direction dir) +{ + pr_err("PCIe S2MPU is NOT Enabled!!!\n"); } #endif diff --git a/drivers/phy/samsung/phy-exynos-usbdp-gen2-v4.c b/drivers/phy/samsung/phy-exynos-usbdp-gen2-v4.c index 39f024d355bd..7a1bd94ca66b 100644 --- a/drivers/phy/samsung/phy-exynos-usbdp-gen2-v4.c +++ b/drivers/phy/samsung/phy-exynos-usbdp-gen2-v4.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include "phy-samsung-usb-cal.h" #include "phy-exynos-usb3p1-reg.h" #include "phy-exynos-usbdp-gen2-v4-reg.h" @@ -957,6 +959,476 @@ phy_exynos_usbdp_g2_v4_pma_default_sfr_update(struct exynos_usbphy_info writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG06ED); } +static inline void phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz(struct exynos_usbphy_info *info) +{ + void __iomem *regs_base = info->pma_base; + + /* 190627: CDR data mode exit GEN1 ON / GEN2 OFF */ + writel(0xff, regs_base + 0x0c8c); + writel(0xff, regs_base + 0x1c8c); + writel(0x7d, regs_base + 0x0c9c); + writel(0x7d, regs_base + 0x1c9c); + + /* 190708: Setting for improvement of EDS distribution */ + writel(0x06, regs_base + 0x0e7c); + writel(0x00, regs_base + 0x09e0); + writel(0x35, regs_base + 0x09e4); + writel(0x06, regs_base + 0x1e7c); + writel(0x00, regs_base + 0x19e0); + writel(0x35, regs_base + 0x19e4); + + /* 190707: Improve LVCC */ + writel(0x30, regs_base + 0x08f0); + writel(0x30, regs_base + 0x18f0); + + /* 190820: LFPS RX VIH shmoo hole */ + writel(0x0c, regs_base + 0x0a08); + writel(0x0c, regs_base + 0x1a08); + + /* 190820: Remove unrelated option for v4 phy */ + writel(0x05, regs_base + 0x0a0c); + writel(0x05, regs_base + 0x1a0c); + + /* 210521: Improve USB Gen2 LVCC */ + writel(0x1c, regs_base + 0x00f8); + writel(0x54, regs_base + 0x00fc); + + /* 191128: Change Vth of RCV_DET because of TD 7.40 Polling Retry Test */ + writel(0x05, regs_base + 0x104c); + writel(0x05, regs_base + 0x204c); + + /* Gen1 */ + writel(0x00, regs_base + 0x0ca8); + writel(0x00, regs_base + 0x1ca8); + writel(0x04, regs_base + 0x0cac); + writel(0x04, regs_base + 0x1cac); + + /* Gen2 */ + writel(0x00, regs_base + 0x0cb8); + writel(0x00, regs_base + 0x1cb8); + writel(0x04, regs_base + 0x0cbc); + writel(0x04, regs_base + 0x1cbc); + + /* CDR Lock Delay for JTOL Link Training */ + writel(0x03, regs_base + 0x0320); + writel(0x23, regs_base + 0x0324); + + /* common reset for 4lane tx */ + writel(0x63, regs_base + 0x0858); + writel(0x63, regs_base + 0x1858); + writel(0x63, regs_base + 0x1058); + writel(0x63, regs_base + 0x2058); + + /* + * Change rx rterm to 90 ohm + */ + writel(0xA0, regs_base + 0x0BB4); + writel(0xA0, regs_base + 0x1BB4); + + /* + * added setting + */ + writel(0x0C, regs_base + 0x0A08); + writel(0x0C, regs_base + 0x1A08); + + writel(0x2B, regs_base + 0x0DEC); + writel(0x2B, regs_base + 0x1DEC); + + /* change rx_hf_cs_ctrl[7:6] */ + writel(0x7F, regs_base + 0x0934); + writel(0x7F, regs_base + 0x1934); + /* change rx_vga_rl_ctrl[5:3] */ + writel(0x32, regs_base + 0x0948); + writel(0x32, regs_base + 0x1948); + /* change vga_bin_ssp[5:1] */ + writel(0x00, regs_base + 0x0DF4); + writel(0x00, regs_base + 0x1DF4); + + writel(0x1D, regs_base + 0x091C); + writel(0x1D, regs_base + 0x191C); + + writel(0x0C, regs_base + 0x0928); + writel(0x0C, regs_base + 0x1928); + + writel(0x3C, regs_base + 0x0E0C); + writel(0x3C, regs_base + 0x1E0C); + + writel(0x04, regs_base + 0x0EBC); + writel(0x04, regs_base + 0x1EBC); + + writel(0x10, regs_base + 0x0908); + writel(0x10, regs_base + 0x1908); + +} + +static inline void phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz_Gen2(struct exynos_usbphy_info *info) +{ + void __iomem *regs_base = info->pma_base; + u32 reg; + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0101); + reg &= USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_CLR; + reg |= USBDP_CMN_REG0101_TIME_CDR_WATCHDOG_WAIT_RESTART__7_0_SET(0xBB); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0101); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG012C); + reg &= USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_CLR; + reg |= USBDP_CMN_REG012C_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SP_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG012C); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG012D); + reg &= USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_CLR; + reg |= USBDP_CMN_REG012D_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SP_SET(0x3); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG012D); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0134); + reg &= USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_CLR; + reg |= USBDP_CMN_REG0134_RX_LFPS_DET_FILT_TH3_SHORT_RISE_SSP_SET(0x3); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0134); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0135); + reg &= USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_CLR; + reg |= USBDP_CMN_REG0135_RX_LFPS_DET_FILT_TH3_SHORT_FALL_SSP_SET(0x3); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0135); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG013C); + reg &= USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_CLR; + reg |= USBDP_CMN_REG013C_RX_LFPS_DET_FILT_TH3_LONG_RISE_SP_SET(0x0F); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG013C); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG013D); + reg &= USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_CLR; + reg |= USBDP_CMN_REG013D_RX_LFPS_DET_FILT_TH3_LONG_FALL_SP_SET(0x0F); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG013D); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0144); + reg &= USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_CLR; + reg |= USBDP_CMN_REG0144_RX_LFPS_DET_FILT_TH3_LONG_RISE_SSP_SET(0x0F); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0144); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0145); + reg &= USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_CLR; + reg |= USBDP_CMN_REG0145_RX_LFPS_DET_FILT_TH3_LONG_FALL_SSP_SET(0x0F); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0145); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG016A); + reg &= USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_CLR; + reg |= USBDP_CMN_REG016A_TX_LFPS_TP_GEN_T_PWM_SET(0x2B); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG016A); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG016B); + reg &= USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_CLR; + reg |= USBDP_CMN_REG016B_TX_LFPS_TP_GEN_T_LFPS0_SET(0x0F); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG016B); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG016C); + reg &= USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_CLR; + reg |= USBDP_CMN_REG016C_TX_LFPS_TP_GEN_T_LFPS1_SET(0x1E); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG016C); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG016F); + reg &= USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_CLR; + reg |= USBDP_CMN_REG016F_BIAS_ICAL_AUTO_COMP_EN_DELAY_SET(0x13); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG016F); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0170); + reg &= USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_CLR; + reg |= USBDP_CMN_REG0170_BIAS_ICAL_AUTO_CODE_DELAY_SET(0x13); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0170); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG031A); + reg &= USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_CLR; + reg |= USBDP_TRSV_REG031A_LN0_TG_RXD_COMP_DELAY_TIME__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG031A); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG031B); + reg &= USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_CLR; + reg |= USBDP_TRSV_REG031B_LN0_TG_RXD_COMP_DELAY_TIME__7_0_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG031B); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0324); + reg &= USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_CLR; + reg |= USBDP_TRSV_REG0324_LN0_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0324); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032A); + reg &= USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_CLR; + reg |= USBDP_TRSV_REG032A_LN0_RX_VALID_RSTN_DELAY_RISE_SP__15_8_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032A); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032B); + reg &= USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_CLR; + reg |= USBDP_TRSV_REG032B_LN0_RX_VALID_RSTN_DELAY_RISE_SP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032B); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032C); + reg &= USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_CLR; + reg |= USBDP_TRSV_REG032C_LN0_RX_VALID_RSTN_DELAY_FALL_SP__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032C); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032D); + reg &= USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_CLR; + reg |= USBDP_TRSV_REG032D_LN0_RX_VALID_RSTN_DELAY_FALL_SP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032D); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032E); + reg &= USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_CLR; + reg |= USBDP_TRSV_REG032E_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032E); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG032F); + reg &= USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG032F_LN0_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG032F); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0330); + reg &= USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_CLR; + reg |= USBDP_TRSV_REG0330_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0330); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0331); + reg &= USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG0331_LN0_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0331); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG071A); + reg &= USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_CLR; + reg |= USBDP_TRSV_REG071A_LN2_TG_RXD_COMP_DELAY_TIME__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG071A); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG071B); + reg &= USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_CLR; + reg |= USBDP_TRSV_REG071B_LN2_TG_RXD_COMP_DELAY_TIME__7_0_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG071B); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0724); + reg &= USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_CLR; + reg |= USBDP_TRSV_REG0724_LN2_RX_CDR_DATA_MODE_EXIT_EXTEND_SP_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0724); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072A); + reg &= USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_CLR; + reg |= USBDP_TRSV_REG072A_LN2_RX_VALID_RSTN_DELAY_RISE_SP__15_8_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072A); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072B); + reg &= USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_CLR; + reg |= USBDP_TRSV_REG072B_LN2_RX_VALID_RSTN_DELAY_RISE_SP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072B); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072C); + reg &= USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_CLR; + reg |= USBDP_TRSV_REG072C_LN2_RX_VALID_RSTN_DELAY_FALL_SP__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072C); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072D); + reg &= USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_CLR; + reg |= USBDP_TRSV_REG072D_LN2_RX_VALID_RSTN_DELAY_FALL_SP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072D); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072E); + reg &= USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_CLR; + reg |= USBDP_TRSV_REG072E_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__15_8_SET(0x03); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072E); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG072F); + reg &= USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG072F_LN2_RX_VALID_RSTN_DELAY_RISE_SSP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG072F); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0730); + reg &= USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_CLR; + reg |= USBDP_TRSV_REG0730_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__15_8_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0730); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0731); + reg &= USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG0731_LN2_RX_VALID_RSTN_DELAY_FALL_SSP__7_0_SET(0x00); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0731); +} + +static inline void phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz_Gen1(struct exynos_usbphy_info *info) +{ + + void __iomem *regs_base = info->pma_base; + u32 reg; + + /* --- Common Block --- */ + + /* ana_lcpll_pms_mdiv, mdiv_afc*/ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0027); + reg &= USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_CLR; + reg |= USBDP_CMN_REG0027_ANA_LCPLL_PMS_MDIV_SET(0x82); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0027); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0028); + reg &= USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_CLR; + + reg |= USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_SET(0x82); + // Fixed: 20210514 + // reg |= USBDP_CMN_REG0028_ANA_LCPLL_PMS_MDIV_AFC_SET(0xD4); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0028); + + /*lcpll_pms_sdiv_sp, ssp*/ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG002A); + reg &= USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_CLR; + reg |= USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SP_SET(0x3); + reg &= USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_CLR; + reg |= USBDP_CMN_REG002A_LCPLL_PMS_SDIV_SSP_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG002A); + + /* IQ Div for LC VCO and RO bypass */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG002D); + reg &= USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_CLR; + reg |= USBDP_CMN_REG002D_ANA_LCPLL_IQDIV_BYPASS_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG002D); + + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0074); + reg &= USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_CLR; + reg |= USBDP_CMN_REG0074_ANA_ROPLL_IQDIV_BYPASS_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0074); + + /* Numerator of SDM with i_lcpll_sdm_numerator_sign (-255~255) */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0034); + reg &= USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_CLR; + reg |= USBDP_CMN_REG0034_ANA_LCPLL_SDM_NUMERATOR_SET(0x10); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0034); + + /* Denominator of SDM (Max. 255) */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0032); + reg &= USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_CLR; + reg |= USBDP_CMN_REG0032_ANA_LCPLL_SDM_DENOMINATOR_SET(0x27); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0032); + + /* LC PLL input clk phase, SDC divide-ratio */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0035); + reg &= USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_CLR; + reg |= USBDP_CMN_REG0035_ANA_LCPLL_SDM_PH_NUM_SEL_SET(0x0); + reg &= USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_CLR; + reg |= USBDP_CMN_REG0035_ANA_LCPLL_SDC_N_SET(0x5); + reg &= USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_CLR; + reg |= USBDP_CMN_REG0035_ANA_LCPLL_SDC_N2_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0035); + + /* RO PLL PI input clock phase number 0: 8-phase, 1: 4-phase */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0086); + reg &= USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_CLR; + reg |= USBDP_CMN_REG0086_ANA_ROPLL_SDM_PH_NUM_SEL_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0086); + + /* RO PLL SDC divide-ratio selection */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0089); + reg &= USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_CLR; + reg |= USBDP_CMN_REG0089_ANA_ROPLL_SDC_N2_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0089); + + /* RO PLL numerator of SDC (Max 65) */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0036); + reg &= USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_CLR; + reg |= USBDP_CMN_REG0036_ANA_LCPLL_SDC_NUMERATOR_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0036); + + /* LC PLL denominator of SDC (Max 65) */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0037); + reg &= USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_CLR; + reg |= USBDP_CMN_REG0037_ANA_LCPLL_SDC_DENOMINATOR_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0037); + + /* LC PLL SSC modulation deviation control */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG0039); + reg &= USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_CLR; + reg |= USBDP_CMN_REG0039_ANA_LCPLL_SSC_FM_DEVIATION_SET(0x32); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG0039); + + /* LC PLL SSC modulation frequency control */ + reg = readl(regs_base + EXYNOS_USBDP_CMN_REG003A); + reg &= USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_CLR; + reg |= USBDP_CMN_REG003A_ANA_LCPLL_SSC_FM_FREQ_SET(0x5); + writel(reg, regs_base + EXYNOS_USBDP_CMN_REG003A); + + /* --- TRSV Block --- */ + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG02B6); + reg &= USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_CLR; + reg |= USBDP_TRSV_REG02B6_LN0_RX_CDR_PMS_M_SP__8_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG02B6); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG02B7); + reg &= USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_CLR; + // modified + reg |= USBDP_TRSV_REG02B7_LN0_RX_CDR_PMS_M_SP__7_0_SET(0x82); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG02B7); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG02B8); + reg &= USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_CLR; + reg |= USBDP_TRSV_REG02B8_LN0_RX_CDR_PMS_M_SSP__8_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG02B8); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG02B9); + reg &= USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG02B9_LN0_RX_CDR_PMS_M_SSP__7_0_SET(0x4); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG02B9); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0386); + reg &= USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_CLR; + reg |= USBDP_TRSV_REG0386_LN0_RX_CDR_AFC_PMS_M_SP__8_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0386); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0387); + reg &= USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_CLR; + reg |= USBDP_TRSV_REG0387_LN0_RX_CDR_AFC_PMS_M_SP__7_0_SET(0x82); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0387); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0388); + reg &= USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_CLR; + reg |= USBDP_TRSV_REG0388_LN0_RX_CDR_AFC_PMS_M_SSP__8_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0388); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0389); + reg &= USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG0389_LN0_RX_CDR_AFC_PMS_M_SSP__7_0_SET(0x4); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0389); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG06B6); + reg &= USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_CLR; + reg |= USBDP_TRSV_REG06B6_LN2_RX_CDR_PMS_M_SP__8_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG06B6); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG06B7); + reg &= USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_CLR; + reg |= USBDP_TRSV_REG06B7_LN2_RX_CDR_PMS_M_SP__7_0_SET(0x82); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG06B7); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG06B8); + reg &= USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_CLR; + reg |= USBDP_TRSV_REG06B8_LN2_RX_CDR_PMS_M_SSP__8_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG06B8); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG06B9); + reg &= USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG06B9_LN2_RX_CDR_PMS_M_SSP__7_0_SET(0x4); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG06B9); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0786); + reg &= USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_CLR; + reg |= USBDP_TRSV_REG0786_LN2_RX_CDR_AFC_PMS_M_SP__8_SET(0x0); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0786); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0787); + reg &= USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_CLR; + reg |= USBDP_TRSV_REG0787_LN2_RX_CDR_AFC_PMS_M_SP__7_0_SET(0x82); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0787); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0788); + reg &= USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_CLR; + reg |= USBDP_TRSV_REG0788_LN2_RX_CDR_AFC_PMS_M_SSP__8_SET(0x1); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0788); + + reg = readl(regs_base + EXYNOS_USBDP_TRSV_REG0789); + reg &= USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_CLR; + reg |= USBDP_TRSV_REG0789_LN2_RX_CDR_AFC_PMS_M_SSP__7_0_SET(0x4); + writel(reg, regs_base + EXYNOS_USBDP_TRSV_REG0789); +} + static void phy_exynos_usbdp_g2_v4_set_pcs(struct exynos_usbphy_info *info) { void __iomem *regs_base = info->pcs_base; @@ -2717,10 +3189,31 @@ int phy_exynos_usbdp_g2_v4_enable(struct exynos_usbphy_info *info) int ret = 0; struct reg_set *reg_base = (struct reg_set *)info->pma_base; + struct device *dev = info->dev; + u32 phy_ref_clock = 0; phy_exynos_usbdp_g2_v4_ctrl_pma_ready(info); phy_exynos_usbdp_g2_v4_aux_force_off(info); - phy_exynos_usbdp_g2_v4_pma_default_sfr_update(info); + + if(dev) { + ret = of_property_read_u32(dev->of_node, "phy_ref_clock", &phy_ref_clock); + if (ret < 0) { + dev_err(dev, "Couldn't read phy_ref_clock %s node, error = %d\n", + dev->of_node->name, ret); + } + } + + if(phy_ref_clock == 19200000) { + // pma default sfr updated for RefClk 19.2Mhz + phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz(info); + // pma configuration for RefClk 19.2Mhz-Gen1 + phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz_Gen1(info); + // pma configuration for RefClk 19.2Mhz-Gen2 + phy_exynos_usbdp_g2_v4_pma_default_sfr_update_19_2Mhz_Gen2(info); + } else { + phy_exynos_usbdp_g2_v4_pma_default_sfr_update(info); + } + phy_exynos_usbdp_g2_v4_set_pcs(info); phy_exynos_usbdp_g2_v4_tune(info); phy_exynos_usbdp_g2_v4_pma_lane_mux_sel(info); diff --git a/drivers/phy/samsung/phy-exynos-usbdrd.c b/drivers/phy/samsung/phy-exynos-usbdrd.c index d4b9a76f27b0..d41dd968638f 100644 --- a/drivers/phy/samsung/phy-exynos-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos-usbdrd.c @@ -43,6 +43,7 @@ //#include #include +#include #undef pr_info #undef pr_debug @@ -1610,6 +1611,7 @@ static void exynos_usbdrd_pipe3_init(struct exynos_usbdrd_phy *phy_drd) phy_drd->usbphy_info.used_phy_port); } + phy_drd->usbphy_sub_info.dev = phy_drd->dev; phy_exynos_usb_v3p1_g2_pma_ready(&phy_drd->usbphy_info); phy_exynos_usbdp_g2_v4_enable(&phy_drd->usbphy_sub_info); #endif @@ -2125,6 +2127,29 @@ int exynos_usbdrd_vdd_hsi_manual_control(bool on) } EXPORT_SYMBOL_GPL(exynos_usbdrd_vdd_hsi_manual_control); +int exynos_usbdrd_s2mpu_manual_control(bool on) +{ + struct exynos_usbdrd_phy *phy_drd; + + if (!IS_ENABLED(CONFIG_PKVM_S2MPU)) + return 0; + + pr_debug("%s s2mpu = %d\n", __func__, on); + + phy_drd = exynos_usbdrd_get_struct(); + if (!phy_drd) { + pr_err("[%s] exynos_usbdrd_get_struct error\n", __func__); + return -ENODEV; + } + + if (!phy_drd->s2mpu) + return 0; + + return on ? pkvm_s2mpu_resume(phy_drd->s2mpu) + : pkvm_s2mpu_suspend(phy_drd->s2mpu); +} +EXPORT_SYMBOL_GPL(exynos_usbdrd_s2mpu_manual_control); + bool exynos_usbdrd_get_ldo_status(void) { struct exynos_usbdrd_phy *phy_drd; @@ -2267,10 +2292,19 @@ static int exynos_usbdrd_phy_probe(struct platform_device *pdev) struct regmap *reg_pmu; struct device_node *syscon_np; struct resource pmu_res; + struct device *s2mpu = NULL; u32 pmu_offset, pmu_offset_dp, pmu_offset_tcxo; u32 pmu_mask, pmu_mask_tcxo, pmu_mask_pll; int i, ret; + if (IS_ENABLED(CONFIG_PKVM_S2MPU)) { + s2mpu = pkvm_s2mpu_of_parse(dev); + if (IS_ERR(s2mpu)) + return PTR_ERR(s2mpu); + if (s2mpu && !pkvm_s2mpu_ready(s2mpu)) + return -EPROBE_DEFER; + } + pr_info("%s: +++ %s %s\n", __func__, dev->init_name, pdev->name); phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL); if (!phy_drd) @@ -2278,6 +2312,7 @@ static int exynos_usbdrd_phy_probe(struct platform_device *pdev) dev_set_drvdata(dev, phy_drd); phy_drd->dev = dev; + phy_drd->s2mpu = s2mpu; match = of_match_node(exynos_usbdrd_phy_of_match, pdev->dev.of_node); diff --git a/drivers/phy/samsung/phy-exynos-usbdrd.h b/drivers/phy/samsung/phy-exynos-usbdrd.h index 74097ab823fd..3b2cfb35a89f 100644 --- a/drivers/phy/samsung/phy-exynos-usbdrd.h +++ b/drivers/phy/samsung/phy-exynos-usbdrd.h @@ -205,6 +205,7 @@ struct exynos_usbdrd_phy { struct extcon_dev *edev; struct notifier_block usb_nb; struct notifier_block usb_host_nb; + struct device *s2mpu; /* eom related parameters */ struct usb_eom_result_s *eom_result; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c90bcf286807..425965733bb0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -439,4 +439,12 @@ config PINCTRL_SLG51000 Say y here to support for the Dialog Semiconductor SLG51000. The SLG51000 is seven compact and customizable low dropout regulators. +config PINCTRL_SLG51002 + tristate "Dialog Semiconductor SLG51002 pinctrl driver" + depends on I2C + select REGMAP_I2C + help + Say y here to support for the Dialog Semiconductor SLG51002. + The SLG51002 is eight compact and customizable low dropout regulators. + endif diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 011bfc0455d6..e81077411a03 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o obj-$(CONFIG_PINCTRL_SLG51000) += pinctrl-slg51000.o +obj-$(CONFIG_PINCTRL_SLG51002) += pinctrl-slg51002.o obj-y += actions/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ diff --git a/drivers/pinctrl/pinctrl-slg51002.c b/drivers/pinctrl/pinctrl-slg51002.c new file mode 100644 index 000000000000..8a5b24532e56 --- /dev/null +++ b/drivers/pinctrl/pinctrl-slg51002.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * slg51002 pinctrl driver + * + * Copyright (C) 2021 Google, LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct slg51002_pinctrl { + struct gpio_chip gc; + + struct pinctrl_ops pctrl_ops; + struct pinmux_ops pmux_ops; + struct pinconf_ops pconf_ops; + struct pinctrl_desc pctrl; + + struct regmap *regmap; + struct slg51002_dev *chip; +}; + +static const struct pinctrl_pin_desc slg51002_pins[] = { + PINCTRL_PIN(SLG51002_GPIO1, "gpio1"), + PINCTRL_PIN(SLG51002_GPIO2, "gpio2"), + PINCTRL_PIN(SLG51002_GPIO3, "gpio3"), + PINCTRL_PIN(SLG51002_GPIO4, "gpio4"), + PINCTRL_PIN(SLG51002_SEQ1, "seq1"), + PINCTRL_PIN(SLG51002_SEQ2, "seq2"), + PINCTRL_PIN(SLG51002_SEQ3, "seq3"), + PINCTRL_PIN(SLG51002_SEQ4, "seq4"), +}; + +static const struct pinctrl_pin_desc slg51002_generic_seq_pins[] = { + PINCTRL_PIN(SLG51002_GENERIC_SEQ0, "seq0"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ1, "seq1"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ2, "seq2"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ3, "seq3"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ4, "seq4"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ5, "seq5"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ6, "seq6"), + PINCTRL_PIN(SLG51002_GENERIC_SEQ7, "seq7"), +}; + +static const int slg51002_ctrl_bit_tbl[] = { + BIT(4), BIT(5), BIT(6), BIT(7), /* gpio1, gpio2, gpio3, gpio4 */ + BIT(0), BIT(1), BIT(2), BIT(3) /* seq1, seq2, seq3 seq4 */ +}; + +/* gpio_chip functions */ +static int slg51002_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + int ret; + unsigned int addr; + unsigned int val; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + switch (offset) { + case SLG51002_GPIO1: + addr = SLG51002_IO_GPIO1_CONF; + break; + case SLG51002_GPIO2: + addr = SLG51002_IO_GPIO2_CONF; + break; + case SLG51002_GPIO3: + addr = SLG51002_IO_GPIO3_CONF; + break; + case SLG51002_GPIO4: + addr = SLG51002_IO_GPIO4_CONF; + break; + case SLG51002_SEQ1: + case SLG51002_SEQ2: + case SLG51002_SEQ3: + case SLG51002_SEQ4: + return GPIOF_DIR_OUT; + default: + return -EOPNOTSUPP; + } + + ret = regmap_read(data->regmap, addr, &val); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + return ret; + } + + return (val & SLG51002_GPIO_DIR_MASK) ? GPIOF_DIR_OUT : GPIOF_DIR_IN; +} + +static int slg51002_generic_seq_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + switch (offset) { + case SLG51002_GENERIC_SEQ0: + case SLG51002_GENERIC_SEQ1: + case SLG51002_GENERIC_SEQ2: + case SLG51002_GENERIC_SEQ3: + case SLG51002_GENERIC_SEQ4: + case SLG51002_GENERIC_SEQ5: + case SLG51002_GENERIC_SEQ6: + case SLG51002_GENERIC_SEQ7: + return GPIOF_DIR_OUT; + default: + return -EOPNOTSUPP; + } +} + +static int slg51002_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + unsigned int val; + unsigned int addr; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + switch (offset) { + case SLG51002_GPIO1: + addr = GPIO1_CTRL; + break; + case SLG51002_GPIO2: + addr = GPIO2_CTRL; + break; + case SLG51002_GPIO3: + addr = GPIO3_CTRL; + break; + case SLG51002_GPIO4: + addr = GPIO4_CTRL; + break; + default: + return -EOPNOTSUPP; + } + + ret = regmap_read(data->regmap, addr, &val); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + return ret; + } + + return val; +} + +static void slg51002_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int ret; + int val = !!value; /* convert value to 0/1 */ + unsigned int addr; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + if (data->chip->enter_sw_test_mode) + data->chip->enter_sw_test_mode(data->regmap); + + switch (offset) { + case SLG51002_GPIO1: + addr = GPIO1_CTRL; + break; + case SLG51002_GPIO2: + addr = GPIO2_CTRL; + break; + case SLG51002_GPIO3: + addr = GPIO3_CTRL; + break; + case SLG51002_GPIO4: + addr = GPIO4_CTRL; + break; + default: + dev_err(data->chip->dev, "Unsupported GPIO offset %d\n", offset); + return; + } + + ret = regmap_write(data->regmap, addr, val); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + } + + if (data->chip->exit_sw_test_mode) + data->chip->exit_sw_test_mode(data->regmap); +} + +static int slg51002_gpio_seq_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + unsigned int val; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + ret = regmap_read(data->regmap, SLG51002_SYSCTL_MATRIX_CONF_A, &val); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + return ret; + } + + return val & slg51002_ctrl_bit_tbl[offset]; +} + +static void slg51002_gpio_seq_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + int ret; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + ret = regmap_update_bits(data->regmap, SLG51002_SYSCTL_MATRIX_CONF_A, + slg51002_ctrl_bit_tbl[offset], + value ? slg51002_ctrl_bit_tbl[offset] : 0); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + } + + return; +} + +static int slg51002_generic_seq_get(struct gpio_chip *chip, unsigned int offset) +{ + int ret; + unsigned int val; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + ret = regmap_read(data->regmap, SLG51002_SYSCTL_MATRIX_CONF_A, &val); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + return ret; + } + + return val & BIT(offset); +} + +static void slg51002_generic_seq_set(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + ret = regmap_update_bits(data->regmap, SLG51002_SYSCTL_MATRIX_CONF_A, + BIT(offset), + value ? BIT(offset) : 0); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + } + + return; +} + +static int slg51002_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + int ret; + unsigned int addr; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + if (data->chip->enter_sw_test_mode) + data->chip->enter_sw_test_mode(data->regmap); + + switch (offset) { + case SLG51002_GPIO1: + addr = SLG51002_IO_GPIO1_CONF; + break; + case SLG51002_GPIO2: + addr = SLG51002_IO_GPIO2_CONF; + break; + case SLG51002_GPIO3: + addr = SLG51002_IO_GPIO3_CONF; + break; + case SLG51002_GPIO4: + addr = SLG51002_IO_GPIO4_CONF; + break; + default: + dev_err(data->chip->dev, "Unsupported GPIO offset %d\n", offset); + ret = -EOPNOTSUPP; + goto out; + } + + ret = regmap_update_bits(data->regmap, addr, SLG51002_GPIO_DIR_MASK, 0); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + } + +out: + if (data->chip->exit_sw_test_mode) + data->chip->exit_sw_test_mode(data->regmap); + + return ret; +} + +static int slg51002_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + int ret; + unsigned int addr; + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + if (data->chip->enter_sw_test_mode) + data->chip->enter_sw_test_mode(data->regmap); + + switch (offset) { + case SLG51002_GPIO1: + addr = SLG51002_IO_GPIO1_CONF; + break; + case SLG51002_GPIO2: + addr = SLG51002_IO_GPIO2_CONF; + break; + case SLG51002_GPIO3: + addr = SLG51002_IO_GPIO3_CONF; + break; + case SLG51002_GPIO4: + addr = SLG51002_IO_GPIO4_CONF; + break; + case SLG51002_SEQ1: + case SLG51002_SEQ2: + case SLG51002_SEQ3: + case SLG51002_SEQ4: + ret = 0; + goto out1; + default: + dev_err(data->chip->dev, "Unsupported GPIO offset %d\n", + offset); + ret = -EOPNOTSUPP; + goto out; + } + + ret = regmap_update_bits(data->regmap, addr, SLG51002_GPIO_DIR_MASK, + BIT(SLG51002_GPIO_DIR_SHIFT)); + if (ret < 0) { + dev_err(data->chip->dev, "Failed on GPIO offset %d\n", offset); + goto out; + } + +out1: + if (data->gc.set) + data->gc.set(chip, offset, value); + +out: + if (data->chip->exit_sw_test_mode) + data->chip->exit_sw_test_mode(data->regmap); + + return ret; +} + +static int slg51002_generic_seq_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + return -EOPNOTSUPP; +} + +static int slg51002_generic_seq_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct slg51002_pinctrl *data = gpiochip_get_data(chip); + + switch (offset) { + case SLG51002_GENERIC_SEQ0: + case SLG51002_GENERIC_SEQ1: + case SLG51002_GENERIC_SEQ2: + case SLG51002_GENERIC_SEQ3: + case SLG51002_GENERIC_SEQ4: + case SLG51002_GENERIC_SEQ5: + case SLG51002_GENERIC_SEQ6: + case SLG51002_GENERIC_SEQ7: + if (data->gc.set) + data->gc.set(chip, offset, value); + return 0; + default: + dev_err(data->chip->dev, "Unsupported GPIO offset %d\n", + offset); + return -EOPNOTSUPP; + } +} + +/* pinctrl_ops functions */ +static int slg51002_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *slg51002_pinctrl_get_group_name( + struct pinctrl_dev *pctldev, unsigned int group) +{ + return NULL; +} + +/* pinmux_ops functions */ +static int slg51002_pinmux_get_funcs_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *slg51002_pinmux_get_func_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return NULL; +} + +static int slg51002_pinmux_get_func_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const num_groups) +{ + return -EOPNOTSUPP; +} + +static int slg51002_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + return -EOPNOTSUPP; +} + +static int slg51002_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + return 0; +} + +/* pinconf_ops functions */ +static int slg51002_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + return 0; +} + +static int slg51002_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + return 0; +} + +static int slg51002_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + struct slg51002_pinctrl *slg51002_pctl; + struct pinctrl_dev *pctl; + u32 ngpios; + const char *pinctrl_of_name = NULL; + + slg51002_pctl = devm_kzalloc(&pdev->dev, + sizeof(struct slg51002_pinctrl), GFP_KERNEL); + if (!slg51002_pctl) + return -ENOMEM; + + slg51002_pctl->chip = dev_get_drvdata(pdev->dev.parent); + + if (slg51002_pctl->chip->op_mode != SLG51002_OP_MODE_LDO_GPIO && + slg51002_pctl->chip->op_mode != SLG51002_OP_MODE_SEQ_GPIO && + slg51002_pctl->chip->op_mode != SLG51002_OP_MODE_SEQ_GENERIC) + return -ENODEV; + + /* Get regmap */ + slg51002_pctl->regmap = slg51002_pctl->chip->regmap; + + /* GPIO config */ + slg51002_pctl->gc.label = pdev->name; + slg51002_pctl->gc.parent = &pdev->dev; + + if (slg51002_pctl->chip->op_mode == SLG51002_OP_MODE_SEQ_GENERIC) { + slg51002_pctl->gc.get_direction = + slg51002_generic_seq_get_direction; + slg51002_pctl->gc.get = slg51002_generic_seq_get; + slg51002_pctl->gc.set = slg51002_generic_seq_set; + slg51002_pctl->gc.direction_input = + slg51002_generic_seq_direction_input; + slg51002_pctl->gc.direction_output = + slg51002_generic_seq_direction_output; + } else { + slg51002_pctl->gc.get_direction = slg51002_gpio_get_direction; + if (slg51002_pctl->chip->op_mode == SLG51002_OP_MODE_SEQ_GPIO) { + slg51002_pctl->gc.get = slg51002_gpio_seq_get; + slg51002_pctl->gc.set = slg51002_gpio_seq_set; + } else { + slg51002_pctl->gc.get = slg51002_gpio_get; + slg51002_pctl->gc.set = slg51002_gpio_set; + } + slg51002_pctl->gc.direction_input = + slg51002_gpio_direction_input; + slg51002_pctl->gc.direction_output = + slg51002_gpio_direction_output; + } + + slg51002_pctl->gc.base = -1; + slg51002_pctl->gc.can_sleep = true; + slg51002_pctl->gc.of_node = + of_find_node_by_name(pdev->dev.parent->of_node, pdev->name); + slg51002_pctl->gc.set_config = gpiochip_generic_config; + slg51002_pctl->gc.request = gpiochip_generic_request; + slg51002_pctl->gc.free = gpiochip_generic_free; + + if (!slg51002_pctl->gc.of_node) { + dev_err(&pdev->dev, "Failed to find %s DT node\n", pdev->name); + return -EINVAL; + } + if (of_property_read_u32(slg51002_pctl->gc.of_node, + "ngpios", &ngpios)) { + dev_err(&pdev->dev, "Failed to get ngpios from %s DT node\n", + pdev->name); + return -EINVAL; + } + slg51002_pctl->gc.ngpio = ngpios; + + /* pinctrl config */ + slg51002_pctl->pctrl_ops.get_groups_count = + slg51002_pinctrl_get_groups_count; + slg51002_pctl->pctrl_ops.get_group_name = + slg51002_pinctrl_get_group_name; + slg51002_pctl->pctrl_ops.dt_node_to_map = + pinconf_generic_dt_node_to_map_pin; + slg51002_pctl->pctrl_ops.dt_free_map = pinconf_generic_dt_free_map; + + slg51002_pctl->pmux_ops.get_functions_count = + slg51002_pinmux_get_funcs_count; + slg51002_pctl->pmux_ops.get_function_name = + slg51002_pinmux_get_func_name; + slg51002_pctl->pmux_ops.get_function_groups = + slg51002_pinmux_get_func_groups; + slg51002_pctl->pmux_ops.set_mux = slg51002_pinmux_set_mux; + slg51002_pctl->pmux_ops.gpio_set_direction = + slg51002_pinmux_gpio_set_direction; + + slg51002_pctl->pconf_ops.is_generic = true; + slg51002_pctl->pconf_ops.pin_config_get = slg51002_pinconf_get; + slg51002_pctl->pconf_ops.pin_config_set = slg51002_pinconf_set; + + /* pins defined in chip */ + if (slg51002_pctl->chip->op_mode == SLG51002_OP_MODE_SEQ_GENERIC) { + slg51002_pctl->pctrl.pins = slg51002_generic_seq_pins; + slg51002_pctl->pctrl.npins = + ARRAY_SIZE(slg51002_generic_seq_pins); + } else { + slg51002_pctl->pctrl.pins = slg51002_pins; + slg51002_pctl->pctrl.npins = ARRAY_SIZE(slg51002_pins); + } + + slg51002_pctl->pctrl.pctlops = &slg51002_pctl->pctrl_ops; + slg51002_pctl->pctrl.pmxops = &slg51002_pctl->pmux_ops; + slg51002_pctl->pctrl.confops = &slg51002_pctl->pconf_ops; + slg51002_pctl->pctrl.owner = THIS_MODULE; + slg51002_pctl->pctrl.name = dev_name(&pdev->dev); + + pinctrl_of_name = "slg51002_pinctrl"; + pdev->dev.of_node = of_find_node_by_name(pdev->dev.parent->of_node, + pinctrl_of_name); + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "Failed to find %s DT node\n", + pinctrl_of_name); + return -EINVAL; + } + + ret = devm_pinctrl_register_and_init(&pdev->dev, + &slg51002_pctl->pctrl, slg51002_pctl, &pctl); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register pinctrl: %d\n", ret); + return ret; + } + + ret = pinctrl_enable(pctl); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to enable pinctrl: %d\n", ret); + return ret; + } + + ret = devm_gpiochip_add_data(&pdev->dev, &slg51002_pctl->gc, + slg51002_pctl); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register gpio_chip: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, slg51002_pctl); + + return 0; +} + +static int slg51002_pinctrl_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct platform_device_id slg51002_pinctrl_id[] = { + { "slg51002_gpio", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(platform, slg51002_pinctrl_id); + +static struct platform_driver slg51002_pinctrl_driver = { + .driver = { + .name = "slg51002_gpio", + .owner = THIS_MODULE, + }, + .probe = slg51002_pinctrl_probe, + .remove = slg51002_pinctrl_remove, + .id_table = slg51002_pinctrl_id, +}; + +static int __init slg51002_pinctrl_init(void) +{ + return platform_driver_register(&slg51002_pinctrl_driver); +} +subsys_initcall(slg51002_pinctrl_init); + +static void __exit slg51002_pinctrl_exit(void) +{ + platform_driver_unregister(&slg51002_pinctrl_driver); +} +module_exit(slg51002_pinctrl_exit); + +MODULE_DESCRIPTION("SLG51002 pinctrl and GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile index ed2b2847be05..96501230ae29 100644 --- a/drivers/pinctrl/samsung/Makefile +++ b/drivers/pinctrl/samsung/Makefile @@ -7,5 +7,6 @@ pinctrl-samsung-core-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o pinctrl-samsung-core-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o pinctrl-samsung-core-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o pinctrl-samsung-core-$(CONFIG_PINCTRL_GS) += pinctrl-gs.o +pinctrl-samsung-core-$(CONFIG_PINCTRL_GS) += pinctrl-gs201.o pinctrl-samsung-core-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o pinctrl-samsung-core-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 40b54cff0b9a..3bf13856f4a5 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -425,7 +425,7 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) struct samsung_pinctrl_drv_data *d = bank->drvdata; u32 bit = 0; - bit = bank->eint_num + irqd->hwirq; + bit = bank->eint_num + irqd->hwirq + bank->wake_mask_bit_offset; if (!on) exynos_eint_wake_mask_bitmap[BIT_WORD(bit)] |= BIT_MASK(bit); else diff --git a/drivers/pinctrl/samsung/pinctrl-gs201.c b/drivers/pinctrl/samsung/pinctrl-gs201.c new file mode 100644 index 000000000000..fa9e30b7eaa7 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-gs201.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// GS specific support for Samsung pinctrl/gpiolib driver +// with eint support. +// +// Copyright (c) 2012 Samsung Electronics Co., Ltd. +// http://www.samsung.com +// Copyright (c) 2012 Linaro Ltd +// http://www.linaro.org +// Copyright (c) 2017 Krzysztof Kozlowski +// +// This file contains the GS201 specific information required by the +// the Samsung pinctrl/gpiolib driver. It also includes the implementation of +// external gpio and wakeup interrupt support. + +#include +#include +#include + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .fltcon_offset = fltcon_offs, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTW_GS201(types, pins, reg, id, offs, fltcon_offs, wake_bit_offset) \ + { \ + .type = &types, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .fltcon_offset = fltcon_offs, \ + .name = id, \ + .wake_mask_bit_offset = wake_bit_offset \ + } + +/* bank type for non-alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + * (CONPDN bit field: 2, PUDPDN bit field: 4) + */ +static struct samsung_pin_bank_type bank_type_6 = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* bank type for alive type + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4) + */ +static struct samsung_pin_bank_type bank_type_7 = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* pin banks of gs201 pin-controller (ALIVE) */ +static struct samsung_pin_bank_data gs201_pin_alive[] = { + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 8, 0x0, "gpa0", 0x00, 0x00, 0), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 7, 0x20, "gpa1", 0x04, 0x08, 0), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 4, 0x40, "gpa2", 0x08, 0x10, 0), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 4, 0x60, "gpa3", 0x0c, 0x14, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 4, 0x80, "gpa4", 0x10, 0x18, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 7, 0xa0, "gpa5", 0x14, 0x1c, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 8, 0xc0, "gpa9", 0x18, 0x24, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 2, 0xe0, "gpa10", 0x1c, 0x2c, 1), +}; + +/* pin banks of gs201 pin-controller (FAR_ALIVE) */ +static struct samsung_pin_bank_data gs201_pin_far_alive[] = { + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 8, 0x0, "gpa6", 0x00, 0x00, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 4, 0x20, "gpa7", 0x04, 0x08, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 8, 0x40, "gpa8", 0x08, 0x0c, 1), + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 2, 0x60, "gpa11", 0x0c, 0x14, 1), +}; + +/* pin banks of gs201 pin-controller (GSACORE) */ +static struct samsung_pin_bank_data gs201_pin_gsacore[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gps0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x20, "gps1", 0x04, 0x04), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 3, 0x40, "gps2", 0x08, 0x0c), +}; + +/* pin banks of gs201 pin-controller (GSACTRL) */ +static struct samsung_pin_bank_data gs201_pin_gsactrl[] = { + EXYNOS9_PIN_BANK_EINTW_GS201(bank_type_7, 6, 0x0, "gps3", 0x00, 0x00, 1), +}; + +/* pin banks of gs201 pin-controller (PERIC0) */ +static struct samsung_pin_bank_data gs201_pin_peric0[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x0, "gpp0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp1", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x40, "gpp2", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x60, "gpp3", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp4", 0x10, 0x14), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xa0, "gpp5", 0x14, 0x18), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xc0, "gpp6", 0x18, 0x1c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0xe0, "gpp7", 0x1c, 0x20), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x100, "gpp8", 0x20, 0x24), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x120, "gpp9", 0x24, 0x28), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x140, "gpp10", 0x28, 0x2c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x160, "gpp11", 0x2c, 0x30), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x180, "gpp12", 0x30, 0x34), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1a0, "gpp13", 0x34, 0x38), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x1c0, "gpp14", 0x38, 0x3c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x1e0, "gpp15", 0x3c, 0x40), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x200, "gpp16", 0x40, 0x44), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x220, "gpp17", 0x44, 0x48), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x240, "gpp18", 0x48, 0x4c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0x260, "gpp19", 0x4c, 0x50), +}; + +/* pin banks of gs201 pin-controller (PERIC1) */ +static struct samsung_pin_bank_data gs201_pin_peric1[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x0, "gpp20", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x20, "gpp21", 0x04, 0x08), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x40, "gpp22", 0x08, 0x0c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 8, 0x60, "gpp23", 0x0c, 0x10), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0x80, "gpp24", 0x10, 0x18), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xa0, "gpp25", 0x14, 0x1c), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 5, 0xc0, "gpp26", 0x18, 0x20), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 4, 0xe0, "gpp27", 0x1c, 0x28), +}; + +/* pin banks of gs201 pin-controller (HSI1) */ +static struct samsung_pin_bank_data gs201_pin_hsi1[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph0", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 7, 0x20, "gph1", 0x04, 0x08), +}; + +/* pin banks of gs201 pin-controller (HSI2) */ +static struct samsung_pin_bank_data gs201_pin_hsi2[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x0, "gph2", 0x00, 0x00), + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 6, 0x20, "gph4", 0x04, 0x08), +}; + +/* pin banks of gs201 pin-controller (HSI2UFS) */ +static struct samsung_pin_bank_data gs201_pin_hsi2ufs[] = { + EXYNOS9_PIN_BANK_EINTG(bank_type_6, 2, 0x0, "gph3", 0x00, 0x00), +}; + +static const struct samsung_pin_ctrl gs201_pin_ctrl[] __initconst = { + { + /* pin banks of gs201 pin-controller (ALIVE) */ + .pin_banks = gs201_pin_alive, + .nr_banks = ARRAY_SIZE(gs201_pin_alive), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (FAR_ALIVE) */ + .pin_banks = gs201_pin_far_alive, + .nr_banks = ARRAY_SIZE(gs201_pin_far_alive), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (GSACORE) */ + .pin_banks = gs201_pin_gsacore, + .nr_banks = ARRAY_SIZE(gs201_pin_gsacore), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin banks of gs201 pin-controller (GSACTRL) */ + .pin_banks = gs201_pin_gsactrl, + .nr_banks = ARRAY_SIZE(gs201_pin_gsactrl), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin banks of gs201 pin-controller (PERIC0) */ + .pin_banks = gs201_pin_peric0, + .nr_banks = ARRAY_SIZE(gs201_pin_peric0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (PERIC1) */ + .pin_banks = gs201_pin_peric1, + .nr_banks = ARRAY_SIZE(gs201_pin_peric1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (HSI1) */ + .pin_banks = gs201_pin_hsi1, + .nr_banks = ARRAY_SIZE(gs201_pin_hsi1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (HSI2) */ + .pin_banks = gs201_pin_hsi2, + .nr_banks = ARRAY_SIZE(gs201_pin_hsi2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin banks of gs201 pin-controller (HSI2UFS) */ + .pin_banks = gs201_pin_hsi2ufs, + .nr_banks = ARRAY_SIZE(gs201_pin_hsi2ufs), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data gs201_of_data __initconst = { + .ctrl = gs201_pin_ctrl, + .num_ctrl = ARRAY_SIZE(gs201_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 0d86d6c52cd2..0dd68072d948 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1156,6 +1156,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, bank->eint_offset = bdata->eint_offset; bank->eint_num = bdata->eint_num; bank->fltcon_offset = bdata->fltcon_offset; + bank->wake_mask_bit_offset = bdata->wake_mask_bit_offset; bank->name = bdata->name; spin_lock_init(&bank->slock); @@ -1447,6 +1448,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos7_of_data }, { .compatible = "google,gs101-pinctrl", .data = &gs101_of_data }, + { .compatible = "google,gs201-pinctrl", + .data = &gs201_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index c9631ca7e285..c51b4462cd3f 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -115,6 +115,7 @@ struct samsung_pin_bank_type { * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. * @fltcon_offset: SoC-specific EINT filter control register offset of bank. + * @wake_mask_bit_offset: SoC-specific wake mask bit offset of bank. * @name: name to be prefixed for each pin in this pin bank. */ struct samsung_pin_bank_data { @@ -128,6 +129,7 @@ struct samsung_pin_bank_data { u32 eint_offset; u32 eint_num; u32 fltcon_offset; + u8 wake_mask_bit_offset; const char *name; }; @@ -143,6 +145,7 @@ struct samsung_pin_bank_data { * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. * @fltcon_offset: SoC-specific EINT filter control register offset of bank. + * @wake_mask_bit_offset: SoC-specific offset of wake-mask bits of bank. * @name: name to be prefixed for each pin in this pin bank. * @pin_base: starting pin number of the bank. * @soc_priv: per-bank private data for SoC-specific code. @@ -167,6 +170,7 @@ struct samsung_pin_bank { u32 eint_offset; u32 eint_num; u32 fltcon_offset; + u8 wake_mask_bit_offset; unsigned long eint_disabled; const char *name; @@ -347,6 +351,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data gs101_of_data; +extern const struct samsung_pinctrl_of_match_data gs201_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 71c3be889189..ea23ddb80bca 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -410,7 +410,7 @@ config PWM_ROCKCHIP config PWM_SAMSUNG tristate "Samsung PWM support" - depends on PLAT_SAMSUNG || ARCH_EXYNOS || SOC_GS101 + depends on PLAT_SAMSUNG || ARCH_EXYNOS || SOC_GS101 || SOC_GS201 help Generic PWM framework driver for Samsung. diff --git a/drivers/pwm/pwm-samsung.c b/drivers/pwm/pwm-samsung.c index 33b39e11c561..71d7f4170334 100644 --- a/drivers/pwm/pwm-samsung.c +++ b/drivers/pwm/pwm-samsung.c @@ -954,8 +954,6 @@ static int pwm_samsung_resume(struct device *dev) { struct samsung_pwm_chip *chip = dev_get_drvdata(dev); - pwm_pin_ctrl(dev, 1); - pwm_samsung_clk_enable(chip); /* Restore pwm register setting */ @@ -964,6 +962,8 @@ static int pwm_samsung_resume(struct device *dev) if (!chip->enable_cnt) pwm_samsung_clk_disable(chip); + pwm_pin_ctrl(dev, 1); + return 0; } #endif diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 849d95f9528e..d8b990ac187c 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -981,7 +981,6 @@ config REGULATOR_S2MPS11 config DRV_SAMSUNG_PMIC tristate "Samsung PMIC sysfs system" - depends on MFD_S2MPG10 || MFD_S2MPG11 help This driver supports a Samsung PMIC sysfs. The sysfs directory made by this config includes directories of @@ -1028,6 +1027,22 @@ config POWERMETER_S2MPG11 The sysfs files in the sysfs directory created by the config DRV_SAMSUNG_PMIC is are made by this driver for debugging. +config REGULATOR_S2MPG12 + tristate "Samsung S2MPG12 voltage regulator" + depends on MFD_S2MPG12 + help + This driver supports a Samsung S2MPG12 voltage output regulator + via I2C bus. S2MPG12 is comprised of high efficient Buck converters + including Dual-Phase Buck converter, Buck-Boost converter, various LDOs. + +config REGULATOR_S2MPG13 + tristate "Samsung S2MPG13 voltage regulator" + depends on MFD_S2MPG13 + help + This driver supports a Samsung S2MPG13 voltage output regulator + via I2C bus. S2MPG13 is comprised of high efficient Buck converters + including Dual-Phase Buck converter, Buck-Boost converter, various LDOs. + config REGULATOR_S5M8767 tristate "Samsung S5M8767A voltage regulator" depends on MFD_SEC_CORE || COMPILE_TEST @@ -1063,6 +1078,15 @@ config REGULATOR_SLG51000 The SLG51000 is seven compact and customizable low dropout regulators. +config REGULATOR_SLG51002 + tristate "Dialog Semiconductor SLG51002 regulators" + depends on I2C + select REGMAP_I2C + help + Say y here to support for the Dialog Semiconductor SLG51002. + The SLG51002 is eight compact and customizable low dropout + regulators. + config REGULATOR_STM32_BOOSTER tristate "STMicroelectronics STM32 BOOSTER" depends on ARCH_STM32 || COMPILE_TEST diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 99412586fa04..ae1e567441c7 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -124,10 +124,13 @@ obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o obj-$(CONFIG_DRV_SAMSUNG_PMIC) += pmic_class.o obj-$(CONFIG_REGULATOR_S2MPG10) += s2mpg10-regulator.o s2mpg10-powermeter.o obj-$(CONFIG_REGULATOR_S2MPG11) += s2mpg11-regulator.o s2mpg11-powermeter.o +obj-$(CONFIG_REGULATOR_S2MPG12) += s2mpg12-regulator.o s2mpg12-powermeter.o +obj-$(CONFIG_REGULATOR_S2MPG13) += s2mpg13-regulator.o s2mpg13-powermeter.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_REGULATOR_SC2731) += sc2731-regulator.o obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o obj-$(CONFIG_REGULATOR_SLG51000) += slg51000-regulator.o +obj-$(CONFIG_REGULATOR_SLG51002) += slg51002-regulator.o obj-$(CONFIG_REGULATOR_STM32_BOOSTER) += stm32-booster.o obj-$(CONFIG_REGULATOR_STM32_VREFBUF) += stm32-vrefbuf.o obj-$(CONFIG_REGULATOR_STM32_PWR) += stm32-pwr.o diff --git a/drivers/regulator/s2mpg10-powermeter.c b/drivers/regulator/s2mpg10-powermeter.c index 8aedccd10684..a14046ecfabb 100644 --- a/drivers/regulator/s2mpg10-powermeter.c +++ b/drivers/regulator/s2mpg10-powermeter.c @@ -29,13 +29,6 @@ #include #include -static void s2mpg10_meter_set_acc_mode(struct s2mpg10_meter *s2mpg10, - s2mpg1x_meter_mode mode); -static void s2mpg10_meter_read_acc_data_reg(struct s2mpg10_meter *s2mpg10, - u64 *data); -static void s2mpg10_meter_read_acc_count(struct s2mpg10_meter *s2mpg10, - u32 *count); - #if IS_ENABLED(CONFIG_ODPM) static struct mfd_cell s2mpg10_meter_devs[] = { { @@ -44,35 +37,7 @@ static struct mfd_cell s2mpg10_meter_devs[] = { }; #endif -/** - * Load measurement into registers and read measurement from the registers - * - * Note: data must be an array with length S2MPG1X_METER_CHANNEL_MAX - */ -int s2mpg10_meter_load_measurement(struct s2mpg10_meter *s2mpg10, - s2mpg1x_meter_mode mode, u64 *data, - u32 *count, u64 *timestamp_capture) -{ - mutex_lock(&s2mpg10->meter_lock); - - s2mpg10_meter_set_acc_mode(s2mpg10, mode); - - s2mpg1x_meter_set_async_blocking(ID_S2MPG10, s2mpg10->i2c, - timestamp_capture); - - if (data) - s2mpg10_meter_read_acc_data_reg(s2mpg10, data); - - if (count) - s2mpg10_meter_read_acc_count(s2mpg10, count); - - mutex_unlock(&s2mpg10->meter_lock); - - return 0; -} -EXPORT_SYMBOL_GPL(s2mpg10_meter_load_measurement); - -static u64 muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) +u32 s2mpg10_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) { switch (m) { case MUXSEL_NONE: @@ -138,6 +103,7 @@ static u64 muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) return INVALID_RESOLUTION; } } +EXPORT_SYMBOL_GPL(s2mpg10_muxsel_to_current_resolution); u32 s2mpg10_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m) { @@ -327,78 +293,6 @@ int s2mpg10_meter_set_muxsel(struct s2mpg10_meter *s2mpg10, int channel, } EXPORT_SYMBOL_GPL(s2mpg10_meter_set_muxsel); -static void s2mpg10_meter_set_lpf_mode(struct s2mpg10_meter *s2mpg10, - s2mpg1x_meter_mode mode) -{ - switch (mode) { - case S2MPG1X_METER_POWER: - s2mpg10_write_reg(s2mpg10->i2c, S2MPG10_METER_CTRL4, 0x00); - break; - case S2MPG1X_METER_CURRENT: - s2mpg10_write_reg(s2mpg10->i2c, S2MPG10_METER_CTRL4, 0xFF); - break; - } -} - -void s2mpg10_meter_read_lpf_data_reg(struct s2mpg10_meter *s2mpg10, u32 *data) -{ - int i; - u8 buf[S2MPG1X_METER_LPF_BUF]; - u8 reg = S2MPG10_METER_LPF_DATA_CH0_1; /* first lpf data register */ - - for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { - s2mpg10_bulk_read(s2mpg10->i2c, reg, S2MPG1X_METER_LPF_BUF, - buf); - data[i] = buf[0] + (buf[1] << 8) + ((buf[2] & 0x1F) << 16); - reg += S2MPG1X_METER_LPF_BUF; - } -} -EXPORT_SYMBOL_GPL(s2mpg10_meter_read_lpf_data_reg); - -static void s2mpg10_meter_set_acc_mode(struct s2mpg10_meter *s2mpg10, - s2mpg1x_meter_mode mode) -{ - switch (mode) { - case S2MPG1X_METER_POWER: - s2mpg10_write_reg(s2mpg10->i2c, S2MPG10_METER_CTRL3, 0x00); - break; - case S2MPG1X_METER_CURRENT: - s2mpg10_write_reg(s2mpg10->i2c, S2MPG10_METER_CTRL3, 0xFF); - break; - } -} - -static void s2mpg10_meter_read_acc_data_reg(struct s2mpg10_meter *s2mpg10, - u64 *data) -{ - int i; - u8 buf[S2MPG1X_METER_ACC_BUF]; - u8 reg = S2MPG10_METER_ACC_DATA_CH0_1; /* first acc data register */ - - for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { - s2mpg10_bulk_read(s2mpg10->i2c, reg, S2MPG1X_METER_ACC_BUF, - buf); - - /* 41 bits of data */ - data[i] = ((u64)buf[0] << 0) | ((u64)buf[1] << 8) | - ((u64)buf[2] << 16) | ((u64)buf[3] << 24) | - ((u64)buf[4] << 32) | (((u64)buf[5] & 0x1) << 8); - - reg += S2MPG1X_METER_ACC_BUF; - } -} - -static void s2mpg10_meter_read_acc_count(struct s2mpg10_meter *s2mpg10, - u32 *count) -{ - u8 data[S2MPG1X_METER_COUNT_BUF]; /* ACC_COUNT is 20-bit data */ - - s2mpg10_bulk_read(s2mpg10->i2c, S2MPG10_METER_ACC_COUNT_1, - S2MPG1X_METER_COUNT_BUF, data); - - *count = (data[0] << 0) | (data[1] << 8) | ((data[2] & 0x0F) << 16); -} - #if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) static ssize_t s2mpg10_muxsel_table_show(struct device *dev, struct device_attribute *attr, @@ -498,8 +392,10 @@ static ssize_t s2mpg10_lpf_current_show(struct device *dev, mutex_lock(&s2mpg10->meter_lock); - s2mpg10_meter_set_lpf_mode(s2mpg10, S2MPG1X_METER_CURRENT); - s2mpg10_meter_read_lpf_data_reg(s2mpg10, s2mpg10->lpf_data); + s2mpg1x_meter_set_lpf_mode(ID_S2MPG10, s2mpg10->i2c, + S2MPG1X_METER_CURRENT); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG10, s2mpg10->i2c, + s2mpg10->lpf_data); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg10->chg_mux_sel[i]; @@ -507,7 +403,7 @@ static ssize_t s2mpg10_lpf_current_show(struct device *dev, count += s2mpg1x_meter_format_channel(buf, count, i, muxsel_to_str(muxsel), "(mA)", s2mpg10->lpf_data[i], - muxsel_to_current_resolution(muxsel), 1); + s2mpg10_muxsel_to_current_resolution(muxsel), 1); } mutex_unlock(&s2mpg10->meter_lock); return count; @@ -522,8 +418,10 @@ static ssize_t s2mpg10_lpf_power_show(struct device *dev, mutex_lock(&s2mpg10->meter_lock); - s2mpg10_meter_set_lpf_mode(s2mpg10, S2MPG1X_METER_POWER); - s2mpg10_meter_read_lpf_data_reg(s2mpg10, s2mpg10->lpf_data); + s2mpg1x_meter_set_lpf_mode(ID_S2MPG10, s2mpg10->i2c, + S2MPG1X_METER_POWER); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG10, s2mpg10->i2c, + s2mpg10->lpf_data); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg10->chg_mux_sel[i]; @@ -548,15 +446,18 @@ static ssize_t s2mpg10_acc_current_show(struct device *dev, u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; u32 acc_count; - s2mpg10_meter_load_measurement(s2mpg10, S2MPG1X_METER_CURRENT, acc_data, - &acc_count, NULL); + s2mpg1x_meter_measure_acc(ID_S2MPG10, s2mpg10->i2c, + &s2mpg10->meter_lock, + S2MPG1X_METER_CURRENT, acc_data, + &acc_count, NULL, INT_125HZ); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg10->chg_mux_sel[i]; count += s2mpg1x_meter_format_channel(buf, count, i, muxsel_to_str(muxsel), "(mA)", - acc_data[i], muxsel_to_current_resolution(muxsel), + acc_data[i], + s2mpg10_muxsel_to_current_resolution(muxsel), acc_count); } @@ -573,8 +474,10 @@ static ssize_t s2mpg10_acc_power_show(struct device *dev, u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; u32 acc_count; - s2mpg10_meter_load_measurement(s2mpg10, S2MPG1X_METER_POWER, acc_data, - &acc_count, NULL); + s2mpg1x_meter_measure_acc(ID_S2MPG10, s2mpg10->i2c, + &s2mpg10->meter_lock, + S2MPG1X_METER_POWER, acc_data, + &acc_count, NULL, INT_125HZ); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg10->chg_mux_sel[i]; @@ -704,7 +607,7 @@ static int s2mpg10_meter_probe(struct platform_device *pdev) /* initial setting */ /* set BUCK1M ~ BUCK8m muxsel from CH0 to CH7 */ /* any necessary settings can be added */ - s2mpg1x_meter_set_int_samp_rate(ID_S2MPG10, s2mpg10->i2c, INT_500HZ); + s2mpg1x_meter_set_int_samp_rate(ID_S2MPG10, s2mpg10->i2c, INT_125HZ); s2mpg10_meter_set_muxsel(s2mpg10, 0, BUCK1); s2mpg10_meter_set_muxsel(s2mpg10, 1, BUCK2); @@ -719,8 +622,6 @@ static int s2mpg10_meter_probe(struct platform_device *pdev) s2mpg10_ext_meter_onoff(s2mpg10, false); #else - s2mpg10_meter_set_lpf_mode(s2mpg10, S2MPG1X_METER_POWER); - ret = mfd_add_devices(s2mpg10->dev, -1, s2mpg10_meter_devs, ARRAY_SIZE(s2mpg10_meter_devs), NULL, 0, NULL); if (ret < 0) { diff --git a/drivers/regulator/s2mpg11-powermeter.c b/drivers/regulator/s2mpg11-powermeter.c index b34821e5b11d..67086c47f533 100644 --- a/drivers/regulator/s2mpg11-powermeter.c +++ b/drivers/regulator/s2mpg11-powermeter.c @@ -29,13 +29,6 @@ #include #include -static void s2mpg11_meter_set_acc_mode(struct s2mpg11_meter *s2mpg11, - s2mpg1x_meter_mode mode); -static void s2mpg11_meter_read_acc_data_reg(struct s2mpg11_meter *s2mpg11, - u64 *data); -static void s2mpg11_meter_read_acc_count(struct s2mpg11_meter *s2mpg11, - u32 *count); - #if IS_ENABLED(CONFIG_ODPM) static struct mfd_cell s2mpg11_meter_devs[] = { { @@ -44,35 +37,7 @@ static struct mfd_cell s2mpg11_meter_devs[] = { }; #endif -/** - * Load measurement into registers and read measurement from the registers - * - * Note: data must be an array with length S2MPG1X_METER_CHANNEL_MAX - */ -int s2mpg11_meter_load_measurement(struct s2mpg11_meter *s2mpg11, - s2mpg1x_meter_mode mode, u64 *data, - u32 *count, u64 *timestamp_capture) -{ - mutex_lock(&s2mpg11->meter_lock); - - s2mpg11_meter_set_acc_mode(s2mpg11, mode); - - s2mpg1x_meter_set_async_blocking(ID_S2MPG11, s2mpg11->i2c, - timestamp_capture); - - if (data) - s2mpg11_meter_read_acc_data_reg(s2mpg11, data); - - if (count) - s2mpg11_meter_read_acc_count(s2mpg11, count); - - mutex_unlock(&s2mpg11->meter_lock); - - return 0; -} -EXPORT_SYMBOL_GPL(s2mpg11_meter_load_measurement); - -static u64 muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) +u32 s2mpg11_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) { switch (m) { case MUXSEL_NONE: @@ -125,6 +90,7 @@ static u64 muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) return INVALID_RESOLUTION; } } +EXPORT_SYMBOL_GPL(s2mpg11_muxsel_to_current_resolution); u32 s2mpg11_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m) { @@ -290,78 +256,6 @@ int s2mpg11_meter_set_muxsel(struct s2mpg11_meter *s2mpg11, int channel, } EXPORT_SYMBOL_GPL(s2mpg11_meter_set_muxsel); -static void s2mpg11_meter_set_lpf_mode(struct s2mpg11_meter *s2mpg11, - s2mpg1x_meter_mode mode) -{ - switch (mode) { - case S2MPG1X_METER_POWER: - s2mpg11_write_reg(s2mpg11->i2c, S2MPG11_METER_CTRL5, 0x00); - break; - case S2MPG1X_METER_CURRENT: - s2mpg11_write_reg(s2mpg11->i2c, S2MPG11_METER_CTRL5, 0xFF); - break; - } -} - -void s2mpg11_meter_read_lpf_data_reg(struct s2mpg11_meter *s2mpg11, u32 *data) -{ - int i; - u8 buf[S2MPG1X_METER_LPF_BUF]; - u8 reg = S2MPG11_METER_LPF_DATA_CH0_1; /* first lpf data register */ - - for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { - s2mpg11_bulk_read(s2mpg11->i2c, reg, S2MPG1X_METER_LPF_BUF, - buf); - data[i] = buf[0] + (buf[1] << 8) + ((buf[2] & 0x1F) << 16); - reg += S2MPG1X_METER_LPF_BUF; - } -} -EXPORT_SYMBOL_GPL(s2mpg11_meter_read_lpf_data_reg); - -static void s2mpg11_meter_set_acc_mode(struct s2mpg11_meter *s2mpg11, - s2mpg1x_meter_mode mode) -{ - switch (mode) { - case S2MPG1X_METER_POWER: - s2mpg11_write_reg(s2mpg11->i2c, S2MPG11_METER_CTRL4, 0x00); - break; - case S2MPG1X_METER_CURRENT: - s2mpg11_write_reg(s2mpg11->i2c, S2MPG11_METER_CTRL4, 0xFF); - break; - } -} - -static void s2mpg11_meter_read_acc_data_reg(struct s2mpg11_meter *s2mpg11, - u64 *data) -{ - int i; - u8 buf[S2MPG1X_METER_ACC_BUF]; - u8 reg = S2MPG11_METER_ACC_DATA_CH0_1; /* first acc data register */ - - for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { - s2mpg11_bulk_read(s2mpg11->i2c, reg, S2MPG1X_METER_ACC_BUF, - buf); - - /* 41 bits of data */ - data[i] = ((u64)buf[0] << 0) | ((u64)buf[1] << 8) | - ((u64)buf[2] << 16) | ((u64)buf[3] << 24) | - ((u64)buf[4] << 32) | (((u64)buf[5] & 0x1) << 8); - - reg += S2MPG1X_METER_ACC_BUF; - } -} - -static void s2mpg11_meter_read_acc_count(struct s2mpg11_meter *s2mpg11, - u32 *count) -{ - u8 data[S2MPG1X_METER_COUNT_BUF]; /* ACC_COUNT is 20-bit data */ - - s2mpg11_bulk_read(s2mpg11->i2c, S2MPG11_METER_ACC_COUNT_1, - S2MPG1X_METER_COUNT_BUF, data); - - *count = data[0] | (data[1] << 8) | ((data[2] & 0x0F) << 16); -} - #if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) static ssize_t s2mpg11_muxsel_table_show(struct device *dev, struct device_attribute *attr, @@ -463,8 +357,10 @@ static ssize_t s2mpg11_lpf_current_show(struct device *dev, mutex_lock(&s2mpg11->meter_lock); - s2mpg11_meter_set_lpf_mode(s2mpg11, S2MPG1X_METER_CURRENT); - s2mpg11_meter_read_lpf_data_reg(s2mpg11, s2mpg11->lpf_data); + s2mpg1x_meter_set_lpf_mode(ID_S2MPG11, s2mpg11->i2c, + S2MPG1X_METER_CURRENT); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG11, s2mpg11->i2c, + s2mpg11->lpf_data); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg11->chg_mux_sel[i]; @@ -473,7 +369,7 @@ static ssize_t s2mpg11_lpf_current_show(struct device *dev, muxsel_to_str(muxsel), "(mA)", s2mpg11->lpf_data[i], - muxsel_to_current_resolution(muxsel), + s2mpg11_muxsel_to_current_resolution(muxsel), 1); } mutex_unlock(&s2mpg11->meter_lock); @@ -489,8 +385,10 @@ static ssize_t s2mpg11_lpf_power_show(struct device *dev, mutex_lock(&s2mpg11->meter_lock); - s2mpg11_meter_set_lpf_mode(s2mpg11, S2MPG1X_METER_POWER); - s2mpg11_meter_read_lpf_data_reg(s2mpg11, s2mpg11->lpf_data); + s2mpg1x_meter_set_lpf_mode(ID_S2MPG11, s2mpg11->i2c, + S2MPG1X_METER_POWER); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG11, s2mpg11->i2c, + s2mpg11->lpf_data); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg11->chg_mux_sel[i]; @@ -515,15 +413,18 @@ static ssize_t s2mpg11_acc_current_show(struct device *dev, u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; u32 acc_count; - s2mpg11_meter_load_measurement(s2mpg11, S2MPG1X_METER_CURRENT, acc_data, - &acc_count, NULL); + s2mpg1x_meter_measure_acc(ID_S2MPG11, s2mpg11->i2c, + &s2mpg11->meter_lock, + S2MPG1X_METER_CURRENT, acc_data, + &acc_count, NULL, INT_125HZ); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg11->chg_mux_sel[i]; count += s2mpg1x_meter_format_channel(buf, count, i, muxsel_to_str(muxsel), "(mA)", - acc_data[i], muxsel_to_current_resolution(muxsel), + acc_data[i], + s2mpg11_muxsel_to_current_resolution(muxsel), acc_count); } @@ -540,8 +441,10 @@ static ssize_t s2mpg11_acc_power_show(struct device *dev, u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; u32 acc_count; - s2mpg11_meter_load_measurement(s2mpg11, S2MPG1X_METER_POWER, acc_data, - &acc_count, NULL); + s2mpg1x_meter_measure_acc(ID_S2MPG11, s2mpg11->i2c, + &s2mpg11->meter_lock, + S2MPG1X_METER_POWER, acc_data, + &acc_count, NULL, INT_125HZ); for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { s2mpg1x_meter_muxsel muxsel = s2mpg11->chg_mux_sel[i]; @@ -646,7 +549,7 @@ static int s2mpg11_meter_probe(struct platform_device *pdev) /* initial setting */ /* set BUCK1S ~ BUCK8S muxsel from CH0 to CH7 */ /* any necessary settings can be added */ - s2mpg1x_meter_set_int_samp_rate(ID_S2MPG11, s2mpg11->i2c, INT_500HZ); + s2mpg1x_meter_set_int_samp_rate(ID_S2MPG11, s2mpg11->i2c, INT_125HZ); s2mpg11_meter_set_muxsel(s2mpg11, 0, BUCK1); s2mpg11_meter_set_muxsel(s2mpg11, 1, BUCK2); @@ -661,8 +564,6 @@ static int s2mpg11_meter_probe(struct platform_device *pdev) s2mpg11_ext_meter_onoff(s2mpg11, false); #else - s2mpg11_meter_set_lpf_mode(s2mpg11, S2MPG1X_METER_POWER); - ret = mfd_add_devices(s2mpg11->dev, -1, s2mpg11_meter_devs, ARRAY_SIZE(s2mpg11_meter_devs), NULL, 0, NULL); if (ret < 0) { diff --git a/drivers/regulator/s2mpg12-powermeter.c b/drivers/regulator/s2mpg12-powermeter.c new file mode 100644 index 000000000000..563f6386eacf --- /dev/null +++ b/drivers/regulator/s2mpg12-powermeter.c @@ -0,0 +1,654 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg12-powermeter.c + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include <../drivers/pinctrl/samsung/pinctrl-samsung.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_ODPM) +static struct mfd_cell s2mpg12_meter_devs[] = { + { + .name = "s2mpg12-odpm", + }, +}; +#endif + +u32 s2mpg12_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) +{ + switch (m) { + case BUCK1: + case BUCK4: + case BUCK6: + case BUCK7: + case BUCK8: + case BUCK9: + return CMS_BUCK_CURRENT; + case BUCK3: + return CMD_BUCK_CURRENT; + case BUCK2: + case BUCK5: + case BUCK10: + return CMT_BUCK_CURRENT; + case LDO5: + return DVS_NLDO_CURRENT_150mA; + case LDO4: + case LDO9: + case LDO10: + case LDO14: + case LDO18: + case LDO20: + case LDO23: + case LDO25: + case LDO27: + return PLDO_CURRENT_150mA; + case LDO1: + case LDO3: + case LDO8: + return NLDO_CURRENT_300mA; + case LDO21: + case LDO26: + return PLDO_CURRENT_300mA; + case LDO6: + case LDO28: + return NLDO_CURRENT_450mA; + case LDO24: + return PLDO_CURRENT_600mA; + case LDO7: + case LDO11: + case LDO12: + case LDO13: + case LDO15: + case LDO17: + case LDO19: + case LDO22: + return DVS_NLDO_CURRENT_800mA; + case LDO16: + return NLDO_CURRENT_800mA; + case LDO2: + return PLDO_CURRENT_800mA; + default: + pr_err("%s: wrong muxsel\n", __func__); + return INVALID_RESOLUTION; + } +} +EXPORT_SYMBOL_GPL(s2mpg12_muxsel_to_current_resolution); + +u32 s2mpg12_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m) +{ + switch (m) { + case BUCK1: + case BUCK4: + case BUCK6: + case BUCK7: + case BUCK8: + case BUCK9: + return CMS_BUCK_POWER; + case BUCK3: + return CMD_BUCK_POWER; + case BUCK2: + case BUCK5: + case BUCK10: + return CMT_BUCK_POWER; + case LDO5: + return DVS_NLDO_POWER_150mA; + case LDO4: + case LDO9: + case LDO10: + case LDO14: + case LDO18: + case LDO20: + case LDO23: + case LDO25: + case LDO27: + return PLDO_POWER_150mA; + case LDO1: + case LDO3: + case LDO8: + return NLDO_POWER_300mA; + case LDO21: + case LDO26: + return PLDO_POWER_300mA; + case LDO6: + case LDO28: + return NLDO_POWER_450mA; + case LDO24: + return PLDO_POWER_600mA; + case LDO7: + case LDO11: + case LDO12: + case LDO13: + case LDO15: + case LDO17: + case LDO19: + case LDO22: + return DVS_NLDO_POWER_800mA; + case LDO16: + return NLDO_POWER_800mA; + case LDO2: + return PLDO_POWER_800mA; + default: + pr_err("%s: wrong muxsel\n", __func__); + return INVALID_RESOLUTION; + } +} +EXPORT_SYMBOL_GPL(s2mpg12_muxsel_to_power_resolution); + +static const char *muxsel_to_str(s2mpg1x_meter_muxsel m) +{ + char *ret; + + switch (m) { + ENUM_STR(BUCK1, "M", ret); + ENUM_STR(BUCK2, "M", ret); + ENUM_STR(BUCK3, "M", ret); + ENUM_STR(BUCK4, "M", ret); + ENUM_STR(BUCK5, "M", ret); + ENUM_STR(BUCK6, "M", ret); + ENUM_STR(BUCK7, "M", ret); + ENUM_STR(BUCK8, "M", ret); + ENUM_STR(BUCK9, "M", ret); + ENUM_STR(BUCK10, "M", ret); + ENUM_STR(VSEN_V1, "", ret); + ENUM_STR(VSEN_V2, "", ret); + ENUM_STR(VSEN_V3, "", ret); + ENUM_STR(LDO1, "M", ret); + ENUM_STR(LDO2, "M", ret); + ENUM_STR(LDO3, "M", ret); + ENUM_STR(LDO4, "M", ret); + ENUM_STR(LDO5, "M", ret); + ENUM_STR(LDO6, "M", ret); + ENUM_STR(LDO7, "M", ret); + ENUM_STR(LDO8, "M", ret); + ENUM_STR(LDO9, "M", ret); + ENUM_STR(LDO10, "M", ret); + ENUM_STR(LDO11, "M", ret); + ENUM_STR(LDO12, "M", ret); + ENUM_STR(LDO13, "M", ret); + ENUM_STR(LDO14, "M", ret); + ENUM_STR(LDO15, "M", ret); + ENUM_STR(LDO16, "M", ret); + ENUM_STR(LDO17, "M", ret); + ENUM_STR(LDO18, "M", ret); + ENUM_STR(LDO19, "M", ret); + ENUM_STR(LDO20, "M", ret); + ENUM_STR(LDO21, "M", ret); + ENUM_STR(LDO22, "M", ret); + ENUM_STR(LDO23, "M", ret); + ENUM_STR(LDO24, "M", ret); + ENUM_STR(LDO25, "M", ret); + ENUM_STR(LDO26, "M", ret); + ENUM_STR(LDO27, "M", ret); + ENUM_STR(LDO28, "M", ret); + ENUM_STR(VSEN_C1, "", ret); + ENUM_STR(VSEN_C2, "", ret); + ENUM_STR(VSEN_C3, "", ret); + default: + return "invalid"; + } + return ret; +} + +int s2mpg12_meter_onoff(struct s2mpg12_meter *s2mpg12, bool onoff) +{ + if (onoff) { + dev_info(s2mpg12->dev, "s2mpg12 meter on\n"); + return s2mpg12_update_reg(s2mpg12->i2c, S2MPG12_METER_CTRL1, + METER_EN_MASK, METER_EN_MASK); + } + dev_info(s2mpg12->dev, "s2mpg12 meter off\n"); + return s2mpg12_update_reg(s2mpg12->i2c, S2MPG12_METER_CTRL1, 0, + METER_EN_MASK); +} +EXPORT_SYMBOL_GPL(s2mpg12_meter_onoff); + +int s2mpg12_ext_meter_onoff(struct s2mpg12_meter *s2mpg12, bool onoff) +{ + if (onoff) { + dev_info(s2mpg12->dev, "s2mpg12 external meter on\n"); + return s2mpg12_update_reg(s2mpg12->i2c, S2MPG12_METER_CTRL1, + EXT_METER_EN_MASK, EXT_METER_EN_MASK); + } + dev_info(s2mpg12->dev, "s2mpg12 external meter off\n"); + return s2mpg12_update_reg(s2mpg12->i2c, S2MPG12_METER_CTRL1, 0, + EXT_METER_EN_MASK); +} +EXPORT_SYMBOL_GPL(s2mpg12_ext_meter_onoff); + +int s2mpg12_meter_set_muxsel(struct s2mpg12_meter *s2mpg12, int channel, + s2mpg1x_meter_muxsel m) +{ + int reg = S2MPG12_METER_MUXSEL0; + int ret = -EPERM; + + if (channel < 0 || channel >= S2MPG1X_METER_CHANNEL_MAX) { + dev_err(s2mpg12->dev, "invalid channel number\n"); + return ret; + } + + dev_info(s2mpg12->dev, "CH%d, %s\n", channel, muxsel_to_str(m)); + + reg += channel; + + mutex_lock(&s2mpg12->meter_lock); + ret = s2mpg12_update_reg(s2mpg12->i2c, reg, m, MUXSEL_MASK); + + s2mpg12->chg_mux_sel[channel] = m; + mutex_unlock(&s2mpg12->meter_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg12_meter_set_muxsel); + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) +static ssize_t s2mpg12_muxsel_table_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int muxsel_cnt = 0; + int muxsel = BUCK1; + size_t count = 0; + + while (muxsel <= VSEN_C3) { + count += scnprintf(buf + count, PAGE_SIZE - count, + "%s : 0x%x , ", muxsel_to_str(muxsel), muxsel); + if (muxsel == VSEN_C3) + break; + + if (muxsel == BUCK10) + muxsel = VSEN_V1; + else if (muxsel == VSEN_V3) + muxsel = LDO1; + else if (muxsel == LDO28) + muxsel = VSEN_C1; + else + muxsel++; + + muxsel_cnt++; + if (!(muxsel_cnt % 8)) + count += scnprintf(buf + count, + PAGE_SIZE - count, "\n"); + } + + return count; +} + +static ssize_t s2mpg12_channel_muxsel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int channel, muxsel; + int ret; + + if (!buf) { + dev_err(s2mpg12->dev, "empty buffer\n"); + return -EINVAL; + } + + ret = sscanf(buf, "%d %x", &channel, &muxsel); + if (ret != 2) { + dev_err(s2mpg12->dev, "input error\n"); + return -EINVAL; + } + + if (channel < 0 || channel >= S2MPG1X_METER_CHANNEL_MAX) { + dev_err(s2mpg12->dev, "wrong channel %d\n", channel); + return -EINVAL; + } + + if ((muxsel >= BUCK1 && muxsel <= BUCK10) || + (muxsel >= VSEN_V1 && muxsel <= VSEN_V3) || + (muxsel >= LDO1 && muxsel <= LDO28) || + (muxsel >= VSEN_C1 && muxsel <= VSEN_C3)) { + s2mpg12_meter_set_muxsel(s2mpg12, channel, muxsel); + } else { + dev_err(s2mpg12->dev, "wrong muxsel 0x%x\n", muxsel); + return -EINVAL; + } + + return size; +} + +static ssize_t s2mpg12_channel_muxsel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int i; + size_t count = 0; + + mutex_lock(&s2mpg12->meter_lock); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + count += scnprintf(buf + count, PAGE_SIZE - count, "CH%d[%s], ", + i, muxsel_to_str(s2mpg12->chg_mux_sel[i])); + } + + mutex_unlock(&s2mpg12->meter_lock); + return count; +} + +static ssize_t s2mpg12_lpf_current_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + mutex_lock(&s2mpg12->meter_lock); + + s2mpg1x_meter_set_lpf_mode(ID_S2MPG12, s2mpg12->i2c, + S2MPG1X_METER_CURRENT); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG12, s2mpg12->i2c, + s2mpg12->lpf_data); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg12->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mA)", + s2mpg12->lpf_data[i], + s2mpg12_muxsel_to_current_resolution(muxsel), 1); + } + mutex_unlock(&s2mpg12->meter_lock); + return count; +} + +static ssize_t s2mpg12_lpf_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + mutex_lock(&s2mpg12->meter_lock); + + s2mpg1x_meter_set_lpf_mode(ID_S2MPG12, s2mpg12->i2c, + S2MPG1X_METER_POWER); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG12, s2mpg12->i2c, + s2mpg12->lpf_data); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg12->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mW)", + s2mpg12->lpf_data[i], + s2mpg12_muxsel_to_power_resolution(muxsel), 1); + } + mutex_unlock(&s2mpg12->meter_lock); + return count; +} + +static ssize_t s2mpg12_acc_current_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; + u32 acc_count; + + s2mpg1x_meter_measure_acc(ID_S2MPG12, s2mpg12->i2c, + &s2mpg12->meter_lock, + S2MPG1X_METER_CURRENT, acc_data, + &acc_count, NULL, INT_125HZ); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg12->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mA)", + acc_data[i], + s2mpg12_muxsel_to_current_resolution(muxsel), + acc_count); + } + + return count; +} + +static ssize_t s2mpg12_acc_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg12_meter *s2mpg12 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; + u32 acc_count; + + s2mpg1x_meter_measure_acc(ID_S2MPG12, s2mpg12->i2c, + &s2mpg12->meter_lock, + S2MPG1X_METER_POWER, acc_data, + &acc_count, NULL, INT_125HZ); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg12->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mW)", + acc_data[i], s2mpg12_muxsel_to_power_resolution(muxsel), + acc_count); + } + + return count; +} + +static DEVICE_ATTR_RO(s2mpg12_muxsel_table); +static DEVICE_ATTR_RW(s2mpg12_channel_muxsel); +static DEVICE_ATTR_RO(s2mpg12_lpf_current); +static DEVICE_ATTR_RO(s2mpg12_lpf_power); +static DEVICE_ATTR_RO(s2mpg12_acc_current); +static DEVICE_ATTR_RO(s2mpg12_acc_power); + +int create_s2mpg12_meter_sysfs(struct s2mpg12_meter *s2mpg12) +{ + struct device *s2mpg12_meter_dev = s2mpg12->dev; + int err = -ENODEV; + + s2mpg12_meter_dev = pmic_device_create(s2mpg12, "s2mpg12-meter"); + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_lpf_current); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_lpf_current.attr.name); + } + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_lpf_power); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_lpf_power.attr.name); + } + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_acc_current); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_acc_current.attr.name); + } + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_acc_power); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_acc_power.attr.name); + } + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_channel_muxsel); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_channel_muxsel.attr.name); + } + + err = device_create_file(s2mpg12_meter_dev, + &dev_attr_s2mpg12_muxsel_table); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_muxsel_table.attr.name); + } + + return 0; +} +#endif + +static int s2mpg12_meter_probe(struct platform_device *pdev) +{ + struct s2mpg12_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg12_platform_data *pdata = iodev->pdata; + struct s2mpg12_meter *s2mpg12; + int ret = 0; + + if (!pdata) { + dev_err(pdev->dev.parent, "Platform data not supplied\n"); + return -ENODEV; + } + + s2mpg12 = devm_kzalloc(&pdev->dev, sizeof(struct s2mpg12_meter), + GFP_KERNEL); + if (!s2mpg12) + return -ENOMEM; + + s2mpg12->iodev = iodev; + s2mpg12->i2c = iodev->meter; + s2mpg12->dev = &pdev->dev; + + mutex_init(&s2mpg12->meter_lock); + platform_set_drvdata(pdev, s2mpg12); + +#if !IS_ENABLED(CONFIG_ODPM) + + /* initial setting */ + /* set BUCK1M ~ BUCK8m muxsel from CH0 to CH7 */ + /* any necessary settings can be added */ + s2mpg1x_meter_set_int_samp_rate(ID_S2MPG12, s2mpg12->i2c, INT_125HZ); + + s2mpg12_meter_set_muxsel(s2mpg12, 0, BUCK1); + s2mpg12_meter_set_muxsel(s2mpg12, 1, BUCK2); + s2mpg12_meter_set_muxsel(s2mpg12, 2, BUCK3); + s2mpg12_meter_set_muxsel(s2mpg12, 3, BUCK4); + s2mpg12_meter_set_muxsel(s2mpg12, 4, BUCK5); + s2mpg12_meter_set_muxsel(s2mpg12, 5, BUCK6); + s2mpg12_meter_set_muxsel(s2mpg12, 6, BUCK7); + s2mpg12_meter_set_muxsel(s2mpg12, 7, BUCK9); + s2mpg12_meter_set_muxsel(s2mpg12, 8, BUCK10); + s2mpg12_meter_set_muxsel(s2mpg12, 9, LDO1); + s2mpg12_meter_set_muxsel(s2mpg12, 10, LDO2); + s2mpg12_meter_set_muxsel(s2mpg12, 11, LDO3); + + s2mpg12_meter_onoff(s2mpg12, true); + s2mpg12_ext_meter_onoff(s2mpg12, false); + +#else + ret = mfd_add_devices(s2mpg12->dev, -1, s2mpg12_meter_devs, + ARRAY_SIZE(s2mpg12_meter_devs), NULL, 0, NULL); + if (ret < 0) { + mfd_remove_devices(s2mpg12->dev); + return ret; + } +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + /* create sysfs */ + ret = create_s2mpg12_meter_sysfs(s2mpg12); +#endif + + return ret; +} + +static int s2mpg12_meter_remove(struct platform_device *pdev) +{ + struct s2mpg12_meter *s2mpg12 = platform_get_drvdata(pdev); + + s2mpg12_meter_onoff(s2mpg12, false); + s2mpg12_ext_meter_onoff(s2mpg12, false); + +#if IS_ENABLED(CONFIG_ODPM) + mfd_remove_devices(s2mpg12->dev); +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + pmic_device_destroy(s2mpg12->dev->devt); +#endif + return 0; +} + +static void s2mpg12_meter_shutdown(struct platform_device *pdev) +{ + struct s2mpg12_meter *s2mpg12 = platform_get_drvdata(pdev); + + s2mpg12_meter_onoff(s2mpg12, false); + s2mpg12_ext_meter_onoff(s2mpg12, false); +} + +static const struct platform_device_id s2mpg12_meter_id[] = { + { "s2mpg12-meter", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(platform, s2mpg12_meter_id); + +static struct platform_driver s2mpg12_meter_driver = { + .driver = { + .name = "s2mpg12-meter", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = s2mpg12_meter_probe, + .remove = s2mpg12_meter_remove, + .shutdown = s2mpg12_meter_shutdown, + .id_table = s2mpg12_meter_id, +}; + +static int __init s2mpg12_meter_init(void) +{ + return platform_driver_register(&s2mpg12_meter_driver); +} + +subsys_initcall(s2mpg12_meter_init); + +static void __exit s2mpg12_meter_exit(void) +{ + platform_driver_unregister(&s2mpg12_meter_driver); +} + +module_exit(s2mpg12_meter_exit); + +/* Module information */ +MODULE_DESCRIPTION("SAMSUNG S2MPG12 Meter Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/s2mpg12-regulator.c b/drivers/regulator/s2mpg12-regulator.c new file mode 100644 index 000000000000..d713d45e6e7e --- /dev/null +++ b/drivers/regulator/s2mpg12-regulator.c @@ -0,0 +1,1124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg12-regulator.c + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include <../drivers/pinctrl/samsung/pinctrl-samsung.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef TEST_DBG +#define TEST_DBG 0 +#endif + +static struct s2mpg12_pmic *s2mpg12_st_pmic; +static struct regulator_desc regulators[S2MPG12_REGULATOR_MAX]; + +static unsigned int s2mpg12_of_map_mode(unsigned int val) +{ + switch (val) { + case SEC_OPMODE_SUSPEND: /* ON in Standby Mode */ + return 0x1; + case SEC_OPMODE_MIF: /* ON in PWREN_MIF mode */ + return 0x2; + case SEC_OPMODE_ON: /* ON in Normal Mode */ + return 0x3; + default: + return 0x3; + } +} + +static int s2m_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + unsigned int val; + int id = rdev_get_id(rdev); + int enable_mask = rdev->desc->enable_mask; + int enable_shift = 0; + + while (1) { + if (enable_mask & 0x1) + break; + + enable_shift++; + enable_mask = enable_mask >> 1; + + if (enable_shift > 7) + dev_err(s2mpg12->dev, "[%d]: error caculating enable_shift!\n", id); + }; + + val = (mode << enable_shift) & rdev->desc->enable_mask; + + s2mpg12->opmode[id] = val; + return 0; +} + +static int s2m_enable(struct regulator_dev *rdev) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + + return s2mpg12_update_reg(s2mpg12->i2c, rdev->desc->enable_reg, + s2mpg12->opmode[rdev_get_id(rdev)], + rdev->desc->enable_mask); +} + +static int s2m_disable(struct regulator_dev *rdev) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + unsigned int val; + + if (rdev->desc->enable_is_inverted) + val = rdev->desc->enable_mask; + else + val = 0; + + return s2mpg12_update_reg(s2mpg12->i2c, rdev->desc->enable_reg, val, + rdev->desc->enable_mask); +} + +static int s2m_is_enabled(struct regulator_dev *rdev) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + int ret; + u8 val; + + ret = s2mpg12_read_reg(s2mpg12->i2c, rdev->desc->enable_reg, &val); + if (ret) + return ret; + + if (rdev->desc->enable_is_inverted) + return (val & rdev->desc->enable_mask) == 0; + return (val & rdev->desc->enable_mask) != 0; +} + +static int s2m_get_voltage_sel(struct regulator_dev *rdev) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + int ret; + u8 val; + + ret = s2mpg12_read_reg(s2mpg12->i2c, rdev->desc->vsel_reg, &val); + if (ret) + return ret; + + val &= rdev->desc->vsel_mask; + + return val; +} + +static int s2m_set_voltage_sel(struct regulator_dev *rdev, + unsigned int sel) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + int ret; + + ret = s2mpg12_update_reg(s2mpg12->i2c, rdev->desc->vsel_reg, sel, + rdev->desc->vsel_mask); + if (ret < 0) + goto out; + + if (rdev->desc->apply_bit) + ret = s2mpg12_update_reg(s2mpg12->i2c, rdev->desc->apply_reg, + rdev->desc->apply_bit, + rdev->desc->apply_bit); + return ret; +out: + dev_warn(s2mpg12->dev, "%s: failed to set regulator voltage\n", + rdev->desc->name); + ret = -EINVAL; + return ret; +} + +static int s2m_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, + unsigned int new_selector) +{ + struct s2mpg12_pmic *s2mpg12 = rdev_get_drvdata(rdev); + unsigned int ramp_delay = 0; + int old_volt, new_volt; + + if (rdev->constraints->ramp_delay) + ramp_delay = rdev->constraints->ramp_delay; + else if (rdev->desc->ramp_delay) + ramp_delay = rdev->desc->ramp_delay; + + if (ramp_delay == 0) { + dev_warn(s2mpg12->dev, "%s: ramp_delay not set\n", + rdev->desc->name); + return -EINVAL; + } + + /* validity check */ + if (!rdev->desc->ops->list_voltage) + return -EINVAL; + + old_volt = rdev->desc->ops->list_voltage(rdev, old_selector); + new_volt = rdev->desc->ops->list_voltage(rdev, new_selector); + + if (old_selector < new_selector) + return DIV_ROUND_UP(new_volt - old_volt, ramp_delay); + return DIV_ROUND_UP(old_volt - new_volt, ramp_delay); +} + +int pmic_read_pwrkey_status(void) +{ + struct s2mpg12_pmic *s2mpg12 = s2mpg12_st_pmic; + u8 val, ret; + + if (!s2mpg12) + return -ENODEV; + + ret = s2mpg12_read_reg(s2mpg12->i2c, S2MPG12_PM_STATUS1, &val); + if (ret) + return ret; + + return (val & S2MPG12_STATUS1_PWRON); +} +EXPORT_SYMBOL_GPL(pmic_read_pwrkey_status); + +static struct regulator_ops s2mpg12_regulator_ops = { + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .is_enabled = s2m_is_enabled, + .enable = s2m_enable, + .disable = s2m_disable, + .get_voltage_sel = s2m_get_voltage_sel, + .set_voltage_sel = s2m_set_voltage_sel, + .set_voltage_time_sel = s2m_set_voltage_time_sel, + .set_mode = s2m_set_mode, +}; + +#define _BUCK(macro) S2MPG12_BUCK##macro +#define _LDO(macro) S2MPG12_LDO##macro +#define _REG(ctrl) S2MPG12_PM##ctrl +#define _TIME(macro) S2MPG12_ENABLE_TIME##macro +#define _MIN(group) S2MPG12_REG_MIN##group +#define _STEP(group) S2MPG12_REG_STEP##group +#define _N_VOLTAGES(num) S2MPG12_REG_N_VOLTAGES_##num +#define _MASK(num) S2MPG12_REG_ENABLE_MASK##num + +#define REG_DESC(_name, _id, g, v, n, e, em, t) \ + { \ + .name = _name, .id = _id, .ops = &s2mpg12_regulator_ops, \ + .type = REGULATOR_VOLTAGE, .owner = THIS_MODULE, \ + .min_uV = _MIN(g), .uV_step = _STEP(g), .n_voltages = n, \ + .vsel_reg = v, .vsel_mask = n - 1, .enable_reg = e, \ + .enable_mask = em, .enable_time = t, \ + .of_map_mode = s2mpg12_of_map_mode \ + } + +static struct regulator_desc regulators[S2MPG12_REGULATOR_MAX] = { + /* name, id, voltage_group, vsel_reg, n_voltages, */ + /* enable_reg, enable_mask, enable_time */ + REG_DESC("LDO1M", _LDO(1), 2, _REG(_L1M_CTRL), _N_VOLTAGES(128), + _REG(_L1M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO2M", _LDO(2), 4, _REG(_L2M_CTRL), _N_VOLTAGES(64), + _REG(_L2M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO3M", _LDO(3), 2, _REG(_L3M_CTRL), _N_VOLTAGES(128), + _REG(_L3M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO4M", _LDO(4), 4, _REG(_L4M_CTRL), _N_VOLTAGES(64), + _REG(_L4M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO5M", _LDO(5), 3, _REG(_L5M_CTRL), _N_VOLTAGES(64), + _REG(_L5M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO6M", _LDO(6), 3, _REG(_L6M_CTRL), _N_VOLTAGES(64), + _REG(_L6M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO7M", _LDO(7), 2, _REG(_L7M_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_1_0), _TIME(_LDO)), + REG_DESC("LDO8M", _LDO(8), 3, _REG(_L8M_CTRL), _N_VOLTAGES(64), + _REG(_L8M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO9M", _LDO(9), 4, _REG(_L9M_CTRL), _N_VOLTAGES(64), + _REG(_L9M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO10M", _LDO(10), 5, _REG(_L10M_CTRL), _N_VOLTAGES(64), + _REG(_L10M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO11M", _LDO(11), 2, _REG(_L11M_CTRL1), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_3_2), _TIME(_LDO)), + REG_DESC("LDO12M", _LDO(12), 2, _REG(_L12M_CTRL1), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_5_4), _TIME(_LDO)), + REG_DESC("LDO13M", _LDO(13), 2, _REG(_L13M_CTRL1), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO14M", _LDO(14), 4, _REG(_L14M_CTRL), _N_VOLTAGES(64), + _REG(_L14M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO15M", _LDO(15), 2, _REG(_L15M_CTRL1), _N_VOLTAGES(128), + _REG(_LDO_CTRL2), _MASK(_1_0), _TIME(_LDO)), + REG_DESC("LDO16M", _LDO(16), 3, _REG(_L16M_CTRL), _N_VOLTAGES(64), + _REG(_L16M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO17M", _LDO(17), 2, _REG(_L17M_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL2), _MASK(_3_2), _TIME(_LDO)), + REG_DESC("LDO18M", _LDO(18), 4, _REG(_L18M_CTRL), _N_VOLTAGES(64), + _REG(_L18M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO19M", _LDO(19), 2, _REG(_L19M_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL2), _MASK(_5_4), _TIME(_LDO)), + REG_DESC("LDO20M", _LDO(20), 4, _REG(_L20M_CTRL), _N_VOLTAGES(64), + _REG(_L20M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO21M", _LDO(21), 5, _REG(_L21M_CTRL), _N_VOLTAGES(64), + _REG(_L21M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO22M", _LDO(22), 2, _REG(_L22M_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL2), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO23M", _LDO(23), 4, _REG(_L23M_CTRL), _N_VOLTAGES(64), + _REG(_L23M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO24M", _LDO(24), 4, _REG(_L24M_CTRL), _N_VOLTAGES(64), + _REG(_L24M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO25M", _LDO(25), 4, _REG(_L25M_CTRL), _N_VOLTAGES(64), + _REG(_L25M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO26M", _LDO(26), 5, _REG(_L26M_CTRL), _N_VOLTAGES(64), + _REG(_L26M_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO27M", _LDO(27), 5, _REG(_L27M_CTRL), _N_VOLTAGES(64), + _REG(_L27M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO28M", _LDO(28), 3, _REG(_L28M_CTRL), _N_VOLTAGES(64), + _REG(_L28M_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("BUCK1M", _BUCK(1), 1, _REG(_B1M_OUT1), _N_VOLTAGES(256), + _REG(_B1M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK2M", _BUCK(2), 1, _REG(_B2M_OUT1), _N_VOLTAGES(256), + _REG(_B2M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK3M", _BUCK(3), 1, _REG(_B3M_OUT1), _N_VOLTAGES(256), + _REG(_B3M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK4M", _BUCK(4), 1, _REG(_B4M_OUT1), _N_VOLTAGES(256), + _REG(_B4M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK5M", _BUCK(5), 1, _REG(_B5M_OUT1), _N_VOLTAGES(256), + _REG(_B5M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK6M", _BUCK(6), 1, _REG(_B6M_OUT1), _N_VOLTAGES(256), + _REG(_B6M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK7M", _BUCK(7), 1, _REG(_B7M_OUT1), _N_VOLTAGES(256), + _REG(_B7M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK8M", _BUCK(8), 1, _REG(_B8M_OUT1), _N_VOLTAGES(256), + _REG(_B8M_CTRL), _MASK(_7), _TIME(_BUCK)), + REG_DESC("BUCK9M", _BUCK(9), 1, _REG(_B9M_OUT1), _N_VOLTAGES(256), + _REG(_B9M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK10M", _BUCK(10), 1, _REG(_B10M_OUT1), _N_VOLTAGES(256), + _REG(_B10M_CTRL), _MASK(_7_6), _TIME(_BUCK)), + +}; + +#if IS_ENABLED(CONFIG_OF) +static int s2mpg12_pmic_dt_parse_pdata(struct s2mpg12_dev *iodev, + struct s2mpg12_platform_data *pdata) +{ + struct device_node *pmic_np, *regulators_np, *reg_np; + struct s2mpg12_regulator_data *rdata; + unsigned int i; + int ret, len; + u32 val; + const u32 *p; + + pmic_np = iodev->dev->of_node; + if (!pmic_np) { + dev_err(iodev->dev, "could not find pmic sub-node\n"); + return -ENODEV; + } + + regulators_np = of_find_node_by_name(pmic_np, "regulators"); + if (!regulators_np) { + dev_err(iodev->dev, "could not find regulators sub-node\n"); + return -EINVAL; + } + + /* count the number of regulators to be supported in pmic */ + pdata->num_regulators = 0; + for_each_child_of_node(regulators_np, reg_np) { + pdata->num_regulators++; + } + + rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) * pdata->num_regulators, + GFP_KERNEL); + if (!rdata) + return -ENOMEM; + + pdata->regulators = rdata; + for_each_child_of_node(regulators_np, reg_np) { + for (i = 0; i < ARRAY_SIZE(regulators); i++) + if (!of_node_cmp(reg_np->name, regulators[i].name)) + break; + + if (i == ARRAY_SIZE(regulators)) { + dev_warn(iodev->dev, + "don't know how to configure regulator %s\n", + reg_np->name); + continue; + } + + rdata->id = i; + rdata->initdata = of_get_regulator_init_data(iodev->dev, reg_np, + ®ulators[i]); + rdata->reg_node = reg_np; + rdata++; + } + + if (of_gpio_count(pmic_np) < 1) { + dev_err(iodev->dev, "could not find pmic gpios\n"); + return -EINVAL; + } + + /* parse BUCK OCP Detection information */ + of_property_read_u32(pmic_np, "buck_ocp_ctrl1", &pdata->buck_ocp_ctrl1); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl2", &pdata->buck_ocp_ctrl2); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl3", &pdata->buck_ocp_ctrl3); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl4", &pdata->buck_ocp_ctrl4); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl5", &pdata->buck_ocp_ctrl5); + + /* parse SMPL_WARN information */ + pdata->smpl_warn_pin = of_get_gpio(pmic_np, 0); + if (pdata->smpl_warn_pin < 0) + dev_err(iodev->dev, "smpl_warn_pin < 0: %d\n", + pdata->smpl_warn_pin); + + ret = of_property_read_u32(pmic_np, "smpl_warn_vth", &val); + pdata->smpl_warn_lvl = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "smpl_warn_hys", &val); + pdata->smpl_warn_hys = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "smpl_warn_lbdt", &val); + pdata->smpl_warn_lbdt = ret ? 0 : val; + + /* parse OCP_WARN information */ + pdata->b2_ocp_warn_pin = of_get_gpio(pmic_np, 2); + if (pdata->b2_ocp_warn_pin < 0) + dev_err(iodev->dev, "b2_ocp_warn_pin < 0: %d\n", + pdata->b2_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_en", &val); + pdata->b2_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_cnt", &val); + pdata->b2_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_dvs_mask", &val); + pdata->b2_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_lvl", &val); + pdata->b2_ocp_warn_lvl = ret ? 0 : val; + + pdata->b3_ocp_warn_pin = of_get_gpio(pmic_np, 1); + if (pdata->b3_ocp_warn_pin < 0) + dev_err(iodev->dev, "b3_ocp_warn_pin < 0: %d\n", + pdata->b3_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b3_ocp_warn_en", &val); + pdata->b3_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_ocp_warn_cnt", &val); + pdata->b3_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_ocp_warn_dvs_mask", &val); + pdata->b3_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_ocp_warn_lvl", &val); + pdata->b3_ocp_warn_lvl = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_ocp_warn_en", &val); + pdata->b10_ocp_warn_en = ret ? 0 : val; + + pdata->b10_ocp_warn_pin = of_get_gpio(pmic_np, 5); + if (pdata->b10_ocp_warn_pin < 0) + dev_err(iodev->dev, "b10_ocp_warn_pin < 0: %d\n", + pdata->b10_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b10_ocp_warn_cnt", &val); + pdata->b10_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_ocp_warn_dvs_mask", &val); + pdata->b10_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_ocp_warn_lvl", &val); + pdata->b10_ocp_warn_lvl = ret ? 0 : val; + + /* parse SOFT_OCP_WARN information */ + pdata->b2_soft_ocp_warn_pin = of_get_gpio(pmic_np, 4); + if (pdata->b2_soft_ocp_warn_pin < 0) + dev_err(iodev->dev, "b2_soft_ocp_warn_pin < 0: %d\n", + pdata->b2_soft_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_en", &val); + pdata->b2_soft_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_cnt", &val); + pdata->b2_soft_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_dvs_mask", &val); + pdata->b2_soft_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_lvl", &val); + pdata->b2_soft_ocp_warn_lvl = ret ? 0 : val; + + pdata->b3_soft_ocp_warn_pin = of_get_gpio(pmic_np, 3); + if (pdata->b3_soft_ocp_warn_pin < 0) + dev_err(iodev->dev, "b3_soft_ocp_warn_pin < 0: %d\n", + pdata->b3_soft_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b3_soft_ocp_warn_en", &val); + pdata->b3_soft_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_soft_ocp_warn_cnt", &val); + pdata->b3_soft_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_soft_ocp_warn_dvs_mask", &val); + pdata->b3_soft_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b3_soft_ocp_warn_lvl", &val); + pdata->b3_soft_ocp_warn_lvl = ret ? 0 : val; + + pdata->b10_soft_ocp_warn_pin = of_get_gpio(pmic_np, 6); + if (pdata->b10_soft_ocp_warn_pin < 0) + dev_err(iodev->dev, "b10_soft_ocp_warn_pin < 0: %d\n", + pdata->b10_soft_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b10_soft_ocp_warn_en", &val); + pdata->b10_soft_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_soft_ocp_warn_cnt", &val); + pdata->b10_soft_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_soft_ocp_warn_dvs_mask", &val); + pdata->b10_soft_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b10_soft_ocp_warn_lvl", &val); + pdata->b10_soft_ocp_warn_lvl = ret ? 0 : val; + + /* Set SEL_VGPIO (control_sel) */ + p = of_get_property(pmic_np, "sel_vgpio", &len); + if (!p) { + dev_err(iodev->dev, "(ERROR) sel_vgpio isn't parsing\n"); + return -EINVAL; + } + + len = len / sizeof(u32); + if (len != S2MPG12_VGPIO_NUM) { + dev_err(iodev->dev, "(ERROR) sel_vgpio num isn't not equal\n"); + return -EINVAL; + } + + pdata->sel_vgpio = devm_kzalloc(iodev->dev, sizeof(u32) * len, GFP_KERNEL); + if (!(pdata->sel_vgpio)) { + dev_err(iodev->dev, + "(ERROR) could not allocate memory for sel_vgpio data\n"); + return -ENOMEM; + } + + for (i = 0; i < len; i++) { + ret = of_property_read_u32_index(pmic_np, "sel_vgpio", i, &pdata->sel_vgpio[i]); + if (ret) { + dev_err(iodev->dev, "(ERROR) sel_vgpio%d is empty\n", i + 1); + pdata->sel_vgpio[i] = 0x1FF; + } + } + + return 0; +} +#else +static int s2mpg12_pmic_dt_parse_pdata(struct s2mpg12_dev *iodev, + struct s2mpg12_platform_data *pdata) +{ + return 0; +} +#endif /* CONFIG_OF */ + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + +#define I2C_ADDR_TOP 0x00 +#define I2C_ADDR_PMIC 0x01 +#define I2C_ADDR_RTC 0x02 +#define I2C_ADDR_METER 0x0A +#define I2C_ADDR_WLWP 0x0B +#define I2C_ADDR_GPIO 0x0C +#define I2C_ADDR_MT_TRIM 0x0E +#define I2C_ADDR_TRIM 0x0F + +static ssize_t s2mpg12_pmic_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg12_pmic *s2mpg12 = dev_get_drvdata(dev); + int ret; + u16 reg_addr; + + if (!buf) + return -1; + + ret = kstrtou16(buf, 0, ®_addr); + if (ret < 0) { + dev_err(dev, "fail to transform i2c address\n"); + return ret; + } + + s2mpg12->read_addr = reg_addr; + + return size; +} + +static ssize_t s2mpg12_pmic_read_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg12_pmic *s2mpg12 = dev_get_drvdata(dev); + struct i2c_client *client = NULL; + u16 reg_addr = s2mpg12->read_addr; + u8 val; + int ret; + + switch (reg_addr >> 8) { + case I2C_ADDR_TOP: + client = s2mpg12->iodev->i2c; + break; + case I2C_ADDR_PMIC: + client = s2mpg12->iodev->pmic; + break; + case I2C_ADDR_RTC: + client = s2mpg12->iodev->rtc; + break; + case I2C_ADDR_METER: + client = s2mpg12->iodev->meter; + break; + case I2C_ADDR_WLWP: + client = s2mpg12->iodev->wlwp; + break; + case I2C_ADDR_GPIO: + client = s2mpg12->iodev->gpio; + break; + case I2C_ADDR_MT_TRIM: + client = s2mpg12->iodev->mt_trim; + break; + case I2C_ADDR_TRIM: + client = s2mpg12->iodev->trim; + break; + default: + return -1; + } + + ret = s2mpg12_read_reg(client, reg_addr, &val); + if (ret < 0) { + dev_err(dev, "fail to read i2c address\n"); + return ret; + } + + dev_dbg(dev, "reg(0x%04X) data(0x%02X)\n", reg_addr, val); + + return scnprintf(buf, PAGE_SIZE, "0x%04X: 0x%02X\n", reg_addr, val); +} + +static ssize_t s2mpg12_pmic_write_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg12_pmic *s2mpg12 = dev_get_drvdata(dev); + struct i2c_client *client = NULL; + int ret; + u16 reg; + u8 data; + + if (!buf) + return size; + + ret = sscanf(buf, "%hx %hhx", ®, &data); + if (ret != 2) { + dev_err(dev, "input error\n"); + return size; + } + + dev_dbg(s2mpg12->dev, "reg(0x%04X) data(0x%02X)\n", reg, data); + + switch (reg >> 8) { + case I2C_ADDR_TOP: + client = s2mpg12->iodev->i2c; + break; + case I2C_ADDR_PMIC: + client = s2mpg12->iodev->pmic; + break; + case I2C_ADDR_RTC: + client = s2mpg12->iodev->rtc; + break; + case I2C_ADDR_METER: + client = s2mpg12->iodev->meter; + break; + case I2C_ADDR_WLWP: + client = s2mpg12->iodev->wlwp; + break; + case I2C_ADDR_GPIO: + client = s2mpg12->iodev->gpio; + break; + case I2C_ADDR_MT_TRIM: + client = s2mpg12->iodev->mt_trim; + break; + case I2C_ADDR_TRIM: + client = s2mpg12->iodev->trim; + break; + default: + return size; + } + + ret = s2mpg12_write_reg(client, reg, data); + if (ret < 0) + dev_err(dev, "fail to write i2c addr/data\n"); + + return size; +} + +static ssize_t s2mpg12_pmic_write_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "echo (register addr.) (data) > s2mpg12_write\n"); +} + +static DEVICE_ATTR_RW(s2mpg12_pmic_write); +static DEVICE_ATTR_RW(s2mpg12_pmic_read); + +int create_s2mpg12_pmic_sysfs(struct s2mpg12_pmic *s2mpg12) +{ + struct device *s2mpg12_pmic = s2mpg12->dev; + int err = -ENODEV; + + s2mpg12->read_addr = 0; + + s2mpg12_pmic = pmic_device_create(s2mpg12, "s2mpg12-pmic"); + + err = device_create_file(s2mpg12_pmic, &dev_attr_s2mpg12_pmic_write); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_pmic_write.attr.name); + } + + err = device_create_file(s2mpg12_pmic, &dev_attr_s2mpg12_pmic_read); + if (err) { + dev_err(s2mpg12->dev, + "s2mpg12_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg12_pmic_read.attr.name); + } + + return 0; +} +#endif + +static irqreturn_t s2mpg12_buck_ocp_irq(int irq, void *data) +{ + struct s2mpg12_pmic *s2mpg12 = data; + int i; + + mutex_lock(&s2mpg12->lock); + + for (i = 0; i < S2MPG12_BUCK_MAX; i++) { + if (s2mpg12->buck_ocp_irq[i] == irq) { + dev_dbg(s2mpg12->dev, "BUCK[%d] OCP IRQ, %d\n", i + 1, irq); + break; + } + } + + mutex_unlock(&s2mpg12->lock); + return IRQ_HANDLED; +} + +void s2mpg12_ocp_detection_config(struct s2mpg12_pmic *s2mpg12, + struct s2mpg12_platform_data *pdata) +{ + int ret; + + dev_info(s2mpg12->dev, "BUCK_OCP_CTRL1: 0x%x\n", pdata->buck_ocp_ctrl1); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_BUCK_OCP_CTRL1, pdata->buck_ocp_ctrl1); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting BUCK_OCP_CTRL1: %d\n", ret); + + dev_info(s2mpg12->dev, "BUCK_OCP_CTRL2: 0x%x\n", pdata->buck_ocp_ctrl2); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_BUCK_OCP_CTRL2, pdata->buck_ocp_ctrl2); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting BUCK_OCP_CTRL2: %d\n", ret); + + dev_info(s2mpg12->dev, "BUCK_OCP_CTRL3: 0x%x\n", pdata->buck_ocp_ctrl3); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_BUCK_OCP_CTRL3, pdata->buck_ocp_ctrl3); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting BUCK_OCP_CTRL3: %d\n", ret); + + dev_info(s2mpg12->dev, "BUCK_OCP_CTRL4: 0x%x\n", pdata->buck_ocp_ctrl4); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_BUCK_OCP_CTRL4, pdata->buck_ocp_ctrl4); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting BUCK_OCP_CTRL4: %d\n", ret); + + dev_info(s2mpg12->dev, "BUCK_OCP_CTRL5: 0x%x\n", pdata->buck_ocp_ctrl5); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_BUCK_OCP_CTRL5, pdata->buck_ocp_ctrl5); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting BUCK_OCP_CTRL5: %d\n", ret); + +} + +int s2mpg12_smpl_warn(struct s2mpg12_pmic *s2mpg12, + struct s2mpg12_platform_data *pdata) +{ + u8 val; + int ret; + + val = (pdata->smpl_warn_lbdt << S2MPG12_SMPL_WARN_LBDT_SHIFT) | + (pdata->smpl_warn_hys << S2MPG12_SMPL_WARN_HYS_SHIFT) | + (pdata->smpl_warn_lvl << S2MPG12_SMPL_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "SMPL_WARN_CTRL : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_SMPL_WARN_CTRL, val); + if (ret) + dev_err(s2mpg12->dev, "i2c write error setting smpl_warn\n"); + + return ret; +} + +int s2mpg12_ocp_warn(struct s2mpg12_pmic *s2mpg12, + struct s2mpg12_platform_data *pdata) +{ + u8 val; + int ret; + + val = (pdata->b2_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b2_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b2_ocp_warn_dvs_mask << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b2_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B2M_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B2M_OCP_WARN, val); + if (ret) + pr_err("i2c write error setting b2m_ocp_warn\n"); + + val = (pdata->b3_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b3_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b3_ocp_warn_dvs_mask << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b3_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B3M_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B3M_OCP_WARN, val); + if (ret) + pr_err("i2c write error setting b3m_ocp_warn\n"); + + val = (pdata->b10_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b10_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b10_ocp_warn_dvs_mask + << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b10_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B10M_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B10M_OCP_WARN, val); + if (ret) + pr_err("i2c write error setting b10m_ocp_warn\n"); + + val = (pdata->b2_soft_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b2_soft_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b2_soft_ocp_warn_dvs_mask + << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b2_soft_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B2M_SOFT_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B2M_SOFT_OCP_WARN, + val); + if (ret) + pr_err("i2c write error setting b2m_soft_ocp_warn\n"); + + val = (pdata->b3_soft_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b3_soft_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b3_soft_ocp_warn_dvs_mask + << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b3_soft_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B3M_SOFT_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B3M_SOFT_OCP_WARN, + val); + if (ret) + pr_err("i2c write error setting b3m_soft_ocp_warn\n"); + + val = (pdata->b10_soft_ocp_warn_en << S2MPG12_OCP_WARN_EN_SHIFT) | + (pdata->b10_soft_ocp_warn_cnt << S2MPG12_OCP_WARN_CNT_SHIFT) | + (pdata->b10_soft_ocp_warn_dvs_mask + << S2MPG12_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b10_soft_ocp_warn_lvl << S2MPG12_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg12->dev, "B10M_SOFT_OCP_WARN : 0x%x\n", val); + ret = s2mpg12_write_reg(s2mpg12->i2c, S2MPG12_PM_B10M_SOFT_OCP_WARN, + val); + if (ret) + pr_err("i2c write error setting b10m_soft_ocp_warn\n"); + + return ret; +} + +static int s2mpg12_set_sel_vgpio(struct s2mpg12_pmic *s2mpg12, + struct s2mpg12_platform_data *pdata) +{ + int ret, i, cnt = 0; + u8 reg, val; + char prtlog[] = "0x%02hhx[0x%02hhx], "; + char buf[(S2MPG12_VGPIO_NUM * sizeof(prtlog))] = {0, }; + + for (i = 0; i < S2MPG12_VGPIO_NUM; i++) { + reg = S2MPG12_PM_PCTRLSEL1 + i; + val = pdata->sel_vgpio[i]; + + if (val > S2MPG12_VGPIO_MAX_VAL) { + dev_err(s2mpg12->dev, "sel_vgpio%d exceed the value\n", i + 1); + goto err; + } + + ret = s2mpg12_write_reg(s2mpg12->i2c, reg, val); + if (ret) { + dev_err(s2mpg12->dev, "sel_vgpio%d write error\n", i + 1); + goto err; + } + + cnt += snprintf(buf + cnt, sizeof(buf) - cnt, prtlog, reg, val); + } + + dev_dbg(s2mpg12->dev, "vgpio: %s\n", buf); + + return 0; +err: + return -1; +} + +int s2mpg12_oi_function(struct s2mpg12_pmic *s2mpg12) +{ + int ret = 0; + /* add OI configuration code if necessary */ + + /* OI function enable */ + /* OI power down disable */ + + /* OI detection time window : 500us, OI comp. output count : 50 times */ + + return ret; +} + +static int s2mpg12_pmic_probe(struct platform_device *pdev) +{ + struct s2mpg12_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg12_platform_data *pdata = iodev->pdata; + struct regulator_config config = {}; + struct s2mpg12_pmic *s2mpg12; + int irq_base; + int i, ret; + + if (iodev->dev->of_node) { + ret = s2mpg12_pmic_dt_parse_pdata(iodev, pdata); + if (ret) + return ret; + } + + if (!pdata) { + dev_err(pdev->dev.parent, "Platform data not supplied\n"); + return -ENODEV; + } + + s2mpg12 = devm_kzalloc(&pdev->dev, sizeof(struct s2mpg12_pmic), + GFP_KERNEL); + if (!s2mpg12) + return -ENOMEM; + + irq_base = pdata->irq_base; + if (!irq_base) { + dev_err(&pdev->dev, "Failed to get irq base %d\n", irq_base); + return -ENODEV; + } + + s2mpg12->rdev = devm_kzalloc(&pdev->dev, + sizeof(struct regulator_dev *) * + S2MPG12_REGULATOR_MAX, + GFP_KERNEL); + s2mpg12->opmode = + devm_kzalloc(&pdev->dev, + sizeof(unsigned int) * S2MPG12_REGULATOR_MAX, + GFP_KERNEL); + s2mpg12->buck_ocp_irq = devm_kzalloc(&pdev->dev, + sizeof(int) * S2MPG12_BUCK_MAX, + GFP_KERNEL); + + s2mpg12->iodev = iodev; + s2mpg12->i2c = iodev->pmic; + s2mpg12->dev = &pdev->dev; + + mutex_init(&s2mpg12->lock); + + s2mpg12_st_pmic = s2mpg12; + + platform_set_drvdata(pdev, s2mpg12); + + for (i = 0; i < pdata->num_regulators; i++) { + int id = pdata->regulators[i].id; + + config.dev = &pdev->dev; + config.init_data = pdata->regulators[i].initdata; + config.driver_data = s2mpg12; + config.of_node = pdata->regulators[i].reg_node; + s2mpg12->opmode[id] = regulators[id].enable_mask; + + s2mpg12->rdev[i] = regulator_register(®ulators[id], &config); + if (IS_ERR(s2mpg12->rdev[i])) { + ret = PTR_ERR(s2mpg12->rdev[i]); + dev_err(&pdev->dev, "regulator init failed for %d\n", i); + s2mpg12->rdev[i] = NULL; + goto err; + } + } + + s2mpg12->num_regulators = pdata->num_regulators; + + /* request IRQ */ + for (i = 0; i < S2MPG12_BUCK_MAX; i++) { + s2mpg12->buck_ocp_irq[i] = + irq_base + S2MPG12_IRQ_OCP_B1M_INT4 + i; + + ret = devm_request_threaded_irq(&pdev->dev, + s2mpg12->buck_ocp_irq[i], NULL, + s2mpg12_buck_ocp_irq, 0, + "BUCK_OCP_IRQ", s2mpg12); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to request BUCK[%d] OCP IRQ: %d: %d\n", + i + 1, s2mpg12->buck_ocp_irq[i], ret); + } + } + + s2mpg12_ocp_detection_config(s2mpg12, pdata); + ret = s2mpg12_smpl_warn(s2mpg12, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg12_smpl_warn fail\n"); + goto err; + } + + ret = s2mpg12_ocp_warn(s2mpg12, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg12_ocp_warn fail\n"); + goto err; + } + + ret = s2mpg12_set_sel_vgpio(s2mpg12, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg12_set_sel_vgpio fail\n"); + goto err; + } +#if IS_ENABLED(TEST_DBG) + ret = s2mpg12_oi_function(s2mpg12); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg12_oi_function fail\n"); + goto err; + } +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + /* create sysfs */ + ret = create_s2mpg12_pmic_sysfs(s2mpg12); + if (ret < 0) + return ret; +#endif + + return 0; +err: + for (i = 0; i < S2MPG12_REGULATOR_MAX; i++) + regulator_unregister(s2mpg12->rdev[i]); + + return ret; +} + +static int s2mpg12_pmic_remove(struct platform_device *pdev) +{ + struct s2mpg12_pmic *s2mpg12 = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < S2MPG12_REGULATOR_MAX; i++) + regulator_unregister(s2mpg12->rdev[i]); + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + pmic_device_destroy(s2mpg12->dev->devt); +#endif + return 0; +} + +static void s2mpg12_pmic_shutdown(struct platform_device *pdev) +{ +} + +#if IS_ENABLED(CONFIG_PM) +static int s2mpg12_pmic_suspend(struct device *dev) +{ +#if IS_ENABLED(TEST_DBG) + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg12_pmic *s2mpg12 = platform_get_drvdata(pdev); +#endif + int ret = 0; + + return ret; +} + +static int s2mpg12_pmic_resume(struct device *dev) +{ +#if IS_ENABLED(TEST_DBG) + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg12_pmic *s2mpg12 = platform_get_drvdata(pdev); +#endif + int ret = 0; + + return ret; +} +#else +#define s2mpg12_pmic_suspend NULL +#define s2mpg12_pmic_resume NULL +#endif /* CONFIG_PM */ + +const struct dev_pm_ops s2mpg12_pmic_pm = { + .suspend = s2mpg12_pmic_suspend, + .resume = s2mpg12_pmic_resume, +}; + +static const struct platform_device_id s2mpg12_pmic_id[] = { + { "s2mpg12-regulator", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(platform, s2mpg12_pmic_id); + +static struct platform_driver s2mpg12_pmic_driver = { + .driver = { + .name = "s2mpg12-regulator", + .owner = THIS_MODULE, +#if IS_ENABLED(CONFIG_PM) + .pm = &s2mpg12_pmic_pm, +#endif + .suppress_bind_attrs = true, + }, + .probe = s2mpg12_pmic_probe, + .remove = s2mpg12_pmic_remove, + .shutdown = s2mpg12_pmic_shutdown, + .id_table = s2mpg12_pmic_id, +}; + +static int __init s2mpg12_pmic_init(void) +{ + return platform_driver_register(&s2mpg12_pmic_driver); +} + +subsys_initcall(s2mpg12_pmic_init); + +static void __exit s2mpg12_pmic_exit(void) +{ + platform_driver_unregister(&s2mpg12_pmic_driver); +} + +module_exit(s2mpg12_pmic_exit); + +/* Module information */ +MODULE_AUTHOR("Sangbeom Kim "); +MODULE_DESCRIPTION("SAMSUNG S2MPG12 Regulator Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/s2mpg13-powermeter.c b/drivers/regulator/s2mpg13-powermeter.c new file mode 100644 index 000000000000..1637e4484f06 --- /dev/null +++ b/drivers/regulator/s2mpg13-powermeter.c @@ -0,0 +1,676 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg13-powermeter.c + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include <../drivers/pinctrl/samsung/pinctrl-samsung.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_ODPM) +static struct mfd_cell s2mpg13_meter_devs[] = { + { + .name = "s2mpg13-odpm", + }, +}; +#endif + +u32 s2mpg13_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m) +{ + switch (m) { + case BUCK3: + case BUCK4: + case BUCK5: + case BUCK6: + case BUCK8: + case BUCK9: + case BUCK10: + case BUCKC: + return CMS_BUCK_CURRENT; + case BUCK1: + case BUCK2: + return CMT_BUCK_CURRENT; + case BUCK7: + case BUCKD: + case BUCKA: + return VM_CURRENT; + case BUCKBOOST_10: + return BB_CURRENT; + case LDO9: + return DVS_NLDO_CURRENT_150mA; + case LDO4: + case LDO5: + case LDO6: + case LDO7: + case LDO10: + case LDO11: + case LDO13: + case LDO15: + case LDO16: + case LDO17: + case LDO18: + case LDO19: + case LDO20: + case LDO22: + case LDO28: + return PLDO_CURRENT_150mA; + case LDO26: + return NLDO_CURRENT_300mA; + case LDO12: + case LDO14: + case LDO27: + return PLDO_CURRENT_300mA; + case LDO1: + case LDO23: + case LDO24: + case LDO25: + return DVS_NLDO_CURRENT_800mA; + case LDO2: + case LDO3: + case LDO21: + return NLDO_CURRENT_800mA; + case LDO8: + return NLDO_CURRENT_1200mA; + default: + pr_err("%s: wrong muxsel\n", __func__); + return INVALID_RESOLUTION; + } +} +EXPORT_SYMBOL_GPL(s2mpg13_muxsel_to_current_resolution); + +u32 s2mpg13_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m) +{ + switch (m) { + case BUCK3: + case BUCK4: + case BUCK5: + case BUCK6: + case BUCK8: + case BUCK9: + case BUCK10: + case BUCKC: + return CMS_BUCK_POWER; + case BUCK1: + case BUCK2: + return CMT_BUCK_POWER; + case BUCK7: + case BUCKD: + case BUCKA: + return VM_POWER; + case BUCKBOOST_10: + return BB_POWER; + case LDO9: + return DVS_NLDO_POWER_150mA; + case LDO4: + case LDO5: + case LDO6: + case LDO7: + case LDO10: + case LDO11: + case LDO13: + case LDO15: + case LDO16: + case LDO17: + case LDO18: + case LDO19: + case LDO20: + case LDO22: + case LDO28: + return PLDO_POWER_150mA; + case LDO26: + return NLDO_POWER_300mA; + case LDO12: + case LDO14: + case LDO27: + return PLDO_POWER_300mA; + case LDO1: + case LDO23: + case LDO24: + case LDO25: + return DVS_NLDO_POWER_800mA; + case LDO2: + case LDO3: + case LDO21: + return NLDO_POWER_800mA; + case LDO8: + return NLDO_POWER_1200mA; + default: + pr_err("%s: wrong muxsel\n", __func__); + return INVALID_RESOLUTION; + } +} +EXPORT_SYMBOL_GPL(s2mpg13_muxsel_to_power_resolution); + +static const char *muxsel_to_str(s2mpg1x_meter_muxsel m) +{ + char *ret; + + switch (m) { + ENUM_STR(BUCK1, "S", ret); + ENUM_STR(BUCK2, "S", ret); + ENUM_STR(BUCK3, "S", ret); + ENUM_STR(BUCK4, "S", ret); + ENUM_STR(BUCK5, "S", ret); + ENUM_STR(BUCK6, "S", ret); + ENUM_STR(BUCK7, "S", ret); + ENUM_STR(BUCK8, "S", ret); + ENUM_STR(BUCK9, "S", ret); + ENUM_STR(BUCK10, "S", ret); + ENUM_STR(BUCKD, "", ret); + ENUM_STR(BUCKA, "", ret); + ENUM_STR(BUCKC, "", ret); + ENUM_STR(BUCKBOOST_10, "", ret); + ENUM_STR(VSEN_P4, "", ret); + ENUM_STR(VSEN_P5, "", ret); + ENUM_STR(VSEN_P6, "", ret); + ENUM_STR(LDO1, "S", ret); + ENUM_STR(LDO2, "S", ret); + ENUM_STR(LDO3, "S", ret); + ENUM_STR(LDO4, "S", ret); + ENUM_STR(LDO5, "S", ret); + ENUM_STR(LDO6, "S", ret); + ENUM_STR(LDO7, "S", ret); + ENUM_STR(LDO8, "S", ret); + ENUM_STR(LDO9, "S", ret); + ENUM_STR(LDO10, "S", ret); + ENUM_STR(LDO11, "S", ret); + ENUM_STR(LDO12, "S", ret); + ENUM_STR(LDO13, "S", ret); + ENUM_STR(LDO14, "S", ret); + ENUM_STR(LDO15, "S", ret); + ENUM_STR(LDO16, "S", ret); + ENUM_STR(LDO17, "S", ret); + ENUM_STR(LDO18, "S", ret); + ENUM_STR(LDO19, "S", ret); + ENUM_STR(LDO20, "S", ret); + ENUM_STR(LDO21, "S", ret); + ENUM_STR(LDO22, "S", ret); + ENUM_STR(LDO23, "S", ret); + ENUM_STR(LDO24, "S", ret); + ENUM_STR(LDO25, "S", ret); + ENUM_STR(LDO26, "S", ret); + ENUM_STR(LDO27, "S", ret); + ENUM_STR(LDO28, "S", ret); + ENUM_STR(VSEN_C4, "", ret); + ENUM_STR(VSEN_C5, "", ret); + ENUM_STR(VSEN_C6, "", ret); + default: + return "invalid"; + } + return ret; +} + +int s2mpg13_meter_onoff(struct s2mpg13_meter *s2mpg13, bool onoff) +{ + int ret; + + if (onoff) { + pr_info("%s: s2mpg13 meter on\n", __func__); + ret = s2mpg13_update_reg(s2mpg13->i2c, S2MPG13_METER_CTRL1, + METER_EN_MASK, METER_EN_MASK); + s2mpg13->meter_en = 1; + } else { + pr_info("%s: s2mpg13 meter off\n", __func__); + ret = s2mpg13_update_reg(s2mpg13->i2c, S2MPG13_METER_CTRL1, 0, + METER_EN_MASK); + s2mpg13->meter_en = 0; + } + + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_meter_onoff); + +int s2mpg13_ext_meter_onoff(struct s2mpg13_meter *s2mpg13, bool onoff) +{ + if (onoff) { + dev_info(s2mpg13->dev, "s2mpg13 external meter on\n"); + return s2mpg13_update_reg(s2mpg13->i2c, S2MPG13_METER_CTRL1, + EXT_METER_EN_MASK, EXT_METER_EN_MASK); + } + dev_info(s2mpg13->dev, "s2mpg13 external meter off\n"); + return s2mpg13_update_reg(s2mpg13->i2c, S2MPG13_METER_CTRL1, 0, + EXT_METER_EN_MASK); +} +EXPORT_SYMBOL_GPL(s2mpg13_ext_meter_onoff); + +int s2mpg13_meter_set_muxsel(struct s2mpg13_meter *s2mpg13, int channel, + s2mpg1x_meter_muxsel m) +{ + int reg = S2MPG13_METER_MUXSEL0; + int ret = -EPERM; + + if (channel < 0 || channel >= S2MPG1X_METER_CHANNEL_MAX) { + dev_err(s2mpg13->dev, "invalid channel number\n"); + return ret; + } + + dev_info(s2mpg13->dev, "CH%d, %s\n", channel, muxsel_to_str(m)); + + reg += channel; + + mutex_lock(&s2mpg13->meter_lock); + ret = s2mpg13_update_reg(s2mpg13->i2c, reg, m, MUXSEL_MASK); + + s2mpg13->chg_mux_sel[channel] = m; + mutex_unlock(&s2mpg13->meter_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(s2mpg13_meter_set_muxsel); + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) +static ssize_t s2mpg13_muxsel_table_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int muxsel_cnt = 0; + int muxsel = BUCK1; + size_t count = 0; + + while (muxsel <= VSEN_C6) { + count += scnprintf(buf + count, PAGE_SIZE - count, + "%s : 0x%x , ", muxsel_to_str(muxsel), muxsel); + if (muxsel == VSEN_C6) + break; + + if (muxsel == BUCKC) + muxsel = BUCKBOOST_10; + else if (muxsel == BUCKBOOST_10) + muxsel = VSEN_P4; + else if (muxsel == VSEN_P6) + muxsel = LDO1; + else if (muxsel == LDO28) + muxsel = VSEN_C4; + else + muxsel++; + + muxsel_cnt++; + if (!(muxsel_cnt % 8)) + count += scnprintf(buf + count, + PAGE_SIZE - count, "\n"); + } + + return count; +} + +static ssize_t s2mpg13_channel_muxsel_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int channel, muxsel; + int ret; + + if (!buf) { + dev_err(s2mpg13->dev, "empty buffer\n"); + return -EINVAL; + } + + ret = sscanf(buf, "%d %x", &channel, &muxsel); + if (ret != 2) { + dev_err(s2mpg13->dev, "input error\n"); + return -EINVAL; + } + + if (channel < 0 || channel >= S2MPG1X_METER_CHANNEL_MAX) { + dev_err(s2mpg13->dev, "wrong channel %d\n", channel); + return -EINVAL; + } + + if ((muxsel >= BUCK1 && muxsel <= BUCKC) || + muxsel == BUCKBOOST_10 || + (muxsel >= VSEN_P4 && muxsel <= VSEN_P6) || + (muxsel >= LDO1 && muxsel <= LDO28) || + (muxsel >= VSEN_C4 && muxsel <= VSEN_C6)) { + s2mpg13_meter_set_muxsel(s2mpg13, channel, muxsel); + } else { + dev_err(s2mpg13->dev, "wrong muxsel 0x%x\n", muxsel); + return -EINVAL; + } + + return size; +} + +static ssize_t s2mpg13_channel_muxsel_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int i; + size_t count = 0; + + mutex_lock(&s2mpg13->meter_lock); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + count += scnprintf(buf + count, PAGE_SIZE - count, "CH%d[%s], ", + i, muxsel_to_str(s2mpg13->chg_mux_sel[i])); + } + + mutex_unlock(&s2mpg13->meter_lock); + return count; +} + +static ssize_t s2mpg13_lpf_current_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + mutex_lock(&s2mpg13->meter_lock); + + s2mpg1x_meter_set_lpf_mode(ID_S2MPG13, s2mpg13->i2c, + S2MPG1X_METER_CURRENT); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG13, s2mpg13->i2c, + s2mpg13->lpf_data); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg13->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), + "(mA)", + s2mpg13->lpf_data[i], + s2mpg13_muxsel_to_current_resolution(muxsel), + 1); + } + mutex_unlock(&s2mpg13->meter_lock); + return count; +} + +static ssize_t s2mpg13_lpf_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + mutex_lock(&s2mpg13->meter_lock); + + s2mpg1x_meter_set_lpf_mode(ID_S2MPG13, s2mpg13->i2c, + S2MPG1X_METER_POWER); + s2mpg1x_meter_read_lpf_data_reg(ID_S2MPG13, s2mpg13->i2c, + s2mpg13->lpf_data); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg13->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mW)", + s2mpg13->lpf_data[i], + s2mpg13_muxsel_to_power_resolution(muxsel), 1); + } + mutex_unlock(&s2mpg13->meter_lock); + return count; +} + +static ssize_t s2mpg13_acc_current_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; + u32 acc_count; + + s2mpg1x_meter_measure_acc(ID_S2MPG13, s2mpg13->i2c, + &s2mpg13->meter_lock, + S2MPG1X_METER_CURRENT, acc_data, + &acc_count, NULL, INT_125HZ); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg13->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mA)", + acc_data[i], + s2mpg13_muxsel_to_current_resolution(muxsel), + acc_count); + } + + return count; +} + +static ssize_t s2mpg13_acc_power_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg13_meter *s2mpg13 = dev_get_drvdata(dev); + int i; + ssize_t count = 0; + + u64 acc_data[S2MPG1X_METER_CHANNEL_MAX]; + u32 acc_count; + + s2mpg1x_meter_measure_acc(ID_S2MPG13, s2mpg13->i2c, + &s2mpg13->meter_lock, + S2MPG1X_METER_POWER, acc_data, + &acc_count, NULL, INT_125HZ); + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_meter_muxsel muxsel = s2mpg13->chg_mux_sel[i]; + + count += s2mpg1x_meter_format_channel(buf, count, i, + muxsel_to_str(muxsel), "(mW)", + acc_data[i], s2mpg13_muxsel_to_power_resolution(muxsel), + acc_count); + } + + return count; +} + +static DEVICE_ATTR_RO(s2mpg13_muxsel_table); +static DEVICE_ATTR_RW(s2mpg13_channel_muxsel); +static DEVICE_ATTR_RO(s2mpg13_lpf_current); +static DEVICE_ATTR_RO(s2mpg13_lpf_power); +static DEVICE_ATTR_RO(s2mpg13_acc_current); +static DEVICE_ATTR_RO(s2mpg13_acc_power); + +int create_s2mpg13_meter_sysfs(struct s2mpg13_meter *s2mpg13) +{ + struct device *s2mpg13_meter_dev = s2mpg13->dev; + int err = -ENODEV; + + s2mpg13_meter_dev = pmic_device_create(s2mpg13, "s2mpg13-meter"); + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_lpf_current); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_lpf_current.attr.name); + } + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_lpf_power); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_lpf_power.attr.name); + } + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_acc_current); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_acc_current.attr.name); + } + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_acc_power); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_acc_power.attr.name); + } + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_muxsel_table); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_muxsel_table.attr.name); + } + + err = device_create_file(s2mpg13_meter_dev, + &dev_attr_s2mpg13_channel_muxsel); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_channel_muxsel.attr.name); + } + + return 0; +} +#endif + +static int s2mpg13_meter_probe(struct platform_device *pdev) +{ + struct s2mpg13_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg13_platform_data *pdata = iodev->pdata; + struct s2mpg13_meter *s2mpg13; + int ret = 0; + + if (!pdata) { + dev_err(pdev->dev.parent, "Platform data not supplied\n"); + return -ENODEV; + } + + s2mpg13 = devm_kzalloc(&pdev->dev, sizeof(struct s2mpg13_meter), + GFP_KERNEL); + if (!s2mpg13) + return -ENOMEM; + + s2mpg13->iodev = iodev; + s2mpg13->i2c = iodev->meter; + s2mpg13->dev = &pdev->dev; + s2mpg13->trim = iodev->trim; + mutex_init(&s2mpg13->meter_lock); + platform_set_drvdata(pdev, s2mpg13); + +#if !IS_ENABLED(CONFIG_ODPM) + + /* initial setting */ + /* set BUCK1S ~ BUCK8S muxsel from CH0 to CH7 */ + /* any necessary settings can be added */ + s2mpg1x_meter_set_int_samp_rate(ID_S2MPG13, s2mpg13->i2c, INT_125HZ); + + s2mpg13_meter_set_muxsel(s2mpg13, 0, BUCK1); + s2mpg13_meter_set_muxsel(s2mpg13, 1, BUCK2); + s2mpg13_meter_set_muxsel(s2mpg13, 2, BUCK3); + s2mpg13_meter_set_muxsel(s2mpg13, 3, BUCK4); + s2mpg13_meter_set_muxsel(s2mpg13, 4, BUCK5); + s2mpg13_meter_set_muxsel(s2mpg13, 5, BUCK6); + s2mpg13_meter_set_muxsel(s2mpg13, 6, BUCK7); + s2mpg13_meter_set_muxsel(s2mpg13, 7, BUCK8); + s2mpg13_meter_set_muxsel(s2mpg13, 8, BUCK9); + s2mpg13_meter_set_muxsel(s2mpg13, 9, BUCK10); + s2mpg13_meter_set_muxsel(s2mpg13, 10, BUCKD); + s2mpg13_meter_set_muxsel(s2mpg13, 11, BUCKA); + + s2mpg13_meter_onoff(s2mpg13, true); + s2mpg13_ext_meter_onoff(s2mpg13, false); + +#else + ret = mfd_add_devices(s2mpg13->dev, -1, s2mpg13_meter_devs, + ARRAY_SIZE(s2mpg13_meter_devs), NULL, 0, NULL); + if (ret < 0) { + mfd_remove_devices(s2mpg13->dev); + return ret; + } +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + /* create sysfs */ + ret = create_s2mpg13_meter_sysfs(s2mpg13); +#endif + + return ret; +} + +static int s2mpg13_meter_remove(struct platform_device *pdev) +{ + struct s2mpg13_meter *s2mpg13 = platform_get_drvdata(pdev); + + s2mpg13_meter_onoff(s2mpg13, false); + s2mpg13_ext_meter_onoff(s2mpg13, false); + +#if IS_ENABLED(CONFIG_ODPM) + mfd_remove_devices(s2mpg13->dev); +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + pmic_device_destroy(s2mpg13->dev->devt); +#endif + return 0; +} + +static void s2mpg13_meter_shutdown(struct platform_device *pdev) +{ + struct s2mpg13_meter *s2mpg13 = platform_get_drvdata(pdev); + + s2mpg13_meter_onoff(s2mpg13, false); + s2mpg13_ext_meter_onoff(s2mpg13, false); +} + +static const struct platform_device_id s2mpg13_meter_id[] = { + { "s2mpg13-meter", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(platform, s2mpg13_meter_id); + +static struct platform_driver s2mpg13_meter_driver = { + .driver = { + .name = "s2mpg13-meter", + .owner = THIS_MODULE, + .suppress_bind_attrs = true, + }, + .probe = s2mpg13_meter_probe, + .remove = s2mpg13_meter_remove, + .shutdown = s2mpg13_meter_shutdown, + .id_table = s2mpg13_meter_id, +}; + +static int __init s2mpg13_meter_init(void) +{ + return platform_driver_register(&s2mpg13_meter_driver); +} + +subsys_initcall(s2mpg13_meter_init); + +static void __exit s2mpg13_meter_exit(void) +{ + platform_driver_unregister(&s2mpg13_meter_driver); +} + +module_exit(s2mpg13_meter_exit); + +/* Module information */ +MODULE_DESCRIPTION("SAMSUNG S2MPG13 Meter Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/s2mpg13-regulator.c b/drivers/regulator/s2mpg13-regulator.c new file mode 100644 index 000000000000..e4a39004af65 --- /dev/null +++ b/drivers/regulator/s2mpg13-regulator.c @@ -0,0 +1,922 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * s2mpg13-regulator.c + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include +#include <../drivers/pinctrl/samsung/pinctrl-samsung.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef TEST_DBG +#define TEST_DBG 0 +#endif + +static struct regulator_desc regulators[S2MPG13_REGULATOR_MAX]; + +static unsigned int s2mpg13_of_map_mode(unsigned int val) +{ + switch (val) { + case SEC_OPMODE_SUSPEND: /* ON in Standby Mode */ + return 0x1; + case SEC_OPMODE_MIF: /* ON in PWREN_MIF mode */ + return 0x2; + case SEC_OPMODE_ON: /* ON in Normal Mode */ + return 0x3; + default: + return 0x3; + } +} + +static int s2m_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + unsigned int val; + int id = rdev_get_id(rdev); + int enable_mask = rdev->desc->enable_mask; + int enable_shift = 0; + + while (1) { + if (enable_mask & 0x1) + break; + + enable_shift++; + enable_mask = enable_mask >> 1; + + if (enable_shift > 7) + dev_err(s2mpg13->dev, "[%d]: error caculating enable_shift!\n", id); + }; + + val = (mode << enable_shift) & rdev->desc->enable_mask; + + s2mpg13->opmode[id] = val; + return 0; +} + +static int s2m_enable(struct regulator_dev *rdev) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + + return s2mpg13_update_reg(s2mpg13->i2c, rdev->desc->enable_reg, + s2mpg13->opmode[rdev_get_id(rdev)], + rdev->desc->enable_mask); +} + +static int s2m_disable(struct regulator_dev *rdev) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + unsigned int val; + + if (rdev->desc->enable_is_inverted) + val = rdev->desc->enable_mask; + else + val = 0; + + return s2mpg13_update_reg(s2mpg13->i2c, rdev->desc->enable_reg, val, + rdev->desc->enable_mask); +} + +static int s2m_is_enabled(struct regulator_dev *rdev) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + int ret; + u8 val; + + ret = s2mpg13_read_reg(s2mpg13->i2c, rdev->desc->enable_reg, &val); + if (ret) + return ret; + + if (rdev->desc->enable_is_inverted) + return (val & rdev->desc->enable_mask) == 0; + return (val & rdev->desc->enable_mask) != 0; +} + +static int s2m_get_voltage_sel(struct regulator_dev *rdev) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + int ret; + u8 val; + + ret = s2mpg13_read_reg(s2mpg13->i2c, rdev->desc->vsel_reg, &val); + if (ret) + return ret; + + val &= rdev->desc->vsel_mask; + + return val; +} + +static int s2m_set_voltage_sel(struct regulator_dev *rdev, unsigned int sel) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + int ret; + + ret = s2mpg13_update_reg(s2mpg13->i2c, rdev->desc->vsel_reg, sel, + rdev->desc->vsel_mask); + if (ret < 0) + goto out; + + if (rdev->desc->apply_bit) + ret = s2mpg13_update_reg(s2mpg13->i2c, rdev->desc->apply_reg, + rdev->desc->apply_bit, + rdev->desc->apply_bit); + return ret; +out: + dev_warn(s2mpg13->dev, "%s: failed to set regulator voltage\n", + rdev->desc->name); + ret = -EINVAL; + return ret; +} + +static int s2m_set_voltage_time_sel(struct regulator_dev *rdev, + unsigned int old_selector, + unsigned int new_selector) +{ + struct s2mpg13_pmic *s2mpg13 = rdev_get_drvdata(rdev); + unsigned int ramp_delay = 0; + int old_volt, new_volt; + + if (rdev->constraints->ramp_delay) + ramp_delay = rdev->constraints->ramp_delay; + else if (rdev->desc->ramp_delay) + ramp_delay = rdev->desc->ramp_delay; + + if (ramp_delay == 0) { + dev_warn(s2mpg13->dev, "%s: ramp_delay not set\n", + rdev->desc->name); + return -EINVAL; + } + + /* validity check */ + if (!rdev->desc->ops->list_voltage) + return -EINVAL; + + old_volt = rdev->desc->ops->list_voltage(rdev, old_selector); + new_volt = rdev->desc->ops->list_voltage(rdev, new_selector); + + if (old_selector < new_selector) + return DIV_ROUND_UP(new_volt - old_volt, ramp_delay); + return DIV_ROUND_UP(old_volt - new_volt, ramp_delay); +} + +static struct regulator_ops s2mpg13_regulator_ops = { + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .is_enabled = s2m_is_enabled, + .enable = s2m_enable, + .disable = s2m_disable, + .get_voltage_sel = s2m_get_voltage_sel, + .set_voltage_sel = s2m_set_voltage_sel, + .set_voltage_time_sel = s2m_set_voltage_time_sel, + .set_mode = s2m_set_mode, +}; + +#define _BUCK(macro) S2MPG13_BUCK##macro +#define _LDO(macro) S2MPG13_LDO##macro +#define _REG(ctrl) S2MPG13_PM##ctrl +#define _TIME(macro) S2MPG13_ENABLE_TIME##macro +#define _MIN(group) S2MPG13_REG_MIN##group +#define _STEP(group) S2MPG13_REG_STEP##group +#define _N_VOLTAGES(num) S2MPG13_REG_N_VOLTAGES_##num +#define _MASK(num) S2MPG13_REG_ENABLE_MASK##num + +#define REG_DESC(_name, _id, g, v, n, e, em, t) \ + { \ + .name = _name, .id = _id, .ops = &s2mpg13_regulator_ops, \ + .type = REGULATOR_VOLTAGE, .owner = THIS_MODULE, \ + .min_uV = _MIN(g), .uV_step = _STEP(g), .n_voltages = n, \ + .vsel_reg = v, .vsel_mask = n - 1, .enable_reg = e, \ + .enable_mask = em, .enable_time = t, \ + .of_map_mode = s2mpg13_of_map_mode \ + } + +static struct regulator_desc regulators[S2MPG13_REGULATOR_MAX] = { + /* name, id, voltage_group, vsel_reg, n_voltages, */ + /* enable_reg, enable_mask, enable_time */ + REG_DESC("LDO1S", _LDO(1), 4, _REG(_L1S_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_1_0), _TIME(_LDO)), + REG_DESC("LDO2S", _LDO(2), 5, _REG(_L2S_CTRL), _N_VOLTAGES(64), + _REG(_L2S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO3S", _LDO(3), 5, _REG(_L3S_CTRL), _N_VOLTAGES(64), + _REG(_L3S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO4S", _LDO(4), 6, _REG(_L4S_CTRL), _N_VOLTAGES(64), + _REG(_L4S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO5S", _LDO(5), 7, _REG(_L5S_CTRL), _N_VOLTAGES(64), + _REG(_L5S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO6S", _LDO(6), 7, _REG(_L6S_CTRL), _N_VOLTAGES(64), + _REG(_L6S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO7S", _LDO(7), 6, _REG(_L7S_CTRL), _N_VOLTAGES(64), + _REG(_L7S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO8S", _LDO(8), 5, _REG(_L8S_CTRL), _N_VOLTAGES(64), + _REG(_L8S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO9S", _LDO(9), 5, _REG(_L9S_CTRL), _N_VOLTAGES(64), + _REG(_L9S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO10S", _LDO(10), 6, _REG(_L10S_CTRL), _N_VOLTAGES(64), + _REG(_L10S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO11S", _LDO(11), 6, _REG(_L11S_CTRL), _N_VOLTAGES(64), + _REG(_L11S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO12S", _LDO(12), 6, _REG(_L12S_CTRL), _N_VOLTAGES(64), + _REG(_L12S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO13S", _LDO(13), 7, _REG(_L13S_CTRL), _N_VOLTAGES(64), + _REG(_L13S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO14S", _LDO(14), 6, _REG(_L14S_CTRL), _N_VOLTAGES(64), + _REG(_L14S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO15S", _LDO(15), 7, _REG(_L15S_CTRL), _N_VOLTAGES(64), + _REG(_L15S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO16S", _LDO(16), 7, _REG(_L16S_CTRL), _N_VOLTAGES(64), + _REG(_L16S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO17S", _LDO(17), 6, _REG(_L17S_CTRL), _N_VOLTAGES(64), + _REG(_L17S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO18S", _LDO(18), 6, _REG(_L18S_CTRL), _N_VOLTAGES(64), + _REG(_L18S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO19S", _LDO(19), 6, _REG(_L19S_CTRL), _N_VOLTAGES(64), + _REG(_L19S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO20S", _LDO(20), 6, _REG(_L20S_CTRL), _N_VOLTAGES(64), + _REG(_L20S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO21S", _LDO(21), 5, _REG(_L21S_CTRL), _N_VOLTAGES(64), + _REG(_L21S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO22S", _LDO(22), 6, _REG(_L22S_CTRL), _N_VOLTAGES(64), + _REG(_L22S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO23S", _LDO(23), 4, _REG(_L23S_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_3_2), _TIME(_LDO)), + REG_DESC("LDO24S", _LDO(24), 4, _REG(_L24S_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_5_4), _TIME(_LDO)), + REG_DESC("LDO25S", _LDO(25), 4, _REG(_L25S_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL1), _MASK(_7), _TIME(_LDO)), + REG_DESC("LDO26S", _LDO(26), 4, _REG(_L26S_CTRL), _N_VOLTAGES(128), + _REG(_LDO_CTRL2), _MASK(_1_0), _TIME(_LDO)), + REG_DESC("LDO27S", _LDO(27), 6, _REG(_L27S_CTRL), _N_VOLTAGES(64), + _REG(_L27S_CTRL), _MASK(_7_6), _TIME(_LDO)), + REG_DESC("LDO28S", _LDO(28), 7, _REG(_L28S_CTRL), _N_VOLTAGES(64), + _REG(_L28S_CTRL), _MASK(_7), _TIME(_LDO)), + REG_DESC("BUCK1S", _BUCK(1), 1, _REG(_B1S_OUT1), _N_VOLTAGES(256), + _REG(_B1S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK2S", _BUCK(2), 1, _REG(_B2S_OUT1), _N_VOLTAGES(256), + _REG(_B2S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK3S", _BUCK(3), 1, _REG(_B3S_OUT1), _N_VOLTAGES(256), + _REG(_B3S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK4S", _BUCK(4), 1, _REG(_B4S_OUT), _N_VOLTAGES(256), + _REG(_B4S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK5S", _BUCK(5), 1, _REG(_B5S_OUT), _N_VOLTAGES(256), + _REG(_B5S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK6S", _BUCK(6), 1, _REG(_B6S_OUT1), _N_VOLTAGES(256), + _REG(_B6S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK7S", _BUCK(7), 2, _REG(_B7S_OUT1), _N_VOLTAGES(256), + _REG(_B7S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK8S", _BUCK(8), 1, _REG(_B8S_OUT1), _N_VOLTAGES(256), + _REG(_B8S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK9S", _BUCK(9), 1, _REG(_B9S_OUT1), _N_VOLTAGES(256), + _REG(_B9S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCK10S", _BUCK(10), 1, _REG(_B10S_OUT), _N_VOLTAGES(256), + _REG(_B10S_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCKD", _BUCK(D), 2, _REG(_BUCKD_OUT), _N_VOLTAGES(256), + _REG(_BUCKD_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCKA", _BUCK(A), 2, _REG(_BUCKA_OUT), _N_VOLTAGES(256), + _REG(_BUCKA_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCKC", _BUCK(C), 1, _REG(_BUCKC_OUT), _N_VOLTAGES(256), + _REG(_BUCKC_CTRL), _MASK(_7_6), _TIME(_BUCK)), + REG_DESC("BUCKBOOST", S2MPG13_BUCKBOOST, 3, _REG(_BB_OUT1), + _N_VOLTAGES(128), _REG(_BB_CTRL), _MASK(_7), _TIME(_BUCK)), +}; + +#if IS_ENABLED(CONFIG_OF) +static int s2mpg13_pmic_dt_parse_pdata(struct s2mpg13_dev *iodev, + struct s2mpg13_platform_data *pdata) +{ + struct device_node *pmic_np, *regulators_np, *reg_np; + struct s2mpg13_regulator_data *rdata; + unsigned int i; + int ret, len; + u32 val; + const u32 *p; + + pmic_np = iodev->dev->of_node; + if (!pmic_np) { + dev_err(iodev->dev, "could not find pmic sub-node\n"); + return -ENODEV; + } + + regulators_np = of_find_node_by_name(pmic_np, "regulators"); + if (!regulators_np) { + dev_err(iodev->dev, "could not find regulators sub-node\n"); + return -EINVAL; + } + + /* count the number of regulators to be supported in pmic */ + pdata->num_regulators = 0; + for_each_child_of_node(regulators_np, reg_np) { + pdata->num_regulators++; + } + + rdata = devm_kzalloc(iodev->dev, sizeof(*rdata) * pdata->num_regulators, + GFP_KERNEL); + if (!rdata) + return -ENOMEM; + + pdata->regulators = rdata; + for_each_child_of_node(regulators_np, reg_np) { + for (i = 0; i < ARRAY_SIZE(regulators); i++) + if (!of_node_cmp(reg_np->name, regulators[i].name)) + break; + + if (i == ARRAY_SIZE(regulators)) { + dev_warn(iodev->dev, + "don't know how to configure regulator %s\n", + reg_np->name); + continue; + } + + rdata->id = i; + rdata->initdata = of_get_regulator_init_data(iodev->dev, reg_np, + ®ulators[i]); + rdata->reg_node = reg_np; + rdata++; + } + + /* parse BUCK OCP Detection information */ + of_property_read_u32(pmic_np, "buck_ocp_ctrl1", &pdata->buck_ocp_ctrl1); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl2", &pdata->buck_ocp_ctrl2); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl3", &pdata->buck_ocp_ctrl3); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl4", &pdata->buck_ocp_ctrl4); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl5", &pdata->buck_ocp_ctrl5); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl6", &pdata->buck_ocp_ctrl6); + + of_property_read_u32(pmic_np, "buck_ocp_ctrl7", &pdata->buck_ocp_ctrl7); + + /* parse OCP_WARN information */ + pdata->b2_ocp_warn_pin = of_get_gpio(pmic_np, 0); + if (pdata->b2_ocp_warn_pin < 0) + dev_err(iodev->dev, "b2_ocp_warn_pin < 0: %d\n", + pdata->b2_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_en", &val); + pdata->b2_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_cnt", &val); + pdata->b2_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_dvs_mask", &val); + pdata->b2_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_ocp_warn_lvl", &val); + pdata->b2_ocp_warn_lvl = ret ? 0 : val; + + /* parse SOFT_OCP_WARN information */ + pdata->b2_soft_ocp_warn_pin = of_get_gpio(pmic_np, 1); + if (pdata->b2_soft_ocp_warn_pin < 0) + dev_err(iodev->dev, "b2_soft_ocp_warn_pin < 0: %d\n", + pdata->b2_soft_ocp_warn_pin); + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_en", &val); + pdata->b2_soft_ocp_warn_en = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_cnt", &val); + pdata->b2_soft_ocp_warn_cnt = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_dvs_mask", &val); + pdata->b2_soft_ocp_warn_dvs_mask = ret ? 0 : val; + + ret = of_property_read_u32(pmic_np, "b2_soft_ocp_warn_lvl", &val); + pdata->b2_soft_ocp_warn_lvl = ret ? 0 : val; + + /* Set SEL_VGPIO (control_sel) */ + p = of_get_property(pmic_np, "sel_vgpio", &len); + if (!p) { + dev_err(iodev->dev, "(ERROR) sel_vgpio isn't parsing\n"); + return -EINVAL; + } + + len = len / sizeof(u32); + if (len != S2MPG13_VGPIO_NUM) { + dev_err(iodev->dev, "(ERROR) sel_vgpio num isn't not equal\n"); + return -EINVAL; + } + + pdata->sel_vgpio = devm_kzalloc(iodev->dev, sizeof(u32) * len, GFP_KERNEL); + if (!(pdata->sel_vgpio)) + return -ENOMEM; + + for (i = 0; i < len; i++) { + ret = of_property_read_u32_index(pmic_np, "sel_vgpio", i, &pdata->sel_vgpio[i]); + if (ret) { + dev_err(iodev->dev, "(ERROR) sel_vgpio%d is empty\n", i + 1); + pdata->sel_vgpio[i] = 0x1FF; + } + } + + return 0; +} +#else +static int s2mpg13_pmic_dt_parse_pdata(struct s2mpg13_dev *iodev, + struct s2mpg13_platform_data *pdata) +{ + return 0; +} +#endif /* CONFIG_OF */ + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + +#define I2C_ADDR_TOP 0x00 +#define I2C_ADDR_PMIC 0x01 +#define I2C_ADDR_METER 0x0A +#define I2C_ADDR_WLWP 0x0B +#define I2C_ADDR_GPIO 0x0C +#define I2C_ADDR_MT_TRIM 0x0E +#define I2C_ADDR_TRIM 0x0F + +static ssize_t s2mpg13_pmic_read_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg13_pmic *s2mpg13 = dev_get_drvdata(dev); + int ret; + u16 reg_addr; + + if (!buf) + return -1; + + ret = kstrtou16(buf, 0, ®_addr); + if (ret < 0) { + dev_err(s2mpg13->dev, "fail to transform i2c address\n"); + return ret; + } + + s2mpg13->read_addr = reg_addr; + + return size; +} + +static ssize_t s2mpg13_pmic_read_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct s2mpg13_pmic *s2mpg13 = dev_get_drvdata(dev); + struct i2c_client *client = NULL; + u16 reg_addr = s2mpg13->read_addr; + u8 val; + int ret; + + switch (reg_addr >> 8) { + case I2C_ADDR_TOP: + client = s2mpg13->iodev->i2c; + break; + case I2C_ADDR_PMIC: + client = s2mpg13->iodev->pmic; + break; + case I2C_ADDR_METER: + client = s2mpg13->iodev->meter; + break; + case I2C_ADDR_WLWP: + client = s2mpg13->iodev->wlwp; + break; + case I2C_ADDR_GPIO: + client = s2mpg13->iodev->gpio; + break; + case I2C_ADDR_MT_TRIM: + client = s2mpg13->iodev->mt_trim; + break; + case I2C_ADDR_TRIM: + client = s2mpg13->iodev->trim; + break; + default: + return -1; + } + + ret = s2mpg13_read_reg(client, reg_addr, &val); + if (ret < 0) { + dev_err(dev, "fail to read i2c address\n"); + return ret; + } + + dev_dbg(dev, "reg(0x%04X) data(0x%02X)\n", reg_addr, val); + + return scnprintf(buf, PAGE_SIZE, "0x%04X: 0x%02X\n", reg_addr, val); +} + +static ssize_t s2mpg13_pmic_write_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct s2mpg13_pmic *s2mpg13 = dev_get_drvdata(dev); + struct i2c_client *client = NULL; + int ret; + u16 reg; + u8 data; + + if (!buf) { + dev_err(s2mpg13->dev, "empty buffer\n"); + return size; + } + + ret = sscanf(buf, "%hx %hhx", ®, &data); + if (ret != 2) { + dev_err(s2mpg13->dev, "input error\n"); + return size; + } + + dev_dbg(s2mpg13->dev, "reg(0x%04X) data(0x%02X)\n", reg, data); + + switch (reg >> 8) { + case I2C_ADDR_TOP: + client = s2mpg13->iodev->i2c; + break; + case I2C_ADDR_PMIC: + client = s2mpg13->iodev->pmic; + break; + case I2C_ADDR_METER: + client = s2mpg13->iodev->meter; + break; + case I2C_ADDR_WLWP: + client = s2mpg13->iodev->wlwp; + break; + case I2C_ADDR_GPIO: + client = s2mpg13->iodev->gpio; + break; + case I2C_ADDR_MT_TRIM: + client = s2mpg13->iodev->mt_trim; + break; + case I2C_ADDR_TRIM: + client = s2mpg13->iodev->trim; + break; + default: + return size; + } + + ret = s2mpg13_write_reg(client, reg, data); + if (ret < 0) + dev_err(s2mpg13->dev, "fail to write i2c addr/data\n"); + + return size; +} + +static ssize_t s2mpg13_pmic_write_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "echo (register addr.) (data) > s2mpg13_write\n"); +} + +static DEVICE_ATTR_RW(s2mpg13_pmic_write); +static DEVICE_ATTR_RW(s2mpg13_pmic_read); + +int create_s2mpg13_pmic_sysfs(struct s2mpg13_pmic *s2mpg13) +{ + struct device *s2mpg13_pmic = s2mpg13->dev; + int err = -ENODEV; + + s2mpg13->read_addr = 0; + + s2mpg13_pmic = pmic_device_create(s2mpg13, "s2mpg13-pmic"); + + err = device_create_file(s2mpg13_pmic, &dev_attr_s2mpg13_pmic_write); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_pmic_write.attr.name); + } + + err = device_create_file(s2mpg13_pmic, &dev_attr_s2mpg13_pmic_read); + if (err) { + dev_err(s2mpg13->dev, + "s2mpg13_sysfs: failed to create device file, %s\n", + dev_attr_s2mpg13_pmic_read.attr.name); + } + + return 0; +} +#endif + +void s2mpg13_ocp_detection_config(struct s2mpg13_pmic *s2mpg13, + struct s2mpg13_platform_data *pdata) +{ + int ret; + + dev_info(s2mpg13->dev, "OCP_CTRL1: 0x%x\n", pdata->buck_ocp_ctrl1); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL1, pdata->buck_ocp_ctrl1); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL1: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL2: 0x%x\n", pdata->buck_ocp_ctrl2); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL2, pdata->buck_ocp_ctrl2); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL2: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL3: 0x%x\n", pdata->buck_ocp_ctrl3); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL3, pdata->buck_ocp_ctrl3); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL3: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL4: 0x%x\n", pdata->buck_ocp_ctrl4); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL4, pdata->buck_ocp_ctrl4); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL4: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL5: 0x%x\n", pdata->buck_ocp_ctrl5); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL5, pdata->buck_ocp_ctrl5); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL5: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL6: 0x%x\n", pdata->buck_ocp_ctrl6); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL6, pdata->buck_ocp_ctrl6); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL6: %d\n", ret); + + dev_info(s2mpg13->dev, "OCP_CTRL7: 0x%x\n", pdata->buck_ocp_ctrl7); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_OCP_CTRL7, pdata->buck_ocp_ctrl7); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting BUCK_OCP_CTRL7: %d\n", ret); +} + +int s2mpg13_ocp_warn(struct s2mpg13_pmic *s2mpg13, + struct s2mpg13_platform_data *pdata) +{ + u8 val; + int ret; + + val = (pdata->b2_ocp_warn_en << S2MPG13_OCP_WARN_EN_SHIFT) | + (pdata->b2_ocp_warn_cnt << S2MPG13_OCP_WARN_CNT_SHIFT) | + (pdata->b2_ocp_warn_dvs_mask << S2MPG13_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b2_ocp_warn_lvl << S2MPG13_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg13->dev, "B2S_OCP_WARN : 0x%x\n", val); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_B2S_OCP_WARN, val); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting b2s_ocp_warn\n"); + + val = (pdata->b2_soft_ocp_warn_en << S2MPG13_OCP_WARN_EN_SHIFT) | + (pdata->b2_soft_ocp_warn_cnt << S2MPG13_OCP_WARN_CNT_SHIFT) | + (pdata->b2_soft_ocp_warn_dvs_mask + << S2MPG13_OCP_WARN_DVS_MASK_SHIFT) | + (pdata->b2_soft_ocp_warn_lvl << S2MPG13_OCP_WARN_LVL_SHIFT); + + dev_info(s2mpg13->dev, "B2S_SOFT_OCP_WARN : 0x%x\n", val); + ret = s2mpg13_write_reg(s2mpg13->i2c, S2MPG13_PM_B2S_SOFT_OCP_WARN, + val); + if (ret) + dev_err(s2mpg13->dev, "i2c write error setting b2s_soft_ocp_warn\n"); + + return ret; +} + +static int s2mpg13_set_sel_vgpio(struct s2mpg13_pmic *s2mpg13, + struct s2mpg13_platform_data *pdata) +{ + int ret, i, cnt = 0; + u8 reg, val; + char prtlog[] = "0x%02hhx[0x%02hhx], "; + char buf[(S2MPG13_VGPIO_NUM * sizeof(prtlog))] = {0, }; + + for (i = 0; i < S2MPG13_VGPIO_NUM; i++) { + reg = S2MPG13_PM_PCTRLSEL1 + i; + val = pdata->sel_vgpio[i]; + + if (val > S2MPG13_VGPIO_MAX_VAL) { + dev_err(s2mpg13->dev, "sel_vgpio%d exceed the value\n", i + 1); + goto err; + } + + ret = s2mpg13_write_reg(s2mpg13->i2c, reg, val); + if (ret) { + dev_err(s2mpg13->dev, "sel_vgpio%d write error\n", i + 1); + goto err; + } + + cnt += snprintf(buf + cnt, sizeof(buf) - cnt, prtlog, reg, val); + } + + dev_dbg(s2mpg13->dev, "vgpio: %s\n", buf); + + return 0; +err: + return -1; +} + +int s2mpg13_oi_function(struct s2mpg13_pmic *s2mpg13) +{ + int ret = 0; + /* add OI configuration code if necessary */ + + /* OI function enable */ + + /* OI power down disable */ + + /* OI detection time window : 500us, OI comp. output count : 50 times */ + + return ret; +} + +static int s2mpg13_pmic_probe(struct platform_device *pdev) +{ + struct s2mpg13_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg13_platform_data *pdata = iodev->pdata; + struct regulator_config config = {}; + struct s2mpg13_pmic *s2mpg13; + int i, ret; + + if (iodev->dev->of_node) { + ret = s2mpg13_pmic_dt_parse_pdata(iodev, pdata); + if (ret) + return ret; + } + + if (!pdata) { + dev_err(pdev->dev.parent, "Platform data not supplied\n"); + return -ENODEV; + } + + s2mpg13 = devm_kzalloc(&pdev->dev, sizeof(struct s2mpg13_pmic), + GFP_KERNEL); + if (!s2mpg13) + return -ENOMEM; + + s2mpg13->rdev = devm_kzalloc(&pdev->dev, + sizeof(struct regulator_dev *) * + S2MPG13_REGULATOR_MAX, + GFP_KERNEL); + if (!s2mpg13->rdev) + return -ENOMEM; + + s2mpg13->opmode = + devm_kzalloc(&pdev->dev, + sizeof(unsigned int) * S2MPG13_REGULATOR_MAX, + GFP_KERNEL); + if (!s2mpg13->opmode) + return -ENOMEM; + + s2mpg13->iodev = iodev; + s2mpg13->i2c = iodev->pmic; + s2mpg13->dev = &pdev->dev; + + mutex_init(&s2mpg13->lock); + platform_set_drvdata(pdev, s2mpg13); + + /* setting for LDOs with exceptional register structure */ + + for (i = 0; i < pdata->num_regulators; i++) { + int id = pdata->regulators[i].id; + + config.dev = &pdev->dev; + config.init_data = pdata->regulators[i].initdata; + config.driver_data = s2mpg13; + config.of_node = pdata->regulators[i].reg_node; + s2mpg13->opmode[id] = regulators[id].enable_mask; + + s2mpg13->rdev[i] = regulator_register(®ulators[id], &config); + if (IS_ERR(s2mpg13->rdev[i])) { + ret = PTR_ERR(s2mpg13->rdev[i]); + dev_err(&pdev->dev, "regulator init failed for %d\n", i); + s2mpg13->rdev[i] = NULL; + goto err; + } + } + + s2mpg13->num_regulators = pdata->num_regulators; + + s2mpg13_ocp_detection_config(s2mpg13, pdata); + ret = s2mpg13_ocp_warn(s2mpg13, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg13_ocp_warn fail\n"); + goto err; + } + + ret = s2mpg13_set_sel_vgpio(s2mpg13, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg13_set_sel_vgpio fail\n"); + goto err; + } +#if IS_ENABLED(TEST_DBG) + ret = s2mpg13_oi_function(s2mpg13); + if (ret < 0) { + dev_err(&pdev->dev, "s2mpg13_oi_function fail\n"); + goto err; + } + +#endif + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + /* create sysfs */ + ret = create_s2mpg13_pmic_sysfs(s2mpg13); + if (ret < 0) + return ret; +#endif + + return 0; +err: + for (i = 0; i < S2MPG13_REGULATOR_MAX; i++) + regulator_unregister(s2mpg13->rdev[i]); + + return ret; +} + +static int s2mpg13_pmic_remove(struct platform_device *pdev) +{ + struct s2mpg13_pmic *s2mpg13 = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < S2MPG13_REGULATOR_MAX; i++) + regulator_unregister(s2mpg13->rdev[i]); + +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + pmic_device_destroy(s2mpg13->dev->devt); +#endif + return 0; +} + +static void s2mpg13_pmic_shutdown(struct platform_device *pdev) +{ +} + +#if IS_ENABLED(CONFIG_PM) +static int s2mpg13_pmic_suspend(struct device *dev) +{ +#if IS_ENABLED(TEST_DBG) + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg13_pmic *s2mpg13 = platform_get_drvdata(pdev); +#endif + int ret = 0; + + return ret; +} + +static int s2mpg13_pmic_resume(struct device *dev) +{ +#if IS_ENABLED(TEST_DBG) + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg13_pmic *s2mpg13 = platform_get_drvdata(pdev); +#endif + int ret = 0; + + return ret; +} +#else +#define s2mpg13_pmic_suspend NULL +#define s2mpg13_pmic_resume NULL +#endif /* CONFIG_PM */ + +const struct dev_pm_ops s2mpg13_pmic_pm = { + .suspend = s2mpg13_pmic_suspend, + .resume = s2mpg13_pmic_resume, +}; + +static const struct platform_device_id s2mpg13_pmic_id[] = { + { "s2mpg13-regulator", 0 }, + {}, +}; + +MODULE_DEVICE_TABLE(platform, s2mpg13_pmic_id); + +static struct platform_driver s2mpg13_pmic_driver = { + .driver = { + .name = "s2mpg13-regulator", + .owner = THIS_MODULE, +#if IS_ENABLED(CONFIG_PM) + .pm = &s2mpg13_pmic_pm, +#endif + .suppress_bind_attrs = true, + }, + .probe = s2mpg13_pmic_probe, + .remove = s2mpg13_pmic_remove, + .shutdown = s2mpg13_pmic_shutdown, + .id_table = s2mpg13_pmic_id, +}; + +static int __init s2mpg13_pmic_init(void) +{ + return platform_driver_register(&s2mpg13_pmic_driver); +} +subsys_initcall(s2mpg13_pmic_init); + +static void __exit s2mpg13_pmic_exit(void) +{ + platform_driver_unregister(&s2mpg13_pmic_driver); +} +module_exit(s2mpg13_pmic_exit); + +/* Module information */ +MODULE_AUTHOR("Sangbeom Kim "); +MODULE_DESCRIPTION("SAMSUNG S2MPG13 Regulator Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/regulator/slg51002-regulator.c b/drivers/regulator/slg51002-regulator.c new file mode 100644 index 000000000000..3227cf115366 --- /dev/null +++ b/drivers/regulator/slg51002-regulator.c @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * slg51002 regulator driver + * + * Copyright (C) 2021 Google, LLC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SLG51002_SCTL_EVT 7 +#define SLG51002_MAX_EVT_REGISTER 8 + +struct slg51002_evt_sta { + unsigned int ereg; + unsigned int sreg; +}; + +static const struct slg51002_evt_sta es_reg[SLG51002_MAX_EVT_REGISTER] = { + {SLG51002_LDO1_EVENT, SLG51002_LDO1_STATUS}, + {SLG51002_LDO2_EVENT, SLG51002_LDO2_STATUS}, + {SLG51002_LDO3_EVENT, SLG51002_LDO3_STATUS}, + {SLG51002_LDO4_EVENT, SLG51002_LDO4_STATUS}, + {SLG51002_LDO5_EVENT, SLG51002_LDO5_STATUS}, + {SLG51002_LDO6_EVENT, SLG51002_LDO6_STATUS}, + {SLG51002_LDO7_EVENT, SLG51002_LDO7_STATUS}, + {SLG51002_SYSCTL_EVENT, SLG51002_SYSCTL_STATUS}, +}; + +static int slg51002_get_status(struct regulator_dev *rdev) +{ + struct slg51002_dev *chip = rdev_get_drvdata(rdev); + int ret, id = rdev_get_id(rdev); + unsigned int status; + + ret = regulator_is_enabled_regmap(rdev); + if (ret < 0) { + dev_err(chip->dev, "Failed to read enable register(%d)\n", ret); + return ret; + } + + if (!ret) + return REGULATOR_STATUS_OFF; + + ret = regmap_read(chip->regmap, es_reg[id].sreg, &status); + if (ret < 0) { + dev_err(chip->dev, "Failed to read status register(%d)\n", ret); + return ret; + } + + if (!(status & SLG51002_STA_ILIM_FLAG_MASK) && + (status & SLG51002_STA_VOUT_OK_FLAG_MASK)) { + if (rdev->desc->n_voltages == 0 && + (id == SLG51002_REGULATOR_LDO5 || + id == SLG51002_REGULATOR_LDO6)) + return REGULATOR_STATUS_BYPASS; + else + return REGULATOR_STATUS_ON; + } + + return REGULATOR_STATUS_ERROR; +} +static int slg51002_regulator_enable_regmap(struct regulator_dev *rdev) +{ + struct slg51002_dev *chip = rdev_get_drvdata(rdev); + int ret; + if (chip->gpio_op_on_sw_test_mode && rdev->desc->id >= SLG51002_REGULATOR_GPIO1) { + if (chip->enter_sw_test_mode) + chip->enter_sw_test_mode(chip->regmap); + + ret = regulator_enable_regmap(rdev); + + if (chip->exit_sw_test_mode) + chip->exit_sw_test_mode(chip->regmap); + + } else { + ret = regulator_enable_regmap(rdev); + } + return ret; +} + +static int slg51002_regulator_disable_regmap(struct regulator_dev *rdev) +{ + struct slg51002_dev *chip = rdev_get_drvdata(rdev); + int ret; + if (chip->gpio_op_on_sw_test_mode && rdev->desc->id >= SLG51002_REGULATOR_GPIO1) { + if (chip->enter_sw_test_mode) + chip->enter_sw_test_mode(chip->regmap); + + ret = regulator_disable_regmap(rdev); + + if (chip->exit_sw_test_mode) + chip->exit_sw_test_mode(chip->regmap); + + } else { + ret = regulator_disable_regmap(rdev); + } + return ret; +} + +static int slg51002_regulator_set_voltage_sel_regmap(struct regulator_dev *rdev, unsigned int sel) +{ + struct slg51002_dev *chip = rdev_get_drvdata(rdev); + + if (chip->op_mode == SLG51002_OP_MODE_CONTROL_REG || + rdev->desc->id >= SLG51002_REGULATOR_GPIO1) + return 0; + + return regulator_set_voltage_sel_regmap(rdev, sel); +} + +static const struct regulator_ops slg51002_regl_ops = { + .enable = slg51002_regulator_enable_regmap, + .disable = slg51002_regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = slg51002_regulator_set_voltage_sel_regmap, + .get_status = slg51002_get_status, +}; + +static const struct regulator_ops slg51002_switch_ops = { + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = slg51002_get_status, +}; + +static int slg51002_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + struct gpio_desc *ena_gpiod; + + ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), "enable", 0, + GPIOD_OUT_LOW | + GPIOD_FLAGS_BIT_NONEXCLUSIVE, + "gpio-en-ldo"); + if (!IS_ERR(ena_gpiod)) + config->ena_gpiod = ena_gpiod; + + return 0; +} + +#define SLG51002_REGL_DESC(_id, _name, _s_name, _min, _step) \ + [SLG51002_REGULATOR_##_id] = { \ + .name = #_name, \ + .supply_name = _s_name, \ + .id = SLG51002_REGULATOR_##_id, \ + .of_match = of_match_ptr(#_name), \ + .of_parse_cb = slg51002_of_parse_cb, \ + .ops = &slg51002_regl_ops, \ + .regulators_node = of_match_ptr("regulators"), \ + .n_voltages = 256, \ + .min_uV = _min, \ + .uV_step = _step, \ + .linear_min_sel = 0, \ + .vsel_mask = SLG51002_VSEL_MASK, \ + .vsel_reg = SLG51002_##_id##_VSEL, \ + .enable_reg = SLG51002_SYSCTL_MATRIX_CONF_A, \ + .enable_mask = BIT(SLG51002_REGULATOR_##_id), \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + } + +#define SLG51002_GPIO_DESC(_id, _name, _s_name, _min, _step) \ + [SLG51002_REGULATOR_##_id] = { \ + .name = #_name, \ + .supply_name = _s_name, \ + .id = SLG51002_REGULATOR_##_id, \ + .of_match = of_match_ptr(#_name), \ + .of_parse_cb = slg51002_of_parse_cb, \ + .ops = &slg51002_regl_ops, \ + .regulators_node = of_match_ptr("regulators"), \ + .n_voltages = 256, \ + .min_uV = _min, \ + .uV_step = _step, \ + .linear_min_sel = 0, \ + .vsel_mask = SLG51002_VSEL_MASK, \ + .vsel_reg = SLG51000_LDO_DUMMY_VSEL, \ + .enable_reg = _id##_CTRL, \ + .enable_mask = BIT(0), \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + } + +static struct regulator_desc regls_desc[SLG51002_MAX_REGULATORS] = { + SLG51002_REGL_DESC(LDO1, ldo1, "vin1_2", 1200000, 10000), + SLG51002_REGL_DESC(LDO2, ldo2, "vin1_2", 1200000, 10000), + SLG51002_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000), + SLG51002_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000), + SLG51002_REGL_DESC(LDO5, ldo5, "vin5", 1200000, 10000), + SLG51002_REGL_DESC(LDO6, ldo6, "vin6", 400000, 5000), + SLG51002_REGL_DESC(LDO7, ldo7, "vin7", 400000, 5000), + SLG51002_REGL_DESC(LDO8, ldo8, "vin8", 400000, 5000), + SLG51002_GPIO_DESC(GPIO1, gpio1, NULL, 400000, 5000), + SLG51002_GPIO_DESC(GPIO2, gpio2, NULL, 400000, 5000), + SLG51002_GPIO_DESC(GPIO3, gpio3, NULL, 400000, 5000), + SLG51002_GPIO_DESC(GPIO4, gpio4, NULL, 400000, 5000), +}; + +static int slg51002_regulator_register(struct slg51002_dev *chip) +{ + struct regulator_config config = { }; + struct regulator_desc *rdesc; + u8 vsel_range[2]; + int id, ret = 0; + const unsigned int min_regs[SLG51002_MAX_REGULATORS] = { + SLG51002_LDO1_MINV, SLG51002_LDO2_MINV, SLG51002_LDO3_MINV, + SLG51002_LDO4_MINV, SLG51002_LDO5_MINV, SLG51002_LDO6_MINV, + SLG51002_LDO7_MINV, SLG51002_LDO8_MINV, + SLG51000_LDO_DUMMY_MINV, SLG51000_LDO_DUMMY_MINV, + SLG51000_LDO_DUMMY_MINV, SLG51000_LDO_DUMMY_MINV, + }; + + for (id = 0; id < SLG51002_MAX_REGULATORS; id++) { + chip->rdesc[id] = ®ls_desc[id]; + rdesc = chip->rdesc[id]; + config.regmap = chip->regmap; + config.dev = chip->dev; + config.driver_data = chip; + + ret = regmap_bulk_read(chip->regmap, min_regs[id], + vsel_range, ARRAY_SIZE(vsel_range)); + if (ret < 0) { + dev_err(chip->dev, + "Failed to read the MIN register\n"); + return ret; + } + + rdesc->linear_min_sel = vsel_range[0]; + rdesc->n_voltages = vsel_range[1] + 1; + rdesc->min_uV = rdesc->min_uV + + (vsel_range[0] * rdesc->uV_step); + + chip->rdev[id] = devm_regulator_register( + chip->dev, rdesc, &config); + if (IS_ERR(chip->rdev[id])) { + ret = PTR_ERR(chip->rdev[id]); + dev_err(chip->dev, + "Failed to register regulator(%s):%d\n", + chip->rdesc[id]->name, ret); + return ret; + } + } + + return 0; +} + +static void slg51002_work_func(struct work_struct *work) +{ + struct slg51002_dev *chip = + container_of(work, struct slg51002_dev, slg51002_work); + struct regmap *regmap = chip->regmap; + enum { R0 = 0, R1, R2, REG_MAX }; + u8 evt[SLG51002_MAX_EVT_REGISTER][REG_MAX]; + int ret, i; + unsigned int evt_otp, mask_otp; + + /* Read event[R0], status[R1] and mask[R2] register */ + for (i = 0; i < SLG51002_MAX_EVT_REGISTER; i++) { + ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX); + if (ret < 0) { + dev_err(chip->dev, + "Failed to read event registers(%d)\n", ret); + return; + } + } + + ret = regmap_read(regmap, SLG51002_OTP_EVENT, &evt_otp); + if (ret < 0) { + dev_err(chip->dev, + "Failed to read otp event registers(%d)\n", ret); + return; + } + + ret = regmap_read(regmap, SLG51002_OTP_IRQ_MASK, &mask_otp); + if (ret < 0) { + dev_err(chip->dev, + "Failed to read otp mask register(%d)\n", ret); + return; + } + + if ((evt_otp & SLG51002_EVT_CRC_MASK) && + !(mask_otp & SLG51002_IRQ_CRC_MASK)) + dev_info(chip->dev, + "OTP has been read or OTP crc is not zero\n"); + + for (i = 0; i < SLG51002_MAX_REGULATORS; i++) { + if (!(evt[i][R2] & SLG51002_IRQ_ILIM_FLAG_MASK) && + (evt[i][R0] & SLG51002_EVT_ILIM_FLAG_MASK)) { + regulator_notifier_call_chain(chip->rdev[i], + REGULATOR_EVENT_OVER_CURRENT, NULL); + + if (evt[i][R1] & SLG51002_STA_ILIM_FLAG_MASK) + dev_warn(chip->dev, + "Over-current limit(ldo%d)\n", i + 1); + } + } + + if (!(evt[SLG51002_SCTL_EVT][R2] & SLG51002_IRQ_HIGH_TEMP_WARN_MASK) && + (evt[SLG51002_SCTL_EVT][R0] & SLG51002_EVT_HIGH_TEMP_WARN_MASK)) { + for (i = 0; i < SLG51002_MAX_REGULATORS; i++) { + if (!(evt[i][R1] & SLG51002_STA_ILIM_FLAG_MASK) && + (evt[i][R1] & SLG51002_STA_VOUT_OK_FLAG_MASK)) { + regulator_notifier_call_chain(chip->rdev[i], + REGULATOR_EVENT_OVER_TEMP, NULL); + } + } + if (evt[SLG51002_SCTL_EVT][R1] & + SLG51002_STA_HIGH_TEMP_WARN_MASK) + dev_warn(chip->dev, "High temperature warning!\n"); + } +} + +static irqreturn_t slg51002_irq_handler(int irq, void *data) +{ + struct slg51002_dev *chip = data; + + if (chip == NULL) + return IRQ_NONE; + + queue_work(chip->slg51002_wq, &chip->slg51002_work); + + return IRQ_HANDLED; +} + +static int slg51002_regulator_probe(struct platform_device *pdev) +{ + struct slg51002_dev *chip = dev_get_drvdata(pdev->dev.parent); + int ret; + + if (chip->op_mode != SLG51002_OP_MODE_LDO_ONLY && + chip->op_mode != SLG51002_OP_MODE_LDO_GPIO && + chip->op_mode != SLG51002_OP_MODE_CONTROL_REG) + return -ENODEV; + + ret = slg51002_regulator_register(chip); + if (ret < 0) { + dev_err(chip->dev, "Failed to init regulator(%d)\n", ret); + return ret; + } + + if (chip->chip_irq) { + ret = devm_request_threaded_irq( + chip->dev, chip->chip_irq, NULL, slg51002_irq_handler, + (IRQF_TRIGGER_HIGH | IRQF_ONESHOT), "slg51002-irq", + chip); + if (ret != 0) { + dev_err(chip->dev, "Failed to request IRQ: %d\n", + chip->chip_irq); + return ret; + } + } else + dev_dbg(chip->dev, "No IRQ configured\n"); + + chip->slg51002_wq = create_workqueue("slg51002wq"); + if (!chip->slg51002_wq) + return -ENOMEM; + INIT_WORK(&chip->slg51002_work, slg51002_work_func); + + return ret; +} + +static int slg51002_regulator_remove(struct platform_device *pdev) +{ + struct slg51002_dev *chip = dev_get_drvdata(pdev->dev.parent); + + flush_workqueue(chip->slg51002_wq); + destroy_workqueue(chip->slg51002_wq); + + return 0; +} + +static const struct platform_device_id slg51002_regulator_id[] = { + {"slg51002-regulator", 0}, + {}, +}; +MODULE_DEVICE_TABLE(platform, slg51002_regulator_id); + +static struct platform_driver slg51002_regulator_driver = { + .driver = { + .name = "slg51002-regulator", + }, + .probe = slg51002_regulator_probe, + .remove = slg51002_regulator_remove, + .id_table = slg51002_regulator_id, +}; + +static int __init slg51002_regulator_init(void) +{ + return platform_driver_register(&slg51002_regulator_driver); +} +subsys_initcall(slg51002_regulator_init); + +static void __exit slg51002_regulator_exit(void) +{ + platform_driver_unregister(&slg51002_regulator_driver); +} +module_exit(slg51002_regulator_exit); + +MODULE_DESCRIPTION("SLG51002 regulator driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index c1f8421b8675..53bbe6dfcf94 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -710,6 +710,15 @@ config RTC_DRV_S2MPG10 This driver can also be built as a module. If so, the module will be called rtc-s2mpg10. +config RTC_DRV_S2MPG12 + tristate "Samsung PMIC S2MPG12 RTC" + depends on MFD_S2MPG12 + help + If you say yes here you will get support for the + RTC of Samsung PMIC series. + This driver can also be built as a module. If so, the module + will be called rtc-s2mpg12. + config RTC_DRV_SD3078 tristate "ZXW Shenzhen whwave SD3078" select REGMAP_I2C diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 6e183d589c21..33daf5569bb5 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -149,6 +149,7 @@ obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o obj-$(CONFIG_RTC_DRV_S2MPG10) += rtc-s2mpg10.o +obj-$(CONFIG_RTC_DRV_S2MPG12) += rtc-s2mpg12.o obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o obj-$(CONFIG_RTC_DRV_S3C) += rtc-s3c.o obj-$(CONFIG_RTC_DRV_S5M) += rtc-s5m.o diff --git a/drivers/rtc/rtc-s2mpg12.c b/drivers/rtc/rtc-s2mpg12.c new file mode 100644 index 000000000000..f1d009955c46 --- /dev/null +++ b/drivers/rtc/rtc-s2mpg12.c @@ -0,0 +1,793 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * rtc-s2mpg12.c + * + * Copyright (c) 2017 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/*#define CONFIG_WEEKDAY_ALARM_ENABLE*/ + +static void s2m_data_to_tm(u8 *data, struct rtc_time *tm) +{ + tm->tm_sec = data[RTC_SEC] & 0x7f; + tm->tm_min = data[RTC_MIN] & 0x7f; + tm->tm_hour = data[RTC_HOUR] & 0x1f; + tm->tm_wday = __fls(data[RTC_WEEKDAY] & 0x7f); + tm->tm_mday = data[RTC_DATE] & 0x1f; + tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1; + tm->tm_year = (data[RTC_YEAR] & 0x7f) + 100; + tm->tm_yday = 0; + tm->tm_isdst = 0; +} + +static int s2m_tm_to_data(struct rtc_time *tm, u8 *data) +{ + data[RTC_SEC] = tm->tm_sec; + data[RTC_MIN] = tm->tm_min; + + if (tm->tm_hour >= 12) + data[RTC_HOUR] = tm->tm_hour | BIT(HOUR_PM_SHIFT); + else + data[RTC_HOUR] = tm->tm_hour; + + data[RTC_WEEKDAY] = BIT(tm->tm_wday); + data[RTC_DATE] = tm->tm_mday; + data[RTC_MONTH] = tm->tm_mon + 1; + data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0; + + if (tm->tm_year < 100) { + pr_warn("SEC RTC cannot handle the year %d\n", + 1900 + tm->tm_year); + return -EINVAL; + } + return 0; +} + +static int s2m_rtc_update(struct s2m_rtc_info *info, enum S2M_RTC_OP op) +{ + u8 data, reg; + int ret; + + if (!info || !info->iodev) { + pr_err("%s: Invalid argument\n", __func__); + return -EINVAL; + } + + ret = s2mpg12_read_reg(info->i2c, S2MPG12_RTC_UPDATE, &data); + if (ret < 0) { + dev_err(info->dev, "fail to read update reg(%d,%u)\n", + ret, data); + return ret; + } + + data |= info->update_reg; + + switch (op) { + case S2M_RTC_READ: + reg = BIT(RTC_RUDR_SHIFT); + break; + case S2M_RTC_WRITE_TIME: + reg = BIT(RTC_WUDR_SHIFT); + break; + case S2M_RTC_WRITE_ALARM: + reg = BIT(RTC_AUDR_SHIFT); + break; + default: + dev_err(info->dev, "invalid op(%d)\n", op); + return -EINVAL; + } + + data &= ~reg; + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_UPDATE, data); + if (ret < 0) { + dev_err(info->dev, "fail to write update reg(%d,%u)\n", + ret, data); + return ret; + } + + usleep_range(50, 51); + + data |= reg; + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_UPDATE, data); + if (ret < 0) + dev_err(info->dev, "fail to write update reg(%d,%u)\n", + ret, data); + else + usleep_range(1000, 1000); + + return ret; +} + +static int s2m_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct s2m_rtc_info *info = dev_get_drvdata(dev); + u8 data[NR_RTC_CNT_REGS]; + int ret; + + mutex_lock(&info->lock); + ret = s2m_rtc_update(info, S2M_RTC_READ); + if (ret < 0) + goto out; + + ret = s2mpg12_bulk_read(info->i2c, S2MPG12_RTC_SEC, NR_RTC_CNT_REGS, + data); + if (ret < 0) { + dev_err(info->dev, "%s: fail to read time reg(%d)\n", __func__, + ret); + goto out; + } + + dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d(0x%02x)%s\n", + __func__, data[RTC_YEAR] + 2000, data[RTC_MONTH], + data[RTC_DATE], data[RTC_HOUR] & 0x1f, data[RTC_MIN], + data[RTC_SEC], data[RTC_WEEKDAY], + data[RTC_HOUR] & BIT(HOUR_PM_SHIFT) ? "PM" : "AM"); + + s2m_data_to_tm(data, tm); + ret = rtc_valid_tm(tm); +out: + mutex_unlock(&info->lock); + return ret; +} + +static int s2m_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct s2m_rtc_info *info = dev_get_drvdata(dev); + u8 data[NR_RTC_CNT_REGS]; + int ret; + + ret = s2m_tm_to_data(tm, data); + if (ret < 0) + return ret; + + dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d(0x%02x)%s\n", + __func__, data[RTC_YEAR] + 2000, data[RTC_MONTH], + data[RTC_DATE], data[RTC_HOUR] & 0x1f, data[RTC_MIN], + data[RTC_SEC], data[RTC_WEEKDAY], + data[RTC_HOUR] & BIT(HOUR_PM_SHIFT) ? "PM" : "AM"); + + mutex_lock(&info->lock); + ret = s2mpg12_bulk_write(info->i2c, S2MPG12_RTC_SEC, NR_RTC_CNT_REGS, + data); + if (ret < 0) { + dev_err(info->dev, "fail to write time reg(%d)\n", ret); + goto out; + } + + ret = s2m_rtc_update(info, S2M_RTC_WRITE_TIME); +out: + mutex_unlock(&info->lock); + return ret; +} + +static int s2m_rtc_check_rtc_time(struct s2m_rtc_info *info) +{ + u8 data[NR_RTC_CNT_REGS]; + struct rtc_time tm; + struct timespec64 sys_time; + time64_t rtc_time; + int ret; + + /* Read RTC TIME */ + ret = s2m_rtc_update(info, S2M_RTC_READ); + if (ret < 0) + goto out; + + ret = s2mpg12_bulk_read(info->i2c, S2MPG12_RTC_SEC, NR_RTC_CNT_REGS, + data); + if (ret < 0) { + dev_err(info->dev, "fail to read time reg(%d)\n", ret); + goto out; + } + + /* Get system time */ + ktime_get_real_ts64(&sys_time); + + /* Convert RTC TIME to seconds since 01-01-1970 00:00:00. */ + s2m_data_to_tm(data, &tm); + rtc_time = rtc_tm_to_time64(&tm); + + if (abs(rtc_time - sys_time.tv_sec) > 2) { + /* Set RTC TIME */ + rtc_time64_to_tm(sys_time.tv_sec, &tm); + ret = s2m_tm_to_data(&tm, data); + if (ret < 0) { + dev_err(info->dev, "fail to tm_to_data(%d)\n", ret); + goto out; + } + + ret = s2mpg12_bulk_write(info->i2c, S2MPG12_RTC_SEC, + NR_RTC_CNT_REGS, data); + if (ret < 0) { + dev_err(info->dev, "fail to write time reg(%d)\n", ret); + goto out; + } + + ret = s2m_rtc_update(info, S2M_RTC_WRITE_TIME); + + dev_warn(info->dev, + "adjust RTC TIME: sys_time: %llu, rtc_time: %lld\n", + sys_time.tv_sec, rtc_time); + + dev_info(info->dev, + "%s: %d-%02d-%02d %02d:%02d:%02d(0x%02x)%s\n", + __func__, data[RTC_YEAR] + 2000, data[RTC_MONTH], + data[RTC_DATE], data[RTC_HOUR] & 0x1f, data[RTC_MIN], + data[RTC_SEC], data[RTC_WEEKDAY], + data[RTC_HOUR] & BIT(HOUR_PM_SHIFT) ? "PM" : "AM"); + } +out: + return ret; +} + +static int s2m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct s2m_rtc_info *info = dev_get_drvdata(dev); + u8 data[NR_RTC_CNT_REGS]; + u8 reg, val; + int ret; + + mutex_lock(&info->lock); + ret = s2m_rtc_update(info, S2M_RTC_READ); + if (ret < 0) + goto out; + + ret = s2mpg12_bulk_read(info->i2c, S2MPG12_RTC_A0SEC, NR_RTC_CNT_REGS, + data); + if (ret < 0) { + dev_err(info->dev, "%d fail to read alarm reg(%d)\n", __LINE__, + ret); + goto out; + } + + s2m_data_to_tm(data, &alrm->time); + + dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d(%d)\n", __func__, + alrm->time.tm_year + 1900, alrm->time.tm_mon + 1, + alrm->time.tm_mday, alrm->time.tm_hour, alrm->time.tm_min, + alrm->time.tm_sec, alrm->time.tm_wday); + + alrm->enabled = info->alarm_enabled; + alrm->pending = 0; + + switch (info->iodev->device_type) { + case S2MPG12X: + reg = S2MPG12_PM_STATUS2; + break; + default: + /* If this happens the core function has a problem */ + WARN_ON(1); + ret = -ENXIO; + goto out; + } + + ret = s2mpg12_read_reg(info->pmic_i2c, reg, &val); /* i2c for PM */ + if (ret < 0) { + dev_err(info->dev, "%d fail to read STATUS2 reg(%d)\n", __LINE__, + ret); + goto out; + } + + if (val & BIT(RTCA0E_SHIFT)) + alrm->pending = 1; +out: + mutex_unlock(&info->lock); + return ret; +} + +static int s2m_rtc_set_alarm_enable(struct s2m_rtc_info *info, bool enabled) +{ + if (!info->use_irq) + return -EPERM; + + if (enabled && !info->alarm_enabled) { + info->alarm_enabled = true; + enable_irq(info->alarm0_irq); + } else if (!enabled && info->alarm_enabled) { + info->alarm_enabled = false; + disable_irq(info->alarm0_irq); + } + return 0; +} + +static int s2m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct s2m_rtc_info *info = dev_get_drvdata(dev); + u8 data[NR_RTC_CNT_REGS]; + int ret, i; + + mutex_lock(&info->lock); + ret = s2m_tm_to_data(&alrm->time, data); + if (ret < 0) + goto out; + + dev_info(info->dev, "%s: %d-%02d-%02d %02d:%02d:%02d(0x%02x)%s\n", + __func__, data[RTC_YEAR] + 2000, data[RTC_MONTH], + data[RTC_DATE], data[RTC_HOUR] & 0x1f, data[RTC_MIN], + data[RTC_SEC], data[RTC_WEEKDAY], + data[RTC_HOUR] & BIT(HOUR_PM_SHIFT) ? "PM" : "AM"); + + if (info->alarm_check) { + for (i = 0; i < NR_RTC_CNT_REGS; i++) + data[i] &= ~BIT(ALARM_ENABLE_SHIFT); + + ret = s2mpg12_bulk_write(info->i2c, S2MPG12_RTC_A0SEC, + NR_RTC_CNT_REGS, data); + if (ret < 0) { + dev_err(info->dev, "fail to disable alarm reg(%d)\n", ret); + goto out; + } + + ret = s2m_rtc_update(info, S2M_RTC_WRITE_ALARM); + if (ret < 0) + goto out; + } + + for (i = 0; i < NR_RTC_CNT_REGS; i++) + data[i] |= BIT(ALARM_ENABLE_SHIFT); + + ret = s2mpg12_bulk_write(info->i2c, S2MPG12_RTC_A0SEC, NR_RTC_CNT_REGS, + data); + if (ret < 0) { + dev_err(info->dev, "fail to write alarm reg(%d)\n", ret); + goto out; + } + + ret = s2m_rtc_update(info, S2M_RTC_WRITE_ALARM); + if (ret < 0) + goto out; + + if (info->use_alarm_workaround) { + ret = s2m_rtc_check_rtc_time(info); + if (ret < 0) + goto out; + } + + ret = s2m_rtc_set_alarm_enable(info, alrm->enabled); +out: + mutex_unlock(&info->lock); + return ret; +} + +static int s2m_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct s2m_rtc_info *info = dev_get_drvdata(dev); + int ret; + + mutex_lock(&info->lock); + ret = s2m_rtc_set_alarm_enable(info, enabled); + mutex_unlock(&info->lock); + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int s2m_rtc_wake_lock_timeout(struct device *dev, unsigned int msec) +{ + struct wakeup_source *ws = NULL; + + if (!dev->power.wakeup) { + dev_err(dev, "Not register wakeup source\n"); + goto err; + } + + ws = dev->power.wakeup; + __pm_wakeup_event(ws, msec); + + return 0; +err: + return -1; +} +#endif + +static irqreturn_t s2m_rtc_alarm_irq(int irq, void *data) +{ + struct s2m_rtc_info *info = data; + + if (!info->rtc_dev) + return IRQ_HANDLED; + + dev_info(info->dev, "irq(%d)\n", irq); + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + +#ifdef CONFIG_PM_SLEEP + if (s2m_rtc_wake_lock_timeout(info->dev, 500) < 0) + return IRQ_NONE; +#endif + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops s2m_rtc_ops = { + .read_time = s2m_rtc_read_time, + .set_time = s2m_rtc_set_time, + .read_alarm = s2m_rtc_read_alarm, + .set_alarm = s2m_rtc_set_alarm, + .alarm_irq_enable = s2m_rtc_alarm_irq_enable, +}; + +static void s2m_rtc_optimize_osc(struct s2m_rtc_info *info, + struct s2mpg12_platform_data *pdata) +{ + int ret = 0; + + /* edit option for OSC_BIAS_UP */ + if (pdata->osc_bias_up >= 0) { + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_CAPSEL, + pdata->osc_bias_up + << OSC_BIAS_UP_SHIFT, + BIT(OSC_BIAS_UP_SHIFT)); + if (ret < 0) { + dev_err(info->dev, "fail to write OSC_BIAS_UP(%d)\n", + pdata->osc_bias_up); + return; + } + } + + /* edit option for CAP_SEL */ + if (pdata->cap_sel >= 0) { + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_CAPSEL, + pdata->cap_sel << CAP_SEL_SHIFT, + CAP_SEL_MASK); + if (ret < 0) { + dev_err(info->dev, "fail to write CAP_SEL(%d)\n", + pdata->cap_sel); + return; + } + } + + /* edit option for OSC_CTRL */ + if (pdata->osc_xin >= 0) { + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_OSCCTRL, + pdata->osc_xin << OSC_XIN_SHIFT, + OSC_XIN_MASK); + if (ret < 0) { + dev_err(info->dev, "fail to write OSC_CTRL(%d)\n", + pdata->osc_xin); + return; + } + } + if (pdata->osc_xout >= 0) { + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_OSCCTRL, + pdata->osc_xout << OSC_XOUT_SHIFT, + OSC_XOUT_MASK); + if (ret < 0) { + dev_err(info->dev, "fail to write OSC_CTRL(%d)\n", + pdata->osc_xout); + return; + } + } +} + +static bool s2m_is_jigonb_low(struct s2m_rtc_info *info) +{ + int ret, reg; + u8 val, mask; + + switch (info->iodev->device_type) { + case S2MPG12X: + reg = S2MPG12_PM_STATUS1; + mask = BIT(1); + break; + default: + WARN_ON(1); + return false; + } + + ret = s2mpg12_read_reg(info->i2c, reg, &val); + if (ret < 0) { + dev_err(info->dev, "fail to read status1 reg(%d)\n", + ret); + return false; + } + + return !(val & mask); +} + +static void s2m_rtc_enable_wtsr_smpl(struct s2m_rtc_info *info, + struct s2mpg12_platform_data *pdata) +{ + u8 wtsr_val, smpl_val; + int ret; + + if (pdata->wtsr_smpl->check_jigon && s2m_is_jigonb_low(info)) + pdata->wtsr_smpl->smpl_en = false; + + wtsr_val = (pdata->wtsr_smpl->wtsr_en << WTSR_EN_SHIFT) | + WTSR_TIMER_BITS(pdata->wtsr_smpl->wtsr_timer_val); + + if (pdata->wtsr_smpl->coldrst_en) + wtsr_val |= (COLDRST_EN_MASK | + ((pdata->wtsr_smpl->coldrst_timer_val + << COLDRST_TIMER_SHIFT) & COLDRST_TIMER_MASK)); + else + wtsr_val &= ~COLDRST_EN_MASK; + + smpl_val = (pdata->wtsr_smpl->smpl_en << SMPL_EN_SHIFT) | + SMPL_TIMER_BITS(pdata->wtsr_smpl->smpl_timer_val); + + dev_info(info->dev, "%s: WTSR: %s, COLDRST : %s, SMPL: %s\n", __func__, + pdata->wtsr_smpl->wtsr_en ? "enable" : "disable", + pdata->wtsr_smpl->coldrst_en ? "enable" : "disable", + pdata->wtsr_smpl->smpl_en ? "enable" : "disable"); + + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_SMPL, smpl_val); + if (ret < 0) { + dev_err(info->dev, "fail to write SMPL reg(%d)\n", ret); + return; + } + + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_WTSR, wtsr_val); + if (ret < 0) { + dev_err(info->dev, "fail to write WTSR reg(%d)\n", ret); + return; + } + + info->wtsr_en = pdata->wtsr_smpl->wtsr_en; + info->smpl_en = pdata->wtsr_smpl->smpl_en; + info->coldrst_en = pdata->wtsr_smpl->coldrst_en; +} + +static void s2m_rtc_disable_wtsr_smpl(struct s2m_rtc_info *info, + struct s2mpg12_platform_data *pdata) +{ + int ret; + + dev_dbg(info->dev, "disable SMPL\n"); + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_SMPL, 0, SMPL_EN_MASK); + if (ret < 0) + dev_err(info->dev, "fail to update SMPL reg(%d)\n", ret); + + ret = s2mpg12_update_reg(info->i2c, S2MPG12_RTC_WTSR, 0, + WTSR_EN_MASK | COLDRST_EN_MASK); + if (ret < 0) + dev_err(info->dev, "fail to update SMPL reg(%d)\n", ret); +} + +static int s2m_rtc_init_reg(struct s2m_rtc_info *info, + struct s2mpg12_platform_data *pdata) +{ + u8 data, update_val, ctrl_val, nonce0_val[NONCE0_CNT]; + bool is_nonce0_val_zero = true; + int i; + int ret; + + ret = s2mpg12_read_reg(info->i2c, S2MPG12_RTC_UPDATE, &update_val); + if (ret < 0) { + dev_err(info->dev, "fail to read update reg(%d)\n", ret); + return ret; + } + + info->update_reg = update_val & ~(info->wudr_mask | + BIT(RTC_FREEZE_SHIFT) | + BIT(RTC_RUDR_SHIFT) | + info->audr_mask); + + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_UPDATE, + info->update_reg); + if (ret < 0) { + dev_err(info->dev, "fail to write update reg(%d)\n", ret); + return ret; + } + + s2m_rtc_update(info, S2M_RTC_READ); + + ret = s2mpg12_read_reg(info->i2c, S2MPG12_RTC_CTRL, &ctrl_val); + if (ret < 0) { + dev_err(info->dev, "fail to read control reg(%d)\n", ret); + return ret; + } + + ret = s2mpg12_bulk_read(info->i2c, S2MPG12_RTC_NONCE0_0, NONCE0_CNT, + nonce0_val); + if (ret < 0) { + dev_err(info->dev, "fail to read NONCE0 regs(%d)\n", ret); + return ret; + } + + + for (i = 0; i < NONCE0_CNT; i++) { + if (nonce0_val[i] != 0) { + is_nonce0_val_zero = false; + break; + } + } + + /* If the value of RTC_CTRL register is 0, RTC registers were reset */ + if ((ctrl_val & BIT(MODEL24_SHIFT)) && !is_nonce0_val_zero) { + return 0; + } + + /* Set RTC control register : Binary mode, 24hour mode */ + data = BIT(MODEL24_SHIFT); + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_CTRL, data); + if (ret < 0) { + dev_err(info->dev, "fail to write CTRL reg(%d)\n", ret); + return ret; + } + + ret = s2m_rtc_update(info, S2M_RTC_WRITE_ALARM); + if (ret < 0) + return ret; + + ret = s2mpg12_write_reg(info->i2c, S2MPG12_RTC_NONCE0_0, NONCE0_0_SPECIAL_VAL); + if (ret < 0) { + dev_err(info->dev, "fail to write RTC_NONCE0_0 reg(%d)\n", ret); + return ret; + } + + if (pdata->init_time) { + dev_info(info->dev, "initialize RTC time\n"); + ret = s2m_rtc_set_time(info->dev, pdata->init_time); + } else { + dev_info(info->dev, + "RTC initialize is not operated: This causes a weekday problem\n"); + } + return ret; +} + +static int s2m_rtc_probe(struct platform_device *pdev) +{ + struct s2mpg12_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg12_platform_data *pdata = dev_get_platdata(iodev->dev); + struct s2m_rtc_info *info; + int irq_base; + int ret = 0; + + info = devm_kzalloc(&pdev->dev, sizeof(struct s2m_rtc_info), + GFP_KERNEL); + + if (!info) + return -ENOMEM; + + irq_base = pdata->irq_base; + if (!irq_base) { + dev_err(&pdev->dev, "Failed to get irq base %d\n", irq_base); + return -ENODEV; + } + + mutex_init(&info->lock); + info->dev = &pdev->dev; + info->iodev = iodev; + info->i2c = iodev->rtc; + info->pmic_i2c = iodev->pmic; + info->alarm_check = true; + info->use_alarm_workaround = false; + + switch (info->iodev->device_type) { + case S2MPG12X: + info->alarm0_irq = irq_base + S2MPG12_IRQ_RTCA0_INT2; + break; + default: + /* If this happens the core function has a problem */ + WARN_ON(1); + ret = -ENXIO; + goto err_rtc_init_reg; + } + + platform_set_drvdata(pdev, info); + + ret = s2m_rtc_init_reg(info, pdata); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret); + goto err_rtc_init_reg; + } + + /* enable wtsr smpl */ + if (pdata->wtsr_smpl) + s2m_rtc_enable_wtsr_smpl(info, pdata); + + s2m_rtc_optimize_osc(info, pdata); + + ret = device_init_wakeup(&pdev->dev, true); + if (ret < 0) { + dev_err(&pdev->dev, "device_init_wakeup fail(%d)\n", ret); + goto err_init_wakeup; + } + + /* request alarm0 interrupt */ + ret = devm_request_threaded_irq(&pdev->dev, info->alarm0_irq, NULL, + s2m_rtc_alarm_irq, 0, "rtc-alarm0", + info); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", + info->alarm0_irq, ret); + goto err_rtc_irq; + } + + disable_irq(info->alarm0_irq); + disable_irq(info->alarm0_irq); + info->use_irq = true; + + info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s2mpg12-rtc", + &s2m_rtc_ops, THIS_MODULE); + + if (IS_ERR(info->rtc_dev)) { + ret = PTR_ERR(info->rtc_dev); + dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret); + goto err_rtc_dev_register; + } + + enable_irq(info->alarm0_irq); + return 0; + +err_rtc_dev_register: + devm_free_irq(&pdev->dev, info->alarm0_irq, info); +err_rtc_irq: +err_init_wakeup: +err_rtc_init_reg: + platform_set_drvdata(pdev, NULL); + mutex_destroy(&info->lock); + + return ret; +} + +static int s2m_rtc_remove(struct platform_device *pdev) +{ + struct s2m_rtc_info *info = platform_get_drvdata(pdev); + + if (!info->alarm_enabled) + enable_irq(info->alarm0_irq); + +#ifdef CONFIG_PM_SLEEP + if (info->dev->power.wakeup) + device_init_wakeup(&pdev->dev, false); +#endif + mutex_destroy(&info->lock); + + return 0; +} + +static void s2m_rtc_shutdown(struct platform_device *pdev) +{ + /* disable wtsr, smpl */ + struct s2m_rtc_info *info = platform_get_drvdata(pdev); + struct s2mpg12_platform_data *pdata = + dev_get_platdata(info->iodev->dev); + + if (info->wtsr_en || info->smpl_en || info->coldrst_en) + s2m_rtc_disable_wtsr_smpl(info, pdata); + + if (system_state == SYSTEM_RESTART) { + s2mpg12_update_reg(info->i2c, S2MPG12_RTC_WTSR, + COLDRST_TIMER_MASK | COLDRST_EN_MASK | + WTSRT_MASK | WTSR_EN_MASK, + GENMASK(6, 0)); + } +} + +static const struct platform_device_id s2m_rtc_id[] = { + { "s2mpg12-rtc", 0 }, + {}, +}; + +static struct platform_driver s2m_rtc_driver = { + .driver = { + .name = "s2mpg12-rtc", + .owner = THIS_MODULE, + }, + .probe = s2m_rtc_probe, + .remove = s2m_rtc_remove, + .shutdown = s2m_rtc_shutdown, + .id_table = s2m_rtc_id, +}; + +module_platform_driver(s2m_rtc_driver); + +/* Module information */ +MODULE_DESCRIPTION("Samsung RTC driver"); +MODULE_AUTHOR("Samsung Electronics"); +MODULE_LICENSE("GPL"); diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig index dcfb9f7b5f4d..979714b3b471 100644 --- a/drivers/scsi/ufs/Kconfig +++ b/drivers/scsi/ufs/Kconfig @@ -209,11 +209,19 @@ config SCSI_UFS_HWMON config SCSI_UFS_PIXEL_FIPS140 tristate "Enable FIPS 140 CMVP Module" - depends on m && SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO + depends on m && SCSI_UFS_EXYNOS && SCSI_UFS_CRYPTO && !LTO_NONE help - Build a module capable of executing FIPS140-2 compliant self tests of + Build a module capable of executing FIPS140-3 compliant self tests of the UFS crypto engine. The module is used to execute power on self test for cases where the hardware component does not support the functionality natively. +config SCSI_UFS_PIXEL_ACVP + tristate "Build FIPS 140 ACVP Module" + depends on m && SCSI_UFS_PIXEL_FIPS140 + help + Build a module to enable testing UFS crypto engine for ACVP + certification. This module should be built to perform testing and + should not be included in a release build. + endif diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile index 3469520b6e2a..9e336fad23ec 100644 --- a/drivers/scsi/ufs/Makefile +++ b/drivers/scsi/ufs/Makefile @@ -30,11 +30,14 @@ obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o obj-$(CONFIG_SCSI_UFS_EXYNOS) += ufs-exynos-core.o ufs-exynos-core-y += ufs-exynos.o ufs-exynos-dbg.o ufs-pixel.o ufs-exynos-core-$(CONFIG_SOC_GS101) += gs101/ufs-cal-if.o +ufs-exynos-core-$(CONFIG_SOC_GS201) += gs201/ufs-cal-if.o ufs-exynos-core-$(CONFIG_SCSI_UFS_CRYPTO) += ufs-pixel-crypto.o ufs-exynos-fmp.o obj-$(CONFIG_SCSI_UFS_PIXEL_FIPS140) += ufs-pixel-fips140.o -ufs-pixel-fips140-y += ufs-pixel-fips.o ufs-pixel-fips_sha256.o \ - ufs-pixel-fips140-refs.o +ufs-pixel-fips140-y += ufs-pixel-fips_sha256.o ufs-pixel-fips140-refs.o +ufs-pixel-fips140-$(CONFIG_SOC_GS101) += gs101/ufs-pixel-fips.o +ufs-pixel-fips140-$(CONFIG_SOC_GS201) += gs201/ufs-pixel-fips.o + # Use -DBUILD_FIPS140_KO to disable dynamic code patching as that would # invalidate the hash of the module's .text section CFLAGS_ufs-pixel-fips140.o += -DBUILD_FIPS140_KO @@ -42,3 +45,5 @@ CFLAGS_ufs-pixel-fips_sha256.o := -DBUILD_FIPS140_KO hostprogs := ufs-pixel-fips_gen_hmac HOSTLDLIBS_ufs-pixel-fips_gen_hmac := -lcrypto -lelf $(obj)/ufs-pixel-fips140.o: $(obj)/ufs-pixel-fips_gen_hmac + +obj-$(CONFIG_SCSI_UFS_PIXEL_ACVP) += ufs-pixel-acvp.o diff --git a/drivers/scsi/ufs/ufs-pixel-fips.c b/drivers/scsi/ufs/gs101/ufs-pixel-fips.c similarity index 100% rename from drivers/scsi/ufs/ufs-pixel-fips.c rename to drivers/scsi/ufs/gs101/ufs-pixel-fips.c diff --git a/drivers/scsi/ufs/gs201/ufs-cal-if.c b/drivers/scsi/ufs/gs201/ufs-cal-if.c new file mode 100644 index 000000000000..555d26939115 --- /dev/null +++ b/drivers/scsi/ufs/gs201/ufs-cal-if.c @@ -0,0 +1,1238 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * + * Authors: + * Kiwoong + */ + +#include +#include +#include +#include "ufs-vs-mmio.h" +#include "ufs-cal-if.h" + +/* + * CAL table, project specifics + * + * This is supposed to be in here, i.e. + * right before definitions for version check. + * + * DO NOT MOVE THIS TO ANYWHERE RANDOMLY !!! + */ +#include "ufs-cal.h" + +/* + * UFS CAL just requires some things that don't have an impact on + * external components, such as macros, not functions. + * The requirement list is below: readl, writel, udelay + */ + +#define NUM_OF_UFS_HOST 2 + +enum { + PA_HS_MODE_A = 1, + PA_HS_MODE_B = 2, +}; + +enum { + FAST_MODE = 1, + SLOW_MODE = 2, + FASTAUTO_MODE = 4, + SLOWAUTO_MODE = 5, + UNCHANGED = 7, +}; + +enum { + TX_LANE_0 = 0, + RX_LANE_0 = 4, +}; + +#define TX_LINE_RESET_TIME 3200 +#define RX_LINE_RESET_DETECT_TIME 1000 + +#define DELAY_PERIOD_IN_US 40 /* 40us */ +#define TIMEOUT_IN_US (40 * 1000) /* 40ms */ + +#define UNIP_DL_ERROR_IRQ_MASK 0x4844 /* shadow of DL error */ +#define PA_ERROR_IND_RECEIVED BIT(15) + +#define PHY_PMA_LANE_OFFSET 0x800 +#define PHY_PMA_COMN_ADDR(reg) (reg) +#define PHY_PMA_TRSV_ADDR(reg, lane) ((reg) + (PHY_PMA_LANE_OFFSET * (lane))) + +#define UNIP_COMP_AXI_AUX_FIELD 0x040 +#define __WSTRB (0xF << 24) +#define __SEL_IDX(L) ((L) & 0xFFFF) + +/* + * private data + */ +static struct ufs_cal_param *ufs_cal[NUM_OF_UFS_HOST]; + +static const struct ufs_cal_phy_cfg init_cfg_evt0[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x44, 0x00, PMD_ALL, UNIPRO_DBG_PRD, BRD_ALL}, + + {0x200, 0x2800, 0x40, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#if (USE_UFS_REFCLK == USE_19_2_MHZ) //UFS Reference CLK = 19.2MHz + {0x202, 0x2808, 0x2, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#elif (USE_UFS_REFCLK == USE_38_4_MHZ) //UFS Reference CLK = 38.4MHz + {0x202, 0x2808, 0x2, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, + {0x0000, 0x0A4, 0x22, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, +#else //UFS Reference CLK = 26MHz + {0x202, 0x2808, 0x12, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#endif + {0x12, 0x2048, 0x00, PMD_ALL, PHY_PCS_RX_PRD_ROUND_OFF, BRD_ALL}, + {0xAA, 0x22A8, 0x00, PMD_ALL, PHY_PCS_TX_PRD_ROUND_OFF, BRD_ALL}, + {0xA9, 0x22A4, 0x02, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0xAB, 0x22AC, 0x00, PMD_ALL, PHY_PCS_TX_LR_PRD, BRD_ALL}, + {0x11, 0x2044, 0x00, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x1B, 0x206C, 0x00, PMD_ALL, PHY_PCS_RX_LR_PRD, BRD_ALL}, + {0x2F, 0x20BC, 0x69, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x76, 0x21D8, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + {0x9E, 0x2278, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + {0x9F, 0x227C, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + + {0x84, 0x2210, 0x01, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x04, 0x2010, 0x01, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0x25, 0x2094, 0xF6, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x7F, 0x21FC, 0x00, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0x200, 0x2800, 0x0, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, + + {0x155E, 0x3178, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x3000, 0x5000, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x3001, 0x5004, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x4021, 0x6084, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x4020, 0x6080, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + + {0xA006, 0x4818, 0x80000000, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0x0000, 0x10C, 0x10, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x0F0, 0x14, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x118, 0x48, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + + {0x0000, 0x800, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x804, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x808, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x80C, 0x0A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x810, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x814, 0x11, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x81C, 0x0C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xB84, 0xC0, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x8B4, 0xB8, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x8D0, 0x60, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x8E0, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8E4, 0x48, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8E8, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8EC, 0x25, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F0, 0x2A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F4, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F8, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8FC, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x900, 0x4A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x90C, 0x40, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x910, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x974, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x978, 0x3F, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x97C, 0xFF, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x9CC, 0x33, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9D0, 0x50, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA10, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA14, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA88, 0x04, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9F4, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBE8, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA18, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA1C, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA20, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA24, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xACC, 0x04, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xAD8, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xADC, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE0, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE4, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE8, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAEC, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF0, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF4, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF8, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xB90, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBB4, 0x25, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9A4, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBD0, 0x2F, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xD2C, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD30, 0x23, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD34, 0x23, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD38, 0x45, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD3C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD40, 0x31, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD44, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD48, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD4C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD50, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x10C, 0x18, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x10C, 0x00, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + + {0x0000, 0xCE0, 0x08, PMD_ALL, PHY_EMB_CAL_WAIT, BRD_ALL}, + {0xA006, 0x4818, 0x0, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg init_cfg_evt1[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x44, 0x00, PMD_ALL, UNIPRO_DBG_PRD, BRD_ALL}, + + {0x200, 0x2800, 0x40, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#if (USE_UFS_REFCLK == USE_19_2_MHZ) //UFS Reference CLK = 19.2MHz + {0x202, 0x2808, 0x2, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#elif (USE_UFS_REFCLK == USE_38_4_MHZ) //UFS Reference CLK = 38.4MHz + {0x202, 0x2808, 0x2, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, + {0x0000, 0x0A4, 0x22, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, +#else //UFS Reference CLK = 26MHz + {0x202, 0x2808, 0x12, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, +#endif + {0x12, 0x2048, 0x00, PMD_ALL, PHY_PCS_RX_PRD_ROUND_OFF, BRD_ALL}, + {0xAA, 0x22A8, 0x00, PMD_ALL, PHY_PCS_TX_PRD_ROUND_OFF, BRD_ALL}, + {0xA9, 0x22A4, 0x02, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0xAB, 0x22AC, 0x00, PMD_ALL, PHY_PCS_TX_LR_PRD, BRD_ALL}, + {0x11, 0x2044, 0x00, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x1B, 0x206C, 0x00, PMD_ALL, PHY_PCS_RX_LR_PRD, BRD_ALL}, + {0x2F, 0x20BC, 0x69, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x76, 0x21D8, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + {0x9E, 0x2278, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + {0x9F, 0x227C, 0x03, PMD_ALL, PHY_PCS_RX, BRD_ZEBU}, + + {0x84, 0x2210, 0x01, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x04, 0x2010, 0x01, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0x25, 0x2094, 0xF6, PMD_ALL, PHY_PCS_RX, BRD_ALL}, + {0x7F, 0x21FC, 0x00, PMD_ALL, PHY_PCS_TX, BRD_ALL}, + {0x200, 0x2800, 0x0, PMD_ALL, PHY_PCS_COMN, BRD_ALL}, + + {0x155E, 0x3178, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x3000, 0x5000, 0x0, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x3001, 0x5004, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x4021, 0x6084, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x4020, 0x6080, 0x1, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + + {0xA006, 0x4818, 0x80000000, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0x0000, 0x10C, 0x10, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x0F0, 0x14, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x118, 0x48, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + + {0x0000, 0x800, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x804, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x808, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x80C, 0x0A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x810, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x814, 0x11, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x81C, 0x0C, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xB84, 0xC0, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8B4, 0xB8, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x8D0, 0x60, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8E0, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8E4, 0x48, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8E8, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8EC, 0x25, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F0, 0x2A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F4, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8F8, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8FC, 0x13, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x900, 0x4A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x90C, 0x40, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x910, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x974, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x978, 0x3F, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x97C, 0xFF, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x9CC, 0x33, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9D0, 0x50, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA10, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA14, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA88, 0x04, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9F4, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBE8, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xA18, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA1C, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA20, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA24, 0x03, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xACC, 0x04, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xAD8, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xADC, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE0, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE4, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAE8, 0x0B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAEC, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF0, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF4, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xAF8, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xB90, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBB4, 0x25, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9A4, 0x1A, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xBD0, 0x2F, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xD2C, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD30, 0x23, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD34, 0x23, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD38, 0x45, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD3C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD40, 0x31, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD44, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD48, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD4C, 0x00, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xD50, 0x01, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0x10C, 0x18, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x10C, 0x00, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0xCE0, 0x08, PMD_ALL, PHY_EMB_CAL_WAIT, BRD_ALL}, + + {0xA006, 0x4818, 0x0, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_init_cfg_evt0[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x15D2, 0x3348, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL}, + {0x15D3, 0x334C, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL}, + + {0x9529, 0x38A4, 0x01, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + {0x15A4, 0x3290, 0x3E8, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x9529, 0x38A4, 0x00, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_init_cfg_evt1[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x15D2, 0x3348, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL}, + {0x15D3, 0x334C, 0x0, PMD_ALL, UNIPRO_ADAPT_LENGTH, BRD_ALL}, + + {0x9529, 0x38A4, 0x01, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + {0x15A4, 0x3290, 0x3E8, PMD_ALL, UNIPRO_STD_MIB, BRD_ALL}, + {0x9529, 0x38A4, 0x00, PMD_ALL, UNIPRO_DBG_MIB, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_pwm[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x2041, 0x4104, 8064, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + {0x2042, 0x4108, 28224, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + {0x2043, 0x410C, 20160, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B0, 0x32C0, 12000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B1, 0x32C4, 32000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B2, 0x32C8, 16000, PMD_PWM, UNIPRO_STD_MIB, BRD_ALL}, + + {0x0000, 0x7888, 8064, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x788C, 28224, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x7890, 20160, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78B8, 12000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78BC, 32000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78C0, 16000, PMD_PWM, UNIPRO_DBG_APB, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_pwm[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x20, 0x60, PMD_PWM, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x888, 0x08, PMD_PWM, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x918, 0x01, PMD_PWM, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_hs_rate_a[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x15D4, 0x3350, 0x1, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + + {0x2041, 0x4104, 8064, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x2042, 0x4108, 28224, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x2043, 0x410C, 20160, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B0, 0x32C0, 12000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B1, 0x32C4, 32000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B2, 0x32C8, 16000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + + {0x0000, 0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + + {0x0000, 0xDA4, 0x11, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x918, 0x03, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_hs_rate_a[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0xCE4, 0x08, PMD_HS, PHY_EMB_CDR_WAIT, BRD_ALL}, + {0x0000, 0x918, 0x01, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_hs_rate_b[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x15D4, 0x3350, 0x1, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + + {0x2041, 0x4104, 8064, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x2042, 0x4108, 28224, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x2043, 0x410C, 20160, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B0, 0x32C0, 12000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B1, 0x32C4, 32000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + {0x15B2, 0x32C8, 16000, PMD_HS, UNIPRO_STD_MIB, BRD_ALL}, + + {0x0000, 0x7888, 8064, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x788C, 28224, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x7890, 20160, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78B8, 12000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78BC, 32000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + {0x0000, 0x78C0, 16000, PMD_HS, UNIPRO_DBG_APB, BRD_ALL}, + + {0x0000, 0xDA4, 0x11, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x918, 0x03, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_hs_rate_b[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0xCE4, 0x08, PMD_HS, PHY_EMB_CDR_WAIT, BRD_ALL^BRD_ZEBU}, + {0x0000, 0x918, 0x01, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg lane1_sq_off[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x988, 0x08, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, BRD_ALL}, + {0x0000, 0x994, 0x0A, PMD_ALL, PHY_PMA_TRSV_LANE1_SQ_OFF, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_h8_enter[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x988, 0x08, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL}, + {0x0000, 0x994, 0x0A, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL}, + {0x0000, 0x04, 0x08, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x00, 0x86, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + + {0x0000, 0x20, 0x60, PMD_HS, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x888, 0x08, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x918, 0x01, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg pre_h8_exit[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x00, 0xC6, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x04, 0x0C, PMD_ALL, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x988, 0x00, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL}, + {0x0000, 0x994, 0x00, PMD_ALL, PHY_PMA_TRSV_SQ, BRD_ALL}, + + {0x0000, 0x20, 0xE0, PMD_HS, PHY_PMA_COMN, BRD_ALL}, + {0x0000, 0x918, 0x03, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x888, 0x18, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xCE0, 0x02, PMD_HS, PHY_EMB_CDR_WAIT, BRD_ZEBU}, + {0x0000, 0xCE4, 0x08, PMD_HS, PHY_EMB_CDR_WAIT, BRD_ALL^BRD_ZEBU}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_init[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0xBB4, 0x23, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x868, 0x02, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9A8, 0xA1, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9AC, 0x40, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_set_1[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0xBB4, 0x2B, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x888, 0x06, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_set_2[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0x9BC, 0x52, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x9A8, 0xA7, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x8AC, 0xC3, PMD_ALL, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg eom_prepare[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0x0000, 0xBC0, 0x00, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xA88, 0x05, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x93C, 0x0F, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + /* per gear */ + {0x0000, 0x940, 0x4F, PMD_HS_G4, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x940, 0x2F, PMD_HS_G3, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x940, 0x1F, PMD_HS_G2, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0x940, 0x0F, PMD_HS_G1, PHY_PMA_TRSV, BRD_ALL}, + + {0x0000, 0xB64, 0xE3, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xB68, 0x04, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + {0x0000, 0xB6C, 0x00, PMD_HS, PHY_PMA_TRSV, BRD_ALL}, + + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg init_cfg_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_init_cfg_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_pwm_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_pwm_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_hs_rate_a_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_hs_rate_a_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg calib_of_hs_rate_b_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_calib_of_hs_rate_b_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg lane1_sq_off_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg post_h8_enter_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg pre_h8_exit_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_init_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_set_1_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +static const struct ufs_cal_phy_cfg loopback_set_2_card[] = { + /* mib(just to monitor), sfr offset, value, .. */ + {0, 0, 0, 0, PHY_CFG_NONE, BRD_ALL} +}; + +const u32 ufs_s_eom_repeat[GEAR_MAX + 1] = { + 0, EOM_RTY_G1, EOM_RTY_G2, EOM_RTY_G3, EOM_RTY_G4 +}; + +/* + * inline functions + */ +static inline bool is_pwr_mode_hs(u8 m) +{ + return m == FAST_MODE || m == FASTAUTO_MODE; +} + +static inline bool is_pwr_mode_pwm(u8 m) +{ + return m == SLOW_MODE || m == SLOWAUTO_MODE; +} + +static inline u32 __get_mclk_period(struct ufs_cal_param *p) +{ + return 1000000000U / p->mclk_rate; +} + +static inline u32 __get_mclk_period_unipro_18(struct ufs_cal_param *p) +{ + u64 val = 16 * 1000 * 1000000UL; + + return div_u64(val, p->mclk_rate); +} + +static inline u32 __get_mclk_period_rnd_off(struct ufs_cal_param *p) +{ + /* assume that mclk_rate is supposed to be unsigned */ + return DIV_ROUND_CLOSEST(1000000000UL, p->mclk_rate); +} + +/* + * This function returns how many ticks is required to line reset + * for predefined time value. + */ +static inline u32 __get_line_reset_ticks(struct ufs_cal_param *p, + u32 time_in_us) +{ + u64 val = (u64)p->mclk_rate * time_in_us; + + return div_u64(val, 1000000U); +} + +static inline enum ufs_cal_errno __match_board_by_cfg(u8 board, u8 cfg_board) +{ + enum ufs_cal_errno match = UFS_CAL_ERROR; + + if (board & cfg_board) + match = UFS_CAL_NO_ERROR; + + return match; +} + +static enum ufs_cal_errno __match_mode_by_cfg(struct uic_pwr_mode *pmd, + int mode) +{ + enum ufs_cal_errno match; + + if (mode == PMD_ALL) { + match = UFS_CAL_NO_ERROR; + } else if (is_pwr_mode_hs(pmd->mode) && mode >= PMD_HS_G1 && + mode <= PMD_HS) { + match = UFS_CAL_NO_ERROR; + if (mode != PMD_HS && pmd->gear != (mode - PMD_HS_G1 + 1)) + match = UFS_CAL_ERROR; + } else if (is_pwr_mode_pwm(pmd->mode) && mode >= PMD_PWM_G1 && + mode <= PMD_PWM) { + match = UFS_CAL_NO_ERROR; + if (mode != PMD_PWM && pmd->gear != (mode - PMD_PWM_G1 + 1)) + match = UFS_CAL_ERROR; + } else { + /* invalid lanes */ + match = UFS_CAL_ERROR; + } + + return match; +} + +static enum ufs_cal_errno ufs_cal_wait_pll_lock(struct ufs_vs_handle *handle, + u32 addr, u32 mask) +{ + u32 attempts = TIMEOUT_IN_US / DELAY_PERIOD_IN_US; + u32 reg; + + while (attempts--) { + reg = pma_readl(handle, PHY_PMA_COMN_ADDR(addr)); + if (mask == (reg & mask)) + return UFS_CAL_NO_ERROR; + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + } + + return UFS_CAL_ERROR; +} + +static enum ufs_cal_errno ufs_cal_wait_cdr_lock(struct ufs_vs_handle *handle, + u32 addr, u32 mask, int lane) +{ + u32 attempts = TIMEOUT_IN_US / DELAY_PERIOD_IN_US; + u32 reg; + + while (attempts--) { + reg = pma_readl(handle, PHY_PMA_TRSV_ADDR(addr, lane)); + if (mask == (reg & mask)) + return UFS_CAL_NO_ERROR; + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + } + + return UFS_CAL_ERROR; +} + +static enum ufs_cal_errno ufs30_cal_wait_cdr_lock(struct ufs_vs_handle *handle, + u32 addr, u32 mask, int lane) +{ + u32 reg; + u32 i; + + for (i = 0; i < 100; i++) { + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + + reg = pma_readl(handle, PHY_PMA_TRSV_ADDR(addr, lane)); + if (mask == (reg & mask)) + return UFS_CAL_NO_ERROR; + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + + pma_writel(handle, 0x10, PHY_PMA_TRSV_ADDR(0x888, lane)); + pma_writel(handle, 0x18, PHY_PMA_TRSV_ADDR(0x888, lane)); + } + + return UFS_CAL_ERROR; +} + +static enum ufs_cal_errno +ufs_cal_wait_cdr_afc_check(struct ufs_vs_handle *handle, u32 addr, u32 mask, + int lane) +{ + u32 i; + + for (i = 0; i < 100; i++) { + u32 reg = 0; + + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + + reg = pma_readl(handle, PHY_PMA_TRSV_ADDR(addr, lane)); + if (mask == (reg & mask)) + return UFS_CAL_NO_ERROR; + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + + pma_writel(handle, 0x7F, PHY_PMA_TRSV_ADDR(0xF0, lane)); + pma_writel(handle, 0xFF, PHY_PMA_TRSV_ADDR(0xF0, lane)); + } + + return UFS_CAL_ERROR; +} + +static enum ufs_cal_errno ufs30_cal_done_wait(struct ufs_vs_handle *handle, + u32 addr, u32 mask, int lane) +{ + u32 i; + + for (i = 0; i < 100; i++) { + u32 reg = 0; + + if (handle->udelay) + handle->udelay(DELAY_PERIOD_IN_US); + + reg = pma_readl(handle, PHY_PMA_TRSV_ADDR(addr, lane)); + if (mask == (reg & mask)) + return UFS_CAL_NO_ERROR; + } + + return UFS_CAL_NO_ERROR; +} + +static inline void __set_pcs(struct ufs_vs_handle *handle, + u8 lane, u32 offset, u32 value) +{ + unipro_writel(handle, __WSTRB | __SEL_IDX(lane), + UNIP_COMP_AXI_AUX_FIELD); + unipro_writel(handle, value, offset); + unipro_writel(handle, __WSTRB, UNIP_COMP_AXI_AUX_FIELD); +} + +static enum ufs_cal_errno __config_uic(struct ufs_vs_handle *handle, u8 lane, + const struct ufs_cal_phy_cfg *cfg, + struct ufs_cal_param *p) +{ + enum ufs_cal_errno ret = UFS_CAL_NO_ERROR; + u32 value, ticks; + + switch (cfg->lyr) { + /* unipro */ + case UNIPRO_STD_MIB: + case UNIPRO_DBG_MIB: + unipro_writel(handle, cfg->val, cfg->addr); + break; + case UNIPRO_ADAPT_LENGTH: + value = unipro_readl(handle, cfg->addr); + if (value & 0x80) { + if ((value & 0x7F) < 2) + unipro_writel(handle, 0x82, cfg->addr); + } else if (((value + 1) & 0x3)) { + value |= 0x3; + unipro_writel(handle, value, cfg->addr); + } + break; + case UNIPRO_DBG_PRD: + unipro_writel(handle, p->mclk_period_unipro_18, cfg->addr); + break; + case UNIPRO_DBG_APB: + unipro_writel(handle, cfg->val, cfg->addr); + break; + + /* pcs */ + case PHY_PCS_COMN: + unipro_writel(handle, cfg->val, cfg->addr); + break; + case PHY_PCS_RX: + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr, cfg->val); + break; + case PHY_PCS_TX: + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr, cfg->val); + break; + case PHY_PCS_RX_PRD: + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr, p->mclk_period); + break; + case PHY_PCS_TX_PRD: + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr, p->mclk_period); + break; + case PHY_PCS_RX_PRD_ROUND_OFF: + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr, + p->mclk_period_rnd_off); + break; + case PHY_PCS_TX_PRD_ROUND_OFF: + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr, + p->mclk_period_rnd_off); + break; + case PHY_PCS_RX_LR_PRD: + ticks = __get_line_reset_ticks(p, RX_LINE_RESET_DETECT_TIME); + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr, + (ticks >> 16) & 0xFF); + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr + 4, + (ticks >> 8) & 0xFF); + __set_pcs(handle, RX_LANE_0 + lane, cfg->addr + 8, + (ticks >> 0) & 0xFF); + break; + case PHY_PCS_TX_LR_PRD: + ticks = __get_line_reset_ticks(p, TX_LINE_RESET_TIME); + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr, + (ticks >> 16) & 0xFF); + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr + 4, + (ticks >> 8) & 0xFF); + __set_pcs(handle, TX_LANE_0 + lane, cfg->addr + 8, + (ticks >> 0) & 0xFF); + break; + + /* pma */ + case PHY_PMA_COMN: + pma_writel(handle, cfg->val, PHY_PMA_COMN_ADDR(cfg->addr)); + break; + case PHY_PMA_TRSV: + pma_writel(handle, cfg->val, + PHY_PMA_TRSV_ADDR(cfg->addr, lane)); + break; + case PHY_PLL_WAIT: + if (ufs_cal_wait_pll_lock(handle, cfg->addr, + cfg->val) == UFS_CAL_ERROR) + ret = UFS_CAL_TIMEOUT; + break; + case PHY_CDR_WAIT: + /* after gear change */ + if (ufs_cal_wait_cdr_lock(handle, cfg->addr, + cfg->val, lane) == UFS_CAL_ERROR) + ret = UFS_CAL_TIMEOUT; + break; + case PHY_EMB_CDR_WAIT: + /* after gear change */ + if (ufs30_cal_wait_cdr_lock(p->handle, cfg->addr, + cfg->val, lane) == UFS_CAL_ERROR) + ret = UFS_CAL_TIMEOUT; + break; + /* after gear change */ + case PHY_CDR_AFC_WAIT: + if (p->tbl == HOST_CARD) { + if (ufs_cal_wait_cdr_afc_check(p->handle, cfg->addr, + cfg->val, lane) == UFS_CAL_ERROR) + ret = UFS_CAL_TIMEOUT; + } + break; + case PHY_EMB_CAL_WAIT: + if (ufs30_cal_done_wait(p->handle, cfg->addr, + cfg->val, lane) == UFS_CAL_ERROR) + ret = UFS_CAL_TIMEOUT; + break; + case COMMON_WAIT: + if (handle->udelay) + handle->udelay(cfg->val); + break; + case PHY_PMA_TRSV_SQ: + /* for hibern8 time */ + pma_writel(handle, cfg->val, + PHY_PMA_TRSV_ADDR(cfg->addr, lane)); + break; + case PHY_PMA_TRSV_LANE1_SQ_OFF: + /* for hibern8 time */ + pma_writel(handle, cfg->val, + PHY_PMA_TRSV_ADDR(cfg->addr, lane)); + break; + default: + break; + } + + return ret; +} + +static enum ufs_cal_errno do_cal_config_uic(int i, struct ufs_cal_param *p, + const struct ufs_cal_phy_cfg *cfg, + struct uic_pwr_mode *pmd) +{ + struct ufs_vs_handle *handle = p->handle; + + if (p->board && __match_board_by_cfg(p->board, cfg->board) == + UFS_CAL_ERROR) + return UFS_CAL_NO_ERROR; + + if (pmd && __match_mode_by_cfg(pmd, cfg->flg) == UFS_CAL_ERROR) + return UFS_CAL_NO_ERROR; + + if (i == 0) + goto skip_base; + + switch (cfg->lyr) { + case PHY_PCS_COMN: + case UNIPRO_STD_MIB: + case UNIPRO_DBG_MIB: + case UNIPRO_ADAPT_LENGTH: + case UNIPRO_DBG_PRD: + case PHY_PMA_COMN: + case UNIPRO_DBG_APB: + case PHY_PLL_WAIT: + case COMMON_WAIT: + return UFS_CAL_NO_ERROR; + default: + break; + } +skip_base: + if (i < p->active_rx_lane) + goto skip_rx_lane; + + switch (cfg->lyr) { + case PHY_CDR_WAIT: + case PHY_EMB_CDR_WAIT: + case PHY_CDR_AFC_WAIT: + return UFS_CAL_NO_ERROR; + default: + break; + } +skip_rx_lane: + if (i < p->connected_rx_lane && cfg->lyr == PHY_PMA_TRSV_LANE1_SQ_OFF) + return UFS_CAL_NO_ERROR; + + if (i >= p->connected_rx_lane && cfg->lyr == PHY_PMA_TRSV_SQ) + return UFS_CAL_NO_ERROR; + + return __config_uic(handle, i, cfg, p); +} + +static enum ufs_cal_errno ufs_cal_config_uic(struct ufs_cal_param *p, + const struct ufs_cal_phy_cfg *cfg, + struct uic_pwr_mode *pmd) +{ + enum ufs_cal_errno ret = UFS_CAL_INV_ARG; + u8 i = 0; + + if (!cfg) + goto out; + + ret = UFS_CAL_NO_ERROR; + for (; cfg->lyr != PHY_CFG_NONE; cfg++) { + for (i = 0; i < p->available_lane; i++) { + ret = do_cal_config_uic(i, p, cfg, pmd); + if (ret != UFS_CAL_NO_ERROR) + goto out; + } + } +out: + return ret; +} + +/* + * public functions + */ +enum ufs_cal_errno ufs_cal_loopback_init(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + cfg = p->tbl == HOST_CARD ? loopback_init_card : loopback_init; + return ufs_cal_config_uic(p, cfg, NULL); +} + +enum ufs_cal_errno ufs_cal_loopback_set_1(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + cfg = p->tbl == HOST_CARD ? loopback_set_1_card : loopback_set_1; + return ufs_cal_config_uic(p, cfg, NULL); +} + +enum ufs_cal_errno ufs_cal_loopback_set_2(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + cfg = p->tbl == HOST_CARD ? loopback_set_2_card : loopback_set_2; + return ufs_cal_config_uic(p, cfg, NULL); +} + +enum ufs_cal_errno ufs_cal_post_h8_enter(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + cfg = p->tbl == HOST_CARD ? post_h8_enter_card : post_h8_enter; + return ufs_cal_config_uic(p, cfg, p->pmd); +} + +enum ufs_cal_errno ufs_cal_pre_h8_exit(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + cfg = p->tbl == HOST_CARD ? pre_h8_exit_card : pre_h8_exit; + return ufs_cal_config_uic(p, cfg, p->pmd); +} + +/* + * This currently uses only SLOW_MODE and FAST_MODE. + * If you want others, you should modify this function. + */ +enum ufs_cal_errno ufs_cal_pre_pmc(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + struct ufs_vs_handle *handle = p->handle; + u32 dl_error; + + /* block PA_ERROR_IND_RECEIVED */ + dl_error = unipro_readl(handle, UNIP_DL_ERROR_IRQ_MASK) | + PA_ERROR_IND_RECEIVED; + unipro_writel(handle, dl_error, UNIP_DL_ERROR_IRQ_MASK); + + if (p->pmd->mode == SLOW_MODE || p->pmd->mode == SLOWAUTO_MODE) + cfg = (p->tbl == HOST_CARD) ? calib_of_pwm_card : calib_of_pwm; + else if (p->pmd->hs_series == PA_HS_MODE_B) + cfg = (p->tbl == HOST_CARD) ? calib_of_hs_rate_b_card : + calib_of_hs_rate_b; + else if (p->pmd->hs_series == PA_HS_MODE_A) + cfg = (p->tbl == HOST_CARD) ? calib_of_hs_rate_a_card : + calib_of_hs_rate_a; + else + return UFS_CAL_INV_ARG; + + return ufs_cal_config_uic(p, cfg, p->pmd); +} + +/* + * This currently uses only SLOW_MODE and FAST_MODE. + * If you want others, you should modify this function. + */ +enum ufs_cal_errno ufs_cal_post_pmc(struct ufs_cal_param *p) +{ + enum ufs_cal_errno ret = UFS_CAL_NO_ERROR; + const struct ufs_cal_phy_cfg *cfg; + + if (p->pmd->mode == SLOWAUTO_MODE || p->pmd->mode == SLOW_MODE) + cfg = (p->tbl == HOST_CARD) ? post_calib_of_pwm_card : + post_calib_of_pwm; + else if (p->pmd->hs_series == PA_HS_MODE_B) + cfg = (p->tbl == HOST_CARD) ? post_calib_of_hs_rate_b_card : + post_calib_of_hs_rate_b; + else if (p->pmd->hs_series == PA_HS_MODE_A) + cfg = (p->tbl == HOST_CARD) ? post_calib_of_hs_rate_a_card : + post_calib_of_hs_rate_a; + else + return UFS_CAL_INV_ARG; + + ret = ufs_cal_config_uic(p, cfg, p->pmd); + + return ret; +} + +enum ufs_cal_errno ufs_cal_post_link(struct ufs_cal_param *p) +{ + enum ufs_cal_errno ret = UFS_CAL_NO_ERROR; + const struct ufs_cal_phy_cfg *cfg; + + switch (p->max_gear) { + case GEAR_1: + case GEAR_2: + case GEAR_3: + case GEAR_4: + if (p->evt_ver == 0) + cfg = (p->tbl == HOST_CARD) ? post_init_cfg_card : + post_init_cfg_evt0; + else + cfg = (p->tbl == HOST_CARD) ? post_init_cfg_card : + post_init_cfg_evt1; + break; + default: + ret = UFS_CAL_INV_ARG; + break; + } + + if (ret) + return ret; + + ret = ufs_cal_config_uic(p, cfg, NULL); + + /* + * If a number of target lanes is 1 and a host's + * a number of available lanes is 2, + * you should turn off phy power of lane #1. + * + * This must be modified when a number of available lanes + * would grow in the future. + */ + if (ret == UFS_CAL_NO_ERROR) { + if (p->available_lane == 2 && p->connected_rx_lane == 1) { + cfg = (p->tbl == HOST_CARD) ? + lane1_sq_off_card : lane1_sq_off; + ret = ufs_cal_config_uic(p, cfg, NULL); + } + } + + /* eom */ + p->eom_sz = EOM_PH_SEL_MAX * EOM_DEF_VREF_MAX * + ufs_s_eom_repeat[p->max_gear]; + + return ret; +} + +enum ufs_cal_errno ufs_cal_pre_link(struct ufs_cal_param *p) +{ + const struct ufs_cal_phy_cfg *cfg; + + /* preset mclk periods */ + p->mclk_period = __get_mclk_period(p); + p->mclk_period_rnd_off = __get_mclk_period_rnd_off(p); + p->mclk_period_unipro_18 = __get_mclk_period_unipro_18(p); + + if (p->evt_ver == 0) + cfg = (p->tbl == HOST_CARD) ? init_cfg_card : init_cfg_evt0; + else + cfg = (p->tbl == HOST_CARD) ? init_cfg_card : init_cfg_evt1; + + return ufs_cal_config_uic(p, cfg, NULL); +} + +static enum ufs_cal_errno ufs_cal_eom_prepare(struct ufs_cal_param *p) +{ + return ufs_cal_config_uic(p, eom_prepare, p->pmd); +} + +static u32 ufs_cal_get_eom_err_cnt(struct ufs_vs_handle *handle, u32 lane_loop) +{ + return (pma_readl(handle, + PHY_PMA_TRSV_ADDR(0xD20, lane_loop)) << 16) + + (pma_readl(handle, PHY_PMA_TRSV_ADDR(0xD24, lane_loop)) << 8) + + (pma_readl(handle, PHY_PMA_TRSV_ADDR(0xD28, lane_loop))); +} + +static void ufs_cal_sweep_get_eom_data(struct ufs_vs_handle *handle, u32 *cnt, + struct ufs_cal_param *p, u32 lane, + u32 repeat) +{ + u32 phase, vref; + u32 errors; + struct ufs_eom_result_s *data = p->eom[lane]; + + for (phase = 0; phase < EOM_PH_SEL_MAX; phase++) { + pma_writel(handle, phase, PHY_PMA_TRSV_ADDR(0xB78, lane)); + + for (vref = 0; vref < EOM_DEF_VREF_MAX; vref++) { + pma_writel(handle, 0x18, + PHY_PMA_TRSV_ADDR(0xB5C, lane)); + pma_writel(handle, vref, + PHY_PMA_TRSV_ADDR(0xB74, lane)); + pma_writel(handle, 0x19, + PHY_PMA_TRSV_ADDR(0xB5C, lane)); + + errors = ufs_cal_get_eom_err_cnt(handle, lane); + + if (handle->udelay) + handle->udelay(1); + + data[*cnt].v_phase = + phase + (repeat * EOM_PH_SEL_MAX); + data[*cnt].v_vref = vref; + data[*cnt].v_err = errors; + (*cnt)++; + } + } +} + +enum ufs_cal_errno ufs_cal_eom(struct ufs_cal_param *p) +{ + u32 repeat, lane; + + ufs_cal_eom_prepare(p); + + repeat = (p->max_gear < GEAR_MAX) ? ufs_s_eom_repeat[p->max_gear] : 0; + if (repeat == 0) + return UFS_CAL_ERROR; + if (repeat > EOM_RTY_MAX) + return UFS_CAL_INV_CONF; + + for (lane = 0; lane < p->available_lane; lane++) { + u32 cnt = 0; + u32 i; + + for (i = 0; i < repeat; i++) + ufs_cal_sweep_get_eom_data(p->handle, &cnt, p, lane, i); + } + return UFS_CAL_NO_ERROR; +} + +enum ufs_cal_errno ufs_cal_init(struct ufs_cal_param *p, int idx) +{ + /* + * Return if innput index is greater than + * the maximum that cal supports + */ + if (idx >= NUM_OF_UFS_HOST) + return UFS_CAL_INV_ARG; + + ufs_cal[idx] = p; + + return UFS_CAL_NO_ERROR; +} diff --git a/drivers/scsi/ufs/gs201/ufs-cal-if.h b/drivers/scsi/ufs/gs201/ufs-cal-if.h new file mode 100644 index 000000000000..4e4056109643 --- /dev/null +++ b/drivers/scsi/ufs/gs201/ufs-cal-if.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * + * Authors: + * Kiwoong + */ + +#ifndef _GS201_UFS_CAL_IF_H +#define _GS201_UFS_CAL_IF_H + +#undef BIT +#define BIT(a) (1U << (a)) + +struct uic_pwr_mode { + u8 lane; + u8 gear; + u8 mode; + u8 hs_series; +}; + +enum { + HOST_EMBD = 0, + HOST_CARD = 1, +}; + +enum { + EOM_RTY_G1 = 8, + EOM_RTY_G2 = 4, + EOM_RTY_G3 = 2, + EOM_RTY_G4 = 1, + EOM_RTY_MAX = 8, +}; + +enum { + GEAR_1 = 1, + GEAR_2, + GEAR_3, + GEAR_4, + GEAR_MAX = GEAR_4, +}; + +extern const u32 ufs_s_eom_repeat[GEAR_MAX + 1]; + +#define MAX_LANE 4 + +#define EOM_PH_SEL_MAX 72 +#define EOM_DEF_VREF_MAX 256 +#define EOM_MAX_SIZE (EOM_RTY_MAX * EOM_PH_SEL_MAX * \ + EOM_DEF_VREF_MAX) + +struct ufs_eom_result_s { + u32 v_phase; + u32 v_vref; + u32 v_err; +}; + +/* interface */ +struct ufs_cal_param { + /* input */ + struct ufs_vs_handle *handle; + u8 available_lane; + u8 connected_tx_lane; + u8 connected_rx_lane; + u8 active_tx_lane; + u8 active_rx_lane; + u32 mclk_rate; + u8 tbl; + u8 board; + u8 evt_ver; + u8 max_gear; + struct uic_pwr_mode *pmd; + + /* output */ + u32 eom_sz; + struct ufs_eom_result_s *eom[MAX_LANE]; /* per lane */ + + /* private data */ + u32 mclk_period; + u32 mclk_period_rnd_off; + u32 mclk_period_unipro_18; +}; + +enum ufs_cal_errno { + UFS_CAL_NO_ERROR = 0, + UFS_CAL_TIMEOUT, + UFS_CAL_ERROR, + UFS_CAL_INV_ARG, + UFS_CAL_INV_CONF, +}; + +enum { + __BRD_SMDK, + __BRD_ASB, + __BRD_HSIE, + __BRD_ZEBU, + __BRD_UNIV, + __BRD_MAX, +}; + +#define BRD_SMDK BIT(__BRD_SMDK) +#define BRD_ASB BIT(__BRD_ASB) +#define BRD_HSIE BIT(__BRD_HSIE) +#define BRD_ZEBU BIT(__BRD_ZEBU) +#define BRD_UNIV BIT(__BRD_UNIV) +#define BRD_MAX BIT(__BRD_MAX) +#define BRD_ALL (BIT(__BRD_MAX) - 1) + +/* UFS CAL interface */ +typedef enum ufs_cal_errno (*cal_if_func_init) (struct ufs_cal_param *, int); +typedef enum ufs_cal_errno (*cal_if_func) (struct ufs_cal_param *); +enum ufs_cal_errno ufs_cal_post_h8_enter(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_pre_h8_exit(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_post_pmc(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_pre_pmc(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_post_link(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_pre_link(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_init(struct ufs_cal_param *p, int idx); +enum ufs_cal_errno ufs_cal_eom(struct ufs_cal_param *p); + +enum ufs_cal_errno ufs_cal_loopback_init(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_loopback_set_1(struct ufs_cal_param *p); +enum ufs_cal_errno ufs_cal_loopback_set_2(struct ufs_cal_param *p); +#endif /*_GS201_UFS_CAL_IF_H */ diff --git a/drivers/scsi/ufs/gs201/ufs-cal.h b/drivers/scsi/ufs/gs201/ufs-cal.h new file mode 100644 index 000000000000..4e496cd672a6 --- /dev/null +++ b/drivers/scsi/ufs/gs201/ufs-cal.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UFS Host Controller driver for Exynos specific extensions + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * + * Authors: + * Kiwoong + */ + +#ifndef _GS201_UFS_CAL_H +#define _GS201_UFS_CAL_H + +#define UFS_CAL_VER 0 + +struct ufs_cal_phy_cfg { + u32 mib; + u32 addr; + u32 val; + u32 flg; + u32 lyr; + u8 board; +}; + +enum { + PHY_CFG_NONE = 0, + PHY_PCS_COMN, + PHY_PCS_RXTX, + PHY_PMA_COMN, + PHY_PMA_TRSV, + PHY_PLL_WAIT, + PHY_CDR_WAIT, + PHY_CDR_AFC_WAIT, + UNIPRO_STD_MIB, + UNIPRO_DBG_MIB, + UNIPRO_DBG_APB, + + PHY_PCS_RX, + PHY_PCS_TX, + PHY_PCS_RX_PRD, + PHY_PCS_TX_PRD, + UNIPRO_DBG_PRD, + PHY_PMA_TRSV_LANE1_SQ_OFF, + PHY_PMA_TRSV_SQ, + COMMON_WAIT, + + PHY_PCS_RX_LR_PRD, + PHY_PCS_TX_LR_PRD, + PHY_PCS_RX_PRD_ROUND_OFF, + PHY_PCS_TX_PRD_ROUND_OFF, + UNIPRO_ADAPT_LENGTH, + PHY_EMB_CDR_WAIT, + PHY_EMB_CAL_WAIT, +}; + +enum { + PMD_PWM_G1 = 0, + PMD_PWM_G2, + PMD_PWM_G3, + PMD_PWM_G4, + PMD_PWM_G5, + PMD_PWM, + + PMD_HS_G1, + PMD_HS_G2, + PMD_HS_G3, + PMD_HS_G4, + PMD_HS, + + PMD_ALL, +}; + +#define USE_19_2_MHZ 0 /* 19.2MHz */ +#define USE_26_0_MHZ 1 /* 26.0MHz */ +#define USE_38_4_MHZ 2 /* 38.4MHz */ + +#define USE_UFS_REFCLK USE_38_4_MHZ + +#endif /* _GS201_UFS_CAL_H */ diff --git a/drivers/scsi/ufs/gs201/ufs-pixel-fips.c b/drivers/scsi/ufs/gs201/ufs-pixel-fips.c new file mode 100644 index 000000000000..912979042b63 --- /dev/null +++ b/drivers/scsi/ufs/gs201/ufs-pixel-fips.c @@ -0,0 +1,677 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pixel-Specific UFS feature support + * + * Copyright 2021 Google LLC + * + * Authors: Konstantin Vyshetsky + * Version: 2.0.0 + */ + +#include +#include +#include +#include +#include +#include "ufs-pixel-fips.h" +#include "ufs-pixel-fips_sha256.h" + +#undef pr_fmt +#define pr_fmt(fmt) "ufs-pixel-fips140: " fmt + +/* + * As the verification logic will run before GPT data is available, module + * params are passed to cmdline from bootloader + */ +static u32 fips_first_lba; +module_param(fips_first_lba, uint, 0444); +MODULE_PARM_DESC(fips_first_lba, "First LBA of FIPS partition"); +static u32 fips_last_lba; +module_param(fips_last_lba, uint, 0444); +MODULE_PARM_DESC(fips_last_lba, "Last LBA of FIPS partition"); +static u32 fips_lu; +module_param(fips_lu, uint, 0444); +MODULE_PARM_DESC(fips_lu, "FIPS partition LUN"); + +#define UFS_PIXEL_UCD_SIZE (4096) +#define UFS_PIXEL_BUFFER_SIZE (4096) +#define UFS_PIXEL_MASTER_KEY_INDEX (15) +#define UTRD_CMD_TYPE_UFS_STORAGE (1 << 28) +#define UTRD_DD_SYSTEM_TO_DEVICE (1 << 25) /* Write */ +#define UTRD_DD_DEVICE_TO_SYSTEM (1 << 26) /* Read */ +#define UTRD_CRYPTO_DISABLE (0) +#define UTRD_CRYPTO_ENABLE (1 << 23) +#define PRDT_FAS_XTS (2 << 28) /* File Algorithm Selector */ +#define PRDT_FKL_256 (1 << 26) /* File Key Length */ +#define SENSE_DATA_ALLOC_LEN (18) +#define UPIU_TT_COMMAND (1) +#define IO_COMPLETION_TIMEOUT_MS (200) +#define IO_RETRY_COUNT (25) +#define SG_ENTRY_IV_NUM_WORDS (4) +#define SG_ENTRY_ENCKEY_NUM_WORDS (8) +#define SG_ENTRY_TWKEY_NUM_WORDS (8) + +struct fips_buffer_info { + void *io_buffer; + struct utp_transfer_cmd_desc *ucd_addr; + dma_addr_t io_buffer_dma_addr; + dma_addr_t ucd_dma_addr; +}; + +struct pixel_ufs_prdt_entry { + /* The first four fields correspond to those of ufshcd_sg_entry. */ + __le32 des0; + __le32 des1; + __le32 des2; + /* + * The crypto enable bit and keyslot are configured in the high bits of + * des3, whose low bits already contain ufshcd_sg_entry::size. + */ +#define CRYPTO_ENABLE (1U << 31) +#define CRYPTO_KEYSLOT(keyslot) ((keyslot) << 18) + __le32 des3; + + /* The IV with all bytes reversed */ + __be32 file_iv[SG_ENTRY_IV_NUM_WORDS]; + + /* Unused (when KE=0) */ + __le32 nonce[4]; + + /* Unused */ + __le32 reserved[20]; +}; + +struct sense_data { + u8 data[SENSE_DATA_ALLOC_LEN]; +}; + +struct scsi_cdb { + u8 op_code; + u8 dword1; + __be32 lba; + u8 dword6; + __be16 transfer_len; + u8 dword9; +} __packed; + +struct upiu_header { + /* DWORD 0 */ + u8 transaction_type; + u8 flags; + u8 lun; + u8 task_tag; + /* DWORD 1 */ + u8 rsvd; // 4 bit initiator_id + 4 bit cmd_set_type + u8 function; + u8 response; + u8 status; + /* DWORD 2 */ + u8 total_ehs_len; + u8 device_info; + __be16 data_segment_len; + /* DWORD 3 - 7 */ + struct { + __be32 edtl; // Expected Data Transfer Length + struct scsi_cdb cdb; // SCSI Command Descriptor Block + }; +} __packed; + +struct upiu { + struct upiu_header header; + __be16 sense_data_length; + struct sense_data sense_data; +} __packed; + +static void ufs_pixel_fips_build_utrd(struct ufs_hba *hba, + struct utp_transfer_req_desc *utrd, + dma_addr_t ucd_dma_addr, + u32 data_direction, u32 crypto) +{ + u16 response_offset = + offsetof(struct utp_transfer_cmd_desc, response_upiu); + u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); + u16 prdt_length = sizeof(struct pixel_ufs_prdt_entry); + + memset(utrd, 0, sizeof(struct utp_transfer_req_desc)); + + utrd->header.dword_0 = cpu_to_le32(UTRD_CMD_TYPE_UFS_STORAGE | + data_direction | crypto); + utrd->header.dword_1 = 0; + utrd->header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS); + utrd->header.dword_3 = 0; + + utrd->command_desc_base_addr_lo = + cpu_to_le32(lower_32_bits(ucd_dma_addr)); + utrd->command_desc_base_addr_hi = + cpu_to_le32(upper_32_bits(ucd_dma_addr)); + + if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { + utrd->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE); + utrd->response_upiu_offset = cpu_to_le16(response_offset); + utrd->prd_table_offset = cpu_to_le16(prdt_offset); + utrd->prd_table_length = cpu_to_le16(prdt_length); + } else { + utrd->response_upiu_length = + cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); + utrd->response_upiu_offset = cpu_to_le16(response_offset >> 2); + utrd->prd_table_offset = cpu_to_le16(prdt_offset >> 2); + utrd->prd_table_length = cpu_to_le16(1); + } +} + +static void ufs_pixel_fips_build_prdt(struct ufs_hba *hba, + struct utp_transfer_cmd_desc *ucd_addr, + dma_addr_t buffer_dma_addr, + u32 buffer_len, u32 mki, const u8 *iv) +{ + struct pixel_ufs_prdt_entry *sg_entry = + (struct pixel_ufs_prdt_entry *)ucd_addr->prd_table; + + sg_entry->des0 = cpu_to_le32(lower_32_bits(buffer_dma_addr)); + sg_entry->des1 = cpu_to_le32(upper_32_bits(buffer_dma_addr)); + sg_entry->des2 = 0; + if (!iv) { + sg_entry->des3 = cpu_to_le32(buffer_len - 1); + } else { + u32 i; + + sg_entry->des3 = cpu_to_le32(CRYPTO_ENABLE | + CRYPTO_KEYSLOT(mki) | + (buffer_len - 1)); + + for (i = 0; i < SG_ENTRY_IV_NUM_WORDS; i++) { + sg_entry->file_iv[SG_ENTRY_IV_NUM_WORDS - 1 - i] = + get_unaligned_be32(&iv[i * 4]); + } + } +} + +static void ufs_pixel_fips_build_upiu(struct ufs_hba *hba, + struct utp_transfer_cmd_desc *ucd_addr, + struct scsi_cdb *cdb, u16 flags, u32 lun, + u32 buffer_len, u8 task_tag) +{ + struct utp_upiu_req *ucd_req_ptr = + (struct utp_upiu_req *)ucd_addr->command_upiu; + + ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD( + UPIU_TRANSACTION_COMMAND, flags, lun, task_tag); + ucd_req_ptr->header.dword_1 = 0; + ucd_req_ptr->header.dword_2 = 0; + ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(buffer_len); + memcpy(ucd_req_ptr->sc.cdb, cdb, sizeof(struct scsi_cdb)); +} + +static int ufs_pixel_fips_send_utrd(struct ufs_hba *hba, + struct utp_transfer_req_desc *utrd, + u8 task_tag) +{ + struct utp_transfer_req_desc utrd_temp; + unsigned long timeout; + u32 tr_doorbell; + + memcpy(&utrd_temp, hba->utrdl_base_addr + task_tag, + sizeof(struct utp_transfer_req_desc)); + memcpy(hba->utrdl_base_addr + task_tag, utrd, + sizeof(struct utp_transfer_req_desc)); + + if (hba->vops && hba->vops->setup_xfer_req) + hba->vops->setup_xfer_req(hba, task_tag, true); + + ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL); + + /* Make sure that doorbell is committed immediately */ + wmb(); + + /* Wait for completion */ + timeout = jiffies + msecs_to_jiffies(IO_COMPLETION_TIMEOUT_MS); + while (time_before(jiffies, timeout)) { + tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); + if (!tr_doorbell) + break; + + usleep_range(50, 100); + } + + memcpy(utrd, hba->utrdl_base_addr + task_tag, + sizeof(struct utp_transfer_req_desc)); + memcpy(hba->utrdl_base_addr + task_tag, &utrd_temp, + sizeof(struct utp_transfer_req_desc)); + + if (tr_doorbell) { + pr_err("Request timed out\n"); + return -ETIMEDOUT; + } + + return 0; +} + +int ufs_pixel_fips_send_request(struct ufs_hba *hba, struct scsi_cdb *cdb, + struct fips_buffer_info *bi, u32 buffer_len, + u32 lu, u32 mki, const u8 *iv) +{ + struct utp_transfer_req_desc utrd; + struct utp_upiu_rsp *resp_upiu = + (struct utp_upiu_rsp *)bi->ucd_addr->response_upiu; + u8 task_tag = 0x7; + u32 data_direction; + u32 flags; + u32 crypto; + int ret; + + memset(bi->ucd_addr, 0, UFS_PIXEL_UCD_SIZE); + + /* Build CDB */ + switch (cdb->op_code) { + case REQUEST_SENSE: + data_direction = UTRD_DD_DEVICE_TO_SYSTEM; + flags = UPIU_CMD_FLAGS_READ; + break; + case READ_10: + data_direction = UTRD_DD_DEVICE_TO_SYSTEM; + flags = UPIU_CMD_FLAGS_READ; + break; + case WRITE_10: + data_direction = UTRD_DD_SYSTEM_TO_DEVICE; + flags = UPIU_CMD_FLAGS_WRITE; + break; + default: + pr_err("unsupported scsi op code 0x%02x\n", cdb->op_code); + return -EBADRQC; + } + + /* Build UTRD */ + crypto = iv ? UTRD_CRYPTO_ENABLE : UTRD_CRYPTO_DISABLE; + ufs_pixel_fips_build_utrd(hba, &utrd, bi->ucd_dma_addr, data_direction, + crypto); + /* Build PRDT */ + ufs_pixel_fips_build_prdt(hba, bi->ucd_addr, bi->io_buffer_dma_addr, + buffer_len, mki, iv); + + /* Build UPIU */ + ufs_pixel_fips_build_upiu(hba, bi->ucd_addr, cdb, flags, lu, buffer_len, + task_tag); + + /* Make sure descriptors are ready before ringing the task doorbell */ + wmb(); + + /* Send */ + ret = ufs_pixel_fips_send_utrd(hba, &utrd, task_tag); + if (!ret) { + u8 ocs = le32_to_cpu(utrd.header.dword_2) & 0xFF; + u8 upiu_status = be32_to_cpu(resp_upiu->header.dword_1) & 0xFF; + u8 upiu_response = + (be32_to_cpu(resp_upiu->header.dword_1) >> 8) & 0xFF; + if (ocs || upiu_status || upiu_response) { + pr_err("Request failed OCS=%02X status=%02X resp=%02X\n", + ocs, upiu_status, upiu_response); + ret = -EIO; + } + } + + return ret; +} + +static int ufs_pixel_fips_request_sense(struct ufs_hba *hba, + struct fips_buffer_info *bi) +{ + struct scsi_cdb cdb = {}; + int ret; + + cdb.op_code = REQUEST_SENSE; + cdb.transfer_len = cpu_to_be16(SENSE_DATA_ALLOC_LEN); + + ret = ufs_pixel_fips_send_request(hba, &cdb, bi, SENSE_DATA_ALLOC_LEN, + fips_lu, 0, NULL); + + if (ret) + return -EIO; + + return 0; +} + +static int ufs_pixel_fips_send_io(struct ufs_hba *hba, + struct fips_buffer_info *bi, u32 mki, + const u8 *iv, u8 op_code) +{ + struct scsi_cdb cdb = {}; + int ret; + int retry = IO_RETRY_COUNT; + + cdb.op_code = op_code; + cdb.lba = cpu_to_be32(fips_first_lba); + cdb.transfer_len = cpu_to_be16(1); + + do { + ret = ufs_pixel_fips_send_request( + hba, &cdb, bi, UFS_PIXEL_BUFFER_SIZE, fips_lu, mki, iv); + } while (ret && retry-- > 0); + + if (ret) + return -EIO; + + return 0; +} + +static int ufs_pixel_fips_read(struct ufs_hba *hba, struct fips_buffer_info *bi, + u32 mki, const u8 *iv) +{ + return ufs_pixel_fips_send_io(hba, bi, mki, iv, READ_10); +} + +static int ufs_pixel_fips_write(struct ufs_hba *hba, + struct fips_buffer_info *bi, u32 mki, + const u8 *iv) +{ + return ufs_pixel_fips_send_io(hba, bi, mki, iv, WRITE_10); +} + +static const u8 pixel_fips_encryption_pt[] = { + 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, /* "This is " */ + 0x61, 0x20, 0x33, 0x32, 0x42, 0x20, 0x65, 0x6E, /* "a 32B en" */ + 0x63, 0x72, 0x79, 0x70, 0x74, 0x20, 0x70, 0x74, /* "crypt pt" */ + 0x20, 0x6D, 0x65, 0x73, 0x73, 0x61, 0x67, 0x65, /* " message" */ +}; + +static const u8 pixel_fips_encryption_ct[] = { + 0xEE, 0xD2, 0xD3, 0x69, 0xE9, 0x60, 0x48, 0xF1, + 0x26, 0xE8, 0xC6, 0xD7, 0x2E, 0xFB, 0x0C, 0x69, + 0x2A, 0xC4, 0xF4, 0x32, 0x58, 0xD0, 0x7B, 0xC2, + 0x75, 0xA9, 0xB0, 0x4B, 0x4E, 0x39, 0x31, 0x98, +}; + +static const u8 pixel_fips_encryption_key[] = { + 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, /* "This is " */ + 0x61, 0x20, 0x33, 0x32, 0x42, 0x20, 0x65, 0x6E, /* "a 32B en" */ + 0x63, 0x72, 0x79, 0x70, 0x74, 0x69, 0x6F, 0x6E, /* "cryption" */ + 0x20, 0x6B, 0x65, 0x79, 0x20, 0x77, 0x69, 0x74, /* " key wit" */ + 0x68, 0x20, 0x61, 0x20, 0x33, 0x32, 0x42, 0x20, /* "h a 32B " */ + 0x65, 0x6E, 0x63, 0x72, 0x79, 0x70, 0x74, 0x69, /* "encrypti" */ + 0x6F, 0x6E, 0x20, 0x74, 0x77, 0x65, 0x61, 0x6B, /* "on tweak" */ + 0x20, 0x6B, 0x65, 0x79, 0x20, 0x20, 0x20, 0x20, /* " key " */ +}; + +static const u8 pixel_fips_encryption_iv[] = { + 0x41, 0x20, 0x31, 0x36, 0x42, 0x20, 0x65, 0x6E, /* "A 16B en" */ + 0x63, 0x72, 0x79, 0x70, 0x74, 0x20, 0x49, 0x56, /* "crypt IV" */ +}; + +int ufs_pixel_fips_verify(struct ufs_hba *hba) +{ + int ret; + u32 interrupts; + struct fips_buffer_info bi; + const u32 mki = UFS_PIXEL_MASTER_KEY_INDEX; + + if (!fips_first_lba || !fips_last_lba || + fips_last_lba < fips_first_lba) { + pr_err("Invalid module params: first_lba=%u last_lba=%u\n", + fips_first_lba, fips_last_lba); + return -EINVAL; + } + + bi.io_buffer = dma_alloc_coherent(hba->dev, UFS_PIXEL_BUFFER_SIZE, + &bi.io_buffer_dma_addr, + GFP_NOIO | __GFP_NOFAIL); + if (!bi.io_buffer) + return -ENOMEM; + + bi.ucd_addr = dma_alloc_coherent(hba->dev, UFS_PIXEL_UCD_SIZE, + &bi.ucd_dma_addr, + GFP_NOIO | __GFP_NOFAIL); + if (!bi.ucd_addr) { + dma_free_coherent(hba->dev, UFS_PIXEL_BUFFER_SIZE, bi.io_buffer, + bi.io_buffer_dma_addr); + return -ENOMEM; + } + + /* + * Enable clocks, exit hibern8, set link as active + * Will release on function exit + */ + ufshcd_hold(hba, false); + + /* + * Disable all interrupts except UTP Transfer Request Completion + * Controller will not complete requests without this enabled + * Restore on function exit + */ + interrupts = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); + ufshcd_writel(hba, UTP_TRANSFER_REQ_COMPL, REG_INTERRUPT_ENABLE); + + ufs_pixel_fips_request_sense(hba, &bi); + + /* + * Verify Encryption: + * Write plaintext with specified crypto parameters, then read raw. + * Compare vs expected ciphertext. + */ + memset(bi.io_buffer, 0, UFS_PIXEL_BUFFER_SIZE); + memcpy(bi.io_buffer, pixel_fips_encryption_pt, + sizeof(pixel_fips_encryption_pt)); + + ret = ufs_pixel_fips_write(hba, &bi, mki, pixel_fips_encryption_iv); + if (ret) + goto out; + + memset(bi.io_buffer, 0, UFS_PIXEL_BUFFER_SIZE); + + ret = ufs_pixel_fips_read(hba, &bi, 0, NULL); + if (ret) + goto out; + + if (memcmp(bi.io_buffer, pixel_fips_encryption_ct, + sizeof(pixel_fips_encryption_ct))) { + pr_err("Encryption verification failed\n"); + ret = -EINVAL; + goto out; + } + pr_info("Encryption verification passed\n"); + + /* + * Verify Decryption: + * Since the ciphertext is already stored we just read back with the + * specified crypto parameters. + * Compare vs expected plaintext. + */ + memset(bi.io_buffer, 0, UFS_PIXEL_BUFFER_SIZE); + + ret = ufs_pixel_fips_read(hba, &bi, mki, pixel_fips_encryption_iv); + if (ret) + goto out; + + if (memcmp(bi.io_buffer, pixel_fips_encryption_pt, + sizeof(pixel_fips_encryption_pt))) { + pr_err("Decryption verification failed\n"); + ret = -EINVAL; + goto out; + } + pr_info("Decryption verification passed\n"); + +out: + ufshcd_writel(hba, interrupts, REG_INTERRUPT_ENABLE); + ufshcd_release(hba); + dma_free_coherent(hba->dev, UFS_PIXEL_UCD_SIZE, bi.ucd_addr, + bi.ucd_dma_addr); + dma_free_coherent(hba->dev, UFS_PIXEL_BUFFER_SIZE, bi.io_buffer, + bi.io_buffer_dma_addr); + + return ret; +} +EXPORT_SYMBOL_GPL(ufs_pixel_fips_verify); + +static int __init unapply_text_relocations(void *section, int section_size, + const Elf64_Rela *rela, int numrels) +{ + while (numrels--) { + u32 *place = (u32 *)(section + rela->r_offset); + + if (rela->r_offset >= section_size) { + pr_err("rela->r_offset(%llu) >= section_size(%u)", + rela->r_offset, section_size); + return -EINVAL; + } + + switch (ELF64_R_TYPE(rela->r_info)) { +#ifdef CONFIG_ARM64 + case R_AARCH64_JUMP26: + case R_AARCH64_CALL26: + *place &= ~GENMASK(25, 0); + break; + + case R_AARCH64_ADR_PREL_LO21: + case R_AARCH64_ADR_PREL_PG_HI21: + case R_AARCH64_ADR_PREL_PG_HI21_NC: + *place &= ~(GENMASK(30, 29) | GENMASK(23, 5)); + break; + + case R_AARCH64_ADD_ABS_LO12_NC: + case R_AARCH64_LDST8_ABS_LO12_NC: + case R_AARCH64_LDST16_ABS_LO12_NC: + case R_AARCH64_LDST32_ABS_LO12_NC: + case R_AARCH64_LDST64_ABS_LO12_NC: + case R_AARCH64_LDST128_ABS_LO12_NC: + *place &= ~GENMASK(21, 10); + break; + default: + pr_err("unhandled relocation type %llu\n", + ELF64_R_TYPE(rela->r_info)); + return -EINVAL; +#else +#error +#endif + } + rela++; + } + + return 0; +} + +static const u8 ufs_pixel_fips_hmac_message[] = { + 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, /* "This is " */ + 0x61, 0x20, 0x35, 0x38, 0x42, 0x20, 0x6D, 0x65, /* "a 58B me" */ + 0x73, 0x73, 0x61, 0x67, 0x65, 0x20, 0x66, 0x6F, /* "ssage fo" */ + 0x72, 0x20, 0x48, 0x4D, 0x41, 0x43, 0x20, 0x76, /* "r HMAC v" */ + 0x65, 0x72, 0x69, 0x66, 0x69, 0x63, 0x61, 0x74, /* "erificat" */ + 0x69, 0x6F, 0x6E, 0x20, 0x69, 0x6E, 0x20, 0x46, /* "ion in F" */ + 0x49, 0x50, 0x53, 0x20, 0x6D, 0x6F, 0x64, 0x75, /* "IPS modu" */ + 0x6C, 0x65, /* "le" */ +}; + +static const u8 ufs_pixel_fips_hmac_key[] = { + 0x54, 0x68, 0x69, 0x73, 0x20, 0x69, 0x73, 0x20, /* "This is " */ + 0x61, 0x20, 0x35, 0x34, 0x42, 0x20, 0x6B, 0x65, /* "a 54B ke" */ + 0x79, 0x20, 0x66, 0x6F, 0x72, 0x20, 0x48, 0x4D, /* "y for HM" */ + 0x41, 0x43, 0x20, 0x76, 0x65, 0x72, 0x69, 0x66, /* "AC verif" */ + 0x69, 0x63, 0x61, 0x74, 0x69, 0x6F, 0x6E, 0x20, /* "ication " */ + 0x69, 0x6E, 0x20, 0x46, 0x49, 0x50, 0x53, 0x20, /* "in FIPS " */ + 0x6D, 0x6F, 0x64, 0x75, 0x6C, 0x65, /* "module" */ +}; + +static const u8 ufs_pixel_fips_hmac_expected[] = { + 0x35, 0x3E, 0xA3, 0xB1, 0xEF, 0x1A, 0x79, 0x46, + 0xDA, 0x21, 0x27, 0x64, 0x8F, 0x37, 0x1D, 0xD2, + 0x5B, 0x5B, 0x84, 0xF3, 0x60, 0xB6, 0x95, 0x61, + 0xF9, 0x06, 0x07, 0x73, 0x18, 0x77, 0xB7, 0x1D, +}; + +u8 __initdata fips140_integ_hmac_key[] = { + 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x69, 0x63, /* "The quic" */ + 0x6B, 0x20, 0x62, 0x72, 0x6F, 0x77, 0x6E, 0x20, /* "k brown " */ + 0x66, 0x6F, 0x78, 0x20, 0x6A, 0x75, 0x6D, 0x70, /* "fox jump" */ + 0x73, 0x20, 0x6F, 0x76, 0x65, 0x72, 0x20, 0x74, /* "s over t" */ + 0x68, 0x65, 0x20, 0x6C, 0x61, 0x7A, 0x79, 0x20, /* "he lazy " */ + 0x64, 0x6F, 0x67, 0x00 /* "dog" */ +}; + +u8 __initdata fips140_integ_hmac_digest[UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE]; +const u8 __fips140_text_start __section(".text.._start"); +const u8 __fips140_text_end __section(".text.._end"); +const u8 __fips140_rodata_start __section(".rodata.._start"); +const u8 __fips140_rodata_end __section(".rodata.._end"); +const u8 *__ufs_pixel_text_start = &__fips140_text_start; +const u8 *__ufs_pixel_rodata_start = &__fips140_rodata_start; + +static int __init ufs_pixel_hmac_self_test(void) +{ + u8 hmac_digest[UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE]; + + ufs_pixel_fips_hmac_sha256(ufs_pixel_fips_hmac_message, + sizeof(ufs_pixel_fips_hmac_message), + ufs_pixel_fips_hmac_key, + sizeof(ufs_pixel_fips_hmac_key), + hmac_digest); + + return memcmp(hmac_digest, ufs_pixel_fips_hmac_expected, + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); +} +extern struct { + u32 offset; + u32 count; +} fips140_rela_text; + +static int __init ufs_pixel_self_integrity_test(void) +{ + u8 hmac_digest[UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE]; + size_t text_len; + size_t rodata_len; + void *hmac_buffer; + int ret; + + text_len = &__fips140_text_end - &__fips140_text_start; + rodata_len = &__fips140_rodata_end - &__fips140_rodata_start; + hmac_buffer = kmalloc(text_len + rodata_len, GFP_KERNEL); + if (!hmac_buffer) + return -ENOMEM; + + memcpy(hmac_buffer, __ufs_pixel_text_start, text_len); + memcpy(hmac_buffer + text_len, __ufs_pixel_rodata_start, rodata_len); + + ret = unapply_text_relocations(hmac_buffer, text_len, + offset_to_ptr(&fips140_rela_text.offset), + fips140_rela_text.count); + if (ret) { + kfree(hmac_buffer); + return ret; + } + + ufs_pixel_fips_hmac_sha256(hmac_buffer, text_len + rodata_len, + fips140_integ_hmac_key, + strlen(fips140_integ_hmac_key), hmac_digest); + + kfree(hmac_buffer); + + return memcmp(hmac_digest, fips140_integ_hmac_digest, + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); +} + +static int __init ufs_pixel_fips_init(void) +{ + /* Verify internal HMAC functionality */ + if (ufs_pixel_hmac_self_test()) { + pr_err("HMAC self test failed\n"); + return -EINVAL; + } + pr_info("HMAC self test passed\n"); + + /* Perform module self integrity check */ + if (ufs_pixel_self_integrity_test()) { + pr_err("Verify self HMAC failed\n"); + return -EINVAL; + } + pr_info("Verify self HMAC passed\n"); + + return 0; +} + +static void ufs_pixel_fips_exit(void) +{ +} + +module_init(ufs_pixel_fips_init); +module_exit(ufs_pixel_fips_exit); + +MODULE_DESCRIPTION( + "FIPS140-3 Compliant SW Driven UFS Inline Encryption Self Test Module"); +MODULE_AUTHOR("Konstantin Vyshetsky"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/scsi/ufs/gs201/ufs-vs-mmio.h b/drivers/scsi/ufs/gs201/ufs-vs-mmio.h new file mode 100644 index 000000000000..995c70c3b8f4 --- /dev/null +++ b/drivers/scsi/ufs/gs201/ufs-vs-mmio.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Samsung Electronics Co., Ltd. + * + * Authors: + * Kiwoong + */ + +#ifndef _GS201_UFS_VS_MMIO_H +#define _GS201_UFS_VS_MMIO_H + +struct ufs_vs_handle { + void *std; /* Need to care conditions */ + void *hci; + void *ufsp; + void *unipro; + void *pma; + void *cport; + void (*udelay)(u32 us); + void *private; +}; + +static inline void std_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + writel(val, handle->std + ofs); +} + +static inline u32 std_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + return readl(handle->std + ofs); +} + +static inline void hci_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + writel(val, handle->hci + ofs); +} + +static inline u32 hci_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + return readl(handle->hci + ofs); +} + +static inline void unipro_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + writel(val, handle->unipro + ofs); +} + +static inline u32 unipro_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + return readl(handle->unipro + ofs); +} + +static inline void cport_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + writel(val, handle->cport + ofs); +} + +static inline u32 cport_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + return readl(handle->cport + ofs); +} + +#if defined(__UFS_CAL_FW__) + +#undef CLKSTOP_CTRL +#undef MPHY_APBCLK_STOP + +#define CLKSTOP_CTRL 0x11B0 +#define MPHY_APBCLK_STOP (1<<3) + +static inline void pma_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + u32 clkstop_ctrl = readl((u8 *)handle->hci + CLKSTOP_CTRL); + + writel(clkstop_ctrl & ~MPHY_APBCLK_STOP, + (u8 *)handle->hci + CLKSTOP_CTRL); + writel(val, (u8 *)handle->pma + ofs); + writel(clkstop_ctrl | MPHY_APBCLK_STOP, + (u8 *)handle->hci + CLKSTOP_CTRL); +} + +static inline u32 pma_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + u32 clkstop_ctrl = readl((u8 *)handle->hci + CLKSTOP_CTRL); + u32 val; + + writel(clkstop_ctrl & ~MPHY_APBCLK_STOP, + (u8 *)handle->hci + CLKSTOP_CTRL); + val = readl((u8 *)handle->pma + ofs); + writel(clkstop_ctrl | MPHY_APBCLK_STOP, + (u8 *)handle->hci + CLKSTOP_CTRL); + return val; +} +#else +static inline void pma_writel(struct ufs_vs_handle *handle, u32 val, u32 ofs) +{ + writel(val, handle->pma + ofs); +} + +static inline u32 pma_readl(struct ufs_vs_handle *handle, u32 ofs) +{ + return readl(handle->pma + ofs); +} +#endif + +#endif /* _GS201_UFS_VS_MMIO_H */ diff --git a/drivers/scsi/ufs/ufs-cal-if.h b/drivers/scsi/ufs/ufs-cal-if.h index a4d7417d46f9..a8c82512a814 100644 --- a/drivers/scsi/ufs/ufs-cal-if.h +++ b/drivers/scsi/ufs/ufs-cal-if.h @@ -8,6 +8,8 @@ #ifdef CONFIG_SOC_GS101 #include "gs101/ufs-cal-if.h" +#elif CONFIG_SOC_GS201 +#include "gs201/ufs-cal-if.h" #endif #endif /*_UFS_CAL_IF_H */ diff --git a/drivers/scsi/ufs/ufs-exynos-fmp.c b/drivers/scsi/ufs/ufs-exynos-fmp.c index b14ffb6d02f6..a36b82242132 100644 --- a/drivers/scsi/ufs/ufs-exynos-fmp.c +++ b/drivers/scsi/ufs/ufs-exynos-fmp.c @@ -193,7 +193,7 @@ static void exynos_ufs_fmp_fill_prdt(void *unused, struct ufs_hba *hba, } } -#if IS_ENABLED(CONFIG_SCSI_UFS_PIXEL_FIPS140) +#if IS_ENABLED(CONFIG_SCSI_UFS_PIXEL_FIPS140) && IS_ENABLED(CONFIG_SOC_GS101) static void exynos_ufs_fmp_fips_self_test(void *data, struct ufs_hba *hba) { if (ufs_pixel_fips_verify(hba)) @@ -210,4 +210,4 @@ static int exynos_ufs_fmp_register_fips_self_test(void) { return 0; } -#endif \ No newline at end of file +#endif diff --git a/drivers/scsi/ufs/ufs-exynos.c b/drivers/scsi/ufs/ufs-exynos.c index 192d2ea1e8f8..bed77cef759e 100644 --- a/drivers/scsi/ufs/ufs-exynos.c +++ b/drivers/scsi/ufs/ufs-exynos.c @@ -506,6 +506,9 @@ static int exynos_ufs_init(struct ufs_hba *hba) pixel_init_io_stats(hba); + // disable hpb1.0 support + hba->ufshpb_dev.hpb_disabled = true; + return 0; } @@ -749,7 +752,7 @@ static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba, } static void exynos_ufs_set_nexus_t_xfer_req(struct ufs_hba *hba, - int tag, bool cmd) + int tag, bool is_scsi_cmd) { struct exynos_ufs *ufs = to_exynos_ufs(hba); u32 type; @@ -762,7 +765,7 @@ static void exynos_ufs_set_nexus_t_xfer_req(struct ufs_hba *hba, type = hci_readl(&ufs->handle, HCI_UTRL_NEXUS_TYPE); - if (cmd) + if (is_scsi_cmd) type |= (1 << tag); else type &= ~(1 << tag); @@ -859,8 +862,12 @@ static int __exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op, { struct exynos_ufs *ufs = to_exynos_ufs(hba); - if (status == PRE_CHANGE) + if (status == PRE_CHANGE) { + /* TODO: should check enabling runtime PM later. */ + if (pm_op == UFS_RUNTIME_PM) + return -EINVAL; return 0; + } if (!IS_C_STATE_ON(ufs) || ufs->h_state != H_HIBERN8) @@ -1074,6 +1081,7 @@ static int exynos_ufs_populate_dt(struct device *dev, struct device_node *np = dev->of_node; struct device_node *child_np; int ret; + u32 soc_rev; /* Regmap for external regions */ ret = exynos_ufs_populate_dt_extern(dev, ufs); @@ -1084,8 +1092,8 @@ static int exynos_ufs_populate_dt(struct device *dev, } /* Get exynos-evt version for featuring */ - if (of_property_read_u8(np, "evt-ver", &ufs->cal_param.evt_ver)) - ufs->cal_param.evt_ver = 0; + soc_rev = gs_chipid_get_revision(); + ufs->cal_param.evt_ver = (u8)(soc_rev >> 4); /* PM QoS */ child_np = of_get_child_by_name(np, "ufs-pm-qos"); diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h index 469d00b3b76b..158a6b940f05 100644 --- a/drivers/scsi/ufs/ufs-exynos.h +++ b/drivers/scsi/ufs/ufs-exynos.h @@ -162,6 +162,9 @@ struct exynos_ufs { u64 slowio_min_us; u64 slowio[PIXEL_SLOWIO_OP_MAX][PIXEL_SLOWIO_SYS_MAX]; + /* pixel ufs power related statistics */ + struct pixel_power_stats power_stats; + /* Pointer to GSA device */ struct device *gsa_dev; @@ -171,6 +174,9 @@ struct exynos_ufs { /* ufs command logging */ u8 enable_cmd_log; struct pixel_cmd_log cmd_log; + + /* Used to enable WB on all write requests */ + bool always_use_wb; }; static inline struct exynos_ufs *to_exynos_ufs(struct ufs_hba *hba) @@ -200,4 +206,5 @@ static inline void pixel_ufs_crypto_resume(struct ufs_hba *hba) { } #endif /* !CONFIG_SCSI_UFS_CRYPTO */ +extern u32 gs_chipid_get_revision(void); #endif /* _UFS_EXYNOS_H_ */ diff --git a/drivers/scsi/ufs/ufs-pixel-acvp.c b/drivers/scsi/ufs/ufs-pixel-acvp.c new file mode 100644 index 000000000000..2388b44fe1cc --- /dev/null +++ b/drivers/scsi/ufs/ufs-pixel-acvp.c @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pixel-Specific UFS feature support + * + * Copyright 2021 Google LLC + * + * Authors: Konstantin Vyshetsky + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "ufs-pixel-acvp.h" +#include "ufs-pixel-fips_sha256.h" + +#undef pr_fmt +#define pr_fmt(fmt) "ufs-pixel-acvp: " fmt + +#define UFS_PIXEL_ACVP_PARTITION "/dev/block/by-name/fips" +#define UFS_PIXEL_ACVP_LBA 0 +#define UFS_PIXEL_ACVP_NAME "fmp_acvp" +#define UFS_PIXEL_ACVP_AES_256_XTS_KEY_LEN 64 +#define UFS_PIXEL_ACVP_AES_256_XTS_IV_LEN 16 +#define UFS_PIXEL_ACVP_AES_MAX_INPUT_LEN 4096 +#define UFS_PIXEL_ACVP_AES_MIN_ALIGN 16 +#define UFS_PIXEL_ACVP_HASH_MAX_INPUT_LEN 65536 +#define UFS_PIXEL_ACVP_HASH_MAX_KEY_LEN 4096 + +struct acvp_crypto_ctx { + struct blk_crypto_key bc_key; + u8 raw_key[UFS_PIXEL_ACVP_AES_256_XTS_KEY_LEN]; + u64 bc_dun[BLK_CRYPTO_DUN_ARRAY_SIZE]; +}; + +static struct { + struct miscdevice miscdev; + struct block_device *bdev; + struct page *io_page; + struct page *crypto_page; + void *io_addr; + struct acvp_crypto_ctx *acvp_crypto_ctx; +} acvp_ctx; + +struct aes_req_int { + void __user *src_ptr; + void __user *dst_ptr; + void __user *key_ptr; + void __user *iv_ptr; + __u32 src_len; + __u32 dst_len; + __u32 key_len; + __u32 iv_len; + __u32 aes_direction; + __u32 aes_algorithm; +}; + +struct hash_req_int { + void __user *src_ptr; + void __user *dst_ptr; + void __user *key_ptr; + __u32 src_len; + __u32 key_len; + __u32 hash_type; +}; + +static int ufs_pixel_acvp_get_aes_req(unsigned long src, + struct aes_req_int *aes_req_int) +{ + struct ufs_pixel_acvp_aes_req aes_req; + + if (unlikely(copy_from_user(&aes_req, (void __user *)src, + sizeof(aes_req)))) + return -EFAULT; + + aes_req_int->src_ptr = u64_to_user_ptr(aes_req.src_ptr); + aes_req_int->dst_ptr = u64_to_user_ptr(aes_req.dst_ptr); + aes_req_int->key_ptr = u64_to_user_ptr(aes_req.key_ptr); + aes_req_int->iv_ptr = u64_to_user_ptr(aes_req.iv_ptr); + aes_req_int->src_len = aes_req.src_len; + aes_req_int->dst_len = aes_req.dst_len; + aes_req_int->key_len = aes_req.key_len; + aes_req_int->iv_len = aes_req.iv_len; + aes_req_int->aes_direction = aes_req.aes_direction; + aes_req_int->aes_algorithm = aes_req.aes_algorithm; + + return 0; +} + +static int ufs_pixel_acvp_get_hash_req(unsigned long src, + struct hash_req_int *hash_req_int) +{ + struct ufs_pixel_acvp_hash_req hash_req; + + if (unlikely(copy_from_user(&hash_req, (void __user *)src, + sizeof(hash_req)))) + return -EFAULT; + + hash_req_int->src_ptr = u64_to_user_ptr(hash_req.src_ptr); + hash_req_int->dst_ptr = u64_to_user_ptr(hash_req.dst_ptr); + hash_req_int->key_ptr = u64_to_user_ptr(hash_req.key_ptr); + hash_req_int->src_len = hash_req.src_len; + hash_req_int->key_len = hash_req.key_len; + hash_req_int->hash_type = hash_req.hash_type; + + return 0; +} + +static int ufs_pixel_acvp_send_io(struct page *page, unsigned int bi_opf, + struct acvp_crypto_ctx *crypto_ctx) +{ + struct bio *bio; + int ret; + + bio = bio_alloc(GFP_KERNEL, 1); + + bio_set_dev(bio, acvp_ctx.bdev); + bio->bi_iter.bi_sector = UFS_PIXEL_ACVP_LBA; + bio->bi_opf = bi_opf; + bio_add_page(bio, page, PAGE_SIZE, 0); + + if (crypto_ctx) + bio_crypt_set_ctx(bio, &crypto_ctx->bc_key, crypto_ctx->bc_dun, + GFP_KERNEL); + + ret = submit_bio_wait(bio); + bio_put(bio); + + return ret; +} + +static int ufs_pixel_acvp_write(struct page *page, + struct acvp_crypto_ctx *crypto_ctx) +{ + return ufs_pixel_acvp_send_io(page, REQ_OP_WRITE | REQ_FUA, crypto_ctx); +} + +static int ufs_pixel_acvp_read(struct page *page, + struct acvp_crypto_ctx *crypto_ctx) +{ + return ufs_pixel_acvp_send_io(page, REQ_OP_READ, crypto_ctx); +} + +static int ufs_pixel_acvp_handle_aes_req(struct aes_req_int *aes_req) +{ + int ret; + + /* + * To align with current kernel capabilities we only support + * AES-256-XTS + */ + if (aes_req->aes_algorithm != AES_XTS) { + pr_err("Invalid AES algorithm\n"); + return -EINVAL; + } + + if (aes_req->key_len != UFS_PIXEL_ACVP_AES_256_XTS_KEY_LEN) { + pr_err("Invalid AES-256-XTS key len (%u)\n", aes_req->key_len); + return -EINVAL; + } + BUILD_BUG_ON(UFS_PIXEL_ACVP_AES_256_XTS_KEY_LEN > BLK_CRYPTO_MAX_KEY_SIZE); + + if (aes_req->iv_len != UFS_PIXEL_ACVP_AES_256_XTS_IV_LEN) { + pr_err("Invalid AES-256-XTS iv len (%u)\n", aes_req->iv_len); + return -EINVAL; + } + BUILD_BUG_ON(UFS_PIXEL_ACVP_AES_256_XTS_IV_LEN > sizeof(acvp_ctx.acvp_crypto_ctx->bc_dun)); + + if (aes_req->src_len > UFS_PIXEL_ACVP_AES_MAX_INPUT_LEN) { + pr_err("Invalid AES-256-XTS input len (%u)\n", + aes_req->src_len); + return -EINVAL; + } + + if (aes_req->src_len % UFS_PIXEL_ACVP_AES_MIN_ALIGN) { + pr_err("Invalid AES-256-XTS input len alignment (%u)\n", + aes_req->src_len); + return -EINVAL; + } + + if (aes_req->dst_len != aes_req->src_len) { + pr_err("Invalid AES-256-XTS output len (%u)\n", + aes_req->dst_len); + return -EINVAL; + } + + if (aes_req->aes_direction >= ACVP_AES_DIRECTION_MAX) { + pr_err("Invalid AES direction (%d)\n", aes_req->aes_direction); + return -EINVAL; + } + + memset(acvp_ctx.acvp_crypto_ctx->bc_dun, 0, + sizeof(acvp_ctx.acvp_crypto_ctx->bc_dun)); + + if (copy_from_user(acvp_ctx.io_addr, aes_req->src_ptr, + aes_req->src_len) || + copy_from_user(acvp_ctx.acvp_crypto_ctx->raw_key, + aes_req->key_ptr, aes_req->key_len) || + copy_from_user(acvp_ctx.acvp_crypto_ctx->bc_dun, aes_req->iv_ptr, + aes_req->iv_len)) + return -EFAULT; + + ret = blk_crypto_init_key(&acvp_ctx.acvp_crypto_ctx->bc_key, + acvp_ctx.acvp_crypto_ctx->raw_key, + aes_req->key_len, + false, + BLK_ENCRYPTION_MODE_AES_256_XTS, + UFS_PIXEL_ACVP_AES_256_XTS_IV_LEN, + UFS_PIXEL_ACVP_AES_MAX_INPUT_LEN); + if (ret) { + pr_err("Failed blk_crypto_init_key (%d)\n", ret); + return ret; + } + + if (aes_req->aes_direction == ACVP_ENCRYPT) { + if (ufs_pixel_acvp_write(acvp_ctx.io_page, + acvp_ctx.acvp_crypto_ctx)) + return -EIO; + if (ufs_pixel_acvp_read(acvp_ctx.io_page, NULL)) + return -EIO; + } else { + if (ufs_pixel_acvp_write(acvp_ctx.io_page, NULL)) + return -EIO; + if (ufs_pixel_acvp_read(acvp_ctx.io_page, + acvp_ctx.acvp_crypto_ctx)) + return -EIO; + } + + if (copy_to_user(aes_req->dst_ptr, acvp_ctx.io_addr, + aes_req->src_len)) + return -EFAULT; + + return 0; +} + +static int ufs_pixel_acvp_handle_hash_req(struct hash_req_int *hash_req) +{ + u8 digest[UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE]; + void *msg = NULL; + void *key = NULL; + int ret = 0; + + if (hash_req->src_len > UFS_PIXEL_ACVP_HASH_MAX_INPUT_LEN) { + pr_err("Message length must be at most %u\n", + UFS_PIXEL_ACVP_HASH_MAX_INPUT_LEN); + return -EINVAL; + } + + if (hash_req->src_len) { + msg = vmemdup_user(hash_req->src_ptr, hash_req->src_len); + if (IS_ERR(msg)) { + ret = PTR_ERR(msg); + msg = NULL; + goto out; + } + } + + if (hash_req->hash_type == HMAC_SHA_256) { + if (hash_req->key_len > UFS_PIXEL_ACVP_HASH_MAX_KEY_LEN) { + pr_err("Key length must be at most %u\n", + UFS_PIXEL_ACVP_HASH_MAX_KEY_LEN); + ret = -EINVAL; + goto out; + } + + key = vmemdup_user(hash_req->key_ptr, hash_req->key_len); + if (IS_ERR(key)) { + ret = PTR_ERR(key); + key = NULL; + goto out; + } + + ufs_pixel_fips_hmac_sha256(msg, hash_req->src_len, key, + hash_req->key_len, digest); + } else if (hash_req->hash_type == SHA_256) { + ufs_pixel_fips_sha256(msg, hash_req->src_len, digest); + } else if (hash_req->hash_type == SHA_256_MCT) { + u8 mc_digest[UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE * 3]; + u8 *md_a = mc_digest; + u8 *md_b = mc_digest + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE; + u8 *md_c = mc_digest + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE * 2; + u32 i; + + if (hash_req->src_len < UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE) { + pr_err("Message length must be at least %u\n", + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + ret = -EINVAL; + goto out; + } + + memcpy(md_a, msg, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + memcpy(md_b, msg, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + memcpy(md_c, msg, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + + for (i = 0; i < 1000; i++) { + ufs_pixel_fips_sha256(mc_digest, + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE * 3, + digest); + memcpy(md_a, md_b, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + memcpy(md_b, md_c, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + memcpy(md_c, digest, UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE); + + if (i && !(i % 64)) + cond_resched(); + } + } else { + pr_err("Unsupported hash type 0x%x\n", hash_req->hash_type); + ret = -EINVAL; + goto out; + } + + if (copy_to_user(hash_req->dst_ptr, digest, + UFS_PIXEL_FIPS_SHA256_DIGEST_SIZE)) + ret = -EFAULT; + +out: + kvfree(msg); + kvfree(key); + + return ret; +} + +static long ufs_pixel_acvp_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + struct aes_req_int aes_req; + struct hash_req_int hash_req; + int ret; + + switch (cmd) { + case UFS_PIXEL_ACVP_AES_REQ: + ret = ufs_pixel_acvp_get_aes_req(arg, &aes_req); + if (ret) + return ret; + ret = ufs_pixel_acvp_handle_aes_req(&aes_req); + break; + case UFS_PIXEL_ACVP_HASH_REQ: + ret = ufs_pixel_acvp_get_hash_req(arg, &hash_req); + if (ret) + return ret; + ret = ufs_pixel_acvp_handle_hash_req(&hash_req); + break; + default: + ret = -ENOTTY; + } + + return ret; +} + +#ifdef CONFIG_COMPAT +static long ufs_pixel_acvp_compat_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return ufs_pixel_acvp_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +#endif + +static const struct file_operations ufs_pixel_acvp_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = ufs_pixel_acvp_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = ufs_pixel_acvp_compat_ioctl, +#endif +}; + +static int ufs_pixel_acvp_init(void) +{ + int ret = 0; + + acvp_ctx.miscdev.minor = MISC_DYNAMIC_MINOR; + acvp_ctx.miscdev.name = UFS_PIXEL_ACVP_NAME; + acvp_ctx.miscdev.fops = &ufs_pixel_acvp_fops; + + ret = misc_register(&acvp_ctx.miscdev); + if (ret) { + pr_err("Failed to register misc device ret=%d\n", ret); + goto out; + } + + acvp_ctx.bdev = blkdev_get_by_path(UFS_PIXEL_ACVP_PARTITION, + FMODE_WRITE | FMODE_READ, NULL); + if (IS_ERR(acvp_ctx.bdev)) { + pr_err("Failed to open %s\n", UFS_PIXEL_ACVP_PARTITION); + ret = -ENODEV; + goto misc_deregister; + } + + acvp_ctx.io_page = alloc_page(GFP_KERNEL); + if (!acvp_ctx.io_page) { + ret = -ENOMEM; + goto blkdev_put; + } + + acvp_ctx.io_addr = page_address(acvp_ctx.io_page); + + acvp_ctx.crypto_page = alloc_page(GFP_KERNEL); + if (!acvp_ctx.crypto_page) { + ret = -ENOMEM; + goto free_page; + } + + acvp_ctx.acvp_crypto_ctx = page_address(acvp_ctx.crypto_page); + + return ret; + +free_page: + __free_page(acvp_ctx.io_page); +blkdev_put: + blkdev_put(acvp_ctx.bdev, FMODE_WRITE | FMODE_READ); +misc_deregister: + misc_deregister(&acvp_ctx.miscdev); +out: + return ret; +} + +static void ufs_pixel_acvp_exit(void) +{ + __free_page(acvp_ctx.crypto_page); + __free_page(acvp_ctx.io_page); + blkdev_put(acvp_ctx.bdev, FMODE_WRITE | FMODE_READ); + misc_deregister(&acvp_ctx.miscdev); +} + +module_init(ufs_pixel_acvp_init); +module_exit(ufs_pixel_acvp_exit); + +MODULE_DESCRIPTION("UFS FIPS140 ACVP Certification Module"); +MODULE_AUTHOR("Konstantin Vyshetsky"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); diff --git a/drivers/scsi/ufs/ufs-pixel-acvp.h b/drivers/scsi/ufs/ufs-pixel-acvp.h new file mode 100644 index 000000000000..5f5c6ac36a58 --- /dev/null +++ b/drivers/scsi/ufs/ufs-pixel-acvp.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pixel-Specific UFS feature support + * + * Copyright 2021 Google LLC + * + * Authors: Konstantin Vyshetsky + */ + +#include +#include + +enum ufs_pixel_acvp_aes_direction { + ACVP_ENCRYPT, + ACVP_DECRYPT, + ACVP_AES_DIRECTION_MAX +}; + +enum ufs_pixel_acvp_aes_algorithm { + AES_XTS, + AES_CBC, + AES_CBC_MCT +}; + +struct ufs_pixel_acvp_aes_req { + __u64 src_ptr; + __u64 dst_ptr; + __u64 key_ptr; + __u64 iv_ptr; + __u32 src_len; + __u32 dst_len; + __u32 key_len; + __u32 iv_len; + __u32 aes_direction; + __u32 aes_algorithm; +}; + +enum ufs_pixel_acvp_hash_type { + HMAC_SHA_256, + SHA_256, + SHA_256_MCT +}; + +struct ufs_pixel_acvp_hash_req { + __u64 src_ptr; + __u64 dst_ptr; + __u64 key_ptr; + __u32 src_len; + __u32 key_len; + __u32 hash_type; +}; + +#define UFS_PIXEL_ACVP_AES_REQ _IOWR('a', 1, struct ufs_pixel_acvp_aes_req) +#define UFS_PIXEL_ACVP_HASH_REQ _IOWR('h', 2, struct ufs_pixel_acvp_hash_req) diff --git a/drivers/scsi/ufs/ufs-pixel-crypto.c b/drivers/scsi/ufs/ufs-pixel-crypto.c index 1f0478c953c6..de9a456266ff 100644 --- a/drivers/scsi/ufs/ufs-pixel-crypto.c +++ b/drivers/scsi/ufs/ufs-pixel-crypto.c @@ -37,6 +37,7 @@ #include "ufshcd.h" #include "ufshcd-crypto.h" #include "ufs-exynos.h" +#include "ufs-pixel-fips.h" #undef pr_info #undef pr_debug @@ -60,6 +61,8 @@ static void pixel_ufs_crypto_fill_prdt(void *unused, struct ufs_hba *hba, struct ufshcd_lrb *lrbp, unsigned int segments, int *err); +static int pixel_ufs_register_fips_self_test(void); + #define CRYPTO_DATA_UNIT_SIZE 4096 /* @@ -381,6 +384,10 @@ static int pixel_ufs_crypto_init_hw_keys_mode(struct ufs_hba *hba) if (err) return err; + err = pixel_ufs_register_fips_self_test(); + if (err) + return err; + /* Advertise crypto support to ufshcd-core. */ hba->caps |= UFSHCD_CAP_CRYPTO; @@ -463,6 +470,8 @@ static void pixel_ufs_crypto_restore_keys(void *unused, struct ufs_hba *hba, if (*err) dev_err(ufs->dev, "kdn: failed to restore keys; err=%d\n", *err); + else + dev_info(ufs->dev, "kdn: restored keys\n"); } void pixel_ufs_crypto_resume(struct ufs_hba *hba) @@ -536,3 +545,37 @@ static void pixel_ufs_crypto_fill_prdt(void *unused, struct ufs_hba *hba, */ lrbp->crypto_key_slot = -1; } + +#if IS_ENABLED(CONFIG_SCSI_UFS_PIXEL_FIPS140) && IS_ENABLED(CONFIG_SOC_GS201) +static void pixel_ufs_ise_self_test(void *data, struct ufs_hba *hba) +{ + /* + * This SMC call sets USEOTPKEY bit to 1 in FMPSECURITY0 register. This + * causes incoming encryption keys to be XOR'ed with EFUSE key per + * section 1.4.3.3 of UFS Link Manual, a functionality needed by the UFS + * CMVP self test. + */ + if (exynos_smc(SMC_CMD_FMP_USE_OTP_KEY, 0, SMU_EMBEDDED, 1)) + panic("SMC_CMD_FMP_USE_OTP_KEY(0) failed"); + + if (ufs_pixel_fips_verify(hba)) + panic("FMP self test failed"); + + /* + * This SMC call sets USEOTPKEY bit back to 0 in FMPSECURITY0 register. + */ + if (exynos_smc(SMC_CMD_FMP_USE_OTP_KEY, 0, SMU_EMBEDDED, 0)) + panic("SMC_CMD_FMP_USE_OTP_KEY(1) failed"); +} + +static int pixel_ufs_register_fips_self_test(void) +{ + return register_trace_android_rvh_ufs_complete_init( + pixel_ufs_ise_self_test, NULL); +} +#else +static int pixel_ufs_register_fips_self_test(void) +{ + return 0; +} +#endif diff --git a/drivers/scsi/ufs/ufs-pixel.c b/drivers/scsi/ufs/ufs-pixel.c index 33571e675d38..2900e2ae56af 100644 --- a/drivers/scsi/ufs/ufs-pixel.c +++ b/drivers/scsi/ufs/ufs-pixel.c @@ -571,6 +571,30 @@ static void __store_cmd_log(struct ufs_hba *hba, u8 event, u8 lun, entry->queue_eh_work = queue_eh_work; } +static void pixel_ufs_trace_fdeviceinit(struct ufs_hba *hba, + struct ufshcd_lrb *lrbp, u8 opcode) +{ + struct exynos_ufs *ufs = to_exynos_ufs(hba); + struct latency_metrics *metric = NULL; + + if (opcode == UPIU_QUERY_OPCODE_SET_FLAG) + metric = &ufs->power_stats.fdevinit_set; + else if (opcode == UPIU_QUERY_OPCODE_READ_FLAG) + metric = &ufs->power_stats.fdevinit_read; + + if (metric) { + s64 delta = ktime_to_us(ktime_sub(lrbp->compl_time_stamp, + lrbp->issue_time_stamp)); + + WARN_ON(delta < 0); + + metric->count++; + metric->time_spent_us += delta; + if (delta > metric->max_latency_us) + metric->max_latency_us = delta; + } +} + static void pixel_ufs_trace_upiu_cmd(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, bool is_start) { @@ -598,6 +622,9 @@ static void pixel_ufs_trace_upiu_cmd(struct ufs_hba *hba, event = (is_start) ? EVENT_QUERY_SEND : EVENT_QUERY_COMPL; opcode = hba->dev_cmd.query.request.upiu_req.opcode; idn = hba->dev_cmd.query.request.upiu_req.idn; + if (idn == QUERY_FLAG_IDN_FDEVICEINIT && + event == EVENT_QUERY_COMPL) + pixel_ufs_trace_fdeviceinit(hba, lrbp, opcode); } } @@ -749,11 +776,13 @@ static void pixel_ufs_compl_command(void *data, struct ufs_hba *hba, static void pixel_ufs_prepare_command(void *data, struct ufs_hba *hba, struct request *rq, struct ufshcd_lrb *lrbp, int *err) { + struct exynos_ufs *ufs = to_exynos_ufs(hba); + u8 opcode; *err = 0; - if (!(rq->cmd_flags & (REQ_META | REQ_IDLE))) + if (!(rq->cmd_flags & (REQ_META | REQ_IDLE)) && !ufs->always_use_wb) return; if (hba->dev_info.wspecversion <= 0x300) @@ -1099,6 +1128,41 @@ static ssize_t uic_link_state_show(struct device *dev, hba->uic_link_state)); } +static ssize_t always_use_wb_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct exynos_ufs *ufs = to_exynos_ufs(hba); + u32 value = ufs->always_use_wb ? 1 : 0; + + return snprintf(buf, PAGE_SIZE, "%x\n", value); +} +static ssize_t always_use_wb_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ufs_hba *hba = dev_get_drvdata(dev); + struct exynos_ufs *ufs = to_exynos_ufs(hba); + bool always_use_wb; + + if (kstrtobool(buf, &always_use_wb)) + return -EINVAL; + + if (always_use_wb != ufs->always_use_wb) { + enum query_opcode opcode = always_use_wb ? + UPIU_QUERY_OPCODE_SET_FLAG : + UPIU_QUERY_OPCODE_CLEAR_FLAG; + u8 index = ufshcd_wb_get_query_index(hba); + + ufshcd_query_flag_retry(hba, opcode, + QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8, + index, NULL); + ufs->always_use_wb = always_use_wb; + } + + return count; +} + static DEVICE_ATTR_RO(vendor); static DEVICE_ATTR_RO(model); static DEVICE_ATTR_RO(rev); @@ -1108,6 +1172,7 @@ static DEVICE_ATTR_RW(manual_gc_hold); static DEVICE_ATTR_RO(host_capabilities); static DEVICE_ATTR_RO(curr_dev_pwr_mode); static DEVICE_ATTR_RO(uic_link_state); +static DEVICE_ATTR_RW(always_use_wb); SLOWIO_ATTR_RW(read, PIXEL_SLOWIO_READ); SLOWIO_ATTR_RW(write, PIXEL_SLOWIO_WRITE); SLOWIO_ATTR_RW(unmap, PIXEL_SLOWIO_UNMAP); @@ -1123,6 +1188,7 @@ static struct attribute *pixel_sysfs_ufshcd_attrs[] = { &dev_attr_host_capabilities.attr, &dev_attr_curr_dev_pwr_mode.attr, &dev_attr_uic_link_state.attr, + &dev_attr_always_use_wb.attr, &ufs_slowio_read_us.attr.attr, &ufs_slowio_read_cnt.attr.attr, &ufs_slowio_write_us.attr.attr, @@ -1667,6 +1733,41 @@ static const struct attribute_group pixel_sysfs_power_info_group = { .attrs = pixel_sysfs_power_info, }; +#define PIXEL_POWER_STATS_ATTR(_name, _metric, _var) \ +static ssize_t _name##_show(struct device *dev, \ + struct device_attribute *attr, char *buf) \ +{ \ + struct ufs_hba *hba = dev_get_drvdata(dev); \ + struct exynos_ufs *ufs = to_exynos_ufs(hba); \ + return sprintf(buf, "%llu\n", ufs->power_stats._metric._var); \ +} \ +static DEVICE_ATTR_RO(_name) + +PIXEL_POWER_STATS_ATTR(fdevinit_set_count, fdevinit_set, count); +PIXEL_POWER_STATS_ATTR(fdevinit_set_time_spent_us, fdevinit_set, time_spent_us); +PIXEL_POWER_STATS_ATTR(fdevinit_set_max_latency_us, fdevinit_set, + max_latency_us); +PIXEL_POWER_STATS_ATTR(fdevinit_read_count, fdevinit_read, count); +PIXEL_POWER_STATS_ATTR(fdevinit_read_time_spent_us, fdevinit_read, + time_spent_us); +PIXEL_POWER_STATS_ATTR(fdevinit_read_max_latency_us, fdevinit_read, + max_latency_us); + +static struct attribute *pixel_sysfs_power_stats[] = { + &dev_attr_fdevinit_set_count.attr, + &dev_attr_fdevinit_set_time_spent_us.attr, + &dev_attr_fdevinit_set_max_latency_us.attr, + &dev_attr_fdevinit_read_count.attr, + &dev_attr_fdevinit_read_time_spent_us.attr, + &dev_attr_fdevinit_read_max_latency_us.attr, + NULL, +}; + +static const struct attribute_group pixel_sysfs_power_stats_group = { + .name = "power_stats", + .attrs = pixel_sysfs_power_stats, +}; + static const struct attribute_group *pixel_ufs_sysfs_groups[] = { &pixel_sysfs_group, &pixel_sysfs_req_stats_group, @@ -1675,6 +1776,7 @@ static const struct attribute_group *pixel_ufs_sysfs_groups[] = { &pixel_sysfs_ufs_stats_group, &pixel_sysfs_hc_register_ifc_group, &pixel_sysfs_power_info_group, + &pixel_sysfs_power_stats_group, NULL, }; @@ -1746,7 +1848,9 @@ int pixel_init(struct ufs_hba *hba) int ret; memset(&ufs->ufs_stats, 0, sizeof(struct pixel_ufs_stats)); + memset(&ufs->power_stats, 0, sizeof(struct pixel_power_stats)); ufs->ufs_stats.hibern8_flag = false; + ufs->always_use_wb = false; ret = register_trace_android_vh_ufs_prepare_command( pixel_ufs_prepare_command, NULL); diff --git a/drivers/scsi/ufs/ufs-vs-mmio.h b/drivers/scsi/ufs/ufs-vs-mmio.h index bce9eedc87bd..0fb64a7fbdec 100644 --- a/drivers/scsi/ufs/ufs-vs-mmio.h +++ b/drivers/scsi/ufs/ufs-vs-mmio.h @@ -8,6 +8,8 @@ #ifdef CONFIG_SOC_GS101 #include "gs101/ufs-vs-mmio.h" +#elif CONFIG_SOC_GS201 +#include "gs201/ufs-vs-mmio.h" #endif #endif /*_UFS_VS_MMIO_H */ diff --git a/drivers/soc/google/Kconfig b/drivers/soc/google/Kconfig index f644f7db02a3..50edb4c5e061 100644 --- a/drivers/soc/google/Kconfig +++ b/drivers/soc/google/Kconfig @@ -12,11 +12,20 @@ config SOC_GS101 bool "Google GS101" depends on SOC_GOOGLE +config SOC_GS201 + bool "Google GS201" + depends on SOC_GOOGLE + config BOARD_SLIDER bool "Google Slider Board" depends on SOC_GS101 select OF_GENERATE_SYMBOLS +config BOARD_CLOUDRIPPER + bool "Google Cloudripper Board" + depends on SOC_GS201 + select OF_GENERATE_SYMBOLS + config GS_CHIPID tristate "GS Chipid controller driver" depends on ARM64 @@ -115,9 +124,9 @@ config EXYNOS_PM config EXYNOS_CPUPM tristate "CPU Power Management driver" - depends on SOC_GS101 && PMUCAL + depends on (SOC_GS101 || SOC_GS201) && PMUCAL help - Support CPU Power Control for GS101 SoC. + Support CPU Power Control for GS SoC. source "drivers/soc/google/acpm/Kconfig" @@ -177,12 +186,23 @@ config VH_KERNEL help Modules for vendor kernel hooks. -config PIXEL_EM - tristate "Enable Pixel Energy Model driver" - depends on VH_KERNEL - default n +config BOARD_EMULATOR + bool "EMULATOR platform" + select OF_GENERATE_SYMBOLS + +config BOARD_GS201_EMULATOR + bool "EMULATOR Platform for GS201" + depends on SOC_GS201 && BOARD_EMULATOR + select OF_GENERATE_SYMBOLS + help + GS201 Zebu Emulator System + +config BOARD_GS201_HYBRID + bool "HYBRID EMULATOR Platform for GS201" + depends on SOC_GS201 && BOARD_EMULATOR + select OF_GENERATE_SYMBOLS help - Support Pixel Energy Model. + GS201 Hybrid Zebu Emulator System, it is support for Android Platform config PIXEL_STAT tristate "Enable Pixel statistics" @@ -240,4 +260,24 @@ config SYSRQ_HOOK help Modules for sysrq hooks. +config PKVM_S2MPU + tristate "S2MPU driver compatible with pKVM" + default n + help + This module is a driver for the stage-2 IOMMU controlled by hypervisor. + +config WLAN_TRACKER + bool "WiFi performance tracker driver" + depends on SOC_GS201 + default n + help + Module for wlan performance tracker. + +config KERNEL_TOP + tristate "Display processes statistic" + default n + help + This module exposes kernel function for modules to debugging + processes statistic. + endmenu diff --git a/drivers/soc/google/Makefile b/drivers/soc/google/Makefile index daf7362f2e51..f2cfc919655d 100644 --- a/drivers/soc/google/Makefile +++ b/drivers/soc/google/Makefile @@ -52,12 +52,14 @@ obj-$(CONFIG_SYSRQ_HOOK) += sysrq-hook.o # vh/kernel/sched obj-$(CONFIG_VH_KERNEL) += vh/kernel/ -obj-$(CONFIG_PIXEL_EM) += pixel_em/ - obj-$(CONFIG_PIXEL_STAT) += pixel_stat/ obj-$(CONFIG_DBGCORE_DUMP) += dbgcore-dump.o obj-$(CONFIG_EXYNOS_SECURE_LOG) += exynos-seclog.o +obj-$(CONFIG_PKVM_S2MPU) += pkvm-s2mpu.o + obj-$(CONFIG_BOOT_CONTROL) += boot_control/ + +obj-$(CONFIG_KERNEL_TOP) += kernel-top.o diff --git a/drivers/soc/google/acpm/acpm.c b/drivers/soc/google/acpm/acpm.c index 5f78457bb45a..10e02f56b482 100644 --- a/drivers/soc/google/acpm/acpm.c +++ b/drivers/soc/google/acpm/acpm.c @@ -294,6 +294,23 @@ void exynos_acpm_reboot(void) } EXPORT_SYMBOL_GPL(exynos_acpm_reboot); +void acpm_prepare_reboot(void) +{ + acpm_ipc_set_waiting_mode(BUSY_WAIT); + + acpm_stop_log_and_dumpram(); +} +EXPORT_SYMBOL_GPL(acpm_prepare_reboot); + +static void acpm_shutdown(struct platform_device *pdev) +{ + pr_info("%s...\n", __func__); + + acpm_framework_debug_cmd_setting(exynos_acpm, ACPM_FRAMEWORK_COMMAND_DEBUG_NOTIFY_SHUTDOWN); + + acpm_prepare_reboot(); +} + static int acpm_probe(struct platform_device *pdev) { struct acpm_info *acpm; @@ -353,6 +370,7 @@ MODULE_DEVICE_TABLE(of, acpm_match); static struct platform_driver samsung_acpm_driver = { .probe = acpm_probe, .remove = acpm_remove, + .shutdown = acpm_shutdown, .driver = { .name = "gs-acpm", .owner = THIS_MODULE, diff --git a/drivers/soc/google/acpm/acpm_ipc.c b/drivers/soc/google/acpm/acpm_ipc.c index 8f39490b487a..f554467a24fe 100644 --- a/drivers/soc/google/acpm/acpm_ipc.c +++ b/drivers/soc/google/acpm/acpm_ipc.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -42,6 +43,7 @@ static struct acpm_ipc_info *acpm_ipc; static struct workqueue_struct *update_log_wq; static struct acpm_debug_info *acpm_debug; static bool is_acpm_stop_log; +static struct cpu_irq_info *irq_info; static struct acpm_framework *acpm_initdata; static void __iomem *acpm_srambase; @@ -574,6 +576,65 @@ int acpm_ipc_send_data_sync(unsigned int channel_id, struct ipc_config *cfg) } EXPORT_SYMBOL_GPL(acpm_ipc_send_data_sync); +#ifndef arch_irq_stat +#define arch_irq_stat() 0 +#endif + +extern int nr_irqs; + +static void cpu_irq_info_dump(u32 retry) +{ + int i, cpu; + u64 sum = 0; + + for_each_possible_cpu(cpu) + sum += kstat_cpu_irqs_sum(cpu); + + sum += arch_irq_stat(); + + if (retry == 5) + pr_info("\n"); + + for_each_irq_nr(i) { + struct irq_data *data; + struct irq_desc *desc; + unsigned int irq_stat = 0, delta; + const char *name; + + data = irq_get_irq_data(i); + if (!data) + continue; + + desc = irq_data_to_desc(data); + if (!desc) + continue; + + for_each_possible_cpu(cpu) + irq_stat += *per_cpu_ptr(desc->kstat_irqs, cpu); + + if (!irq_stat) + continue; + + if (desc->action && desc->action->name) + name = desc->action->name; + else + name = "???"; + + if (retry == 1) { + irq_info[i].irq_num = i; + irq_info[i].hwirq_num = desc->irq_data.hwirq; + irq_info[i].irq_stat = irq_stat; + irq_info[i].name = name; + } else if (retry == 5) { + delta = irq_stat - irq_info[i].irq_stat; + if (delta > 0) { + pr_info("irq-%-4d(hwirq-%-3d) delta of irqs: %8u %s\n", + i, (int)desc->irq_data.hwirq, delta, name); + } + } + } +} + int __acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg, bool w_mode) { volatile unsigned int tx_front, tx_rear, rx_front; @@ -683,8 +744,6 @@ int __acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg, bool w timeout_flag = true; break; } else if (retry_cnt > 0) { - unsigned int saved_debug_log_level = - acpm_debug->debug_log_level; frc = get_frc_time(); pr_err("acpm_ipc retry %d, now = %llu, frc = %llu, timeout = %llu", retry_cnt, now, frc, timeout); @@ -704,14 +763,17 @@ int __acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg, bool w __raw_readl(acpm_ipc->intr + INTMR1), __raw_readl(acpm_ipc->intr + INTMSR1)); + cpu_irq_info_dump(retry_cnt); ++retry_cnt; - acpm_debug->debug_log_level = 2; - acpm_log_print(); - acpm_debug->debug_log_level = saved_debug_log_level; goto retry; } else { + unsigned int saved_debug_log_level = + acpm_debug->debug_log_level; ++retry_cnt; + acpm_debug->debug_log_level = 2; + acpm_log_print(); + acpm_debug->debug_log_level = saved_debug_log_level; continue; } cnt_10us = 0; @@ -731,7 +793,6 @@ int __acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg, bool w pr_err("%s Timeout error! now = %llu timeout = %llu ch:%u s:%u bitmap:%lx\n", __func__, now, timeout, channel->id, seq_num, channel->bitmap_seqnum[0]); - acpm_ramdump(); dump_stack(); dbg_snapshot_do_dpm_policy(acpm_ipc->panic_action, "acpm_ipc timeout"); @@ -1019,6 +1080,9 @@ int acpm_ipc_probe(struct platform_device *pdev) } ret = plugins_init(node); + + irq_info = kcalloc(nr_irqs, sizeof(struct cpu_irq_info), GFP_KERNEL); + dev_info(&pdev->dev, "acpm_ipc probe done.\n"); return ret; } diff --git a/drivers/soc/google/acpm/acpm_ipc.h b/drivers/soc/google/acpm/acpm_ipc.h index 3ae9f49f7c67..669f6737db21 100644 --- a/drivers/soc/google/acpm/acpm_ipc.h +++ b/drivers/soc/google/acpm/acpm_ipc.h @@ -86,6 +86,13 @@ struct acpm_debug_info { spinlock_t lock; /* generic spin-lock for debug */ }; +struct cpu_irq_info { + const char *name; + int irq_num; + unsigned long hwirq_num; + unsigned int irq_stat; +}; + #define LOG_ID_SHIFT (28) #define LOG_IS_RAW_SHIFT (27) #define LOG_IS_ERR_SHIFT (26) diff --git a/drivers/soc/google/acpm/acpm_mbox_test.c b/drivers/soc/google/acpm/acpm_mbox_test.c index 5c17194cc605..e32b4070ed74 100644 --- a/drivers/soc/google/acpm/acpm_mbox_test.c +++ b/drivers/soc/google/acpm/acpm_mbox_test.c @@ -28,11 +28,19 @@ #include #include #include "../../../soc/google/cal-if/acpm_dvfs.h" +#if defined(CONFIG_SOC_GS101) #include #include #include #include #include +#elif defined(CONFIG_SOC_GS201) +#include +#include +#include +#include +#include +#endif #include #include #include @@ -282,13 +290,96 @@ static void acpm_dvfs_mbox_stress_trigger(struct work_struct *work) msecs_to_jiffies(STRESS_TRIGGER_DELAY)); } +static int acpm_main_pm_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) +{ + struct device_node *dt_node = mbox->device->of_node; + u8 channel = mbox->mfd->main_channel; + int ret; + + mutex_lock(&mbox->mfd->main_pm_lock); + ret = exynos_acpm_read_reg(dt_node, channel, i2c->addr, reg, dest); + mutex_unlock(&mbox->mfd->main_pm_lock); + if (ret) { + dev_err(mbox->device, "%s acpm ipc fail, ret: %d\n", + __func__, ret); + return ret; + } + return 0; +} + +static int acpm_main_pm_write_reg(struct i2c_client *i2c, u8 reg, u8 value) +{ + struct device_node *dt_node = mbox->device->of_node; + u8 channel = mbox->mfd->main_channel; + int ret; + + mutex_lock(&mbox->mfd->main_pm_lock); + ret = exynos_acpm_write_reg(dt_node, channel, i2c->addr, reg, value); + mutex_unlock(&mbox->mfd->main_pm_lock); + if (ret) { + dev_err(mbox->device, "%s acpm ipc fail, ret: %d\n", + __func__, ret); + return ret; + } + return ret; +} + +static int acpm_main_pm_bulk_read(struct i2c_client *i2c, u8 reg, int count, + u8 *buf) +{ + struct device_node *dt_node = mbox->device->of_node; + u8 channel = mbox->mfd->main_channel; + int ret; + + mutex_lock(&mbox->mfd->main_pm_lock); + ret = exynos_acpm_bulk_read(dt_node, channel, i2c->addr, + reg, count, buf); + mutex_unlock(&mbox->mfd->main_pm_lock); + if (ret) { + dev_err(mbox->device, "%s acpm ipc fail, ret: %d\n", + __func__, ret); + return ret; + } + return 0; +} + +static int acpm_sub_pm_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest) +{ + struct device_node *dt_node = mbox->device->of_node; + u8 channel = mbox->mfd->sub_channel; + int ret; + + mutex_lock(&mbox->mfd->sub_pm_lock); + ret = exynos_acpm_read_reg(dt_node, channel, i2c->addr, reg, dest); + mutex_unlock(&mbox->mfd->sub_pm_lock); + if (ret) + dev_err(mbox->device, "%s acpm ipc fail, ret: %d\n", + __func__, ret); + return ret; +} + +static int acpm_sub_pm_write_reg(struct i2c_client *i2c, u8 reg, u8 value) +{ + struct device_node *dt_node = mbox->device->of_node; + u8 channel = mbox->mfd->sub_channel; + int ret; + + mutex_lock(&mbox->mfd->sub_pm_lock); + ret = exynos_acpm_write_reg(dt_node, channel, i2c->addr, reg, value); + mutex_unlock(&mbox->mfd->sub_pm_lock); + if (ret) + dev_err(mbox->device, "%s acpm ipc fail, ret: %d\n", + __func__, ret); + return ret; +} + static int acpm_mfd_rtc_update(void) { u8 data, reg; int ret; - ret = s2mpg10_read_reg(mbox->mfd->rtc, S2MPG10_RTC_UPDATE, &data); - if (ret < 0) { + ret = acpm_main_pm_read_reg(mbox->mfd->rtc, RTC_REG_UPDATE, &data); + if (ret) { dev_err(mbox->device, "%s: fail to read update ret(%d,%u)\n", __func__, ret, data); return ret; @@ -299,7 +390,7 @@ static int acpm_mfd_rtc_update(void) reg = BIT(RTC_RUDR_SHIFT); data &= ~reg; - ret = s2mpg10_write_reg(mbox->mfd->rtc, S2MPG10_RTC_UPDATE, data); + ret = acpm_main_pm_write_reg(mbox->mfd->rtc, RTC_REG_UPDATE, data); if (ret) { dev_err(mbox->device, "%s: fail to write update ret(%d,%u)\n", __func__, ret, data); @@ -309,7 +400,7 @@ static int acpm_mfd_rtc_update(void) usleep_range(50, 51); data |= reg; - ret = s2mpg10_write_reg(mbox->mfd->rtc, S2MPG10_RTC_UPDATE, data); + ret = acpm_main_pm_write_reg(mbox->mfd->rtc, RTC_REG_UPDATE, data); if (ret) dev_err(mbox->device, "%s: fail to write update ret(%d,%u)\n", __func__, ret, data); @@ -356,7 +447,7 @@ static int acpm_mfd_rtc_read_time(void) u8 now[NR_RTC_CNT_REGS]; int ret; - mutex_lock(&mbox->mfd->lock); + mutex_lock(&mbox->mfd->rtc_lock); ret = acpm_mfd_rtc_update(); if (ret < 0) { dev_err(mbox->device, "%s: rtc update failed, ret: %d\n", @@ -365,9 +456,9 @@ static int acpm_mfd_rtc_read_time(void) goto out; } - ret = s2mpg10_bulk_read(mbox->mfd->rtc, S2MPG10_RTC_SEC, NR_RTC_CNT_REGS, - now); - if (ret < 0) { + ret = acpm_main_pm_bulk_read(mbox->mfd->rtc, RTC_REG_SEC, + NR_RTC_CNT_REGS, now); + if (ret) { dev_err(mbox->device, "%s: fail to read time reg(%d)\n", __func__, ret); cancel_delayed_work_sync(&mbox->mfd->mbox_stress_trigger_wk); @@ -389,39 +480,42 @@ static int acpm_mfd_rtc_read_time(void) now[RTC_HOUR] & BIT(HOUR_PM_SHIFT) ? "PM" : "AM"); out: - mutex_unlock(&mbox->mfd->lock); + mutex_unlock(&mbox->mfd->rtc_lock); return ret; } -static void acpm_mbox_mfd_s2mpg10_random_read(struct work_struct *work) +static void acpm_mbox_mfd_main_pm_random_read(struct work_struct *work) { u32 addr; u8 val = 0; addr = get_random_for_type(GRANVILLE_M_REG); - if (s2mpg10_read_reg(mbox->mfd->s2mpg10_pmic, addr, &val)) { - dev_err(mbox->device, "%s: Failed to read S2MPG10\n", __func__); + if (acpm_main_pm_read_reg(mbox->mfd->main_pmic, addr, &val)) { + dev_err(mbox->device, "%s: Failed to read S2MPG-Main\n", + __func__); cancel_delayed_work_sync(&mbox->mfd->mbox_stress_trigger_wk); } else - dev_info(mbox->device, "%s: [S2MPG10]addr: 0x%X, val: 0x%X\n", - __func__, addr, val); + dev_info(mbox->device, + "%s: [S2MPG-Main]addr: 0x%X, val: 0x%X\n", __func__, + addr, val); acpm_mfd_rtc_read_time(); } -static void acpm_mbox_mfd_s2mpg11_random_read(struct work_struct *work) +static void acpm_mbox_mfd_sub_pm_random_read(struct work_struct *work) { u32 addr; u8 val = 0; addr = get_random_for_type(GRANVILLE_S_REG); - if (s2mpg11_read_reg(mbox->mfd->s2mpg11_pmic, addr, &val)) { - dev_err(mbox->device, "%s: Failed to read S2MPG11\n", __func__); + if (acpm_sub_pm_read_reg(mbox->mfd->sub_pmic, addr, &val)) { + dev_err(mbox->device, "%s: Failed to read S2MPG-Sub\n", + __func__); cancel_delayed_work_sync(&mbox->mfd->mbox_stress_trigger_wk); } else - dev_info(mbox->device, "%s: [S2MPG11]addr: 0x%X, val: 0x%X\n", + dev_info(mbox->device, "%s: [S2MPG-Sub]addr: 0x%X, val: 0x%X\n", __func__, addr, val); } @@ -431,10 +525,10 @@ static int acpm_pmic_ctrlist_stress(void) u16 addr; u8 value; - for (i = 0; i < sizeof(def_lck_regs_m) / sizeof(u16); i++) { - addr = def_lck_regs_m[i]; + for (i = 0; i < mbox->mfd->num_of_main_regulator_regs; i++) { + addr = mbox->mfd->regulator_lst_main[i]; - ret = s2mpg10_read_reg(mbox->mfd->s2mpg10_pmic, addr, &value); + ret = acpm_main_pm_read_reg(mbox->mfd->main_pmic, addr, &value); if (ret) { dev_err(mbox->device, "%s: fail to read ret: %d\n", __func__, ret); @@ -442,7 +536,7 @@ static int acpm_pmic_ctrlist_stress(void) } /* Verify PMIC ctrlist by writing the same setting */ - ret = s2mpg10_write_reg(mbox->mfd->s2mpg10_pmic, addr, value); + ret = acpm_main_pm_write_reg(mbox->mfd->main_pmic, addr, value); if (ret == 0) { dev_err(mbox->device, "%s: ctrlist protection failed, ret: %d\n", @@ -455,10 +549,10 @@ static int acpm_pmic_ctrlist_stress(void) __func__, addr, value, err_result); } - for (i = 0; i < sizeof(def_lck_regs_s) / sizeof(u16); i++) { - addr = def_lck_regs_s[i]; + for (i = 0; i < mbox->mfd->num_of_sub_regulator_regs; i++) { + addr = mbox->mfd->regulator_lst_sub[i]; - ret = s2mpg11_read_reg(mbox->mfd->s2mpg11_pmic, addr, &value); + ret = acpm_sub_pm_read_reg(mbox->mfd->sub_pmic, addr, &value); if (ret) { dev_err(mbox->device, "%s: fail to read ret: %d\n", __func__, ret); @@ -466,7 +560,7 @@ static int acpm_pmic_ctrlist_stress(void) } /* Verify PMIC ctrlist by writing the same setting */ - ret = s2mpg11_write_reg(mbox->mfd->s2mpg11_pmic, addr, value); + ret = acpm_sub_pm_write_reg(mbox->mfd->sub_pmic, addr, value); if (ret == 0) { dev_err(mbox->device, "%s: ctrlist protection failed, ret: %d\n", @@ -491,22 +585,20 @@ static void acpm_mfd_mbox_stress_trigger(struct work_struct *work) { int i; - if ((!mbox->mfd->s2mpg10_pmic) - || (!mbox->mfd->s2mpg11_pmic)) { + if ((!mbox->mfd->main_pmic) + || (!mbox->mfd->sub_pmic)) { cancel_delayed_work_sync(&mbox->mfd->mbox_stress_trigger_wk); } else { for (i = 0; i < NUM_OF_WQ; i++) { queue_delayed_work_on(get_random_for_type(CPU_ID), - mbox->mfd->s2mpg10_mfd_read_wq[i], - &mbox-> - mfd->s2mpg10_mfd_read_wk[i], + mbox->mfd->main_pm_mfd_read_wq[i], + &mbox->mfd->main_pm_mfd_read_wk[i], msecs_to_jiffies (get_random_for_type(DELAY_MS))); queue_delayed_work_on(get_random_for_type(CPU_ID), - mbox->mfd->s2mpg11_mfd_read_wq[i], - &mbox-> - mfd->s2mpg11_mfd_read_wk[i], + mbox->mfd->sub_pm_mfd_read_wq[i], + &mbox->mfd->sub_pm_mfd_read_wk[i], msecs_to_jiffies (get_random_for_type(DELAY_MS))); } @@ -686,12 +778,11 @@ static int acpm_mfd_set_pmic(void) { struct device_node *p_np; struct device_node *np = mbox->device->of_node; - struct s2mpg10_dev *s2mpg10 = NULL; - struct s2mpg11_dev *s2mpg11 = NULL; struct i2c_client *i2c_main; struct i2c_client *i2c_sub; u8 update_val; - int ret; + int ret, len, i; + u32 *regulator_list; if (mbox->mfd->init_done) { return 0; @@ -706,26 +797,29 @@ static int acpm_mfd_set_pmic(void) __func__); return -ENODEV; } - s2mpg10 = i2c_get_clientdata(i2c_main); + mbox->mfd->s2mpg_main = i2c_get_clientdata(i2c_main); } else dev_err(mbox->device, "%s: Cannot find main-pmic\n", __func__); of_node_put(p_np); - if (!s2mpg10) { - dev_err(mbox->device, "%s: S2MPG10 device not found\n", + if (!mbox->mfd->s2mpg_main) { + dev_err(mbox->device, "%s: S2MPG-Main device not found\n", __func__); return -ENODEV; } - i2c_set_clientdata(s2mpg10->pmic, s2mpg10); - mbox->mfd->s2mpg10_pmic = s2mpg10->pmic; - i2c_set_clientdata(s2mpg10->rtc, s2mpg10); - mbox->mfd->rtc = s2mpg10->rtc; + i2c_set_clientdata(mbox->mfd->s2mpg_main->pmic, mbox->mfd->s2mpg_main); + mbox->mfd->main_pmic = mbox->mfd->s2mpg_main->pmic; + mbox->mfd->main_channel = 0; + + i2c_set_clientdata(mbox->mfd->s2mpg_main->rtc, mbox->mfd->s2mpg_main); + mbox->mfd->rtc = mbox->mfd->s2mpg_main->rtc; /* Configure for RTC bulk_read */ - ret = s2mpg10_read_reg(mbox->mfd->rtc, S2MPG10_RTC_UPDATE, &update_val); - if (ret < 0) { + ret = + acpm_main_pm_read_reg(mbox->mfd->rtc, RTC_REG_UPDATE, &update_val); + if (ret) { dev_err(mbox->device, "%s: Fail to read RTC_UPDATE ret: %d\n", __func__, ret); return ret; @@ -743,20 +837,61 @@ static int acpm_mfd_set_pmic(void) __func__); return -ENODEV; } - s2mpg11 = i2c_get_clientdata(i2c_sub); + mbox->mfd->s2mpg_sub = i2c_get_clientdata(i2c_sub); } else dev_err(mbox->device, "%s: Cannot find sub-pmic\n", __func__); of_node_put(p_np); - if (!s2mpg11) { - dev_err(mbox->device, "%s: S2MPG11 device not found\n", + if (!mbox->mfd->s2mpg_sub) { + dev_err(mbox->device, "%s: S2MPG-Sub device not found\n", __func__); return -ENODEV; } - i2c_set_clientdata(s2mpg11->pmic, s2mpg11); - mbox->mfd->s2mpg11_pmic = s2mpg11->pmic; + i2c_set_clientdata(mbox->mfd->s2mpg_sub->pmic, mbox->mfd->s2mpg_sub); + mbox->mfd->sub_pmic = mbox->mfd->s2mpg_sub->pmic; + mbox->mfd->sub_channel = 1; + + len = of_property_count_u32_elems(np, "mfd-regulator-list-main"); + if (len <= 0) { + dev_err(mbox->device, + "%s: main regulator list not found, len: %d\n", + __func__, len); + } else { + mbox->mfd->num_of_main_regulator_regs = len; + + regulator_list = kcalloc(len, sizeof(unsigned int), GFP_KERNEL); + + of_property_read_u32_array(np, "mfd-regulator-list-main", + regulator_list, len); + + mbox->mfd->regulator_lst_main = regulator_list; + + for (i = 0; i < len; i++) + dev_dbg(mbox->device, "%s: main regulator_lst: 0x%X\n", + __func__, mbox->mfd->regulator_lst_main[i]); + } + + len = of_property_count_u32_elems(np, "mfd-regulator-list-sub"); + if (len <= 0) { + dev_err(mbox->device, + "%s: sub regulator list not found, len: %d\n", + __func__, len); + } else { + mbox->mfd->num_of_sub_regulator_regs = len; + + regulator_list = kcalloc(len, sizeof(unsigned int), GFP_KERNEL); + + of_property_read_u32_array(np, "mfd-regulator-list-sub", + regulator_list, len); + + mbox->mfd->regulator_lst_sub = regulator_list; + + for (i = 0; i < len; i++) + dev_dbg(mbox->device, "%s: sub regulator_lst: 0x%X\n", + __func__, mbox->mfd->regulator_lst_sub[i]); + } mbox->mfd->init_done = 1; @@ -819,13 +954,13 @@ static void acpm_mbox_test_init(void) snprintf(buf, sizeof(buf), "acpm_dvfs_req_wq%d", i); mbox->dvfs->rate_change_wq[i] = create_freezable_workqueue(buf); - snprintf(buf, sizeof(buf), "acpm_s2mpg10_mfd_rd_wq%d", - i); - mbox->mfd->s2mpg10_mfd_read_wq[i] = + snprintf(buf, sizeof(buf), + "acpm_s2mpg_main_mfd_rd_wq%d", i); + mbox->mfd->main_pm_mfd_read_wq[i] = create_freezable_workqueue(buf); - snprintf(buf, sizeof(buf), "acpm_s2mpg11_mfd_rd_wq%d", + snprintf(buf, sizeof(buf), "acpm_s2mpg_sub_mfd_rd_wq%d", i); - mbox->mfd->s2mpg11_mfd_read_wq[i] = + mbox->mfd->sub_pm_mfd_read_wq[i] = create_freezable_workqueue(buf); snprintf(buf, sizeof(buf), "acpm_slc_request_wq%d", i); mbox->slc->slc_request_wq[i] = @@ -851,10 +986,10 @@ static void acpm_mbox_test_init(void) acpm_debug_tmu_rd_tmp_concur); INIT_DELAYED_WORK(&mbox->dvfs->rate_change_wk[i], acpm_mbox_dvfs_rate_random_change); - INIT_DELAYED_WORK(&mbox->mfd->s2mpg10_mfd_read_wk[i], - acpm_mbox_mfd_s2mpg10_random_read); - INIT_DELAYED_WORK(&mbox->mfd->s2mpg11_mfd_read_wk[i], - acpm_mbox_mfd_s2mpg11_random_read); + INIT_DELAYED_WORK(&mbox->mfd->main_pm_mfd_read_wk[i], + acpm_mbox_mfd_main_pm_random_read); + INIT_DELAYED_WORK(&mbox->mfd->sub_pm_mfd_read_wk[i], + acpm_mbox_mfd_sub_pm_random_read); INIT_DELAYED_WORK(&mbox->slc->slc_request_wk[i], acpm_mbox_slc_request_send); } @@ -915,8 +1050,7 @@ static int dvfs_freq_table_init(void) dev_info(mbox->device, "%s: dvfs_test->dm[%d]->table[%d] = %d Hz\n", __func__, i, index, - dvfs_test->dm[i]->table[index]. - freq); + dvfs_test->dm[i]->table[index].freq); } } dvfs_test->init_done = true; @@ -934,8 +1068,7 @@ static void acpm_framework_mbox_test(bool start) queue_delayed_work_on(get_random_for_type(CPU_ID), mbox->tmu->suspend_wq, &mbox->tmu->suspend_work, - msecs_to_jiffies - (TMU_SUSPEND_RESUME_DELAY)); + msecs_to_jiffies(TMU_SUSPEND_RESUME_DELAY)); queue_delayed_work_on(get_random_for_type(CPU_ID), mbox->tmu->rd_tmp_stress_trigger_wq, &mbox->tmu->rd_tmp_stress_trigger_wk, @@ -1235,12 +1368,9 @@ static void acpm_dvfs_stats_dump(void) "%s: dm_id[%d], set_rate: %d Hz, " "get_rate: %d Hz, latency= %u ns\n", __func__, dm_id, - dvfs_test->dm[dm_id]->stats[cycle]. - set_rate, - dvfs_test->dm[dm_id]->stats[cycle]. - get_rate, - dvfs_test->dm[dm_id]->stats[cycle]. - latency); + dvfs_test->dm[dm_id]->stats[cycle].set_rate, + dvfs_test->dm[dm_id]->stats[cycle].get_rate, + dvfs_test->dm[dm_id]->stats[cycle].latency); dev_info(mbox->device, "\n"); } } @@ -1323,6 +1453,32 @@ static int debug_dvfs_latency_stats_set(void *data, u64 val) return dvfs_latency_stats_setting(acpm, val); } +static int debug_dvfs_latency_stats_get(void *data, unsigned long long *val) +{ + u32 dm_id, delayed_latency_ratio, cycle_cnt, scale_cnt; + + for (dm_id = DVFS_MIF; dm_id < NUM_OF_DVFS_DOMAINS; dm_id++) { + if (dm_id == DVFS_G3D || dm_id == DVFS_G3DL2 + || dm_id == DVFS_TPU) + continue; + + if (!dvfs_test->dm[dm_id]) + return -ENOENT; + + if (dvfs_test->dm[dm_id]->total_cycle_cnt) { + cycle_cnt = dvfs_test->dm[dm_id]->total_cycle_cnt; + scale_cnt = dvfs_test->dm[dm_id]->scales[SLOW_LATENCY_IDX].count; + delayed_latency_ratio = scale_cnt * 100 / cycle_cnt; + if (delayed_latency_ratio > LATENCY_FAIL_CRITERIA) { + /*Flag domains with unusually slow DVFS latency*/ + *val |= 1 << dm_id; + } + } + } + + return 0; +} + static void acpm_acpm_mbox_dvfs(bool start) { if (start) { @@ -1371,8 +1527,9 @@ static int debug_acpm_mbox_dvfs_set(void *data, u64 val) DEFINE_SIMPLE_ATTRIBUTE(debug_acpm_mbox_test_fops, debug_acpm_mbox_test_get, debug_acpm_mbox_test_set, "0x%016llx\n"); -DEFINE_SIMPLE_ATTRIBUTE(debug_dvfs_latency_stats_fops, NULL, - debug_dvfs_latency_stats_set, "0x%016llx\n"); +DEFINE_SIMPLE_ATTRIBUTE(debug_dvfs_latency_stats_fops, + debug_dvfs_latency_stats_get, debug_dvfs_latency_stats_set, + "0x%016llx\n"); DEFINE_SIMPLE_ATTRIBUTE(debug_acpm_mbox_dvfs_fops, NULL, debug_acpm_mbox_dvfs_set, "0x%016llx\n"); @@ -1624,7 +1781,9 @@ static int acpm_mbox_test_probe(struct platform_device *pdev) acpm_test_debugfs_init(mbox_test); - mutex_init(&mbox_test->mfd->lock); + mutex_init(&mbox_test->mfd->rtc_lock); + mutex_init(&mbox_test->mfd->main_pm_lock); + mutex_init(&mbox_test->mfd->sub_pm_lock); mbox = mbox_test; dvfs_test = dvfs; @@ -1659,8 +1818,8 @@ static int acpm_mbox_test_remove(struct platform_device *pdev) flush_workqueue(mbox->tmu->rd_tmp_random_wq[i]); flush_workqueue(mbox->tmu->rd_tmp_concur_wq[i]); flush_workqueue(mbox->dvfs->rate_change_wq[i]); - flush_workqueue(mbox->mfd->s2mpg10_mfd_read_wq[i]); - flush_workqueue(mbox->mfd->s2mpg11_mfd_read_wq[i]); + flush_workqueue(mbox->mfd->main_pm_mfd_read_wq[i]); + flush_workqueue(mbox->mfd->sub_pm_mfd_read_wq[i]); flush_workqueue(mbox->slc->slc_request_wq[i]); } @@ -1674,12 +1833,14 @@ static int acpm_mbox_test_remove(struct platform_device *pdev) destroy_workqueue(mbox->tmu->rd_tmp_random_wq[i]); destroy_workqueue(mbox->tmu->rd_tmp_concur_wq[i]); destroy_workqueue(mbox->dvfs->rate_change_wq[i]); - destroy_workqueue(mbox->mfd->s2mpg10_mfd_read_wq[i]); - destroy_workqueue(mbox->mfd->s2mpg11_mfd_read_wq[i]); + destroy_workqueue(mbox->mfd->main_pm_mfd_read_wq[i]); + destroy_workqueue(mbox->mfd->sub_pm_mfd_read_wq[i]); destroy_workqueue(mbox->slc->slc_request_wq[i]); } - mutex_destroy(&mbox->mfd->lock); + mutex_destroy(&mbox->mfd->rtc_lock); + mutex_destroy(&mbox->mfd->main_pm_lock); + mutex_destroy(&mbox->mfd->sub_pm_lock); dev_info(mbox->device, "%s done.\n", __func__); kfree(mbox); diff --git a/drivers/soc/google/acpm/acpm_mbox_test.h b/drivers/soc/google/acpm/acpm_mbox_test.h index c8c2643850aa..c7064d34a3ad 100644 --- a/drivers/soc/google/acpm/acpm_mbox_test.h +++ b/drivers/soc/google/acpm/acpm_mbox_test.h @@ -6,8 +6,13 @@ #ifndef __ACPM_MBOX_TEST_H__ #define __ACPM_MBOX_TEST_H__ #include +#if defined(CONFIG_SOC_GS101) #include #include +#elif defined(CONFIG_SOC_GS201) +#include +#include +#endif enum tz_id { TZ_BIG = 0, @@ -119,6 +124,72 @@ enum pmic_id { NUM_OF_PMIC_ID, }; +#if defined(CONFIG_SOC_GS101) +/* RTC(0x2) Registers */ +enum GS101_S2MPG10_RTC_REG { + RTC_REG_CTRL = 0x0, + RTC_REG_UPDATE = 0x1, + RTC_REG_SMPL = 0x2, + RTC_REG_WTSR = 0x3, + RTC_REG_CAPSEL = 0x4, + RTC_REG_MSEC = 0x5, + RTC_REG_SEC = 0x6, + RTC_REG_MIN = 0x7, + RTC_REG_HOUR = 0x8, + RTC_REG_WEEK = 0x9, + RTC_REG_DAY = 0xA, + RTC_REG_MON = 0xB, + RTC_REG_YEAR = 0xC, + RTC_REG_A0SEC = 0xD, + RTC_REG_A0MIN = 0xE, + RTC_REG_A0HOUR = 0xF, + RTC_REG_A0WEEK = 0x10, + RTC_REG_A0DAY = 0x11, + RTC_REG_A0MON = 0x12, + RTC_REG_A0YEAR = 0x13, + RTC_REG_A1SEC = 0x14, + RTC_REG_A1MIN = 0x15, + RTC_REG_A1HOUR = 0x16, + RTC_REG_A1WEEK = 0x17, + RTC_REG_A1DAY = 0x18, + RTC_REG_A1MON = 0x19, + RTC_REG_A1YEAR = 0x1A, + RTC_REG_OSCCTRL = 0x1B, +}; +#elif defined(CONFIG_SOC_GS201) +/* RTC(0x2) Registers */ +enum GS201_S2MPG12_RTC_REG { + RTC_REG_CTRL = 0x0, + RTC_REG_UPDATE = 0x1, + RTC_REG_SMPL = 0x2, + RTC_REG_WTSR = 0x3, + RTC_REG_CAPSEL = 0x4, + RTC_REG_MSEC = 0x5, + RTC_REG_SEC = 0x6, + RTC_REG_MIN = 0x7, + RTC_REG_HOUR = 0x8, + RTC_REG_WEEK = 0x9, + RTC_REG_DAY = 0xA, + RTC_REG_MON = 0xB, + RTC_REG_YEAR = 0xC, + RTC_REG_A0SEC = 0xD, + RTC_REG_A0MIN = 0xE, + RTC_REG_A0HOUR = 0xF, + RTC_REG_A0WEEK = 0x10, + RTC_REG_A0DAY = 0x11, + RTC_REG_A0MON = 0x12, + RTC_REG_A0YEAR = 0x13, + RTC_REG_A1SEC = 0x14, + RTC_REG_A1MIN = 0x15, + RTC_REG_A1HOUR = 0x16, + RTC_REG_A1WEEK = 0x17, + RTC_REG_A1DAY = 0x18, + RTC_REG_A1MON = 0x19, + RTC_REG_A1YEAR = 0x1A, + RTC_REG_OSCCTRL = 0x1B, +}; +#endif + #define NUM_OF_WQ 16 /* IPC Mailbox Channel */ @@ -168,53 +239,37 @@ struct acpm_dvfs_validity { #define SECS_PER_HR 3600 #define SECS_PER_MIN 60 -#define BUCK1M_OUT1 (0x119) -#define BUCK2M_OUT1 (0x11C) -#define BUCK3M_OUT1 (0x11F) -#define BUCK4M_OUT1 (0x122) -#define BUCK5M_OUT1 (0x125) -#define BUCK6M_OUT1 (0x128) -#define BUCK7M_OUT1 (0x12B) -#define BUCK10M_OUT1 (0x134) -#define LDO12M_CTRL1 (0x14C) -#define LDO13M_CTRL1 (0x14E) -#define LDO15M_CTRL1 (0x151) - -#define BUCK1S_OUT1 (0x113) -#define BUCK2S_OUT1 (0x116) -#define BUCK3S_OUT1 (0x119) -#define BUCK4S_OUT (0x11C) -#define BUCK5S_OUT (0x11E) -#define BUCK8S_OUT1 (0x126) -#define BUCK9S_OUT1 (0x129) -#define LDO2S_CTRL1 (0x143) - -static u16 def_lck_regs_m[NUM_OF_PMIC_MASTER] = { - BUCK1M_OUT1, BUCK2M_OUT1, BUCK3M_OUT1, BUCK4M_OUT1, - BUCK5M_OUT1, BUCK6M_OUT1, BUCK7M_OUT1, BUCK10M_OUT1, - LDO12M_CTRL1, LDO13M_CTRL1, LDO15M_CTRL1 -}; - -static u16 def_lck_regs_s[NUM_OF_PMIC_ID - NUM_OF_PMIC_MASTER] = { - BUCK1S_OUT1, BUCK2S_OUT1, BUCK3S_OUT1, BUCK4S_OUT, - BUCK5S_OUT, BUCK8S_OUT1, BUCK9S_OUT1, LDO2S_CTRL1 -}; - struct acpm_mfd_validity { - struct i2c_client *s2mpg10_pmic; - struct i2c_client *s2mpg11_pmic; +#if defined(CONFIG_SOC_GS101) + struct s2mpg10_dev *s2mpg_main; + struct s2mpg11_dev *s2mpg_sub; +#elif defined(CONFIG_SOC_GS201) + struct s2mpg12_dev *s2mpg_main; + struct s2mpg13_dev *s2mpg_sub; +#endif + struct i2c_client *main_pmic; + struct i2c_client *sub_pmic; struct i2c_client *rtc; - struct delayed_work s2mpg10_mfd_read_wk[NUM_OF_WQ]; - struct delayed_work s2mpg11_mfd_read_wk[NUM_OF_WQ]; + struct delayed_work main_pm_mfd_read_wk[NUM_OF_WQ]; + struct delayed_work sub_pm_mfd_read_wk[NUM_OF_WQ]; struct delayed_work mbox_stress_trigger_wk; - struct workqueue_struct *s2mpg10_mfd_read_wq[NUM_OF_WQ]; - struct workqueue_struct *s2mpg11_mfd_read_wq[NUM_OF_WQ]; + struct workqueue_struct *main_pm_mfd_read_wq[NUM_OF_WQ]; + struct workqueue_struct *sub_pm_mfd_read_wq[NUM_OF_WQ]; struct workqueue_struct *mbox_stress_trigger_wq; u8 update_reg; + u8 main_channel; + u8 sub_channel; /* mutex for RTC */ - struct mutex lock; + struct mutex rtc_lock; + /* mutex for Main/Sub PMIC */ + struct mutex main_pm_lock; + struct mutex sub_pm_lock; int ctrlist_err_result; int init_done; + int *regulator_lst_main; + int *regulator_lst_sub; + int num_of_main_regulator_regs; + int num_of_sub_regulator_regs; }; #define PT_VERSION 0xd005 @@ -265,12 +320,14 @@ struct dvfs_frequency_table { }; struct stats_scale { - int limit; /* in us */ - int count; + unsigned int limit; /* in us */ + unsigned int count; }; #define MICRO_SEC 1000 #define TIME_SCALES 12 +#define LATENCY_FAIL_CRITERIA 10 /*the percent of slow DVFS latency*/ +#define SLOW_LATENCY_IDX 11 /*bucket idx for 2ms latency case*/ struct stats_scale buckets[TIME_SCALES] = { { 0, 0 }, { 1, 0 }, { 10, 0 }, { 30, 0 }, { 50, 0 }, { 100, 0 }, { 200, 0 }, { 300, 0 }, diff --git a/drivers/soc/google/acpm/fw_header/acpm_power_stats.h b/drivers/soc/google/acpm/fw_header/acpm_power_stats.h index 3473bb042163..3757a17b73cf 100644 --- a/drivers/soc/google/acpm/fw_header/acpm_power_stats.h +++ b/drivers/soc/google/acpm/fw_header/acpm_power_stats.h @@ -33,6 +33,9 @@ enum sys_powermode { enum mif_users { MIF_USER_AOC, MIF_USER_GSA, +#if defined(CONFIG_SOC_GS201) + MIF_USER_TPU, +#endif NUM_MIF_USERS, // NR_MIF_USERS in plugins/flexpmu//sfr_map.h }; @@ -68,6 +71,9 @@ enum fvp_domains { DOMAIN_CPUCL0, DOMAIN_CPUCL1, DOMAIN_CPUCL2, +#if defined(CONFIG_SOC_GS201) + DOMAIN_AUR, +#endif NUM_DOMAINS, }; diff --git a/drivers/soc/google/acpm/power_stats.c b/drivers/soc/google/acpm/power_stats.c index a470b75f9ae5..8628cea4d37e 100644 --- a/drivers/soc/google/acpm/power_stats.c +++ b/drivers/soc/google/acpm/power_stats.c @@ -25,7 +25,11 @@ #define GS_POWER_STATS_PREFIX "power_stats: " +#if defined(CONFIG_SOC_GS101) static char const *const mif_user_names[NUM_MIF_USERS] = { "AOC", "GSA" }; +#elif defined(CONFIG_SOC_GS201) +static char const *const mif_user_names[NUM_MIF_USERS] = { "AOC", "GSA", "TPU" }; +#endif static char const *const slc_user_names[NUM_SLC_USERS] = { "AOC" }; @@ -40,8 +44,13 @@ static char const *const core_names[NUM_CORES] = { "CORE00", "CORE01", "CORE02", "CORE03", "CORE10", "CORE11", "CORE20", "CORE21" }; +#if defined(CONFIG_SOC_GS101) static char const *const domain_names[NUM_DOMAINS] = { "MIF", "TPU", "CL0", "CL1", "CL2" }; +#elif defined(CONFIG_SOC_GS201) +static char const *const domain_names[NUM_DOMAINS] = { "MIF", "TPU", "CL0", + "CL1", "CL2", "AUR" }; +#endif struct pd_entry { struct list_head entry; @@ -522,6 +531,24 @@ static int init_stat_node(struct platform_device *pdev, const char *buffer_name, return ret; } +static int check_exynos_pd_initialized(struct device *dev) +{ + struct platform_device *pdev; + struct device_node *np; + + for_each_compatible_node (np, NULL, "samsung,exynos-pd") { + if (of_device_is_available(np)) { + pdev = of_find_device_by_node(np); + if (!platform_get_drvdata(pdev)) { + dev_info(dev, "defer probe, %s not ready\n", + dev_name(&pdev->dev)); + return -EPROBE_DEFER; + } + } + } + return 0; +} + static int init_pd_stat_node(struct power_stats_device *ps_dev) { struct device_node *np; @@ -536,6 +563,8 @@ static int init_pd_stat_node(struct power_stats_device *ps_dev) pdev = of_find_device_by_node(np); pd = (struct exynos_pm_domain *)platform_get_drvdata( pdev); + if (!pd) + return -EINVAL; new_pd_entry = devm_kzalloc( ps_dev->dev, sizeof(*new_pd_entry), GFP_KERNEL); @@ -569,11 +598,15 @@ ATTRIBUTE_GROUPS(power_stats); static int power_stats_probe(struct platform_device *pdev) { - int ret = 0; + int ret; u32 timer_freq_hz; + struct power_stats_device *ps_dev; + + ret = check_exynos_pd_initialized(&pdev->dev); + if (ret) + return ret; - struct power_stats_device *ps_dev = - devm_kzalloc(&pdev->dev, sizeof(*ps_dev), GFP_KERNEL); + ps_dev = devm_kzalloc(&pdev->dev, sizeof(*ps_dev), GFP_KERNEL); if (!ps_dev) return -ENOMEM; @@ -660,6 +693,9 @@ static void __exit power_stats_exit(void) module_init(power_stats_init); module_exit(power_stats_exit); +#if defined(CONFIG_SOC_GS201) +MODULE_SOFTDEP("pre: exynos-pm"); +#endif MODULE_AUTHOR("Benjamin Schwartz "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("APM power stats collection"); diff --git a/drivers/soc/google/cal-if/Makefile b/drivers/soc/google/cal-if/Makefile index be81759f204e..ba1ea724b632 100644 --- a/drivers/soc/google/cal-if/Makefile +++ b/drivers/soc/google/cal-if/Makefile @@ -10,7 +10,8 @@ cmupmucal-$(CONFIG_PMUCAL) += pmucal_system.o pmucal_local.o pmucal_cpu.o pmuca cmupmucal-$(CONFIG_PMUCAL_DBG) += pmucal_dbg.o cmupmucal-$(CONFIG_SOC_EXYNOS9820) += exynos9820/cal_data.o cmupmucal-$(CONFIG_SOC_GS101) += gs101/cal_data.o +cmupmucal-$(CONFIG_SOC_GS201) += gs201/cal_data.o cmupmucal-$(CONFIG_ACPM_DVFS) += acpm_dvfs.o fvmap.o -cmupmucal-$(CONFIG_CP_PMUCAL) += pmucal_cp.o +cmupmucal-$(CONFIG_CP_PMUCAL) += pmucal_cp.o obj-$(CONFIG_CMU_EWF) += cmu_ewf.o diff --git a/drivers/soc/google/cal-if/cal-if.c b/drivers/soc/google/cal-if/cal-if.c index 15562245d3de..39e558d6d4bd 100644 --- a/drivers/soc/google/cal-if/cal-if.c +++ b/drivers/soc/google/cal-if/cal-if.c @@ -29,6 +29,8 @@ #include "../acpm/acpm.h" +extern s32 gs_chipid_get_dvfs_version(void); + int (*exynos_cal_pd_bcm_sync)(unsigned int id, bool on); EXPORT_SYMBOL(exynos_cal_pd_bcm_sync); @@ -473,8 +475,14 @@ int cal_if_init(void *np) return 0; prop = of_get_property(np, "minmax_idx", &len); - if (prop) + if (prop) { minmax_idx = be32_to_cpup(prop); + } else { + int dvfs_version = gs_chipid_get_dvfs_version(); + if (dvfs_version < 0) + return dvfs_version; + minmax_idx = dvfs_version; + } ect_parse_binary_header(); diff --git a/drivers/soc/google/cal-if/gs201/acpm_dvfs_gs201.h b/drivers/soc/google/cal-if/gs201/acpm_dvfs_gs201.h new file mode 100644 index 000000000000..7ebca1e7bf7e --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/acpm_dvfs_gs201.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +enum acpm_dvfs_id { + MIF = ACPM_VCLK_TYPE, + INT, + CPUCL0, + CPUCL1, + CPUCL2, + G3D, + G3DL2, + TPU, + INTCAM, + TNR, + CAM, + MFC, + DISP, + BO, +}; + +struct vclk acpm_vclk_list[] = { + CMUCAL_ACPM_VCLK(MIF, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(INT, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(CPUCL0, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(CPUCL1, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(CPUCL2, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(G3D, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(G3DL2, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(TPU, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(INTCAM, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(TNR, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(CAM, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(MFC, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(DISP, NULL, NULL, NULL, NULL), + CMUCAL_ACPM_VCLK(BO, NULL, NULL, NULL, NULL), +}; + +unsigned int acpm_vclk_size = ARRAY_SIZE(acpm_vclk_list); diff --git a/drivers/soc/google/cal-if/gs201/asv_gs201.h b/drivers/soc/google/cal-if/gs201/asv_gs201.h new file mode 100644 index 000000000000..fbf947a313ad --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/asv_gs201.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __ASV_GS201_H__ +#define __ASV_GS201_H__ + +int asv_get_grp(unsigned int id) +{ + int grp = -1; + + return grp; +} + +int asv_get_ids_info(unsigned int id) +{ + int ids = 0; + + return ids; +} + +#endif diff --git a/drivers/soc/google/cal-if/gs201/cal_data.c b/drivers/soc/google/cal-if/gs201/cal_data.c new file mode 100644 index 000000000000..e9f6857080c9 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cal_data.c @@ -0,0 +1,89 @@ +#include "../pmucal_common.h" +#include "../pmucal_cpu.h" +#include "../pmucal_local.h" +#include "../pmucal_rae.h" +#include "../pmucal_system.h" +#include "../pmucal_powermode.h" + +#include "flexpmu_cal_cpu_gs201.h" +#include "flexpmu_cal_local_gs201.h" +#include "flexpmu_cal_p2vmap_gs201.h" +#include "flexpmu_cal_system_gs201.h" +#include "flexpmu_cal_define_gs201.h" + +#include "cmucal-node.c" +#include "cmucal-qch.c" +#include "cmucal-sfr.c" +#include "cmucal-vclk.c" +#include "cmucal-vclklut.c" +#include "cmu-pmu_map.h" + +#include "clkout_gs201.c" + +#include "acpm_dvfs_gs201.h" + +#include "asv_gs201.h" + +#include "../ra.h" + +#include + +extern unsigned int fin_hz_var; +void __iomem *gpio_alive; + +#define GPIO_ALIVE_BASE (0x180D0000) +#define GPA1_DAT (0x24) + +struct cmu_pmu cmu_pmu_map[] = { + /* TODO: will be added after bring-up done */ +}; + +void gs201_cal_data_init(void) +{ + pr_info("%s: cal data init\n", __func__); + + /* cpu inform sfr initialize */ + pmucal_sys_powermode[SYS_SICD] = CPU_INFORM_SICD; + pmucal_sys_powermode[SYS_SLEEP] = CPU_INFORM_SLEEP; + pmucal_sys_powermode[SYS_SLEEP_SLCMON] = CPU_INFORM_SLEEP_SLCMON; + pmucal_sys_powermode[SYS_SLEEP_HSI1ON] = CPU_INFORM_SLEEP_HSI1ON; + + cpu_inform_c2 = CPU_INFORM_C2; + cpu_inform_cpd = CPU_INFORM_CPD; + + gpio_alive = ioremap(GPIO_ALIVE_BASE, SZ_4K); + if (!gpio_alive) { + pr_err("%s: gpio_alive ioremap failed\n", __func__); + BUG(); + } + + /* check DEBUG_SEL and determine FIN src */ + if (__raw_readl(gpio_alive + GPA1_DAT) & (1 << 6)) + fin_hz_var = FIN_HZ_26M; + else + fin_hz_var = 24576000; + + cmucal_dbg_mux_dbg_offset(0x4004); +} + +void (*cal_data_init)(void) = gs201_cal_data_init; +int (*wa_set_cmuewf)(unsigned int index, unsigned int en, void *cmu_cmu, int *ewf_refcnt) = NULL; +void (*cal_set_cmu_smpl_warn)(void) = NULL; + +char *gs201_get_pd_name_by_cmu(unsigned int addr) +{ + int i, map_size; + + map_size = ARRAY_SIZE(cmu_pmu_map); + for (i = 0; i < map_size; i++) { + if (cmu_pmu_map[i].cmu == addr) + break; + } + + if (i < map_size) + return cmu_pmu_map[i].pmu; + + return NULL; +} + +char *(*cal_get_pd_name_by_cmu)(unsigned int addr) = gs201_get_pd_name_by_cmu; diff --git a/drivers/soc/google/cal-if/gs201/clkout_gs201.c b/drivers/soc/google/cal-if/gs201/clkout_gs201.c new file mode 100644 index 000000000000..087c6ed1113a --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/clkout_gs201.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "clkout_gs201.h" + +#define CLKOUT0_OFFSET (0x3e80) +#define CLKOUT0_SEL_SHIFT (8) +#define CLKOUT0_SEL_WIDTH (6) +#define CLKOUT0_SEL_TCXO (0x0) +#define CLKOUT0_ENABLE_SHIFT (0) +#define CLKOUT0_ENABLE_WIDTH (1) + +#define CLKOUT1_OFFSET (0x3e84) +#define CLKOUT1_SEL_SHIFT (8) +#define CLKOUT1_SEL_WIDTH (6) +#define CLKOUT1_SEL_TCXO (0x0) +#define CLKOUT1_ENABLE_SHIFT (0) +#define CLKOUT1_ENABLE_WIDTH (1) + +struct cmucal_clkout cmucal_clkout_list[] = { + CLKOUT(VCLK_CLKOUT0, CLKOUT0_OFFSET, CLKOUT0_SEL_SHIFT, CLKOUT0_SEL_WIDTH, CLKOUT0_SEL_TCXO, CLKOUT0_ENABLE_SHIFT, CLKOUT0_ENABLE_WIDTH), + CLKOUT(VCLK_CLKOUT1, CLKOUT1_OFFSET, CLKOUT1_SEL_SHIFT, CLKOUT1_SEL_WIDTH, CLKOUT1_SEL_TCXO, CLKOUT1_ENABLE_SHIFT, CLKOUT1_ENABLE_WIDTH), +}; + +unsigned int cmucal_clkout_size = 2; diff --git a/drivers/soc/google/cal-if/gs201/clkout_gs201.h b/drivers/soc/google/cal-if/gs201/clkout_gs201.h new file mode 100644 index 000000000000..042390bb2737 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/clkout_gs201.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +enum cmucal_clkout_id { + VCLK_CLKOUT0 = CLKOUT_TYPE, + VCLK_CLKOUT1, +}; diff --git a/drivers/soc/google/cal-if/gs201/cmu-pmu_map.h b/drivers/soc/google/cal-if/gs201/cmu-pmu_map.h new file mode 100644 index 000000000000..3f2951d33fe1 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmu-pmu_map.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Defines CMU_PMU mapping table. + * + * Copyright (c) 2020-2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMU_PMU_MAP_H__ +#define __CMU_PMU_MAP_H__ + +struct cmu_pmu { + unsigned int cmu; + char pmu[20]; +}; + +#endif diff --git a/drivers/soc/google/cal-if/gs201/cmucal-node.c b/drivers/soc/google/cal-if/gs201/cmucal-node.c new file mode 100644 index 000000000000..6f9d443de0fa --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-node.c @@ -0,0 +1,3594 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "../cmucal.h" +#include "cmucal-node.h" +#include "cmucal-sfr.h" + +struct cmucal_pll_table pll_aur_rate_table[] = { + PLL_RATE_MPS(1150000000, 234, 5, 0), + PLL_RATE_MPS(747000000, 152, 5, 0), + PLL_RATE_MPS(373000000, 334, 11, 1), + PLL_RATE_MPS(178000000, 116, 4, 2), +}; + +struct cmucal_pll_table pll_shared0_rate_table[] = { + PLL_RATE_MPS(2132999936, 347, 4, 0), +}; + +struct cmucal_pll_table pll_shared1_rate_table[] = { + PLL_RATE_MPS(1866000000, 455, 6, 0), +}; + +struct cmucal_pll_table pll_shared2_rate_table[] = { + PLL_RATE_MPS(800000000, 358, 11, 0), +}; + +struct cmucal_pll_table pll_shared3_rate_table[] = { + PLL_RATE_MPS(666000000, 298, 11, 0), +}; + +struct cmucal_pll_table pll_spare_rate_table[] = { + PLL_RATE_MPS(2400000000, 488, 5, 0), +}; + +struct cmucal_pll_table pll_lf_mif_rate_table[] = { + PLL_RATE_MPS(2132999936, 347, 4, 0), + PLL_RATE_MPS(1420000000, 231, 4, 0), + PLL_RATE_MPS(711000000, 231, 4, 1), +}; + +struct cmucal_pll_table pll_cpucl0_rate_table[] = { + PLL_RATE_MPS(2100000000, 256, 3, 0), + PLL_RATE_MPS(1800000000, 293, 4, 0), + PLL_RATE_MPS(1400000000, 341, 6, 0), + PLL_RATE_MPS(930000000, 227, 3, 1), + PLL_RATE_MPS(580000000, 472, 5, 2), + PLL_RATE_MPS(300000000, 195, 4, 2), +}; + +struct cmucal_pll_table pll_cpucl1_rate_table[] = { + PLL_RATE_MPS(2350000128, 478, 5, 0), + PLL_RATE_MPS(2000000000, 407, 5, 0), + PLL_RATE_MPS(1495000064, 304, 5, 0), + PLL_RATE_MPS(1027000000, 209, 5, 0), + PLL_RATE_MPS(700000000, 171, 3, 1), + PLL_RATE_MPS(400000000, 195, 3, 2), +}; + +struct cmucal_pll_table pll_cpucl2_rate_table[] = { + PLL_RATE_MPSK(2849999872, 174, 3, 0, 0), + PLL_RATE_MPSK(2249999872, 366, 4, 1, 0), + PLL_RATE_MPSK(1824999936, 297, 4, 1, 0), + PLL_RATE_MPSK(1275000064, 415, 4, 2, 0), + PLL_RATE_MPSK(850000000, 346, 5, 2, 0), + PLL_RATE_MPSK(500000000, 244, 3, 3, 0), +}; + +struct cmucal_pll_table pll_g3d_rate_table[] = { + PLL_RATE_MPS(850000000, 415, 12, 0), + PLL_RATE_MPS(700000000, 256, 9, 0), + PLL_RATE_MPS(470000000, 229, 6, 1), + PLL_RATE_MPS(150000000, 537, 11, 3), +}; + +struct cmucal_pll_table pll_g3d_l2_rate_table[] = { + PLL_RATE_MPS(1000000000, 244, 6, 0), + PLL_RATE_MPS(750000000, 122, 4, 0), + PLL_RATE_MPS(470000000, 153, 4, 1), + PLL_RATE_MPS(150000000, 98, 4, 2), +}; + +struct cmucal_pll_table pll_usb_rate_table[] = { + PLL_RATE_MPS(614400000, 100, 4, 0), +}; + +struct cmucal_pll_table pll_mif_main_rate_table[] = { + PLL_RATE_MPSK(6400000000, 651, 5, 0, 0), + PLL_RATE_MPSK(3732000000, 228, 3, 0, 0), + PLL_RATE_MPSK(2688000000, 328, 3, 1, 0), + PLL_RATE_MPSK(1422000000, 463, 4, 2, 0), + PLL_RATE_MPSK(710000000, 289, 5, 2, 0), +}; + +struct cmucal_pll_table pll_mif_sub_rate_table[] = { + PLL_RATE_MPSK(6400000000, 651, 5, 0, 0), + PLL_RATE_MPSK(3732000000, 228, 3, 0, 0), + PLL_RATE_MPSK(2688000000, 328, 3, 1, 0), + PLL_RATE_MPSK(1422000000, 463, 4, 2, 0), + PLL_RATE_MPSK(842000000, 289, 5, 2, 0), +}; + +struct cmucal_pll_table pll_nocl0_rate_table[] = { + PLL_RATE_MPS(1067000000, 537, 11, 0), + PLL_RATE_MPS(980000000, 319, 8, 0), + PLL_RATE_MPS(640000000, 537, 11, 0), + PLL_RATE_MPS(320000000, 537, 11, 0), + PLL_RATE_MPS(133000000, 173, 4, 3), +}; + +struct cmucal_pll_table pll_mif_s2d_rate_table[] = { + PLL_RATE_MPSK(400000000, 651, 5, 4, 0), +}; + +struct cmucal_pll_table pll_tpu_rate_table[] = { + PLL_RATE_MPS(1067000000, 347, 8, 0), + PLL_RATE_MPS(833000000, 237, 7, 0), + PLL_RATE_MPS(622000000, 253, 10, 0), + PLL_RATE_MPS(350000000, 171, 6, 1), +}; + +unsigned int cmucal_pll_size = 18; +struct cmucal_pll cmucal_pll_list[] = { + CLK_PLL(PLL_0518X, PLL_AUR, OSCCLK_AUR, PLL_LOCKTIME_PLL_AUR_PLL_LOCK_TIME, PLL_CON3_PLL_AUR_ENABLE, PLL_CON3_PLL_AUR_STABLE, PLL_CON3_PLL_AUR_DIV_P, PLL_CON3_PLL_AUR_DIV_M, PLL_CON3_PLL_AUR_DIV_S, EMPTY_CAL_ID, pll_aur_rate_table, 0, 0), + CLK_PLL(PLL_0517X, PLL_SHARED0, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED0_ENABLE, PLL_CON3_PLL_SHARED0_STABLE, PLL_CON3_PLL_SHARED0_DIV_P, PLL_CON3_PLL_SHARED0_DIV_M, PLL_CON3_PLL_SHARED0_DIV_S, EMPTY_CAL_ID, pll_shared0_rate_table, 0, 0), + CLK_PLL(PLL_0517X, PLL_SHARED1, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED1_ENABLE, PLL_CON3_PLL_SHARED1_STABLE, PLL_CON3_PLL_SHARED1_DIV_P, PLL_CON3_PLL_SHARED1_DIV_M, PLL_CON3_PLL_SHARED1_DIV_S, EMPTY_CAL_ID, pll_shared1_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_SHARED2, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED2_ENABLE, PLL_CON3_PLL_SHARED2_STABLE, PLL_CON3_PLL_SHARED2_DIV_P, PLL_CON3_PLL_SHARED2_DIV_M, PLL_CON3_PLL_SHARED2_DIV_S, EMPTY_CAL_ID, pll_shared2_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_SHARED3, OSCCLK_CMU, PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, PLL_CON3_PLL_SHARED3_ENABLE, PLL_CON3_PLL_SHARED3_STABLE, PLL_CON3_PLL_SHARED3_DIV_P, PLL_CON3_PLL_SHARED3_DIV_M, PLL_CON3_PLL_SHARED3_DIV_S, EMPTY_CAL_ID, pll_shared3_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_SPARE, OSCCLK_CMU, PLL_LOCKTIME_PLL_SPARE_PLL_LOCK_TIME, PLL_CON3_PLL_SPARE_ENABLE, PLL_CON3_PLL_SPARE_STABLE, PLL_CON3_PLL_SPARE_DIV_P, PLL_CON3_PLL_SPARE_DIV_M, PLL_CON3_PLL_SPARE_DIV_S, EMPTY_CAL_ID, pll_spare_rate_table, 0, 0), + CLK_PLL(PLL_0517X, PLL_LF_MIF, OSCCLK_CMU, PLL_LOCKTIME_PLL_LF_MIF_PLL_LOCK_TIME, PLL_CON3_PLL_LF_MIF_ENABLE, PLL_CON3_PLL_LF_MIF_STABLE, PLL_CON3_PLL_LF_MIF_DIV_P, PLL_CON3_PLL_LF_MIF_DIV_M, PLL_CON3_PLL_LF_MIF_DIV_S, EMPTY_CAL_ID, pll_lf_mif_rate_table, 0, 0), + CLK_PLL(PLL_0517X, PLL_CPUCL0, OSCCLK_CPUCL0, PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL0_ENABLE, PLL_CON3_PLL_CPUCL0_STABLE, PLL_CON3_PLL_CPUCL0_DIV_P, PLL_CON3_PLL_CPUCL0_DIV_M, PLL_CON3_PLL_CPUCL0_DIV_S, EMPTY_CAL_ID, pll_cpucl0_rate_table, 0, 0), + CLK_PLL(PLL_0517X, PLL_CPUCL1, OSCCLK_CPUCL1, PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL1_ENABLE, PLL_CON3_PLL_CPUCL1_STABLE, PLL_CON3_PLL_CPUCL1_DIV_P, PLL_CON3_PLL_CPUCL1_DIV_M, PLL_CON3_PLL_CPUCL1_DIV_S, EMPTY_CAL_ID, pll_cpucl1_rate_table, 0, 0), + CLK_PLL(PLL_0516X, PLL_CPUCL2, OSCCLK_CPUCL2, PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, PLL_CON3_PLL_CPUCL2_ENABLE, PLL_CON3_PLL_CPUCL2_STABLE, PLL_CON3_PLL_CPUCL2_DIV_P, PLL_CON3_PLL_CPUCL2_DIV_M, PLL_CON3_PLL_CPUCL2_DIV_S, EMPTY_CAL_ID, pll_cpucl2_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_G3D, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_ENABLE, PLL_CON3_PLL_G3D_STABLE, PLL_CON3_PLL_G3D_DIV_P, PLL_CON3_PLL_G3D_DIV_M, PLL_CON3_PLL_G3D_DIV_S, EMPTY_CAL_ID, pll_g3d_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_G3D_L2, OSCCLK_G3D, PLL_LOCKTIME_PLL_G3D_L2_PLL_LOCK_TIME, PLL_CON3_PLL_G3D_L2_ENABLE, PLL_CON3_PLL_G3D_L2_STABLE, PLL_CON3_PLL_G3D_L2_DIV_P, PLL_CON3_PLL_G3D_L2_DIV_M, PLL_CON3_PLL_G3D_L2_DIV_S, EMPTY_CAL_ID, pll_g3d_l2_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_USB, OSCCLK_HSI0, PLL_LOCKTIME_PLL_USB_PLL_LOCK_TIME, PLL_CON3_PLL_USB_ENABLE, PLL_CON3_PLL_USB_STABLE, PLL_CON3_PLL_USB_DIV_P, PLL_CON3_PLL_USB_DIV_M, PLL_CON3_PLL_USB_DIV_S, EMPTY_CAL_ID, pll_usb_rate_table, 0, 0), + CLK_PLL(PLL_0516X, PLL_MIF_MAIN, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_MAIN_ENABLE, PLL_CON3_PLL_MIF_MAIN_STABLE, PLL_CON3_PLL_MIF_MAIN_DIV_P, PLL_CON3_PLL_MIF_MAIN_DIV_M, PLL_CON3_PLL_MIF_MAIN_DIV_S, EMPTY_CAL_ID, pll_mif_main_rate_table, 0, 0), + CLK_PLL(PLL_0516X, PLL_MIF_SUB, OSCCLK_MIF, PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_SUB_ENABLE, PLL_CON3_PLL_MIF_SUB_STABLE, PLL_CON3_PLL_MIF_SUB_DIV_P, PLL_CON3_PLL_MIF_SUB_DIV_M, PLL_CON3_PLL_MIF_SUB_DIV_S, EMPTY_CAL_ID, pll_mif_sub_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_NOCL0, OSCCLK_NOCL0, PLL_LOCKTIME_PLL_NOCL0_PLL_LOCK_TIME, PLL_CON3_PLL_NOCL0_ENABLE, PLL_CON3_PLL_NOCL0_STABLE, PLL_CON3_PLL_NOCL0_DIV_P, PLL_CON3_PLL_NOCL0_DIV_M, PLL_CON3_PLL_NOCL0_DIV_S, EMPTY_CAL_ID, pll_nocl0_rate_table, 0, 0), + CLK_PLL(PLL_0516X, PLL_MIF_S2D, OSCCLK_S2D, PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, PLL_CON3_PLL_MIF_S2D_ENABLE, PLL_CON3_PLL_MIF_S2D_STABLE, PLL_CON3_PLL_MIF_S2D_DIV_P, PLL_CON3_PLL_MIF_S2D_DIV_M, PLL_CON3_PLL_MIF_S2D_DIV_S, EMPTY_CAL_ID, pll_mif_s2d_rate_table, 0, 0), + CLK_PLL(PLL_0518X, PLL_TPU, OSCCLK_TPU, PLL_LOCKTIME_PLL_TPU_PLL_LOCK_TIME, PLL_CON3_PLL_TPU_ENABLE, PLL_CON3_PLL_TPU_STABLE, PLL_CON3_PLL_TPU_DIV_P, PLL_CON3_PLL_TPU_DIV_M, PLL_CON3_PLL_TPU_DIV_S, EMPTY_CAL_ID, pll_tpu_rate_table, 0, 0), +}; + +enum clk_id cmucal_mux_clkcmu_apm_func_parents[] = { + OSCCLK_APM, + MUX_CLKCMU_APM_FUNCSRC, + PAD_CLK_APM, + OSCCLK_APM, +}; +enum clk_id cmucal_mux_clkcmu_apm_funcsrc_parents[] = { + PLL_ALV_DIV2_APM, + PLL_ALV_DIV4_APM, + PLL_ALV_DIV16_APM, + PLL_ALV_DIV8_APM, +}; +enum clk_id cmucal_mux_clk_aur_aur_parents[] = { + PLL_AUR, + MUX_CLKCMU_AUR_SWITCH_USER, +}; +enum clk_id cmucal_mux_clkcmu_mfc_mfc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_usb31drd_parents[] = { + OSCCLK_CMU, + PLL_SHARED2_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_g2d_g2d_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_csis_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cpucl0_switch_parents[] = { + PLL_SHARED1, + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_nocl0_noc_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV5, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_mif_switch_parents[] = { + PLL_SHARED0, + PLL_SHARED1, + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED0_DIV3, + PLL_LF_MIF, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_itp_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_g3aa_g3aa_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_mcsc_itsc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_g2d_mscl_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_hpm_parents[] = { + OSCCLK_CMU, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_parents[] = { + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_hsi1_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk0_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk1_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk2_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk3_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_bo_noc_parents[] = { + PLL_SHARED2, + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_ufs_embd_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_cmu_cmuref_parents[] = { + MUX_CLKCMU_TOP_BOOST_OPTION1, + DIV_CLK_CMU_CMUREF, +}; +enum clk_id cmucal_mux_clkcmu_peric0_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_peric1_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_misc_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_pcie_parents[] = { + OSCCLK_CMU, + PLL_SHARED2_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_mif_nocp_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED0_DIV5, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_peric0_ip_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_peric1_ip_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_tpu_noc_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_usbdpdbg_parents[] = { + OSCCLK_CMU, + PLL_SHARED2_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_pdp_vra_parents[] = { + PLL_SHARED2, + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_dpu_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cpucl1_switch_parents[] = { + PLL_SHARED1, + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_hsi1_pcie_parents[] = { + OSCCLK_CMU, + PLL_SHARED2_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_top_cmuref_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_ipp_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk4_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cmu_boost_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, +}; +enum clk_id cmucal_mux_clkcmu_tnr_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_nocl2a_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_nocl1a_noc_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV5, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_nocl1b_noc_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk5_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk6_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_dns_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_gdc_gdc0_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_gdc_gdc1_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_tpu_tpu_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_mmc_card_parents[] = { + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_cis_clk7_parents[] = { + OSCCLK_CMU, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, + OSCCLK_CMU, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_g3d_glb_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_cpucl2_switch_parents[] = { + PLL_SHARED1, + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_gdc_scsc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_misc_sss_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_disp_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_eh_noc_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV5, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_cmu_boost_option1_parents[] = { + DIV_CLKCMU_CMU_BOOST, + CLK_CMU_BOOST_OPTION1, +}; +enum clk_id cmucal_mux_clkcmu_top_boost_option1_parents[] = { + OSCCLK_CMU, + CLK_CMU_BOOST_OPTION1, +}; +enum clk_id cmucal_mux_clkcmu_pdp_noc_parents[] = { + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, + OSCCLK_CMU, +}; +enum clk_id cmucal_mux_clkcmu_tpu_uart_parents[] = { + PLL_SHARED0_DIV4, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_tpu_tpuctl_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_g3d_switch_parents[] = { + PLL_SHARED2, + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SPARE, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_g3d_nocd_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_aur_aur_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_aur_noc_parents[] = { + PLL_SHARED0_DIV2, + PLL_SHARED1_DIV2, + PLL_SHARED2, + PLL_SHARED3, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV5, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clkcmu_aur_aurctl_parents[] = { + PLL_SHARED2, + PLL_SHARED0_DIV3, + PLL_SHARED3, + PLL_SHARED1_DIV3, + PLL_SHARED0_DIV4, + PLL_SHARED1_DIV4, + PLL_SHARED2_DIV2, + PLL_SPARE, +}; +enum clk_id cmucal_mux_clk_cpucl0_pll_parents[] = { + PLL_CPUCL0, + MUX_CLKCMU_CPUCL0_SWITCH_USER, + OSCCLK_CPUCL0, + OSCCLK_CPUCL0, +}; +enum clk_id cmucal_mux_cpucl0_cmuref_parents[] = { + OSCCLK_CPUCL0, + CLKCMU_CPUCL0_BOOST, +}; +enum clk_id cmucal_mux_cpucl1_cmuref_parents[] = { + OSCCLK_CPUCL1, + CLKCMU_CPUCL1_BOOST, +}; +enum clk_id cmucal_mux_clk_cpucl1_pll_parents[] = { + PLL_CPUCL1, + MUX_CLKCMU_CPUCL1_SWITCH_USER, + OSCCLK_CPUCL1, + OSCCLK_CPUCL1, +}; +enum clk_id cmucal_mux_clk_cpucl2_pll_parents[] = { + PLL_CPUCL2, + MUX_CLKCMU_CPUCL2_SWITCH_USER, + OSCCLK_CPUCL2, + OSCCLK_CPUCL2, +}; +enum clk_id cmucal_mux_cpucl2_cmuref_parents[] = { + OSCCLK_CPUCL2, + CLKCMU_CPUCL2_BOOST, +}; +enum clk_id cmucal_mux_clk_eh_noc_parents[] = { + MUX_CLKCMU_EH_NOC_USER, + MUX_CLKCMU_EH_PLL_NOCL0_USER, +}; +enum clk_id cmucal_mux_clk_g3d_stacks_parents[] = { + PLL_G3D, + MUX_CLKCMU_G3D_SWITCH_USER, +}; +enum clk_id cmucal_mux_clk_g3d_l2_glb_parents[] = { + PLL_G3D_L2, + MUX_CLKCMU_G3D_GLB_USER, +}; +enum clk_id cmucal_mux_clk_g3d_top_parents[] = { + MUX_CLK_G3D_STACKS, + MUX_CLKCMU_G3D_NOCD_USER, + MUX_CLK_G3D_L2_GLB, + OSCCLK_G3D, +}; +enum clk_id cmucal_mux_clk_gsacore_cpu_hch_parents[] = { + DIV_CLK_GSACORE_NOC, + OSCCLK_GSACORE, +}; +enum clk_id cmucal_mux_clkcmu_gsa_func_parents[] = { + OSCCLK_GSA, + MUX_CLKCMU_GSA_FUNCSRC, + PAD_CLK_GSA, + OSCCLK_GSA, +}; +enum clk_id cmucal_mux_clkcmu_gsa_funcsrc_parents[] = { + PLL_ALV_DIV2, + PLL_ALV, + PLL_ALV_DIV16, + PLL_ALV_DIV4, +}; +enum clk_id cmucal_mux_clk_hsi0_usb31drd_parents[] = { + DIV_CLK_HSI0_USB, + MUX_CLKCMU_HSI0_USB31DRD_USER, + DIV_CLK_HSI0_USB31DRD, + OSCCLK_HSI0, +}; +enum clk_id cmucal_mux_clk_hsi0_noc_parents[] = { + MUX_CLKCMU_HSI0_NOC_USER, + MUX_CLKCMU_HSI0_ALT_USER, +}; +enum clk_id cmucal_mux_clk_hsi0_usb20_ref_parents[] = { + DIV_CLK_HSI0_USB, + MUX_CLKCMU_HSI0_TCXO_USER, +}; +enum clk_id cmucal_mux_mif_cmuref_parents[] = { + OSCCLK_MIF, + CLKCMU_MIF_BOOST, +}; +enum clk_id cmucal_mux_nocl0_cmuref_parents[] = { + OSCCLK_NOCL0, + CLKCMU_NOCL0_BOOST, +}; +enum clk_id cmucal_mux_clk_nocl0_noc_parents[] = { + MUX_CLKCMU_NOCL0_NOC_USER, + PLL_NOCL0, +}; +enum clk_id cmucal_mux_clk_nocl0_noc_option1_parents[] = { + MUX_CLK_NOCL0_NOC, + CLK_NOCL0_BOOST_OPTION1, +}; +enum clk_id cmucal_mux_nocl1a_cmuref_parents[] = { + OSCCLK_NOCL1A, + CLKCMU_NOCL1A_BOOST, +}; +enum clk_id cmucal_mux_nocl1b_cmuref_parents[] = { + OSCCLK_NOCL1B, + CLKCMU_NOCL1B_BOOST, +}; +enum clk_id cmucal_mux_clk_nocl1b_noc_option1_parents[] = { + MUX_CLKCMU_NOCL1B_NOC_USER, + CLK_NOCL1B_BOOST_OPTION1, +}; +enum clk_id cmucal_mux_nocl2a_cmuref_parents[] = { + OSCCLK_NOCL2A, + CLKCMU_NOCL2A_BOOST, +}; +enum clk_id cmucal_mux_clk_s2d_core_parents[] = { + OSCCLK_S2D, + CLK_MIF_NOCD_S2D, +}; +enum clk_id cmucal_mux_clk_tpu_tpu_parents[] = { + PLL_TPU, + MUX_CLKCMU_TPU_TPU_USER, +}; +enum clk_id cmucal_mux_clk_tpu_tpuctl_parents[] = { + PLL_TPU, + MUX_CLKCMU_TPU_TPUCTL_USER, +}; +enum clk_id cmucal_mux_clkcmu_aur_switch_user_parents[] = { + OSCCLK_AUR, + CLKCMU_AUR_AUR, +}; +enum clk_id cmucal_mux_clkcmu_aur_aurctl_user_parents[] = { + OSCCLK_AUR, + CLKCMU_AUR_AURCTL, +}; +enum clk_id cmucal_mux_clkcmu_aur_noc_user_parents[] = { + OSCCLK_AUR, + CLKCMU_AUR_NOC, +}; +enum clk_id cmucal_mux_clkcmu_bo_noc_user_parents[] = { + OSCCLK_BO, + CLKCMU_BO_NOC, +}; +enum clk_id cmucal_mux_clkcmu_cpucl0_switch_user_parents[] = { + OSCCLK_CPUCL0, + CLKCMU_CPUCL0_SWITCH, +}; +enum clk_id cmucal_mux_clkcmu_cpucl0_dbg_noc_user_parents[] = { + OSCCLK_CPUCL0, + CLKCMU_CPUCL0_DBG, +}; +enum clk_id cmucal_mux_clkcmu_cpucl1_switch_user_parents[] = { + OSCCLK_CPUCL1, + CLKCMU_CPUCL1_SWITCH, +}; +enum clk_id cmucal_mux_clkcmu_cpucl2_switch_user_parents[] = { + OSCCLK_CPUCL2, + CLKCMU_CPUCL2_SWITCH, +}; +enum clk_id cmucal_mux_clkcmu_csis_noc_user_parents[] = { + OSCCLK_CSIS, + CLKCMU_CSIS_NOC, +}; +enum clk_id cmucal_mux_clkcmu_disp_noc_user_parents[] = { + OSCCLK_DISP, + CLKCMU_DISP_NOC, +}; +enum clk_id cmucal_mux_clkcmu_dns_noc_user_parents[] = { + OSCCLK_DNS, + CLKCMU_DNS_NOC, +}; +enum clk_id cmucal_mux_clkcmu_dpu_noc_user_parents[] = { + OSCCLK_DPU, + CLKCMU_DPU_NOC, +}; +enum clk_id cmucal_mux_clkcmu_eh_noc_user_parents[] = { + OSCCLK_EH, + CLKCMU_EH_NOC, +}; +enum clk_id cmucal_mux_clkcmu_eh_pll_nocl0_user_parents[] = { + OSCCLK_EH, + PLL_NOCL0, +}; +enum clk_id cmucal_mux_clkcmu_g2d_g2d_user_parents[] = { + OSCCLK_G2D, + CLKCMU_G2D_G2D, +}; +enum clk_id cmucal_mux_clkcmu_g2d_mscl_user_parents[] = { + OSCCLK_G2D, + CLKCMU_G2D_MSCL, +}; +enum clk_id cmucal_mux_clkcmu_g3aa_g3aa_user_parents[] = { + OSCCLK_G3AA, + CLKCMU_G3AA_G3AA, +}; +enum clk_id cmucal_mux_clkcmu_g3d_switch_user_parents[] = { + OSCCLK_G3D, + CLKCMU_G3D_SWITCH, +}; +enum clk_id cmucal_mux_clkcmu_embedded_g3d_stacks_user_parents[] = { + OSCCLK_G3D, + DIV_CLK_G3D_STACKS, +}; +enum clk_id cmucal_mux_clkcmu_g3d_glb_user_parents[] = { + OSCCLK_G3D, + CLKCMU_G3D_GLB, +}; +enum clk_id cmucal_mux_clkcmu_embedded_g3d_coregroup_user_parents[] = { + OSCCLK_G3D, + DIV_CLK_G3D_L2_GLB, +}; +enum clk_id cmucal_mux_clkcmu_g3d_nocd_user_parents[] = { + OSCCLK_G3D, + CLKCMU_G3D_NOCD, +}; +enum clk_id cmucal_mux_clkcmu_embedded_g3d_top_user_parents[] = { + OSCCLK_G3D, + DIV_CLK_G3D_TOP, +}; +enum clk_id cmucal_mux_clkcmu_gdc_scsc_user_parents[] = { + OSCCLK_GDC, + CLKCMU_GDC_SCSC, +}; +enum clk_id cmucal_mux_clkcmu_gdc_gdc0_user_parents[] = { + OSCCLK_GDC, + CLKCMU_GDC_GDC0, +}; +enum clk_id cmucal_mux_clkcmu_gdc_gdc1_user_parents[] = { + OSCCLK_GDC, + CLKCMU_GDC_GDC1, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_noc_user_parents[] = { + OSCCLK_HSI0, + CLKCMU_HSI0_NOC, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_usb31drd_user_parents[] = { + OSCCLK_HSI0, + CLKCMU_HSI0_USB31DRD, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_dpgtc_user_parents[] = { + OSCCLK_HSI0, + CLKCMU_HSI0_DPGTC, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_uspdpdbg_user_parents[] = { + OSCCLK_HSI0, + CLKCMU_HSI0_USBDPDBG, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_alt_user_parents[] = { + OSCCLK_HSI0, + CLK_HSI0_ALT, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_usb20_user_parents[] = { + OSCCLK_HSI0, + USB20PHY_PHY_CLOCK, +}; +enum clk_id cmucal_mux_clkcmu_hsi0_tcxo_user_parents[] = { + OSCCLK_HSI0, + TCXO_HSI1_HSI0, +}; +enum clk_id cmucal_mux_clkcmu_hsi1_noc_user_parents[] = { + OSCCLK_HSI1, + CLKCMU_HSI1_NOC, +}; +enum clk_id cmucal_mux_clkcmu_hsi1_pcie_user_parents[] = { + OSCCLK_HSI1, + CLKCMU_HSI1_PCIE, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_noc_user_parents[] = { + OSCCLK_HSI2, + CLKCMU_HSI2_NOC, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_pcie_user_parents[] = { + OSCCLK_HSI2, + CLKCMU_HSI2_PCIE, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_ufs_embd_user_parents[] = { + OSCCLK_HSI2, + CLKCMU_HSI2_UFS_EMBD, +}; +enum clk_id cmucal_mux_clkcmu_hsi2_mmc_card_user_parents[] = { + OSCCLK_HSI2, + CLKCMU_HSI2_MMC_CARD, +}; +enum clk_id cmucal_mux_clkcmu_ipp_noc_user_parents[] = { + OSCCLK_IPP, + CLKCMU_IPP_NOC, +}; +enum clk_id cmucal_mux_clkcmu_itp_noc_user_parents[] = { + OSCCLK_ITP, + CLKCMU_ITP_NOC, +}; +enum clk_id cmucal_mux_clkcmu_mcsc_itsc_user_parents[] = { + OSCCLK_MCSC, + CLKCMU_MCSC_ITSC, +}; +enum clk_id cmucal_mux_clkcmu_mcsc_mcsc_user_parents[] = { + OSCCLK_MCSC, + CLKCMU_MCSC_MCSC, +}; +enum clk_id cmucal_mux_clkcmu_mfc_mfc_user_parents[] = { + OSCCLK_MFC, + CLKCMU_MFC_MFC, +}; +enum clk_id cmucal_mux_clkcmu_mif_nocp_user_parents[] = { + OSCCLK_MIF, + CLKCMU_MIF_NOCP, +}; +enum clk_id cmucal_clkmux_mif_ddrphy2x_parents[] = { + OSCCLK_MIF, + CLKCMU_MIF_SWITCH, + PLL_MIF_MAIN, + PLL_MIF_SUB, +}; +enum clk_id cmucal_mux_clkcmu_misc_noc_user_parents[] = { + OSCCLK_MISC, + CLKCMU_MISC_NOC, +}; +enum clk_id cmucal_mux_clkcmu_misc_sss_user_parents[] = { + OSCCLK_MISC, + CLKCMU_MISC_SSS, +}; +enum clk_id cmucal_mux_clkcmu_nocl0_noc_user_parents[] = { + OSCCLK_NOCL0, + CLKCMU_NOCL0_NOC, +}; +enum clk_id cmucal_mux_clkcmu_nocl1a_noc_user_parents[] = { + OSCCLK_NOCL1A, + CLKCMU_NOCL1A_NOC, +}; +enum clk_id cmucal_mux_clkcmu_nocl1b_noc_user_parents[] = { + OSCCLK_NOCL1B, + CLKCMU_NOCL1B_NOC, +}; +enum clk_id cmucal_mux_clkcmu_nocl2a_noc_user_parents[] = { + OSCCLK_NOCL2A, + CLKCMU_NOCL2A_NOC, +}; +enum clk_id cmucal_mux_clkcmu_pdp_noc_user_parents[] = { + OSCCLK_PDP, + CLKCMU_PDP_NOC, +}; +enum clk_id cmucal_mux_clkcmu_pdp_vra_user_parents[] = { + OSCCLK_PDP, + CLKCMU_PDP_VRA, +}; +enum clk_id cmucal_mux_clkcmu_peric0_noc_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_NOC, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi6_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi3_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi4_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi5_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi14_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_i3c_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi7_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi8_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi1_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi0_uart_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric0_usi2_usi_user_parents[] = { + OSCCLK_PERIC0, + CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_noc_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_NOC, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi11_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi12_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi0_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_i3c_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi9_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi10_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi13_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi15_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_mux_clkcmu_peric1_usi16_usi_user_parents[] = { + OSCCLK_PERIC1, + CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_clkcmu_mif_ddrphy2x_s2d_parents[] = { + OSCCLK_S2D, + PLL_MIF_S2D, + PLL_MIF_S2D, + PLL_MIF_S2D, +}; +enum clk_id cmucal_mux_clkcmu_tnr_noc_user_parents[] = { + OSCCLK_TNR, + CLKCMU_TNR_NOC, +}; +enum clk_id cmucal_mux_clkcmu_tpu_noc_user_parents[] = { + OSCCLK_TPU, + CLKCMU_TPU_NOC, +}; +enum clk_id cmucal_mux_clkcmu_tpu_tpu_user_parents[] = { + OSCCLK_TPU, + CLKCMU_TPU_TPU, +}; +enum clk_id cmucal_mux_clkcmu_tpu_tpuctl_user_parents[] = { + OSCCLK_TPU, + CLKCMU_TPU_TPUCTL, +}; +enum clk_id cmucal_mux_clkcmu_tpu_uart_user_parents[] = { + OSCCLK_TPU, + CLKCMU_TPU_UART, +}; +unsigned int cmucal_mux_size = 219; +struct cmucal_mux cmucal_mux_list[] = { + CLK_MUX(MUX_CLKCMU_APM_FUNC, cmucal_mux_clkcmu_apm_func_parents, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_APM_FUNCSRC, cmucal_mux_clkcmu_apm_funcsrc_parents, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_SELECT, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_BUSY, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_AUR_AUR, cmucal_mux_clk_aur_aur_parents, CLK_CON_MUX_MUX_CLK_AUR_AUR_SELECT, CLK_CON_MUX_MUX_CLK_AUR_AUR_BUSY, CLK_CON_MUX_MUX_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MFC_MFC, cmucal_mux_clkcmu_mfc_mfc_parents, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_USB31DRD, cmucal_mux_clkcmu_hsi0_usb31drd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G2D_G2D, cmucal_mux_clkcmu_g2d_g2d_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CSIS_NOC, cmucal_mux_clkcmu_csis_noc_parents, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH, cmucal_mux_clkcmu_cpucl0_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL0_NOC, cmucal_mux_clkcmu_nocl0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MIF_SWITCH, cmucal_mux_clkcmu_mif_switch_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_ITP_NOC, cmucal_mux_clkcmu_itp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3AA_G3AA, cmucal_mux_clkcmu_g3aa_g3aa_parents, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MCSC_ITSC, cmucal_mux_clkcmu_mcsc_itsc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G2D_MSCL, cmucal_mux_clkcmu_g2d_mscl_parents, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HPM, cmucal_mux_clkcmu_hpm_parents, CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL0_DBG, cmucal_mux_clkcmu_cpucl0_dbg_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI1_NOC, cmucal_mux_clkcmu_hsi1_noc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK0, cmucal_mux_clkcmu_cis_clk0_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK1, cmucal_mux_clkcmu_cis_clk1_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK2, cmucal_mux_clkcmu_cis_clk2_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK3, cmucal_mux_clkcmu_cis_clk3_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_BO_NOC, cmucal_mux_clkcmu_bo_noc_parents, CLK_CON_MUX_MUX_CLKCMU_BO_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_BO_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_UFS_EMBD, cmucal_mux_clkcmu_hsi2_ufs_embd_parents, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CMU_CMUREF, cmucal_mux_cmu_cmuref_parents, CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_NOC, cmucal_mux_clkcmu_peric0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_NOC, cmucal_mux_clkcmu_peric1_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MISC_NOC, cmucal_mux_clkcmu_misc_noc_parents, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_DPGTC, cmucal_mux_clkcmu_hsi0_dpgtc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_PCIE, cmucal_mux_clkcmu_hsi2_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_NOC, cmucal_mux_clkcmu_hsi2_noc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MIF_NOCP, cmucal_mux_clkcmu_mif_nocp_parents, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_IP, cmucal_mux_clkcmu_peric0_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_IP, cmucal_mux_clkcmu_peric1_ip_parents, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_NOC, cmucal_mux_clkcmu_tpu_noc_parents, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_USBDPDBG, cmucal_mux_clkcmu_hsi0_usbdpdbg_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PDP_VRA, cmucal_mux_clkcmu_pdp_vra_parents, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_SELECT, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_BUSY, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DPU_NOC, cmucal_mux_clkcmu_dpu_noc_parents, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH, cmucal_mux_clkcmu_cpucl1_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI1_PCIE, cmucal_mux_clkcmu_hsi1_pcie_parents, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_NOC, cmucal_mux_clkcmu_hsi0_noc_parents, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TOP_CMUREF, cmucal_mux_clkcmu_top_cmuref_parents, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_SELECT, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_BUSY, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_IPP_NOC, cmucal_mux_clkcmu_ipp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK4, cmucal_mux_clkcmu_cis_clk4_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CMU_BOOST, cmucal_mux_clkcmu_cmu_boost_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TNR_NOC, cmucal_mux_clkcmu_tnr_noc_parents, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL2A_NOC, cmucal_mux_clkcmu_nocl2a_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL1A_NOC, cmucal_mux_clkcmu_nocl1a_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL1B_NOC, cmucal_mux_clkcmu_nocl1b_noc_parents, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK5, cmucal_mux_clkcmu_cis_clk5_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK6, cmucal_mux_clkcmu_cis_clk6_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DNS_NOC, cmucal_mux_clkcmu_dns_noc_parents, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_GDC0, cmucal_mux_clkcmu_gdc_gdc0_parents, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_SELECT, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_BUSY, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_GDC1, cmucal_mux_clkcmu_gdc_gdc1_parents, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_SELECT, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_BUSY, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MCSC_MCSC, cmucal_mux_clkcmu_mcsc_mcsc_parents, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_TPU, cmucal_mux_clkcmu_tpu_tpu_parents, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_SELECT, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_BUSY, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_MMC_CARD, cmucal_mux_clkcmu_hsi2_mmc_card_parents, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_SELECT, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_BUSY, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CIS_CLK7, cmucal_mux_clkcmu_cis_clk7_parents, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_GLB, cmucal_mux_clkcmu_g3d_glb_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH, cmucal_mux_clkcmu_cpucl2_switch_parents, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_SCSC, cmucal_mux_clkcmu_gdc_scsc_parents, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_SELECT, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_BUSY, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MISC_SSS, cmucal_mux_clkcmu_misc_sss_parents, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_SELECT, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_BUSY, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DISP_NOC, cmucal_mux_clkcmu_disp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EH_NOC, cmucal_mux_clkcmu_eh_noc_parents, CLK_CON_MUX_MUX_CLKCMU_EH_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_EH_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CMU_BOOST_OPTION1, cmucal_mux_clkcmu_cmu_boost_option1_parents, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_SELECT, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_BUSY, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TOP_BOOST_OPTION1, cmucal_mux_clkcmu_top_boost_option1_parents, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_SELECT, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_BUSY, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PDP_NOC, cmucal_mux_clkcmu_pdp_noc_parents, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_UART, cmucal_mux_clkcmu_tpu_uart_parents, CLK_CON_MUX_MUX_CLKCMU_TPU_UART_SELECT, CLK_CON_MUX_MUX_CLKCMU_TPU_UART_BUSY, CLK_CON_MUX_MUX_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_TPUCTL, cmucal_mux_clkcmu_tpu_tpuctl_parents, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_SELECT, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_BUSY, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_SWITCH, cmucal_mux_clkcmu_g3d_switch_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_NOCD, cmucal_mux_clkcmu_g3d_nocd_parents, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_SELECT, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_BUSY, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_AUR_AUR, cmucal_mux_clkcmu_aur_aur_parents, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_AUR_NOC, cmucal_mux_clkcmu_aur_noc_parents, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_AUR_AURCTL, cmucal_mux_clkcmu_aur_aurctl_parents, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_SELECT, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_BUSY, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_CPUCL0_PLL, cmucal_mux_clk_cpucl0_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CPUCL0_CMUREF, cmucal_mux_cpucl0_cmuref_parents, CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CPUCL1_CMUREF, cmucal_mux_cpucl1_cmuref_parents, CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_CPUCL1_PLL, cmucal_mux_clk_cpucl1_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_CPUCL2_PLL, cmucal_mux_clk_cpucl2_pll_parents, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_SELECT, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_BUSY, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CPUCL2_CMUREF, cmucal_mux_cpucl2_cmuref_parents, CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_EH_NOC, cmucal_mux_clk_eh_noc_parents, CLK_CON_MUX_MUX_CLK_EH_NOC_SELECT, CLK_CON_MUX_MUX_CLK_EH_NOC_BUSY, CLK_CON_MUX_MUX_CLK_EH_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_G3D_STACKS, cmucal_mux_clk_g3d_stacks_parents, CLK_CON_MUX_MUX_CLK_G3D_STACKS_SELECT, CLK_CON_MUX_MUX_CLK_G3D_STACKS_BUSY, CLK_CON_MUX_MUX_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_G3D_L2_GLB, cmucal_mux_clk_g3d_l2_glb_parents, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_SELECT, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_BUSY, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_G3D_TOP, cmucal_mux_clk_g3d_top_parents, CLK_CON_MUX_MUX_CLK_G3D_TOP_SELECT, CLK_CON_MUX_MUX_CLK_G3D_TOP_BUSY, CLK_CON_MUX_MUX_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_GSACORE_CPU_HCH, cmucal_mux_clk_gsacore_cpu_hch_parents, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_SELECT, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_BUSY, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GSA_FUNC, cmucal_mux_clkcmu_gsa_func_parents, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_SELECT, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_BUSY, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GSA_FUNCSRC, cmucal_mux_clkcmu_gsa_funcsrc_parents, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_SELECT, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_BUSY, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_HSI0_USB31DRD, cmucal_mux_clk_hsi0_usb31drd_parents, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_HSI0_NOC, cmucal_mux_clk_hsi0_noc_parents, CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_HSI0_USB20_REF, cmucal_mux_clk_hsi0_usb20_ref_parents, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_SELECT, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_BUSY, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_MIF_CMUREF, cmucal_mux_mif_cmuref_parents, CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_NOCL0_CMUREF, cmucal_mux_nocl0_cmuref_parents, CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_NOCL0_NOC, cmucal_mux_clk_nocl0_noc_parents, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_SELECT, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_BUSY, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_NOCL0_NOC_OPTION1, cmucal_mux_clk_nocl0_noc_option1_parents, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_SELECT, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_BUSY, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_NOCL1A_CMUREF, cmucal_mux_nocl1a_cmuref_parents, CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_NOCL1B_CMUREF, cmucal_mux_nocl1b_cmuref_parents, CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_NOCL1B_NOC_OPTION1, cmucal_mux_clk_nocl1b_noc_option1_parents, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_SELECT, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_BUSY, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_NOCL2A_CMUREF, cmucal_mux_nocl2a_cmuref_parents, CLK_CON_MUX_MUX_NOCL2A_CMUREF_SELECT, CLK_CON_MUX_MUX_NOCL2A_CMUREF_BUSY, CLK_CON_MUX_MUX_NOCL2A_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_S2D_CORE, cmucal_mux_clk_s2d_core_parents, CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_TPU_TPU, cmucal_mux_clk_tpu_tpu_parents, CLK_CON_MUX_MUX_CLK_TPU_TPU_SELECT, CLK_CON_MUX_MUX_CLK_TPU_TPU_BUSY, CLK_CON_MUX_MUX_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLK_TPU_TPUCTL, cmucal_mux_clk_tpu_tpuctl_parents, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_SELECT, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_BUSY, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(AOC_CMU_AOC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(APM_CMU_APM_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(AUR_CMU_AUR_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(BO_CMU_BO_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CMU_CMU_TOP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CPUCL0_CMU_CPUCL0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CPUCL1_CMU_CPUCL1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CPUCL2_CMU_CPUCL2_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(CSIS_CMU_CSIS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(DISP_CMU_DISP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(DNS_CMU_DNS_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(DPU_CMU_DPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(EH_CMU_EH_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(G2D_CMU_G2D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(G3AA_CMU_G3AA_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(G3D_CMU_G3D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(G3D_EMBEDDED_CMU_G3D_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(GDC_CMU_GDC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(HSI0_CMU_HSI0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(HSI1_CMU_HSI1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(HSI2_CMU_HSI2_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(IPP_CMU_IPP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(ITP_CMU_ITP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(MCSC_CMU_MCSC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(MFC_CMU_MFC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(MIF_CMU_MIF_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(MISC_CMU_MISC_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(NOCL0_CMU_NOCL0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(NOCL1A_CMU_NOCL1A_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(NOCL1B_CMU_NOCL1B_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(NOCL2A_CMU_NOCL2A_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(PDP_CMU_PDP_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(PERIC0_CMU_PERIC0_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(PERIC1_CMU_PERIC1_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(TNR_CMU_TNR_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(TPU_CMU_TPU_CLKOUT0, NULL, EMPTY_CAL_ID, EMPTY_CAL_ID, EMPTY_CAL_ID), + CLK_MUX(MUX_CLKCMU_AUR_SWITCH_USER, cmucal_mux_clkcmu_aur_switch_user_parents, PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_AUR_AURCTL_USER, cmucal_mux_clkcmu_aur_aurctl_user_parents, PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_AUR_NOC_USER, cmucal_mux_clkcmu_aur_noc_user_parents, PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_BO_NOC_USER, cmucal_mux_clkcmu_bo_noc_user_parents, PLL_CON0_MUX_CLKCMU_BO_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_BO_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_BO_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL0_SWITCH_USER, cmucal_mux_clkcmu_cpucl0_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL0_DBG_NOC_USER, cmucal_mux_clkcmu_cpucl0_dbg_noc_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL1_SWITCH_USER, cmucal_mux_clkcmu_cpucl1_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CPUCL2_SWITCH_USER, cmucal_mux_clkcmu_cpucl2_switch_user_parents, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_CSIS_NOC_USER, cmucal_mux_clkcmu_csis_noc_user_parents, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DISP_NOC_USER, cmucal_mux_clkcmu_disp_noc_user_parents, PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DNS_NOC_USER, cmucal_mux_clkcmu_dns_noc_user_parents, PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_DPU_NOC_USER, cmucal_mux_clkcmu_dpu_noc_user_parents, PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EH_NOC_USER, cmucal_mux_clkcmu_eh_noc_user_parents, PLL_CON0_MUX_CLKCMU_EH_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EH_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_EH_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EH_PLL_NOCL0_USER, cmucal_mux_clkcmu_eh_pll_nocl0_user_parents, PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_BUSY, PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G2D_G2D_USER, cmucal_mux_clkcmu_g2d_g2d_user_parents, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G2D_MSCL_USER, cmucal_mux_clkcmu_g2d_mscl_user_parents, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3AA_G3AA_USER, cmucal_mux_clkcmu_g3aa_g3aa_user_parents, PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_SWITCH_USER, cmucal_mux_clkcmu_g3d_switch_user_parents, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, cmucal_mux_clkcmu_embedded_g3d_stacks_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_BUSY, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_GLB_USER, cmucal_mux_clkcmu_g3d_glb_user_parents, PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, cmucal_mux_clkcmu_embedded_g3d_coregroup_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_BUSY, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_G3D_NOCD_USER, cmucal_mux_clkcmu_g3d_nocd_user_parents, PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_BUSY, PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, cmucal_mux_clkcmu_embedded_g3d_top_user_parents, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_BUSY, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_SCSC_USER, cmucal_mux_clkcmu_gdc_scsc_user_parents, PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_GDC0_USER, cmucal_mux_clkcmu_gdc_gdc0_user_parents, PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_BUSY, PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_GDC_GDC1_USER, cmucal_mux_clkcmu_gdc_gdc1_user_parents, PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_BUSY, PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_NOC_USER, cmucal_mux_clkcmu_hsi0_noc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_USB31DRD_USER, cmucal_mux_clkcmu_hsi0_usb31drd_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_DPGTC_USER, cmucal_mux_clkcmu_hsi0_dpgtc_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_USPDPDBG_USER, cmucal_mux_clkcmu_hsi0_uspdpdbg_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_ALT_USER, cmucal_mux_clkcmu_hsi0_alt_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_USB20_USER, cmucal_mux_clkcmu_hsi0_usb20_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI0_TCXO_USER, cmucal_mux_clkcmu_hsi0_tcxo_user_parents, PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI1_NOC_USER, cmucal_mux_clkcmu_hsi1_noc_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI1_PCIE_USER, cmucal_mux_clkcmu_hsi1_pcie_user_parents, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_NOC_USER, cmucal_mux_clkcmu_hsi2_noc_user_parents, PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_PCIE_USER, cmucal_mux_clkcmu_hsi2_pcie_user_parents, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_UFS_EMBD_USER, cmucal_mux_clkcmu_hsi2_ufs_embd_user_parents, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_HSI2_MMC_CARD_USER, cmucal_mux_clkcmu_hsi2_mmc_card_user_parents, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_BUSY, PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_IPP_NOC_USER, cmucal_mux_clkcmu_ipp_noc_user_parents, PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_ITP_NOC_USER, cmucal_mux_clkcmu_itp_noc_user_parents, PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MCSC_ITSC_USER, cmucal_mux_clkcmu_mcsc_itsc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MCSC_MCSC_USER, cmucal_mux_clkcmu_mcsc_mcsc_user_parents, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MFC_MFC_USER, cmucal_mux_clkcmu_mfc_mfc_user_parents, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MIF_NOCP_USER, cmucal_mux_clkcmu_mif_nocp_user_parents, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(CLKMUX_MIF_DDRPHY2X, cmucal_clkmux_mif_ddrphy2x_parents, PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MISC_NOC_USER, cmucal_mux_clkcmu_misc_noc_user_parents, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_MISC_SSS_USER, cmucal_mux_clkcmu_misc_sss_user_parents, PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_BUSY, PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL0_NOC_USER, cmucal_mux_clkcmu_nocl0_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL1A_NOC_USER, cmucal_mux_clkcmu_nocl1a_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL1B_NOC_USER, cmucal_mux_clkcmu_nocl1b_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_NOCL2A_NOC_USER, cmucal_mux_clkcmu_nocl2a_noc_user_parents, PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PDP_NOC_USER, cmucal_mux_clkcmu_pdp_noc_user_parents, PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PDP_VRA_USER, cmucal_mux_clkcmu_pdp_vra_user_parents, PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_BUSY, PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_NOC_USER, cmucal_mux_clkcmu_peric0_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI6_USI_USER, cmucal_mux_clkcmu_peric0_usi6_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI3_USI_USER, cmucal_mux_clkcmu_peric0_usi3_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI4_USI_USER, cmucal_mux_clkcmu_peric0_usi4_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI5_USI_USER, cmucal_mux_clkcmu_peric0_usi5_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI14_USI_USER, cmucal_mux_clkcmu_peric0_usi14_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_I3C_USER, cmucal_mux_clkcmu_peric0_i3c_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI7_USI_USER, cmucal_mux_clkcmu_peric0_usi7_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI8_USI_USER, cmucal_mux_clkcmu_peric0_usi8_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI1_USI_USER, cmucal_mux_clkcmu_peric0_usi1_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI0_UART_USER, cmucal_mux_clkcmu_peric0_usi0_uart_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC0_USI2_USI_USER, cmucal_mux_clkcmu_peric0_usi2_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_NOC_USER, cmucal_mux_clkcmu_peric1_noc_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI11_USI_USER, cmucal_mux_clkcmu_peric1_usi11_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI12_USI_USER, cmucal_mux_clkcmu_peric1_usi12_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI0_USI_USER, cmucal_mux_clkcmu_peric1_usi0_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_I3C_USER, cmucal_mux_clkcmu_peric1_i3c_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI9_USI_USER, cmucal_mux_clkcmu_peric1_usi9_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI10_USI_USER, cmucal_mux_clkcmu_peric1_usi10_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI13_USI_USER, cmucal_mux_clkcmu_peric1_usi13_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI15_USI_USER, cmucal_mux_clkcmu_peric1_usi15_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_PERIC1_USI16_USI_USER, cmucal_mux_clkcmu_peric1_usi16_usi_user_parents, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_BUSY, PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(CLKCMU_MIF_DDRPHY2X_S2D, cmucal_clkcmu_mif_ddrphy2x_s2d_parents, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TNR_NOC_USER, cmucal_mux_clkcmu_tnr_noc_user_parents, PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_NOC_USER, cmucal_mux_clkcmu_tpu_noc_user_parents, PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_BUSY, PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_TPU_USER, cmucal_mux_clkcmu_tpu_tpu_user_parents, PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_BUSY, PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_TPUCTL_USER, cmucal_mux_clkcmu_tpu_tpuctl_user_parents, PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_BUSY, PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_ENABLE_AUTOMATIC_CLKGATING), + CLK_MUX(MUX_CLKCMU_TPU_UART_USER, cmucal_mux_clkcmu_tpu_uart_user_parents, PLL_CON0_MUX_CLKCMU_TPU_UART_USER_MUX_SEL, PLL_CON0_MUX_CLKCMU_TPU_UART_USER_BUSY, PLL_CON1_MUX_CLKCMU_TPU_UART_USER_ENABLE_AUTOMATIC_CLKGATING), +}; + +unsigned int cmucal_div_size = 193; +struct cmucal_div cmucal_div_list[] = { + CLK_DIV(DIV_CLK_AOC_NOC_LH, I_CLK_AOC_NOC, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_AOC_TRACE_LH, I_CLK_AOC_TRACE, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_BUSY, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_BOOST, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_BOOST_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_BOOST_BUSY, CLK_CON_DIV_DIV_CLK_APM_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_USI0_USI, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_USI0_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_USI0_USI_BUSY, CLK_CON_DIV_DIV_CLK_APM_USI0_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_USI0_UART, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_USI0_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_USI0_UART_BUSY, CLK_CON_DIV_DIV_CLK_APM_USI0_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_USI1_UART, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_USI1_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_USI1_UART_BUSY, CLK_CON_DIV_DIV_CLK_APM_USI1_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_I3C_PMIC, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_BUSY, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_APM_NOC_LH, GATE_CLKCMU_APM_FUNC, CLK_CON_DIV_DIV_CLK_APM_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_APM_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_APM_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_AUR_NOCP, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_DIV_DIV_CLK_AUR_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUR_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_AUR_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLK_AUR_ADD_CH_CLK, OSCCLK_AUR, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_AUR_AURCTL_LH, MUX_CLKCMU_AUR_AURCTL_USER, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_BUSY, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_AUR_NOCP_LH, DIV_CLK_AUR_NOCP, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_BO_NOCP, MUX_CLKCMU_BO_NOC_USER, CLK_CON_DIV_DIV_CLK_BO_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_BO_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_BO_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PERIC0_NOC, GATE_CLKCMU_PERIC0_NOC, CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MISC_NOC, GATE_CLKCMU_MISC_NOC, CLK_CON_DIV_CLKCMU_MISC_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_MISC_NOC_BUSY, CLK_CON_DIV_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI1_NOC, GATE_CLKCMU_HSI1_NOC, CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY, CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_DPU_NOC, GATE_CLKCMU_DPU_NOC, CLK_CON_DIV_CLKCMU_DPU_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_DPU_NOC_BUSY, CLK_CON_DIV_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MFC_MFC, GATE_CLKCMU_MFC_MFC, CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G2D_G2D, GATE_CLKCMU_G2D_G2D, CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI0_USB31DRD, GATE_CLKCMU_HSI0_USB31DRD, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CSIS_NOC, GATE_CLKCMU_CSIS_NOC, CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY, CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PERIC1_NOC, GATE_CLKCMU_PERIC1_NOC, CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CPUCL0_SWITCH, GATE_CLKCMU_CPUCL0_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_NOCL0_NOC, GATE_CLKCMU_NOCL0_NOC, CLK_CON_DIV_CLKCMU_NOCL0_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_NOCL0_NOC_BUSY, CLK_CON_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_ITP_NOC, GATE_CLKCMU_ITP_NOC, CLK_CON_DIV_CLKCMU_ITP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_ITP_NOC_BUSY, CLK_CON_DIV_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G3AA_G3AA, GATE_CLKCMU_G3AA_G3AA, CLK_CON_DIV_CLKCMU_G3AA_G3AA_DIVRATIO, CLK_CON_DIV_CLKCMU_G3AA_G3AA_BUSY, CLK_CON_DIV_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MCSC_ITSC, GATE_CLKCMU_MCSC_ITSC, CLK_CON_DIV_CLKCMU_MCSC_ITSC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_ITSC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G2D_MSCL, GATE_CLKCMU_G2D_MSCL, CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HPM, GATE_CLKCMU_HPM, CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, CLK_CON_DIV_CLKCMU_HPM_BUSY, CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI2_PCIE, GATE_CLKCMU_HSI2_PCIE, CLK_CON_DIV_CLKCMU_HSI2_PCIE_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI2_PCIE_BUSY, CLK_CON_DIV_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CPUCL0_DBG, GATE_CLKCMU_CPUCL0_DBG_NOC, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK0, GATE_CLKCMU_CIS_CLK0, CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK1, GATE_CLKCMU_CIS_CLK1, CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK2, GATE_CLKCMU_CIS_CLK2, CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK3, GATE_CLKCMU_CIS_CLK3, CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_BO_NOC, GATE_CLKCMU_BO_NOC, CLK_CON_DIV_CLKCMU_BO_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_BO_NOC_BUSY, CLK_CON_DIV_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI2_UFS_EMBD, GATE_CLKCMU_HSI2_UFS_EMBD, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_BUSY, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI0_DPGTC, GATE_CLKCMU_HSI0_DPGTC, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CMU_CMUREF, GATE_CLKCMU_TOP_CMUREF, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MIF_NOCP, GATE_CLKCMU_MIF_NOCP, CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO, CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY, CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PERIC0_IP, GATE_CLKCMU_PERIC0_IP, CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY, CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PERIC1_IP, GATE_CLKCMU_PERIC1_IP, CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO, CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY, CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_TPU_NOC, GATE_CLKCMU_TPU_NOC, CLK_CON_DIV_CLKCMU_TPU_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_TPU_NOC_BUSY, CLK_CON_DIV_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PDP_VRA, GATE_CLKCMU_PDP_VRA, CLK_CON_DIV_CLKCMU_PDP_VRA_DIVRATIO, CLK_CON_DIV_CLKCMU_PDP_VRA_BUSY, CLK_CON_DIV_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CPUCL1_SWITCH, GATE_CLKCMU_CPUCL1_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI1_PCIE, GATE_CLKCMU_HSI1_PCIE, CLK_CON_DIV_CLKCMU_HSI1_PCIE_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI1_PCIE_BUSY, CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI0_NOC, GATE_CLKCMU_HSI0_NOC, CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY, CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_IPP_NOC, GATE_CLKCMU_IPP_NOC, CLK_CON_DIV_CLKCMU_IPP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_IPP_NOC_BUSY, CLK_CON_DIV_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK4, GATE_CLKCMU_CIS_CLK4, CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLKCMU_CMU_BOOST, GATE_CLKCMU_CMU_BOOST, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_DIVRATIO, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_BUSY, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_TNR_NOC, GATE_CLKCMU_TNR_NOC, CLK_CON_DIV_CLKCMU_TNR_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_TNR_NOC_BUSY, CLK_CON_DIV_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_NOCL2A_NOC, GATE_CLKCMU_NOCL2A_NOC, CLK_CON_DIV_CLKCMU_NOCL2A_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_NOCL2A_NOC_BUSY, CLK_CON_DIV_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_NOCL1A_NOC, GATE_CLKCMU_NOCL1A_NOC, CLK_CON_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_NOCL1A_NOC_BUSY, CLK_CON_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_NOCL1B_NOC, GATE_CLKCMU_NOCL1B_NOC, CLK_CON_DIV_CLKCMU_NOCL1B_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_NOCL1B_NOC_BUSY, CLK_CON_DIV_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK5, GATE_CLKCMU_CIS_CLK5, CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK6, GATE_CLKCMU_CIS_CLK6, CLK_CON_DIV_CLKCMU_CIS_CLK6_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK6_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CIS_CLK7, GATE_CLKCMU_CIS_CLK7, CLK_CON_DIV_CLKCMU_CIS_CLK7_DIVRATIO, CLK_CON_DIV_CLKCMU_CIS_CLK7_BUSY, CLK_CON_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_DNS_NOC, GATE_CLKCMU_DNS_NOC, CLK_CON_DIV_CLKCMU_DNS_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_DNS_NOC_BUSY, CLK_CON_DIV_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_GDC_GDC0, GATE_CLKCMU_GDC_GDC0, CLK_CON_DIV_CLKCMU_GDC_GDC0_DIVRATIO, CLK_CON_DIV_CLKCMU_GDC_GDC0_BUSY, CLK_CON_DIV_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_GDC_GDC1, GATE_CLKCMU_GDC_GDC1, CLK_CON_DIV_CLKCMU_GDC_GDC1_DIVRATIO, CLK_CON_DIV_CLKCMU_GDC_GDC1_BUSY, CLK_CON_DIV_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MCSC_MCSC, GATE_CLKCMU_MCSC_MCSC, CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_TPU_TPU, GATE_CLKCMU_TPU_TPU, CLK_CON_DIV_CLKCMU_TPU_TPU_DIVRATIO, CLK_CON_DIV_CLKCMU_TPU_TPU_BUSY, CLK_CON_DIV_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI2_NOC, GATE_CLKCMU_HSI2_NOC, CLK_CON_DIV_CLKCMU_HSI2_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI2_NOC_BUSY, CLK_CON_DIV_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_HSI2_MMC_CARD, GATE_CLKCMU_HSI2_MMCCARD, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_DIVRATIO, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_BUSY, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G3D_GLB, GATE_CLKCMU_G3D_GLB, CLK_CON_DIV_CLKCMU_G3D_GLB_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_GLB_BUSY, CLK_CON_DIV_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_CPUCL2_SWITCH, GATE_CLKCMU_CPUCL2_SWITCH, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_GDC_SCSC, GATE_CLKCMU_GDC_SCSC, CLK_CON_DIV_CLKCMU_GDC_SCSC_DIVRATIO, CLK_CON_DIV_CLKCMU_GDC_SCSC_BUSY, CLK_CON_DIV_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_MISC_SSS, GATE_CLKCMU_MISC_SSS, CLK_CON_DIV_CLKCMU_MISC_SSS_DIVRATIO, CLK_CON_DIV_CLKCMU_MISC_SSS_BUSY, CLK_CON_DIV_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_DISP_NOC, GATE_CLKCMU_DISP_NOC, CLK_CON_DIV_CLKCMU_DISP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_DISP_NOC_BUSY, CLK_CON_DIV_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_EH_NOC, GATE_CLKCMU_EH_NOC, CLK_CON_DIV_CLKCMU_EH_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_EH_NOC_BUSY, CLK_CON_DIV_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_PDP_NOC, GATE_CLKCMU_PDP_NOC, CLK_CON_DIV_CLKCMU_PDP_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_PDP_NOC_BUSY, CLK_CON_DIV_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_TPU_UART, GATE_CLKCMU_TPU_UART, CLK_CON_DIV_CLKCMU_TPU_UART_DIVRATIO, CLK_CON_DIV_CLKCMU_TPU_UART_BUSY, CLK_CON_DIV_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_TPU_TPUCTL, GATE_CLKCMU_TPU_TPUCTL, CLK_CON_DIV_CLKCMU_TPU_TPUCTL_DIVRATIO, CLK_CON_DIV_CLKCMU_TPU_TPUCTL_BUSY, CLK_CON_DIV_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED0_DIV5, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV5_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV5_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV5_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_G3D_NOCD, GATE_CLKCMU_G3D_NOCD, CLK_CON_DIV_CLKCMU_G3D_NOCD_DIVRATIO, CLK_CON_DIV_CLKCMU_G3D_NOCD_BUSY, CLK_CON_DIV_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_AUR_AUR, GATE_CLKCMU_AUR_AUR, CLK_CON_DIV_CLKCMU_AUR_AUR_DIVRATIO, CLK_CON_DIV_CLKCMU_AUR_AUR_BUSY, CLK_CON_DIV_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_AUR_NOC, GATE_CLKCMU_AUR_NOC, CLK_CON_DIV_CLKCMU_AUR_NOC_DIVRATIO, CLK_CON_DIV_CLKCMU_AUR_NOC_BUSY, CLK_CON_DIV_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLKCMU_AUR_AURCTL, GATE_CLKCMU_AUR_AURCTL, CLK_CON_DIV_CLKCMU_AUR_AURCTL_DIVRATIO, CLK_CON_DIV_CLKCMU_AUR_AURCTL_BUSY, CLK_CON_DIV_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED0_DIV2, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED0_DIV4, PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED0_DIV3, PLL_SHARED0, CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED1_DIV2, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED1_DIV4, PLL_SHARED1_DIV2, CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED1_DIV3, PLL_SHARED1, CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED2_DIV2, PLL_SHARED2, CLK_CON_DIV_PLL_SHARED2_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED2_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(PLL_SHARED3_DIV2, PLL_SHARED3, CLK_CON_DIV_PLL_SHARED3_DIV2_DIVRATIO, CLK_CON_DIV_PLL_SHARED3_DIV2_BUSY, CLK_CON_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_CMUREF, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CLUSTER0_ACLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CLUSTER0_ATCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CLUSTER0_PCLKDBG, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CLUSTER0_PERIPHCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_DBG_PCLKDBG, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_PCLK, DIV_CLK_CPUCL0_CPU, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_DBG_NOC, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_DBG_ATCLK_LH, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_DBG_NOC_LH, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CLUSTER0_ATCLK_LH, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_BUSY, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_PCLK_LH, DIV_CLK_CPUCL0_PCLK, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL1_CMUREF, DIV_CLK_CPUCL1_CPU, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL2_CMUREF, DIV_CLK_CPUCL2_CPU, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_DIVRATIO, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CSIS_NOCP, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_DISP_NOCP, MUX_CLKCMU_DISP_NOC_USER, CLK_CON_DIV_DIV_CLK_DISP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DISP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DISP_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_DNS_NOCP, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_DIV_DIV_CLK_DNS_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DNS_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DNS_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_DPU_NOCP, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_DIV_DIV_CLK_DPU_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_DPU_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_DPU_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_EH_NOCP, MUX_CLK_EH_NOC, CLK_CON_DIV_DIV_CLK_EH_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_EH_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_EH_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_EH_NOCP_LH, DIV_CLK_EH_NOCP, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G2D_NOCP, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_DIV_DIV_CLK_G2D_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G2D_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_G2D_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3AA_NOCP, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_DIV_DIV_CLK_G3AA_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3AA_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_G3AA_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3D_NOCP, DIV_CLK_G3D_L2_GLB, CLK_CON_DIV_DIV_CLK_G3D_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(CLK_G3D_ADD_CH_CLK, OSCCLK_G3D, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3D_TOP, MUX_CLK_G3D_TOP, CLK_CON_DIV_DIV_CLK_G3D_TOP_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_TOP_BUSY, CLK_CON_DIV_DIV_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3D_NOCP_LH, DIV_CLK_G3D_NOCP, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GDC_NOCP, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_DIV_DIV_CLK_GDC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_GDC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_GDC_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_NOCP, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_NOCD, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_SPI_FPS, CLK_GSACORE, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_SPI_GSC, CLK_GSACORE, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_UART, CLK_GSACORE, CLK_CON_DIV_DIV_CLK_GSACORE_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_UART_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_NOC, CLK_GSACORE, CLK_CON_DIV_DIV_CLK_GSACORE_NOC_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_NOC_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACORE_CPU_LH, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_BUSY, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACTRL_NOCP, DIV_CLK_GSACTRL_NOCD, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACTRL_NOCD, GATE_CLK_GSA_FUNC, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_BUSY, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_GSACTRL_NOCP_LH, DIV_CLK_GSACTRL_NOCP, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI0_USB31DRD, MUX_CLKCMU_HSI0_USB20_USER, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_BUSY, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI0_USB, PLL_USB, CLK_CON_DIV_DIV_CLK_HSI0_USB_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI0_USB_BUSY, CLK_CON_DIV_DIV_CLK_HSI0_USB_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI0_NOC_LH, MUX_CLK_HSI0_NOC, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI1_NOCP, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_DIV_DIV_CLK_HSI1_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI1_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_HSI1_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI1_NOC_LH, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI2_NOCP, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_DIV_DIV_CLK_HSI2_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI2_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_HSI2_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_HSI2_NOC_LH, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_BUSY, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_IPP_NOCP, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_DIV_DIV_CLK_IPP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_IPP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_IPP_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_ITP_NOCP, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_DIV_DIV_CLK_ITP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_ITP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_ITP_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MCSC_NOCP, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MFC_NOCP, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_DIV_DIV_CLK_MFC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MFC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MFC_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MIF_NOCP_LH, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MIF_NOCD_DBG_LH, CLK_MIF_NOCD_DBG, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_BUSY, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MISC_NOCP, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_DIV_DIV_CLK_MISC_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_MISC_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_MISC_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MISC_GIC, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_DIV_DIV_CLK_MISC_GIC_DIVRATIO, CLK_CON_DIV_DIV_CLK_MISC_GIC_BUSY, CLK_CON_DIV_DIV_CLK_MISC_GIC_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MISC_GIC_LH, DIV_CLK_MISC_GIC, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_BUSY, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_MISC_NOCP_LH, DIV_CLK_MISC_NOCP, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL0_NOCP, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_SLC_DCLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_SLC_DCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_SLC_DCLK_BUSY, CLK_CON_DIV_DIV_CLK_SLC_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_SLC1_DCLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_SLC1_DCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_SLC1_DCLK_BUSY, CLK_CON_DIV_DIV_CLK_SLC1_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_SLC2_DCLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_SLC2_DCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_SLC2_DCLK_BUSY, CLK_CON_DIV_DIV_CLK_SLC2_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_SLC3_DCLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_SLC3_DCLK_DIVRATIO, CLK_CON_DIV_DIV_CLK_SLC3_DCLK_BUSY, CLK_CON_DIV_DIV_CLK_SLC3_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL0_NOCD_LH, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL0_NOCP_LH, DIV_CLK_NOCL0_NOCP, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1A_NOCP, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1A_NOCD_LH, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1A_NOCP_LH, DIV_CLK_NOCL1A_NOCP, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1B_NOCP, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1B_NOCD_LH, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL1B_NOCP_LH, DIV_CLK_NOCL1B_NOCP, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL2A_NOCP, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL2A_NOCD_LH, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_NOCL2A_NOCP_LH, DIV_CLK_NOCL2A_NOCP, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PDP_NOCP, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_DIV_DIV_CLK_PDP_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_PDP_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_PDP_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI6_USI, MUX_CLKCMU_PERIC0_USI6_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI3_USI, MUX_CLKCMU_PERIC0_USI3_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI4_USI, MUX_CLKCMU_PERIC0_USI4_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI5_USI, MUX_CLKCMU_PERIC0_USI5_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI14_USI, MUX_CLKCMU_PERIC0_USI14_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_I3C, MUX_CLKCMU_PERIC0_I3C_USER, CLK_CON_DIV_DIV_CLK_PERIC0_I3C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_I3C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_I3C_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI7_USI, MUX_CLKCMU_PERIC0_USI7_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI8_USI, MUX_CLKCMU_PERIC0_USI8_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI1_USI, MUX_CLKCMU_PERIC0_USI1_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI0_UART, MUX_CLKCMU_PERIC0_USI0_UART_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_USI2_USI, MUX_CLKCMU_PERIC0_USI2_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC0_NOCP_LH, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI11_USI, MUX_CLKCMU_PERIC1_USI11_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_I3C, MUX_CLKCMU_PERIC1_I3C_USER, CLK_CON_DIV_DIV_CLK_PERIC1_I3C_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_I3C_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_I3C_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI12_USI, MUX_CLKCMU_PERIC1_USI12_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI0_USI, MUX_CLKCMU_PERIC1_USI0_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI9_USI, MUX_CLKCMU_PERIC1_USI9_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI10_USI, MUX_CLKCMU_PERIC1_USI10_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI13_USI, MUX_CLKCMU_PERIC1_USI13_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_NOCP_LH, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI15_USI, MUX_CLKCMU_PERIC1_USI15_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_PERIC1_USI16_USI, MUX_CLKCMU_PERIC1_USI16_USI_USER, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_S2D_CORE_LH, MUX_CLK_S2D_CORE, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_BUSY, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TNR_NOCP, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_DIV_DIV_CLK_TNR_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TNR_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_TNR_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TPU_NOCP, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_DIV_DIV_CLK_TPU_NOCP_DIVRATIO, CLK_CON_DIV_DIV_CLK_TPU_NOCP_BUSY, CLK_CON_DIV_DIV_CLK_TPU_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TPU_TPUCTL_DBG, DIV_CLK_TPU_TPUCTL, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_DIVRATIO, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_BUSY, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TPU_NOCP_LH, DIV_CLK_TPU_NOCP, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_DIVRATIO, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_BUSY, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_AUR_AUR, MUX_CLK_AUR_AUR, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_AUR_AUR_BUSY, CLK_CON_DIV_DIV_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL0_CPU, MUX_CLK_CPUCL0_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL1_CPU, MUX_CLK_CPUCL1_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_CPUCL2_CPU, MUX_CLK_CPUCL2_PLL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_BUSY, CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3D_STACKS, MUX_CLK_G3D_STACKS, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_STACKS_BUSY, CLK_CON_DIV_DIV_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_G3D_L2_GLB, MUX_CLK_G3D_L2_GLB, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_BUSY, CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TPU_TPU, MUX_CLK_TPU_TPU, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_TPU_TPU_BUSY, CLK_CON_DIV_DIV_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_DIV(DIV_CLK_TPU_TPUCTL, MUX_CLK_TPU_TPUCTL, EMPTY_CAL_ID, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_BUSY, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING), +}; + +unsigned int cmucal_gate_size = 1886; +struct cmucal_gate cmucal_gate_list[] = { + CLK_GATE(CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK, I_CLK_AOC_TRACE, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK, I_CLK_AOC_NOC, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK, DIV_CLK_AOC_TRACE_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK, DIV_CLK_AOC_TRACE_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK, DIV_CLK_AOC_NOC_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK, DIV_CLK_AOC_TRACE_LH, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK, I_CLK_AOC_NOC, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK, I_CLK_AOC_TRACE, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_APM_FUNC, MUX_CLKCMU_APM_FUNC, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_NOCL1B_BOOST_OPTION1, DIV_CLK_APM_BOOST, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_CG_VAL, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_MANUAL, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_NOCL0_BOOST_OPTION1, DIV_CLK_APM_BOOST, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_CG_VAL, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_MANUAL, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_CMU_BOOST_OPTION1, DIV_CLK_APM_BOOST, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_CG_VAL, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_MANUAL, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, DIV_CLK_APM_USI0_UART, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, DIV_CLK_APM_USI1_UART, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, DIV_CLK_APM_USI0_USI, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, DIV_CLK_APM_USI0_UART, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, DIV_CLK_APM_USI0_USI, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, DIV_CLK_APM_USI1_UART, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK, DIV_CLK_APM_I3C_PMIC, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK, DIV_CLK_APM_I3C_PMIC, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK, DIV_CLK_APM_NOC_LH, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK, GATE_CLKCMU_APM_FUNC, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK, DIV_CLK_AUR_AUR, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK, MUX_CLKCMU_AUR_AURCTL_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK, OSCCLK_AUR, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK, MUX_CLK_AUR_AUR, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_AUR_AURCTL_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, MUX_CLKCMU_AUR_AURCTL_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_AUR_AURCTL_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK, DIV_CLK_AUR_NOCP_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK, DIV_CLK_AUR_NOCP_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK, DIV_CLK_AUR_AURCTL_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_AUR_NOCP_LH, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK, DIV_CLK_AUR_NOCP, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK, MUX_CLKCMU_AUR_AURCTL_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK, MUX_CLKCMU_AUR_NOC_USER, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK, DIV_CLK_BO_NOCP, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK, MUX_CLKCMU_BO_NOC_USER, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI1_NOC, MUX_CLKCMU_HSI1_NOC, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_MIF_SWITCH, MUX_CLKCMU_MIF_SWITCH, CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MFC_MFC, MUX_CLKCMU_MFC_MFC, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G2D_G2D, MUX_CLKCMU_G2D_G2D, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI0_USB31DRD, MUX_CLKCMU_HSI0_USB31DRD, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI2_NOC, MUX_CLKCMU_HSI2_NOC, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_DPU_NOC, MUX_CLKCMU_DPU_NOC, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MISC_NOC, MUX_CLKCMU_MISC_NOC, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CSIS_NOC, MUX_CLKCMU_CSIS_NOC, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PERIC0_NOC, MUX_CLKCMU_PERIC0_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PERIC1_NOC, MUX_CLKCMU_PERIC1_NOC, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CPUCL0_SWITCH, MUX_CLKCMU_CPUCL0_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_NOCL0_NOC, MUX_CLKCMU_NOCL0_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_ITP_NOC, MUX_CLKCMU_ITP_NOC, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G3AA_G3AA, MUX_CLKCMU_G3AA_G3AA, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MCSC_ITSC, MUX_CLKCMU_MCSC_ITSC, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G2D_MSCL, MUX_CLKCMU_G2D_MSCL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HPM, MUX_CLKCMU_HPM, CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI2_PCIE, MUX_CLKCMU_HSI2_PCIE, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CPUCL0_DBG_NOC, MUX_CLKCMU_CPUCL0_DBG, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK0, MUX_CLKCMU_CIS_CLK0, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK1, MUX_CLKCMU_CIS_CLK1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK3, MUX_CLKCMU_CIS_CLK3, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK2, MUX_CLKCMU_CIS_CLK2, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_BO_NOC, MUX_CLKCMU_BO_NOC, CLK_CON_GAT_GATE_CLKCMU_BO_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_BO_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI2_UFS_EMBD, MUX_CLKCMU_HSI2_UFS_EMBD, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI0_DPGTC, MUX_CLKCMU_HSI0_DPGTC, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MIF_NOCP, MUX_CLKCMU_MIF_NOCP, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PERIC0_IP, MUX_CLKCMU_PERIC0_IP, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PERIC1_IP, MUX_CLKCMU_PERIC1_IP, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TPU_NOC, MUX_CLKCMU_TPU_NOC, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI0_USBDPDBG, MUX_CLKCMU_HSI0_USBDPDBG, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PDP_VRA, MUX_CLKCMU_PDP_VRA, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CPUCL1_SWITCH, MUX_CLKCMU_CPUCL1_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI1_PCIE, MUX_CLKCMU_HSI1_PCIE, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI0_NOC, MUX_CLKCMU_HSI0_NOC, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_IPP_NOC, MUX_CLKCMU_IPP_NOC, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK4, MUX_CLKCMU_CIS_CLK4, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TNR_NOC, MUX_CLKCMU_TNR_NOC, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_NOCL2A_NOC, MUX_CLKCMU_NOCL2A_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_NOCL1A_NOC, MUX_CLKCMU_NOCL1A_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_NOCL1B_NOC, MUX_CLKCMU_NOCL1B_NOC, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK5, MUX_CLKCMU_CIS_CLK5, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK6, MUX_CLKCMU_CIS_CLK6, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CIS_CLK7, MUX_CLKCMU_CIS_CLK7, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_CPUCL0_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_CPUCL1_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_NOCL1B_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_NOCL2A_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_NOCL1A_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_NOCL0_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_NOCL0_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_NOCL0_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_NOCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_MIF_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_MIF_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_MIF_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_MIF_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_DNS_NOC, MUX_CLKCMU_DNS_NOC, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_GDC_GDC0, MUX_CLKCMU_GDC_GDC0, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_MANUAL, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_GDC_GDC1, MUX_CLKCMU_GDC_GDC1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_MANUAL, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MCSC_MCSC, MUX_CLKCMU_MCSC_MCSC, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TPU_TPU, MUX_CLKCMU_TPU_TPU, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CMU_BOOST, MUX_CLKCMU_CMU_BOOST, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_HSI2_MMCCARD, MUX_CLKCMU_HSI2_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G3D_GLB, MUX_CLKCMU_G3D_GLB, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_CPUCL2_SWITCH, MUX_CLKCMU_CPUCL2_SWITCH, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLKCMU_CPUCL2_BOOST, MUX_CLKCMU_CMU_BOOST_OPTION1, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_CG_VAL, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_MANUAL, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_GDC_SCSC, MUX_CLKCMU_GDC_SCSC, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_MISC_SSS, MUX_CLKCMU_MISC_SSS, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_MANUAL, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_DISP_NOC, MUX_CLKCMU_DISP_NOC, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_EH_NOC, MUX_CLKCMU_EH_NOC, CLK_CON_GAT_GATE_CLKCMU_EH_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_EH_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TOP_CMUREF, MUX_CLKCMU_TOP_CMUREF, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_PDP_NOC, MUX_CLKCMU_PDP_NOC, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TPU_UART, MUX_CLKCMU_TPU_UART, CLK_CON_GAT_GATE_CLKCMU_TPU_UART_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TPU_UART_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_TPU_TPUCTL, MUX_CLKCMU_TPU_TPUCTL, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_G3D_NOCD, MUX_CLKCMU_G3D_NOCD, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_MANUAL, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_AUR_AUR, MUX_CLKCMU_AUR_AUR, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_AUR_NOC, MUX_CLKCMU_AUR_NOC, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLKCMU_AUR_AURCTL, MUX_CLKCMU_AUR_AURCTL, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_CG_VAL, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_MANUAL, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_CPUCL0, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ACLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_PCLKDBG, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_CLUSTER0_PCLKDBG, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, DIV_CLK_CLUSTER0_ATCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_NOC, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_CPUCL0_DBG_NOC_USER, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_NOC_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK, DIV_CLK_CPUCL0_DBG_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK, DIV_CLK_CLUSTER0_ATCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK, DIV_CLK_CPUCL0_PCLK_LH, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK, DIV_CLK_CLUSTER0_PERIPHCLK, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1, MUX_CLK_CPUCL1_PLL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0, MUX_CLK_CPUCL1_PLL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN, MUX_CLK_CPUCL1_PLL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, DIV_CLK_CPUCL0_PCLK, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK, DIV_CLK_CPUCL2_CMUREF, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0, MUX_CLK_CPUCL2_PLL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1, MUX_CLK_CPUCL2_PLL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN, MUX_CLK_CPUCL2_PLL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, MUX_CLKCMU_CSIS_NOC_USER, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, DIV_CLK_CSIS_NOCP, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, MUX_CLKCMU_DISP_NOC_USER, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK, OSCCLK_DISP, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DISP_NOC_USER, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON, MUX_CLKCMU_DISP_NOC_USER, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK, DIV_CLK_DISP_NOCP, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_MANUAL, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK, DIV_CLK_DNS_NOCP, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_DNS_NOC_USER, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, OSCCLK_DPU, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, MUX_CLKCMU_DPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, DIV_CLK_DPU_NOCP, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK, MUX_CLK_EH_NOC, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK, MUX_CLK_EH_NOC, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK, DIV_CLK_EH_NOCP_LH, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK, DIV_CLK_EH_NOCP_LH, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_EH_NOCP_LH, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK, DIV_CLK_EH_NOCP, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK, MUX_CLK_EH_NOC, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_G2D_NOCP, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM, MUX_CLKCMU_G2D_G2D_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM, MUX_CLKCMU_G2D_MSCL_USER, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_G3AA_G3AA_USER, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK, DIV_CLK_G3AA_NOCP, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, OSCCLK_G3D, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, DIV_CLK_G3D_NOCP, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, CLK_G3D_ADD_CH_CLK, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK, MUX_CLK_G3D_STACKS, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH, MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_G3D_NOCP_LH, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK, DIV_CLK_G3D_NOCP_LH, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_G3D_NOCP_LH, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM, MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC0_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK, DIV_CLK_GDC_NOCP, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_GDC1_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, MUX_CLKCMU_GDC_SCSC_USER, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_GSACORE, GATE_CLK_GSACTRL2CORE, CLK_CON_GAT_CLK_GSACORE_CG_VAL, CLK_CON_GAT_CLK_GSACORE_MANUAL, CLK_CON_GAT_CLK_GSACORE_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK, DIV_CLK_GSACORE_SPI_FPS, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK, DIV_CLK_GSACORE_SPI_GSC, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK, DIV_CLK_GSACORE_UART, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK, DIV_CLK_GSACORE_SPI_FPS, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK, DIV_CLK_GSACORE_SPI_GSC, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK, DIV_CLK_GSACORE_UART, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK, CMU_GSACORE_REFCLK, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_CPU_LH, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_CPU_LH, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK, DIV_CLK_GSACORE_CPU_LH, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK, DIV_CLK_GSACORE_NOCP, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK, MUX_CLK_GSACORE_CPU_HCH, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM, DIV_CLK_GSACORE_NOCD, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLK_GSA_FUNC, MUX_CLKCMU_GSA_FUNC, CLK_CON_GAT_GATE_CLK_GSA_FUNC_CG_VAL, CLK_CON_GAT_GATE_CLK_GSA_FUNC_MANUAL, CLK_CON_GAT_GATE_CLK_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GATE_CLK_GSACTRL2CORE, GATE_CLK_GSA_FUNC, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_CG_VAL, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_MANUAL, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK, OSCCLK_GSACTRL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCP_LH, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCP_LH, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_GSACTRL_NOCP_LH, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, DIV_CLK_GSACTRL_NOCP, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK, DIV_CLK_GSACTRL_NOCD, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, MUX_CLK_HSI0_USB31DRD, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, MUX_CLKCMU_HSI0_DPGTC_USER, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, MUX_CLKCMU_HSI0_USPDPDBG_USER, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, MUX_CLK_HSI0_USB20_REF, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_HSI0_ALT, I_CLK_HSI0_ALT, CLK_CON_GAT_CLK_HSI0_ALT_CG_VAL, CLK_CON_GAT_CLK_HSI0_ALT_MANUAL, CLK_CON_GAT_CLK_HSI0_ALT_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK, MUX_CLK_HSI0_NOC, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK, DIV_CLK_HSI0_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, MUX_CLK_HSI0_USB20_REF, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_MANUAL, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, MUX_CLKCMU_HSI1_PCIE_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, OSCCLK_HSI1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM, DIV_CLK_HSI1_NOCP, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, DIV_CLK_HSI1_NOCP, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK, DIV_CLK_HSI1_NOCP, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, MUX_CLKCMU_HSI1_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, DIV_CLK_HSI1_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK, DIV_CLK_HSI1_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK, DIV_CLK_HSI1_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, OSCCLK_HSI2, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, MUX_CLKCMU_HSI2_UFS_EMBD_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, MUX_CLKCMU_HSI2_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, MUX_CLKCMU_HSI2_PCIE_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MUX_CLKCMU_HSI2_MMC_CARD_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM, DIV_CLK_HSI2_NOCP, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, DIV_CLK_HSI2_NOCP, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK, DIV_CLK_HSI2_NOCP, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1, MUX_CLKCMU_HSI2_NOC_USER, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK, DIV_CLK_HSI2_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK, DIV_CLK_HSI2_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK, DIV_CLK_HSI2_NOC_LH, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK, DIV_CLK_IPP_NOCP, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK, MUX_CLKCMU_IPP_NOC_USER, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK, DIV_CLK_ITP_NOCP, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_ITP_NOC_USER, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_ITSC_USER, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK, MUX_CLKCMU_MCSC_MCSC_USER, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK, DIV_CLK_MCSC_NOCP, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK, DIV_CLK_MFC_NOCP, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MFC_MFC_USER, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, OSCCLK_MIF, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, DIV_CLK_MIF_NOCD, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, DIV_CLK_MIF_NOCD, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK, MUX_CLKCMU_MIF_NOCP_USER, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK, CLK_MIF_NOCD_DBG, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, DIV_CLK_MIF_NOCP_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK, DIV_CLK_MIF_NOCP_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK, DIV_CLK_MIF_NOCD_DBG_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK, DIV_CLK_MIF_NOCD_DBG_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_MIF_NOCP_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK, CLK_MIF_NOCD_DBG, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK, DIV_CLK_MIF_NOCD_DBG_LH, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, OSCCLK_MISC, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, DIV_CLK_MISC_GIC, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, DIV_CLK_MISC_GIC, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, OSCCLK_MISC, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, OSCCLK_MISC, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, OSCCLK_MISC, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_SSS_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_MISC_NOCP_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK, DIV_CLK_MISC_NOCP_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_NOCP_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK, DIV_CLK_MISC_NOCP, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK, MUX_CLKCMU_MISC_NOC_USER, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK, DIV_CLK_MISC_GIC_LH, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK, DIV_CLK_SLC_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK, DIV_CLK_SLC_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK, DIV_CLK_SLC1_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK, DIV_CLK_SLC2_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK, DIV_CLK_SLC3_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK, DIV_CLK_SLC1_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK, DIV_CLK_SLC2_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK, DIV_CLK_SLC3_DCLK, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL0_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, MUX_CLK_NOCL0_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL0_NOCP, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL0, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL1A, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL1A, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL1A, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL1A, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL1A, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK, DIV_CLK_NOCL1A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL1A_NOC_USER, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL1A, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK, OSCCLK_NOCL1B, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL1B, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK, DIV_CLK_NOCL1B_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, MUX_CLK_NOCL1B_NOC_OPTION1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL1B_NOCP, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, OSCCLK_NOCL1B, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_NOCL2A_NOC_USER, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_CG_VAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_MANUAL, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_NOCL2A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK, DIV_CLK_NOCL2A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCD_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP_LH, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK, DIV_CLK_NOCL2A_NOCP, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_NOC_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK, DIV_CLK_PDP_NOCP, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK, MUX_CLKCMU_PDP_VRA_USER, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIC0, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI3_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI4_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI5_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI1_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI0_UART, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI2_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI6_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI7_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI8_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI1_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI2_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI3_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI4_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI5_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI6_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI7_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI8_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK, DIV_CLK_PERIC0_I3C, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI0_UART, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC0_USI14_USI, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC0_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, DIV_CLK_PERIC0_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK, DIV_CLK_PERIC0_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_PERIC0_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, OSCCLK_PERIC1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI12_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, DIV_CLK_PERIC1_I3C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI0_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI9_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI10_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI13_USI, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI0_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI9_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI10_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI11_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI12_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI13_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK, DIV_CLK_PERIC1_I3C, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, DIV_CLK_PERIC1_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK, DIV_CLK_PERIC1_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_PERIC1_NOCP_LH, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI15_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK, DIV_CLK_PERIC1_USI16_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK, MUX_CLKCMU_PERIC1_NOC_USER, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI15_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, DIV_CLK_PERIC1_USI16_USI, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, I_SCLK_S2D, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, MUX_CLK_S2D_CORE, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, I_SCLK_S2D, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, DIV_CLK_S2D_CORE_LH, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, DIV_CLK_S2D_CORE_LH, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK, DIV_CLK_S2D_CORE_LH, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK, MUX_CLKCMU_TNR_NOC_USER, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK, DIV_CLK_TNR_NOCP, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK, DIV_CLK_TPU_TPU, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK, MUX_CLKCMU_TPU_UART_USER, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL_DBG, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM, DIV_CLK_TPU_TPUCTL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C, CLKCMU_HPM, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, DIV_CLK_TPU_TPUCTL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK, OSCCLK_TPU, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK, DIV_CLK_TPU_TPUCTL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK, MUX_CLK_TPU_TPU, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN, MUX_CLK_TPU_TPU, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN, MUX_CLK_TPU_TPU, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK, DIV_CLK_TPU_TPUCTL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK, DIV_CLK_TPU_NOCP_LH, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK, DIV_CLK_TPU_NOCP_LH, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK, DIV_CLK_TPU_NOCP_LH, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK, MUX_CLKCMU_TPU_NOC_USER, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), + CLK_GATE(CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK, DIV_CLK_TPU_NOCP, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_CG_VAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_MANUAL, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING), +}; + +unsigned int cmucal_fixed_rate_size = 56; +struct cmucal_clk_fixed_rate cmucal_fixed_rate_list[] = { + FIXEDRATE(I_CLK_AOC_NOC, 787000000, EMPTY_CAL_ID), + FIXEDRATE(I_CLK_AOC_TRACE, 787000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_APM, 26000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV2_APM, 394000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV16_APM, 50000000, EMPTY_CAL_ID), + FIXEDRATE(PAD_CLK_APM, 100000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV4_APM, 197000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV8_APM, 99000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_AUR, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_BO, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_CMU, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_CPUCL0, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_CPUCL1, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_CPUCL2, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_CSIS, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_DISP, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_DNS, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_DPU, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_EH, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_G2D, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_G3AA, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_G3D, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_GDC, 26000000, EMPTY_CAL_ID), + FIXEDRATE(CMU_GSACORE_REFCLK, 100000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_GSACORE, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_GSA, 26000000, EMPTY_CAL_ID), + FIXEDRATE(PAD_CLK_GSA, 100000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV2, 393000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV, 787000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_GSACTRL, 26000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV16, 50000000, EMPTY_CAL_ID), + FIXEDRATE(PLL_ALV_DIV4, 197000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_HSI0, 26000000, EMPTY_CAL_ID), + FIXEDRATE(USB20PHY_PHY_CLOCK, 120000000, EMPTY_CAL_ID), + FIXEDRATE(TCXO_HSI1_HSI0, 26000000, EMPTY_CAL_ID), + FIXEDRATE(I_CLK_HSI0_ALT, 213000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_HSI1, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_HSI2, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_IPP, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_ITP, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_MCSC, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_MFC, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_MIF, 26000000, EMPTY_CAL_ID), + FIXEDRATE(CLK_MIF_NOCD_DBG, 466000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_MISC, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_NOCL0, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_NOCL1A, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_NOCL1B, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_NOCL2A, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_PDP, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_PERIC0, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_PERIC1, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_S2D, 26000000, EMPTY_CAL_ID), + FIXEDRATE(I_SCLK_S2D, 6500000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_TNR, 26000000, EMPTY_CAL_ID), + FIXEDRATE(OSCCLK_TPU, 26000000, EMPTY_CAL_ID), +}; + +unsigned int cmucal_fixed_factor_size = 4; +struct cmucal_clk_fixed_factor cmucal_fixed_factor_list[] = { + FIXEDFACTOR(CLKCMU_OTP, OSCCLK_CMU, 7, CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING), + FIXEDFACTOR(CLKCMU_HSI0_USBDPDBG, GATE_CLKCMU_HSI0_USBDPDBG, 3, CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING), + FIXEDFACTOR(DIV_CLK_MIF_NOCD, CLKMUX_MIF_DDRPHY2X, 3, CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING), + FIXEDFACTOR(CLK_MIF_NOCD_S2D, CLKCMU_MIF_DDRPHY2X_S2D, 3, CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING), +}; + diff --git a/drivers/soc/google/cal-if/gs201/cmucal-node.h b/drivers/soc/google/cal-if/gs201/cmucal-node.h new file mode 100644 index 000000000000..1b4340e01034 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-node.h @@ -0,0 +1,2407 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMUCAL_NODE_H__ +#define __CMUCAL_NODE_H__ + +#include "../cmucal.h" + +enum clk_id { + I_CLK_AOC_NOC = FIXED_RATE_TYPE, + I_CLK_AOC_TRACE, + OSCCLK_APM, + PLL_ALV_DIV2_APM, + PLL_ALV_DIV16_APM, + PAD_CLK_APM, + PLL_ALV_DIV4_APM, + PLL_ALV_DIV8_APM, + OSCCLK_AUR, + OSCCLK_BO, + OSCCLK_CMU, + OSCCLK_CPUCL0, + OSCCLK_CPUCL1, + OSCCLK_CPUCL2, + OSCCLK_CSIS, + OSCCLK_DISP, + OSCCLK_DNS, + OSCCLK_DPU, + OSCCLK_EH, + OSCCLK_G2D, + OSCCLK_G3AA, + OSCCLK_G3D, + OSCCLK_GDC, + CMU_GSACORE_REFCLK, + OSCCLK_GSACORE, + OSCCLK_GSA, + PAD_CLK_GSA, + PLL_ALV_DIV2, + PLL_ALV, + OSCCLK_GSACTRL, + PLL_ALV_DIV16, + PLL_ALV_DIV4, + OSCCLK_HSI0, + USB20PHY_PHY_CLOCK, + TCXO_HSI1_HSI0, + I_CLK_HSI0_ALT, + OSCCLK_HSI1, + OSCCLK_HSI2, + OSCCLK_IPP, + OSCCLK_ITP, + OSCCLK_MCSC, + OSCCLK_MFC, + OSCCLK_MIF, + CLK_MIF_NOCD_DBG, + OSCCLK_MISC, + OSCCLK_NOCL0, + OSCCLK_NOCL1A, + OSCCLK_NOCL1B, + OSCCLK_NOCL2A, + OSCCLK_PDP, + OSCCLK_PERIC0, + OSCCLK_PERIC1, + OSCCLK_S2D, + I_SCLK_S2D, + OSCCLK_TNR, + OSCCLK_TPU, + end_of_fixed_rate, + num_of_fixed_rate = (end_of_fixed_rate - FIXED_RATE_TYPE) & MASK_OF_ID, + + CLKCMU_OTP = FIXED_FACTOR_TYPE, + CLKCMU_HSI0_USBDPDBG, + DIV_CLK_MIF_NOCD, + CLK_MIF_NOCD_S2D, + end_of_fixed_factor, + num_of_fixed_factor = (end_of_fixed_factor - FIXED_FACTOR_TYPE) & MASK_OF_ID, + + PLL_AUR = PLL_TYPE, + PLL_SHARED0, + PLL_SHARED1, + PLL_SHARED2, + PLL_SHARED3, + PLL_SPARE, + PLL_LF_MIF, + PLL_CPUCL0, + PLL_CPUCL1, + PLL_CPUCL2, + PLL_G3D, + PLL_G3D_L2, + PLL_USB, + PLL_MIF_MAIN, + PLL_MIF_SUB, + PLL_NOCL0, + PLL_MIF_S2D, + PLL_TPU, + end_of_pll, + num_of_pll = (end_of_pll - PLL_TYPE) & MASK_OF_ID, + + MUX_CLKCMU_APM_FUNC = MUX_TYPE, + MUX_CLKCMU_APM_FUNCSRC, + MUX_CLK_AUR_AUR, + MUX_CLKCMU_MFC_MFC, + MUX_CLKCMU_HSI0_USB31DRD, + MUX_CLKCMU_G2D_G2D, + MUX_CLKCMU_CSIS_NOC, + MUX_CLKCMU_CPUCL0_SWITCH, + MUX_CLKCMU_NOCL0_NOC, + MUX_CLKCMU_MIF_SWITCH, + MUX_CLKCMU_ITP_NOC, + MUX_CLKCMU_G3AA_G3AA, + MUX_CLKCMU_MCSC_ITSC, + MUX_CLKCMU_G2D_MSCL, + MUX_CLKCMU_HPM, + MUX_CLKCMU_CPUCL0_DBG, + MUX_CLKCMU_HSI1_NOC, + MUX_CLKCMU_CIS_CLK0, + MUX_CLKCMU_CIS_CLK1, + MUX_CLKCMU_CIS_CLK2, + MUX_CLKCMU_CIS_CLK3, + MUX_CLKCMU_BO_NOC, + MUX_CLKCMU_HSI2_UFS_EMBD, + MUX_CMU_CMUREF, + MUX_CLKCMU_PERIC0_NOC, + MUX_CLKCMU_PERIC1_NOC, + MUX_CLKCMU_MISC_NOC, + MUX_CLKCMU_HSI0_DPGTC, + MUX_CLKCMU_HSI2_PCIE, + MUX_CLKCMU_HSI2_NOC, + MUX_CLKCMU_MIF_NOCP, + MUX_CLKCMU_PERIC0_IP, + MUX_CLKCMU_PERIC1_IP, + MUX_CLKCMU_TPU_NOC, + MUX_CLKCMU_HSI0_USBDPDBG, + MUX_CLKCMU_PDP_VRA, + MUX_CLKCMU_DPU_NOC, + MUX_CLKCMU_CPUCL1_SWITCH, + MUX_CLKCMU_HSI1_PCIE, + MUX_CLKCMU_HSI0_NOC, + MUX_CLKCMU_TOP_CMUREF, + MUX_CLKCMU_IPP_NOC, + MUX_CLKCMU_CIS_CLK4, + MUX_CLKCMU_CMU_BOOST, + MUX_CLKCMU_TNR_NOC, + MUX_CLKCMU_NOCL2A_NOC, + MUX_CLKCMU_NOCL1A_NOC, + MUX_CLKCMU_NOCL1B_NOC, + MUX_CLKCMU_CIS_CLK5, + MUX_CLKCMU_CIS_CLK6, + MUX_CLKCMU_DNS_NOC, + MUX_CLKCMU_GDC_GDC0, + MUX_CLKCMU_GDC_GDC1, + MUX_CLKCMU_MCSC_MCSC, + MUX_CLKCMU_TPU_TPU, + MUX_CLKCMU_HSI2_MMC_CARD, + MUX_CLKCMU_CIS_CLK7, + MUX_CLKCMU_G3D_GLB, + MUX_CLKCMU_CPUCL2_SWITCH, + MUX_CLKCMU_GDC_SCSC, + MUX_CLKCMU_MISC_SSS, + MUX_CLKCMU_DISP_NOC, + MUX_CLKCMU_EH_NOC, + MUX_CLKCMU_CMU_BOOST_OPTION1, + MUX_CLKCMU_TOP_BOOST_OPTION1, + MUX_CLKCMU_PDP_NOC, + MUX_CLKCMU_TPU_UART, + MUX_CLKCMU_TPU_TPUCTL, + MUX_CLKCMU_G3D_SWITCH, + MUX_CLKCMU_G3D_NOCD, + MUX_CLKCMU_AUR_AUR, + MUX_CLKCMU_AUR_NOC, + MUX_CLKCMU_AUR_AURCTL, + MUX_CLK_CPUCL0_PLL, + MUX_CPUCL0_CMUREF, + MUX_CPUCL1_CMUREF, + MUX_CLK_CPUCL1_PLL, + MUX_CLK_CPUCL2_PLL, + MUX_CPUCL2_CMUREF, + MUX_CLK_EH_NOC, + MUX_CLK_G3D_STACKS, + MUX_CLK_G3D_L2_GLB, + MUX_CLK_G3D_TOP, + MUX_CLK_GSACORE_CPU_HCH, + MUX_CLKCMU_GSA_FUNC, + MUX_CLKCMU_GSA_FUNCSRC, + MUX_CLK_HSI0_USB31DRD, + MUX_CLK_HSI0_NOC, + MUX_CLK_HSI0_USB20_REF, + MUX_MIF_CMUREF, + MUX_NOCL0_CMUREF, + MUX_CLK_NOCL0_NOC, + MUX_CLK_NOCL0_NOC_OPTION1, + MUX_NOCL1A_CMUREF, + MUX_NOCL1B_CMUREF, + MUX_CLK_NOCL1B_NOC_OPTION1, + MUX_NOCL2A_CMUREF, + MUX_CLK_S2D_CORE, + MUX_CLK_TPU_TPU, + MUX_CLK_TPU_TPUCTL, + AOC_CMU_AOC_CLKOUT0, + APM_CMU_APM_CLKOUT0, + AUR_CMU_AUR_CLKOUT0, + BO_CMU_BO_CLKOUT0, + CMU_CMU_TOP_CLKOUT0, + CPUCL0_CMU_CPUCL0_CLKOUT0, + CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0, + CPUCL1_CMU_CPUCL1_CLKOUT0, + CPUCL2_CMU_CPUCL2_CLKOUT0, + CSIS_CMU_CSIS_CLKOUT0, + DISP_CMU_DISP_CLKOUT0, + DNS_CMU_DNS_CLKOUT0, + DPU_CMU_DPU_CLKOUT0, + EH_CMU_EH_CLKOUT0, + G2D_CMU_G2D_CLKOUT0, + G3AA_CMU_G3AA_CLKOUT0, + G3D_CMU_G3D_CLKOUT0, + G3D_EMBEDDED_CMU_G3D_CLKOUT0, + GDC_CMU_GDC_CLKOUT0, + HSI0_CMU_HSI0_CLKOUT0, + HSI1_CMU_HSI1_CLKOUT0, + HSI2_CMU_HSI2_CLKOUT0, + IPP_CMU_IPP_CLKOUT0, + ITP_CMU_ITP_CLKOUT0, + MCSC_CMU_MCSC_CLKOUT0, + MFC_CMU_MFC_CLKOUT0, + MIF_CMU_MIF_CLKOUT0, + MISC_CMU_MISC_CLKOUT0, + NOCL0_CMU_NOCL0_CLKOUT0, + NOCL1A_CMU_NOCL1A_CLKOUT0, + NOCL1B_CMU_NOCL1B_CLKOUT0, + NOCL2A_CMU_NOCL2A_CLKOUT0, + PDP_CMU_PDP_CLKOUT0, + PERIC0_CMU_PERIC0_CLKOUT0, + PERIC1_CMU_PERIC1_CLKOUT0, + TNR_CMU_TNR_CLKOUT0, + TPU_CMU_TPU_CLKOUT0, + MUX_CLKCMU_AUR_SWITCH_USER = ((MASK_OF_ID & TPU_CMU_TPU_CLKOUT0) | USER_MUX_TYPE) + 1, + MUX_CLKCMU_AUR_AURCTL_USER, + MUX_CLKCMU_AUR_NOC_USER, + MUX_CLKCMU_BO_NOC_USER, + MUX_CLKCMU_CPUCL0_SWITCH_USER, + MUX_CLKCMU_CPUCL0_DBG_NOC_USER, + MUX_CLKCMU_CPUCL1_SWITCH_USER, + MUX_CLKCMU_CPUCL2_SWITCH_USER, + MUX_CLKCMU_CSIS_NOC_USER, + MUX_CLKCMU_DISP_NOC_USER, + MUX_CLKCMU_DNS_NOC_USER, + MUX_CLKCMU_DPU_NOC_USER, + MUX_CLKCMU_EH_NOC_USER, + MUX_CLKCMU_EH_PLL_NOCL0_USER, + MUX_CLKCMU_G2D_G2D_USER, + MUX_CLKCMU_G2D_MSCL_USER, + MUX_CLKCMU_G3AA_G3AA_USER, + MUX_CLKCMU_G3D_SWITCH_USER, + MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, + MUX_CLKCMU_G3D_GLB_USER, + MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, + MUX_CLKCMU_G3D_NOCD_USER, + MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, + MUX_CLKCMU_GDC_SCSC_USER, + MUX_CLKCMU_GDC_GDC0_USER, + MUX_CLKCMU_GDC_GDC1_USER, + MUX_CLKCMU_HSI0_NOC_USER, + MUX_CLKCMU_HSI0_USB31DRD_USER, + MUX_CLKCMU_HSI0_DPGTC_USER, + MUX_CLKCMU_HSI0_USPDPDBG_USER, + MUX_CLKCMU_HSI0_ALT_USER, + MUX_CLKCMU_HSI0_USB20_USER, + MUX_CLKCMU_HSI0_TCXO_USER, + MUX_CLKCMU_HSI1_NOC_USER, + MUX_CLKCMU_HSI1_PCIE_USER, + MUX_CLKCMU_HSI2_NOC_USER, + MUX_CLKCMU_HSI2_PCIE_USER, + MUX_CLKCMU_HSI2_UFS_EMBD_USER, + MUX_CLKCMU_HSI2_MMC_CARD_USER, + MUX_CLKCMU_IPP_NOC_USER, + MUX_CLKCMU_ITP_NOC_USER, + MUX_CLKCMU_MCSC_ITSC_USER, + MUX_CLKCMU_MCSC_MCSC_USER, + MUX_CLKCMU_MFC_MFC_USER, + MUX_CLKCMU_MIF_NOCP_USER, + CLKMUX_MIF_DDRPHY2X, + MUX_CLKCMU_MISC_NOC_USER, + MUX_CLKCMU_MISC_SSS_USER, + MUX_CLKCMU_NOCL0_NOC_USER, + MUX_CLKCMU_NOCL1A_NOC_USER, + MUX_CLKCMU_NOCL1B_NOC_USER, + MUX_CLKCMU_NOCL2A_NOC_USER, + MUX_CLKCMU_PDP_NOC_USER, + MUX_CLKCMU_PDP_VRA_USER, + MUX_CLKCMU_PERIC0_NOC_USER, + MUX_CLKCMU_PERIC0_USI6_USI_USER, + MUX_CLKCMU_PERIC0_USI3_USI_USER, + MUX_CLKCMU_PERIC0_USI4_USI_USER, + MUX_CLKCMU_PERIC0_USI5_USI_USER, + MUX_CLKCMU_PERIC0_USI14_USI_USER, + MUX_CLKCMU_PERIC0_I3C_USER, + MUX_CLKCMU_PERIC0_USI7_USI_USER, + MUX_CLKCMU_PERIC0_USI8_USI_USER, + MUX_CLKCMU_PERIC0_USI1_USI_USER, + MUX_CLKCMU_PERIC0_USI0_UART_USER, + MUX_CLKCMU_PERIC0_USI2_USI_USER, + MUX_CLKCMU_PERIC1_NOC_USER, + MUX_CLKCMU_PERIC1_USI11_USI_USER, + MUX_CLKCMU_PERIC1_USI12_USI_USER, + MUX_CLKCMU_PERIC1_USI0_USI_USER, + MUX_CLKCMU_PERIC1_I3C_USER, + MUX_CLKCMU_PERIC1_USI9_USI_USER, + MUX_CLKCMU_PERIC1_USI10_USI_USER, + MUX_CLKCMU_PERIC1_USI13_USI_USER, + MUX_CLKCMU_PERIC1_USI15_USI_USER, + MUX_CLKCMU_PERIC1_USI16_USI_USER, + CLKCMU_MIF_DDRPHY2X_S2D, + MUX_CLKCMU_TNR_NOC_USER, + MUX_CLKCMU_TPU_NOC_USER, + MUX_CLKCMU_TPU_TPU_USER, + MUX_CLKCMU_TPU_TPUCTL_USER, + MUX_CLKCMU_TPU_UART_USER, + end_of_mux, + num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID, + + DIV_CLK_AOC_NOC_LH = DIV_TYPE, + DIV_CLK_AOC_TRACE_LH, + DIV_CLK_APM_BOOST, + DIV_CLK_APM_USI0_USI, + DIV_CLK_APM_USI0_UART, + DIV_CLK_APM_USI1_UART, + DIV_CLK_APM_I3C_PMIC, + DIV_CLK_APM_NOC_LH, + DIV_CLK_AUR_NOCP, + CLK_AUR_ADD_CH_CLK, + DIV_CLK_AUR_AURCTL_LH, + DIV_CLK_AUR_NOCP_LH, + DIV_CLK_BO_NOCP, + CLKCMU_G3D_SWITCH, + CLKCMU_PERIC0_NOC, + CLKCMU_MISC_NOC, + CLKCMU_HSI1_NOC, + CLKCMU_DPU_NOC, + CLKCMU_MFC_MFC, + CLKCMU_G2D_G2D, + CLKCMU_HSI0_USB31DRD, + CLKCMU_CSIS_NOC, + CLKCMU_PERIC1_NOC, + CLKCMU_CPUCL0_SWITCH, + CLKCMU_NOCL0_NOC, + CLKCMU_ITP_NOC, + CLKCMU_G3AA_G3AA, + CLKCMU_MCSC_ITSC, + CLKCMU_G2D_MSCL, + CLKCMU_HPM, + CLKCMU_HSI2_PCIE, + CLKCMU_CPUCL0_DBG, + CLKCMU_CIS_CLK0, + CLKCMU_CIS_CLK1, + CLKCMU_CIS_CLK2, + CLKCMU_CIS_CLK3, + CLKCMU_BO_NOC, + CLKCMU_HSI2_UFS_EMBD, + CLKCMU_HSI0_DPGTC, + DIV_CLK_CMU_CMUREF, + CLKCMU_MIF_NOCP, + CLKCMU_PERIC0_IP, + CLKCMU_PERIC1_IP, + CLKCMU_TPU_NOC, + CLKCMU_PDP_VRA, + CLKCMU_CPUCL1_SWITCH, + CLKCMU_HSI1_PCIE, + CLKCMU_HSI0_NOC, + CLKCMU_IPP_NOC, + CLKCMU_CIS_CLK4, + DIV_CLKCMU_CMU_BOOST, + CLKCMU_TNR_NOC, + CLKCMU_NOCL2A_NOC, + CLKCMU_NOCL1A_NOC, + CLKCMU_NOCL1B_NOC, + CLKCMU_CIS_CLK5, + CLKCMU_CIS_CLK6, + CLKCMU_CIS_CLK7, + CLKCMU_DNS_NOC, + CLKCMU_GDC_GDC0, + CLKCMU_GDC_GDC1, + CLKCMU_MCSC_MCSC, + CLKCMU_TPU_TPU, + CLKCMU_HSI2_NOC, + CLKCMU_HSI2_MMC_CARD, + CLKCMU_G3D_GLB, + CLKCMU_CPUCL2_SWITCH, + CLKCMU_GDC_SCSC, + CLKCMU_MISC_SSS, + CLKCMU_DISP_NOC, + CLKCMU_EH_NOC, + CLKCMU_PDP_NOC, + CLKCMU_TPU_UART, + CLKCMU_TPU_TPUCTL, + PLL_SHARED0_DIV5, + CLKCMU_G3D_NOCD, + CLKCMU_AUR_AUR, + CLKCMU_AUR_NOC, + CLKCMU_AUR_AURCTL, + PLL_SHARED0_DIV2, + PLL_SHARED0_DIV4, + PLL_SHARED0_DIV3, + PLL_SHARED1_DIV2, + PLL_SHARED1_DIV4, + PLL_SHARED1_DIV3, + PLL_SHARED2_DIV2, + PLL_SHARED3_DIV2, + DIV_CLK_CPUCL0_CMUREF, + DIV_CLK_CLUSTER0_ACLK, + DIV_CLK_CLUSTER0_ATCLK, + DIV_CLK_CLUSTER0_PCLKDBG, + DIV_CLK_CLUSTER0_PERIPHCLK, + DIV_CLK_CPUCL0_DBG_PCLKDBG, + DIV_CLK_CPUCL0_PCLK, + DIV_CLK_CPUCL0_DBG_NOC, + DIV_CLK_CPUCL0_DBG_ATCLK_LH, + DIV_CLK_CPUCL0_DBG_NOC_LH, + DIV_CLK_CLUSTER0_ATCLK_LH, + DIV_CLK_CPUCL0_PCLK_LH, + DIV_CLK_CPUCL1_CMUREF, + DIV_CLK_CPUCL2_CMUREF, + DIV_CLK_CSIS_NOCP, + DIV_CLK_DISP_NOCP, + DIV_CLK_DNS_NOCP, + DIV_CLK_DPU_NOCP, + DIV_CLK_EH_NOCP, + DIV_CLK_EH_NOCP_LH, + DIV_CLK_G2D_NOCP, + DIV_CLK_G3AA_NOCP, + DIV_CLK_G3D_NOCP, + CLK_G3D_ADD_CH_CLK, + DIV_CLK_G3D_TOP, + DIV_CLK_G3D_NOCP_LH, + DIV_CLK_GDC_NOCP, + DIV_CLK_GSACORE_NOCP, + DIV_CLK_GSACORE_NOCD, + DIV_CLK_GSACORE_SPI_FPS, + DIV_CLK_GSACORE_SPI_GSC, + DIV_CLK_GSACORE_UART, + DIV_CLK_GSACORE_NOC, + DIV_CLK_GSACORE_CPU_LH, + DIV_CLK_GSACTRL_NOCP, + DIV_CLK_GSACTRL_NOCD, + DIV_CLK_GSACTRL_NOCP_LH, + DIV_CLK_HSI0_USB31DRD, + DIV_CLK_HSI0_USB, + DIV_CLK_HSI0_NOC_LH, + DIV_CLK_HSI1_NOCP, + DIV_CLK_HSI1_NOC_LH, + DIV_CLK_HSI2_NOCP, + DIV_CLK_HSI2_NOC_LH, + DIV_CLK_IPP_NOCP, + DIV_CLK_ITP_NOCP, + DIV_CLK_MCSC_NOCP, + DIV_CLK_MFC_NOCP, + DIV_CLK_MIF_NOCP_LH, + DIV_CLK_MIF_NOCD_DBG_LH, + DIV_CLK_MISC_NOCP, + DIV_CLK_MISC_GIC, + DIV_CLK_MISC_GIC_LH, + DIV_CLK_MISC_NOCP_LH, + DIV_CLK_NOCL0_NOCP, + DIV_CLK_SLC_DCLK, + DIV_CLK_SLC1_DCLK, + DIV_CLK_SLC2_DCLK, + DIV_CLK_SLC3_DCLK, + DIV_CLK_NOCL0_NOCD_LH, + DIV_CLK_NOCL0_NOCP_LH, + DIV_CLK_NOCL1A_NOCP, + DIV_CLK_NOCL1A_NOCD_LH, + DIV_CLK_NOCL1A_NOCP_LH, + DIV_CLK_NOCL1B_NOCP, + DIV_CLK_NOCL1B_NOCD_LH, + DIV_CLK_NOCL1B_NOCP_LH, + DIV_CLK_NOCL2A_NOCP, + DIV_CLK_NOCL2A_NOCD_LH, + DIV_CLK_NOCL2A_NOCP_LH, + DIV_CLK_PDP_NOCP, + DIV_CLK_PERIC0_USI6_USI, + DIV_CLK_PERIC0_USI3_USI, + DIV_CLK_PERIC0_USI4_USI, + DIV_CLK_PERIC0_USI5_USI, + DIV_CLK_PERIC0_USI14_USI, + DIV_CLK_PERIC0_I3C, + DIV_CLK_PERIC0_USI7_USI, + DIV_CLK_PERIC0_USI8_USI, + DIV_CLK_PERIC0_USI1_USI, + DIV_CLK_PERIC0_USI0_UART, + DIV_CLK_PERIC0_USI2_USI, + DIV_CLK_PERIC0_NOCP_LH, + DIV_CLK_PERIC1_USI11_USI, + DIV_CLK_PERIC1_I3C, + DIV_CLK_PERIC1_USI12_USI, + DIV_CLK_PERIC1_USI0_USI, + DIV_CLK_PERIC1_USI9_USI, + DIV_CLK_PERIC1_USI10_USI, + DIV_CLK_PERIC1_USI13_USI, + DIV_CLK_PERIC1_NOCP_LH, + DIV_CLK_PERIC1_USI15_USI, + DIV_CLK_PERIC1_USI16_USI, + DIV_CLK_S2D_CORE_LH, + DIV_CLK_TNR_NOCP, + DIV_CLK_TPU_NOCP, + DIV_CLK_TPU_TPUCTL_DBG, + DIV_CLK_TPU_NOCP_LH, + DIV_CLK_AUR_AUR = ((MASK_OF_ID & DIV_CLK_TPU_NOCP_LH) | CONST_DIV_TYPE) + 1, + DIV_CLK_CPUCL0_CPU, + DIV_CLK_CPUCL1_CPU, + DIV_CLK_CPUCL2_CPU, + DIV_CLK_G3D_STACKS, + DIV_CLK_G3D_L2_GLB, + DIV_CLK_TPU_TPU, + DIV_CLK_TPU_TPUCTL, + end_of_div, + num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID, + + CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK = GATE_TYPE, + GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK, + GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK, + GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK, + GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1, + GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2, + GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK, + GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK, + GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK, + CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK, + CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK, + CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK, + CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK, + GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, + GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK, + GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, + CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, + GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, + GATE_CLKCMU_APM_FUNC, + GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, + GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, + GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, + CLK_NOCL1B_BOOST_OPTION1, + CLK_NOCL0_BOOST_OPTION1, + CLK_CMU_BOOST_OPTION1, + GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK, + GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, + GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, + GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, + GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, + GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, + GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK, + CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK, + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK, + CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK, + CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK, + CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK, + CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, + CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK, + CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM, + CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1, + CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1, + CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2, + CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2, + CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM, + CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK, + CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK, + CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK, + GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK, + GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK, + GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1, + GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM, + GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK, + GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK, + GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK, + GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK, + GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2, + CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK, + CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK, + CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK, + GATE_CLKCMU_HSI1_NOC, + CLKCMU_MIF_SWITCH, + GATE_CLKCMU_MFC_MFC, + GATE_CLKCMU_G2D_G2D, + GATE_CLKCMU_HSI0_USB31DRD, + GATE_CLKCMU_HSI2_NOC, + GATE_CLKCMU_DPU_NOC, + GATE_CLKCMU_G3D_SWITCH, + GATE_CLKCMU_MISC_NOC, + GATE_CLKCMU_CSIS_NOC, + GATE_CLKCMU_PERIC0_NOC, + GATE_CLKCMU_PERIC1_NOC, + GATE_CLKCMU_CPUCL0_SWITCH, + GATE_CLKCMU_NOCL0_NOC, + GATE_CLKCMU_ITP_NOC, + GATE_CLKCMU_G3AA_G3AA, + GATE_CLKCMU_MCSC_ITSC, + GATE_CLKCMU_G2D_MSCL, + GATE_CLKCMU_HPM, + GATE_CLKCMU_HSI2_PCIE, + GATE_CLKCMU_CPUCL0_DBG_NOC, + GATE_CLKCMU_CIS_CLK0, + GATE_CLKCMU_CIS_CLK1, + GATE_CLKCMU_CIS_CLK3, + GATE_CLKCMU_CIS_CLK2, + GATE_CLKCMU_BO_NOC, + GATE_CLKCMU_HSI2_UFS_EMBD, + GATE_CLKCMU_HSI0_DPGTC, + GATE_CLKCMU_MIF_NOCP, + GATE_CLKCMU_PERIC0_IP, + GATE_CLKCMU_PERIC1_IP, + GATE_CLKCMU_TPU_NOC, + GATE_CLKCMU_HSI0_USBDPDBG, + GATE_CLKCMU_PDP_VRA, + GATE_CLKCMU_CPUCL1_SWITCH, + GATE_CLKCMU_HSI1_PCIE, + GATE_CLKCMU_HSI0_NOC, + GATE_CLKCMU_IPP_NOC, + GATE_CLKCMU_CIS_CLK4, + GATE_CLKCMU_TNR_NOC, + GATE_CLKCMU_NOCL2A_NOC, + GATE_CLKCMU_NOCL1A_NOC, + GATE_CLKCMU_NOCL1B_NOC, + GATE_CLKCMU_CIS_CLK5, + GATE_CLKCMU_CIS_CLK6, + GATE_CLKCMU_CIS_CLK7, + CLKCMU_CPUCL0_BOOST, + CLKCMU_CPUCL1_BOOST, + CLKCMU_NOCL1B_BOOST, + CLKCMU_NOCL2A_BOOST, + CLKCMU_NOCL1A_BOOST, + CLKCMU_NOCL0_BOOST, + CLKCMU_MIF_BOOST, + GATE_CLKCMU_DNS_NOC, + GATE_CLKCMU_GDC_GDC0, + GATE_CLKCMU_GDC_GDC1, + GATE_CLKCMU_MCSC_MCSC, + GATE_CLKCMU_TPU_TPU, + GATE_CLKCMU_CMU_BOOST, + GATE_CLKCMU_HSI2_MMCCARD, + GATE_CLKCMU_G3D_GLB, + GATE_CLKCMU_CPUCL2_SWITCH, + CLKCMU_CPUCL2_BOOST, + GATE_CLKCMU_GDC_SCSC, + GATE_CLKCMU_MISC_SSS, + GATE_CLKCMU_DISP_NOC, + GATE_CLKCMU_EH_NOC, + GATE_CLKCMU_TOP_CMUREF, + GATE_CLKCMU_PDP_NOC, + GATE_CLKCMU_TPU_UART, + GATE_CLKCMU_TPU_TPUCTL, + GATE_CLKCMU_G3D_NOCD, + GATE_CLKCMU_AUR_AUR, + GATE_CLKCMU_AUR_NOC, + GATE_CLKCMU_AUR_AURCTL, + GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, + GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, + GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, + GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, + CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, + GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, + GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK, + GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2, + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM, + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, + GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK, + CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK, + CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1, + CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0, + CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, + CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN, + CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK, + CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0, + CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1, + CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN, + GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, + GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, + CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, + GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, + GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, + GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, + GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, + GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF, + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA, + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, + CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK, + GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, + GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK, + GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON, + CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK, + GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK, + GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK, + GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK, + GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM, + GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1, + GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK, + GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK, + GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK, + GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, + CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, + CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK, + CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, + CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK, + CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK, + CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK, + GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK, + CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, + GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, + GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, + GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, + GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, + GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, + GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, + GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, + CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM, + GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK, + GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK, + GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK, + GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2, + GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK, + GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK, + GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK, + CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK, + CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK, + CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK, + CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK, + CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK, + CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK, + CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK, + GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK, + GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK, + GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, + GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2, + GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2, + GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2, + GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM, + GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM, + GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM, + GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK, + GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK, + GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK, + CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK, + GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK, + GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK, + GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK, + GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM, + GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK, + GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK, + GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK, + GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1, + GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2, + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK, + GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, + CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, + GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, + GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, + CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, + GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, + GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK, + GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, + GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, + GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK, + GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK, + GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, + GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK, + GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, + CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, + GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK, + CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH, + CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, + CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK, + CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM, + CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM, + GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM, + GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM, + GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2, + GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK, + GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK, + GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK, + GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2, + GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2, + GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK, + CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, + CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, + CLK_GSACORE, + CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN, + GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK, + GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK, + GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK, + GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK, + GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1, + GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK, + GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2, + GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM, + GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI, + GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB, + GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM, + CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM, + CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK, + GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK, + GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK, + CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK, + CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK, + CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK, + CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK, + CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM, + CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK, + GATE_CLK_GSA_FUNC, + GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK, + GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK, + GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK, + GATE_CLK_GSACTRL2CORE, + GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK, + GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK, + GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK, + GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK, + GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM, + GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK, + CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK, + CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK, + CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, + CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, + CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK, + CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, + GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, + GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, + GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK, + GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, + GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, + GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, + GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, + GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, + GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, + CLK_HSI0_ALT, + GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, + CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1, + CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK, + CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, + CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, + GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK, + GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, + GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, + GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK, + GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK, + GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, + GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK, + CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, + CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, + CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK, + GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK, + GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK, + GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK, + GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, + GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, + GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, + CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, + GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, + GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK, + CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK, + CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1, + CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK, + CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK, + CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK, + CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK, + GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM, + GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK, + GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1, + GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2, + GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, + GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, + GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, + GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK, + GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, + GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK, + GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK, + GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, + GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, + CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK, + CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK, + CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK, + CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, + CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK, + CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK, + GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, + GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM, + GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, + GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK, + GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, + GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK, + CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK, + CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK, + CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK, + CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK, + CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, + GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK, + GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK, + GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, + GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1, + GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1, + GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK, + GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK, + GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK, + GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2, + GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2, + CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK, + GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK, + GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, + CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK, + GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, + CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, + CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, + GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK, + CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK, + CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, + CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK, + CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK, + CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK, + CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK, + CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK, + GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK, + CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, + GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, + GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, + CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, + GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK, + GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, + GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, + GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, + GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, + GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM, + GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, + GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, + GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, + GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, + GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, + GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK, + GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK, + CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK, + CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM, + GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0, + GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0, + GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK, + CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK, + GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK, + GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK, + GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, + GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK, + GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, + CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, + GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, + GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0, + GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM, + GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK, + CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, + CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, + CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, + GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, + GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B, + GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, + CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK, + GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK, + GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A, + CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK, + CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK, + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK, + CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK, + GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK, + GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK, + GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK, + GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK, + GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM, + CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK, + CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK, + CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK, + CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK, + CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK, + CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK, + CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK, + CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK, + GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, + CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK, + CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, + CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, + CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK, + CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0, + CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK, + CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK, + CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK, + CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, + GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, + GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, + GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, + GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, + GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, + CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, + CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, + CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK, + GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM, + GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, + CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK, + GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK, + GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, + GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, + GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2, + GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2, + GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK, + GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK, + GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2, + GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, + CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK, + CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK, + CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK, + CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK, + GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK, + GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1, + GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK, + GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK, + GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2, + GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK, + GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK, + GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK, + GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS, + GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM, + CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C, + GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK, + GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN, + CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK, + CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK, + CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK, + CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK, + end_of_gate, + num_of_gate = (end_of_gate - GATE_TYPE) & MASK_OF_ID, + +}; +#endif diff --git a/drivers/soc/google/cal-if/gs201/cmucal-qch.c b/drivers/soc/google/cal-if/gs201/cmucal-qch.c new file mode 100644 index 000000000000..9b5fe055b36e --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-qch.c @@ -0,0 +1,1301 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "../cmucal.h" +#include "cmucal-sfr.h" +#include "cmucal-qch.h" + +unsigned int cmucal_qch_size = 1240; +struct cmucal_qch cmucal_qch_list[] = { + CLK_QCH(AOC_CMU_AOC_QCH, QCH_CON_AOC_CMU_AOC_QCH_ENABLE, QCH_CON_AOC_CMU_AOC_QCH_CLOCK_REQ, QCH_CON_AOC_CMU_AOC_QCH_EXPIRE_VAL, QCH_CON_AOC_CMU_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(AOC_SYSCTRL_APB_QCH, QCH_CON_AOC_SYSCTRL_APB_QCH_ENABLE, QCH_CON_AOC_SYSCTRL_APB_QCH_CLOCK_REQ, QCH_CON_AOC_SYSCTRL_APB_QCH_EXPIRE_VAL, QCH_CON_AOC_SYSCTRL_APB_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BAAW_AOC_QCH, QCH_CON_BAAW_AOC_QCH_ENABLE, QCH_CON_BAAW_AOC_QCH_CLOCK_REQ, QCH_CON_BAAW_AOC_QCH_EXPIRE_VAL, QCH_CON_BAAW_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_AOC_QCH, QCH_CON_D_TZPC_AOC_QCH_ENABLE, QCH_CON_D_TZPC_AOC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AOC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_AOC_QCH, QCH_CON_GPC_AOC_QCH_ENABLE, QCH_CON_GPC_AOC_QCH_CLOCK_REQ, QCH_CON_GPC_AOC_QCH_EXPIRE_VAL, QCH_CON_GPC_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AOC_CD_QCH, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AOC_QCH, QCH_CON_LH_ATB_SI_LT_AOC_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AOC_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AOC_CD_QCH, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_HSI0_AOC_QCH, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LP0_AOC_CD_QCH, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LP1_AOC_CD_QCH, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_AOC_CU_QCH, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_AOC_QCH, QCH_CON_LH_AXI_SI_D_AOC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_AOC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LP0_AOC_CD_QCH, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LP1_AOC_CD_QCH, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_AOC_CU_QCH, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_AOC_QCH, QCH_CON_PPMU_AOC_QCH_ENABLE, QCH_CON_PPMU_AOC_QCH_CLOCK_REQ, QCH_CON_PPMU_AOC_QCH_EXPIRE_VAL, QCH_CON_PPMU_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_USB_QCH, QCH_CON_PPMU_USB_QCH_ENABLE, QCH_CON_PPMU_USB_QCH_CLOCK_REQ, QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LG_AOC_QCH, QCH_CON_SLH_AXI_MI_LG_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LG_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LG_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LG_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_AOC_QCH, QCH_CON_SLH_AXI_MI_P_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_LP0_AOC_QCH, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_LP1_AOC_QCH, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_AOC_QCH, QCH_CON_SSMT_AOC_QCH_ENABLE, QCH_CON_SSMT_AOC_QCH_CLOCK_REQ, QCH_CON_SSMT_AOC_QCH_EXPIRE_VAL, QCH_CON_SSMT_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_AOC_QCH_S1, QCH_CON_SYSMMU_AOC_QCH_S1_ENABLE, QCH_CON_SYSMMU_AOC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_AOC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_AOC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_AOC_QCH_S2, QCH_CON_SYSMMU_AOC_QCH_S2_ENABLE, QCH_CON_SYSMMU_AOC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_AOC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_AOC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_AOC_QCH, QCH_CON_SYSREG_AOC_QCH_ENABLE, QCH_CON_SYSREG_AOC_QCH_CLOCK_REQ, QCH_CON_SYSREG_AOC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_AOC_QCH, QCH_CON_UASC_AOC_QCH_ENABLE, QCH_CON_UASC_AOC_QCH_CLOCK_REQ, QCH_CON_UASC_AOC_QCH_EXPIRE_VAL, QCH_CON_UASC_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_GPIO_FAR_ALIVE_QCH, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_INTCOMB_VGPIO2AP_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_EXPIRE_VAL, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_INTCOMB_VGPIO2APM_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_EXPIRE_VAL, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_INTCOMB_VGPIO2PMU_QCH, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_EXPIRE_VAL, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_TRTC_QCH, QCH_CON_APBIF_TRTC_QCH_ENABLE, QCH_CON_APBIF_TRTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TRTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TRTC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_CMU_APM_QCH, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_I3C_PMIC_QCH_P, QCH_CON_APM_I3C_PMIC_QCH_P_ENABLE, QCH_CON_APM_I3C_PMIC_QCH_P_CLOCK_REQ, QCH_CON_APM_I3C_PMIC_QCH_P_EXPIRE_VAL, QCH_CON_APM_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_I3C_PMIC_QCH_S, DMYQCH_CON_APM_I3C_PMIC_QCH_S_ENABLE, DMYQCH_CON_APM_I3C_PMIC_QCH_S_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_APM_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_USI0_UART_QCH, QCH_CON_APM_USI0_UART_QCH_ENABLE, QCH_CON_APM_USI0_UART_QCH_CLOCK_REQ, QCH_CON_APM_USI0_UART_QCH_EXPIRE_VAL, QCH_CON_APM_USI0_UART_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_USI0_USI_QCH, QCH_CON_APM_USI0_USI_QCH_ENABLE, QCH_CON_APM_USI0_USI_QCH_CLOCK_REQ, QCH_CON_APM_USI0_USI_QCH_EXPIRE_VAL, QCH_CON_APM_USI0_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APM_USI1_UART_QCH, QCH_CON_APM_USI1_UART_QCH_ENABLE, QCH_CON_APM_USI1_UART_QCH_CLOCK_REQ, QCH_CON_APM_USI1_UART_QCH_EXPIRE_VAL, QCH_CON_APM_USI1_UART_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_APM_QCH, QCH_CON_D_TZPC_APM_QCH_ENABLE, QCH_CON_D_TZPC_APM_QCH_CLOCK_REQ, QCH_CON_D_TZPC_APM_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_APM_QCH, QCH_CON_GPC_APM_QCH_ENABLE, QCH_CON_GPC_APM_QCH_CLOCK_REQ, QCH_CON_GPC_APM_QCH_EXPIRE_VAL, QCH_CON_GPC_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN), + CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN), + CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IG_SWD_QCH, QCH_CON_LH_AXI_MI_IG_SWD_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_SWD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_SWD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IG_SWD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_DBGCORE_CD_QCH, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_SCAN2DRAM_CD_QCH, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LP0_AOC_CU_QCH, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_ALIVE_CU_QCH, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_APM_QCH, QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_DBGCORE_CD_QCH, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_SCAN2DRAM_CD_QCH, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LP0_AOC_CU_QCH, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_ALIVE_CU_QCH, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_AOC_QCH, QCH_CON_MAILBOX_APM_AOC_QCH_ENABLE, QCH_CON_MAILBOX_APM_AOC_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AOC_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_AUR_QCH, QCH_CON_MAILBOX_APM_AUR_QCH_ENABLE, QCH_CON_MAILBOX_APM_AUR_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AUR_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_GSA_QCH, QCH_CON_MAILBOX_APM_GSA_QCH_ENABLE, QCH_CON_MAILBOX_APM_GSA_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_GSA_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_SWD_QCH, QCH_CON_MAILBOX_APM_SWD_QCH_ENABLE, QCH_CON_MAILBOX_APM_SWD_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_SWD_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_SWD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_APM_TPU_QCH, QCH_CON_MAILBOX_APM_TPU_QCH_ENABLE, QCH_CON_MAILBOX_APM_TPU_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_TPU_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AOCA32_QCH, QCH_CON_MAILBOX_AP_AOCA32_QCH_ENABLE, QCH_CON_MAILBOX_AP_AOCA32_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AOCA32_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AOCA32_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AOCF1_QCH, QCH_CON_MAILBOX_AP_AOCF1_QCH_ENABLE, QCH_CON_MAILBOX_AP_AOCF1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AOCF1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AOCF1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AOCP6_QCH, QCH_CON_MAILBOX_AP_AOCP6_QCH_ENABLE, QCH_CON_MAILBOX_AP_AOCP6_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AOCP6_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AOCP6_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AUR0_QCH, QCH_CON_MAILBOX_AP_AUR0_QCH_ENABLE, QCH_CON_MAILBOX_AP_AUR0_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AUR0_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AUR0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AUR1_QCH, QCH_CON_MAILBOX_AP_AUR1_QCH_ENABLE, QCH_CON_MAILBOX_AP_AUR1_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AUR1_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AUR1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AUR2_QCH, QCH_CON_MAILBOX_AP_AUR2_QCH_ENABLE, QCH_CON_MAILBOX_AP_AUR2_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AUR2_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AUR2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_AUR3_QCH, QCH_CON_MAILBOX_AP_AUR3_QCH_ENABLE, QCH_CON_MAILBOX_AP_AUR3_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_AUR3_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_AUR3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ROM_CRC32_HOST_QCH, QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_APM_GREBE_QCH, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LP0_AOC_QCH, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_ALIVE_QCH, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_LG_DBGCORE_QCH, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_LG_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D_APM_QCH, QCH_CON_SSMT_D_APM_QCH_ENABLE, QCH_CON_SSMT_D_APM_QCH_CLOCK_REQ, QCH_CON_SSMT_D_APM_QCH_EXPIRE_VAL, QCH_CON_SSMT_D_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_LG_DBGCORE_QCH, QCH_CON_SSMT_LG_DBGCORE_QCH_ENABLE, QCH_CON_SSMT_LG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SSMT_LG_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SSMT_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SS_DBGCORE_QCH_GREBE, QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN), + CLK_QCH(SS_DBGCORE_QCH_DBG, QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D_APM_QCH, QCH_CON_SYSMMU_D_APM_QCH_ENABLE, QCH_CON_SYSMMU_D_APM_QCH_CLOCK_REQ, QCH_CON_SYSMMU_D_APM_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_D_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_APM_QCH, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_APM_QCH, QCH_CON_UASC_APM_QCH_ENABLE, QCH_CON_UASC_APM_QCH_CLOCK_REQ, QCH_CON_UASC_APM_QCH_EXPIRE_VAL, QCH_CON_UASC_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_DBGCORE_QCH, QCH_CON_UASC_DBGCORE_QCH_ENABLE, QCH_CON_UASC_DBGCORE_QCH_CLOCK_REQ, QCH_CON_UASC_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_UASC_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_IG_SWD_QCH, QCH_CON_UASC_IG_SWD_QCH_ENABLE, QCH_CON_UASC_IG_SWD_QCH_CLOCK_REQ, QCH_CON_UASC_IG_SWD_QCH_EXPIRE_VAL, QCH_CON_UASC_IG_SWD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_LP0_AOC_QCH, QCH_CON_UASC_LP0_AOC_QCH_ENABLE, QCH_CON_UASC_LP0_AOC_QCH_CLOCK_REQ, QCH_CON_UASC_LP0_AOC_QCH_EXPIRE_VAL, QCH_CON_UASC_LP0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_P_ALIVE_QCH, QCH_CON_UASC_P_ALIVE_QCH_ENABLE, QCH_CON_UASC_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_UASC_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_UASC_P_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(WDT_APM_QCH, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADD_APBIF_AUR_QCH, QCH_CON_ADD_APBIF_AUR_QCH_ENABLE, QCH_CON_ADD_APBIF_AUR_QCH_CLOCK_REQ, QCH_CON_ADD_APBIF_AUR_QCH_EXPIRE_VAL, QCH_CON_ADD_APBIF_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADD_AUR_QCH, DMYQCH_CON_ADD_AUR_QCH_ENABLE, DMYQCH_CON_ADD_AUR_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(AUR_QCH, DMYQCH_CON_AUR_QCH_ENABLE, DMYQCH_CON_AUR_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(AUR_CMU_AUR_QCH, QCH_CON_AUR_CMU_AUR_QCH_ENABLE, QCH_CON_AUR_CMU_AUR_QCH_CLOCK_REQ, QCH_CON_AUR_CMU_AUR_QCH_EXPIRE_VAL, QCH_CON_AUR_CMU_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BAAW_AUR_QCH, QCH_CON_BAAW_AUR_QCH_ENABLE, QCH_CON_BAAW_AUR_QCH_CLOCK_REQ, QCH_CON_BAAW_AUR_QCH_EXPIRE_VAL, QCH_CON_BAAW_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_AUR_QCH, QCH_CON_D_TZPC_AUR_QCH_ENABLE, QCH_CON_D_TZPC_AUR_QCH_CLOCK_REQ, QCH_CON_D_TZPC_AUR_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_AUR_QCH, QCH_CON_GPC_AUR_QCH_ENABLE, QCH_CON_GPC_AUR_QCH_CLOCK_REQ, QCH_CON_GPC_AUR_QCH_EXPIRE_VAL, QCH_CON_GPC_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AUR_CPUCL0_QCH, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_AUR_CU_QCH, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_AUR_QCH, QCH_CON_LH_AXI_SI_D0_AUR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_AUR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_AUR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_AUR_QCH, QCH_CON_LH_AXI_SI_D1_AUR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_AUR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_AUR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_AUR_CU_QCH, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_AUR_QCH, QCH_CON_PPMU_D0_AUR_QCH_ENABLE, QCH_CON_PPMU_D0_AUR_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_AUR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_AUR_QCH, QCH_CON_PPMU_D1_AUR_QCH_ENABLE, QCH_CON_PPMU_D1_AUR_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_AUR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_AUR_QCH, QCH_CON_SLH_AXI_MI_P_AUR_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_AUR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_AUR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_AUR_QCH, QCH_CON_SSMT_D0_AUR_QCH_ENABLE, QCH_CON_SSMT_D0_AUR_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_AUR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_AUR_QCH, QCH_CON_SSMT_D1_AUR_QCH_ENABLE, QCH_CON_SSMT_D1_AUR_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_AUR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_AUR_WP_QCH_S1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_AUR_WP_QCH_S2, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_AUR_WP_QCH_S1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_AUR_WP_QCH_S2, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_AUR_QCH, QCH_CON_SYSREG_AUR_QCH_ENABLE, QCH_CON_SYSREG_AUR_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUR_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_AUR_QCH, QCH_CON_UASC_AUR_QCH_ENABLE, QCH_CON_UASC_AUR_QCH_CLOCK_REQ, QCH_CON_UASC_AUR_QCH_EXPIRE_VAL, QCH_CON_UASC_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BO_QCH, DMYQCH_CON_BO_QCH_ENABLE, DMYQCH_CON_BO_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BO_CMU_BO_QCH, QCH_CON_BO_CMU_BO_QCH_ENABLE, QCH_CON_BO_CMU_BO_QCH_CLOCK_REQ, QCH_CON_BO_CMU_BO_QCH_EXPIRE_VAL, QCH_CON_BO_CMU_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_BO_QCH, QCH_CON_D_TZPC_BO_QCH_ENABLE, QCH_CON_D_TZPC_BO_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BO_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_BO_QCH, QCH_CON_GPC_BO_QCH_ENABLE, QCH_CON_GPC_BO_QCH_CLOCK_REQ, QCH_CON_GPC_BO_QCH_EXPIRE_VAL, QCH_CON_GPC_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_BO_QCH, QCH_CON_LH_AXI_MI_IP_BO_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_BO_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_BO_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_BO_QCH, QCH_CON_LH_AXI_SI_D_BO_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_BO_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_BO_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_BO_QCH, QCH_CON_LH_AXI_SI_IP_BO_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_BO_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_BO_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_BO_QCH, QCH_CON_PPMU_BO_QCH_ENABLE, QCH_CON_PPMU_BO_QCH_CLOCK_REQ, QCH_CON_PPMU_BO_QCH_EXPIRE_VAL, QCH_CON_PPMU_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_BO_QCH, QCH_CON_SLH_AXI_MI_P_BO_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_BO_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_BO_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_BO_QCH, QCH_CON_SSMT_BO_QCH_ENABLE, QCH_CON_SSMT_BO_QCH_CLOCK_REQ, QCH_CON_SSMT_BO_QCH_EXPIRE_VAL, QCH_CON_SSMT_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_BO_QCH_S1, QCH_CON_SYSMMU_BO_QCH_S1_ENABLE, QCH_CON_SYSMMU_BO_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_BO_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_BO_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_BO_QCH_S2, QCH_CON_SYSMMU_BO_QCH_S2_ENABLE, QCH_CON_SYSMMU_BO_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_BO_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_BO_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_BO_QCH, QCH_CON_SYSREG_BO_QCH_ENABLE, QCH_CON_SYSREG_BO_QCH_CLOCK_REQ, QCH_CON_SYSREG_BO_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_BO_QCH, QCH_CON_UASC_BO_QCH_ENABLE, QCH_CON_UASC_BO_QCH_CLOCK_REQ, QCH_CON_UASC_BO_QCH_EXPIRE_VAL, QCH_CON_UASC_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_TOP_CMUREF_QCH, DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK5, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK6, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN), + CLK_QCH(DFTMUX_CMU_QCH_CIS_CLK7, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN), + CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADM_APB_G_CLUSTER0_QCH, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BPS_CPUCL0_QCH, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_SCLK, QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_ATCLK, QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_GIC, QCH_CON_CLUSTER0_QCH_GIC_ENABLE, QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_PCLK, QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_PERIPHCLK, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_DBG_PD, QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN), + CLK_QCH(CLUSTER0_QCH_PDBGCLK, QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL0_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL, QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_CPUCL0_QCH, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_CPUCL0_QCH, QCH_CON_GPC_CPUCL0_QCH_ENABLE, QCH_CON_GPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_GPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_GPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(HPM_APBIF_CPUCL0_QCH, QCH_CON_HPM_APBIF_CPUCL0_QCH_ENABLE, QCH_CON_HPM_APBIF_CPUCL0_QCH_CLOCK_REQ, QCH_CON_HPM_APBIF_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_HPM_APBIF_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACE_SI_D0_CPUCL0_QCH, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_ENABLE, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACE_SI_D1_CPUCL0_QCH, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_ENABLE, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT0_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT1_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT2_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT3_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT4_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT5_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT6_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_IT7_CLUSTER0_QCH, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT0_TPU_CPUCL0_QCH, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT1_TPU_CPUCL0_QCH, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AOC_QCH, QCH_CON_LH_ATB_MI_LT_AOC_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AOC_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AOC_CU_QCH, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AUR_CPUCL0_QCH, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_GSA_CPUCL0_QCH, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_BDU_QCH, QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_BDU_CU_QCH, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_SLC_QCH, QCH_CON_LH_ATB_MI_T_SLC_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_SLC_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_SLC_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_SLC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_SLC_CU_QCH, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT0_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT1_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT2_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT3_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT4_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT5_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT6_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_IT7_CLUSTER0_QCH, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_ENABLE, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AOC_CU_QCH, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_BDU_CU_QCH, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_SLC_CU_QCH, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_G_CSSYS_CD_QCH, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IG_CSSYS_QCH, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IG_DBGCORE_QCH, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IG_HSI0_QCH, QCH_CON_LH_AXI_MI_IG_HSI0_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_HSI0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_HSI0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IG_STM_QCH, QCH_CON_LH_AXI_MI_IG_STM_QCH_ENABLE, QCH_CON_LH_AXI_MI_IG_STM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IG_STM_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_DBGCORE_CU_QCH, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_ETR_HSI0_CD_QCH, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_CPUCL0_CU_QCH, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_G_CSSYS_CD_QCH, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IG_CSSYS_QCH, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_ENABLE, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IG_DBGCORE_QCH, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_ENABLE, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IG_HSI0_QCH, QCH_CON_LH_AXI_SI_IG_HSI0_QCH_ENABLE, QCH_CON_LH_AXI_SI_IG_HSI0_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IG_HSI0_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IG_STM_QCH, QCH_CON_LH_AXI_SI_IG_STM_QCH_ENABLE, QCH_CON_LH_AXI_SI_IG_STM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IG_STM_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_DBGCORE_CU_QCH, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_ETR_HSI0_CD_QCH, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_CPUCL0_CU_QCH, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LG_DBGCORE_QCH, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_G_CSSYS_QCH, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_LG_ETR_HSI0_QCH, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_CPUCL0_QCH, QCH_CON_SSMT_CPUCL0_QCH_ENABLE, QCH_CON_SSMT_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SSMT_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SSMT_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_S2_CPUCL0_QCH, QCH_CON_SYSMMU_S2_CPUCL0_QCH_ENABLE, QCH_CON_SYSMMU_S2_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_S2_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_S2_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL1_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CPUCL1_QCH_MID, DMYQCH_CON_CPUCL1_QCH_MID_ENABLE, DMYQCH_CON_CPUCL1_QCH_MID_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_MID_IGNORE_FORCE_PM_EN), + CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL2_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_CPUCL2_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CPUCL2_QCH_BIG, DMYQCH_CON_CPUCL2_QCH_BIG_ENABLE, DMYQCH_CON_CPUCL2_QCH_BIG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL2_QCH_BIG_IGNORE_FORCE_PM_EN), + CLK_QCH(CPUCL2_CMU_CPUCL2_QCH, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CSISX8_QCH_C2_CSIS, QCH_CON_CSISX8_QCH_C2_CSIS_ENABLE, QCH_CON_CSISX8_QCH_C2_CSIS_CLOCK_REQ, QCH_CON_CSISX8_QCH_C2_CSIS_EXPIRE_VAL, QCH_CON_CSISX8_QCH_C2_CSIS_IGNORE_FORCE_PM_EN), + CLK_QCH(CSISX8_QCH_CSIS_DMA, QCH_CON_CSISX8_QCH_CSIS_DMA_ENABLE, QCH_CON_CSISX8_QCH_CSIS_DMA_CLOCK_REQ, QCH_CON_CSISX8_QCH_CSIS_DMA_EXPIRE_VAL, QCH_CON_CSISX8_QCH_CSIS_DMA_IGNORE_FORCE_PM_EN), + CLK_QCH(CSISX8_QCH_EBUF, QCH_CON_CSISX8_QCH_EBUF_ENABLE, QCH_CON_CSISX8_QCH_EBUF_CLOCK_REQ, QCH_CON_CSISX8_QCH_EBUF_EXPIRE_VAL, QCH_CON_CSISX8_QCH_EBUF_IGNORE_FORCE_PM_EN), + CLK_QCH(CSIS_CMU_CSIS_QCH, QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_CSIS_QCH, QCH_CON_D_TZPC_CSIS_QCH_ENABLE, QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_CSIS_QCH, QCH_CON_GPC_CSIS_QCH_ENABLE, QCH_CON_GPC_CSIS_QCH_CLOCK_REQ, QCH_CON_GPC_CSIS_QCH_EXPIRE_VAL, QCH_CON_GPC_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_PDP_CSIS_QCH, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_PDP_CSIS_QCH, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF2_PDP_CSIS_QCH, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_SOTF0_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_SOTF1_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_SOTF2_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_MCSC_CSIS_QCH, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_CSIS_PDP_QCH, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_CSIS_PDP_QCH, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF2_CSIS_PDP_QCH, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_CSIS_PDP_QCH, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_PDP_CSIS_QCH, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_CSIS_QCH, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_CSIS_QCH, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS0, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS2, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS3, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS4, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS5, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS6, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN), + CLK_QCH(MIPI_PHY_LINK_WRAP_QCH_CSIS7, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_ENABLE, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_CLOCK_REQ, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_EXPIRE_VAL, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_QCH, QCH_CON_PPMU_D0_QCH_ENABLE, QCH_CON_PPMU_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_QCH, QCH_CON_PPMU_D1_QCH_ENABLE, QCH_CON_PPMU_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_CSIS_DMA0_QCH, QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_CSIS_DMA1_QCH, QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_CSIS_DMA2_QCH, QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_CSIS_DMA3_QCH, QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_STRP0_QCH, QCH_CON_QE_STRP0_QCH_ENABLE, QCH_CON_QE_STRP0_QCH_CLOCK_REQ, QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_STRP1_QCH, QCH_CON_QE_STRP1_QCH_ENABLE, QCH_CON_QE_STRP1_QCH_CLOCK_REQ, QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_STRP2_QCH, QCH_CON_QE_STRP2_QCH_ENABLE, QCH_CON_QE_STRP2_QCH_CLOCK_REQ, QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ZSL0_QCH, QCH_CON_QE_ZSL0_QCH_ENABLE, QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ZSL1_QCH, QCH_CON_QE_ZSL1_QCH_ENABLE, QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ZSL2_QCH, QCH_CON_QE_ZSL2_QCH_ENABLE, QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_CSIS_QCH, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_QCH, QCH_CON_SSMT_D0_QCH_ENABLE, QCH_CON_SSMT_D0_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_QCH, QCH_CON_SSMT_D1_QCH_ENABLE, QCH_CON_SSMT_D1_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_CSIS_QCH_S1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_CSIS_QCH_S2, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_CSIS_QCH_S1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_CSIS_QCH_S2, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_CSIS_QCH, QCH_CON_SYSREG_CSIS_QCH_ENABLE, QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DISP_CMU_DISP_QCH, QCH_CON_DISP_CMU_DISP_QCH_ENABLE, QCH_CON_DISP_CMU_DISP_QCH_CLOCK_REQ, QCH_CON_DISP_CMU_DISP_QCH_EXPIRE_VAL, QCH_CON_DISP_CMU_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DPUB_QCH, QCH_CON_DPUB_QCH_ENABLE, QCH_CON_DPUB_QCH_CLOCK_REQ, QCH_CON_DPUB_QCH_EXPIRE_VAL, QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_DISP_QCH, QCH_CON_D_TZPC_DISP_QCH_ENABLE, QCH_CON_D_TZPC_DISP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DISP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_DISP_QCH, QCH_CON_GPC_DISP_QCH_ENABLE, QCH_CON_GPC_DISP_QCH_CLOCK_REQ, QCH_CON_GPC_DISP_QCH_EXPIRE_VAL, QCH_CON_GPC_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_DISP_QCH, QCH_CON_SLH_AXI_MI_P_DISP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_DISP_QCH, QCH_CON_SYSREG_DISP_QCH_ENABLE, QCH_CON_SYSREG_DISP_QCH_CLOCK_REQ, QCH_CON_SYSREG_DISP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DNS_QCH_00, QCH_CON_DNS_QCH_00_ENABLE, QCH_CON_DNS_QCH_00_CLOCK_REQ, QCH_CON_DNS_QCH_00_EXPIRE_VAL, QCH_CON_DNS_QCH_00_IGNORE_FORCE_PM_EN), + CLK_QCH(DNS_QCH_01, QCH_CON_DNS_QCH_01_ENABLE, QCH_CON_DNS_QCH_01_CLOCK_REQ, QCH_CON_DNS_QCH_01_EXPIRE_VAL, QCH_CON_DNS_QCH_01_IGNORE_FORCE_PM_EN), + CLK_QCH(DNS_CMU_DNS_QCH, QCH_CON_DNS_CMU_DNS_QCH_ENABLE, QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ, QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL, QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_DNS_QCH, QCH_CON_D_TZPC_DNS_QCH_ENABLE, QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_DNS_QCH, QCH_CON_GPC_DNS_QCH_ENABLE, QCH_CON_GPC_DNS_QCH_CLOCK_REQ, QCH_CON_GPC_DNS_QCH_EXPIRE_VAL, QCH_CON_GPC_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_IPP_DNS_QCH, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_ITP_DNS_QCH, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_IPP_DNS_QCH, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_DNS_ITP_QCH, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_DNS_MCSC_QCH, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_DNS_ITP_QCH, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_DNS_MCSC_QCH, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF2_DNS_MCSC_QCH, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_DNS_GDC_QCH, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_DNS_TNR_QCH, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_IPP_DNS_QCH, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_ITP_DNS_QCH, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_MCSC_DNS_QCH, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LD_PDP_DNS_QCH, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_DNS_QCH, QCH_CON_LH_AXI_SI_D_DNS_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_DNS_QCH, QCH_CON_PPMU_D0_DNS_QCH_ENABLE, QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_DNS_QCH, QCH_CON_PPMU_D1_DNS_QCH_ENABLE, QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D0_DNS_QCH, QCH_CON_QE_D0_DNS_QCH_ENABLE, QCH_CON_QE_D0_DNS_QCH_CLOCK_REQ, QCH_CON_QE_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_QE_D0_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_DNS_QCH, QCH_CON_QE_D1_DNS_QCH_ENABLE, QCH_CON_QE_D1_DNS_QCH_CLOCK_REQ, QCH_CON_QE_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_QE_D1_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_DNS_QCH, QCH_CON_SLH_AXI_MI_P_DNS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DNS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DNS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_DNS_QCH, QCH_CON_SSMT_D0_DNS_QCH_ENABLE, QCH_CON_SSMT_D0_DNS_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_DNS_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_DNS_QCH, QCH_CON_SSMT_D1_DNS_QCH_ENABLE, QCH_CON_SSMT_D1_DNS_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_DNS_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DNS_QCH_S1, QCH_CON_SYSMMU_DNS_QCH_S1_ENABLE, QCH_CON_SYSMMU_DNS_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DNS_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DNS_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DNS_QCH_S2, QCH_CON_SYSMMU_DNS_QCH_S2_ENABLE, QCH_CON_SYSMMU_DNS_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DNS_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DNS_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_DNS_QCH, QCH_CON_SYSREG_DNS_QCH_ENABLE, QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ, QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DPUF_QCH_DPU_DMA, QCH_CON_DPUF_QCH_DPU_DMA_ENABLE, QCH_CON_DPUF_QCH_DPU_DMA_CLOCK_REQ, QCH_CON_DPUF_QCH_DPU_DMA_EXPIRE_VAL, QCH_CON_DPUF_QCH_DPU_DMA_IGNORE_FORCE_PM_EN), + CLK_QCH(DPUF_QCH_DPU_DPP, QCH_CON_DPUF_QCH_DPU_DPP_ENABLE, QCH_CON_DPUF_QCH_DPU_DPP_CLOCK_REQ, QCH_CON_DPUF_QCH_DPU_DPP_EXPIRE_VAL, QCH_CON_DPUF_QCH_DPU_DPP_IGNORE_FORCE_PM_EN), + CLK_QCH(DPU_CMU_DPU_QCH, QCH_CON_DPU_CMU_DPU_QCH_ENABLE, QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_DPU_QCH, QCH_CON_D_TZPC_DPU_QCH_ENABLE, QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_DPU_QCH, QCH_CON_GPC_DPU_QCH_ENABLE, QCH_CON_GPC_DPU_QCH_CLOCK_REQ, QCH_CON_GPC_DPU_QCH_EXPIRE_VAL, QCH_CON_GPC_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_DPU_QCH, QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_DPU_QCH, QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D2_DPU_QCH, QCH_CON_LH_AXI_SI_D2_DPU_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_DPUD0_QCH, QCH_CON_PPMU_DPUD0_QCH_ENABLE, QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_DPUD1_QCH, QCH_CON_PPMU_DPUD1_QCH_ENABLE, QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_DPUD2_QCH, QCH_CON_PPMU_DPUD2_QCH_ENABLE, QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_DPU_QCH, QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_DPU0_QCH, QCH_CON_SSMT_DPU0_QCH_ENABLE, QCH_CON_SSMT_DPU0_QCH_CLOCK_REQ, QCH_CON_SSMT_DPU0_QCH_EXPIRE_VAL, QCH_CON_SSMT_DPU0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_DPU1_QCH, QCH_CON_SSMT_DPU1_QCH_ENABLE, QCH_CON_SSMT_DPU1_QCH_CLOCK_REQ, QCH_CON_SSMT_DPU1_QCH_EXPIRE_VAL, QCH_CON_SSMT_DPU1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_DPU2_QCH, QCH_CON_SSMT_DPU2_QCH_ENABLE, QCH_CON_SSMT_DPU2_QCH_CLOCK_REQ, QCH_CON_SSMT_DPU2_QCH_EXPIRE_VAL, QCH_CON_SSMT_DPU2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD0_QCH_S1, QCH_CON_SYSMMU_DPUD0_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD0_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD0_QCH_S2, QCH_CON_SYSMMU_DPUD0_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD0_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD1_QCH_S1, QCH_CON_SYSMMU_DPUD1_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD1_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD1_QCH_S2, QCH_CON_SYSMMU_DPUD1_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD1_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD2_QCH_S1, QCH_CON_SYSMMU_DPUD2_QCH_S1_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD2_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_DPUD2_QCH_S2, QCH_CON_SYSMMU_DPUD2_QCH_S2_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD2_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_DPU_QCH, QCH_CON_SYSREG_DPU_QCH_ENABLE, QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_EH_QCH, QCH_CON_D_TZPC_EH_QCH_ENABLE, QCH_CON_D_TZPC_EH_QCH_CLOCK_REQ, QCH_CON_D_TZPC_EH_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(EH_QCH, QCH_CON_EH_QCH_ENABLE, QCH_CON_EH_QCH_CLOCK_REQ, QCH_CON_EH_QCH_EXPIRE_VAL, QCH_CON_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(EH_CMU_EH_QCH, QCH_CON_EH_CMU_EH_QCH_ENABLE, QCH_CON_EH_CMU_EH_QCH_CLOCK_REQ, QCH_CON_EH_CMU_EH_QCH_EXPIRE_VAL, QCH_CON_EH_CMU_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_EH_QCH, QCH_CON_GPC_EH_QCH_ENABLE, QCH_CON_GPC_EH_QCH_CLOCK_REQ, QCH_CON_GPC_EH_QCH_EXPIRE_VAL, QCH_CON_GPC_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_EH_QCH, QCH_CON_LH_ACEL_SI_D_EH_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_EH_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_EH_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_EH_QCH, QCH_CON_LH_AXI_MI_IP_EH_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_EH_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_EH_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_EH_CU_QCH, QCH_CON_LH_AXI_MI_P_EH_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_EH_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_EH_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_EH_QCH, QCH_CON_LH_AXI_SI_IP_EH_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_EH_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_EH_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_EH_CU_QCH, QCH_CON_LH_AXI_SI_P_EH_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_EH_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_EH_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_EH_QCH, QCH_CON_PPMU_EH_QCH_ENABLE, QCH_CON_PPMU_EH_QCH_CLOCK_REQ, QCH_CON_PPMU_EH_QCH_EXPIRE_VAL, QCH_CON_PPMU_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_EH_QCH, QCH_CON_QE_EH_QCH_ENABLE, QCH_CON_QE_EH_QCH_CLOCK_REQ, QCH_CON_QE_EH_QCH_EXPIRE_VAL, QCH_CON_QE_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_EH_QCH, QCH_CON_SLH_AXI_MI_P_EH_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_EH_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_EH_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_EH_QCH, QCH_CON_SSMT_EH_QCH_ENABLE, QCH_CON_SSMT_EH_QCH_CLOCK_REQ, QCH_CON_SSMT_EH_QCH_EXPIRE_VAL, QCH_CON_SSMT_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_EH_QCH, QCH_CON_SYSMMU_EH_QCH_ENABLE, QCH_CON_SYSMMU_EH_QCH_CLOCK_REQ, QCH_CON_SYSMMU_EH_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_EH_QCH, QCH_CON_SYSREG_EH_QCH_ENABLE, QCH_CON_SYSREG_EH_QCH_CLOCK_REQ, QCH_CON_SYSREG_EH_QCH_EXPIRE_VAL, QCH_CON_SYSREG_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_EH_QCH, QCH_CON_UASC_EH_QCH_ENABLE, QCH_CON_UASC_EH_QCH_CLOCK_REQ, QCH_CON_UASC_EH_QCH_EXPIRE_VAL, QCH_CON_UASC_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_G2D_QCH, QCH_CON_D_TZPC_G2D_QCH_ENABLE, QCH_CON_D_TZPC_G2D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G2D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(G2D_QCH, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(G2D_CMU_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_G2D_QCH, QCH_CON_GPC_G2D_QCH_ENABLE, QCH_CON_GPC_G2D_QCH_CLOCK_REQ, QCH_CON_GPC_G2D_QCH_EXPIRE_VAL, QCH_CON_GPC_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(JPEG_QCH, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D2_G2D_QCH, QCH_CON_LH_ACEL_SI_D2_G2D_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D2_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_G2D_QCH, QCH_CON_LH_AXI_SI_D0_G2D_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_G2D_QCH, QCH_CON_LH_AXI_SI_D1_G2D_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_G2D_QCH, QCH_CON_PPMU_D0_G2D_QCH_ENABLE, QCH_CON_PPMU_D0_G2D_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_G2D_QCH, QCH_CON_PPMU_D1_G2D_QCH_ENABLE, QCH_CON_PPMU_D1_G2D_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D2_G2D_QCH, QCH_CON_PPMU_D2_G2D_QCH_ENABLE, QCH_CON_PPMU_D2_G2D_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_G2D_QCH, QCH_CON_SLH_AXI_MI_P_G2D_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G2D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_G2D_QCH, QCH_CON_SSMT_D0_G2D_QCH_ENABLE, QCH_CON_SSMT_D0_G2D_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_G2D_QCH, QCH_CON_SSMT_D1_G2D_QCH_ENABLE, QCH_CON_SSMT_D1_G2D_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D2_G2D_QCH, QCH_CON_SSMT_D2_G2D_QCH_ENABLE, QCH_CON_SSMT_D2_G2D_QCH_CLOCK_REQ, QCH_CON_SSMT_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_SSMT_D2_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_G2D_QCH_0, QCH_CON_SYSMMU_D0_G2D_QCH_0_ENABLE, QCH_CON_SYSMMU_D0_G2D_QCH_0_CLOCK_REQ, QCH_CON_SYSMMU_D0_G2D_QCH_0_EXPIRE_VAL, QCH_CON_SYSMMU_D0_G2D_QCH_0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_G2D_QCH_1, QCH_CON_SYSMMU_D0_G2D_QCH_1_ENABLE, QCH_CON_SYSMMU_D0_G2D_QCH_1_CLOCK_REQ, QCH_CON_SYSMMU_D0_G2D_QCH_1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_G2D_QCH_1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_G2D_QCH_0, QCH_CON_SYSMMU_D1_G2D_QCH_0_ENABLE, QCH_CON_SYSMMU_D1_G2D_QCH_0_CLOCK_REQ, QCH_CON_SYSMMU_D1_G2D_QCH_0_EXPIRE_VAL, QCH_CON_SYSMMU_D1_G2D_QCH_0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_G2D_QCH_1, QCH_CON_SYSMMU_D1_G2D_QCH_1_ENABLE, QCH_CON_SYSMMU_D1_G2D_QCH_1_CLOCK_REQ, QCH_CON_SYSMMU_D1_G2D_QCH_1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_G2D_QCH_1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_G2D_QCH_0, QCH_CON_SYSMMU_D2_G2D_QCH_0_ENABLE, QCH_CON_SYSMMU_D2_G2D_QCH_0_CLOCK_REQ, QCH_CON_SYSMMU_D2_G2D_QCH_0_EXPIRE_VAL, QCH_CON_SYSMMU_D2_G2D_QCH_0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_G2D_QCH_1, QCH_CON_SYSMMU_D2_G2D_QCH_1_ENABLE, QCH_CON_SYSMMU_D2_G2D_QCH_1_CLOCK_REQ, QCH_CON_SYSMMU_D2_G2D_QCH_1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_G2D_QCH_1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_G2D_QCH, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_G3AA_QCH, QCH_CON_D_TZPC_G3AA_QCH_ENABLE, QCH_CON_D_TZPC_G3AA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3AA_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(G3AA_QCH, DMYQCH_CON_G3AA_QCH_ENABLE, DMYQCH_CON_G3AA_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(G3AA_CMU_G3AA_QCH, QCH_CON_G3AA_CMU_G3AA_QCH_ENABLE, QCH_CON_G3AA_CMU_G3AA_QCH_CLOCK_REQ, QCH_CON_G3AA_CMU_G3AA_QCH_EXPIRE_VAL, QCH_CON_G3AA_CMU_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_G3AA_QCH, QCH_CON_GPC_G3AA_QCH_ENABLE, QCH_CON_GPC_G3AA_QCH_CLOCK_REQ, QCH_CON_GPC_G3AA_QCH_EXPIRE_VAL, QCH_CON_GPC_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_PDP_G3AA_QCH, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_PDP_G3AA_QCH, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF2_PDP_G3AA_QCH, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_YOTF0_PDP_G3AA_QCH, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_YOTF1_PDP_G3AA_QCH, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_G3AA_QCH, QCH_CON_LH_AXI_SI_D_G3AA_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_G3AA_QCH, QCH_CON_PPMU_G3AA_QCH_ENABLE, QCH_CON_PPMU_G3AA_QCH_CLOCK_REQ, QCH_CON_PPMU_G3AA_QCH_EXPIRE_VAL, QCH_CON_PPMU_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_G3AA_QCH, QCH_CON_SLH_AXI_MI_P_G3AA_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G3AA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G3AA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_G3AA_QCH, QCH_CON_SSMT_G3AA_QCH_ENABLE, QCH_CON_SSMT_G3AA_QCH_CLOCK_REQ, QCH_CON_SSMT_G3AA_QCH_EXPIRE_VAL, QCH_CON_SSMT_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3AA_QCH_S1, QCH_CON_SYSMMU_G3AA_QCH_S1_ENABLE, QCH_CON_SYSMMU_G3AA_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_G3AA_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_G3AA_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3AA_QCH_S2, QCH_CON_SYSMMU_G3AA_QCH_S2_ENABLE, QCH_CON_SYSMMU_G3AA_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_G3AA_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_G3AA_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_G3AA_QCH, QCH_CON_SYSREG_G3AA_QCH_ENABLE, QCH_CON_SYSREG_G3AA_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3AA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADD_APBIF_G3D_QCH, QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL, QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADD_G3D_QCH, DMYQCH_CON_ADD_G3D_QCH_ENABLE, DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADM_AHB_G_GPU_QCH, QCH_CON_ADM_AHB_G_GPU_QCH_ENABLE, QCH_CON_ADM_AHB_G_GPU_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_G_GPU_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_G_GPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ASB_G3D_QCH_LH_D0_G3D, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN), + CLK_QCH(ASB_G3D_QCH_LH_D1_G3D, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN), + CLK_QCH(ASB_G3D_QCH_LH_D2_G3D, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN), + CLK_QCH(ASB_G3D_QCH_LH_D3_G3D, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN), + CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_G3D_QCH, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_G3D_QCH, QCH_CON_GPC_G3D_QCH_ENABLE, QCH_CON_GPC_G3D_QCH_CLOCK_REQ, QCH_CON_GPC_G3D_QCH_EXPIRE_VAL, QCH_CON_GPC_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPU_QCH, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_G3D_QCH, QCH_CON_LH_AXI_MI_IP_G3D_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_G3D_CU_QCH, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_G3D_QCH, QCH_CON_LH_AXI_SI_IP_G3D_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_G3D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_G3D_CU_QCH, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_G3D_DD_QCH, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_G3D_QCH, QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_G3D_QCH, QCH_CON_UASC_G3D_QCH_ENABLE, QCH_CON_UASC_G3D_QCH_CLOCK_REQ, QCH_CON_UASC_G3D_QCH_EXPIRE_VAL, QCH_CON_UASC_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_GDC_QCH, QCH_CON_D_TZPC_GDC_QCH_ENABLE, QCH_CON_D_TZPC_GDC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_GDC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GDC0_QCH_CLK, QCH_CON_GDC0_QCH_CLK_ENABLE, QCH_CON_GDC0_QCH_CLK_CLOCK_REQ, QCH_CON_GDC0_QCH_CLK_EXPIRE_VAL, QCH_CON_GDC0_QCH_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(GDC0_QCH_C2CLK, QCH_CON_GDC0_QCH_C2CLK_ENABLE, QCH_CON_GDC0_QCH_C2CLK_CLOCK_REQ, QCH_CON_GDC0_QCH_C2CLK_EXPIRE_VAL, QCH_CON_GDC0_QCH_C2CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(GDC1_QCH_CLK, QCH_CON_GDC1_QCH_CLK_ENABLE, QCH_CON_GDC1_QCH_CLK_CLOCK_REQ, QCH_CON_GDC1_QCH_CLK_EXPIRE_VAL, QCH_CON_GDC1_QCH_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(GDC1_QCH_C2CLK, QCH_CON_GDC1_QCH_C2CLK_ENABLE, QCH_CON_GDC1_QCH_C2CLK_CLOCK_REQ, QCH_CON_GDC1_QCH_C2CLK_EXPIRE_VAL, QCH_CON_GDC1_QCH_C2CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(GDC_CMU_GDC_QCH, QCH_CON_GDC_CMU_GDC_QCH_ENABLE, QCH_CON_GDC_CMU_GDC_QCH_CLOCK_REQ, QCH_CON_GDC_CMU_GDC_QCH_EXPIRE_VAL, QCH_CON_GDC_CMU_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_GDC_QCH, QCH_CON_GPC_GDC_QCH_ENABLE, QCH_CON_GPC_GDC_QCH_CLOCK_REQ, QCH_CON_GPC_GDC_QCH_EXPIRE_VAL, QCH_CON_GPC_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_I_GDC0_GDC1_QCH, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_ENABLE, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_I_GDC1_SCSC_QCH, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_DNS_GDC_QCH, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_TNR_GDC_QCH, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_TNR_GDC_QCH, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_I_GDC0_GDC1_QCH, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_ENABLE, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_I_GDC1_SCSC_QCH, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_GDC_MCSC_QCH, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_ID_SCSC_GDC1_QCH, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_GDC_QCH, QCH_CON_LH_AXI_SI_D0_GDC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_GDC_QCH, QCH_CON_LH_AXI_SI_D1_GDC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D2_GDC_QCH, QCH_CON_LH_AXI_SI_D2_GDC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_ID_SCSC_GDC1_QCH, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_GDC_QCH, QCH_CON_PPMU_D0_GDC_QCH_ENABLE, QCH_CON_PPMU_D0_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_SCSC_QCH, QCH_CON_PPMU_D0_SCSC_QCH_ENABLE, QCH_CON_PPMU_D0_SCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_SCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_GDC_QCH, QCH_CON_PPMU_D1_GDC_QCH_ENABLE, QCH_CON_PPMU_D1_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_SCSC_QCH, QCH_CON_PPMU_D1_SCSC_QCH_ENABLE, QCH_CON_PPMU_D1_SCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_SCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D2_GDC_QCH, QCH_CON_PPMU_D2_GDC_QCH_ENABLE, QCH_CON_PPMU_D2_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D2_SCSC_QCH, QCH_CON_PPMU_D2_SCSC_QCH_ENABLE, QCH_CON_PPMU_D2_SCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_SCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D3_GDC_QCH, QCH_CON_PPMU_D3_GDC_QCH_ENABLE, QCH_CON_PPMU_D3_GDC_QCH_CLOCK_REQ, QCH_CON_PPMU_D3_GDC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D3_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D0_GDC_QCH, QCH_CON_QE_D0_GDC_QCH_ENABLE, QCH_CON_QE_D0_GDC_QCH_CLOCK_REQ, QCH_CON_QE_D0_GDC_QCH_EXPIRE_VAL, QCH_CON_QE_D0_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D0_SCSC_QCH, QCH_CON_QE_D0_SCSC_QCH_ENABLE, QCH_CON_QE_D0_SCSC_QCH_CLOCK_REQ, QCH_CON_QE_D0_SCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D0_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_GDC_QCH, QCH_CON_QE_D1_GDC_QCH_ENABLE, QCH_CON_QE_D1_GDC_QCH_CLOCK_REQ, QCH_CON_QE_D1_GDC_QCH_EXPIRE_VAL, QCH_CON_QE_D1_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_SCSC_QCH, QCH_CON_QE_D1_SCSC_QCH_ENABLE, QCH_CON_QE_D1_SCSC_QCH_CLOCK_REQ, QCH_CON_QE_D1_SCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D1_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D2_GDC_QCH, QCH_CON_QE_D2_GDC_QCH_ENABLE, QCH_CON_QE_D2_GDC_QCH_CLOCK_REQ, QCH_CON_QE_D2_GDC_QCH_EXPIRE_VAL, QCH_CON_QE_D2_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D2_SCSC_QCH, QCH_CON_QE_D2_SCSC_QCH_ENABLE, QCH_CON_QE_D2_SCSC_QCH_CLOCK_REQ, QCH_CON_QE_D2_SCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D2_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D3_GDC_QCH, QCH_CON_QE_D3_GDC_QCH_ENABLE, QCH_CON_QE_D3_GDC_QCH_CLOCK_REQ, QCH_CON_QE_D3_GDC_QCH_EXPIRE_VAL, QCH_CON_QE_D3_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SCSC_QCH_CLK, QCH_CON_SCSC_QCH_CLK_ENABLE, QCH_CON_SCSC_QCH_CLK_CLOCK_REQ, QCH_CON_SCSC_QCH_CLK_EXPIRE_VAL, QCH_CON_SCSC_QCH_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(SCSC_QCH_C2CLK, QCH_CON_SCSC_QCH_C2CLK_ENABLE, QCH_CON_SCSC_QCH_C2CLK_CLOCK_REQ, QCH_CON_SCSC_QCH_C2CLK_EXPIRE_VAL, QCH_CON_SCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_GDC_QCH, QCH_CON_SLH_AXI_MI_P_GDC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_GDC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_GDC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_GDC_QCH, QCH_CON_SSMT_D0_GDC_QCH_ENABLE, QCH_CON_SSMT_D0_GDC_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_GDC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_SCSC_QCH, QCH_CON_SSMT_D0_SCSC_QCH_ENABLE, QCH_CON_SSMT_D0_SCSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_SCSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_GDC_QCH, QCH_CON_SSMT_D1_GDC_QCH_ENABLE, QCH_CON_SSMT_D1_GDC_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_GDC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_SCSC_QCH, QCH_CON_SSMT_D1_SCSC_QCH_ENABLE, QCH_CON_SSMT_D1_SCSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_SCSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D2_GDC_QCH, QCH_CON_SSMT_D2_GDC_QCH_ENABLE, QCH_CON_SSMT_D2_GDC_QCH_CLOCK_REQ, QCH_CON_SSMT_D2_GDC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D2_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D2_SCSC_QCH, QCH_CON_SSMT_D2_SCSC_QCH_ENABLE, QCH_CON_SSMT_D2_SCSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D2_SCSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D2_SCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D3_GDC_QCH, QCH_CON_SSMT_D3_GDC_QCH_ENABLE, QCH_CON_SSMT_D3_GDC_QCH_CLOCK_REQ, QCH_CON_SSMT_D3_GDC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D3_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_GDC_QCH_S1, QCH_CON_SYSMMU_D0_GDC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_GDC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_GDC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_GDC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_GDC_QCH_S2, QCH_CON_SYSMMU_D0_GDC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_GDC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_GDC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_GDC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_GDC_QCH_S1, QCH_CON_SYSMMU_D1_GDC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_GDC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_GDC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_GDC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_GDC_QCH_S2, QCH_CON_SYSMMU_D1_GDC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_GDC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_GDC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_GDC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_GDC_QCH_S1, QCH_CON_SYSMMU_D2_GDC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_GDC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_GDC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_GDC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_GDC_QCH_S2, QCH_CON_SYSMMU_D2_GDC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_GDC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_GDC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_GDC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_GDC_QCH, QCH_CON_SYSREG_GDC_QCH_ENABLE, QCH_CON_SYSREG_GDC_QCH_CLOCK_REQ, QCH_CON_SYSREG_GDC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(AD_APB_SYSMMU_GSACORE_NS_QCH, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_ENABLE, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BAAW_GSACORE_QCH, QCH_CON_BAAW_GSACORE_QCH_ENABLE, QCH_CON_BAAW_GSACORE_QCH_CLOCK_REQ, QCH_CON_BAAW_GSACORE_QCH_EXPIRE_VAL, QCH_CON_BAAW_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CA32_GSACORE_QCH, DMYQCH_CON_CA32_GSACORE_QCH_ENABLE, DMYQCH_CON_CA32_GSACORE_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DMA_GSACORE_QCH, QCH_CON_DMA_GSACORE_QCH_ENABLE, QCH_CON_DMA_GSACORE_QCH_CLOCK_REQ, QCH_CON_DMA_GSACORE_QCH_EXPIRE_VAL, QCH_CON_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GIC_GSACORE_QCH, QCH_CON_GIC_GSACORE_QCH_ENABLE, QCH_CON_GIC_GSACORE_QCH_CLOCK_REQ, QCH_CON_GIC_GSACORE_QCH_EXPIRE_VAL, QCH_CON_GIC_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_GSACORE_QCH, QCH_CON_GPIO_GSACORE_QCH_ENABLE, QCH_CON_GPIO_GSACORE_QCH_CLOCK_REQ, QCH_CON_GPIO_GSACORE_QCH_EXPIRE_VAL, QCH_CON_GPIO_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GSACORE_CMU_GSACORE_QCH, QCH_CON_GSACORE_CMU_GSACORE_QCH_ENABLE, QCH_CON_GSACORE_CMU_GSACORE_QCH_CLOCK_REQ, QCH_CON_GSACORE_CMU_GSACORE_QCH_EXPIRE_VAL, QCH_CON_GSACORE_CMU_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(INTMEM_GSACORE_QCH, QCH_CON_INTMEM_GSACORE_QCH_ENABLE, QCH_CON_INTMEM_GSACORE_QCH_CLOCK_REQ, QCH_CON_INTMEM_GSACORE_QCH_EXPIRE_VAL, QCH_CON_INTMEM_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(KDN_GSACORE_QCH, QCH_CON_KDN_GSACORE_QCH_ENABLE, QCH_CON_KDN_GSACORE_QCH_CLOCK_REQ, QCH_CON_KDN_GSACORE_QCH_EXPIRE_VAL, QCH_CON_KDN_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_I_CA32_GIC_QCH, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_ENABLE, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_I_GIC_CA32_QCH, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_ENABLE, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_I_CA32_GIC_QCH, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_ENABLE, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_I_GIC_CA32_QCH, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_ENABLE, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_GSA_CPUCL0_QCH, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_GME_QCH, QCH_CON_LH_AXI_MI_IP_GME_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_GME_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_GME_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_GME_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_I_DAP_GSA_QCH, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_ENABLE, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_GSA_QCH, QCH_CON_LH_AXI_SI_D_GSA_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_GME_QCH, QCH_CON_LH_AXI_SI_IP_GME_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_GME_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_GME_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_GME_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_GSA_QCH, QCH_CON_LH_AXI_SI_IP_GSA_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(OTP_CON_GSACORE_QCH, QCH_CON_OTP_CON_GSACORE_QCH_ENABLE, QCH_CON_OTP_CON_GSACORE_QCH_CLOCK_REQ, QCH_CON_OTP_CON_GSACORE_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_GSACORE_QCH, QCH_CON_PPMU_GSACORE_QCH_ENABLE, QCH_CON_PPMU_GSACORE_QCH_CLOCK_REQ, QCH_CON_PPMU_GSACORE_QCH_EXPIRE_VAL, QCH_CON_PPMU_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PUF_GSACORE_QCH, DMYQCH_CON_PUF_GSACORE_QCH_ENABLE, DMYQCH_CON_PUF_GSACORE_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PUF_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_CA32_GSACORE_QCH, QCH_CON_QE_CA32_GSACORE_QCH_ENABLE, QCH_CON_QE_CA32_GSACORE_QCH_CLOCK_REQ, QCH_CON_QE_CA32_GSACORE_QCH_EXPIRE_VAL, QCH_CON_QE_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_DMA_GSACORE_QCH, QCH_CON_QE_DMA_GSACORE_QCH_ENABLE, QCH_CON_QE_DMA_GSACORE_QCH_CLOCK_REQ, QCH_CON_QE_DMA_GSACORE_QCH_EXPIRE_VAL, QCH_CON_QE_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_SSS_GSACORE_QCH, QCH_CON_QE_SSS_GSACORE_QCH_ENABLE, QCH_CON_QE_SSS_GSACORE_QCH_CLOCK_REQ, QCH_CON_QE_SSS_GSACORE_QCH_EXPIRE_VAL, QCH_CON_QE_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RESETMON_GSACORE_QCH, QCH_CON_RESETMON_GSACORE_QCH_ENABLE, QCH_CON_RESETMON_GSACORE_QCH_CLOCK_REQ, QCH_CON_RESETMON_GSACORE_QCH_EXPIRE_VAL, QCH_CON_RESETMON_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_SSS_ARESETN_QCH, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_SSS_HRESETN_QCH, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_SSS_PORRESETN_QCH, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SPI_FPS_GSACORE_QCH, QCH_CON_SPI_FPS_GSACORE_QCH_ENABLE, QCH_CON_SPI_FPS_GSACORE_QCH_CLOCK_REQ, QCH_CON_SPI_FPS_GSACORE_QCH_EXPIRE_VAL, QCH_CON_SPI_FPS_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SPI_GSC_GSACORE_QCH, QCH_CON_SPI_GSC_GSACORE_QCH_ENABLE, QCH_CON_SPI_GSC_GSACORE_QCH_CLOCK_REQ, QCH_CON_SPI_GSC_GSACORE_QCH_EXPIRE_VAL, QCH_CON_SPI_GSC_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_GSACORE_QCH, QCH_CON_SSMT_GSACORE_QCH_ENABLE, QCH_CON_SSMT_GSACORE_QCH_CLOCK_REQ, QCH_CON_SSMT_GSACORE_QCH_EXPIRE_VAL, QCH_CON_SSMT_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSS_GSACORE_QCH, QCH_CON_SSS_GSACORE_QCH_ENABLE, QCH_CON_SSS_GSACORE_QCH_CLOCK_REQ, QCH_CON_SSS_GSACORE_QCH_EXPIRE_VAL, QCH_CON_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_GSACORE_QCH_S1, QCH_CON_SYSMMU_GSACORE_QCH_S1_ENABLE, QCH_CON_SYSMMU_GSACORE_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_GSACORE_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_GSACORE_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_GSACORE_QCH_S2, QCH_CON_SYSMMU_GSACORE_QCH_S2_ENABLE, QCH_CON_SYSMMU_GSACORE_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_GSACORE_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_GSACORE_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_GSACORE_QCH, QCH_CON_SYSREG_GSACORE_QCH_ENABLE, QCH_CON_SYSREG_GSACORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_GSACORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UART_GSACORE_QCH, QCH_CON_UART_GSACORE_QCH_ENABLE, QCH_CON_UART_GSACORE_QCH_CLOCK_REQ, QCH_CON_UART_GSACORE_QCH_EXPIRE_VAL, QCH_CON_UART_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(WDT_GSACORE_QCH, QCH_CON_WDT_GSACORE_QCH_ENABLE, QCH_CON_WDT_GSACORE_QCH_CLOCK_REQ, QCH_CON_WDT_GSACORE_QCH_EXPIRE_VAL, QCH_CON_WDT_GSACORE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UDAP_SSS_AHB_ASYNC_QCH, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_ENABLE, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_CLOCK_REQ, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_EXPIRE_VAL, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UGME_QCH, QCH_CON_UGME_QCH_ENABLE, QCH_CON_UGME_QCH_CLOCK_REQ, QCH_CON_UGME_QCH_EXPIRE_VAL, QCH_CON_UGME_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBIF_GPIO_GSACTRL_QCH, QCH_CON_APBIF_GPIO_GSACTRL_QCH_ENABLE, QCH_CON_APBIF_GPIO_GSACTRL_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DAP_GSACTRL_QCH, DMYQCH_CON_DAP_GSACTRL_QCH_ENABLE, DMYQCH_CON_DAP_GSACTRL_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DAP_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_GSACTRL_QCH, QCH_CON_GPC_GSACTRL_QCH_ENABLE, QCH_CON_GPC_GSACTRL_QCH_CLOCK_REQ, QCH_CON_GPC_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_GPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GSACTRL_CMU_GSACTRL_QCH, QCH_CON_GSACTRL_CMU_GSACTRL_QCH_ENABLE, QCH_CON_GSACTRL_CMU_GSACTRL_QCH_CLOCK_REQ, QCH_CON_GSACTRL_CMU_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_GSACTRL_CMU_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(INTMEM_GSACTRL_QCH, QCH_CON_INTMEM_GSACTRL_QCH_ENABLE, QCH_CON_INTMEM_GSACTRL_QCH_CLOCK_REQ, QCH_CON_INTMEM_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_INTMEM_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_IP_GSA_QCH, QCH_CON_LH_AXI_MI_IP_GSA_QCH_ENABLE, QCH_CON_LH_AXI_MI_IP_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_IP_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_IP_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_GSA_CU_QCH, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_I_DAP_GSA_QCH, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_ENABLE, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_GSA_CU_QCH, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_GSA2AOC_QCH, QCH_CON_MAILBOX_GSA2AOC_QCH_ENABLE, QCH_CON_MAILBOX_GSA2AOC_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GSA2AOC_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GSA2AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_GSA2AUR_QCH, QCH_CON_MAILBOX_GSA2AUR_QCH_ENABLE, QCH_CON_MAILBOX_GSA2AUR_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GSA2AUR_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GSA2AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_GSA2NONTZ_QCH, QCH_CON_MAILBOX_GSA2NONTZ_QCH_ENABLE, QCH_CON_MAILBOX_GSA2NONTZ_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GSA2NONTZ_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GSA2NONTZ_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_GSA2TPU_QCH, QCH_CON_MAILBOX_GSA2TPU_QCH_ENABLE, QCH_CON_MAILBOX_GSA2TPU_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GSA2TPU_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GSA2TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MAILBOX_GSA2TZ_QCH, QCH_CON_MAILBOX_GSA2TZ_QCH_ENABLE, QCH_CON_MAILBOX_GSA2TZ_QCH_CLOCK_REQ, QCH_CON_MAILBOX_GSA2TZ_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_GSA2TZ_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PMU_GSA_QCH, QCH_CON_PMU_GSA_QCH_ENABLE, QCH_CON_PMU_GSA_QCH_CLOCK_REQ, QCH_CON_PMU_GSA_QCH_EXPIRE_VAL, QCH_CON_PMU_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SECJTAG_GSACTRL_QCH, QCH_CON_SECJTAG_GSACTRL_QCH_ENABLE, QCH_CON_SECJTAG_GSACTRL_QCH_CLOCK_REQ, QCH_CON_SECJTAG_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_GSA_QCH, QCH_CON_SLH_AXI_MI_P_GSA_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_GSA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_GSA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_GSACTRL_QCH, QCH_CON_SYSREG_GSACTRL_QCH_ENABLE, QCH_CON_SYSREG_GSACTRL_QCH_CLOCK_REQ, QCH_CON_SYSREG_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_SYSREG_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_GSACTRLEXT_QCH, QCH_CON_SYSREG_GSACTRLEXT_QCH_ENABLE, QCH_CON_SYSREG_GSACTRLEXT_QCH_CLOCK_REQ, QCH_CON_SYSREG_GSACTRLEXT_QCH_EXPIRE_VAL, QCH_CON_SYSREG_GSACTRLEXT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TIMER_GSACTRL_QCH, QCH_CON_TIMER_GSACTRL_QCH_ENABLE, QCH_CON_TIMER_GSACTRL_QCH_CLOCK_REQ, QCH_CON_TIMER_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_TIMER_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TZPC_GSACTRL_QCH, QCH_CON_TZPC_GSACTRL_QCH_ENABLE, QCH_CON_TZPC_GSACTRL_QCH_CLOCK_REQ, QCH_CON_TZPC_GSACTRL_QCH_EXPIRE_VAL, QCH_CON_TZPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DP_LINK_QCH_PCLK, QCH_CON_DP_LINK_QCH_PCLK_ENABLE, QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(DP_LINK_QCH_GTC_CLK, QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_HSI0_QCH, QCH_CON_D_TZPC_HSI0_QCH_ENABLE, QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ETR_MIU_QCH_ACLK, QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN), + CLK_QCH(ETR_MIU_QCH_PCLK, QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_HSI0_QCH, QCH_CON_GPC_HSI0_QCH_ENABLE, QCH_CON_GPC_HSI0_QCH_CLOCK_REQ, QCH_CON_GPC_HSI0_QCH_EXPIRE_VAL, QCH_CON_GPC_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(HSI0_CMU_HSI0_QCH, QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL, QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_HSI0_QCH, QCH_CON_LH_ACEL_SI_D_HSI0_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_HSI0_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_ETR_HSI0_CU_QCH, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LP1_AOC_CU_QCH, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI0_CU_QCH, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_HSI0_AOC_QCH, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_ETR_HSI0_CU_QCH, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LP1_AOC_CU_QCH, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI0_CU_QCH, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_HSI0_AOC_QCH, QCH_CON_PPMU_HSI0_AOC_QCH_ENABLE, QCH_CON_PPMU_HSI0_AOC_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI0_AOC_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_HSI0_NOCL1B_QCH, QCH_CON_PPMU_HSI0_NOCL1B_QCH_ENABLE, QCH_CON_PPMU_HSI0_NOCL1B_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI0_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI0_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LG_ETR_HSI0_QCH, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LP1_AOC_QCH, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_HSI0_QCH, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_USB_QCH, QCH_CON_SSMT_USB_QCH_ENABLE, QCH_CON_SSMT_USB_QCH_CLOCK_REQ, QCH_CON_SSMT_USB_QCH_EXPIRE_VAL, QCH_CON_SSMT_USB_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_USB_QCH_S2, QCH_CON_SYSMMU_USB_QCH_S2_ENABLE, QCH_CON_SYSMMU_USB_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_USB_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_USB_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_USB_QCH_S1, QCH_CON_SYSMMU_USB_QCH_S1_ENABLE, QCH_CON_SYSMMU_USB_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_USB_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_USB_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_HSI0_QCH, QCH_CON_SYSREG_HSI0_QCH_ENABLE, QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_HSI0_CTRL_QCH, QCH_CON_UASC_HSI0_CTRL_QCH_ENABLE, QCH_CON_UASC_HSI0_CTRL_QCH_CLOCK_REQ, QCH_CON_UASC_HSI0_CTRL_QCH_EXPIRE_VAL, QCH_CON_UASC_HSI0_CTRL_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_HSI0_LINK_QCH, QCH_CON_UASC_HSI0_LINK_QCH_ENABLE, QCH_CON_UASC_HSI0_LINK_QCH_CLOCK_REQ, QCH_CON_UASC_HSI0_LINK_QCH_EXPIRE_VAL, QCH_CON_UASC_HSI0_LINK_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_REF, DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_SLV_CTRL, QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_SLV_LINK, QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_APB, QCH_CON_USB31DRD_QCH_APB_ENABLE, QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_PCS, QCH_CON_USB31DRD_QCH_PCS_ENABLE, QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH_DBG, QCH_CON_USB31DRD_QCH_DBG_ENABLE, QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ, QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN), + CLK_QCH(USB31DRD_QCH, DMYQCH_CON_USB31DRD_QCH_ENABLE, DMYQCH_CON_USB31DRD_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USB31DRD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_HSI1_QCH, QCH_CON_D_TZPC_HSI1_QCH_ENABLE, QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_HSI1_QCH, QCH_CON_GPC_HSI1_QCH_ENABLE, QCH_CON_GPC_HSI1_QCH_CLOCK_REQ, QCH_CON_GPC_HSI1_QCH_EXPIRE_VAL, QCH_CON_GPC_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_HSI1_QCH, QCH_CON_GPIO_HSI1_QCH_ENABLE, QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(HSI1_CMU_HSI1_QCH, QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL, QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_HSI1_QCH, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI1_CU_QCH, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI1_CU_QCH, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_DBG_1, QCH_CON_PCIE_GEN4_0_QCH_DBG_1_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_DBG_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_DBG_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_DBG_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_AXI_1, QCH_CON_PCIE_GEN4_0_QCH_AXI_1_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_AXI_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_AXI_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_AXI_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_APB_1, QCH_CON_PCIE_GEN4_0_QCH_APB_1_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_APB_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_APB_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_APB_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_SCLK_1, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_ENABLE, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_PCS_APB, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_PMA_APB, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_DBG_2, QCH_CON_PCIE_GEN4_0_QCH_DBG_2_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_DBG_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_DBG_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_DBG_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_AXI_2, QCH_CON_PCIE_GEN4_0_QCH_AXI_2_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_AXI_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_AXI_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_AXI_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_APB_2, QCH_CON_PCIE_GEN4_0_QCH_APB_2_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_APB_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_APB_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_APB_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH_UDBG, QCH_CON_PCIE_GEN4_0_QCH_UDBG_ENABLE, QCH_CON_PCIE_GEN4_0_QCH_UDBG_CLOCK_REQ, QCH_CON_PCIE_GEN4_0_QCH_UDBG_EXPIRE_VAL, QCH_CON_PCIE_GEN4_0_QCH_UDBG_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_0_QCH, DMYQCH_CON_PCIE_GEN4_0_QCH_ENABLE, DMYQCH_CON_PCIE_GEN4_0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN4_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_IA_GEN4A_0_QCH, QCH_CON_PCIE_IA_GEN4A_0_QCH_ENABLE, QCH_CON_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_IA_GEN4B_0_QCH, QCH_CON_PCIE_IA_GEN4B_0_QCH_ENABLE, QCH_CON_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_HSI1_QCH, QCH_CON_PPMU_HSI1_QCH_ENABLE, QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PCIE_GEN4A_HSI1_QCH, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_ENABLE, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_CLOCK_REQ, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_EXPIRE_VAL, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PCIE_GEN4B_HSI1_QCH, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_ENABLE, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_CLOCK_REQ, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_EXPIRE_VAL, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_HSI1_QCH, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_HSI1_QCH, QCH_CON_SSMT_HSI1_QCH_ENABLE, QCH_CON_SSMT_HSI1_QCH_CLOCK_REQ, QCH_CON_SSMT_HSI1_QCH_EXPIRE_VAL, QCH_CON_SSMT_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PCIE_IA_GEN4A_0_QCH, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_ENABLE, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PCIE_IA_GEN4B_0_QCH, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_ENABLE, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_HSI1_QCH_S2, QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE, QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_HSI1_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_HSI1_QCH_S1, QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE, QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_HSI1_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_HSI1_QCH, QCH_CON_SYSREG_HSI1_QCH_ENABLE, QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4A_DBI_0_QCH, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4A_SLV_0_QCH, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4B_DBI_0_QCH, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4B_SLV_0_QCH, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_HSI2_QCH, QCH_CON_D_TZPC_HSI2_QCH_ENABLE, QCH_CON_D_TZPC_HSI2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_HSI2_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_HSI2_QCH, QCH_CON_GPC_HSI2_QCH_ENABLE, QCH_CON_GPC_HSI2_QCH_CLOCK_REQ, QCH_CON_GPC_HSI2_QCH_EXPIRE_VAL, QCH_CON_GPC_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_HSI2_QCH, QCH_CON_GPIO_HSI2_QCH_ENABLE, QCH_CON_GPIO_HSI2_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI2_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_HSI2UFS_QCH, QCH_CON_GPIO_HSI2UFS_QCH_ENABLE, QCH_CON_GPIO_HSI2UFS_QCH_CLOCK_REQ, QCH_CON_GPIO_HSI2UFS_QCH_EXPIRE_VAL, QCH_CON_GPIO_HSI2UFS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(HSI2_CMU_HSI2_QCH, QCH_CON_HSI2_CMU_HSI2_QCH_ENABLE, QCH_CON_HSI2_CMU_HSI2_QCH_CLOCK_REQ, QCH_CON_HSI2_CMU_HSI2_QCH_EXPIRE_VAL, QCH_CON_HSI2_CMU_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_HSI2_QCH, QCH_CON_LH_ACEL_SI_D_HSI2_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_HSI2_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_HSI2_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI2_CU_QCH, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI2_CU_QCH, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_AXI_1, QCH_CON_PCIE_GEN4_1_QCH_AXI_1_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_AXI_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_AXI_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_AXI_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_APB_1, QCH_CON_PCIE_GEN4_1_QCH_APB_1_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_APB_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_APB_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_APB_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_DBG_1, QCH_CON_PCIE_GEN4_1_QCH_DBG_1_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_DBG_1_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_DBG_1_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_DBG_1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_PCS_APB, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_REF0, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_ENABLE, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_PMA_APB, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_AXI_2, QCH_CON_PCIE_GEN4_1_QCH_AXI_2_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_AXI_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_AXI_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_AXI_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_DBG_2, QCH_CON_PCIE_GEN4_1_QCH_DBG_2_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_DBG_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_DBG_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_DBG_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_APB_2, QCH_CON_PCIE_GEN4_1_QCH_APB_2_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_APB_2_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_APB_2_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_APB_2_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_UDBG, QCH_CON_PCIE_GEN4_1_QCH_UDBG_ENABLE, QCH_CON_PCIE_GEN4_1_QCH_UDBG_CLOCK_REQ, QCH_CON_PCIE_GEN4_1_QCH_UDBG_EXPIRE_VAL, QCH_CON_PCIE_GEN4_1_QCH_UDBG_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_GEN4_1_QCH_REF1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_ENABLE, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_IA_GEN4A_1_QCH, QCH_CON_PCIE_IA_GEN4A_1_QCH_ENABLE, QCH_CON_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PCIE_IA_GEN4B_1_QCH, QCH_CON_PCIE_IA_GEN4B_1_QCH_ENABLE, QCH_CON_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_HSI2_QCH, QCH_CON_PPMU_HSI2_QCH_ENABLE, QCH_CON_PPMU_HSI2_QCH_CLOCK_REQ, QCH_CON_PPMU_HSI2_QCH_EXPIRE_VAL, QCH_CON_PPMU_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_MMC_CARD_HSI2_QCH, QCH_CON_QE_MMC_CARD_HSI2_QCH_ENABLE, QCH_CON_QE_MMC_CARD_HSI2_QCH_CLOCK_REQ, QCH_CON_QE_MMC_CARD_HSI2_QCH_EXPIRE_VAL, QCH_CON_QE_MMC_CARD_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PCIE_GEN4A_HSI2_QCH, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_ENABLE, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_CLOCK_REQ, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_EXPIRE_VAL, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PCIE_GEN4B_HSI2_QCH, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_ENABLE, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_CLOCK_REQ, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_EXPIRE_VAL, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_UFS_EMBD_HSI2_QCH, QCH_CON_QE_UFS_EMBD_HSI2_QCH_ENABLE, QCH_CON_QE_UFS_EMBD_HSI2_QCH_CLOCK_REQ, QCH_CON_QE_UFS_EMBD_HSI2_QCH_EXPIRE_VAL, QCH_CON_QE_UFS_EMBD_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_HSI2_QCH, QCH_CON_SLH_AXI_MI_P_HSI2_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_HSI2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_HSI2_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_HSI2_QCH, QCH_CON_SSMT_HSI2_QCH_ENABLE, QCH_CON_SSMT_HSI2_QCH_CLOCK_REQ, QCH_CON_SSMT_HSI2_QCH_EXPIRE_VAL, QCH_CON_SSMT_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PCIE_IA_GEN4A_1_QCH, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_ENABLE, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PCIE_IA_GEN4B_1_QCH, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_ENABLE, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_HSI2_QCH_S2, QCH_CON_SYSMMU_HSI2_QCH_S2_ENABLE, QCH_CON_SYSMMU_HSI2_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_HSI2_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_HSI2_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_HSI2_QCH_S1, QCH_CON_SYSMMU_HSI2_QCH_S1_ENABLE, QCH_CON_SYSMMU_HSI2_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_HSI2_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_HSI2_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_HSI2_QCH, QCH_CON_SYSREG_HSI2_QCH_ENABLE, QCH_CON_SYSREG_HSI2_QCH_CLOCK_REQ, QCH_CON_SYSREG_HSI2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4A_DBI_1_QCH, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4A_SLV_1_QCH, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4B_DBI_1_QCH, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UASC_PCIE_GEN4B_SLV_1_QCH, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_ENABLE, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_CLOCK_REQ, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_EXPIRE_VAL, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_IPP_QCH, QCH_CON_D_TZPC_IPP_QCH_ENABLE, QCH_CON_D_TZPC_IPP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_IPP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_IPP_QCH, QCH_CON_GPC_IPP_QCH_ENABLE, QCH_CON_GPC_IPP_QCH_CLOCK_REQ, QCH_CON_GPC_IPP_QCH_EXPIRE_VAL, QCH_CON_GPC_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(IPP_CMU_IPP_QCH, QCH_CON_IPP_CMU_IPP_QCH_ENABLE, QCH_CON_IPP_CMU_IPP_QCH_CLOCK_REQ, QCH_CON_IPP_CMU_IPP_QCH_EXPIRE_VAL, QCH_CON_IPP_CMU_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_PDP_IPP_QCH, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_PDP_IPP_QCH, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF2_PDP_IPP_QCH, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_PDP_IPP_QCH, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_IPP_DNS_QCH, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_SOTF0_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_SOTF1_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_SOTF2_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_IPP_DNS_QCH, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D_IPP_QCH, QCH_CON_LH_AXI_SI_D_IPP_QCH_ENABLE, QCH_CON_LH_AXI_SI_D_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_IPP_DNS_QCH, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_IPP_QCH, QCH_CON_PPMU_IPP_QCH_ENABLE, QCH_CON_PPMU_IPP_QCH_CLOCK_REQ, QCH_CON_PPMU_IPP_QCH_EXPIRE_VAL, QCH_CON_PPMU_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_MSA_QCH, QCH_CON_PPMU_MSA_QCH_ENABLE, QCH_CON_PPMU_MSA_QCH_CLOCK_REQ, QCH_CON_PPMU_MSA_QCH_EXPIRE_VAL, QCH_CON_PPMU_MSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ALIGN0_QCH, QCH_CON_QE_ALIGN0_QCH_ENABLE, QCH_CON_QE_ALIGN0_QCH_CLOCK_REQ, QCH_CON_QE_ALIGN0_QCH_EXPIRE_VAL, QCH_CON_QE_ALIGN0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ALIGN1_QCH, QCH_CON_QE_ALIGN1_QCH_ENABLE, QCH_CON_QE_ALIGN1_QCH_CLOCK_REQ, QCH_CON_QE_ALIGN1_QCH_EXPIRE_VAL, QCH_CON_QE_ALIGN1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ALIGN2_QCH, QCH_CON_QE_ALIGN2_QCH_ENABLE, QCH_CON_QE_ALIGN2_QCH_CLOCK_REQ, QCH_CON_QE_ALIGN2_QCH_EXPIRE_VAL, QCH_CON_QE_ALIGN2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ALIGN3_QCH, QCH_CON_QE_ALIGN3_QCH_ENABLE, QCH_CON_QE_ALIGN3_QCH_CLOCK_REQ, QCH_CON_QE_ALIGN3_QCH_EXPIRE_VAL, QCH_CON_QE_ALIGN3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ALN_STAT_QCH, QCH_CON_QE_ALN_STAT_QCH_ENABLE, QCH_CON_QE_ALN_STAT_QCH_CLOCK_REQ, QCH_CON_QE_ALN_STAT_QCH_EXPIRE_VAL, QCH_CON_QE_ALN_STAT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_FDPIG_QCH, QCH_CON_QE_FDPIG_QCH_ENABLE, QCH_CON_QE_FDPIG_QCH_CLOCK_REQ, QCH_CON_QE_FDPIG_QCH_EXPIRE_VAL, QCH_CON_QE_FDPIG_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_RGBH0_QCH, QCH_CON_QE_RGBH0_QCH_ENABLE, QCH_CON_QE_RGBH0_QCH_CLOCK_REQ, QCH_CON_QE_RGBH0_QCH_EXPIRE_VAL, QCH_CON_QE_RGBH0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_RGBH1_QCH, QCH_CON_QE_RGBH1_QCH_ENABLE, QCH_CON_QE_RGBH1_QCH_CLOCK_REQ, QCH_CON_QE_RGBH1_QCH_EXPIRE_VAL, QCH_CON_QE_RGBH1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_RGBH2_QCH, QCH_CON_QE_RGBH2_QCH_ENABLE, QCH_CON_QE_RGBH2_QCH_CLOCK_REQ, QCH_CON_QE_RGBH2_QCH_EXPIRE_VAL, QCH_CON_QE_RGBH2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_THSTAT_QCH, QCH_CON_QE_THSTAT_QCH_ENABLE, QCH_CON_QE_THSTAT_QCH_CLOCK_REQ, QCH_CON_QE_THSTAT_QCH_EXPIRE_VAL, QCH_CON_QE_THSTAT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_TNR_MSA0_QCH, QCH_CON_QE_TNR_MSA0_QCH_ENABLE, QCH_CON_QE_TNR_MSA0_QCH_CLOCK_REQ, QCH_CON_QE_TNR_MSA0_QCH_EXPIRE_VAL, QCH_CON_QE_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_TNR_MSA1_QCH, QCH_CON_QE_TNR_MSA1_QCH_ENABLE, QCH_CON_QE_TNR_MSA1_QCH_CLOCK_REQ, QCH_CON_QE_TNR_MSA1_QCH_EXPIRE_VAL, QCH_CON_QE_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SIPU_IPP_QCH, QCH_CON_SIPU_IPP_QCH_ENABLE, QCH_CON_SIPU_IPP_QCH_CLOCK_REQ, QCH_CON_SIPU_IPP_QCH_EXPIRE_VAL, QCH_CON_SIPU_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_IPP_QCH, QCH_CON_SLH_AXI_MI_P_IPP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_IPP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_IPP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ALIGN0_QCH, QCH_CON_SSMT_ALIGN0_QCH_ENABLE, QCH_CON_SSMT_ALIGN0_QCH_CLOCK_REQ, QCH_CON_SSMT_ALIGN0_QCH_EXPIRE_VAL, QCH_CON_SSMT_ALIGN0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ALIGN1_QCH, QCH_CON_SSMT_ALIGN1_QCH_ENABLE, QCH_CON_SSMT_ALIGN1_QCH_CLOCK_REQ, QCH_CON_SSMT_ALIGN1_QCH_EXPIRE_VAL, QCH_CON_SSMT_ALIGN1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ALIGN2_QCH, QCH_CON_SSMT_ALIGN2_QCH_ENABLE, QCH_CON_SSMT_ALIGN2_QCH_CLOCK_REQ, QCH_CON_SSMT_ALIGN2_QCH_EXPIRE_VAL, QCH_CON_SSMT_ALIGN2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ALIGN3_QCH, QCH_CON_SSMT_ALIGN3_QCH_ENABLE, QCH_CON_SSMT_ALIGN3_QCH_CLOCK_REQ, QCH_CON_SSMT_ALIGN3_QCH_EXPIRE_VAL, QCH_CON_SSMT_ALIGN3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ALN_STAT_QCH, QCH_CON_SSMT_ALN_STAT_QCH_ENABLE, QCH_CON_SSMT_ALN_STAT_QCH_CLOCK_REQ, QCH_CON_SSMT_ALN_STAT_QCH_EXPIRE_VAL, QCH_CON_SSMT_ALN_STAT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_FDPIG_QCH, QCH_CON_SSMT_FDPIG_QCH_ENABLE, QCH_CON_SSMT_FDPIG_QCH_CLOCK_REQ, QCH_CON_SSMT_FDPIG_QCH_EXPIRE_VAL, QCH_CON_SSMT_FDPIG_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_RGBH0_QCH, QCH_CON_SSMT_RGBH0_QCH_ENABLE, QCH_CON_SSMT_RGBH0_QCH_CLOCK_REQ, QCH_CON_SSMT_RGBH0_QCH_EXPIRE_VAL, QCH_CON_SSMT_RGBH0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_RGBH1_QCH, QCH_CON_SSMT_RGBH1_QCH_ENABLE, QCH_CON_SSMT_RGBH1_QCH_CLOCK_REQ, QCH_CON_SSMT_RGBH1_QCH_EXPIRE_VAL, QCH_CON_SSMT_RGBH1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_RGBH2_QCH, QCH_CON_SSMT_RGBH2_QCH_ENABLE, QCH_CON_SSMT_RGBH2_QCH_CLOCK_REQ, QCH_CON_SSMT_RGBH2_QCH_EXPIRE_VAL, QCH_CON_SSMT_RGBH2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_THSTAT_QCH, QCH_CON_SSMT_THSTAT_QCH_ENABLE, QCH_CON_SSMT_THSTAT_QCH_CLOCK_REQ, QCH_CON_SSMT_THSTAT_QCH_EXPIRE_VAL, QCH_CON_SSMT_THSTAT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_TNR_MSA0_QCH, QCH_CON_SSMT_TNR_MSA0_QCH_ENABLE, QCH_CON_SSMT_TNR_MSA0_QCH_CLOCK_REQ, QCH_CON_SSMT_TNR_MSA0_QCH_EXPIRE_VAL, QCH_CON_SSMT_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_TNR_MSA1_QCH, QCH_CON_SSMT_TNR_MSA1_QCH_ENABLE, QCH_CON_SSMT_TNR_MSA1_QCH_CLOCK_REQ, QCH_CON_SSMT_TNR_MSA1_QCH_EXPIRE_VAL, QCH_CON_SSMT_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_IPP_QCH_S1, QCH_CON_SYSMMU_IPP_QCH_S1_ENABLE, QCH_CON_SYSMMU_IPP_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_IPP_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_IPP_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_IPP_QCH_S2, QCH_CON_SYSMMU_IPP_QCH_S2_ENABLE, QCH_CON_SYSMMU_IPP_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_IPP_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_IPP_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_IPP_QCH, QCH_CON_SYSREG_IPP_QCH_ENABLE, QCH_CON_SYSREG_IPP_QCH_CLOCK_REQ, QCH_CON_SYSREG_IPP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TNR_A_QCH, QCH_CON_TNR_A_QCH_ENABLE, QCH_CON_TNR_A_QCH_CLOCK_REQ, QCH_CON_TNR_A_QCH_EXPIRE_VAL, QCH_CON_TNR_A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_ITP_QCH, QCH_CON_D_TZPC_ITP_QCH_ENABLE, QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_ITP_QCH, QCH_CON_GPC_ITP_QCH_ENABLE, QCH_CON_GPC_ITP_QCH_CLOCK_REQ, QCH_CON_GPC_ITP_QCH_EXPIRE_VAL, QCH_CON_GPC_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ITP_QCH, QCH_CON_ITP_QCH_ENABLE, QCH_CON_ITP_QCH_CLOCK_REQ, QCH_CON_ITP_QCH_EXPIRE_VAL, QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ITP_CMU_ITP_QCH, QCH_CON_ITP_CMU_ITP_QCH_ENABLE, QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ, QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL, QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_DNS_ITP_QCH, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_DNS_ITP_QCH, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_ITP_DNS_QCH, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_ITP_DNS_QCH, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_ITP_QCH, QCH_CON_PPMU_ITP_QCH_ENABLE, QCH_CON_PPMU_ITP_QCH_CLOCK_REQ, QCH_CON_PPMU_ITP_QCH_EXPIRE_VAL, QCH_CON_PPMU_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_ITP_QCH, QCH_CON_QE_ITP_QCH_ENABLE, QCH_CON_QE_ITP_QCH_CLOCK_REQ, QCH_CON_QE_ITP_QCH_EXPIRE_VAL, QCH_CON_QE_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_ITP_QCH, QCH_CON_SLH_AXI_MI_P_ITP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_ITP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_ITP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_ITP_QCH, QCH_CON_SSMT_ITP_QCH_ENABLE, QCH_CON_SSMT_ITP_QCH_CLOCK_REQ, QCH_CON_SSMT_ITP_QCH_EXPIRE_VAL, QCH_CON_SSMT_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_ITP_QCH, QCH_CON_SYSREG_ITP_QCH_ENABLE, QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(C2R_MCSC_QCH, QCH_CON_C2R_MCSC_QCH_ENABLE, QCH_CON_C2R_MCSC_QCH_CLOCK_REQ, QCH_CON_C2R_MCSC_QCH_EXPIRE_VAL, QCH_CON_C2R_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_MCSC_QCH, QCH_CON_D_TZPC_MCSC_QCH_ENABLE, QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_MCSC_QCH, QCH_CON_GPC_MCSC_QCH_ENABLE, QCH_CON_GPC_MCSC_QCH_CLOCK_REQ, QCH_CON_GPC_MCSC_QCH_EXPIRE_VAL, QCH_CON_GPC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ITSC_QCH_CLK, QCH_CON_ITSC_QCH_CLK_ENABLE, QCH_CON_ITSC_QCH_CLK_CLOCK_REQ, QCH_CON_ITSC_QCH_CLK_EXPIRE_VAL, QCH_CON_ITSC_QCH_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(ITSC_QCH_C2, QCH_CON_ITSC_QCH_C2_ENABLE, QCH_CON_ITSC_QCH_C2_CLOCK_REQ, QCH_CON_ITSC_QCH_C2_EXPIRE_VAL, QCH_CON_ITSC_QCH_C2_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_I_ITSC_MCSC_QCH, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_DNS_MCSC_QCH, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_DNS_MCSC_QCH, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF2_DNS_MCSC_QCH, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_TNR_MCSC_QCH, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_GDC_MCSC_QCH, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_I_ITSC_MCSC_QCH, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_MCSC_TNR_QCH, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_MCSC_CSIS_QCH, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_MCSC_QCH, QCH_CON_LH_AXI_SI_D0_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_MCSC_QCH, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D2_MCSC_QCH, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_MCSC_DNS_QCH, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MCSC_QCH_CLK, QCH_CON_MCSC_QCH_CLK_ENABLE, QCH_CON_MCSC_QCH_CLK_CLOCK_REQ, QCH_CON_MCSC_QCH_CLK_EXPIRE_VAL, QCH_CON_MCSC_QCH_CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(MCSC_QCH_C2CLK, QCH_CON_MCSC_QCH_C2CLK_ENABLE, QCH_CON_MCSC_QCH_C2CLK_CLOCK_REQ, QCH_CON_MCSC_QCH_C2CLK_EXPIRE_VAL, QCH_CON_MCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN), + CLK_QCH(MCSC_CMU_MCSC_QCH, QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_ITSC_QCH, QCH_CON_PPMU_D0_ITSC_QCH_ENABLE, QCH_CON_PPMU_D0_ITSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_ITSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_MCSC_QCH, QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_ITSC_QCH, QCH_CON_PPMU_D1_ITSC_QCH_ENABLE, QCH_CON_PPMU_D1_ITSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_ITSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_MCSC_QCH, QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D0_MCSC_QCH, QCH_CON_QE_D0_MCSC_QCH_ENABLE, QCH_CON_QE_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_ITSC_QCH, QCH_CON_QE_D1_ITSC_QCH_ENABLE, QCH_CON_QE_D1_ITSC_QCH_CLOCK_REQ, QCH_CON_QE_D1_ITSC_QCH_EXPIRE_VAL, QCH_CON_QE_D1_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_MCSC_QCH, QCH_CON_QE_D1_MCSC_QCH_ENABLE, QCH_CON_QE_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D2_ITSC_QCH, QCH_CON_QE_D2_ITSC_QCH_ENABLE, QCH_CON_QE_D2_ITSC_QCH_CLOCK_REQ, QCH_CON_QE_D2_ITSC_QCH_EXPIRE_VAL, QCH_CON_QE_D2_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D2_MCSC_QCH, QCH_CON_QE_D2_MCSC_QCH_ENABLE, QCH_CON_QE_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D3_ITSC_QCH, QCH_CON_QE_D3_ITSC_QCH_ENABLE, QCH_CON_QE_D3_ITSC_QCH_CLOCK_REQ, QCH_CON_QE_D3_ITSC_QCH_EXPIRE_VAL, QCH_CON_QE_D3_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D3_MCSC_QCH, QCH_CON_QE_D3_MCSC_QCH_ENABLE, QCH_CON_QE_D3_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D3_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D3_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D4_MCSC_QCH, QCH_CON_QE_D4_MCSC_QCH_ENABLE, QCH_CON_QE_D4_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D4_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D4_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D5_MCSC_QCH, QCH_CON_QE_D5_MCSC_QCH_ENABLE, QCH_CON_QE_D5_MCSC_QCH_CLOCK_REQ, QCH_CON_QE_D5_MCSC_QCH_EXPIRE_VAL, QCH_CON_QE_D5_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_MCSC_QCH, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_ITSC_QCH, QCH_CON_SSMT_D0_ITSC_QCH_ENABLE, QCH_CON_SSMT_D0_ITSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_ITSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_MCSC_QCH, QCH_CON_SSMT_D0_MCSC_QCH_ENABLE, QCH_CON_SSMT_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_ITSC_QCH, QCH_CON_SSMT_D1_ITSC_QCH_ENABLE, QCH_CON_SSMT_D1_ITSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_ITSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_ITSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_MCSC_QCH, QCH_CON_SSMT_D1_MCSC_QCH_ENABLE, QCH_CON_SSMT_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_MCSC_QCH_S1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_MCSC_QCH_S2, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_MCSC_QCH_S1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_MCSC_QCH_S2, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_MCSC_QCH_S1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_MCSC_QCH_S2, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_MCSC_QCH, QCH_CON_SYSREG_MCSC_QCH_ENABLE, QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_MFC_QCH, QCH_CON_D_TZPC_MFC_QCH_ENABLE, QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_MFC_QCH, QCH_CON_GPC_MFC_QCH_ENABLE, QCH_CON_GPC_MFC_QCH_CLOCK_REQ, QCH_CON_GPC_MFC_QCH_EXPIRE_VAL, QCH_CON_GPC_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_MFC_QCH, QCH_CON_LH_AXI_SI_D0_MFC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_MFC_QCH, QCH_CON_LH_AXI_SI_D1_MFC_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_MFC_QCH, QCH_CON_PPMU_D0_MFC_QCH_ENABLE, QCH_CON_PPMU_D0_MFC_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_MFC_QCH, QCH_CON_PPMU_D1_MFC_QCH_ENABLE, QCH_CON_PPMU_D1_MFC_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_MFC_QCH, QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_MFC_QCH, QCH_CON_SSMT_D0_MFC_QCH_ENABLE, QCH_CON_SSMT_D0_MFC_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_MFC_QCH, QCH_CON_SSMT_D1_MFC_QCH_ENABLE, QCH_CON_SSMT_D1_MFC_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_MFC_QCH_0, QCH_CON_SYSMMU_D0_MFC_QCH_0_ENABLE, QCH_CON_SYSMMU_D0_MFC_QCH_0_CLOCK_REQ, QCH_CON_SYSMMU_D0_MFC_QCH_0_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MFC_QCH_0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_MFC_QCH_1, QCH_CON_SYSMMU_D0_MFC_QCH_1_ENABLE, QCH_CON_SYSMMU_D0_MFC_QCH_1_CLOCK_REQ, QCH_CON_SYSMMU_D0_MFC_QCH_1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_MFC_QCH_1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_MFC_QCH_0, QCH_CON_SYSMMU_D1_MFC_QCH_0_ENABLE, QCH_CON_SYSMMU_D1_MFC_QCH_0_CLOCK_REQ, QCH_CON_SYSMMU_D1_MFC_QCH_0_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MFC_QCH_0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_MFC_QCH_1, QCH_CON_SYSMMU_D1_MFC_QCH_1_ENABLE, QCH_CON_SYSMMU_D1_MFC_QCH_1_CLOCK_REQ, QCH_CON_SYSMMU_D1_MFC_QCH_1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_MFC_QCH_1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBBR_DDRPHY_QCH, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(APBBR_DMC_QCH, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_MIF_QCH, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GEN_WREN_SECURE_QCH, QCH_CON_GEN_WREN_SECURE_QCH_ENABLE, QCH_CON_GEN_WREN_SECURE_QCH_CLOCK_REQ, QCH_CON_GEN_WREN_SECURE_QCH_EXPIRE_VAL, QCH_CON_GEN_WREN_SECURE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_MIF_QCH, QCH_CON_GPC_MIF_QCH_ENABLE, QCH_CON_GPC_MIF_QCH_CLOCK_REQ, QCH_CON_GPC_MIF_QCH_EXPIRE_VAL, QCH_CON_GPC_MIF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC_CD_QCH, QCH_CON_LH_AST_MI_G_DMC_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC_QCH, QCH_CON_LH_AST_SI_G_DMC_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC_CD_QCH, QCH_CON_LH_AST_SI_G_DMC_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MIF_CU_QCH, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MIF_CU_QCH, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QCH_ADAPTER_PPC_DEBUG_QCH, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_MIF_QCH, QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ADM_AHB_G_SSS_QCH, QCH_CON_ADM_AHB_G_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_G_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_G_SSS_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_G_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_MISC_QCH, QCH_CON_D_TZPC_MISC_QCH_ENABLE, QCH_CON_D_TZPC_MISC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MISC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_MISC_QCH, QCH_CON_GPC_MISC_QCH_ENABLE, QCH_CON_GPC_MISC_QCH_CLOCK_REQ, QCH_CON_GPC_MISC_QCH_EXPIRE_VAL, QCH_CON_GPC_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_MISC_QCH, QCH_CON_LH_ACEL_SI_D_MISC_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_MISC_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_MISC_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_ID_SSS_QCH, QCH_CON_LH_AXI_MI_ID_SSS_QCH_ENABLE, QCH_CON_LH_AXI_MI_ID_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_ID_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_ID_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_GIC_CU_QCH, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MISC_CU_QCH, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_ID_SSS_QCH, QCH_CON_LH_AXI_SI_ID_SSS_QCH_ENABLE, QCH_CON_LH_AXI_SI_ID_SSS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_ID_SSS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_ID_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_GIC_CU_QCH, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MISC_CU_QCH, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(MISC_CMU_MISC_QCH, QCH_CON_MISC_CMU_MISC_QCH_ENABLE, QCH_CON_MISC_CMU_MISC_QCH_CLOCK_REQ, QCH_CON_MISC_CMU_MISC_QCH_EXPIRE_VAL, QCH_CON_MISC_CMU_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(OTP_CON_BISR_QCH, QCH_CON_OTP_CON_BISR_QCH_ENABLE, QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PDMA0_QCH, QCH_CON_PDMA0_QCH_ENABLE, QCH_CON_PDMA0_QCH_CLOCK_REQ, QCH_CON_PDMA0_QCH_EXPIRE_VAL, QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PDMA1_QCH, QCH_CON_PDMA1_QCH_ENABLE, QCH_CON_PDMA1_QCH_CLOCK_REQ, QCH_CON_PDMA1_QCH_EXPIRE_VAL, QCH_CON_PDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_MISC_QCH, QCH_CON_PPMU_MISC_QCH_ENABLE, QCH_CON_PPMU_MISC_QCH_CLOCK_REQ, QCH_CON_PPMU_MISC_QCH_EXPIRE_VAL, QCH_CON_PPMU_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PUF_QCH, DMYQCH_CON_PUF_QCH_ENABLE, DMYQCH_CON_PUF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_DIT_QCH, QCH_CON_QE_DIT_QCH_ENABLE, QCH_CON_QE_DIT_QCH_CLOCK_REQ, QCH_CON_QE_DIT_QCH_EXPIRE_VAL, QCH_CON_QE_DIT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDMA0_QCH, QCH_CON_QE_PDMA0_QCH_ENABLE, QCH_CON_QE_PDMA0_QCH_CLOCK_REQ, QCH_CON_QE_PDMA0_QCH_EXPIRE_VAL, QCH_CON_QE_PDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDMA1_QCH, QCH_CON_QE_PDMA1_QCH_ENABLE, QCH_CON_QE_PDMA1_QCH_CLOCK_REQ, QCH_CON_QE_PDMA1_QCH_EXPIRE_VAL, QCH_CON_QE_PDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_RTIC_QCH, QCH_CON_QE_RTIC_QCH_ENABLE, QCH_CON_QE_RTIC_QCH_CLOCK_REQ, QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_SPDMA0_QCH, QCH_CON_QE_SPDMA0_QCH_ENABLE, QCH_CON_QE_SPDMA0_QCH_CLOCK_REQ, QCH_CON_QE_SPDMA0_QCH_EXPIRE_VAL, QCH_CON_QE_SPDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_SPDMA1_QCH, QCH_CON_QE_SPDMA1_QCH_ENABLE, QCH_CON_QE_SPDMA1_QCH_CLOCK_REQ, QCH_CON_QE_SPDMA1_QCH_EXPIRE_VAL, QCH_CON_QE_SPDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_SSS_QCH, QCH_CON_QE_SSS_QCH_ENABLE, QCH_CON_QE_SSS_QCH_CLOCK_REQ, QCH_CON_QE_SSS_QCH_EXPIRE_VAL, QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_GIC_QCH, QCH_CON_SLH_AXI_MI_P_GIC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_GIC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_GIC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_MISC_QCH, QCH_CON_SLH_AXI_MI_P_MISC_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_MISC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_MISC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SPDMA0_QCH, QCH_CON_SPDMA0_QCH_ENABLE, QCH_CON_SPDMA0_QCH_CLOCK_REQ, QCH_CON_SPDMA0_QCH_EXPIRE_VAL, QCH_CON_SPDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SPDMA1_QCH, QCH_CON_SPDMA1_QCH_ENABLE, QCH_CON_SPDMA1_QCH_CLOCK_REQ, QCH_CON_SPDMA1_QCH_EXPIRE_VAL, QCH_CON_SPDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_DIT_QCH, QCH_CON_SSMT_DIT_QCH_ENABLE, QCH_CON_SSMT_DIT_QCH_CLOCK_REQ, QCH_CON_SSMT_DIT_QCH_EXPIRE_VAL, QCH_CON_SSMT_DIT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PDMA0_QCH, QCH_CON_SSMT_PDMA0_QCH_ENABLE, QCH_CON_SSMT_PDMA0_QCH_CLOCK_REQ, QCH_CON_SSMT_PDMA0_QCH_EXPIRE_VAL, QCH_CON_SSMT_PDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PDMA1_QCH, QCH_CON_SSMT_PDMA1_QCH_ENABLE, QCH_CON_SSMT_PDMA1_QCH_CLOCK_REQ, QCH_CON_SSMT_PDMA1_QCH_EXPIRE_VAL, QCH_CON_SSMT_PDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_RTIC_QCH, QCH_CON_SSMT_RTIC_QCH_ENABLE, QCH_CON_SSMT_RTIC_QCH_CLOCK_REQ, QCH_CON_SSMT_RTIC_QCH_EXPIRE_VAL, QCH_CON_SSMT_RTIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_SPDMA0_QCH, QCH_CON_SSMT_SPDMA0_QCH_ENABLE, QCH_CON_SSMT_SPDMA0_QCH_CLOCK_REQ, QCH_CON_SSMT_SPDMA0_QCH_EXPIRE_VAL, QCH_CON_SSMT_SPDMA0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_SPDMA1_QCH, QCH_CON_SSMT_SPDMA1_QCH_ENABLE, QCH_CON_SSMT_SPDMA1_QCH_CLOCK_REQ, QCH_CON_SSMT_SPDMA1_QCH_EXPIRE_VAL, QCH_CON_SSMT_SPDMA1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_SSS_QCH, QCH_CON_SSMT_SSS_QCH_ENABLE, QCH_CON_SSMT_SSS_QCH_CLOCK_REQ, QCH_CON_SSMT_SSS_QCH_EXPIRE_VAL, QCH_CON_SSMT_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_MISC_QCH, QCH_CON_SYSMMU_MISC_QCH_ENABLE, QCH_CON_SYSMMU_MISC_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MISC_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_SSS_QCH, QCH_CON_SYSMMU_SSS_QCH_ENABLE, QCH_CON_SYSMMU_SSS_QCH_CLOCK_REQ, QCH_CON_SYSMMU_SSS_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_SSS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_MISC_QCH, QCH_CON_SYSREG_MISC_QCH_ENABLE, QCH_CON_SYSREG_MISC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MISC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TMU_SUB_QCH, QCH_CON_TMU_SUB_QCH_ENABLE, QCH_CON_TMU_SUB_QCH_CLOCK_REQ, QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TMU_TOP_QCH, QCH_CON_TMU_TOP_QCH_ENABLE, QCH_CON_TMU_TOP_QCH_CLOCK_REQ, QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(WDT_CLUSTER1_QCH, QCH_CON_WDT_CLUSTER1_QCH_ENABLE, QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(ASYNCSFR_WR_SMC_QCH, QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE, QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ, QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL, QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CCI_QCH, QCH_CON_CCI_QCH_ENABLE, QCH_CON_CCI_QCH_CLOCK_REQ, QCH_CON_CCI_QCH_EXPIRE_VAL, QCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_NOCL0_CMUREF_QCH, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CPE425_QCH, QCH_CON_CPE425_QCH_ENABLE, QCH_CON_CPE425_QCH_CLOCK_REQ, QCH_CON_CPE425_QCH_EXPIRE_VAL, QCH_CON_CPE425_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_NOCL0_QCH, QCH_CON_D_TZPC_NOCL0_QCH_ENABLE, QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_NOCL0_QCH, QCH_CON_GPC_NOCL0_QCH_ENABLE, QCH_CON_GPC_NOCL0_QCH_CLOCK_REQ, QCH_CON_GPC_NOCL0_QCH_EXPIRE_VAL, QCH_CON_GPC_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_EH_QCH, QCH_CON_LH_ACEL_MI_D_EH_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_EH_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_EH_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACE_MI_D0_CPUCL0_QCH, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_ENABLE, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACE_MI_D1_CPUCL0_QCH, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_ENABLE, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC0_QCH, QCH_CON_LH_AST_MI_G_DMC0_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC0_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC0_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC0_CU_QCH, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC1_QCH, QCH_CON_LH_AST_MI_G_DMC1_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC1_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC1_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC1_CU_QCH, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC2_QCH, QCH_CON_LH_AST_MI_G_DMC2_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC2_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC2_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC2_CU_QCH, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC3_QCH, QCH_CON_LH_AST_MI_G_DMC3_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC3_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC3_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_DMC3_CU_QCH, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1A_QCH, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1A_CU_QCH, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1B_QCH, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1B_CU_QCH, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL2A_QCH, QCH_CON_LH_AST_MI_G_NOCL2A_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL2A_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL2A_CU_QCH, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC0_CU_QCH, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC1_CU_QCH, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC2_CU_QCH, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_DMC3_CU_QCH, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1A_CU_QCH, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1B_CU_QCH, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL2A_CU_QCH, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_BDU_CD_QCH, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_T_SLC_CD_QCH, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_BDU_QCH, QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_BDU_CD_QCH, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_SLC_QCH, QCH_CON_LH_ATB_SI_T_SLC_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_SLC_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_SLC_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_SLC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_T_SLC_CD_QCH, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_ALIVE_CD_QCH, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_CPUCL0_CD_QCH, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_EH_CD_QCH, QCH_CON_LH_AXI_MI_P_EH_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_EH_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_EH_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_GIC_CD_QCH, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MIF0_CD_QCH, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MIF1_CD_QCH, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MIF2_CD_QCH, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MIF3_CD_QCH, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_MISC_CD_QCH, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_PERIC0_CD_QCH, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_PERIC1_CD_QCH, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_ALIVE_CD_QCH, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_CPUCL0_CD_QCH, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_EH_CD_QCH, QCH_CON_LH_AXI_SI_P_EH_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_EH_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_EH_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_GIC_CD_QCH, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MIF0_CD_QCH, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MIF1_CD_QCH, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MIF2_CD_QCH, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MIF3_CD_QCH, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_MISC_CD_QCH, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_PERIC0_CD_QCH, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_PERIC1_CD_QCH, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(NOCL0_CMU_NOCL0_QCH, QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE, QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ, QCH_CON_NOCL0_CMU_NOCL0_QCH_EXPIRE_VAL, QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CCI_M1_CYCLE_QCH, QCH_CON_PPC_CCI_M1_CYCLE_QCH_ENABLE, QCH_CON_PPC_CCI_M1_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_CCI_M1_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_CCI_M1_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CCI_M1_EVENT_QCH, QCH_CON_PPC_CCI_M1_EVENT_QCH_ENABLE, QCH_CON_PPC_CCI_M1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CCI_M1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CCI_M1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CCI_M2_EVENT_QCH, QCH_CON_PPC_CCI_M2_EVENT_QCH_ENABLE, QCH_CON_PPC_CCI_M2_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CCI_M2_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CCI_M2_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CCI_M3_EVENT_QCH, QCH_CON_PPC_CCI_M3_EVENT_QCH_ENABLE, QCH_CON_PPC_CCI_M3_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CCI_M3_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CCI_M3_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CCI_M4_EVENT_QCH, QCH_CON_PPC_CCI_M4_EVENT_QCH_ENABLE, QCH_CON_PPC_CCI_M4_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CCI_M4_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CCI_M4_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CPUCL0_D0_CYCLE_QCH, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_ENABLE, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CPUCL0_D0_EVENT_QCH, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_ENABLE, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_CPUCL0_D1_EVENT_QCH, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_ENABLE, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_DBG_CC_QCH, DMYQCH_CON_PPC_DBG_CC_QCH_ENABLE, DMYQCH_CON_PPC_DBG_CC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PPC_DBG_CC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_EH_CYCLE_QCH, QCH_CON_PPC_EH_CYCLE_QCH_ENABLE, QCH_CON_PPC_EH_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_EH_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_EH_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_EH_EVENT_QCH, QCH_CON_PPC_EH_EVENT_QCH_ENABLE, QCH_CON_PPC_EH_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_EH_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_EH_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_IO_CYCLE_QCH, QCH_CON_PPC_IO_CYCLE_QCH_ENABLE, QCH_CON_PPC_IO_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_IO_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_IO_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_IO_EVENT_QCH, QCH_CON_PPC_IO_EVENT_QCH_ENABLE, QCH_CON_PPC_IO_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_IO_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_IO_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1A_M0_CYCLE_QCH, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_ENABLE, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1A_M0_EVENT_QCH, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1A_M1_EVENT_QCH, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1A_M2_EVENT_QCH, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1A_M3_EVENT_QCH, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1B_M0_CYCLE_QCH, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_ENABLE, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL1B_M0_EVENT_QCH, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_ACE_CPUCL0_D0_QCH, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_ACE_CPUCL0_D1_QCH, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_ENABLE, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_CLOCK_REQ, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_EXPIRE_VAL, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SFR_APBIF_CMU_TOPC_QCH, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLC_CB_TOP_QCH, QCH_CON_SLC_CB_TOP_QCH_ENABLE, QCH_CON_SLC_CB_TOP_QCH_CLOCK_REQ, QCH_CON_SLC_CB_TOP_QCH_EXPIRE_VAL, QCH_CON_SLC_CB_TOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLC_CH1_QCH, DMYQCH_CON_SLC_CH1_QCH_ENABLE, DMYQCH_CON_SLC_CH1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SLC_CH1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLC_CH2_QCH, DMYQCH_CON_SLC_CH2_QCH_ENABLE, DMYQCH_CON_SLC_CH2_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SLC_CH2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLC_CH3_QCH, DMYQCH_CON_SLC_CH3_QCH_ENABLE, DMYQCH_CON_SLC_CH3_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SLC_CH3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLC_CH_TOP_QCH, DMYQCH_CON_SLC_CH_TOP_QCH_ENABLE, DMYQCH_CON_SLC_CH_TOP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_SLC_CH_TOP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_G_NOCL0_QCH, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_ALIVE_QCH, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_CPUCL0_QCH, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_EH_QCH, QCH_CON_SLH_AXI_SI_P_EH_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_EH_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_EH_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_EH_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_GIC_QCH, QCH_CON_SLH_AXI_SI_P_GIC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GIC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GIC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_GIC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MIF0_QCH, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MIF1_QCH, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MIF2_QCH, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MIF3_QCH, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MISC_QCH, QCH_CON_SLH_AXI_SI_P_MISC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MISC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MISC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_PERIC0_QCH, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_PERIC1_QCH, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_NOCL0_QCH, QCH_CON_SYSREG_NOCL0_QCH_ENABLE, QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_D_NOCL0_QCH, QCH_CON_TREX_D_NOCL0_QCH_ENABLE, QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL0_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_P_NOCL0_QCH, QCH_CON_TREX_P_NOCL0_QCH_ENABLE, QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL0_QCH_EXPIRE_VAL, QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_NOCL1A_CMUREF_QCH, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_NOCL1A_QCH, QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE, QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_NOCL1A_QCH, QCH_CON_GPC_NOCL1A_QCH_ENABLE, QCH_CON_GPC_NOCL1A_QCH_CLOCK_REQ, QCH_CON_GPC_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_GPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D0_G3D_QCH, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D1_G3D_QCH, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D2_G3D_QCH, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D3_G3D_QCH, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_TPU_QCH, QCH_CON_LH_ACEL_MI_D_TPU_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_TPU_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_TPU_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1A_CD_QCH, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1A_QCH, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1A_CD_QCH, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_AUR_QCH, QCH_CON_LH_AXI_MI_D0_AUR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_AUR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_AUR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_AUR_QCH, QCH_CON_LH_AXI_MI_D1_AUR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_AUR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_AUR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_AUR_CD_QCH, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_G3D_CD_QCH, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_TPU_CD_QCH, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_AUR_CD_QCH, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_G3D_CD_QCH, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_TPU_CD_QCH, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(NOCL1A_CMU_NOCL1A_QCH, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPCFW_G3D0_QCH, QCH_CON_PPCFW_G3D0_QCH_ENABLE, QCH_CON_PPCFW_G3D0_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D0_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPCFW_G3D1_QCH, QCH_CON_PPCFW_G3D1_QCH_ENABLE, QCH_CON_PPCFW_G3D1_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D1_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_AUR_D0_CYCLE_QCH, QCH_CON_PPC_AUR_D0_CYCLE_QCH_ENABLE, QCH_CON_PPC_AUR_D0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_AUR_D0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_AUR_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_AUR_D0_EVENT_QCH, QCH_CON_PPC_AUR_D0_EVENT_QCH_ENABLE, QCH_CON_PPC_AUR_D0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_AUR_D0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_AUR_D0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_AUR_D1_EVENT_QCH, QCH_CON_PPC_AUR_D1_EVENT_QCH_ENABLE, QCH_CON_PPC_AUR_D1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_AUR_D1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_AUR_D1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_G3D_D0_CYCLE_QCH, QCH_CON_PPC_G3D_D0_CYCLE_QCH_ENABLE, QCH_CON_PPC_G3D_D0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_G3D_D0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_G3D_D0_EVENT_QCH, QCH_CON_PPC_G3D_D0_EVENT_QCH_ENABLE, QCH_CON_PPC_G3D_D0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_G3D_D0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D_D0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_G3D_D1_EVENT_QCH, QCH_CON_PPC_G3D_D1_EVENT_QCH_ENABLE, QCH_CON_PPC_G3D_D1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_G3D_D1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D_D1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_G3D_D2_EVENT_QCH, QCH_CON_PPC_G3D_D2_EVENT_QCH_ENABLE, QCH_CON_PPC_G3D_D2_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_G3D_D2_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D_D2_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_G3D_D3_EVENT_QCH, QCH_CON_PPC_G3D_D3_EVENT_QCH_ENABLE, QCH_CON_PPC_G3D_D3_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_G3D_D3_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D_D3_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL2A_M0_CYCLE_QCH, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_ENABLE, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL2A_M0_EVENT_QCH, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL2A_M1_EVENT_QCH, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL2A_M2_EVENT_QCH, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_NOCL2A_M3_EVENT_QCH, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_ENABLE, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_TPU_CYCLE_QCH, QCH_CON_PPC_TPU_CYCLE_QCH_ENABLE, QCH_CON_PPC_TPU_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_TPU_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_TPU_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_TPU_EVENT_QCH, QCH_CON_PPC_TPU_EVENT_QCH_ENABLE, QCH_CON_PPC_TPU_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_TPU_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_TPU_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_AUR_QCH, QCH_CON_SLH_AXI_SI_P_AUR_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_AUR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_AUR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_AUR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_G3D_QCH, QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_TPU_QCH, QCH_CON_SLH_AXI_SI_P_TPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_G3D0_QCH, QCH_CON_SSMT_G3D0_QCH_ENABLE, QCH_CON_SSMT_G3D0_QCH_CLOCK_REQ, QCH_CON_SSMT_G3D0_QCH_EXPIRE_VAL, QCH_CON_SSMT_G3D0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_G3D1_QCH, QCH_CON_SSMT_G3D1_QCH_ENABLE, QCH_CON_SSMT_G3D1_QCH_CLOCK_REQ, QCH_CON_SSMT_G3D1_QCH_EXPIRE_VAL, QCH_CON_SSMT_G3D1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_G3D2_QCH, QCH_CON_SSMT_G3D2_QCH_ENABLE, QCH_CON_SSMT_G3D2_QCH_CLOCK_REQ, QCH_CON_SSMT_G3D2_QCH_EXPIRE_VAL, QCH_CON_SSMT_G3D2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_G3D3_QCH, QCH_CON_SSMT_G3D3_QCH_ENABLE, QCH_CON_SSMT_G3D3_QCH_CLOCK_REQ, QCH_CON_SSMT_G3D3_QCH_EXPIRE_VAL, QCH_CON_SSMT_G3D3_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3D_QCH_D0, QCH_CON_SYSMMU_G3D_QCH_D0_ENABLE, QCH_CON_SYSMMU_G3D_QCH_D0_CLOCK_REQ, QCH_CON_SYSMMU_G3D_QCH_D0_EXPIRE_VAL, QCH_CON_SYSMMU_G3D_QCH_D0_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3D_QCH_D1, QCH_CON_SYSMMU_G3D_QCH_D1_ENABLE, QCH_CON_SYSMMU_G3D_QCH_D1_CLOCK_REQ, QCH_CON_SYSMMU_G3D_QCH_D1_EXPIRE_VAL, QCH_CON_SYSMMU_G3D_QCH_D1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3D_QCH_D2, QCH_CON_SYSMMU_G3D_QCH_D2_ENABLE, QCH_CON_SYSMMU_G3D_QCH_D2_CLOCK_REQ, QCH_CON_SYSMMU_G3D_QCH_D2_EXPIRE_VAL, QCH_CON_SYSMMU_G3D_QCH_D2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3D_QCH_D3, QCH_CON_SYSMMU_G3D_QCH_D3_ENABLE, QCH_CON_SYSMMU_G3D_QCH_D3_CLOCK_REQ, QCH_CON_SYSMMU_G3D_QCH_D3_EXPIRE_VAL, QCH_CON_SYSMMU_G3D_QCH_D3_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_G3D_QCH_MPTW, QCH_CON_SYSMMU_G3D_QCH_MPTW_ENABLE, QCH_CON_SYSMMU_G3D_QCH_MPTW_CLOCK_REQ, QCH_CON_SYSMMU_G3D_QCH_MPTW_EXPIRE_VAL, QCH_CON_SYSMMU_G3D_QCH_MPTW_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_NOCL1A_QCH, QCH_CON_SYSREG_NOCL1A_QCH_ENABLE, QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_D_NOCL1A_QCH, QCH_CON_TREX_D_NOCL1A_QCH_ENABLE, QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_P_NOCL1A_QCH, QCH_CON_TREX_P_NOCL1A_QCH_ENABLE, QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL1A_QCH_EXPIRE_VAL, QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_NOCL1B_CMUREF_QCH, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_NOCL1B_QCH, QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE, QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_NOCL1B_QCH, QCH_CON_GPC_NOCL1B_QCH_ENABLE, QCH_CON_GPC_NOCL1B_QCH_CLOCK_REQ, QCH_CON_GPC_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_GPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_HSI0_QCH, QCH_CON_LH_ACEL_MI_D_HSI0_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_HSI0_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_HSI1_QCH, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL1B_CD_QCH, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1B_QCH, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL1B_CD_QCH, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_AOC_QCH, QCH_CON_LH_AXI_MI_D_AOC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_AOC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_AOC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_APM_QCH, QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_GSA_QCH, QCH_CON_LH_AXI_MI_D_GSA_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_GSA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_GSA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_G_CSSYS_CU_QCH, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_AOC_CD_QCH, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_GSA_CD_QCH, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI0_CD_QCH, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI1_CD_QCH, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_G_CSSYS_CU_QCH, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_AOC_CD_QCH, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_GSA_CD_QCH, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI0_CD_QCH, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI1_CD_QCH, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(NOCL1B_CMU_NOCL1B_QCH, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_AOC_CYCLE_QCH, QCH_CON_PPC_AOC_CYCLE_QCH_ENABLE, QCH_CON_PPC_AOC_CYCLE_QCH_CLOCK_REQ, QCH_CON_PPC_AOC_CYCLE_QCH_EXPIRE_VAL, QCH_CON_PPC_AOC_CYCLE_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPC_AOC_EVENT_QCH, QCH_CON_PPC_AOC_EVENT_QCH_ENABLE, QCH_CON_PPC_AOC_EVENT_QCH_CLOCK_REQ, QCH_CON_PPC_AOC_EVENT_QCH_EXPIRE_VAL, QCH_CON_PPC_AOC_EVENT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_G_CSSYS_QCH, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_AOC_QCH, QCH_CON_SLH_AXI_SI_P_AOC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_AOC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_AOC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_AOC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_GSA_QCH, QCH_CON_SLH_AXI_SI_P_GSA_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GSA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GSA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_GSA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_HSI0_QCH, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_HSI1_QCH, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_NOCL1B_QCH, QCH_CON_SYSREG_NOCL1B_QCH_ENABLE, QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_D_NOCL1B_QCH, QCH_CON_TREX_D_NOCL1B_QCH_ENABLE, QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_P_NOCL1B_QCH, QCH_CON_TREX_P_NOCL1B_QCH_ENABLE, QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL1B_QCH_EXPIRE_VAL, QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(CMU_NOCL2A_CMUREF_QCH, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_NOCL2A_QCH, QCH_CON_D_TZPC_NOCL2A_QCH_ENABLE, QCH_CON_D_TZPC_NOCL2A_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_NOCL2A_QCH, QCH_CON_GPC_NOCL2A_QCH_ENABLE, QCH_CON_GPC_NOCL2A_QCH_CLOCK_REQ, QCH_CON_GPC_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_GPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D2_G2D_QCH, QCH_CON_LH_ACEL_MI_D2_G2D_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D2_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_HSI2_QCH, QCH_CON_LH_ACEL_MI_D_HSI2_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_HSI2_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_HSI2_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_MI_D_MISC_QCH, QCH_CON_LH_ACEL_MI_D_MISC_QCH_ENABLE, QCH_CON_LH_ACEL_MI_D_MISC_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_MI_D_MISC_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_MI_D_MISC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_G_NOCL2A_CD_QCH, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_ENABLE, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL2A_QCH, QCH_CON_LH_AST_SI_G_NOCL2A_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL2A_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_G_NOCL2A_CD_QCH, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_ENABLE, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_CSIS_QCH, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_DPU_QCH, QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_G2D_QCH, QCH_CON_LH_AXI_MI_D0_G2D_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_GDC_QCH, QCH_CON_LH_AXI_MI_D0_GDC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_MCSC_QCH, QCH_CON_LH_AXI_MI_D0_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_MFC_QCH, QCH_CON_LH_AXI_MI_D0_MFC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D0_TNR_QCH, QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_CSIS_QCH, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_DPU_QCH, QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_G2D_QCH, QCH_CON_LH_AXI_MI_D1_G2D_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_GDC_QCH, QCH_CON_LH_AXI_MI_D1_GDC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_MCSC_QCH, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_MFC_QCH, QCH_CON_LH_AXI_MI_D1_MFC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D1_TNR_QCH, QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D2_DPU_QCH, QCH_CON_LH_AXI_MI_D2_DPU_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D2_GDC_QCH, QCH_CON_LH_AXI_MI_D2_GDC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D2_MCSC_QCH, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D2_TNR_QCH, QCH_CON_LH_AXI_MI_D2_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D2_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D2_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D2_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D3_TNR_QCH, QCH_CON_LH_AXI_MI_D3_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D3_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D3_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D3_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D4_TNR_QCH, QCH_CON_LH_AXI_MI_D4_TNR_QCH_ENABLE, QCH_CON_LH_AXI_MI_D4_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D4_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D4_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_BO_QCH, QCH_CON_LH_AXI_MI_D_BO_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_BO_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_BO_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_DNS_QCH, QCH_CON_LH_AXI_MI_D_DNS_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_G3AA_QCH, QCH_CON_LH_AXI_MI_D_G3AA_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_D_IPP_QCH, QCH_CON_LH_AXI_MI_D_IPP_QCH_ENABLE, QCH_CON_LH_AXI_MI_D_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_D_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_D_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_HSI2_CD_QCH, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_HSI2_CD_QCH, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(NOCL2A_CMU_NOCL2A_QCH, QCH_CON_NOCL2A_CMU_NOCL2A_QCH_ENABLE, QCH_CON_NOCL2A_CMU_NOCL2A_QCH_CLOCK_REQ, QCH_CON_NOCL2A_CMU_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_NOCL2A_CMU_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_BO_QCH, QCH_CON_SLH_AXI_SI_P_BO_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_BO_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_BO_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_BO_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_CSIS_QCH, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_DISP_QCH, QCH_CON_SLH_AXI_SI_P_DISP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DISP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DISP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_DISP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_DNS_QCH, QCH_CON_SLH_AXI_SI_P_DNS_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DNS_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DNS_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_DPU_QCH, QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_G2D_QCH, QCH_CON_SLH_AXI_SI_P_G2D_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G2D_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_G2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_G3AA_QCH, QCH_CON_SLH_AXI_SI_P_G3AA_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_G3AA_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_G3AA_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_GDC_QCH, QCH_CON_SLH_AXI_SI_P_GDC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_GDC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_GDC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_HSI2_QCH, QCH_CON_SLH_AXI_SI_P_HSI2_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_HSI2_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_HSI2_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_HSI2_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_IPP_QCH, QCH_CON_SLH_AXI_SI_P_IPP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_IPP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_IPP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_ITP_QCH, QCH_CON_SLH_AXI_SI_P_ITP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_ITP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_ITP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_ITP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MCSC_QCH, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_MFC_QCH, QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_PDP_QCH, QCH_CON_SLH_AXI_SI_P_PDP_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_PDP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_PDP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_SI_P_TNR_QCH, QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_NOCL2A_QCH, QCH_CON_SYSREG_NOCL2A_QCH_ENABLE, QCH_CON_SYSREG_NOCL2A_QCH_CLOCK_REQ, QCH_CON_SYSREG_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_D_NOCL2A_QCH, QCH_CON_TREX_D_NOCL2A_QCH_ENABLE, QCH_CON_TREX_D_NOCL2A_QCH_CLOCK_REQ, QCH_CON_TREX_D_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_TREX_D_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TREX_P_NOCL2A_QCH, QCH_CON_TREX_P_NOCL2A_QCH_ENABLE, QCH_CON_TREX_P_NOCL2A_QCH_CLOCK_REQ, QCH_CON_TREX_P_NOCL2A_QCH_EXPIRE_VAL, QCH_CON_TREX_P_NOCL2A_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_PDP_QCH, QCH_CON_D_TZPC_PDP_QCH_ENABLE, QCH_CON_D_TZPC_PDP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PDP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_PDP_QCH, QCH_CON_GPC_PDP_QCH_ENABLE, QCH_CON_GPC_PDP_QCH_CLOCK_REQ, QCH_CON_GPC_PDP_QCH_EXPIRE_VAL, QCH_CON_GPC_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF0_CSIS_PDP_QCH, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF1_CSIS_PDP_QCH, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF2_CSIS_PDP_QCH, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_CSIS_PDP_QCH, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_PDP_CSIS_QCH, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_PDP_G3AA_QCH, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF0_PDP_IPP_QCH, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_PDP_CSIS_QCH, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_PDP_G3AA_QCH, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF1_PDP_IPP_QCH, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF2_PDP_CSIS_QCH, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF2_PDP_G3AA_QCH, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF2_PDP_IPP_QCH, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_PDP_IPP_QCH, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_YOTF0_PDP_G3AA_QCH, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_YOTF1_PDP_G3AA_QCH, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_ENABLE, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_PDP_CSIS_QCH, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LD_PDP_DNS_QCH, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_ENABLE, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PDP_CMU_PDP_QCH, QCH_CON_PDP_CMU_PDP_QCH_ENABLE, QCH_CON_PDP_CMU_PDP_QCH_CLOCK_REQ, QCH_CON_PDP_CMU_PDP_QCH_EXPIRE_VAL, QCH_CON_PDP_CMU_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PDP_TOP_QCH_C2_PDP, QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE, QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ, QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL, QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN), + CLK_QCH(PDP_TOP_QCH_PDP_TOP, QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE, QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ, QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL, QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_VRA_QCH, QCH_CON_PPMU_VRA_QCH_ENABLE, QCH_CON_PPMU_VRA_QCH_CLOCK_REQ, QCH_CON_PPMU_VRA_QCH_EXPIRE_VAL, QCH_CON_PPMU_VRA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDP_AF0_QCH, QCH_CON_QE_PDP_AF0_QCH_ENABLE, QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDP_AF1_QCH, QCH_CON_QE_PDP_AF1_QCH_ENABLE, QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDP_STAT0_QCH, QCH_CON_QE_PDP_STAT0_QCH_ENABLE, QCH_CON_QE_PDP_STAT0_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT0_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_PDP_STAT1_QCH, QCH_CON_QE_PDP_STAT1_QCH_ENABLE, QCH_CON_QE_PDP_STAT1_QCH_CLOCK_REQ, QCH_CON_QE_PDP_STAT1_QCH_EXPIRE_VAL, QCH_CON_QE_PDP_STAT1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_VRA_QCH, QCH_CON_QE_VRA_QCH_ENABLE, QCH_CON_QE_VRA_QCH_CLOCK_REQ, QCH_CON_QE_VRA_QCH_EXPIRE_VAL, QCH_CON_QE_VRA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_PDP_QCH, QCH_CON_SLH_AXI_MI_P_PDP_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PDP_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PDP_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_PDP_STAT_QCH, QCH_CON_SSMT_PDP_STAT_QCH_ENABLE, QCH_CON_SSMT_PDP_STAT_QCH_CLOCK_REQ, QCH_CON_SSMT_PDP_STAT_QCH_EXPIRE_VAL, QCH_CON_SSMT_PDP_STAT_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_VRA_QCH, QCH_CON_SSMT_VRA_QCH_ENABLE, QCH_CON_SSMT_VRA_QCH_CLOCK_REQ, QCH_CON_SSMT_VRA_QCH_EXPIRE_VAL, QCH_CON_SSMT_VRA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_PDP_QCH, QCH_CON_SYSREG_PDP_QCH_ENABLE, QCH_CON_SYSREG_PDP_QCH_CLOCK_REQ, QCH_CON_SYSREG_PDP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PDP_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(VRA_QCH, QCH_CON_VRA_QCH_ENABLE, QCH_CON_VRA_QCH_CLOCK_REQ, QCH_CON_VRA_QCH_EXPIRE_VAL, QCH_CON_VRA_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_PERIC0_QCH, QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_PERIC0_QCH, QCH_CON_GPC_PERIC0_QCH_ENABLE, QCH_CON_GPC_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPC_PERIC0_QCH_EXPIRE_VAL, QCH_CON_GPC_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C1_QCH_SCLK, DMYQCH_CON_I3C1_QCH_SCLK_ENABLE, DMYQCH_CON_I3C1_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C1_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C1_QCH_PCLK, QCH_CON_I3C1_QCH_PCLK_ENABLE, QCH_CON_I3C1_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C1_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C1_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C2_QCH_SCLK, DMYQCH_CON_I3C2_QCH_SCLK_ENABLE, DMYQCH_CON_I3C2_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C2_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C2_QCH_PCLK, QCH_CON_I3C2_QCH_PCLK_ENABLE, QCH_CON_I3C2_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C2_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C2_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C3_QCH_SCLK, DMYQCH_CON_I3C3_QCH_SCLK_ENABLE, DMYQCH_CON_I3C3_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C3_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C3_QCH_PCLK, QCH_CON_I3C3_QCH_PCLK_ENABLE, QCH_CON_I3C3_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C3_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C3_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C4_QCH_SCLK, DMYQCH_CON_I3C4_QCH_SCLK_ENABLE, DMYQCH_CON_I3C4_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C4_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C4_QCH_PCLK, QCH_CON_I3C4_QCH_PCLK_ENABLE, QCH_CON_I3C4_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C4_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C4_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C5_QCH_SCLK, DMYQCH_CON_I3C5_QCH_SCLK_ENABLE, DMYQCH_CON_I3C5_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C5_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C5_QCH_PCLK, QCH_CON_I3C5_QCH_PCLK_ENABLE, QCH_CON_I3C5_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C5_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C5_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C6_QCH_SCLK, DMYQCH_CON_I3C6_QCH_SCLK_ENABLE, DMYQCH_CON_I3C6_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C6_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C6_QCH_PCLK, QCH_CON_I3C6_QCH_PCLK_ENABLE, QCH_CON_I3C6_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C6_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C6_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C7_QCH_SCLK, DMYQCH_CON_I3C7_QCH_SCLK_ENABLE, DMYQCH_CON_I3C7_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C7_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C7_QCH_PCLK, QCH_CON_I3C7_QCH_PCLK_ENABLE, QCH_CON_I3C7_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C7_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C7_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C8_QCH_SCLK, DMYQCH_CON_I3C8_QCH_SCLK_ENABLE, DMYQCH_CON_I3C8_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C8_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C8_QCH_PCLK, QCH_CON_I3C8_QCH_PCLK_ENABLE, QCH_CON_I3C8_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C8_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C8_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_PERIC0_CU_QCH, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_PERIC0_CU_QCH, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_PERIC0_QCH, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI0_UART_QCH, QCH_CON_USI0_UART_QCH_ENABLE, QCH_CON_USI0_UART_QCH_CLOCK_REQ, QCH_CON_USI0_UART_QCH_EXPIRE_VAL, QCH_CON_USI0_UART_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI14_USI_QCH, QCH_CON_USI14_USI_QCH_ENABLE, QCH_CON_USI14_USI_QCH_CLOCK_REQ, QCH_CON_USI14_USI_QCH_EXPIRE_VAL, QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI1_USI_QCH, QCH_CON_USI1_USI_QCH_ENABLE, QCH_CON_USI1_USI_QCH_CLOCK_REQ, QCH_CON_USI1_USI_QCH_EXPIRE_VAL, QCH_CON_USI1_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI2_USI_QCH, QCH_CON_USI2_USI_QCH_ENABLE, QCH_CON_USI2_USI_QCH_CLOCK_REQ, QCH_CON_USI2_USI_QCH_EXPIRE_VAL, QCH_CON_USI2_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI3_USI_QCH, QCH_CON_USI3_USI_QCH_ENABLE, QCH_CON_USI3_USI_QCH_CLOCK_REQ, QCH_CON_USI3_USI_QCH_EXPIRE_VAL, QCH_CON_USI3_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI4_USI_QCH, QCH_CON_USI4_USI_QCH_ENABLE, QCH_CON_USI4_USI_QCH_CLOCK_REQ, QCH_CON_USI4_USI_QCH_EXPIRE_VAL, QCH_CON_USI4_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI5_USI_QCH, QCH_CON_USI5_USI_QCH_ENABLE, QCH_CON_USI5_USI_QCH_CLOCK_REQ, QCH_CON_USI5_USI_QCH_EXPIRE_VAL, QCH_CON_USI5_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI6_USI_QCH, QCH_CON_USI6_USI_QCH_ENABLE, QCH_CON_USI6_USI_QCH_CLOCK_REQ, QCH_CON_USI6_USI_QCH_EXPIRE_VAL, QCH_CON_USI6_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI7_USI_QCH, QCH_CON_USI7_USI_QCH_ENABLE, QCH_CON_USI7_USI_QCH_CLOCK_REQ, QCH_CON_USI7_USI_QCH_EXPIRE_VAL, QCH_CON_USI7_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI8_USI_QCH, QCH_CON_USI8_USI_QCH_ENABLE, QCH_CON_USI8_USI_QCH_CLOCK_REQ, QCH_CON_USI8_USI_QCH_EXPIRE_VAL, QCH_CON_USI8_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_PERIC1_QCH, QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_PERIC1_QCH, QCH_CON_GPC_PERIC1_QCH_ENABLE, QCH_CON_GPC_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPC_PERIC1_QCH_EXPIRE_VAL, QCH_CON_GPC_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C0_QCH_SCLK, DMYQCH_CON_I3C0_QCH_SCLK_ENABLE, DMYQCH_CON_I3C0_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C0_QCH_SCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(I3C0_QCH_PCLK, QCH_CON_I3C0_QCH_PCLK_ENABLE, QCH_CON_I3C0_QCH_PCLK_CLOCK_REQ, QCH_CON_I3C0_QCH_PCLK_EXPIRE_VAL, QCH_CON_I3C0_QCH_PCLK_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_PERIC1_CU_QCH, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_PERIC1_CU_QCH, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_PERIC1_QCH, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI0_USI_QCH, QCH_CON_USI0_USI_QCH_ENABLE, QCH_CON_USI0_USI_QCH_CLOCK_REQ, QCH_CON_USI0_USI_QCH_EXPIRE_VAL, QCH_CON_USI0_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI10_USI_QCH, QCH_CON_USI10_USI_QCH_ENABLE, QCH_CON_USI10_USI_QCH_CLOCK_REQ, QCH_CON_USI10_USI_QCH_EXPIRE_VAL, QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI11_USI_QCH, QCH_CON_USI11_USI_QCH_ENABLE, QCH_CON_USI11_USI_QCH_CLOCK_REQ, QCH_CON_USI11_USI_QCH_EXPIRE_VAL, QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI12_USI_QCH, QCH_CON_USI12_USI_QCH_ENABLE, QCH_CON_USI12_USI_QCH_CLOCK_REQ, QCH_CON_USI12_USI_QCH_EXPIRE_VAL, QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI13_USI_QCH, QCH_CON_USI13_USI_QCH_ENABLE, QCH_CON_USI13_USI_QCH_CLOCK_REQ, QCH_CON_USI13_USI_QCH_EXPIRE_VAL, QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI15_USI_QCH, QCH_CON_USI15_USI_QCH_ENABLE, QCH_CON_USI15_USI_QCH_CLOCK_REQ, QCH_CON_USI15_USI_QCH_EXPIRE_VAL, QCH_CON_USI15_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI16_USI_QCH, QCH_CON_USI16_USI_QCH_ENABLE, QCH_CON_USI16_USI_QCH_CLOCK_REQ, QCH_CON_USI16_USI_QCH_EXPIRE_VAL, QCH_CON_USI16_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(USI9_USI_QCH, QCH_CON_USI9_USI_QCH_ENABLE, QCH_CON_USI9_USI_QCH_CLOCK_REQ, QCH_CON_USI9_USI_QCH_EXPIRE_VAL, QCH_CON_USI9_USI_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BIS_S2D_QCH, DMYQCH_CON_BIS_S2D_QCH_ENABLE, DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_LG_SCAN2DRAM_CU_QCH, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_LG_SCAN2DRAM_CU_QCH, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_LG_SCAN2DRAM_QCH, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_ENABLE, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_TNR_QCH, QCH_CON_D_TZPC_TNR_QCH_ENABLE, QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_TNR_QCH, QCH_CON_GPC_TNR_QCH_ENABLE, QCH_CON_GPC_TNR_QCH_CLOCK_REQ, QCH_CON_GPC_TNR_QCH_EXPIRE_VAL, QCH_CON_GPC_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_OTF_MCSC_TNR_QCH, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_ENABLE, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_MI_L_VO_DNS_TNR_QCH, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_ENABLE, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_TNR_GDC_QCH, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_OTF_TNR_MCSC_QCH, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AST_SI_L_VO_TNR_GDC_QCH, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_ENABLE, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_CLOCK_REQ, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D0_TNR_QCH, QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D1_TNR_QCH, QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D2_TNR_QCH, QCH_CON_LH_AXI_SI_D2_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D2_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D2_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D2_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D3_TNR_QCH, QCH_CON_LH_AXI_SI_D3_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D3_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D3_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D3_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_D4_TNR_QCH, QCH_CON_LH_AXI_SI_D4_TNR_QCH_ENABLE, QCH_CON_LH_AXI_SI_D4_TNR_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_D4_TNR_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_D4_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D0_TNR_QCH, QCH_CON_PPMU_D0_TNR_QCH_ENABLE, QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D1_TNR_QCH, QCH_CON_PPMU_D1_TNR_QCH_ENABLE, QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D2_TNR_QCH, QCH_CON_PPMU_D2_TNR_QCH_ENABLE, QCH_CON_PPMU_D2_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D2_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D2_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D3_TNR_QCH, QCH_CON_PPMU_D3_TNR_QCH_ENABLE, QCH_CON_PPMU_D3_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D3_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D3_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D4_TNR_QCH, QCH_CON_PPMU_D4_TNR_QCH_ENABLE, QCH_CON_PPMU_D4_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D4_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D4_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D5_TNR_QCH, QCH_CON_PPMU_D5_TNR_QCH_ENABLE, QCH_CON_PPMU_D5_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D5_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D5_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D6_TNR_QCH, QCH_CON_PPMU_D6_TNR_QCH_ENABLE, QCH_CON_PPMU_D6_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D6_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D6_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D7_TNR_QCH, QCH_CON_PPMU_D7_TNR_QCH_ENABLE, QCH_CON_PPMU_D7_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D7_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D7_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_D8_TNR_QCH, QCH_CON_PPMU_D8_TNR_QCH_ENABLE, QCH_CON_PPMU_D8_TNR_QCH_CLOCK_REQ, QCH_CON_PPMU_D8_TNR_QCH_EXPIRE_VAL, QCH_CON_PPMU_D8_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D0_TNR_QCH, QCH_CON_QE_D0_TNR_QCH_ENABLE, QCH_CON_QE_D0_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D0_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D1_TNR_QCH, QCH_CON_QE_D1_TNR_QCH_ENABLE, QCH_CON_QE_D1_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D1_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D5_TNR_QCH, QCH_CON_QE_D5_TNR_QCH_ENABLE, QCH_CON_QE_D5_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D5_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D5_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D6_TNR_QCH, QCH_CON_QE_D6_TNR_QCH_ENABLE, QCH_CON_QE_D6_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D6_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D6_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D7_TNR_QCH, QCH_CON_QE_D7_TNR_QCH_ENABLE, QCH_CON_QE_D7_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D7_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D7_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(QE_D8_TNR_QCH, QCH_CON_QE_D8_TNR_QCH_ENABLE, QCH_CON_QE_D8_TNR_QCH_CLOCK_REQ, QCH_CON_QE_D8_TNR_QCH_EXPIRE_VAL, QCH_CON_QE_D8_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_TNR_QCH, QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D0_TNR_QCH, QCH_CON_SSMT_D0_TNR_QCH_ENABLE, QCH_CON_SSMT_D0_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D0_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D0_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D1_TNR_QCH, QCH_CON_SSMT_D1_TNR_QCH_ENABLE, QCH_CON_SSMT_D1_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D1_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D1_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D2_TNR_QCH, QCH_CON_SSMT_D2_TNR_QCH_ENABLE, QCH_CON_SSMT_D2_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D2_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D2_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D3_TNR_QCH, QCH_CON_SSMT_D3_TNR_QCH_ENABLE, QCH_CON_SSMT_D3_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D3_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D3_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D4_TNR_QCH, QCH_CON_SSMT_D4_TNR_QCH_ENABLE, QCH_CON_SSMT_D4_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D4_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D4_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D5_TNR_QCH, QCH_CON_SSMT_D5_TNR_QCH_ENABLE, QCH_CON_SSMT_D5_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D5_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D5_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D6_TNR_QCH, QCH_CON_SSMT_D6_TNR_QCH_ENABLE, QCH_CON_SSMT_D6_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D6_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D6_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D7_TNR_QCH, QCH_CON_SSMT_D7_TNR_QCH_ENABLE, QCH_CON_SSMT_D7_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D7_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D7_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_D8_TNR_QCH, QCH_CON_SSMT_D8_TNR_QCH_ENABLE, QCH_CON_SSMT_D8_TNR_QCH_CLOCK_REQ, QCH_CON_SSMT_D8_TNR_QCH_EXPIRE_VAL, QCH_CON_SSMT_D8_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_TNR_QCH_S1, QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D0_TNR_QCH_S2, QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_TNR_QCH_S1, QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D1_TNR_QCH_S2, QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_TNR_QCH_S2, QCH_CON_SYSMMU_D2_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D2_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D2_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D2_TNR_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D2_TNR_QCH_S1, QCH_CON_SYSMMU_D2_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D2_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D2_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D2_TNR_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D3_TNR_QCH_S2, QCH_CON_SYSMMU_D3_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D3_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D3_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D3_TNR_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D3_TNR_QCH_S1, QCH_CON_SYSMMU_D3_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D3_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D3_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D3_TNR_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D4_TNR_QCH_S1, QCH_CON_SYSMMU_D4_TNR_QCH_S1_ENABLE, QCH_CON_SYSMMU_D4_TNR_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_D4_TNR_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_D4_TNR_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_D4_TNR_QCH_S2, QCH_CON_SYSMMU_D4_TNR_QCH_S2_ENABLE, QCH_CON_SYSMMU_D4_TNR_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_D4_TNR_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_D4_TNR_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_TNR_QCH, QCH_CON_SYSREG_TNR_QCH_ENABLE, QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TNR_QCH_C2, QCH_CON_TNR_QCH_C2_ENABLE, QCH_CON_TNR_QCH_C2_CLOCK_REQ, QCH_CON_TNR_QCH_C2_EXPIRE_VAL, QCH_CON_TNR_QCH_C2_IGNORE_FORCE_PM_EN), + CLK_QCH(TNR_QCH_ACLK, QCH_CON_TNR_QCH_ACLK_ENABLE, QCH_CON_TNR_QCH_ACLK_CLOCK_REQ, QCH_CON_TNR_QCH_ACLK_EXPIRE_VAL, QCH_CON_TNR_QCH_ACLK_IGNORE_FORCE_PM_EN), + CLK_QCH(TNR_CMU_TNR_QCH, QCH_CON_TNR_CMU_TNR_QCH_ENABLE, QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(BUSIF_HPMTPU_QCH, QCH_CON_BUSIF_HPMTPU_QCH_ENABLE, QCH_CON_BUSIF_HPMTPU_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMTPU_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMTPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(D_TZPC_TPU_QCH, QCH_CON_D_TZPC_TPU_QCH_ENABLE, QCH_CON_D_TZPC_TPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_TPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(GPC_TPU_QCH, QCH_CON_GPC_TPU_QCH_ENABLE, QCH_CON_GPC_TPU_QCH_CLOCK_REQ, QCH_CON_GPC_TPU_QCH_EXPIRE_VAL, QCH_CON_GPC_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ACEL_SI_D_TPU_QCH, QCH_CON_LH_ACEL_SI_D_TPU_QCH_ENABLE, QCH_CON_LH_ACEL_SI_D_TPU_QCH_CLOCK_REQ, QCH_CON_LH_ACEL_SI_D_TPU_QCH_EXPIRE_VAL, QCH_CON_LH_ACEL_SI_D_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT0_TPU_CPUCL0_QCH, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT1_TPU_CPUCL0_QCH, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_MI_P_TPU_CU_QCH, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_ENABLE, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(LH_AXI_SI_P_TPU_CU_QCH, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_ENABLE, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_CLOCK_REQ, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_EXPIRE_VAL, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(PPMU_TPU_QCH, QCH_CON_PPMU_TPU_QCH_ENABLE, QCH_CON_PPMU_TPU_QCH_CLOCK_REQ, QCH_CON_PPMU_TPU_QCH_EXPIRE_VAL, QCH_CON_PPMU_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SLH_AXI_MI_P_TPU_QCH, QCH_CON_SLH_AXI_MI_P_TPU_QCH_ENABLE, QCH_CON_SLH_AXI_MI_P_TPU_QCH_CLOCK_REQ, QCH_CON_SLH_AXI_MI_P_TPU_QCH_EXPIRE_VAL, QCH_CON_SLH_AXI_MI_P_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SSMT_TPU_QCH, QCH_CON_SSMT_TPU_QCH_ENABLE, QCH_CON_SSMT_TPU_QCH_CLOCK_REQ, QCH_CON_SSMT_TPU_QCH_EXPIRE_VAL, QCH_CON_SSMT_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_TPU_QCH_S1, QCH_CON_SYSMMU_TPU_QCH_S1_ENABLE, QCH_CON_SYSMMU_TPU_QCH_S1_CLOCK_REQ, QCH_CON_SYSMMU_TPU_QCH_S1_EXPIRE_VAL, QCH_CON_SYSMMU_TPU_QCH_S1_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSMMU_TPU_QCH_S2, QCH_CON_SYSMMU_TPU_QCH_S2_ENABLE, QCH_CON_SYSMMU_TPU_QCH_S2_CLOCK_REQ, QCH_CON_SYSMMU_TPU_QCH_S2_EXPIRE_VAL, QCH_CON_SYSMMU_TPU_QCH_S2_IGNORE_FORCE_PM_EN), + CLK_QCH(SYSREG_TPU_QCH, QCH_CON_SYSREG_TPU_QCH_ENABLE, QCH_CON_SYSREG_TPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_TPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TPU_QCH, DMYQCH_CON_TPU_QCH_ENABLE, DMYQCH_CON_TPU_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_TPU_QCH_IGNORE_FORCE_PM_EN), + CLK_QCH(TPU_CMU_TPU_QCH, QCH_CON_TPU_CMU_TPU_QCH_ENABLE, QCH_CON_TPU_CMU_TPU_QCH_CLOCK_REQ, QCH_CON_TPU_CMU_TPU_QCH_EXPIRE_VAL, QCH_CON_TPU_CMU_TPU_QCH_IGNORE_FORCE_PM_EN), +}; + +unsigned int cmucal_option_size = 44; +struct cmucal_option cmucal_option_list[] = { + CLK_OPTION(CTRL_OPTION_CMU_AOC, AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_APM, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_AUR, AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_BO, BO_CMU_BO_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BO_CMU_BO_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_TOP, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_CPUCL0, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_CPUCL2, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_CSIS, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_DISP, DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_DNS, DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_DPU, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_EH, EH_CMU_EH_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, EH_CMU_EH_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_G2D, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_G3AA, G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_G3D, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_GDC, GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_GSACORE, GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_GSACTRL, GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_HSI0, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_HSI1, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_HSI2, HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_IPP, IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_ITP, ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_MCSC, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_MFC, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_MISC, MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_NOCL0, NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_NOCL0, NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_NOCL01, NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_NOCL02, NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_NOCL03, NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_NOCL1A, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_NOCL1B, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_NOCL2A, NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_PDP, PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_PERIC0, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_PERIC1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_S2D, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_TNR, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), + CLK_OPTION(CTRL_OPTION_CMU_TPU, TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), +}; + diff --git a/drivers/soc/google/cal-if/gs201/cmucal-qch.h b/drivers/soc/google/cal-if/gs201/cmucal-qch.h new file mode 100644 index 000000000000..6bce620200ad --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-qch.h @@ -0,0 +1,1305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMUCAL_QCH_H__ +#define __CMUCAL_QCH_H__ + +#include "../cmucal.h" + +enum qch_id { + AOC_CMU_AOC_QCH = QCH_TYPE, + AOC_SYSCTRL_APB_QCH, + BAAW_AOC_QCH, + D_TZPC_AOC_QCH, + GPC_AOC_QCH, + LH_ATB_MI_LT_AOC_CD_QCH, + LH_ATB_SI_LT_AOC_QCH, + LH_ATB_SI_LT_AOC_CD_QCH, + LH_AXI_MI_LD_HSI0_AOC_QCH, + LH_AXI_MI_LP0_AOC_CD_QCH, + LH_AXI_MI_LP1_AOC_CD_QCH, + LH_AXI_MI_P_AOC_CU_QCH, + LH_AXI_SI_D_AOC_QCH, + LH_AXI_SI_LP0_AOC_CD_QCH, + LH_AXI_SI_LP1_AOC_CD_QCH, + LH_AXI_SI_P_AOC_CU_QCH, + PPMU_AOC_QCH, + PPMU_USB_QCH, + SLH_AXI_MI_LG_AOC_QCH, + SLH_AXI_MI_P_AOC_QCH, + SLH_AXI_SI_LP0_AOC_QCH, + SLH_AXI_SI_LP1_AOC_QCH, + SSMT_AOC_QCH, + SYSMMU_AOC_QCH_S1, + SYSMMU_AOC_QCH_S2, + SYSREG_AOC_QCH, + UASC_AOC_QCH, + APBIF_GPIO_ALIVE_QCH, + APBIF_GPIO_FAR_ALIVE_QCH, + APBIF_INTCOMB_VGPIO2AP_QCH, + APBIF_INTCOMB_VGPIO2APM_QCH, + APBIF_INTCOMB_VGPIO2PMU_QCH, + APBIF_PMU_ALIVE_QCH, + APBIF_RTC_QCH, + APBIF_TRTC_QCH, + APM_CMU_APM_QCH, + APM_I3C_PMIC_QCH_P, + APM_I3C_PMIC_QCH_S, + APM_USI0_UART_QCH, + APM_USI0_USI_QCH, + APM_USI1_UART_QCH, + D_TZPC_APM_QCH, + GPC_APM_QCH, + GREBEINTEGRATION_QCH_GREBE, + GREBEINTEGRATION_QCH_DBG, + INTMEM_QCH, + LH_AXI_MI_IG_SWD_QCH, + LH_AXI_MI_LG_DBGCORE_CD_QCH, + LH_AXI_MI_LG_SCAN2DRAM_CD_QCH, + LH_AXI_MI_LP0_AOC_CU_QCH, + LH_AXI_MI_P_ALIVE_CU_QCH, + LH_AXI_SI_D_APM_QCH, + LH_AXI_SI_LG_DBGCORE_CD_QCH, + LH_AXI_SI_LG_SCAN2DRAM_CD_QCH, + LH_AXI_SI_LP0_AOC_CU_QCH, + LH_AXI_SI_P_ALIVE_CU_QCH, + MAILBOX_APM_AOC_QCH, + MAILBOX_APM_AP_QCH, + MAILBOX_APM_AUR_QCH, + MAILBOX_APM_GSA_QCH, + MAILBOX_APM_SWD_QCH, + MAILBOX_APM_TPU_QCH, + MAILBOX_AP_AOCA32_QCH, + MAILBOX_AP_AOCF1_QCH, + MAILBOX_AP_AOCP6_QCH, + MAILBOX_AP_AUR0_QCH, + MAILBOX_AP_AUR1_QCH, + MAILBOX_AP_AUR2_QCH, + MAILBOX_AP_AUR3_QCH, + MAILBOX_AP_DBGCORE_QCH, + PMU_INTR_GEN_QCH, + ROM_CRC32_HOST_QCH, + RSTNSYNC_CLK_APM_GREBE_QCH, + RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH, + SLH_AXI_MI_LP0_AOC_QCH, + SLH_AXI_MI_P_ALIVE_QCH, + SLH_AXI_SI_LG_DBGCORE_QCH, + SLH_AXI_SI_LG_SCAN2DRAM_QCH, + SSMT_D_APM_QCH, + SSMT_LG_DBGCORE_QCH, + SS_DBGCORE_QCH_GREBE, + SS_DBGCORE_QCH_DBG, + SYSMMU_D_APM_QCH, + SYSREG_APM_QCH, + UASC_APM_QCH, + UASC_DBGCORE_QCH, + UASC_IG_SWD_QCH, + UASC_LP0_AOC_QCH, + UASC_P_ALIVE_QCH, + WDT_APM_QCH, + ADD_APBIF_AUR_QCH, + ADD_AUR_QCH, + AUR_QCH, + AUR_CMU_AUR_QCH, + BAAW_AUR_QCH, + D_TZPC_AUR_QCH, + GPC_AUR_QCH, + LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH, + LH_ATB_SI_LT_AUR_CPUCL0_QCH, + LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH, + LH_AXI_MI_P_AUR_CU_QCH, + LH_AXI_SI_D0_AUR_QCH, + LH_AXI_SI_D1_AUR_QCH, + LH_AXI_SI_P_AUR_CU_QCH, + PPMU_D0_AUR_QCH, + PPMU_D1_AUR_QCH, + SLH_AXI_MI_P_AUR_QCH, + SSMT_D0_AUR_QCH, + SSMT_D1_AUR_QCH, + SYSMMU_D0_AUR_WP_QCH_S1, + SYSMMU_D0_AUR_WP_QCH_S2, + SYSMMU_D1_AUR_WP_QCH_S1, + SYSMMU_D1_AUR_WP_QCH_S2, + SYSREG_AUR_QCH, + UASC_AUR_QCH, + BO_QCH, + BO_CMU_BO_QCH, + D_TZPC_BO_QCH, + GPC_BO_QCH, + LH_AXI_MI_IP_BO_QCH, + LH_AXI_SI_D_BO_QCH, + LH_AXI_SI_IP_BO_QCH, + PPMU_BO_QCH, + SLH_AXI_MI_P_BO_QCH, + SSMT_BO_QCH, + SYSMMU_BO_QCH_S1, + SYSMMU_BO_QCH_S2, + SYSREG_BO_QCH, + UASC_BO_QCH, + CMU_TOP_CMUREF_QCH, + DFTMUX_CMU_QCH_CIS_CLK0, + DFTMUX_CMU_QCH_CIS_CLK1, + DFTMUX_CMU_QCH_CIS_CLK2, + DFTMUX_CMU_QCH_CIS_CLK3, + DFTMUX_CMU_QCH_CIS_CLK4, + DFTMUX_CMU_QCH_CIS_CLK5, + DFTMUX_CMU_QCH_CIS_CLK6, + DFTMUX_CMU_QCH_CIS_CLK7, + OTP_QCH, + ADM_APB_G_CLUSTER0_QCH, + BPS_CPUCL0_QCH, + CLUSTER0_QCH_SCLK, + CLUSTER0_QCH_ATCLK, + CLUSTER0_QCH_GIC, + CLUSTER0_QCH_PCLK, + CLUSTER0_QCH_PERIPHCLK, + CLUSTER0_QCH_DBG_PD, + CLUSTER0_QCH_PDBGCLK, + CMU_CPUCL0_CMUREF_QCH, + CMU_CPUCL0_SHORTSTOP_QCH, + CPUCL0_CMU_CPUCL0_QCH, + CSSYS_QCH, + D_TZPC_CPUCL0_QCH, + GPC_CPUCL0_QCH, + HPM_APBIF_CPUCL0_QCH, + LH_ACE_SI_D0_CPUCL0_QCH, + LH_ACE_SI_D1_CPUCL0_QCH, + LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH, + LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH, + LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH, + LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH, + LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH, + LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH, + LH_ATB_MI_IT0_CLUSTER0_QCH, + LH_ATB_MI_IT1_CLUSTER0_QCH, + LH_ATB_MI_IT2_CLUSTER0_QCH, + LH_ATB_MI_IT3_CLUSTER0_QCH, + LH_ATB_MI_IT4_CLUSTER0_QCH, + LH_ATB_MI_IT5_CLUSTER0_QCH, + LH_ATB_MI_IT6_CLUSTER0_QCH, + LH_ATB_MI_IT7_CLUSTER0_QCH, + LH_ATB_MI_LT0_TPU_CPUCL0_QCH, + LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH, + LH_ATB_MI_LT1_TPU_CPUCL0_QCH, + LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH, + LH_ATB_MI_LT_AOC_QCH, + LH_ATB_MI_LT_AOC_CU_QCH, + LH_ATB_MI_LT_AUR_CPUCL0_QCH, + LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH, + LH_ATB_MI_LT_GSA_CPUCL0_QCH, + LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH, + LH_ATB_MI_T_BDU_QCH, + LH_ATB_MI_T_BDU_CU_QCH, + LH_ATB_MI_T_SLC_QCH, + LH_ATB_MI_T_SLC_CU_QCH, + LH_ATB_SI_IT0_CLUSTER0_QCH, + LH_ATB_SI_IT1_CLUSTER0_QCH, + LH_ATB_SI_IT2_CLUSTER0_QCH, + LH_ATB_SI_IT3_CLUSTER0_QCH, + LH_ATB_SI_IT4_CLUSTER0_QCH, + LH_ATB_SI_IT5_CLUSTER0_QCH, + LH_ATB_SI_IT6_CLUSTER0_QCH, + LH_ATB_SI_IT7_CLUSTER0_QCH, + LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH, + LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH, + LH_ATB_SI_LT_AOC_CU_QCH, + LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH, + LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH, + LH_ATB_SI_T_BDU_CU_QCH, + LH_ATB_SI_T_SLC_CU_QCH, + LH_AXI_MI_G_CSSYS_CD_QCH, + LH_AXI_MI_IG_CSSYS_QCH, + LH_AXI_MI_IG_DBGCORE_QCH, + LH_AXI_MI_IG_HSI0_QCH, + LH_AXI_MI_IG_STM_QCH, + LH_AXI_MI_LG_DBGCORE_CU_QCH, + LH_AXI_MI_LG_ETR_HSI0_CD_QCH, + LH_AXI_MI_P_CPUCL0_CU_QCH, + LH_AXI_SI_G_CSSYS_CD_QCH, + LH_AXI_SI_IG_CSSYS_QCH, + LH_AXI_SI_IG_DBGCORE_QCH, + LH_AXI_SI_IG_HSI0_QCH, + LH_AXI_SI_IG_STM_QCH, + LH_AXI_SI_LG_DBGCORE_CU_QCH, + LH_AXI_SI_LG_ETR_HSI0_CD_QCH, + LH_AXI_SI_P_CPUCL0_CU_QCH, + SLH_AXI_MI_LG_DBGCORE_QCH, + SLH_AXI_MI_P_CPUCL0_QCH, + SLH_AXI_SI_G_CSSYS_QCH, + SLH_AXI_SI_LG_ETR_HSI0_QCH, + SSMT_CPUCL0_QCH, + SYSMMU_S2_CPUCL0_QCH, + SYSREG_CPUCL0_QCH, + CMU_CPUCL1_CMUREF_QCH, + CMU_CPUCL1_SHORTSTOP_QCH, + CPUCL1_QCH_MID, + CPUCL1_CMU_CPUCL1_QCH, + CMU_CPUCL2_CMUREF_QCH, + CMU_CPUCL2_SHORTSTOP_QCH, + CPUCL2_QCH_BIG, + CPUCL2_CMU_CPUCL2_QCH, + CSISX8_QCH_C2_CSIS, + CSISX8_QCH_CSIS_DMA, + CSISX8_QCH_EBUF, + CSIS_CMU_CSIS_QCH, + D_TZPC_CSIS_QCH, + GPC_CSIS_QCH, + LH_AST_MI_L_OTF0_PDP_CSIS_QCH, + LH_AST_MI_L_OTF1_PDP_CSIS_QCH, + LH_AST_MI_L_OTF2_PDP_CSIS_QCH, + LH_AST_MI_L_SOTF0_IPP_CSIS_QCH, + LH_AST_MI_L_SOTF1_IPP_CSIS_QCH, + LH_AST_MI_L_SOTF2_IPP_CSIS_QCH, + LH_AST_MI_L_VO_MCSC_CSIS_QCH, + LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH, + LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH, + LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH, + LH_AST_SI_L_OTF0_CSIS_PDP_QCH, + LH_AST_SI_L_OTF1_CSIS_PDP_QCH, + LH_AST_SI_L_OTF2_CSIS_PDP_QCH, + LH_AST_SI_L_VO_CSIS_PDP_QCH, + LH_AXI_MI_LD_PDP_CSIS_QCH, + LH_AXI_SI_D0_CSIS_QCH, + LH_AXI_SI_D1_CSIS_QCH, + MIPI_PHY_LINK_WRAP_QCH_CSIS0, + MIPI_PHY_LINK_WRAP_QCH_CSIS1, + MIPI_PHY_LINK_WRAP_QCH_CSIS2, + MIPI_PHY_LINK_WRAP_QCH_CSIS3, + MIPI_PHY_LINK_WRAP_QCH_CSIS4, + MIPI_PHY_LINK_WRAP_QCH_CSIS5, + MIPI_PHY_LINK_WRAP_QCH_CSIS6, + MIPI_PHY_LINK_WRAP_QCH_CSIS7, + PPMU_D0_QCH, + PPMU_D1_QCH, + QE_CSIS_DMA0_QCH, + QE_CSIS_DMA1_QCH, + QE_CSIS_DMA2_QCH, + QE_CSIS_DMA3_QCH, + QE_STRP0_QCH, + QE_STRP1_QCH, + QE_STRP2_QCH, + QE_ZSL0_QCH, + QE_ZSL1_QCH, + QE_ZSL2_QCH, + SLH_AXI_MI_P_CSIS_QCH, + SSMT_D0_QCH, + SSMT_D1_QCH, + SYSMMU_D0_CSIS_QCH_S1, + SYSMMU_D0_CSIS_QCH_S2, + SYSMMU_D1_CSIS_QCH_S1, + SYSMMU_D1_CSIS_QCH_S2, + SYSREG_CSIS_QCH, + DISP_CMU_DISP_QCH, + DPUB_QCH, + D_TZPC_DISP_QCH, + GPC_DISP_QCH, + SLH_AXI_MI_P_DISP_QCH, + SYSREG_DISP_QCH, + DNS_QCH_00, + DNS_QCH_01, + DNS_CMU_DNS_QCH, + D_TZPC_DNS_QCH, + GPC_DNS_QCH, + LH_AST_MI_L_OTF_IPP_DNS_QCH, + LH_AST_MI_L_OTF_ITP_DNS_QCH, + LH_AST_MI_L_VO_IPP_DNS_QCH, + LH_AST_SI_L_OTF0_DNS_ITP_QCH, + LH_AST_SI_L_OTF0_DNS_MCSC_QCH, + LH_AST_SI_L_OTF1_DNS_ITP_QCH, + LH_AST_SI_L_OTF1_DNS_MCSC_QCH, + LH_AST_SI_L_OTF2_DNS_MCSC_QCH, + LH_AST_SI_L_OTF_DNS_GDC_QCH, + LH_AST_SI_L_VO_DNS_TNR_QCH, + LH_AXI_MI_LD_IPP_DNS_QCH, + LH_AXI_MI_LD_ITP_DNS_QCH, + LH_AXI_MI_LD_MCSC_DNS_QCH, + LH_AXI_MI_LD_PDP_DNS_QCH, + LH_AXI_SI_D_DNS_QCH, + PPMU_D0_DNS_QCH, + PPMU_D1_DNS_QCH, + QE_D0_DNS_QCH, + QE_D1_DNS_QCH, + SLH_AXI_MI_P_DNS_QCH, + SSMT_D0_DNS_QCH, + SSMT_D1_DNS_QCH, + SYSMMU_DNS_QCH_S1, + SYSMMU_DNS_QCH_S2, + SYSREG_DNS_QCH, + DPUF_QCH_DPU_DMA, + DPUF_QCH_DPU_DPP, + DPU_CMU_DPU_QCH, + D_TZPC_DPU_QCH, + GPC_DPU_QCH, + LH_AXI_SI_D0_DPU_QCH, + LH_AXI_SI_D1_DPU_QCH, + LH_AXI_SI_D2_DPU_QCH, + PPMU_DPUD0_QCH, + PPMU_DPUD1_QCH, + PPMU_DPUD2_QCH, + SLH_AXI_MI_P_DPU_QCH, + SSMT_DPU0_QCH, + SSMT_DPU1_QCH, + SSMT_DPU2_QCH, + SYSMMU_DPUD0_QCH_S1, + SYSMMU_DPUD0_QCH_S2, + SYSMMU_DPUD1_QCH_S1, + SYSMMU_DPUD1_QCH_S2, + SYSMMU_DPUD2_QCH_S1, + SYSMMU_DPUD2_QCH_S2, + SYSREG_DPU_QCH, + D_TZPC_EH_QCH, + EH_QCH, + EH_CMU_EH_QCH, + GPC_EH_QCH, + LH_ACEL_SI_D_EH_QCH, + LH_AXI_MI_IP_EH_QCH, + LH_AXI_MI_P_EH_CU_QCH, + LH_AXI_SI_IP_EH_QCH, + LH_AXI_SI_P_EH_CU_QCH, + PPMU_EH_QCH, + QE_EH_QCH, + SLH_AXI_MI_P_EH_QCH, + SSMT_EH_QCH, + SYSMMU_EH_QCH, + SYSREG_EH_QCH, + UASC_EH_QCH, + D_TZPC_G2D_QCH, + G2D_QCH, + G2D_CMU_G2D_QCH, + GPC_G2D_QCH, + JPEG_QCH, + LH_ACEL_SI_D2_G2D_QCH, + LH_AXI_SI_D0_G2D_QCH, + LH_AXI_SI_D1_G2D_QCH, + PPMU_D0_G2D_QCH, + PPMU_D1_G2D_QCH, + PPMU_D2_G2D_QCH, + SLH_AXI_MI_P_G2D_QCH, + SSMT_D0_G2D_QCH, + SSMT_D1_G2D_QCH, + SSMT_D2_G2D_QCH, + SYSMMU_D0_G2D_QCH_0, + SYSMMU_D0_G2D_QCH_1, + SYSMMU_D1_G2D_QCH_0, + SYSMMU_D1_G2D_QCH_1, + SYSMMU_D2_G2D_QCH_0, + SYSMMU_D2_G2D_QCH_1, + SYSREG_G2D_QCH, + D_TZPC_G3AA_QCH, + G3AA_QCH, + G3AA_CMU_G3AA_QCH, + GPC_G3AA_QCH, + LH_AST_MI_L_OTF0_PDP_G3AA_QCH, + LH_AST_MI_L_OTF1_PDP_G3AA_QCH, + LH_AST_MI_L_OTF2_PDP_G3AA_QCH, + LH_AST_MI_L_YOTF0_PDP_G3AA_QCH, + LH_AST_MI_L_YOTF1_PDP_G3AA_QCH, + LH_AXI_SI_D_G3AA_QCH, + PPMU_G3AA_QCH, + SLH_AXI_MI_P_G3AA_QCH, + SSMT_G3AA_QCH, + SYSMMU_G3AA_QCH_S1, + SYSMMU_G3AA_QCH_S2, + SYSREG_G3AA_QCH, + ADD_APBIF_G3D_QCH, + ADD_G3D_QCH, + ADM_AHB_G_GPU_QCH, + ASB_G3D_QCH_LH_D0_G3D, + ASB_G3D_QCH_LH_D1_G3D, + ASB_G3D_QCH_LH_D2_G3D, + ASB_G3D_QCH_LH_D3_G3D, + BUSIF_HPMG3D_QCH, + D_TZPC_G3D_QCH, + G3D_CMU_G3D_QCH, + GPC_G3D_QCH, + GPU_QCH, + LH_AXI_MI_IP_G3D_QCH, + LH_AXI_MI_P_G3D_CU_QCH, + LH_AXI_SI_IP_G3D_QCH, + LH_AXI_SI_P_G3D_CU_QCH, + RSTNSYNC_CLK_G3D_DD_QCH, + SLH_AXI_MI_P_G3D_QCH, + SYSREG_G3D_QCH, + UASC_G3D_QCH, + D_TZPC_GDC_QCH, + GDC0_QCH_CLK, + GDC0_QCH_C2CLK, + GDC1_QCH_CLK, + GDC1_QCH_C2CLK, + GDC_CMU_GDC_QCH, + GPC_GDC_QCH, + LH_AST_MI_I_GDC0_GDC1_QCH, + LH_AST_MI_I_GDC1_SCSC_QCH, + LH_AST_MI_L_OTF_DNS_GDC_QCH, + LH_AST_MI_L_OTF_TNR_GDC_QCH, + LH_AST_MI_L_VO_TNR_GDC_QCH, + LH_AST_SI_I_GDC0_GDC1_QCH, + LH_AST_SI_I_GDC1_SCSC_QCH, + LH_AST_SI_L_VO_GDC_MCSC_QCH, + LH_AXI_MI_ID_SCSC_GDC1_QCH, + LH_AXI_SI_D0_GDC_QCH, + LH_AXI_SI_D1_GDC_QCH, + LH_AXI_SI_D2_GDC_QCH, + LH_AXI_SI_ID_SCSC_GDC1_QCH, + PPMU_D0_GDC_QCH, + PPMU_D0_SCSC_QCH, + PPMU_D1_GDC_QCH, + PPMU_D1_SCSC_QCH, + PPMU_D2_GDC_QCH, + PPMU_D2_SCSC_QCH, + PPMU_D3_GDC_QCH, + QE_D0_GDC_QCH, + QE_D0_SCSC_QCH, + QE_D1_GDC_QCH, + QE_D1_SCSC_QCH, + QE_D2_GDC_QCH, + QE_D2_SCSC_QCH, + QE_D3_GDC_QCH, + SCSC_QCH_CLK, + SCSC_QCH_C2CLK, + SLH_AXI_MI_P_GDC_QCH, + SSMT_D0_GDC_QCH, + SSMT_D0_SCSC_QCH, + SSMT_D1_GDC_QCH, + SSMT_D1_SCSC_QCH, + SSMT_D2_GDC_QCH, + SSMT_D2_SCSC_QCH, + SSMT_D3_GDC_QCH, + SYSMMU_D0_GDC_QCH_S1, + SYSMMU_D0_GDC_QCH_S2, + SYSMMU_D1_GDC_QCH_S1, + SYSMMU_D1_GDC_QCH_S2, + SYSMMU_D2_GDC_QCH_S1, + SYSMMU_D2_GDC_QCH_S2, + SYSREG_GDC_QCH, + AD_APB_SYSMMU_GSACORE_NS_QCH, + BAAW_GSACORE_QCH, + CA32_GSACORE_QCH, + DMA_GSACORE_QCH, + GIC_GSACORE_QCH, + GPIO_GSACORE_QCH, + GSACORE_CMU_GSACORE_QCH, + INTMEM_GSACORE_QCH, + KDN_GSACORE_QCH, + LH_AST_MI_I_CA32_GIC_QCH, + LH_AST_MI_I_GIC_CA32_QCH, + LH_AST_SI_I_CA32_GIC_QCH, + LH_AST_SI_I_GIC_CA32_QCH, + LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH, + LH_ATB_SI_LT_GSA_CPUCL0_QCH, + LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH, + LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH, + LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH, + LH_AXI_MI_IP_GME_QCH, + LH_AXI_MI_I_DAP_GSA_QCH, + LH_AXI_SI_D_GSA_QCH, + LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH, + LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH, + LH_AXI_SI_IP_GME_QCH, + LH_AXI_SI_IP_GSA_QCH, + OTP_CON_GSACORE_QCH, + PPMU_GSACORE_QCH, + PUF_GSACORE_QCH, + QE_CA32_GSACORE_QCH, + QE_DMA_GSACORE_QCH, + QE_SSS_GSACORE_QCH, + RESETMON_GSACORE_QCH, + RSTNSYNC_CLK_SSS_ARESETN_QCH, + RSTNSYNC_CLK_SSS_HRESETN_QCH, + RSTNSYNC_CLK_SSS_PORRESETN_QCH, + SPI_FPS_GSACORE_QCH, + SPI_GSC_GSACORE_QCH, + SSMT_GSACORE_QCH, + SSS_GSACORE_QCH, + SYSMMU_GSACORE_QCH_S1, + SYSMMU_GSACORE_QCH_S2, + SYSREG_GSACORE_QCH, + UART_GSACORE_QCH, + WDT_GSACORE_QCH, + UDAP_SSS_AHB_ASYNC_QCH, + UGME_QCH, + APBIF_GPIO_GSACTRL_QCH, + DAP_GSACTRL_QCH, + GPC_GSACTRL_QCH, + GSACTRL_CMU_GSACTRL_QCH, + INTMEM_GSACTRL_QCH, + LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH, + LH_AXI_MI_IP_GSA_QCH, + LH_AXI_MI_P_GSA_CU_QCH, + LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH, + LH_AXI_SI_I_DAP_GSA_QCH, + LH_AXI_SI_P_GSA_CU_QCH, + MAILBOX_GSA2AOC_QCH, + MAILBOX_GSA2AUR_QCH, + MAILBOX_GSA2NONTZ_QCH, + MAILBOX_GSA2TPU_QCH, + MAILBOX_GSA2TZ_QCH, + PMU_GSA_QCH, + SECJTAG_GSACTRL_QCH, + SLH_AXI_MI_P_GSA_QCH, + SYSREG_GSACTRL_QCH, + SYSREG_GSACTRLEXT_QCH, + TIMER_GSACTRL_QCH, + TZPC_GSACTRL_QCH, + DP_LINK_QCH_PCLK, + DP_LINK_QCH_GTC_CLK, + D_TZPC_HSI0_QCH, + ETR_MIU_QCH_ACLK, + ETR_MIU_QCH_PCLK, + GPC_HSI0_QCH, + HSI0_CMU_HSI0_QCH, + LH_ACEL_SI_D_HSI0_QCH, + LH_AXI_MI_LG_ETR_HSI0_CU_QCH, + LH_AXI_MI_LP1_AOC_CU_QCH, + LH_AXI_MI_P_HSI0_CU_QCH, + LH_AXI_SI_LD_HSI0_AOC_QCH, + LH_AXI_SI_LG_ETR_HSI0_CU_QCH, + LH_AXI_SI_LP1_AOC_CU_QCH, + LH_AXI_SI_P_HSI0_CU_QCH, + PPMU_HSI0_AOC_QCH, + PPMU_HSI0_NOCL1B_QCH, + SLH_AXI_MI_LG_ETR_HSI0_QCH, + SLH_AXI_MI_LP1_AOC_QCH, + SLH_AXI_MI_P_HSI0_QCH, + SSMT_USB_QCH, + SYSMMU_USB_QCH_S2, + SYSMMU_USB_QCH_S1, + SYSREG_HSI0_QCH, + UASC_HSI0_CTRL_QCH, + UASC_HSI0_LINK_QCH, + USB31DRD_QCH_REF, + USB31DRD_QCH_SLV_CTRL, + USB31DRD_QCH_SLV_LINK, + USB31DRD_QCH_APB, + USB31DRD_QCH_PCS, + USB31DRD_QCH_DBG, + USB31DRD_QCH, + D_TZPC_HSI1_QCH, + GPC_HSI1_QCH, + GPIO_HSI1_QCH, + HSI1_CMU_HSI1_QCH, + LH_ACEL_SI_D_HSI1_QCH, + LH_AXI_MI_P_HSI1_CU_QCH, + LH_AXI_SI_P_HSI1_CU_QCH, + PCIE_GEN4_0_QCH_DBG_1, + PCIE_GEN4_0_QCH_AXI_1, + PCIE_GEN4_0_QCH_APB_1, + PCIE_GEN4_0_QCH_SCLK_1, + PCIE_GEN4_0_QCH_PCS_APB, + PCIE_GEN4_0_QCH_PMA_APB, + PCIE_GEN4_0_QCH_DBG_2, + PCIE_GEN4_0_QCH_AXI_2, + PCIE_GEN4_0_QCH_APB_2, + PCIE_GEN4_0_QCH_UDBG, + PCIE_GEN4_0_QCH, + PCIE_IA_GEN4A_0_QCH, + PCIE_IA_GEN4B_0_QCH, + PPMU_HSI1_QCH, + QE_PCIE_GEN4A_HSI1_QCH, + QE_PCIE_GEN4B_HSI1_QCH, + SLH_AXI_MI_P_HSI1_QCH, + SSMT_HSI1_QCH, + SSMT_PCIE_IA_GEN4A_0_QCH, + SSMT_PCIE_IA_GEN4B_0_QCH, + SYSMMU_HSI1_QCH_S2, + SYSMMU_HSI1_QCH_S1, + SYSREG_HSI1_QCH, + UASC_PCIE_GEN4A_DBI_0_QCH, + UASC_PCIE_GEN4A_SLV_0_QCH, + UASC_PCIE_GEN4B_DBI_0_QCH, + UASC_PCIE_GEN4B_SLV_0_QCH, + D_TZPC_HSI2_QCH, + GPC_HSI2_QCH, + GPIO_HSI2_QCH, + GPIO_HSI2UFS_QCH, + HSI2_CMU_HSI2_QCH, + LH_ACEL_SI_D_HSI2_QCH, + LH_AXI_MI_P_HSI2_CU_QCH, + LH_AXI_SI_P_HSI2_CU_QCH, + MMC_CARD_QCH, + PCIE_GEN4_1_QCH_AXI_1, + PCIE_GEN4_1_QCH_APB_1, + PCIE_GEN4_1_QCH_DBG_1, + PCIE_GEN4_1_QCH_PCS_APB, + PCIE_GEN4_1_QCH_REF0, + PCIE_GEN4_1_QCH_PMA_APB, + PCIE_GEN4_1_QCH_AXI_2, + PCIE_GEN4_1_QCH_DBG_2, + PCIE_GEN4_1_QCH_APB_2, + PCIE_GEN4_1_QCH_UDBG, + PCIE_GEN4_1_QCH_REF1, + PCIE_IA_GEN4A_1_QCH, + PCIE_IA_GEN4B_1_QCH, + PPMU_HSI2_QCH, + QE_MMC_CARD_HSI2_QCH, + QE_PCIE_GEN4A_HSI2_QCH, + QE_PCIE_GEN4B_HSI2_QCH, + QE_UFS_EMBD_HSI2_QCH, + SLH_AXI_MI_P_HSI2_QCH, + SSMT_HSI2_QCH, + SSMT_PCIE_IA_GEN4A_1_QCH, + SSMT_PCIE_IA_GEN4B_1_QCH, + SYSMMU_HSI2_QCH_S2, + SYSMMU_HSI2_QCH_S1, + SYSREG_HSI2_QCH, + UASC_PCIE_GEN4A_DBI_1_QCH, + UASC_PCIE_GEN4A_SLV_1_QCH, + UASC_PCIE_GEN4B_DBI_1_QCH, + UASC_PCIE_GEN4B_SLV_1_QCH, + UFS_EMBD_QCH, + UFS_EMBD_QCH_FMP, + D_TZPC_IPP_QCH, + GPC_IPP_QCH, + IPP_CMU_IPP_QCH, + LH_AST_MI_L_OTF0_PDP_IPP_QCH, + LH_AST_MI_L_OTF1_PDP_IPP_QCH, + LH_AST_MI_L_OTF2_PDP_IPP_QCH, + LH_AST_MI_L_VO_PDP_IPP_QCH, + LH_AST_SI_L_OTF_IPP_DNS_QCH, + LH_AST_SI_L_SOTF0_IPP_CSIS_QCH, + LH_AST_SI_L_SOTF1_IPP_CSIS_QCH, + LH_AST_SI_L_SOTF2_IPP_CSIS_QCH, + LH_AST_SI_L_VO_IPP_DNS_QCH, + LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH, + LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH, + LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH, + LH_AXI_SI_D_IPP_QCH, + LH_AXI_SI_LD_IPP_DNS_QCH, + PPMU_IPP_QCH, + PPMU_MSA_QCH, + QE_ALIGN0_QCH, + QE_ALIGN1_QCH, + QE_ALIGN2_QCH, + QE_ALIGN3_QCH, + QE_ALN_STAT_QCH, + QE_FDPIG_QCH, + QE_RGBH0_QCH, + QE_RGBH1_QCH, + QE_RGBH2_QCH, + QE_THSTAT_QCH, + QE_TNR_MSA0_QCH, + QE_TNR_MSA1_QCH, + SIPU_IPP_QCH, + SLH_AXI_MI_P_IPP_QCH, + SSMT_ALIGN0_QCH, + SSMT_ALIGN1_QCH, + SSMT_ALIGN2_QCH, + SSMT_ALIGN3_QCH, + SSMT_ALN_STAT_QCH, + SSMT_FDPIG_QCH, + SSMT_RGBH0_QCH, + SSMT_RGBH1_QCH, + SSMT_RGBH2_QCH, + SSMT_THSTAT_QCH, + SSMT_TNR_MSA0_QCH, + SSMT_TNR_MSA1_QCH, + SYSMMU_IPP_QCH_S1, + SYSMMU_IPP_QCH_S2, + SYSREG_IPP_QCH, + TNR_A_QCH, + D_TZPC_ITP_QCH, + GPC_ITP_QCH, + ITP_QCH, + ITP_CMU_ITP_QCH, + LH_AST_MI_L_OTF0_DNS_ITP_QCH, + LH_AST_MI_L_OTF1_DNS_ITP_QCH, + LH_AST_SI_L_OTF_ITP_DNS_QCH, + LH_AXI_SI_LD_ITP_DNS_QCH, + PPMU_ITP_QCH, + QE_ITP_QCH, + SLH_AXI_MI_P_ITP_QCH, + SSMT_ITP_QCH, + SYSREG_ITP_QCH, + C2R_MCSC_QCH, + D_TZPC_MCSC_QCH, + GPC_MCSC_QCH, + ITSC_QCH_CLK, + ITSC_QCH_C2, + LH_AST_MI_I_ITSC_MCSC_QCH, + LH_AST_MI_L_OTF0_DNS_MCSC_QCH, + LH_AST_MI_L_OTF1_DNS_MCSC_QCH, + LH_AST_MI_L_OTF2_DNS_MCSC_QCH, + LH_AST_MI_L_OTF_TNR_MCSC_QCH, + LH_AST_MI_L_VO_GDC_MCSC_QCH, + LH_AST_SI_I_ITSC_MCSC_QCH, + LH_AST_SI_L_OTF_MCSC_TNR_QCH, + LH_AST_SI_L_VO_MCSC_CSIS_QCH, + LH_AXI_SI_D0_MCSC_QCH, + LH_AXI_SI_D1_MCSC_QCH, + LH_AXI_SI_D2_MCSC_QCH, + LH_AXI_SI_LD_MCSC_DNS_QCH, + MCSC_QCH_CLK, + MCSC_QCH_C2CLK, + MCSC_CMU_MCSC_QCH, + PPMU_D0_ITSC_QCH, + PPMU_D0_MCSC_QCH, + PPMU_D1_ITSC_QCH, + PPMU_D1_MCSC_QCH, + QE_D0_MCSC_QCH, + QE_D1_ITSC_QCH, + QE_D1_MCSC_QCH, + QE_D2_ITSC_QCH, + QE_D2_MCSC_QCH, + QE_D3_ITSC_QCH, + QE_D3_MCSC_QCH, + QE_D4_MCSC_QCH, + QE_D5_MCSC_QCH, + SLH_AXI_MI_P_MCSC_QCH, + SSMT_D0_ITSC_QCH, + SSMT_D0_MCSC_QCH, + SSMT_D1_ITSC_QCH, + SSMT_D1_MCSC_QCH, + SYSMMU_D0_MCSC_QCH_S1, + SYSMMU_D0_MCSC_QCH_S2, + SYSMMU_D1_MCSC_QCH_S1, + SYSMMU_D1_MCSC_QCH_S2, + SYSMMU_D2_MCSC_QCH_S1, + SYSMMU_D2_MCSC_QCH_S2, + SYSREG_MCSC_QCH, + D_TZPC_MFC_QCH, + GPC_MFC_QCH, + LH_AXI_SI_D0_MFC_QCH, + LH_AXI_SI_D1_MFC_QCH, + MFC_QCH, + MFC_CMU_MFC_QCH, + PPMU_D0_MFC_QCH, + PPMU_D1_MFC_QCH, + RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH, + SLH_AXI_MI_P_MFC_QCH, + SSMT_D0_MFC_QCH, + SSMT_D1_MFC_QCH, + SYSMMU_D0_MFC_QCH_0, + SYSMMU_D0_MFC_QCH_1, + SYSMMU_D1_MFC_QCH_0, + SYSMMU_D1_MFC_QCH_1, + SYSREG_MFC_QCH, + APBBR_DDRPHY_QCH, + APBBR_DMC_QCH, + CMU_MIF_CMUREF_QCH, + DMC_QCH, + D_TZPC_MIF_QCH, + GEN_WREN_SECURE_QCH, + GPC_MIF_QCH, + LH_AST_MI_G_DMC_CD_QCH, + LH_AST_SI_G_DMC_QCH, + LH_AST_SI_G_DMC_CD_QCH, + LH_AXI_MI_P_MIF_CU_QCH, + LH_AXI_SI_P_MIF_CU_QCH, + MIF_CMU_MIF_QCH, + QCH_ADAPTER_PPC_DEBUG_QCH, + SLH_AXI_MI_P_MIF_QCH, + SYSREG_MIF_QCH, + ADM_AHB_G_SSS_QCH, + DIT_QCH, + D_TZPC_MISC_QCH, + GIC_QCH, + GPC_MISC_QCH, + LH_ACEL_SI_D_MISC_QCH, + LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH, + LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH, + LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH, + LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH, + LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH, + LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH, + LH_AXI_MI_ID_SSS_QCH, + LH_AXI_MI_P_GIC_CU_QCH, + LH_AXI_MI_P_MISC_CU_QCH, + LH_AXI_SI_ID_SSS_QCH, + LH_AXI_SI_P_GIC_CU_QCH, + LH_AXI_SI_P_MISC_CU_QCH, + MCT_QCH, + MISC_CMU_MISC_QCH, + OTP_CON_BIRA_QCH, + OTP_CON_BISR_QCH, + OTP_CON_TOP_QCH, + PDMA0_QCH, + PDMA1_QCH, + PPMU_MISC_QCH, + PUF_QCH, + QE_DIT_QCH, + QE_PDMA0_QCH, + QE_PDMA1_QCH, + QE_RTIC_QCH, + QE_SPDMA0_QCH, + QE_SPDMA1_QCH, + QE_SSS_QCH, + RTIC_QCH, + SLH_AXI_MI_P_GIC_QCH, + SLH_AXI_MI_P_MISC_QCH, + SPDMA0_QCH, + SPDMA1_QCH, + SSMT_DIT_QCH, + SSMT_PDMA0_QCH, + SSMT_PDMA1_QCH, + SSMT_RTIC_QCH, + SSMT_SPDMA0_QCH, + SSMT_SPDMA1_QCH, + SSMT_SSS_QCH, + SSS_QCH, + SYSMMU_MISC_QCH, + SYSMMU_SSS_QCH, + SYSREG_MISC_QCH, + TMU_SUB_QCH, + TMU_TOP_QCH, + WDT_CLUSTER0_QCH, + WDT_CLUSTER1_QCH, + ASYNCSFR_WR_SMC_QCH, + BDU_QCH, + CCI_QCH, + CMU_NOCL0_CMUREF_QCH, + CPE425_QCH, + D_TZPC_NOCL0_QCH, + GPC_NOCL0_QCH, + LH_ACEL_MI_D_EH_QCH, + LH_ACE_MI_D0_CPUCL0_QCH, + LH_ACE_MI_D1_CPUCL0_QCH, + LH_AST_MI_G_DMC0_QCH, + LH_AST_MI_G_DMC0_CU_QCH, + LH_AST_MI_G_DMC1_QCH, + LH_AST_MI_G_DMC1_CU_QCH, + LH_AST_MI_G_DMC2_QCH, + LH_AST_MI_G_DMC2_CU_QCH, + LH_AST_MI_G_DMC3_QCH, + LH_AST_MI_G_DMC3_CU_QCH, + LH_AST_MI_G_NOCL1A_QCH, + LH_AST_MI_G_NOCL1A_CU_QCH, + LH_AST_MI_G_NOCL1B_QCH, + LH_AST_MI_G_NOCL1B_CU_QCH, + LH_AST_MI_G_NOCL2A_QCH, + LH_AST_MI_G_NOCL2A_CU_QCH, + LH_AST_SI_G_DMC0_CU_QCH, + LH_AST_SI_G_DMC1_CU_QCH, + LH_AST_SI_G_DMC2_CU_QCH, + LH_AST_SI_G_DMC3_CU_QCH, + LH_AST_SI_G_NOCL1A_CU_QCH, + LH_AST_SI_G_NOCL1B_CU_QCH, + LH_AST_SI_G_NOCL2A_CU_QCH, + LH_ATB_MI_T_BDU_CD_QCH, + LH_ATB_MI_T_SLC_CD_QCH, + LH_ATB_SI_T_BDU_QCH, + LH_ATB_SI_T_BDU_CD_QCH, + LH_ATB_SI_T_SLC_QCH, + LH_ATB_SI_T_SLC_CD_QCH, + LH_AXI_MI_P_ALIVE_CD_QCH, + LH_AXI_MI_P_CPUCL0_CD_QCH, + LH_AXI_MI_P_EH_CD_QCH, + LH_AXI_MI_P_GIC_CD_QCH, + LH_AXI_MI_P_MIF0_CD_QCH, + LH_AXI_MI_P_MIF1_CD_QCH, + LH_AXI_MI_P_MIF2_CD_QCH, + LH_AXI_MI_P_MIF3_CD_QCH, + LH_AXI_MI_P_MISC_CD_QCH, + LH_AXI_MI_P_PERIC0_CD_QCH, + LH_AXI_MI_P_PERIC1_CD_QCH, + LH_AXI_SI_P_ALIVE_CD_QCH, + LH_AXI_SI_P_CPUCL0_CD_QCH, + LH_AXI_SI_P_EH_CD_QCH, + LH_AXI_SI_P_GIC_CD_QCH, + LH_AXI_SI_P_MIF0_CD_QCH, + LH_AXI_SI_P_MIF1_CD_QCH, + LH_AXI_SI_P_MIF2_CD_QCH, + LH_AXI_SI_P_MIF3_CD_QCH, + LH_AXI_SI_P_MISC_CD_QCH, + LH_AXI_SI_P_PERIC0_CD_QCH, + LH_AXI_SI_P_PERIC1_CD_QCH, + NOCL0_CMU_NOCL0_QCH, + PPC_CCI_M1_CYCLE_QCH, + PPC_CCI_M1_EVENT_QCH, + PPC_CCI_M2_EVENT_QCH, + PPC_CCI_M3_EVENT_QCH, + PPC_CCI_M4_EVENT_QCH, + PPC_CPUCL0_D0_CYCLE_QCH, + PPC_CPUCL0_D0_EVENT_QCH, + PPC_CPUCL0_D1_EVENT_QCH, + PPC_DBG_CC_QCH, + PPC_EH_CYCLE_QCH, + PPC_EH_EVENT_QCH, + PPC_IO_CYCLE_QCH, + PPC_IO_EVENT_QCH, + PPC_NOCL1A_M0_CYCLE_QCH, + PPC_NOCL1A_M0_EVENT_QCH, + PPC_NOCL1A_M1_EVENT_QCH, + PPC_NOCL1A_M2_EVENT_QCH, + PPC_NOCL1A_M3_EVENT_QCH, + PPC_NOCL1B_M0_CYCLE_QCH, + PPC_NOCL1B_M0_EVENT_QCH, + PPMU_ACE_CPUCL0_D0_QCH, + PPMU_ACE_CPUCL0_D1_QCH, + SFR_APBIF_CMU_TOPC_QCH, + SLC_CB_TOP_QCH, + SLC_CH1_QCH, + SLC_CH2_QCH, + SLC_CH3_QCH, + SLC_CH_TOP_QCH, + SLH_AXI_MI_G_NOCL0_QCH, + SLH_AXI_SI_P_ALIVE_QCH, + SLH_AXI_SI_P_CPUCL0_QCH, + SLH_AXI_SI_P_EH_QCH, + SLH_AXI_SI_P_GIC_QCH, + SLH_AXI_SI_P_MIF0_QCH, + SLH_AXI_SI_P_MIF1_QCH, + SLH_AXI_SI_P_MIF2_QCH, + SLH_AXI_SI_P_MIF3_QCH, + SLH_AXI_SI_P_MISC_QCH, + SLH_AXI_SI_P_PERIC0_QCH, + SLH_AXI_SI_P_PERIC1_QCH, + SYSREG_NOCL0_QCH, + TREX_D_NOCL0_QCH, + TREX_P_NOCL0_QCH, + CMU_NOCL1A_CMUREF_QCH, + D_TZPC_NOCL1A_QCH, + GPC_NOCL1A_QCH, + LH_ACEL_MI_D0_G3D_QCH, + LH_ACEL_MI_D1_G3D_QCH, + LH_ACEL_MI_D2_G3D_QCH, + LH_ACEL_MI_D3_G3D_QCH, + LH_ACEL_MI_D_TPU_QCH, + LH_AST_MI_G_NOCL1A_CD_QCH, + LH_AST_SI_G_NOCL1A_QCH, + LH_AST_SI_G_NOCL1A_CD_QCH, + LH_AXI_MI_D0_AUR_QCH, + LH_AXI_MI_D1_AUR_QCH, + LH_AXI_MI_P_AUR_CD_QCH, + LH_AXI_MI_P_G3D_CD_QCH, + LH_AXI_MI_P_TPU_CD_QCH, + LH_AXI_SI_P_AUR_CD_QCH, + LH_AXI_SI_P_G3D_CD_QCH, + LH_AXI_SI_P_TPU_CD_QCH, + NOCL1A_CMU_NOCL1A_QCH, + PPCFW_G3D0_QCH, + PPCFW_G3D1_QCH, + PPC_AUR_D0_CYCLE_QCH, + PPC_AUR_D0_EVENT_QCH, + PPC_AUR_D1_EVENT_QCH, + PPC_G3D_D0_CYCLE_QCH, + PPC_G3D_D0_EVENT_QCH, + PPC_G3D_D1_EVENT_QCH, + PPC_G3D_D2_EVENT_QCH, + PPC_G3D_D3_EVENT_QCH, + PPC_NOCL2A_M0_CYCLE_QCH, + PPC_NOCL2A_M0_EVENT_QCH, + PPC_NOCL2A_M1_EVENT_QCH, + PPC_NOCL2A_M2_EVENT_QCH, + PPC_NOCL2A_M3_EVENT_QCH, + PPC_TPU_CYCLE_QCH, + PPC_TPU_EVENT_QCH, + SLH_AXI_SI_P_AUR_QCH, + SLH_AXI_SI_P_G3D_QCH, + SLH_AXI_SI_P_TPU_QCH, + SSMT_G3D0_QCH, + SSMT_G3D1_QCH, + SSMT_G3D2_QCH, + SSMT_G3D3_QCH, + SYSMMU_G3D_QCH_D0, + SYSMMU_G3D_QCH_D1, + SYSMMU_G3D_QCH_D2, + SYSMMU_G3D_QCH_D3, + SYSMMU_G3D_QCH_MPTW, + SYSREG_NOCL1A_QCH, + TREX_D_NOCL1A_QCH, + TREX_P_NOCL1A_QCH, + CMU_NOCL1B_CMUREF_QCH, + D_TZPC_NOCL1B_QCH, + GPC_NOCL1B_QCH, + LH_ACEL_MI_D_HSI0_QCH, + LH_ACEL_MI_D_HSI1_QCH, + LH_AST_MI_G_NOCL1B_CD_QCH, + LH_AST_SI_G_NOCL1B_QCH, + LH_AST_SI_G_NOCL1B_CD_QCH, + LH_AXI_MI_D_AOC_QCH, + LH_AXI_MI_D_APM_QCH, + LH_AXI_MI_D_GSA_QCH, + LH_AXI_MI_G_CSSYS_CU_QCH, + LH_AXI_MI_P_AOC_CD_QCH, + LH_AXI_MI_P_GSA_CD_QCH, + LH_AXI_MI_P_HSI0_CD_QCH, + LH_AXI_MI_P_HSI1_CD_QCH, + LH_AXI_SI_G_CSSYS_CU_QCH, + LH_AXI_SI_P_AOC_CD_QCH, + LH_AXI_SI_P_GSA_CD_QCH, + LH_AXI_SI_P_HSI0_CD_QCH, + LH_AXI_SI_P_HSI1_CD_QCH, + NOCL1B_CMU_NOCL1B_QCH, + PPC_AOC_CYCLE_QCH, + PPC_AOC_EVENT_QCH, + SLH_AXI_MI_G_CSSYS_QCH, + SLH_AXI_SI_P_AOC_QCH, + SLH_AXI_SI_P_GSA_QCH, + SLH_AXI_SI_P_HSI0_QCH, + SLH_AXI_SI_P_HSI1_QCH, + SYSREG_NOCL1B_QCH, + TREX_D_NOCL1B_QCH, + TREX_P_NOCL1B_QCH, + CMU_NOCL2A_CMUREF_QCH, + D_TZPC_NOCL2A_QCH, + GPC_NOCL2A_QCH, + LH_ACEL_MI_D2_G2D_QCH, + LH_ACEL_MI_D_HSI2_QCH, + LH_ACEL_MI_D_MISC_QCH, + LH_AST_MI_G_NOCL2A_CD_QCH, + LH_AST_SI_G_NOCL2A_QCH, + LH_AST_SI_G_NOCL2A_CD_QCH, + LH_AXI_MI_D0_CSIS_QCH, + LH_AXI_MI_D0_DPU_QCH, + LH_AXI_MI_D0_G2D_QCH, + LH_AXI_MI_D0_GDC_QCH, + LH_AXI_MI_D0_MCSC_QCH, + LH_AXI_MI_D0_MFC_QCH, + LH_AXI_MI_D0_TNR_QCH, + LH_AXI_MI_D1_CSIS_QCH, + LH_AXI_MI_D1_DPU_QCH, + LH_AXI_MI_D1_G2D_QCH, + LH_AXI_MI_D1_GDC_QCH, + LH_AXI_MI_D1_MCSC_QCH, + LH_AXI_MI_D1_MFC_QCH, + LH_AXI_MI_D1_TNR_QCH, + LH_AXI_MI_D2_DPU_QCH, + LH_AXI_MI_D2_GDC_QCH, + LH_AXI_MI_D2_MCSC_QCH, + LH_AXI_MI_D2_TNR_QCH, + LH_AXI_MI_D3_TNR_QCH, + LH_AXI_MI_D4_TNR_QCH, + LH_AXI_MI_D_BO_QCH, + LH_AXI_MI_D_DNS_QCH, + LH_AXI_MI_D_G3AA_QCH, + LH_AXI_MI_D_IPP_QCH, + LH_AXI_MI_P_HSI2_CD_QCH, + LH_AXI_SI_P_HSI2_CD_QCH, + NOCL2A_CMU_NOCL2A_QCH, + SLH_AXI_SI_P_BO_QCH, + SLH_AXI_SI_P_CSIS_QCH, + SLH_AXI_SI_P_DISP_QCH, + SLH_AXI_SI_P_DNS_QCH, + SLH_AXI_SI_P_DPU_QCH, + SLH_AXI_SI_P_G2D_QCH, + SLH_AXI_SI_P_G3AA_QCH, + SLH_AXI_SI_P_GDC_QCH, + SLH_AXI_SI_P_HSI2_QCH, + SLH_AXI_SI_P_IPP_QCH, + SLH_AXI_SI_P_ITP_QCH, + SLH_AXI_SI_P_MCSC_QCH, + SLH_AXI_SI_P_MFC_QCH, + SLH_AXI_SI_P_PDP_QCH, + SLH_AXI_SI_P_TNR_QCH, + SYSREG_NOCL2A_QCH, + TREX_D_NOCL2A_QCH, + TREX_P_NOCL2A_QCH, + D_TZPC_PDP_QCH, + GPC_PDP_QCH, + LH_AST_MI_L_OTF0_CSIS_PDP_QCH, + LH_AST_MI_L_OTF1_CSIS_PDP_QCH, + LH_AST_MI_L_OTF2_CSIS_PDP_QCH, + LH_AST_MI_L_VO_CSIS_PDP_QCH, + LH_AST_SI_L_OTF0_PDP_CSIS_QCH, + LH_AST_SI_L_OTF0_PDP_G3AA_QCH, + LH_AST_SI_L_OTF0_PDP_IPP_QCH, + LH_AST_SI_L_OTF1_PDP_CSIS_QCH, + LH_AST_SI_L_OTF1_PDP_G3AA_QCH, + LH_AST_SI_L_OTF1_PDP_IPP_QCH, + LH_AST_SI_L_OTF2_PDP_CSIS_QCH, + LH_AST_SI_L_OTF2_PDP_G3AA_QCH, + LH_AST_SI_L_OTF2_PDP_IPP_QCH, + LH_AST_SI_L_VO_PDP_IPP_QCH, + LH_AST_SI_L_YOTF0_PDP_G3AA_QCH, + LH_AST_SI_L_YOTF1_PDP_G3AA_QCH, + LH_AXI_SI_LD_PDP_CSIS_QCH, + LH_AXI_SI_LD_PDP_DNS_QCH, + PDP_CMU_PDP_QCH, + PDP_TOP_QCH_C2_PDP, + PDP_TOP_QCH_PDP_TOP, + PPMU_VRA_QCH, + QE_PDP_AF0_QCH, + QE_PDP_AF1_QCH, + QE_PDP_STAT0_QCH, + QE_PDP_STAT1_QCH, + QE_VRA_QCH, + SLH_AXI_MI_P_PDP_QCH, + SSMT_PDP_STAT_QCH, + SSMT_VRA_QCH, + SYSREG_PDP_QCH, + VRA_QCH, + D_TZPC_PERIC0_QCH, + GPC_PERIC0_QCH, + GPIO_PERIC0_QCH, + I3C1_QCH_SCLK, + I3C1_QCH_PCLK, + I3C2_QCH_SCLK, + I3C2_QCH_PCLK, + I3C3_QCH_SCLK, + I3C3_QCH_PCLK, + I3C4_QCH_SCLK, + I3C4_QCH_PCLK, + I3C5_QCH_SCLK, + I3C5_QCH_PCLK, + I3C6_QCH_SCLK, + I3C6_QCH_PCLK, + I3C7_QCH_SCLK, + I3C7_QCH_PCLK, + I3C8_QCH_SCLK, + I3C8_QCH_PCLK, + LH_AXI_MI_P_PERIC0_CU_QCH, + LH_AXI_SI_P_PERIC0_CU_QCH, + PERIC0_CMU_PERIC0_QCH, + SLH_AXI_MI_P_PERIC0_QCH, + SYSREG_PERIC0_QCH, + USI0_UART_QCH, + USI14_USI_QCH, + USI1_USI_QCH, + USI2_USI_QCH, + USI3_USI_QCH, + USI4_USI_QCH, + USI5_USI_QCH, + USI6_USI_QCH, + USI7_USI_QCH, + USI8_USI_QCH, + D_TZPC_PERIC1_QCH, + GPC_PERIC1_QCH, + GPIO_PERIC1_QCH, + I3C0_QCH_SCLK, + I3C0_QCH_PCLK, + LH_AXI_MI_P_PERIC1_CU_QCH, + LH_AXI_SI_P_PERIC1_CU_QCH, + PERIC1_CMU_PERIC1_QCH, + PWM_QCH, + SLH_AXI_MI_P_PERIC1_QCH, + SYSREG_PERIC1_QCH, + USI0_USI_QCH, + USI10_USI_QCH, + USI11_USI_QCH, + USI12_USI_QCH, + USI13_USI_QCH, + USI15_USI_QCH, + USI16_USI_QCH, + USI9_USI_QCH, + BIS_S2D_QCH, + LH_AXI_MI_LG_SCAN2DRAM_CU_QCH, + LH_AXI_SI_LG_SCAN2DRAM_CU_QCH, + S2D_CMU_S2D_QCH, + SLH_AXI_MI_LG_SCAN2DRAM_QCH, + D_TZPC_TNR_QCH, + GPC_TNR_QCH, + LH_AST_MI_L_OTF_MCSC_TNR_QCH, + LH_AST_MI_L_VO_DNS_TNR_QCH, + LH_AST_SI_L_OTF_TNR_GDC_QCH, + LH_AST_SI_L_OTF_TNR_MCSC_QCH, + LH_AST_SI_L_VO_TNR_GDC_QCH, + LH_AXI_SI_D0_TNR_QCH, + LH_AXI_SI_D1_TNR_QCH, + LH_AXI_SI_D2_TNR_QCH, + LH_AXI_SI_D3_TNR_QCH, + LH_AXI_SI_D4_TNR_QCH, + PPMU_D0_TNR_QCH, + PPMU_D1_TNR_QCH, + PPMU_D2_TNR_QCH, + PPMU_D3_TNR_QCH, + PPMU_D4_TNR_QCH, + PPMU_D5_TNR_QCH, + PPMU_D6_TNR_QCH, + PPMU_D7_TNR_QCH, + PPMU_D8_TNR_QCH, + QE_D0_TNR_QCH, + QE_D1_TNR_QCH, + QE_D5_TNR_QCH, + QE_D6_TNR_QCH, + QE_D7_TNR_QCH, + QE_D8_TNR_QCH, + SLH_AXI_MI_P_TNR_QCH, + SSMT_D0_TNR_QCH, + SSMT_D1_TNR_QCH, + SSMT_D2_TNR_QCH, + SSMT_D3_TNR_QCH, + SSMT_D4_TNR_QCH, + SSMT_D5_TNR_QCH, + SSMT_D6_TNR_QCH, + SSMT_D7_TNR_QCH, + SSMT_D8_TNR_QCH, + SYSMMU_D0_TNR_QCH_S1, + SYSMMU_D0_TNR_QCH_S2, + SYSMMU_D1_TNR_QCH_S1, + SYSMMU_D1_TNR_QCH_S2, + SYSMMU_D2_TNR_QCH_S2, + SYSMMU_D2_TNR_QCH_S1, + SYSMMU_D3_TNR_QCH_S2, + SYSMMU_D3_TNR_QCH_S1, + SYSMMU_D4_TNR_QCH_S1, + SYSMMU_D4_TNR_QCH_S2, + SYSREG_TNR_QCH, + TNR_QCH_C2, + TNR_QCH_ACLK, + TNR_CMU_TNR_QCH, + BUSIF_HPMTPU_QCH, + D_TZPC_TPU_QCH, + GPC_TPU_QCH, + LH_ACEL_SI_D_TPU_QCH, + LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH, + LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH, + LH_ATB_SI_LT0_TPU_CPUCL0_QCH, + LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH, + LH_ATB_SI_LT1_TPU_CPUCL0_QCH, + LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH, + LH_AXI_MI_P_TPU_CU_QCH, + LH_AXI_SI_P_TPU_CU_QCH, + PPMU_TPU_QCH, + SLH_AXI_MI_P_TPU_QCH, + SSMT_TPU_QCH, + SYSMMU_TPU_QCH_S1, + SYSMMU_TPU_QCH_S2, + SYSREG_TPU_QCH, + TPU_QCH, + TPU_CMU_TPU_QCH, + end_of_qch, + num_of_qch = (end_of_qch - QCH_TYPE) & MASK_OF_ID, + +}; +enum option_id { + CTRL_OPTION_CMU_AOC = OPTION_TYPE, + CTRL_OPTION_CMU_APM, + CTRL_OPTION_CMU_AUR, + CTRL_OPTION_CMU_BO, + CTRL_OPTION_CMU_TOP, + CTRL_OPTION_CMU_CPUCL0, + CTRL_OPTION_EMBEDDED_CMU_CPUCL0, + CTRL_OPTION_CMU_CPUCL1, + CTRL_OPTION_CMU_CPUCL2, + CTRL_OPTION_CMU_CSIS, + CTRL_OPTION_CMU_DISP, + CTRL_OPTION_CMU_DNS, + CTRL_OPTION_CMU_DPU, + CTRL_OPTION_CMU_EH, + CTRL_OPTION_CMU_G2D, + CTRL_OPTION_CMU_G3AA, + CTRL_OPTION_CMU_G3D, + CTRL_OPTION_EMBEDDED_CMU_G3D, + CTRL_OPTION_CMU_GDC, + CTRL_OPTION_CMU_GSACORE, + CTRL_OPTION_CMU_GSACTRL, + CTRL_OPTION_CMU_HSI0, + CTRL_OPTION_CMU_HSI1, + CTRL_OPTION_CMU_HSI2, + CTRL_OPTION_CMU_IPP, + CTRL_OPTION_CMU_ITP, + CTRL_OPTION_CMU_MCSC, + CTRL_OPTION_CMU_MFC, + CTRL_OPTION_CMU_MIF, + CTRL_OPTION_CMU_MISC, + CTRL_OPTION_CMU_NOCL0, + CTRL_OPTION_EMBEDDED_CMU_NOCL0, + CTRL_OPTION_EMBEDDED_CMU_NOCL01, + CTRL_OPTION_EMBEDDED_CMU_NOCL02, + CTRL_OPTION_EMBEDDED_CMU_NOCL03, + CTRL_OPTION_CMU_NOCL1A, + CTRL_OPTION_CMU_NOCL1B, + CTRL_OPTION_CMU_NOCL2A, + CTRL_OPTION_CMU_PDP, + CTRL_OPTION_CMU_PERIC0, + CTRL_OPTION_CMU_PERIC1, + CTRL_OPTION_CMU_S2D, + CTRL_OPTION_CMU_TNR, + CTRL_OPTION_CMU_TPU, + end_of_option, + num_of_option = (end_of_option - OPTION_TYPE) & MASK_OF_ID, + +}; +#endif diff --git a/drivers/soc/google/cal-if/gs201/cmucal-sfr.c b/drivers/soc/google/cal-if/gs201/cmucal-sfr.c new file mode 100644 index 000000000000..784753993506 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-sfr.c @@ -0,0 +1,17434 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "../cmucal.h" +#include "cmucal-sfr.h" + +unsigned int cmucal_sfr_block_size = 38; +struct sfr_block cmucal_sfr_block_list[] = { + SFR_BLOCK(CMU_AUR, 0x25a00000, 0x8000), + SFR_BLOCK(CMU_TOP, 0x1e080000, 0x8000), + SFR_BLOCK(CMU_CPUCL0, 0x20c00000, 0x8000), + SFR_BLOCK(CMU_CPUCL1, 0x20c10000, 0x8000), + SFR_BLOCK(CMU_CPUCL2, 0x20c20000, 0x8000), + SFR_BLOCK(CMU_G3D, 0x27f00000, 0x8000), + SFR_BLOCK(CMU_HSI0, 0x11000000, 0x8000), + SFR_BLOCK(CMU_MIF, 0x20800000, 0x8000), + SFR_BLOCK(CMU_NOCL0, 0x1e000000, 0x8000), + SFR_BLOCK(CMU_S2D, 0x18830000, 0x8000), + SFR_BLOCK(CMU_TPU, 0x1cc00000, 0x8000), + SFR_BLOCK(CMU_APM, 0x18000000, 0x8000), + SFR_BLOCK(CMU_EH, 0x17000000, 0x8000), + SFR_BLOCK(CMU_GSACORE, 0x17a00000, 0x8000), + SFR_BLOCK(CMU_GSACTRL, 0x17900000, 0x8000), + SFR_BLOCK(CMU_NOCL1A, 0x20000000, 0x8000), + SFR_BLOCK(CMU_NOCL1B, 0x1e800000, 0x8000), + SFR_BLOCK(CMU_NOCL2A, 0x1f000000, 0x8000), + SFR_BLOCK(CMU_BO, 0x1ca00000, 0x8000), + SFR_BLOCK(CMU_CSIS, 0x1a400000, 0x8000), + SFR_BLOCK(CMU_DISP, 0x1c200000, 0x8000), + SFR_BLOCK(CMU_DNS, 0x1b000000, 0x8000), + SFR_BLOCK(CMU_DPU, 0x1c000000, 0x8000), + SFR_BLOCK(CMU_G2D, 0x1c600000, 0x8000), + SFR_BLOCK(CMU_G3AA, 0x1a800000, 0x8000), + SFR_BLOCK(CMU_GDC, 0x1d000000, 0x8000), + SFR_BLOCK(CMU_HSI1, 0x11800000, 0x8000), + SFR_BLOCK(CMU_HSI2, 0x14400000, 0x8000), + SFR_BLOCK(CMU_IPP, 0x1ac00000, 0x8000), + SFR_BLOCK(CMU_ITP, 0x1b400000, 0x8000), + SFR_BLOCK(CMU_MCSC, 0x1b700000, 0x8000), + SFR_BLOCK(CMU_MFC, 0x1c800000, 0x8000), + SFR_BLOCK(CMU_MISC, 0x10010000, 0x8000), + SFR_BLOCK(CMU_PDP, 0x1aa00000, 0x8000), + SFR_BLOCK(CMU_PERIC0, 0x10800000, 0x8000), + SFR_BLOCK(CMU_PERIC1, 0x10c00000, 0x8000), + SFR_BLOCK(CMU_TNR, 0x1bc00000, 0x8000), + SFR_BLOCK(CMU_AOC, 0x1a000000, 0x8000), +}; + +unsigned int dbg_offset = 0x4000; +unsigned int cmucal_sfr_size = 4140; +struct sfr cmucal_sfr_list[] = { + SFR(PLL_LOCKTIME_PLL_AUR, 0x0, CMU_AUR), + SFR(PLL_CON3_PLL_AUR, 0x10c, CMU_AUR), + SFR(PLL_CON4_PLL_AUR, 0x110, CMU_AUR), + SFR(DBG_NFO_PLL_AUR, 0x4100, CMU_AUR), + SFR(PLL_CON0_PLL_AUR, 0x100, CMU_AUR), + SFR(PLL_CON1_PLL_AUR, 0x104, CMU_AUR), + SFR(PLL_CON2_PLL_AUR, 0x108, CMU_AUR), + SFR(PLL_LOCKTIME_PLL_SHARED0, 0x4, CMU_TOP), + SFR(PLL_CON3_PLL_SHARED0, 0x14c, CMU_TOP), + SFR(PLL_CON4_PLL_SHARED0, 0x150, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED0, 0x4140, CMU_TOP), + SFR(PLL_CON0_PLL_SHARED0, 0x140, CMU_TOP), + SFR(PLL_CON1_PLL_SHARED0, 0x144, CMU_TOP), + SFR(PLL_CON2_PLL_SHARED0, 0x148, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_SHARED1, 0x8, CMU_TOP), + SFR(PLL_CON3_PLL_SHARED1, 0x18c, CMU_TOP), + SFR(PLL_CON4_PLL_SHARED1, 0x190, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED1, 0x4180, CMU_TOP), + SFR(PLL_CON0_PLL_SHARED1, 0x180, CMU_TOP), + SFR(PLL_CON1_PLL_SHARED1, 0x184, CMU_TOP), + SFR(PLL_CON2_PLL_SHARED1, 0x188, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_SHARED2, 0xc, CMU_TOP), + SFR(PLL_CON3_PLL_SHARED2, 0x1cc, CMU_TOP), + SFR(PLL_CON4_PLL_SHARED2, 0x1d0, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED2, 0x41c0, CMU_TOP), + SFR(PLL_CON0_PLL_SHARED2, 0x1c0, CMU_TOP), + SFR(PLL_CON1_PLL_SHARED2, 0x1c4, CMU_TOP), + SFR(PLL_CON2_PLL_SHARED2, 0x1c8, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_SHARED3, 0x10, CMU_TOP), + SFR(PLL_CON3_PLL_SHARED3, 0x20c, CMU_TOP), + SFR(PLL_CON4_PLL_SHARED3, 0x210, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED3, 0x4200, CMU_TOP), + SFR(PLL_CON0_PLL_SHARED3, 0x200, CMU_TOP), + SFR(PLL_CON1_PLL_SHARED3, 0x204, CMU_TOP), + SFR(PLL_CON2_PLL_SHARED3, 0x208, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_SPARE, 0x14, CMU_TOP), + SFR(PLL_CON3_PLL_SPARE, 0x24c, CMU_TOP), + SFR(PLL_CON4_PLL_SPARE, 0x250, CMU_TOP), + SFR(DBG_NFO_PLL_SPARE, 0x4240, CMU_TOP), + SFR(PLL_CON0_PLL_SPARE, 0x240, CMU_TOP), + SFR(PLL_CON1_PLL_SPARE, 0x244, CMU_TOP), + SFR(PLL_CON2_PLL_SPARE, 0x248, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_LF_MIF, 0x0, CMU_TOP), + SFR(PLL_CON3_PLL_LF_MIF, 0x10c, CMU_TOP), + SFR(PLL_CON4_PLL_LF_MIF, 0x110, CMU_TOP), + SFR(DBG_NFO_PLL_LF_MIF, 0x4100, CMU_TOP), + SFR(PLL_CON0_PLL_LF_MIF, 0x100, CMU_TOP), + SFR(PLL_CON1_PLL_LF_MIF, 0x104, CMU_TOP), + SFR(PLL_CON2_PLL_LF_MIF, 0x108, CMU_TOP), + SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0, CMU_CPUCL0), + SFR(PLL_CON3_PLL_CPUCL0, 0x10c, CMU_CPUCL0), + SFR(PLL_CON4_PLL_CPUCL0, 0x110, CMU_CPUCL0), + SFR(DBG_NFO_PLL_CPUCL0, 0x4100, CMU_CPUCL0), + SFR(PLL_CON0_PLL_CPUCL0, 0x100, CMU_CPUCL0), + SFR(PLL_CON1_PLL_CPUCL0, 0x104, CMU_CPUCL0), + SFR(PLL_CON2_PLL_CPUCL0, 0x108, CMU_CPUCL0), + SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x4, CMU_CPUCL1), + SFR(PLL_CON3_PLL_CPUCL1, 0x14c, CMU_CPUCL1), + SFR(PLL_CON4_PLL_CPUCL1, 0x150, CMU_CPUCL1), + SFR(DBG_NFO_PLL_CPUCL1, 0x4140, CMU_CPUCL1), + SFR(PLL_CON0_PLL_CPUCL1, 0x140, CMU_CPUCL1), + SFR(PLL_CON1_PLL_CPUCL1, 0x144, CMU_CPUCL1), + SFR(PLL_CON2_PLL_CPUCL1, 0x148, CMU_CPUCL1), + SFR(PLL_LOCKTIME_PLL_CPUCL2, 0x0, CMU_CPUCL2), + SFR(PLL_CON3_PLL_CPUCL2, 0x10c, CMU_CPUCL2), + SFR(PLL_CON4_PLL_CPUCL2, 0x110, CMU_CPUCL2), + SFR(DBG_NFO_PLL_CPUCL2, 0x4100, CMU_CPUCL2), + SFR(PLL_CON0_PLL_CPUCL2, 0x100, CMU_CPUCL2), + SFR(PLL_CON1_PLL_CPUCL2, 0x104, CMU_CPUCL2), + SFR(PLL_CON2_PLL_CPUCL2, 0x108, CMU_CPUCL2), + SFR(PLL_CON6_PLL_CPUCL2, 0x118, CMU_CPUCL2), + SFR(PLL_LOCKTIME_REG_PLL_CPUCL2, 0x80, CMU_CPUCL2), + SFR(PLL_LOCKTIME_PLL_G3D, 0x4, CMU_G3D), + SFR(PLL_CON3_PLL_G3D, 0x10c, CMU_G3D), + SFR(PLL_CON4_PLL_G3D, 0x110, CMU_G3D), + SFR(DBG_NFO_PLL_G3D, 0x4140, CMU_G3D), + SFR(PLL_CON0_PLL_G3D, 0x100, CMU_G3D), + SFR(PLL_CON1_PLL_G3D, 0x104, CMU_G3D), + SFR(PLL_CON2_PLL_G3D, 0x108, CMU_G3D), + SFR(PLL_LOCKTIME_PLL_G3D_L2, 0x8, CMU_G3D), + SFR(PLL_CON3_PLL_G3D_L2, 0x14c, CMU_G3D), + SFR(PLL_CON4_PLL_G3D_L2, 0x150, CMU_G3D), + SFR(DBG_NFO_PLL_G3D_L2, 0x4180, CMU_G3D), + SFR(PLL_CON0_PLL_G3D_L2, 0x140, CMU_G3D), + SFR(PLL_CON1_PLL_G3D_L2, 0x144, CMU_G3D), + SFR(PLL_CON2_PLL_G3D_L2, 0x148, CMU_G3D), + SFR(PLL_LOCKTIME_PLL_USB, 0x4, CMU_HSI0), + SFR(PLL_CON3_PLL_USB, 0x14c, CMU_HSI0), + SFR(PLL_CON4_PLL_USB, 0x150, CMU_HSI0), + SFR(DBG_NFO_PLL_USB, 0x4140, CMU_HSI0), + SFR(PLL_CON0_PLL_USB, 0x140, CMU_HSI0), + SFR(PLL_CON1_PLL_USB, 0x144, CMU_HSI0), + SFR(PLL_CON2_PLL_USB, 0x148, CMU_HSI0), + SFR(PLL_LOCKTIME_PLL_MIF_MAIN, 0x0, CMU_MIF), + SFR(PLL_CON3_PLL_MIF_MAIN, 0x10c, CMU_MIF), + SFR(PLL_CON4_PLL_MIF_MAIN, 0x110, CMU_MIF), + SFR(DBG_NFO_PLL_MIF_MAIN, 0x4100, CMU_MIF), + SFR(PLL_CON0_PLL_MIF_MAIN, 0x100, CMU_MIF), + SFR(PLL_CON1_PLL_MIF_MAIN, 0x104, CMU_MIF), + SFR(PLL_CON2_PLL_MIF_MAIN, 0x108, CMU_MIF), + SFR(PLL_CON6_PLL_MIF_MAIN, 0x118, CMU_MIF), + SFR(PLL_LOCKTIME_REG_PLL_MIF_MAIN, 0x80, CMU_MIF), + SFR(PLL_LOCKTIME_PLL_MIF_SUB, 0x4, CMU_MIF), + SFR(PLL_CON3_PLL_MIF_SUB, 0x14c, CMU_MIF), + SFR(PLL_CON4_PLL_MIF_SUB, 0x150, CMU_MIF), + SFR(DBG_NFO_PLL_MIF_SUB, 0x4140, CMU_MIF), + SFR(PLL_CON0_PLL_MIF_SUB, 0x140, CMU_MIF), + SFR(PLL_CON1_PLL_MIF_SUB, 0x144, CMU_MIF), + SFR(PLL_CON2_PLL_MIF_SUB, 0x148, CMU_MIF), + SFR(PLL_CON6_PLL_MIF_SUB, 0x158, CMU_MIF), + SFR(PLL_LOCKTIME_REG_PLL_MIF_SUB, 0x84, CMU_MIF), + SFR(PLL_LOCKTIME_PLL_NOCL0, 0x0, CMU_NOCL0), + SFR(PLL_CON3_PLL_NOCL0, 0x10c, CMU_NOCL0), + SFR(PLL_CON4_PLL_NOCL0, 0x110, CMU_NOCL0), + SFR(DBG_NFO_PLL_NOCL0, 0x4100, CMU_NOCL0), + SFR(PLL_CON0_PLL_NOCL0, 0x100, CMU_NOCL0), + SFR(PLL_CON1_PLL_NOCL0, 0x104, CMU_NOCL0), + SFR(PLL_CON2_PLL_NOCL0, 0x108, CMU_NOCL0), + SFR(PLL_LOCKTIME_PLL_MIF_S2D, 0x0, CMU_S2D), + SFR(PLL_CON3_PLL_MIF_S2D, 0x10c, CMU_S2D), + SFR(PLL_CON4_PLL_MIF_S2D, 0x110, CMU_S2D), + SFR(DBG_NFO_PLL_MIF_S2D, 0x4100, CMU_S2D), + SFR(PLL_CON0_PLL_MIF_S2D, 0x100, CMU_S2D), + SFR(PLL_CON1_PLL_MIF_S2D, 0x104, CMU_S2D), + SFR(PLL_CON2_PLL_MIF_S2D, 0x108, CMU_S2D), + SFR(PLL_CON6_PLL_MIF_S2D, 0x118, CMU_S2D), + SFR(PLL_LOCKTIME_REG_PLL_MIF_S2D, 0x80, CMU_S2D), + SFR(PLL_LOCKTIME_PLL_TPU, 0x0, CMU_TPU), + SFR(PLL_CON3_PLL_TPU, 0x10c, CMU_TPU), + SFR(PLL_CON4_PLL_TPU, 0x110, CMU_TPU), + SFR(DBG_NFO_PLL_TPU, 0x4100, CMU_TPU), + SFR(PLL_CON0_PLL_TPU, 0x100, CMU_TPU), + SFR(PLL_CON1_PLL_TPU, 0x104, CMU_TPU), + SFR(PLL_CON2_PLL_TPU, 0x108, CMU_TPU), + SFR(CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 0x1000, CMU_APM), + SFR(DBG_NFO_MUX_CLKCMU_APM_FUNC, 0x5000, CMU_APM), + SFR(CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 0x1004, CMU_APM), + SFR(DBG_NFO_MUX_CLKCMU_APM_FUNCSRC, 0x5004, CMU_APM), + SFR(CLK_CON_MUX_MUX_CLK_AUR_AUR, 0x1000, CMU_AUR), + SFR(DBG_NFO_MUX_CLK_AUR_AUR, 0x5000, CMU_AUR), + SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0x10bc, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MFC_MFC, 0x50c0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, 0x108c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD, 0x5090, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0x105c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G2D_G2D, 0x5060, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, 0x1048, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CSIS_NOC, 0x504c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x103c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH, 0x5040, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, 0x10d0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_NOCL0_NOC, 0x50d4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x10c4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MIF_SWITCH, 0x50c8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_ITP_NOC, 0x10b0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_ITP_NOC, 0x50b4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0x1064, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G3AA_G3AA, 0x5068, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0x10b4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MCSC_ITSC, 0x50b8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0x1060, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G2D_MSCL, 0x5064, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HPM, 0x1080, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HPM, 0x5084, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0x1038, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG, 0x503c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, 0x1094, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI1_NOC, 0x5098, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1010, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK0, 0x5014, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x1014, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK1, 0x5018, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x1018, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK2, 0x501c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x101c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK3, 0x5020, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_BO_NOC, 0x100c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_BO_NOC, 0x5010, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, 0x10a8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD, 0x50ac, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x1114, CMU_TOP), + SFR(DBG_NFO_MUX_CMU_CMUREF, 0x5118, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, 0x10ec, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_NOC, 0x50f0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, 0x10f4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_NOC, 0x50f8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, 0x10c8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MISC_NOC, 0x50cc, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0x1084, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_DPGTC, 0x5088, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0x10a4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_PCIE, 0x50a8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, 0x10a0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_NOC, 0x50a4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, 0x10c0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MIF_NOCP, 0x50c4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0x10e8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_IP, 0x50ec, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0x10f0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_IP, 0x50f4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TPU_NOC, 0x1104, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TPU_NOC, 0x5108, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, 0x1090, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_USBDPDBG, 0x5094, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0x10e4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PDP_VRA, 0x50e8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_DPU_NOC, 0x1054, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_DPU_NOC, 0x5058, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x1040, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH, 0x5044, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0x1098, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI1_PCIE, 0x509c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, 0x1088, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_NOC, 0x508c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0x1100, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TOP_CMUREF, 0x5104, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_IPP_NOC, 0x10ac, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_IPP_NOC, 0x50b0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0x1020, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK4, 0x5024, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0x1030, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CMU_BOOST, 0x5034, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TNR_NOC, 0x10f8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TNR_NOC, 0x50fc, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC, 0x10dc, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_NOCL2A_NOC, 0x50e0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC, 0x10d4, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_NOCL1A_NOC, 0x50d8, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC, 0x10d8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_NOCL1B_NOC, 0x50dc, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0x1024, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK5, 0x5028, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0x1028, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK6, 0x502c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_DNS_NOC, 0x1050, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_DNS_NOC, 0x5054, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0x1074, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_GDC_GDC0, 0x5078, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0x1078, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_GDC_GDC1, 0x507c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0x10b8, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MCSC_MCSC, 0x50bc, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0x1108, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TPU_TPU, 0x510c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, 0x109c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD, 0x50a0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0x102c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CIS_CLK7, 0x5030, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0x1068, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G3D_GLB, 0x506c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, 0x1044, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH, 0x5048, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0x107c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_GDC_SCSC, 0x5080, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0x10cc, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_MISC_SSS, 0x50d0, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_DISP_NOC, 0x104c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_DISP_NOC, 0x5050, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_EH_NOC, 0x1058, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_EH_NOC, 0x505c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0x1034, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_CMU_BOOST_OPTION1, 0x5038, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0x10fc, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TOP_BOOST_OPTION1, 0x5100, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_PDP_NOC, 0x10e0, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_PDP_NOC, 0x50e4, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0x1110, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TPU_UART, 0x5114, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0x110c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_TPU_TPUCTL, 0x5110, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0x1070, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G3D_SWITCH, 0x5074, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD, 0x106c, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_G3D_NOCD, 0x5070, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_AUR_AUR, 0x1000, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_AUR_AUR, 0x5004, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_AUR_NOC, 0x1008, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_AUR_NOC, 0x500c, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL, 0x1004, CMU_TOP), + SFR(DBG_NFO_MUX_CLKCMU_AUR_AURCTL, 0x5008, CMU_TOP), + SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x1000, CMU_CPUCL0), + SFR(DBG_NFO_MUX_CLK_CPUCL0_PLL, 0x5000, CMU_CPUCL0), + SFR(CLK_CON_MUX_MUX_CPUCL0_CMUREF, 0x1004, CMU_CPUCL0), + SFR(DBG_NFO_MUX_CPUCL0_CMUREF, 0x5004, CMU_CPUCL0), + SFR(CLK_CON_MUX_MUX_CPUCL1_CMUREF, 0x1004, CMU_CPUCL1), + SFR(DBG_NFO_MUX_CPUCL1_CMUREF, 0x5004, CMU_CPUCL1), + SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CMU_CPUCL1), + SFR(DBG_NFO_MUX_CLK_CPUCL1_PLL, 0x5000, CMU_CPUCL1), + SFR(CLK_CON_MUX_MUX_CLK_CPUCL2_PLL, 0x1000, CMU_CPUCL2), + SFR(DBG_NFO_MUX_CLK_CPUCL2_PLL, 0x5000, CMU_CPUCL2), + SFR(CLK_CON_MUX_MUX_CPUCL2_CMUREF, 0x1004, CMU_CPUCL2), + SFR(DBG_NFO_MUX_CPUCL2_CMUREF, 0x5004, CMU_CPUCL2), + SFR(CLK_CON_MUX_MUX_CLK_EH_NOC, 0x1004, CMU_EH), + SFR(DBG_NFO_MUX_CLK_EH_NOC, 0x5004, CMU_EH), + SFR(CLK_CON_MUX_MUX_CLK_G3D_STACKS, 0x1004, CMU_G3D), + SFR(DBG_NFO_MUX_CLK_G3D_STACKS, 0x5004, CMU_G3D), + SFR(CLK_CON_MUX_MUX_CLK_G3D_L2_GLB, 0x1000, CMU_G3D), + SFR(DBG_NFO_MUX_CLK_G3D_L2_GLB, 0x5000, CMU_G3D), + SFR(CLK_CON_MUX_MUX_CLK_G3D_TOP, 0x1008, CMU_G3D), + SFR(DBG_NFO_MUX_CLK_G3D_TOP, 0x5008, CMU_G3D), + SFR(CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH, 0x1000, CMU_GSACORE), + SFR(DBG_NFO_MUX_CLK_GSACORE_CPU_HCH, 0x5000, CMU_GSACORE), + SFR(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC, 0x1000, CMU_GSACTRL), + SFR(DBG_NFO_MUX_CLKCMU_GSA_FUNC, 0x5000, CMU_GSACTRL), + SFR(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC, 0x1004, CMU_GSACTRL), + SFR(DBG_NFO_MUX_CLKCMU_GSA_FUNCSRC, 0x5004, CMU_GSACTRL), + SFR(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0x1008, CMU_HSI0), + SFR(DBG_NFO_MUX_CLK_HSI0_USB31DRD, 0x5008, CMU_HSI0), + SFR(CLK_CON_MUX_MUX_CLK_HSI0_NOC, 0x1000, CMU_HSI0), + SFR(DBG_NFO_MUX_CLK_HSI0_NOC, 0x5000, CMU_HSI0), + SFR(CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0x1004, CMU_HSI0), + SFR(DBG_NFO_MUX_CLK_HSI0_USB20_REF, 0x5004, CMU_HSI0), + SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1000, CMU_MIF), + SFR(DBG_NFO_MUX_MIF_CMUREF, 0x5000, CMU_MIF), + SFR(CLK_CON_MUX_MUX_NOCL0_CMUREF, 0x1008, CMU_NOCL0), + SFR(DBG_NFO_MUX_NOCL0_CMUREF, 0x5008, CMU_NOCL0), + SFR(CLK_CON_MUX_MUX_CLK_NOCL0_NOC, 0x1000, CMU_NOCL0), + SFR(DBG_NFO_MUX_CLK_NOCL0_NOC, 0x5000, CMU_NOCL0), + SFR(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1, 0x1004, CMU_NOCL0), + SFR(DBG_NFO_MUX_CLK_NOCL0_NOC_OPTION1, 0x5004, CMU_NOCL0), + SFR(CLK_CON_MUX_MUX_NOCL1A_CMUREF, 0x1000, CMU_NOCL1A), + SFR(DBG_NFO_MUX_NOCL1A_CMUREF, 0x5000, CMU_NOCL1A), + SFR(CLK_CON_MUX_MUX_NOCL1B_CMUREF, 0x1004, CMU_NOCL1B), + SFR(DBG_NFO_MUX_NOCL1B_CMUREF, 0x5004, CMU_NOCL1B), + SFR(CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1, 0x1000, CMU_NOCL1B), + SFR(DBG_NFO_MUX_CLK_NOCL1B_NOC_OPTION1, 0x5000, CMU_NOCL1B), + SFR(CLK_CON_MUX_MUX_NOCL2A_CMUREF, 0x1000, CMU_NOCL2A), + SFR(DBG_NFO_MUX_NOCL2A_CMUREF, 0x5000, CMU_NOCL2A), + SFR(CLK_CON_MUX_MUX_CLK_S2D_CORE, 0x1004, CMU_S2D), + SFR(DBG_NFO_MUX_CLK_S2D_CORE, 0x5004, CMU_S2D), + SFR(CLK_CON_MUX_MUX_CLK_TPU_TPU, 0x1000, CMU_TPU), + SFR(DBG_NFO_MUX_CLK_TPU_TPU, 0x5000, CMU_TPU), + SFR(CLK_CON_MUX_MUX_CLK_TPU_TPUCTL, 0x1004, CMU_TPU), + SFR(DBG_NFO_MUX_CLK_TPU_TPUCTL, 0x5004, CMU_TPU), + SFR(PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER, 0x620, CMU_AUR), + SFR(PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER, 0x624, CMU_AUR), + SFR(DBG_NFO_MUX_CLKCMU_AUR_SWITCH_USER, 0x4620, CMU_AUR), + SFR(PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER, 0x600, CMU_AUR), + SFR(PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER, 0x604, CMU_AUR), + SFR(DBG_NFO_MUX_CLKCMU_AUR_AURCTL_USER, 0x4600, CMU_AUR), + SFR(PLL_CON0_MUX_CLKCMU_AUR_NOC_USER, 0x610, CMU_AUR), + SFR(PLL_CON1_MUX_CLKCMU_AUR_NOC_USER, 0x614, CMU_AUR), + SFR(DBG_NFO_MUX_CLKCMU_AUR_NOC_USER, 0x4610, CMU_AUR), + SFR(PLL_CON0_MUX_CLKCMU_BO_NOC_USER, 0x600, CMU_BO), + SFR(PLL_CON1_MUX_CLKCMU_BO_NOC_USER, 0x604, CMU_BO), + SFR(DBG_NFO_MUX_CLKCMU_BO_NOC_USER, 0x4600, CMU_BO), + SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x610, CMU_CPUCL0), + SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x614, CMU_CPUCL0), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x4610, CMU_CPUCL0), + SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, 0x600, CMU_CPUCL0), + SFR(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, 0x604, CMU_CPUCL0), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, 0x4600, CMU_CPUCL0), + SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x600, CMU_CPUCL1), + SFR(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x604, CMU_CPUCL1), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x4600, CMU_CPUCL1), + SFR(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x600, CMU_CPUCL2), + SFR(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x604, CMU_CPUCL2), + SFR(DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_USER, 0x4600, CMU_CPUCL2), + SFR(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER, 0x600, CMU_CSIS), + SFR(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER, 0x604, CMU_CSIS), + SFR(DBG_NFO_MUX_CLKCMU_CSIS_NOC_USER, 0x4600, CMU_CSIS), + SFR(PLL_CON0_MUX_CLKCMU_DISP_NOC_USER, 0x600, CMU_DISP), + SFR(PLL_CON1_MUX_CLKCMU_DISP_NOC_USER, 0x604, CMU_DISP), + SFR(DBG_NFO_MUX_CLKCMU_DISP_NOC_USER, 0x4600, CMU_DISP), + SFR(PLL_CON0_MUX_CLKCMU_DNS_NOC_USER, 0x600, CMU_DNS), + SFR(PLL_CON1_MUX_CLKCMU_DNS_NOC_USER, 0x604, CMU_DNS), + SFR(DBG_NFO_MUX_CLKCMU_DNS_NOC_USER, 0x4600, CMU_DNS), + SFR(PLL_CON0_MUX_CLKCMU_DPU_NOC_USER, 0x600, CMU_DPU), + SFR(PLL_CON1_MUX_CLKCMU_DPU_NOC_USER, 0x604, CMU_DPU), + SFR(DBG_NFO_MUX_CLKCMU_DPU_NOC_USER, 0x4600, CMU_DPU), + SFR(PLL_CON0_MUX_CLKCMU_EH_NOC_USER, 0x600, CMU_EH), + SFR(PLL_CON1_MUX_CLKCMU_EH_NOC_USER, 0x604, CMU_EH), + SFR(DBG_NFO_MUX_CLKCMU_EH_NOC_USER, 0x4600, CMU_EH), + SFR(PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER, 0x610, CMU_EH), + SFR(PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER, 0x614, CMU_EH), + SFR(DBG_NFO_MUX_CLKCMU_EH_PLL_NOCL0_USER, 0x4610, CMU_EH), + SFR(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 0x600, CMU_G2D), + SFR(PLL_CON1_MUX_CLKCMU_G2D_G2D_USER, 0x604, CMU_G2D), + SFR(DBG_NFO_MUX_CLKCMU_G2D_G2D_USER, 0x4600, CMU_G2D), + SFR(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, 0x610, CMU_G2D), + SFR(PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER, 0x614, CMU_G2D), + SFR(DBG_NFO_MUX_CLKCMU_G2D_MSCL_USER, 0x4610, CMU_G2D), + SFR(PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER, 0x600, CMU_G3AA), + SFR(PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER, 0x604, CMU_G3AA), + SFR(DBG_NFO_MUX_CLKCMU_G3AA_G3AA_USER, 0x4600, CMU_G3AA), + SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x650, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER, 0x654, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_G3D_SWITCH_USER, 0x4650, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, 0x610, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, 0x614, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, 0x4610, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_G3D_GLB_USER, 0x640, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_G3D_GLB_USER, 0x644, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_G3D_GLB_USER, 0x4640, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, 0x600, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, 0x604, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, 0x4600, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER, 0x630, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER, 0x634, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_G3D_NOCD_USER, 0x4630, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, 0x620, CMU_G3D), + SFR(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, 0x624, CMU_G3D), + SFR(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, 0x4620, CMU_G3D), + SFR(PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER, 0x620, CMU_GDC), + SFR(PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER, 0x624, CMU_GDC), + SFR(DBG_NFO_MUX_CLKCMU_GDC_SCSC_USER, 0x4620, CMU_GDC), + SFR(PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER, 0x600, CMU_GDC), + SFR(PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER, 0x604, CMU_GDC), + SFR(DBG_NFO_MUX_CLKCMU_GDC_GDC0_USER, 0x4600, CMU_GDC), + SFR(PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER, 0x610, CMU_GDC), + SFR(PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER, 0x614, CMU_GDC), + SFR(DBG_NFO_MUX_CLKCMU_GDC_GDC1_USER, 0x4610, CMU_GDC), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 0x610, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER, 0x614, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_NOC_USER, 0x4610, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 0x650, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER, 0x654, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_USER, 0x4650, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 0x620, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, 0x624, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_USER, 0x4620, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 0x660, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER, 0x664, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_USPDPDBG_USER, 0x4660, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 0x600, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER, 0x604, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_ALT_USER, 0x4600, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 0x640, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER, 0x644, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_USB20_USER, 0x4640, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 0x630, CMU_HSI0), + SFR(PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER, 0x634, CMU_HSI0), + SFR(DBG_NFO_MUX_CLKCMU_HSI0_TCXO_USER, 0x4630, CMU_HSI0), + SFR(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 0x600, CMU_HSI1), + SFR(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER, 0x604, CMU_HSI1), + SFR(DBG_NFO_MUX_CLKCMU_HSI1_NOC_USER, 0x4600, CMU_HSI1), + SFR(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, 0x610, CMU_HSI1), + SFR(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER, 0x614, CMU_HSI1), + SFR(DBG_NFO_MUX_CLKCMU_HSI1_PCIE_USER, 0x4610, CMU_HSI1), + SFR(PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER, 0x600, CMU_HSI2), + SFR(PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER, 0x604, CMU_HSI2), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_NOC_USER, 0x4600, CMU_HSI2), + SFR(PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, 0x620, CMU_HSI2), + SFR(PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER, 0x624, CMU_HSI2), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_PCIE_USER, 0x4620, CMU_HSI2), + SFR(PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 0x630, CMU_HSI2), + SFR(PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 0x634, CMU_HSI2), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_USER, 0x4630, CMU_HSI2), + SFR(PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, 0x610, CMU_HSI2), + SFR(PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER, 0x614, CMU_HSI2), + SFR(DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_USER, 0x4610, CMU_HSI2), + SFR(PLL_CON0_MUX_CLKCMU_IPP_NOC_USER, 0x600, CMU_IPP), + SFR(PLL_CON1_MUX_CLKCMU_IPP_NOC_USER, 0x604, CMU_IPP), + SFR(DBG_NFO_MUX_CLKCMU_IPP_NOC_USER, 0x4600, CMU_IPP), + SFR(PLL_CON0_MUX_CLKCMU_ITP_NOC_USER, 0x600, CMU_ITP), + SFR(PLL_CON1_MUX_CLKCMU_ITP_NOC_USER, 0x604, CMU_ITP), + SFR(DBG_NFO_MUX_CLKCMU_ITP_NOC_USER, 0x4600, CMU_ITP), + SFR(PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER, 0x600, CMU_MCSC), + SFR(PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER, 0x604, CMU_MCSC), + SFR(DBG_NFO_MUX_CLKCMU_MCSC_ITSC_USER, 0x4600, CMU_MCSC), + SFR(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER, 0x610, CMU_MCSC), + SFR(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER, 0x614, CMU_MCSC), + SFR(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER, 0x4610, CMU_MCSC), + SFR(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, 0x600, CMU_MFC), + SFR(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER, 0x604, CMU_MFC), + SFR(DBG_NFO_MUX_CLKCMU_MFC_MFC_USER, 0x4600, CMU_MFC), + SFR(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER, 0x610, CMU_MIF), + SFR(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER, 0x614, CMU_MIF), + SFR(DBG_NFO_MUX_CLKCMU_MIF_NOCP_USER, 0x4610, CMU_MIF), + SFR(PLL_CON0_CLKMUX_MIF_DDRPHY2X, 0x600, CMU_MIF), + SFR(PLL_CON1_CLKMUX_MIF_DDRPHY2X, 0x604, CMU_MIF), + SFR(DBG_NFO_CLKMUX_MIF_DDRPHY2X, 0x4600, CMU_MIF), + SFR(PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 0x600, CMU_MISC), + SFR(PLL_CON1_MUX_CLKCMU_MISC_NOC_USER, 0x604, CMU_MISC), + SFR(DBG_NFO_MUX_CLKCMU_MISC_NOC_USER, 0x4600, CMU_MISC), + SFR(PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 0x610, CMU_MISC), + SFR(PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, 0x614, CMU_MISC), + SFR(DBG_NFO_MUX_CLKCMU_MISC_SSS_USER, 0x4610, CMU_MISC), + SFR(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER, 0x600, CMU_NOCL0), + SFR(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER, 0x604, CMU_NOCL0), + SFR(DBG_NFO_MUX_CLKCMU_NOCL0_NOC_USER, 0x4600, CMU_NOCL0), + SFR(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER, 0x600, CMU_NOCL1A), + SFR(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER, 0x604, CMU_NOCL1A), + SFR(DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_USER, 0x4600, CMU_NOCL1A), + SFR(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER, 0x600, CMU_NOCL1B), + SFR(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER, 0x604, CMU_NOCL1B), + SFR(DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_USER, 0x4600, CMU_NOCL1B), + SFR(PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER, 0x600, CMU_NOCL2A), + SFR(PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER, 0x604, CMU_NOCL2A), + SFR(DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_USER, 0x4600, CMU_NOCL2A), + SFR(PLL_CON0_MUX_CLKCMU_PDP_NOC_USER, 0x600, CMU_PDP), + SFR(PLL_CON1_MUX_CLKCMU_PDP_NOC_USER, 0x604, CMU_PDP), + SFR(DBG_NFO_MUX_CLKCMU_PDP_NOC_USER, 0x4600, CMU_PDP), + SFR(PLL_CON0_MUX_CLKCMU_PDP_VRA_USER, 0x610, CMU_PDP), + SFR(PLL_CON1_MUX_CLKCMU_PDP_VRA_USER, 0x614, CMU_PDP), + SFR(DBG_NFO_MUX_CLKCMU_PDP_VRA_USER, 0x4610, CMU_PDP), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, 0x600, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER, 0x604, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_NOC_USER, 0x4600, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 0x6a0, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, 0x6a4, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI6_USI_USER, 0x46a0, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 0x670, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, 0x674, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI3_USI_USER, 0x4670, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 0x680, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, 0x684, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI4_USI_USER, 0x4680, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 0x690, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, 0x694, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI5_USI_USER, 0x4690, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 0x640, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, 0x644, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI14_USI_USER, 0x4640, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 0x610, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, 0x614, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_I3C_USER, 0x4610, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 0x6b0, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, 0x6b4, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI7_USI_USER, 0x46b0, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 0x6c0, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, 0x6c4, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI8_USI_USER, 0x46c0, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 0x650, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, 0x654, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI1_USI_USER, 0x4650, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 0x620, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, 0x624, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI0_UART_USER, 0x4620, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 0x660, CMU_PERIC0), + SFR(PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, 0x664, CMU_PERIC0), + SFR(DBG_NFO_MUX_CLKCMU_PERIC0_USI2_USI_USER, 0x4660, CMU_PERIC0), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 0x610, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER, 0x614, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_NOC_USER, 0x4610, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 0x640, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, 0x644, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI11_USI_USER, 0x4640, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 0x650, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, 0x654, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI12_USI_USER, 0x4650, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 0x620, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, 0x624, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI0_USI_USER, 0x4620, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 0x600, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, 0x604, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_I3C_USER, 0x4600, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 0x690, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, 0x694, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI9_USI_USER, 0x4690, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 0x630, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, 0x634, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI10_USI_USER, 0x4630, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 0x660, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, 0x664, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI13_USI_USER, 0x4660, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER, 0x670, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER, 0x674, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI15_USI_USER, 0x4670, CMU_PERIC1), + SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, 0x680, CMU_PERIC1), + SFR(PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER, 0x684, CMU_PERIC1), + SFR(DBG_NFO_MUX_CLKCMU_PERIC1_USI16_USI_USER, 0x4680, CMU_PERIC1), + SFR(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, 0x600, CMU_S2D), + SFR(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, 0x604, CMU_S2D), + SFR(DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D, 0x4600, CMU_S2D), + SFR(PLL_CON0_MUX_CLKCMU_TNR_NOC_USER, 0x600, CMU_TNR), + SFR(PLL_CON1_MUX_CLKCMU_TNR_NOC_USER, 0x604, CMU_TNR), + SFR(DBG_NFO_MUX_CLKCMU_TNR_NOC_USER, 0x4600, CMU_TNR), + SFR(PLL_CON0_MUX_CLKCMU_TPU_NOC_USER, 0x600, CMU_TPU), + SFR(PLL_CON1_MUX_CLKCMU_TPU_NOC_USER, 0x604, CMU_TPU), + SFR(DBG_NFO_MUX_CLKCMU_TPU_NOC_USER, 0x4600, CMU_TPU), + SFR(PLL_CON0_MUX_CLKCMU_TPU_TPU_USER, 0x620, CMU_TPU), + SFR(PLL_CON1_MUX_CLKCMU_TPU_TPU_USER, 0x624, CMU_TPU), + SFR(DBG_NFO_MUX_CLKCMU_TPU_TPU_USER, 0x4620, CMU_TPU), + SFR(PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER, 0x610, CMU_TPU), + SFR(PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER, 0x614, CMU_TPU), + SFR(DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_USER, 0x4610, CMU_TPU), + SFR(PLL_CON0_MUX_CLKCMU_TPU_UART_USER, 0x630, CMU_TPU), + SFR(PLL_CON1_MUX_CLKCMU_TPU_UART_USER, 0x634, CMU_TPU), + SFR(DBG_NFO_MUX_CLKCMU_TPU_UART_USER, 0x4630, CMU_TPU), + SFR(CLK_CON_DIV_DIV_CLK_AOC_NOC_LH, 0x1800, CMU_AOC), + SFR(DBG_NFO_DIV_CLK_AOC_NOC_LH, 0x5800, CMU_AOC), + SFR(CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH, 0x1804, CMU_AOC), + SFR(DBG_NFO_DIV_CLK_AOC_TRACE_LH, 0x5804, CMU_AOC), + SFR(CLK_CON_DIV_DIV_CLK_APM_BOOST, 0x1800, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_BOOST, 0x5800, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0x1810, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_USI0_USI, 0x5810, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0x180c, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_USI0_UART, 0x580c, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0x1814, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_USI1_UART, 0x5814, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC, 0x1804, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_I3C_PMIC, 0x5804, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_APM_NOC_LH, 0x1808, CMU_APM), + SFR(DBG_NFO_DIV_CLK_APM_NOC_LH, 0x5808, CMU_APM), + SFR(CLK_CON_DIV_DIV_CLK_AUR_NOCP, 0x180c, CMU_AUR), + SFR(DBG_NFO_DIV_CLK_AUR_NOCP, 0x580c, CMU_AUR), + SFR(CLK_CON_DIV_CLK_AUR_ADD_CH_CLK, 0x1800, CMU_AUR), + SFR(DBG_NFO_CLK_AUR_ADD_CH_CLK, 0x5800, CMU_AUR), + SFR(CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH, 0x1808, CMU_AUR), + SFR(DBG_NFO_DIV_CLK_AUR_AURCTL_LH, 0x5808, CMU_AUR), + SFR(CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH, 0x1810, CMU_AUR), + SFR(DBG_NFO_DIV_CLK_AUR_NOCP_LH, 0x5810, CMU_AUR), + SFR(CLK_CON_DIV_DIV_CLK_BO_NOCP, 0x1800, CMU_BO), + SFR(DBG_NFO_DIV_CLK_BO_NOCP, 0x5800, CMU_BO), + SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x186c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G3D_SWITCH, 0x586c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PERIC0_NOC, 0x18e8, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PERIC0_NOC, 0x58e8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MISC_NOC, 0x18c0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MISC_NOC, 0x58c0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI1_NOC, 0x1890, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI1_NOC, 0x5890, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_DPU_NOC, 0x1850, CMU_TOP), + SFR(DBG_NFO_CLKCMU_DPU_NOC, 0x5850, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MFC_MFC, 0x18b8, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MFC_MFC, 0x58b8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_G2D_G2D, 0x1858, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G2D_G2D, 0x5858, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0x1888, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI0_USB31DRD, 0x5888, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CSIS_NOC, 0x1844, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CSIS_NOC, 0x5844, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PERIC1_NOC, 0x18f0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PERIC1_NOC, 0x58f0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1838, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CPUCL0_SWITCH, 0x5838, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_NOCL0_NOC, 0x18c8, CMU_TOP), + SFR(DBG_NFO_CLKCMU_NOCL0_NOC, 0x58c8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_ITP_NOC, 0x18ac, CMU_TOP), + SFR(DBG_NFO_CLKCMU_ITP_NOC, 0x58ac, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0x1860, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G3AA_G3AA, 0x5860, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0x18b0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MCSC_ITSC, 0x58b0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_G2D_MSCL, 0x185c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G2D_MSCL, 0x585c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HPM, 0x187c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HPM, 0x587c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0x18a0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI2_PCIE, 0x58a0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0x1834, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CPUCL0_DBG, 0x5834, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1814, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK0, 0x5814, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1818, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK1, 0x5818, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x181c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK2, 0x581c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x1820, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK3, 0x5820, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_BO_NOC, 0x1810, CMU_TOP), + SFR(DBG_NFO_CLKCMU_BO_NOC, 0x5810, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0x18a4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI2_UFS_EMBD, 0x58a4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0x1880, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI0_DPGTC, 0x5880, CMU_TOP), + SFR(CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0x1924, CMU_TOP), + SFR(DBG_NFO_DIV_CLK_CMU_CMUREF, 0x5924, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MIF_NOCP, 0x18bc, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MIF_NOCP, 0x58bc, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PERIC0_IP, 0x18e4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PERIC0_IP, 0x58e4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PERIC1_IP, 0x18ec, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PERIC1_IP, 0x58ec, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_TPU_NOC, 0x18f8, CMU_TOP), + SFR(DBG_NFO_CLKCMU_TPU_NOC, 0x58f8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PDP_VRA, 0x18e0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PDP_VRA, 0x58e0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x183c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CPUCL1_SWITCH, 0x583c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0x1894, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI1_PCIE, 0x5894, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI0_NOC, 0x1884, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI0_NOC, 0x5884, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_IPP_NOC, 0x18a8, CMU_TOP), + SFR(DBG_NFO_CLKCMU_IPP_NOC, 0x58a8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK4, 0x1824, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK4, 0x5824, CMU_TOP), + SFR(CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0x1920, CMU_TOP), + SFR(DBG_NFO_DIV_CLKCMU_CMU_BOOST, 0x5920, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_TNR_NOC, 0x18f4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_TNR_NOC, 0x58f4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_NOCL2A_NOC, 0x18d4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_NOCL2A_NOC, 0x58d4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_NOCL1A_NOC, 0x18cc, CMU_TOP), + SFR(DBG_NFO_CLKCMU_NOCL1A_NOC, 0x58cc, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_NOCL1B_NOC, 0x18d0, CMU_TOP), + SFR(DBG_NFO_CLKCMU_NOCL1B_NOC, 0x58d0, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK5, 0x1828, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK5, 0x5828, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK6, 0x182c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK6, 0x582c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CIS_CLK7, 0x1830, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CIS_CLK7, 0x5830, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_DNS_NOC, 0x184c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_DNS_NOC, 0x584c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_GDC_GDC0, 0x1870, CMU_TOP), + SFR(DBG_NFO_CLKCMU_GDC_GDC0, 0x5870, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_GDC_GDC1, 0x1874, CMU_TOP), + SFR(DBG_NFO_CLKCMU_GDC_GDC1, 0x5874, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0x18b4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MCSC_MCSC, 0x58b4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_TPU_TPU, 0x18fc, CMU_TOP), + SFR(DBG_NFO_CLKCMU_TPU_TPU, 0x58fc, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI2_NOC, 0x189c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI2_NOC, 0x589c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0x1898, CMU_TOP), + SFR(DBG_NFO_CLKCMU_HSI2_MMC_CARD, 0x5898, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_G3D_GLB, 0x1864, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G3D_GLB, 0x5864, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0x1840, CMU_TOP), + SFR(DBG_NFO_CLKCMU_CPUCL2_SWITCH, 0x5840, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_GDC_SCSC, 0x1878, CMU_TOP), + SFR(DBG_NFO_CLKCMU_GDC_SCSC, 0x5878, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_MISC_SSS, 0x18c4, CMU_TOP), + SFR(DBG_NFO_CLKCMU_MISC_SSS, 0x58c4, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_DISP_NOC, 0x1848, CMU_TOP), + SFR(DBG_NFO_CLKCMU_DISP_NOC, 0x5848, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_EH_NOC, 0x1854, CMU_TOP), + SFR(DBG_NFO_CLKCMU_EH_NOC, 0x5854, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_PDP_NOC, 0x18dc, CMU_TOP), + SFR(DBG_NFO_CLKCMU_PDP_NOC, 0x58dc, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_TPU_UART, 0x1904, CMU_TOP), + SFR(DBG_NFO_CLKCMU_TPU_UART, 0x5904, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0x1900, CMU_TOP), + SFR(DBG_NFO_CLKCMU_TPU_TPUCTL, 0x5900, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED0_DIV5, 0x1934, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED0_DIV5, 0x5934, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_G3D_NOCD, 0x1868, CMU_TOP), + SFR(DBG_NFO_CLKCMU_G3D_NOCD, 0x5868, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_AUR_AUR, 0x1804, CMU_TOP), + SFR(DBG_NFO_CLKCMU_AUR_AUR, 0x5804, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_AUR_NOC, 0x180c, CMU_TOP), + SFR(DBG_NFO_CLKCMU_AUR_NOC, 0x580c, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_AUR_AURCTL, 0x1808, CMU_TOP), + SFR(DBG_NFO_CLKCMU_AUR_AURCTL, 0x5808, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED0_DIV2, 0x1928, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED0_DIV2, 0x5928, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED0_DIV4, 0x1930, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED0_DIV4, 0x5930, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED0_DIV3, 0x192c, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED0_DIV3, 0x592c, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED1_DIV2, 0x1938, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED1_DIV2, 0x5938, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED1_DIV4, 0x1940, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED1_DIV4, 0x5940, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED1_DIV3, 0x193c, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED1_DIV3, 0x593c, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED2_DIV2, 0x1944, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED2_DIV2, 0x5944, CMU_TOP), + SFR(CLK_CON_DIV_PLL_SHARED3_DIV2, 0x1948, CMU_TOP), + SFR(DBG_NFO_PLL_SHARED3_DIV2, 0x5948, CMU_TOP), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0x1814, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_CMUREF, 0x5814, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0x1800, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CLUSTER0_ACLK, 0x5800, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0x1804, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK, 0x5804, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0x180c, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CLUSTER0_PCLKDBG, 0x580c, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0x1810, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK, 0x5810, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x1828, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG, 0x5828, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0x182c, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_PCLK, 0x582c, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, 0x1820, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC, 0x5820, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH, 0x181c, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_DBG_ATCLK_LH, 0x581c, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH, 0x1824, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_LH, 0x5824, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH, 0x1808, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_LH, 0x5808, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH, 0x1830, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_PCLK_LH, 0x5830, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0x1800, CMU_CPUCL1), + SFR(DBG_NFO_DIV_CLK_CPUCL1_CMUREF, 0x5800, CMU_CPUCL1), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF, 0x1800, CMU_CPUCL2), + SFR(DBG_NFO_DIV_CLK_CPUCL2_CMUREF, 0x5800, CMU_CPUCL2), + SFR(CLK_CON_DIV_DIV_CLK_CSIS_NOCP, 0x1800, CMU_CSIS), + SFR(DBG_NFO_DIV_CLK_CSIS_NOCP, 0x5800, CMU_CSIS), + SFR(CLK_CON_DIV_DIV_CLK_DISP_NOCP, 0x1804, CMU_DISP), + SFR(DBG_NFO_DIV_CLK_DISP_NOCP, 0x5804, CMU_DISP), + SFR(CLK_CON_DIV_DIV_CLK_DNS_NOCP, 0x1800, CMU_DNS), + SFR(DBG_NFO_DIV_CLK_DNS_NOCP, 0x5800, CMU_DNS), + SFR(CLK_CON_DIV_DIV_CLK_DPU_NOCP, 0x1800, CMU_DPU), + SFR(DBG_NFO_DIV_CLK_DPU_NOCP, 0x5800, CMU_DPU), + SFR(CLK_CON_DIV_DIV_CLK_EH_NOCP, 0x1800, CMU_EH), + SFR(DBG_NFO_DIV_CLK_EH_NOCP, 0x5800, CMU_EH), + SFR(CLK_CON_DIV_DIV_CLK_EH_NOCP_LH, 0x1804, CMU_EH), + SFR(DBG_NFO_DIV_CLK_EH_NOCP_LH, 0x5804, CMU_EH), + SFR(CLK_CON_DIV_DIV_CLK_G2D_NOCP, 0x1800, CMU_G2D), + SFR(DBG_NFO_DIV_CLK_G2D_NOCP, 0x5800, CMU_G2D), + SFR(CLK_CON_DIV_DIV_CLK_G3AA_NOCP, 0x1800, CMU_G3AA), + SFR(DBG_NFO_DIV_CLK_G3AA_NOCP, 0x5800, CMU_G3AA), + SFR(CLK_CON_DIV_DIV_CLK_G3D_NOCP, 0x1808, CMU_G3D), + SFR(DBG_NFO_DIV_CLK_G3D_NOCP, 0x5808, CMU_G3D), + SFR(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK, 0x1800, CMU_G3D), + SFR(DBG_NFO_CLK_G3D_ADD_CH_CLK, 0x5800, CMU_G3D), + SFR(CLK_CON_DIV_DIV_CLK_G3D_TOP, 0x1814, CMU_G3D), + SFR(DBG_NFO_DIV_CLK_G3D_TOP, 0x5814, CMU_G3D), + SFR(CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH, 0x180c, CMU_G3D), + SFR(DBG_NFO_DIV_CLK_G3D_NOCP_LH, 0x580c, CMU_G3D), + SFR(CLK_CON_DIV_DIV_CLK_GDC_NOCP, 0x1800, CMU_GDC), + SFR(DBG_NFO_DIV_CLK_GDC_NOCP, 0x5800, CMU_GDC), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_NOCP, 0x180c, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_NOCP, 0x580c, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_NOCD, 0x1808, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_NOCD, 0x5808, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS, 0x1810, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_SPI_FPS, 0x5810, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC, 0x1814, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_SPI_GSC, 0x5814, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_UART, 0x1818, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_UART, 0x5818, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_NOC, 0x1804, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_NOC, 0x5804, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH, 0x1800, CMU_GSACORE), + SFR(DBG_NFO_DIV_CLK_GSACORE_CPU_LH, 0x5800, CMU_GSACORE), + SFR(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP, 0x1804, CMU_GSACTRL), + SFR(DBG_NFO_DIV_CLK_GSACTRL_NOCP, 0x5804, CMU_GSACTRL), + SFR(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD, 0x1800, CMU_GSACTRL), + SFR(DBG_NFO_DIV_CLK_GSACTRL_NOCD, 0x5800, CMU_GSACTRL), + SFR(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH, 0x1808, CMU_GSACTRL), + SFR(DBG_NFO_DIV_CLK_GSACTRL_NOCP_LH, 0x5808, CMU_GSACTRL), + SFR(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0x1808, CMU_HSI0), + SFR(DBG_NFO_DIV_CLK_HSI0_USB31DRD, 0x5808, CMU_HSI0), + SFR(CLK_CON_DIV_DIV_CLK_HSI0_USB, 0x1804, CMU_HSI0), + SFR(DBG_NFO_DIV_CLK_HSI0_USB, 0x5804, CMU_HSI0), + SFR(CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH, 0x1800, CMU_HSI0), + SFR(DBG_NFO_DIV_CLK_HSI0_NOC_LH, 0x5800, CMU_HSI0), + SFR(CLK_CON_DIV_DIV_CLK_HSI1_NOCP, 0x1800, CMU_HSI1), + SFR(DBG_NFO_DIV_CLK_HSI1_NOCP, 0x5800, CMU_HSI1), + SFR(CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH, 0x1804, CMU_HSI1), + SFR(DBG_NFO_DIV_CLK_HSI1_NOC_LH, 0x5804, CMU_HSI1), + SFR(CLK_CON_DIV_DIV_CLK_HSI2_NOCP, 0x1800, CMU_HSI2), + SFR(DBG_NFO_DIV_CLK_HSI2_NOCP, 0x5800, CMU_HSI2), + SFR(CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH, 0x1804, CMU_HSI2), + SFR(DBG_NFO_DIV_CLK_HSI2_NOC_LH, 0x5804, CMU_HSI2), + SFR(CLK_CON_DIV_DIV_CLK_IPP_NOCP, 0x1800, CMU_IPP), + SFR(DBG_NFO_DIV_CLK_IPP_NOCP, 0x5800, CMU_IPP), + SFR(CLK_CON_DIV_DIV_CLK_ITP_NOCP, 0x1800, CMU_ITP), + SFR(DBG_NFO_DIV_CLK_ITP_NOCP, 0x5800, CMU_ITP), + SFR(CLK_CON_DIV_DIV_CLK_MCSC_NOCP, 0x1800, CMU_MCSC), + SFR(DBG_NFO_DIV_CLK_MCSC_NOCP, 0x5800, CMU_MCSC), + SFR(CLK_CON_DIV_DIV_CLK_MFC_NOCP, 0x1800, CMU_MFC), + SFR(DBG_NFO_DIV_CLK_MFC_NOCP, 0x5800, CMU_MFC), + SFR(CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH, 0x1808, CMU_MIF), + SFR(DBG_NFO_DIV_CLK_MIF_NOCP_LH, 0x5808, CMU_MIF), + SFR(CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH, 0x1804, CMU_MIF), + SFR(DBG_NFO_DIV_CLK_MIF_NOCD_DBG_LH, 0x5804, CMU_MIF), + SFR(CLK_CON_DIV_DIV_CLK_MISC_NOCP, 0x1808, CMU_MISC), + SFR(DBG_NFO_DIV_CLK_MISC_NOCP, 0x5808, CMU_MISC), + SFR(CLK_CON_DIV_DIV_CLK_MISC_GIC, 0x1800, CMU_MISC), + SFR(DBG_NFO_DIV_CLK_MISC_GIC, 0x5800, CMU_MISC), + SFR(CLK_CON_DIV_DIV_CLK_MISC_GIC_LH, 0x1804, CMU_MISC), + SFR(DBG_NFO_DIV_CLK_MISC_GIC_LH, 0x5804, CMU_MISC), + SFR(CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH, 0x180c, CMU_MISC), + SFR(DBG_NFO_DIV_CLK_MISC_NOCP_LH, 0x580c, CMU_MISC), + SFR(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP, 0x1804, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_NOCL0_NOCP, 0x5804, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_SLC_DCLK, 0x1818, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_SLC_DCLK, 0x5818, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_SLC1_DCLK, 0x180c, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_SLC1_DCLK, 0x580c, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_SLC2_DCLK, 0x1810, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_SLC2_DCLK, 0x5810, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_SLC3_DCLK, 0x1814, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_SLC3_DCLK, 0x5814, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH, 0x1800, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_NOCL0_NOCD_LH, 0x5800, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH, 0x1808, CMU_NOCL0), + SFR(DBG_NFO_DIV_CLK_NOCL0_NOCP_LH, 0x5808, CMU_NOCL0), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP, 0x1804, CMU_NOCL1A), + SFR(DBG_NFO_DIV_CLK_NOCL1A_NOCP, 0x5804, CMU_NOCL1A), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH, 0x1800, CMU_NOCL1A), + SFR(DBG_NFO_DIV_CLK_NOCL1A_NOCD_LH, 0x5800, CMU_NOCL1A), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH, 0x1808, CMU_NOCL1A), + SFR(DBG_NFO_DIV_CLK_NOCL1A_NOCP_LH, 0x5808, CMU_NOCL1A), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP, 0x1804, CMU_NOCL1B), + SFR(DBG_NFO_DIV_CLK_NOCL1B_NOCP, 0x5804, CMU_NOCL1B), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH, 0x1800, CMU_NOCL1B), + SFR(DBG_NFO_DIV_CLK_NOCL1B_NOCD_LH, 0x5800, CMU_NOCL1B), + SFR(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH, 0x1808, CMU_NOCL1B), + SFR(DBG_NFO_DIV_CLK_NOCL1B_NOCP_LH, 0x5808, CMU_NOCL1B), + SFR(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP, 0x1804, CMU_NOCL2A), + SFR(DBG_NFO_DIV_CLK_NOCL2A_NOCP, 0x5804, CMU_NOCL2A), + SFR(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH, 0x1800, CMU_NOCL2A), + SFR(DBG_NFO_DIV_CLK_NOCL2A_NOCD_LH, 0x5800, CMU_NOCL2A), + SFR(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH, 0x1808, CMU_NOCL2A), + SFR(DBG_NFO_DIV_CLK_NOCL2A_NOCP_LH, 0x5808, CMU_NOCL2A), + SFR(CLK_CON_DIV_DIV_CLK_PDP_NOCP, 0x1800, CMU_PDP), + SFR(DBG_NFO_DIV_CLK_PDP_NOCP, 0x5800, CMU_PDP), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0x1824, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI6_USI, 0x5824, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0x1818, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI3_USI, 0x5818, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0x181c, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI4_USI, 0x581c, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0x1820, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI5_USI, 0x5820, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0x180c, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI14_USI, 0x580c, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0x1800, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_I3C, 0x5800, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0x1828, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI7_USI, 0x5828, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0x182c, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI8_USI, 0x582c, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0x1810, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI1_USI, 0x5810, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0x1808, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI0_UART, 0x5808, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0x1814, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_USI2_USI, 0x5814, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH, 0x1804, CMU_PERIC0), + SFR(DBG_NFO_DIV_CLK_PERIC0_NOCP_LH, 0x5804, CMU_PERIC0), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0x1810, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI11_USI, 0x5810, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0x1800, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_I3C, 0x5800, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0x1814, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI12_USI, 0x5814, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0x1808, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI0_USI, 0x5808, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0x1824, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI9_USI, 0x5824, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0x180c, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI10_USI, 0x580c, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0x1818, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI13_USI, 0x5818, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH, 0x1804, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_NOCP_LH, 0x5804, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, 0x181c, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI15_USI, 0x581c, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, 0x1820, CMU_PERIC1), + SFR(DBG_NFO_DIV_CLK_PERIC1_USI16_USI, 0x5820, CMU_PERIC1), + SFR(CLK_CON_DIV_DIV_CLK_S2D_CORE_LH, 0x1804, CMU_S2D), + SFR(DBG_NFO_DIV_CLK_S2D_CORE_LH, 0x5804, CMU_S2D), + SFR(CLK_CON_DIV_DIV_CLK_TNR_NOCP, 0x1800, CMU_TNR), + SFR(DBG_NFO_DIV_CLK_TNR_NOCP, 0x5800, CMU_TNR), + SFR(CLK_CON_DIV_DIV_CLK_TPU_NOCP, 0x1800, CMU_TPU), + SFR(DBG_NFO_DIV_CLK_TPU_NOCP, 0x5800, CMU_TPU), + SFR(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG, 0x1810, CMU_TPU), + SFR(DBG_NFO_DIV_CLK_TPU_TPUCTL_DBG, 0x5810, CMU_TPU), + SFR(CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH, 0x1804, CMU_TPU), + SFR(DBG_NFO_DIV_CLK_TPU_NOCP_LH, 0x5804, CMU_TPU), + SFR(CLK_CON_DIV_DIV_CLK_AUR_AUR, 0x1804, CMU_AUR), + SFR(DBG_NFO_DIV_CLK_AUR_AUR, 0x5804, CMU_AUR), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x1818, CMU_CPUCL0), + SFR(DBG_NFO_DIV_CLK_CPUCL0_CPU, 0x5818, CMU_CPUCL0), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x1804, CMU_CPUCL1), + SFR(DBG_NFO_DIV_CLK_CPUCL1_CPU, 0x5804, CMU_CPUCL1), + SFR(CLK_CON_DIV_DIV_CLK_CPUCL2_CPU, 0x1804, CMU_CPUCL2), + SFR(DBG_NFO_DIV_CLK_CPUCL2_CPU, 0x5804, CMU_CPUCL2), + SFR(CLK_CON_DIV_DIV_CLK_G3D_STACKS, 0x1810, CMU_G3D), + SFR(DBG_NFO_DIV_CLK_G3D_STACKS, 0x5810, CMU_G3D), + SFR(CLK_CON_DIV_DIV_CLK_G3D_L2_GLB, 0x1804, CMU_G3D), + SFR(DBG_NFO_DIV_CLK_G3D_L2_GLB, 0x5804, CMU_G3D), + SFR(CLK_CON_DIV_DIV_CLK_TPU_TPU, 0x1808, CMU_TPU), + SFR(DBG_NFO_DIV_CLK_TPU_TPU, 0x5808, CMU_TPU), + SFR(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL, 0x180c, CMU_TPU), + SFR(DBG_NFO_DIV_CLK_TPU_TPUCTL, 0x580c, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK, 0x2004, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK, 0x2048, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK, 0x204c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK, 0x2050, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK, 0x2054, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK, 0x2058, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK, 0x205c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK, 0x2060, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK, 0x2068, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK, 0x2064, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK, 0x2078, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK, 0x2074, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1, 0x207c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2, 0x2080, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK, 0x2084, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK, 0x2088, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK, 0x208c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK, 0x2090, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK, 0x2094, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK, 0x206c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK, 0x2070, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK, 0x2044, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK, 0x2020, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK, 0x2014, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK, 0x2024, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK, 0x2018, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK, 0x203c, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK, 0x2040, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK, 0x2010, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK, 0x2008, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK, 0x2038, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK, 0x2028, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK, 0x201c, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK, 0x202c, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK, 0x2030, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK, 0x2034, CMU_AOC), + SFR(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK, 0x200c, CMU_AOC), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, 0x20cc, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK, 0x20f4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 0x2148, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 0x211c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, 0x20d4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, 0x2090, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 0x20c0, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 0x20c4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, 0x20e8, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, 0x214c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 0x200c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, 0x20bc, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, 0x2088, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 0x2098, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 0x20b4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, 0x20d0, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, 0x20e4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 0x2094, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, 0x20d8, CMU_APM), + SFR(CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 0x2084, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 0x2104, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 0x2108, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK, 0x210c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK, 0x2110, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, 0x2118, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 0x20b8, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 0x2120, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 0x2124, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, 0x2128, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, 0x212c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK, 0x2140, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK, 0x2144, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK, 0x2138, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK, 0x213c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, 0x208c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, 0x20ec, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, 0x20f0, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, 0x2114, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, 0x20dc, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, 0x20e0, CMU_APM), + SFR(CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1, 0x2080, CMU_APM), + SFR(CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1, 0x207c, CMU_APM), + SFR(CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 0x2078, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK, 0x20c8, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK, 0x2130, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK, 0x2134, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, 0x20a0, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, 0x20b0, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, 0x20a8, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, 0x20f8, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, 0x2100, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, 0x20fc, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, 0x209c, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, 0x20a4, CMU_APM), + SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, 0x20ac, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK, 0x203c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK, 0x2040, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK, 0x2044, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK, 0x2048, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK, 0x204c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK, 0x2050, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK, 0x2054, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK, 0x2010, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK, 0x2014, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, 0x2008, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, 0x2004, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, 0x2000, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK, 0x2060, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK, 0x2038, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK, 0x2070, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, 0x2074, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK, 0x206c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK, 0x2068, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, 0x2028, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, 0x2018, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, 0x202c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, 0x201c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK, 0x2030, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK, 0x2020, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK, 0x2034, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK, 0x2024, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK, 0x2064, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, 0x205c, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK, 0x2058, CMU_APM), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK, 0x2018, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK, 0x201c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM, 0x2014, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK, 0x2030, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK, 0x2034, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK, 0x2048, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK, 0x2084, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK, 0x2088, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK, 0x208c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK, 0x2090, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK, 0x2054, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK, 0x2058, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK, 0x205c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK, 0x2060, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1, 0x2094, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1, 0x209c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2, 0x20a0, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2, 0x2098, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK, 0x20a4, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK, 0x20a8, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK, 0x20ac, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK, 0x204c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK, 0x2064, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK, 0x2070, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK, 0x2074, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM, 0x2010, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK, 0x200c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK, 0x207c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK, 0x206c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK, 0x202c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, 0x2040, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, 0x203c, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2038, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK, 0x2050, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK, 0x2080, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK, 0x2044, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK, 0x2068, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK, 0x2078, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK, 0x2024, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK, 0x2028, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK, 0x2020, CMU_AUR), + SFR(CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK, 0x2000, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK, 0x201c, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK, 0x2030, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK, 0x2020, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK, 0x2024, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1, 0x203c, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM, 0x2010, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK, 0x2044, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK, 0x2028, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK, 0x202c, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK, 0x2038, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK, 0x2014, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK, 0x2034, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK, 0x2018, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK, 0x2048, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK, 0x204c, CMU_BO), + SFR(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2, 0x2040, CMU_BO), + SFR(CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK, 0x2004, CMU_BO), + SFR(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK, 0x200c, CMU_BO), + SFR(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK, 0x2008, CMU_BO), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC, 0x20b8, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_MIF_SWITCH, 0x2010, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 0x20e0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 0x2080, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, 0x20b0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC, 0x20c4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_DPU_NOC, 0x2078, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x2094, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MISC_NOC, 0x20e8, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC, 0x206c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC, 0x210c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC, 0x2114, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2060, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC, 0x20f0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_ITP_NOC, 0x20d4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, 0x2088, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 0x20d8, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 0x2084, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HPM, 0x20a4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 0x20c8, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC, 0x205c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x2038, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x203c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x2044, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2040, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_BO_NOC, 0x2034, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, 0x20cc, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, 0x20a8, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP, 0x20e4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 0x2108, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 0x2110, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TPU_NOC, 0x2120, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, 0x20b4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, 0x2104, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2064, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 0x20bc, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC, 0x20ac, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_IPP_NOC, 0x20d0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 0x2048, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TNR_NOC, 0x2118, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC, 0x20fc, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC, 0x20f4, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC, 0x20f8, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 0x204c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 0x2050, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 0x2054, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, 0x2000, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, 0x2004, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_NOCL1B_BOOST, 0x201c, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_NOCL2A_BOOST, 0x2020, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_NOCL1A_BOOST, 0x2018, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_NOCL0_BOOST, 0x2014, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_MIF_BOOST, 0x200c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_DNS_NOC, 0x2074, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 0x2098, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 0x209c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 0x20dc, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 0x2124, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 0x2058, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, 0x20c0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 0x208c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, 0x2068, CMU_TOP), + SFR(CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, 0x2008, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 0x20a0, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 0x20ec, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_DISP_NOC, 0x2070, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_EH_NOC, 0x207c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, 0x211c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_PDP_NOC, 0x2100, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 0x212c, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, 0x2128, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD, 0x2090, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_AUR_AUR, 0x2028, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_AUR_NOC, 0x2030, CMU_TOP), + SFR(CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL, 0x202c, CMU_TOP), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x2190, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK, 0x2100, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, 0x20c0, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, 0x2180, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x20f4, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK, 0x210c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK, 0x2124, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK, 0x2110, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK, 0x2128, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK, 0x2114, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK, 0x2118, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, 0x20bc, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, 0x20b0, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK, 0x2104, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK, 0x212c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK, 0x2130, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK, 0x2134, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK, 0x2138, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, 0x20e0, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, 0x216c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, 0x2170, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, 0x2174, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2010, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, 0x200c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, 0x20f0, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK, 0x211c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK, 0x2120, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK, 0x2108, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK, 0x213c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK, 0x2140, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, 0x20f8, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, 0x215c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, 0x214c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, 0x2198, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, 0x217c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, 0x201c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, 0x2018, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, 0x20e4, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, 0x20ec, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, 0x2008, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, 0x2004, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK, 0x2144, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK, 0x20fc, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, 0x2160, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, 0x2194, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, 0x2150, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK, 0x2188, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK, 0x2184, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2, 0x218c, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK, 0x2154, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM, 0x20e8, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK, 0x2164, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, 0x2168, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK, 0x2148, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, 0x2158, CMU_CPUCL0), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK, 0x2178, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, 0x20d0, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK, 0x209c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK, 0x208c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, 0x2030, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, 0x202c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, 0x2020, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK, 0x20d4, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, 0x20a4, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, 0x2094, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, 0x2028, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, 0x2034, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, 0x2024, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK, 0x20c8, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, 0x20a0, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, 0x2090, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK, 0x204c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK, 0x2078, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK, 0x2048, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, 0x2054, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, 0x207c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2050, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, 0x205c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2080, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2058, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, 0x20cc, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK, 0x20a8, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2098, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, 0x203c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, 0x2044, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2070, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2038, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2074, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, 0x2040, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, 0x2064, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK, 0x206c, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK, 0x2084, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK, 0x2060, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK, 0x2088, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK, 0x2068, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK, 0x20b8, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK, 0x20b4, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK, 0x20ac, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK, 0x20c4, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK, 0x2014, CMU_CPUCL0), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1, 0x2008, CMU_CPUCL1), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0, 0x2004, CMU_CPUCL1), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2000, CMU_CPUCL1), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN, 0x200c, CMU_CPUCL1), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, 0x2000, CMU_CPUCL2), + SFR(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK, 0x2014, CMU_CPUCL2), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0, 0x2004, CMU_CPUCL2), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1, 0x2008, CMU_CPUCL2), + SFR(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN, 0x200c, CMU_CPUCL2), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, 0x2064, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, 0x20f4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, 0x2118, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, 0x20ec, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, 0x20f0, CMU_CSIS), + SFR(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, 0x2000, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, 0x204c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, 0x2070, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, 0x2074, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, 0x2078, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, 0x2020, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, 0x2080, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, 0x2048, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, 0x2090, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, 0x207c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, 0x2044, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, 0x2034, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, 0x2038, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, 0x203c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, 0x2050, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, 0x2054, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, 0x2058, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK, 0x2024, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, 0x2010, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, 0x208c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, 0x2094, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, 0x2098, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, 0x210c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, 0x2110, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK, 0x2100, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK, 0x2104, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK, 0x20f8, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK, 0x20fc, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, 0x20dc, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, 0x20e0, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, 0x20e4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, 0x20e8, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, 0x20d4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, 0x20d8, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, 0x20bc, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, 0x20c0, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, 0x211c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, 0x2120, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6, 0x2084, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7, 0x2088, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, 0x2040, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, 0x2068, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, 0x2108, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, 0x2114, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, 0x2028, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, 0x202c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, 0x2030, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, 0x205c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK, 0x2060, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, 0x20cc, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, 0x20d0, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, 0x20c4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, 0x20c8, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, 0x2124, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, 0x206c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF, 0x201c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA, 0x2018, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS, 0x2014, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, 0x209c, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, 0x20a0, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, 0x20a4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, 0x20a8, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, 0x20ac, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, 0x20b0, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, 0x20b4, CMU_CSIS), + SFR(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, 0x20b8, CMU_CSIS), + SFR(CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK, 0x2000, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, 0x2010, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK, 0x2028, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK, 0x2020, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON, 0x2014, CMU_DISP), + SFR(CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK, 0x200c, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK, 0x2018, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK, 0x201c, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK, 0x2024, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK, 0x202c, CMU_DISP), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM, 0x2028, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, 0x2034, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, 0x202c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK, 0x2038, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK, 0x208c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK, 0x2070, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, 0x2074, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, 0x2078, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK, 0x2090, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK, 0x2094, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1, 0x2098, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, 0x20a0, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK, 0x2084, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK, 0x2088, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2, 0x209c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, 0x2048, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, 0x2050, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, 0x204c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, 0x2054, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, 0x2058, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, 0x2040, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, 0x205c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, 0x2044, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, 0x2060, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK, 0x206c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK, 0x20a4, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK, 0x2064, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK, 0x2068, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK, 0x207c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK, 0x2080, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, 0x203c, CMU_DNS), + SFR(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, 0x2030, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, 0x2000, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK, 0x2020, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK, 0x2024, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, 0x200c, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, 0x2010, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK, 0x2014, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK, 0x2018, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK, 0x2004, CMU_DNS), + SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 0x2000, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 0x2084, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, 0x206c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, 0x2050, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, 0x2028, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK, 0x202c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, 0x207c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, 0x2074, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 0x2030, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 0x2034, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 0x2038, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 0x203c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 0x2040, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 0x2044, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK, 0x2048, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK, 0x204c, CMU_DPU), + SFR(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, 0x200c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, 0x2024, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 0x2014, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 0x2018, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 0x201c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, 0x2070, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, 0x2078, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 0x2080, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, 0x2010, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 0x2054, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 0x205c, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 0x2064, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 0x2020, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 0x2058, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 0x2060, CMU_DPU), + SFR(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 0x2068, CMU_DPU), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK, 0x2000, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM, 0x2024, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK, 0x2028, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK, 0x2030, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK, 0x2038, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK, 0x2034, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK, 0x202c, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK, 0x204c, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK, 0x2050, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK, 0x203c, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK, 0x2040, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2, 0x2054, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK, 0x2058, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK, 0x205c, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK, 0x2060, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK, 0x2044, CMU_EH), + SFR(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK, 0x2048, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK, 0x2010, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK, 0x2014, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK, 0x201c, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK, 0x200c, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK, 0x2018, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK, 0x2008, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK, 0x2004, CMU_EH), + SFR(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, 0x2000, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK, 0x2030, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK, 0x2034, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK, 0x2038, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK, 0x203c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1, 0x2070, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, 0x2088, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK, 0x2028, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK, 0x202c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1, 0x2080, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK, 0x2040, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK, 0x2044, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK, 0x2024, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK, 0x2048, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK, 0x2050, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK, 0x204c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK, 0x205c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, 0x2018, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1, 0x2078, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, 0x2020, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK, 0x2014, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK, 0x2058, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK, 0x2060, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK, 0x2064, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK, 0x2068, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK, 0x206c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK, 0x201c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2, 0x2074, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2, 0x207c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2, 0x2084, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK, 0x2054, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM, 0x200c, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM, 0x2010, CMU_G2D), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK, 0x2034, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM, 0x2010, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK, 0x2040, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK, 0x2044, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK, 0x2058, CMU_G3AA), + SFR(CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK, 0x2000, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK, 0x2038, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK, 0x2014, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK, 0x201c, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM, 0x2018, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK, 0x203c, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK, 0x2048, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK, 0x204c, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1, 0x2050, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2, 0x2054, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, 0x2020, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, 0x202c, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, 0x2024, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, 0x2028, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, 0x2030, CMU_G3AA), + SFR(CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK, 0x200c, CMU_G3AA), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK, 0x205c, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, 0x2048, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, 0x2020, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2070, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, 0x2068, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, 0x2030, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2010, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK, 0x2060, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, 0x201c, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK, 0x2058, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, 0x2054, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, 0x204c, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK, 0x2050, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK, 0x2074, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK, 0x2078, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, 0x2018, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK, 0x206c, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, 0x2044, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, 0x2000, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, 0x2014, CMU_G3D), + SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK, 0x2064, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH, 0x2008, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, 0x2034, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK, 0x2028, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK, 0x202c, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM, 0x2004, CMU_G3D), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK, 0x2000, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM, 0x2084, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM, 0x2088, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM, 0x208c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK, 0x2090, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK, 0x2098, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK, 0x20a0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK, 0x20a4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK, 0x20d0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK, 0x20d8, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK, 0x20e8, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK, 0x2110, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK, 0x211c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK, 0x212c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK, 0x2120, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK, 0x2124, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1, 0x2140, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2, 0x2144, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK, 0x2148, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK, 0x20a8, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK, 0x20ac, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, 0x20b0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, 0x20b4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, 0x20b8, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK, 0x20bc, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK, 0x20c0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, 0x20c4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK, 0x2108, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK, 0x2104, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK, 0x20fc, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK, 0x2100, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK, 0x2094, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK, 0x209c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK, 0x210c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK, 0x20d4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK, 0x20e4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK, 0x2118, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK, 0x2128, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1, 0x2130, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2, 0x2134, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1, 0x2138, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2, 0x213c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK, 0x20c8, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK, 0x20dc, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK, 0x214c, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK, 0x20f4, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK, 0x20ec, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK, 0x2114, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK, 0x20cc, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK, 0x20e0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK, 0x20f0, CMU_GDC), + SFR(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK, 0x20f8, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK, 0x207c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK, 0x2080, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK, 0x2018, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK, 0x201c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK, 0x2028, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK, 0x202c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK, 0x2010, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK, 0x2014, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK, 0x2020, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK, 0x2024, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK, 0x2064, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK, 0x2068, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK, 0x2074, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK, 0x2078, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK, 0x205c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK, 0x2060, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK, 0x206c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK, 0x2070, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK, 0x2030, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK, 0x2034, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK, 0x2038, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK, 0x203c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK, 0x2040, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK, 0x2044, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK, 0x2048, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK, 0x204c, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK, 0x2050, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK, 0x2054, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, 0x2004, CMU_GDC), + SFR(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, 0x2008, CMU_GDC), + SFR(CLK_CON_GAT_CLK_GSACORE, 0x2048, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK, 0x200c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN, 0x2054, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK, 0x205c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK, 0x206c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK, 0x208c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK, 0x2094, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK, 0x20a0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK, 0x20a8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK, 0x20b0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK, 0x20b4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK, 0x20d8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK, 0x20e0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK, 0x20e8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK, 0x20f0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK, 0x20fc, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK, 0x2104, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK, 0x2114, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK, 0x2050, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK, 0x20b8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK, 0x20bc, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK, 0x20c0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK, 0x2060, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK, 0x2084, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK, 0x2088, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK, 0x2058, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK, 0x2068, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK, 0x209c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK, 0x2090, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK, 0x20a4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK, 0x20ac, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK, 0x20ec, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK, 0x20e4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK, 0x20d4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK, 0x20dc, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK, 0x2100, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK, 0x20c8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK, 0x20cc, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK, 0x20d0, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1, 0x20f4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK, 0x20c4, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2, 0x20f8, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM, 0x204c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK, 0x2098, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK, 0x2118, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK, 0x2080, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI, 0x2110, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB, 0x210c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK, 0x2070, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK, 0x2074, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM, 0x2108, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM, 0x2004, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK, 0x2008, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK, 0x2064, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK, 0x207c, CMU_GSACORE), + SFR(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK, 0x2078, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2014, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, 0x2018, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2010, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK, 0x2038, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, 0x2028, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, 0x201c, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, 0x202c, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, 0x2020, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK, 0x2030, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK, 0x2024, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK, 0x2034, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK, 0x2044, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK, 0x2040, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK, 0x203c, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM, 0x2000, CMU_GSACORE), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK, 0x2004, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK, 0x2034, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK, 0x204c, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK, 0x2054, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK, 0x2058, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK, 0x2050, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK, 0x2078, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK, 0x2080, CMU_GSACTRL), + SFR(CLK_CON_GAT_GATE_CLK_GSA_FUNC, 0x2020, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK, 0x2038, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK, 0x2040, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK, 0x205c, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK, 0x2060, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK, 0x2064, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK, 0x2068, CMU_GSACTRL), + SFR(CLK_CON_GAT_GATE_CLK_GSACTRL2CORE, 0x201c, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK, 0x2028, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK, 0x207c, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK, 0x2030, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK, 0x2044, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK, 0x206c, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK, 0x2074, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK, 0x2070, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK, 0x2048, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM, 0x2024, CMU_GSACTRL), + SFR(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK, 0x203c, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK, 0x2018, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK, 0x2010, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK, 0x2014, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, 0x200c, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, 0x2008, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK, 0x202c, CMU_GSACTRL), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, 0x2000, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, 0x2098, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, 0x2068, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, 0x2038, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, 0x20b0, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 0x2044, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK, 0x2060, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK, 0x2064, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, 0x2058, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, 0x205c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK, 0x2054, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, 0x2050, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, 0x209c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 0x204c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 0x2048, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, 0x2040, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 0x203c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, 0x2070, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, 0x206c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, 0x2074, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, 0x2078, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, 0x208c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, 0x20a0, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, 0x20a4, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, 0x2090, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, 0x20b8, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, 0x2094, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_HSI0_ALT, 0x2034, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, 0x20b4, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, 0x207c, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, 0x2080, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, 0x2084, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, 0x2088, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, 0x20ac, CMU_HSI0), + SFR(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, 0x20a8, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1, 0x202c, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK, 0x2020, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK, 0x2024, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, 0x2028, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, 0x2010, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, 0x2004, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK, 0x2014, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK, 0x2008, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK, 0x2018, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK, 0x200c, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK, 0x201c, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, 0x2030, CMU_HSI0), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, 0x2000, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, 0x2034, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK, 0x2038, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, 0x20a8, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, 0x20cc, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, 0x2094, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, 0x2078, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, 0x207c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, 0x20a4, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, 0x20d0, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 0x2068, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x203c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2040, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2048, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 0x204c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2044, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK, 0x2070, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK, 0x2074, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, 0x2028, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK, 0x202c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK, 0x209c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK, 0x20a0, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x2050, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2054, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2058, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x205c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 0x2060, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, 0x2030, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, 0x2098, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK, 0x2080, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK, 0x2084, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK, 0x208c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK, 0x2088, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK, 0x20ac, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK, 0x20b0, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK, 0x20b4, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK, 0x20b8, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK, 0x20bc, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK, 0x20c0, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK, 0x20c4, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK, 0x20c8, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 0x2064, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK, 0x2014, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK, 0x2010, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK, 0x2018, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK, 0x201c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM, 0x2024, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 0x206c, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK, 0x2090, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, 0x2020, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, 0x200c, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK, 0x2004, CMU_HSI1), + SFR(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK, 0x2008, CMU_HSI1), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, 0x203c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, 0x20c4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 0x2038, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK, 0x2040, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK, 0x2044, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, 0x20f4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, 0x20f8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, 0x2084, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, 0x2088, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2058, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x2050, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, 0x2074, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x205c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK, 0x20b0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, 0x20b4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, 0x20c0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, 0x20b8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2054, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, 0x207c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, 0x2030, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x20e8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x20f0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x20ec, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, 0x2080, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 0x2008, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, 0x200c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, 0x2060, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, 0x2068, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, 0x2064, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x206c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 0x2034, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, 0x20bc, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2048, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x204c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, 0x2094, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, 0x2098, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, 0x209c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, 0x20a0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, 0x20a4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, 0x20a8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, 0x20c8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, 0x20cc, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, 0x20d0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, 0x20d4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, 0x20d8, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, 0x20dc, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, 0x20e0, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, 0x20e4, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, 0x2070, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, 0x208c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, 0x2090, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, 0x2018, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, 0x201c, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, 0x2020, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, 0x2024, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM, 0x202c, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, 0x2078, CMU_HSI2), + SFR(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK, 0x20ac, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK, 0x2000, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1, 0x2028, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK, 0x2014, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK, 0x2004, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK, 0x2010, CMU_HSI2), + SFR(CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK, 0x2000, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK, 0x2010, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK, 0x20cc, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK, 0x2138, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK, 0x20c0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK, 0x20c4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, 0x2038, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, 0x2024, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM, 0x200c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK, 0x2048, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, 0x202c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, 0x2030, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, 0x2034, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, 0x203c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, 0x2040, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, 0x2044, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK, 0x2050, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK, 0x2054, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK, 0x20c8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1, 0x2130, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK, 0x2014, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2, 0x2134, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK, 0x2118, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK, 0x211c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK, 0x204c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK, 0x2058, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK, 0x205c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK, 0x2060, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK, 0x2064, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK, 0x2068, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK, 0x206c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK, 0x20d0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK, 0x20d4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK, 0x20d8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK, 0x20dc, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK, 0x2144, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK, 0x213c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK, 0x20a8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK, 0x20ac, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, 0x2018, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, 0x201c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, 0x2020, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, 0x2028, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK, 0x2148, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK, 0x2140, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK, 0x20f8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK, 0x20fc, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK, 0x2104, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK, 0x2108, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK, 0x210c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK, 0x2110, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK, 0x2114, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK, 0x20e0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK, 0x20e4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK, 0x20e8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK, 0x20ec, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK, 0x2088, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK, 0x208c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK, 0x2090, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK, 0x2094, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK, 0x2098, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK, 0x209c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK, 0x20a0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK, 0x20a4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK, 0x2070, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK, 0x2074, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK, 0x2078, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK, 0x207c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK, 0x2124, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK, 0x2120, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK, 0x20f0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK, 0x20f4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK, 0x20b4, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK, 0x20b0, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK, 0x2084, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK, 0x2080, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK, 0x212c, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK, 0x2128, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK, 0x20b8, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK, 0x20bc, CMU_IPP), + SFR(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK, 0x2100, CMU_IPP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, 0x2000, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, 0x2028, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, 0x202c, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK, 0x2030, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, 0x2034, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK, 0x204c, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, 0x2050, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK, 0x2044, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK, 0x2048, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, 0x2038, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, 0x203c, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, 0x2040, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK, 0x2020, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK, 0x2024, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK, 0x2014, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK, 0x2018, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK, 0x200c, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK, 0x2010, CMU_ITP), + SFR(CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK, 0x2004, CMU_ITP), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, 0x20d8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, 0x2064, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, 0x2114, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, 0x2004, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, 0x2044, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK, 0x2018, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, 0x201c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, 0x2030, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, 0x205c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, 0x2048, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK, 0x2034, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK, 0x203c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK, 0x2038, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK, 0x20e8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, 0x20fc, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, 0x2088, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK, 0x20dc, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK, 0x20e0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK, 0x208c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK, 0x2090, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK, 0x207c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK, 0x2080, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, 0x2100, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, 0x2054, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK, 0x2070, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM, 0x2024, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, 0x2028, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, 0x2078, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, 0x2084, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, 0x20d4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK, 0x20e4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK, 0x2074, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, 0x2068, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, 0x2104, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, 0x2108, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, 0x204c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK, 0x2040, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, 0x2050, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK, 0x2058, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, 0x2060, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK, 0x20ec, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK, 0x20f0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, 0x2094, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, 0x2098, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK, 0x20f4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK, 0x20f8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK, 0x20a4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK, 0x20a8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK, 0x20b4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK, 0x20b8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK, 0x209c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK, 0x20a0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK, 0x20ac, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK, 0x20b0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK, 0x20bc, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK, 0x20c0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK, 0x20c4, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK, 0x20c8, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, 0x210c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, 0x2110, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, 0x206c, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK, 0x20cc, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK, 0x20d0, CMU_MCSC), + SFR(CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK, 0x202c, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK, 0x2008, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK, 0x200c, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK, 0x2010, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK, 0x2014, CMU_MCSC), + SFR(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, 0x2004, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, 0x200c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, 0x2064, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK, 0x2018, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK, 0x201c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, 0x2040, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1, 0x2054, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1, 0x205c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK, 0x2024, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK, 0x2028, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK, 0x202c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK, 0x2030, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK, 0x2034, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK, 0x203c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK, 0x2048, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, 0x2020, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK, 0x2038, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, 0x2010, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK, 0x2044, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK, 0x204c, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK, 0x2050, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK, 0x2014, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2, 0x2058, CMU_MFC), + SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2, 0x2060, CMU_MFC), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2010, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, 0x2040, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2060, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK, 0x2054, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK, 0x203c, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, 0x2034, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, 0x2038, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, 0x2044, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, 0x205c, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, 0x2028, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, 0x2058, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK, 0x2050, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, 0x2048, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, 0x2014, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, 0x2020, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK, 0x204c, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK, 0x2004, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, 0x202c, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK, 0x200c, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK, 0x2008, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK, 0x2000, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK, 0x2024, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK, 0x2018, CMU_MIF), + SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK, 0x201c, CMU_MIF), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, 0x2138, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 0x2148, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 0x2144, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK, 0x20ec, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, 0x2044, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, 0x20e4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 0x20a0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, 0x2078, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, 0x209c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x20a8, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, 0x2074, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, 0x213c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, 0x2140, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, 0x201c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, 0x2020, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 0x2024, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, 0x20a4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, 0x2070, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK, 0x2094, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK, 0x2080, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK, 0x20e8, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK, 0x20ac, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, 0x20b0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, 0x20b4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, 0x20bc, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, 0x20c0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK, 0x20c4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK, 0x20c8, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, 0x2018, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, 0x20cc, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, 0x20d0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK, 0x20d4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK, 0x20d8, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, 0x20e0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, 0x20f4, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, 0x20f8, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK, 0x20fc, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, 0x212c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, 0x2124, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, 0x207c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, 0x2068, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM, 0x2064, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, 0x206c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, 0x2084, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK, 0x208c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, 0x2088, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK, 0x2098, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, 0x20b8, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, 0x20dc, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, 0x20f0, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, 0x2128, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, 0x214c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, 0x2130, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, 0x2134, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK, 0x2090, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, 0x2120, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, 0x2110, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, 0x2114, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK, 0x2118, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK, 0x211c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK, 0x2108, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK, 0x210c, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, 0x2100, CMU_MISC), + SFR(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, 0x2104, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK, 0x203c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK, 0x2040, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, 0x2004, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, 0x200c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, 0x2000, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, 0x2008, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK, 0x204c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK, 0x2014, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK, 0x2050, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK, 0x2030, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK, 0x202c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK, 0x2034, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK, 0x2038, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK, 0x2054, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK, 0x2058, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK, 0x205c, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK, 0x2060, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK, 0x2028, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK, 0x2048, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK, 0x2010, CMU_MISC), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, 0x20d8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, 0x2264, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, 0x2278, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, 0x2210, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, 0x2214, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, 0x20fc, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK, 0x2160, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK, 0x2164, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, 0x226c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM, 0x213c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, 0x2268, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, 0x2150, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, 0x2140, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK, 0x2154, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK, 0x2200, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK, 0x2204, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK, 0x2208, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK, 0x220c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, 0x2238, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK, 0x21d4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK, 0x21d8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK, 0x21dc, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK, 0x21e0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK, 0x21e4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK, 0x21e8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK, 0x21ec, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK, 0x21f0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK, 0x21f8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK, 0x21fc, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK, 0x219c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK, 0x223c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK, 0x2148, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK, 0x215c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK, 0x21b8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0, 0x2270, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK, 0x21c8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK, 0x21cc, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK, 0x21bc, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK, 0x21c0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK, 0x21a0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK, 0x21a4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK, 0x217c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK, 0x2180, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK, 0x2184, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK, 0x2188, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK, 0x218c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK, 0x2190, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK, 0x2194, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK, 0x2198, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK, 0x21c4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK, 0x2178, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK, 0x21d0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK, 0x21f4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK, 0x21b4, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, 0x2168, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, 0x216c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, 0x2170, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, 0x2174, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK, 0x21ac, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK, 0x21a8, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0, 0x2274, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK, 0x2258, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK, 0x225c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK, 0x20e8, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK, 0x20e4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK, 0x20e0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK, 0x20dc, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK, 0x20ec, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK, 0x20f0, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK, 0x2230, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK, 0x2234, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK, 0x2240, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK, 0x2244, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK, 0x2248, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK, 0x224c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK, 0x2250, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK, 0x2254, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, 0x2144, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK, 0x214c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK, 0x2218, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK, 0x2220, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK, 0x2228, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK, 0x221c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK, 0x2224, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK, 0x222c, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK, 0x2158, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK, 0x2260, CMU_NOCL0), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK, 0x21b0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK, 0x2034, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK, 0x201c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK, 0x2024, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK, 0x202c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK, 0x203c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK, 0x2044, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, 0x2010, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK, 0x210c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2110, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK, 0x2114, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK, 0x2118, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, 0x211c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, 0x2120, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, 0x2124, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, 0x2128, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK, 0x212c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, 0x2130, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, 0x2134, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, 0x2074, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK, 0x207c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK, 0x20ac, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK, 0x20b0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK, 0x20b4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK, 0x20b8, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK, 0x20bc, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK, 0x20c0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK, 0x20c4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK, 0x20c8, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK, 0x20cc, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK, 0x20d0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK, 0x20d4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK, 0x2070, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2084, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK, 0x2088, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK, 0x20f8, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK, 0x20f4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK, 0x2090, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK, 0x2094, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK, 0x2098, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK, 0x209c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK, 0x20a0, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK, 0x20a4, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK, 0x20a8, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK, 0x204c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK, 0x2020, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK, 0x2028, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK, 0x2054, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK, 0x2030, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, 0x2038, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, 0x2040, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK, 0x2048, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK, 0x2064, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, 0x2100, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, 0x2104, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, 0x2108, CMU_NOCL0), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, 0x2024, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, 0x213c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, 0x2140, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, 0x2108, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, 0x210c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, 0x2138, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, 0x2078, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, 0x2084, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, 0x2088, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK, 0x2114, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK, 0x2090, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0, 0x2134, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK, 0x2098, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK, 0x207c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK, 0x2118, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK, 0x211c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK, 0x2120, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK, 0x2124, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK, 0x2128, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK, 0x212c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK, 0x2130, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK, 0x209c, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM, 0x2074, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, 0x2148, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK, 0x2094, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK, 0x20d8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK, 0x20dc, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK, 0x20e0, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK, 0x20e4, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK, 0x20e8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK, 0x20ec, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK, 0x20f0, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK, 0x20f4, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK, 0x20b0, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK, 0x20b4, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK, 0x20b8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK, 0x20bc, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK, 0x20c0, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK, 0x20c4, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK, 0x20c8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK, 0x20cc, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK, 0x2100, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK, 0x2104, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A, 0x2144, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK, 0x20d0, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK, 0x20d4, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK, 0x20a8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK, 0x20ac, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK, 0x20f8, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK, 0x20fc, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, 0x2110, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK, 0x20a0, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK, 0x2028, CMU_NOCL1A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK, 0x20a4, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK, 0x2008, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK, 0x200c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK, 0x201c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1, 0x2068, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2, 0x206c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3, 0x2070, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW, 0x2064, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK, 0x2038, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK, 0x2034, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK, 0x2040, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK, 0x203c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK, 0x2030, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK, 0x202c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK, 0x2000, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, 0x2004, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK, 0x2010, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK, 0x2048, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK, 0x2044, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK, 0x2020, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, 0x204c, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, 0x2050, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, 0x2054, CMU_NOCL1A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, 0x201c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, 0x209c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, 0x20a0, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, 0x208c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, 0x2090, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, 0x2048, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, 0x2054, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK, 0x2064, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK, 0x2070, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK, 0x2074, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, 0x2098, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B, 0x20a4, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, 0x20a8, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK, 0x204c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK, 0x2084, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK, 0x2088, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK, 0x207c, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK, 0x2080, CMU_NOCL1B), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, 0x2094, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK, 0x2000, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, 0x2004, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK, 0x2008, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK, 0x2038, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK, 0x200c, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK, 0x203c, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK, 0x2010, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, 0x2040, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK, 0x2014, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, 0x2044, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK, 0x2024, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK, 0x2020, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, 0x2034, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK, 0x2018, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, 0x2028, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, 0x202c, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, 0x2030, CMU_NOCL1B), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK, 0x2040, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK, 0x2140, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK, 0x2134, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK, 0x2138, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK, 0x20a4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK, 0x20c0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK, 0x208c, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, 0x209c, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK, 0x2094, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, 0x20a0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK, 0x20b0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, 0x20bc, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK, 0x20cc, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK, 0x20d4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK, 0x2118, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, 0x20b8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK, 0x2090, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK, 0x20ec, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK, 0x2084, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK, 0x2144, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK, 0x2148, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK, 0x213c, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK, 0x2088, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK, 0x20f4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK, 0x20f0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK, 0x20f8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, 0x20ac, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, 0x20b4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, 0x20c8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, 0x20d0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK, 0x2150, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK, 0x20a8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK, 0x20c4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK, 0x20d8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK, 0x20e0, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK, 0x20e4, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK, 0x2098, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, 0x20dc, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK, 0x20e8, CMU_NOCL2A), + SFR(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A, 0x214c, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK, 0x2048, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK, 0x2044, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK, 0x2000, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK, 0x2004, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK, 0x2024, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK, 0x2068, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, 0x2058, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, 0x204c, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK, 0x2060, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK, 0x206c, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK, 0x2054, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK, 0x2070, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, 0x2074, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, 0x2080, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, 0x2078, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK, 0x205c, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK, 0x2064, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK, 0x2050, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK, 0x207c, CMU_NOCL2A), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK, 0x2008, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK, 0x2034, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, 0x203c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, 0x2040, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, 0x2044, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK, 0x20b4, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK, 0x2038, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK, 0x2080, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK, 0x2084, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK, 0x20b8, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK, 0x20bc, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK, 0x2098, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK, 0x209c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM, 0x202c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, 0x2054, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, 0x2060, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, 0x206c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, 0x204c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, 0x2058, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, 0x2064, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, 0x2050, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, 0x205c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, 0x2068, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, 0x2074, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, 0x2078, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, 0x2048, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, 0x2070, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK, 0x207c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK, 0x20c0, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK, 0x20a8, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK, 0x20ac, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK, 0x20c4, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK, 0x20a0, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK, 0x20a4, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK, 0x2088, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK, 0x208c, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK, 0x2090, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK, 0x2094, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM, 0x2030, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK, 0x2014, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK, 0x2028, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK, 0x2024, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK, 0x2020, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK, 0x2018, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK, 0x2000, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK, 0x200c, CMU_PDP), + SFR(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK, 0x2010, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK, 0x20b0, CMU_PDP), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 0x20b0, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 0x20e8, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 0x2048, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, 0x20bc, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, 0x2050, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, 0x20b8, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, 0x20d0, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, 0x20d4, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, 0x20d8, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK, 0x20b4, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, 0x20c8, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, 0x20c0, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, 0x20a8, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, 0x20cc, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, 0x20dc, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, 0x20e0, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, 0x20e4, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, 0x20c4, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, 0x20ac, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK, 0x2068, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK, 0x206c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK, 0x2070, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK, 0x2074, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK, 0x2078, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK, 0x207c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK, 0x2080, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK, 0x2084, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK, 0x2088, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK, 0x208c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK, 0x2090, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK, 0x2094, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK, 0x2098, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK, 0x209c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK, 0x20a0, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK, 0x20a4, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK, 0x2008, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK, 0x2004, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK, 0x2010, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK, 0x200c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK, 0x2018, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK, 0x2014, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK, 0x2020, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK, 0x201c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK, 0x2028, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK, 0x2024, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK, 0x2030, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK, 0x202c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK, 0x2038, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK, 0x2034, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK, 0x2040, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK, 0x203c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK, 0x2058, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK, 0x205c, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, 0x2060, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, 0x2064, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, 0x2054, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK, 0x2044, CMU_PERIC0), + SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK, 0x204c, CMU_PERIC0), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 0x2078, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 0x209c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 0x2010, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, 0x2080, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, 0x2020, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, 0x208c, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, 0x2090, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, 0x2018, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK, 0x207c, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, 0x2084, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, 0x2070, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, 0x2098, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, 0x2088, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, 0x2074, CMU_PERIC1), + SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, 0x2094, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK, 0x2030, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK, 0x2034, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK, 0x2068, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK, 0x206c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, 0x2038, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, 0x203c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, 0x2040, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, 0x2044, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK, 0x2048, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK, 0x204c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK, 0x2050, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK, 0x2054, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK, 0x2008, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK, 0x2004, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0, 0x2014, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, 0x202c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK, 0x200c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK, 0x201c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK, 0x2058, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK, 0x205c, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK, 0x2060, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK, 0x2064, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK, 0x2024, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, 0x2028, CMU_PERIC1), + SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, 0x2008, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, 0x2020, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, 0x2018, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, 0x2014, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, 0x201c, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, 0x2024, CMU_S2D), + SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, 0x200c, CMU_S2D), + SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, 0x2000, CMU_S2D), + SFR(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK, 0x2004, CMU_S2D), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM, 0x2024, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, 0x2028, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, 0x2034, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, 0x20c8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, 0x203c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, 0x2044, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, 0x2048, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, 0x2058, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, 0x205c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, 0x2060, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, 0x2064, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, 0x210c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, 0x2114, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, 0x2134, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, 0x2020, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK, 0x20c0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK, 0x20c4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, 0x2040, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, 0x2110, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, 0x2118, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK, 0x2138, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, 0x2030, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK, 0x204c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK, 0x2050, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK, 0x206c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK, 0x2068, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK, 0x2070, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK, 0x2074, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1, 0x211c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2, 0x2120, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1, 0x2124, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2, 0x2128, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK, 0x213c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK, 0x2078, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK, 0x207c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK, 0x2080, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK, 0x2084, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK, 0x2088, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK, 0x208c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK, 0x2090, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK, 0x2094, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, 0x2140, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, 0x2144, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK, 0x209c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK, 0x2098, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK, 0x20a0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK, 0x20a4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK, 0x20a8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK, 0x20ac, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK, 0x20b0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK, 0x20b4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK, 0x20b8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK, 0x20bc, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK, 0x20cc, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK, 0x20d0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK, 0x20d4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK, 0x20d8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK, 0x20dc, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK, 0x20e0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK, 0x20e4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK, 0x20e8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK, 0x2054, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1, 0x212c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2, 0x2130, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK, 0x20ec, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK, 0x20f0, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK, 0x20f4, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK, 0x20f8, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK, 0x20fc, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK, 0x2100, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK, 0x2104, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK, 0x2108, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK, 0x202c, CMU_TNR), + SFR(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, 0x2038, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK, 0x2018, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK, 0x201c, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK, 0x200c, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK, 0x2010, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK, 0x2004, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK, 0x2008, CMU_TNR), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK, 0x2024, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK, 0x208c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK, 0x2090, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK, 0x207c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK, 0x2058, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK, 0x2060, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK, 0x20a8, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1, 0x20a0, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK, 0x2080, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK, 0x2084, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK, 0x209c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK, 0x2098, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK, 0x205c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2, 0x20a4, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM, 0x2050, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK, 0x2038, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, 0x2070, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, 0x2078, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM, 0x2044, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK, 0x2028, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK, 0x2030, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK, 0x2094, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK, 0x202c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS, 0x204c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2064, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2068, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM, 0x2048, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK, 0x2054, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, 0x206c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, 0x2074, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK, 0x2018, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK, 0x203c, CMU_TPU), + SFR(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK, 0x2088, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN, 0x2000, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN, 0x2034, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK, 0x201c, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK, 0x2020, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK, 0x2008, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK, 0x2014, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK, 0x2010, CMU_TPU), + SFR(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK, 0x200c, CMU_TPU), + SFR(CLK_CON_DIV_CLKCMU_OTP, 0x18d8, CMU_TOP), + SFR(CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, 0x188c, CMU_TOP), + SFR(CLK_CON_DIV_DIV_CLK_MIF_NOCD, 0x1800, CMU_MIF), + SFR(CLK_CON_DIV_CLK_MIF_NOCD_S2D, 0x1800, CMU_S2D), + SFR(QCH_CON_AOC_CMU_AOC_QCH, 0x3044, CMU_AOC), + SFR(QCH_CON_AOC_SYSCTRL_APB_QCH, 0x3048, CMU_AOC), + SFR(QCH_CON_BAAW_AOC_QCH, 0x304c, CMU_AOC), + SFR(QCH_CON_D_TZPC_AOC_QCH, 0x3050, CMU_AOC), + SFR(QCH_CON_GPC_AOC_QCH, 0x3054, CMU_AOC), + SFR(QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH, 0x3058, CMU_AOC), + SFR(QCH_CON_LH_ATB_SI_LT_AOC_QCH, 0x3060, CMU_AOC), + SFR(QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH, 0x305c, CMU_AOC), + SFR(QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH, 0x3064, CMU_AOC), + SFR(QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH, 0x306c, CMU_AOC), + SFR(QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH, 0x3070, CMU_AOC), + SFR(QCH_CON_LH_AXI_MI_P_AOC_CU_QCH, 0x3074, CMU_AOC), + SFR(QCH_CON_LH_AXI_SI_D_AOC_QCH, 0x3078, CMU_AOC), + SFR(QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH, 0x3080, CMU_AOC), + SFR(QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH, 0x3084, CMU_AOC), + SFR(QCH_CON_LH_AXI_SI_P_AOC_CU_QCH, 0x3088, CMU_AOC), + SFR(QCH_CON_PPMU_AOC_QCH, 0x308c, CMU_AOC), + SFR(QCH_CON_PPMU_USB_QCH, 0x3090, CMU_AOC), + SFR(QCH_CON_SLH_AXI_MI_LG_AOC_QCH, 0x3094, CMU_AOC), + SFR(QCH_CON_SLH_AXI_MI_P_AOC_QCH, 0x3098, CMU_AOC), + SFR(QCH_CON_SLH_AXI_SI_LP0_AOC_QCH, 0x309c, CMU_AOC), + SFR(QCH_CON_SLH_AXI_SI_LP1_AOC_QCH, 0x30a0, CMU_AOC), + SFR(QCH_CON_SSMT_AOC_QCH, 0x30a4, CMU_AOC), + SFR(QCH_CON_SYSMMU_AOC_QCH_S1, 0x30a8, CMU_AOC), + SFR(QCH_CON_SYSMMU_AOC_QCH_S2, 0x30ac, CMU_AOC), + SFR(QCH_CON_SYSREG_AOC_QCH, 0x30b0, CMU_AOC), + SFR(QCH_CON_UASC_AOC_QCH, 0x30b4, CMU_AOC), + SFR(QCH_CON_APBIF_GPIO_ALIVE_QCH, 0x303c, CMU_APM), + SFR(QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH, 0x3040, CMU_APM), + SFR(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH, 0x3048, CMU_APM), + SFR(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH, 0x3044, CMU_APM), + SFR(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH, 0x304c, CMU_APM), + SFR(QCH_CON_APBIF_PMU_ALIVE_QCH, 0x3050, CMU_APM), + SFR(QCH_CON_APBIF_RTC_QCH, 0x3054, CMU_APM), + SFR(QCH_CON_APBIF_TRTC_QCH, 0x3058, CMU_APM), + SFR(QCH_CON_APM_CMU_APM_QCH, 0x305c, CMU_APM), + SFR(QCH_CON_APM_I3C_PMIC_QCH_P, 0x3060, CMU_APM), + SFR(DMYQCH_CON_APM_I3C_PMIC_QCH_S, 0x3000, CMU_APM), + SFR(QCH_CON_APM_USI0_UART_QCH, 0x3064, CMU_APM), + SFR(QCH_CON_APM_USI0_USI_QCH, 0x3068, CMU_APM), + SFR(QCH_CON_APM_USI1_UART_QCH, 0x306c, CMU_APM), + SFR(QCH_CON_D_TZPC_APM_QCH, 0x3070, CMU_APM), + SFR(QCH_CON_GPC_APM_QCH, 0x3074, CMU_APM), + SFR(QCH_CON_GREBEINTEGRATION_QCH_GREBE, 0x307c, CMU_APM), + SFR(QCH_CON_GREBEINTEGRATION_QCH_DBG, 0x3078, CMU_APM), + SFR(QCH_CON_INTMEM_QCH, 0x3080, CMU_APM), + SFR(QCH_CON_LH_AXI_MI_IG_SWD_QCH, 0x3084, CMU_APM), + SFR(QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH, 0x3088, CMU_APM), + SFR(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH, 0x308c, CMU_APM), + SFR(QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH, 0x3090, CMU_APM), + SFR(QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH, 0x3094, CMU_APM), + SFR(QCH_CON_LH_AXI_SI_D_APM_QCH, 0x3098, CMU_APM), + SFR(QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH, 0x309c, CMU_APM), + SFR(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH, 0x30a0, CMU_APM), + SFR(QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH, 0x30a4, CMU_APM), + SFR(QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH, 0x30a8, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_AOC_QCH, 0x30ac, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_AP_QCH, 0x30b0, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_AUR_QCH, 0x30b4, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_GSA_QCH, 0x30b8, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_SWD_QCH, 0x30bc, CMU_APM), + SFR(QCH_CON_MAILBOX_APM_TPU_QCH, 0x30c0, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AOCA32_QCH, 0x30c4, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AOCF1_QCH, 0x30c8, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AOCP6_QCH, 0x30cc, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AUR0_QCH, 0x30d0, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AUR1_QCH, 0x30d4, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AUR2_QCH, 0x30d8, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_AUR3_QCH, 0x30dc, CMU_APM), + SFR(QCH_CON_MAILBOX_AP_DBGCORE_QCH, 0x30e0, CMU_APM), + SFR(QCH_CON_PMU_INTR_GEN_QCH, 0x30e4, CMU_APM), + SFR(QCH_CON_ROM_CRC32_HOST_QCH, 0x30e8, CMU_APM), + SFR(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH, 0x30f0, CMU_APM), + SFR(QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH, 0x30ec, CMU_APM), + SFR(QCH_CON_SLH_AXI_MI_LP0_AOC_QCH, 0x30f4, CMU_APM), + SFR(QCH_CON_SLH_AXI_MI_P_ALIVE_QCH, 0x30f8, CMU_APM), + SFR(QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH, 0x30fc, CMU_APM), + SFR(QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH, 0x3100, CMU_APM), + SFR(QCH_CON_SSMT_D_APM_QCH, 0x3104, CMU_APM), + SFR(QCH_CON_SSMT_LG_DBGCORE_QCH, 0x3108, CMU_APM), + SFR(QCH_CON_SS_DBGCORE_QCH_GREBE, 0x3110, CMU_APM), + SFR(QCH_CON_SS_DBGCORE_QCH_DBG, 0x310c, CMU_APM), + SFR(QCH_CON_SYSMMU_D_APM_QCH, 0x3114, CMU_APM), + SFR(QCH_CON_SYSREG_APM_QCH, 0x3118, CMU_APM), + SFR(QCH_CON_UASC_APM_QCH, 0x311c, CMU_APM), + SFR(QCH_CON_UASC_DBGCORE_QCH, 0x3120, CMU_APM), + SFR(QCH_CON_UASC_IG_SWD_QCH, 0x3124, CMU_APM), + SFR(QCH_CON_UASC_LP0_AOC_QCH, 0x3128, CMU_APM), + SFR(QCH_CON_UASC_P_ALIVE_QCH, 0x312c, CMU_APM), + SFR(QCH_CON_WDT_APM_QCH, 0x3130, CMU_APM), + SFR(QCH_CON_ADD_APBIF_AUR_QCH, 0x3028, CMU_AUR), + SFR(DMYQCH_CON_ADD_AUR_QCH, 0x3000, CMU_AUR), + SFR(DMYQCH_CON_AUR_QCH, 0x3004, CMU_AUR), + SFR(QCH_CON_AUR_CMU_AUR_QCH, 0x302c, CMU_AUR), + SFR(QCH_CON_BAAW_AUR_QCH, 0x3030, CMU_AUR), + SFR(QCH_CON_D_TZPC_AUR_QCH, 0x3034, CMU_AUR), + SFR(QCH_CON_GPC_AUR_QCH, 0x3038, CMU_AUR), + SFR(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH, 0x303c, CMU_AUR), + SFR(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH, 0x3044, CMU_AUR), + SFR(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH, 0x3040, CMU_AUR), + SFR(QCH_CON_LH_AXI_MI_P_AUR_CU_QCH, 0x3048, CMU_AUR), + SFR(QCH_CON_LH_AXI_SI_D0_AUR_QCH, 0x304c, CMU_AUR), + SFR(QCH_CON_LH_AXI_SI_D1_AUR_QCH, 0x3050, CMU_AUR), + SFR(QCH_CON_LH_AXI_SI_P_AUR_CU_QCH, 0x3054, CMU_AUR), + SFR(QCH_CON_PPMU_D0_AUR_QCH, 0x3058, CMU_AUR), + SFR(QCH_CON_PPMU_D1_AUR_QCH, 0x305c, CMU_AUR), + SFR(QCH_CON_SLH_AXI_MI_P_AUR_QCH, 0x3064, CMU_AUR), + SFR(QCH_CON_SSMT_D0_AUR_QCH, 0x3068, CMU_AUR), + SFR(QCH_CON_SSMT_D1_AUR_QCH, 0x306c, CMU_AUR), + SFR(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1, 0x3070, CMU_AUR), + SFR(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2, 0x3074, CMU_AUR), + SFR(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1, 0x3078, CMU_AUR), + SFR(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2, 0x307c, CMU_AUR), + SFR(QCH_CON_SYSREG_AUR_QCH, 0x3080, CMU_AUR), + SFR(QCH_CON_UASC_AUR_QCH, 0x3084, CMU_AUR), + SFR(DMYQCH_CON_BO_QCH, 0x3000, CMU_BO), + SFR(QCH_CON_BO_CMU_BO_QCH, 0x3014, CMU_BO), + SFR(QCH_CON_D_TZPC_BO_QCH, 0x3018, CMU_BO), + SFR(QCH_CON_GPC_BO_QCH, 0x301c, CMU_BO), + SFR(QCH_CON_LH_AXI_MI_IP_BO_QCH, 0x3020, CMU_BO), + SFR(QCH_CON_LH_AXI_SI_D_BO_QCH, 0x3024, CMU_BO), + SFR(QCH_CON_LH_AXI_SI_IP_BO_QCH, 0x3028, CMU_BO), + SFR(QCH_CON_PPMU_BO_QCH, 0x302c, CMU_BO), + SFR(QCH_CON_SLH_AXI_MI_P_BO_QCH, 0x3030, CMU_BO), + SFR(QCH_CON_SSMT_BO_QCH, 0x3034, CMU_BO), + SFR(QCH_CON_SYSMMU_BO_QCH_S1, 0x3038, CMU_BO), + SFR(QCH_CON_SYSMMU_BO_QCH_S2, 0x303c, CMU_BO), + SFR(QCH_CON_SYSREG_BO_QCH, 0x3040, CMU_BO), + SFR(QCH_CON_UASC_BO_QCH, 0x3044, CMU_BO), + SFR(DMYQCH_CON_CMU_TOP_CMUREF_QCH, 0x3000, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, 0x3004, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, 0x3008, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, 0x300c, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, 0x3010, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, 0x3014, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, 0x3018, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, 0x301c, CMU_TOP), + SFR(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, 0x3020, CMU_TOP), + SFR(DMYQCH_CON_OTP_QCH, 0x3024, CMU_TOP), + SFR(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH, 0x3000, CMU_CPUCL0), + SFR(QCH_CON_BPS_CPUCL0_QCH, 0x312c, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_SCLK, 0x3144, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_ATCLK, 0x3130, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_GIC, 0x3138, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_PCLK, 0x313c, CMU_CPUCL0), + SFR(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, 0x3004, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_DBG_PD, 0x3134, CMU_CPUCL0), + SFR(QCH_CON_CLUSTER0_QCH_PDBGCLK, 0x3140, CMU_CPUCL0), + SFR(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, 0x3008, CMU_CPUCL0), + SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3148, CMU_CPUCL0), + SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x314c, CMU_CPUCL0), + SFR(QCH_CON_CSSYS_QCH, 0x3150, CMU_CPUCL0), + SFR(QCH_CON_D_TZPC_CPUCL0_QCH, 0x3154, CMU_CPUCL0), + SFR(QCH_CON_GPC_CPUCL0_QCH, 0x3158, CMU_CPUCL0), + SFR(QCH_CON_HPM_APBIF_CPUCL0_QCH, 0x315c, CMU_CPUCL0), + SFR(QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH, 0x3160, CMU_CPUCL0), + SFR(QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH, 0x3164, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH, 0x3168, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH, 0x3170, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH, 0x316c, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH, 0x3178, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH, 0x3174, CMU_CPUCL0), + SFR(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH, 0x317c, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH, 0x3180, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH, 0x3184, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH, 0x3188, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH, 0x318c, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH, 0x3190, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH, 0x3194, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH, 0x3198, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH, 0x319c, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH, 0x31a4, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH, 0x31a0, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH, 0x31ac, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH, 0x31a8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_AOC_QCH, 0x31b4, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH, 0x31b0, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH, 0x31bc, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH, 0x31b8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH, 0x31cc, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH, 0x31c8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_T_BDU_QCH, 0x31d4, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_T_BDU_CU_QCH, 0x31d0, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_T_SLC_QCH, 0x31dc, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_MI_T_SLC_CU_QCH, 0x31d8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH, 0x31e0, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH, 0x31e4, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH, 0x31e8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH, 0x31ec, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH, 0x31f0, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH, 0x31f4, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH, 0x31f8, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH, 0x31fc, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH, 0x3200, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH, 0x3204, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH, 0x3208, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH, 0x320c, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH, 0x3214, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_T_BDU_CU_QCH, 0x3218, CMU_CPUCL0), + SFR(QCH_CON_LH_ATB_SI_T_SLC_CU_QCH, 0x321c, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH, 0x3220, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_IG_CSSYS_QCH, 0x3224, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH, 0x3228, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_IG_HSI0_QCH, 0x322c, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_IG_STM_QCH, 0x3230, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH, 0x3234, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH, 0x3238, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH, 0x323c, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH, 0x3240, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_IG_CSSYS_QCH, 0x3244, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH, 0x3248, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_IG_HSI0_QCH, 0x324c, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_IG_STM_QCH, 0x3250, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH, 0x3254, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH, 0x3258, CMU_CPUCL0), + SFR(QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH, 0x325c, CMU_CPUCL0), + SFR(QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH, 0x3260, CMU_CPUCL0), + SFR(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH, 0x3264, CMU_CPUCL0), + SFR(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH, 0x3268, CMU_CPUCL0), + SFR(QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH, 0x326c, CMU_CPUCL0), + SFR(QCH_CON_SSMT_CPUCL0_QCH, 0x3270, CMU_CPUCL0), + SFR(QCH_CON_SYSMMU_S2_CPUCL0_QCH, 0x3274, CMU_CPUCL0), + SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x3278, CMU_CPUCL0), + SFR(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, 0x3000, CMU_CPUCL1), + SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3010, CMU_CPUCL1), + SFR(DMYQCH_CON_CPUCL1_QCH_MID, 0x3004, CMU_CPUCL1), + SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3014, CMU_CPUCL1), + SFR(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH, 0x3000, CMU_CPUCL2), + SFR(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH, 0x3010, CMU_CPUCL2), + SFR(DMYQCH_CON_CPUCL2_QCH_BIG, 0x3004, CMU_CPUCL2), + SFR(QCH_CON_CPUCL2_CMU_CPUCL2_QCH, 0x3014, CMU_CPUCL2), + SFR(QCH_CON_CSISX8_QCH_C2_CSIS, 0x3050, CMU_CSIS), + SFR(QCH_CON_CSISX8_QCH_CSIS_DMA, 0x3054, CMU_CSIS), + SFR(QCH_CON_CSISX8_QCH_EBUF, 0x3058, CMU_CSIS), + SFR(QCH_CON_CSIS_CMU_CSIS_QCH, 0x305c, CMU_CSIS), + SFR(QCH_CON_D_TZPC_CSIS_QCH, 0x3060, CMU_CSIS), + SFR(QCH_CON_GPC_CSIS_QCH, 0x3064, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH, 0x3068, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH, 0x306c, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH, 0x3070, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH, 0x3074, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH, 0x3078, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH, 0x307c, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH, 0x3080, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH, 0x3084, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH, 0x3088, CMU_CSIS), + SFR(QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH, 0x308c, CMU_CSIS), + SFR(QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH, 0x3090, CMU_CSIS), + SFR(QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH, 0x3094, CMU_CSIS), + SFR(QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH, 0x3098, CMU_CSIS), + SFR(QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH, 0x309c, CMU_CSIS), + SFR(QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH, 0x30a0, CMU_CSIS), + SFR(QCH_CON_LH_AXI_SI_D0_CSIS_QCH, 0x30a4, CMU_CSIS), + SFR(QCH_CON_LH_AXI_SI_D1_CSIS_QCH, 0x30a8, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0, 0x30b0, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1, 0x30b4, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2, 0x30b8, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3, 0x30bc, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4, 0x30c0, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5, 0x30c4, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6, 0x30c8, CMU_CSIS), + SFR(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7, 0x30cc, CMU_CSIS), + SFR(QCH_CON_PPMU_D0_QCH, 0x30d0, CMU_CSIS), + SFR(QCH_CON_PPMU_D1_QCH, 0x30d4, CMU_CSIS), + SFR(QCH_CON_QE_CSIS_DMA0_QCH, 0x30d8, CMU_CSIS), + SFR(QCH_CON_QE_CSIS_DMA1_QCH, 0x30dc, CMU_CSIS), + SFR(QCH_CON_QE_CSIS_DMA2_QCH, 0x30e0, CMU_CSIS), + SFR(QCH_CON_QE_CSIS_DMA3_QCH, 0x30e4, CMU_CSIS), + SFR(QCH_CON_QE_STRP0_QCH, 0x30e8, CMU_CSIS), + SFR(QCH_CON_QE_STRP1_QCH, 0x30ec, CMU_CSIS), + SFR(QCH_CON_QE_STRP2_QCH, 0x30f0, CMU_CSIS), + SFR(QCH_CON_QE_ZSL0_QCH, 0x30f4, CMU_CSIS), + SFR(QCH_CON_QE_ZSL1_QCH, 0x30f8, CMU_CSIS), + SFR(QCH_CON_QE_ZSL2_QCH, 0x30fc, CMU_CSIS), + SFR(QCH_CON_SLH_AXI_MI_P_CSIS_QCH, 0x3100, CMU_CSIS), + SFR(QCH_CON_SSMT_D0_QCH, 0x3108, CMU_CSIS), + SFR(QCH_CON_SSMT_D1_QCH, 0x310c, CMU_CSIS), + SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S1, 0x3110, CMU_CSIS), + SFR(QCH_CON_SYSMMU_D0_CSIS_QCH_S2, 0x3114, CMU_CSIS), + SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S1, 0x3118, CMU_CSIS), + SFR(QCH_CON_SYSMMU_D1_CSIS_QCH_S2, 0x311c, CMU_CSIS), + SFR(QCH_CON_SYSREG_CSIS_QCH, 0x3120, CMU_CSIS), + SFR(QCH_CON_DISP_CMU_DISP_QCH, 0x3008, CMU_DISP), + SFR(QCH_CON_DPUB_QCH, 0x300c, CMU_DISP), + SFR(QCH_CON_D_TZPC_DISP_QCH, 0x3010, CMU_DISP), + SFR(QCH_CON_GPC_DISP_QCH, 0x3014, CMU_DISP), + SFR(QCH_CON_SLH_AXI_MI_P_DISP_QCH, 0x301c, CMU_DISP), + SFR(QCH_CON_SYSREG_DISP_QCH, 0x3020, CMU_DISP), + SFR(QCH_CON_DNS_QCH_00, 0x3048, CMU_DNS), + SFR(QCH_CON_DNS_QCH_01, 0x304c, CMU_DNS), + SFR(QCH_CON_DNS_CMU_DNS_QCH, 0x3044, CMU_DNS), + SFR(QCH_CON_D_TZPC_DNS_QCH, 0x3050, CMU_DNS), + SFR(QCH_CON_GPC_DNS_QCH, 0x3054, CMU_DNS), + SFR(QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH, 0x3058, CMU_DNS), + SFR(QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH, 0x305c, CMU_DNS), + SFR(QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH, 0x3060, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH, 0x3064, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH, 0x3068, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH, 0x306c, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH, 0x3070, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH, 0x3074, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH, 0x3078, CMU_DNS), + SFR(QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH, 0x307c, CMU_DNS), + SFR(QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH, 0x3080, CMU_DNS), + SFR(QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH, 0x3084, CMU_DNS), + SFR(QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH, 0x3088, CMU_DNS), + SFR(QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH, 0x308c, CMU_DNS), + SFR(QCH_CON_LH_AXI_SI_D_DNS_QCH, 0x3090, CMU_DNS), + SFR(QCH_CON_PPMU_D0_DNS_QCH, 0x3098, CMU_DNS), + SFR(QCH_CON_PPMU_D1_DNS_QCH, 0x309c, CMU_DNS), + SFR(QCH_CON_QE_D0_DNS_QCH, 0x30a0, CMU_DNS), + SFR(QCH_CON_QE_D1_DNS_QCH, 0x30a4, CMU_DNS), + SFR(QCH_CON_SLH_AXI_MI_P_DNS_QCH, 0x30a8, CMU_DNS), + SFR(QCH_CON_SSMT_D0_DNS_QCH, 0x30ac, CMU_DNS), + SFR(QCH_CON_SSMT_D1_DNS_QCH, 0x30b0, CMU_DNS), + SFR(QCH_CON_SYSMMU_DNS_QCH_S1, 0x30b4, CMU_DNS), + SFR(QCH_CON_SYSMMU_DNS_QCH_S2, 0x30b8, CMU_DNS), + SFR(QCH_CON_SYSREG_DNS_QCH, 0x30bc, CMU_DNS), + SFR(QCH_CON_DPUF_QCH_DPU_DMA, 0x3014, CMU_DPU), + SFR(QCH_CON_DPUF_QCH_DPU_DPP, 0x3018, CMU_DPU), + SFR(QCH_CON_DPU_CMU_DPU_QCH, 0x301c, CMU_DPU), + SFR(QCH_CON_D_TZPC_DPU_QCH, 0x3020, CMU_DPU), + SFR(QCH_CON_GPC_DPU_QCH, 0x3024, CMU_DPU), + SFR(QCH_CON_LH_AXI_SI_D0_DPU_QCH, 0x3028, CMU_DPU), + SFR(QCH_CON_LH_AXI_SI_D1_DPU_QCH, 0x302c, CMU_DPU), + SFR(QCH_CON_LH_AXI_SI_D2_DPU_QCH, 0x3030, CMU_DPU), + SFR(QCH_CON_PPMU_DPUD0_QCH, 0x3038, CMU_DPU), + SFR(QCH_CON_PPMU_DPUD1_QCH, 0x303c, CMU_DPU), + SFR(QCH_CON_PPMU_DPUD2_QCH, 0x3040, CMU_DPU), + SFR(QCH_CON_SLH_AXI_MI_P_DPU_QCH, 0x3044, CMU_DPU), + SFR(QCH_CON_SSMT_DPU0_QCH, 0x3048, CMU_DPU), + SFR(QCH_CON_SSMT_DPU1_QCH, 0x304c, CMU_DPU), + SFR(QCH_CON_SSMT_DPU2_QCH, 0x3050, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD0_QCH_S1, 0x3054, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD0_QCH_S2, 0x3058, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD1_QCH_S1, 0x305c, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD1_QCH_S2, 0x3060, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD2_QCH_S1, 0x3064, CMU_DPU), + SFR(QCH_CON_SYSMMU_DPUD2_QCH_S2, 0x3068, CMU_DPU), + SFR(QCH_CON_SYSREG_DPU_QCH, 0x306c, CMU_DPU), + SFR(QCH_CON_D_TZPC_EH_QCH, 0x3018, CMU_EH), + SFR(QCH_CON_EH_QCH, 0x3020, CMU_EH), + SFR(QCH_CON_EH_CMU_EH_QCH, 0x301c, CMU_EH), + SFR(QCH_CON_GPC_EH_QCH, 0x3024, CMU_EH), + SFR(QCH_CON_LH_ACEL_SI_D_EH_QCH, 0x3028, CMU_EH), + SFR(QCH_CON_LH_AXI_MI_IP_EH_QCH, 0x302c, CMU_EH), + SFR(QCH_CON_LH_AXI_MI_P_EH_CU_QCH, 0x3030, CMU_EH), + SFR(QCH_CON_LH_AXI_SI_IP_EH_QCH, 0x3034, CMU_EH), + SFR(QCH_CON_LH_AXI_SI_P_EH_CU_QCH, 0x3038, CMU_EH), + SFR(QCH_CON_PPMU_EH_QCH, 0x303c, CMU_EH), + SFR(QCH_CON_QE_EH_QCH, 0x3040, CMU_EH), + SFR(QCH_CON_SLH_AXI_MI_P_EH_QCH, 0x3044, CMU_EH), + SFR(QCH_CON_SSMT_EH_QCH, 0x3048, CMU_EH), + SFR(QCH_CON_SYSMMU_EH_QCH, 0x304c, CMU_EH), + SFR(QCH_CON_SYSREG_EH_QCH, 0x3050, CMU_EH), + SFR(QCH_CON_UASC_EH_QCH, 0x3054, CMU_EH), + SFR(QCH_CON_D_TZPC_G2D_QCH, 0x3014, CMU_G2D), + SFR(QCH_CON_G2D_QCH, 0x301c, CMU_G2D), + SFR(QCH_CON_G2D_CMU_G2D_QCH, 0x3018, CMU_G2D), + SFR(QCH_CON_GPC_G2D_QCH, 0x3020, CMU_G2D), + SFR(QCH_CON_JPEG_QCH, 0x3024, CMU_G2D), + SFR(QCH_CON_LH_ACEL_SI_D2_G2D_QCH, 0x3028, CMU_G2D), + SFR(QCH_CON_LH_AXI_SI_D0_G2D_QCH, 0x302c, CMU_G2D), + SFR(QCH_CON_LH_AXI_SI_D1_G2D_QCH, 0x3030, CMU_G2D), + SFR(QCH_CON_PPMU_D0_G2D_QCH, 0x3038, CMU_G2D), + SFR(QCH_CON_PPMU_D1_G2D_QCH, 0x303c, CMU_G2D), + SFR(QCH_CON_PPMU_D2_G2D_QCH, 0x3040, CMU_G2D), + SFR(QCH_CON_SLH_AXI_MI_P_G2D_QCH, 0x3044, CMU_G2D), + SFR(QCH_CON_SSMT_D0_G2D_QCH, 0x3048, CMU_G2D), + SFR(QCH_CON_SSMT_D1_G2D_QCH, 0x304c, CMU_G2D), + SFR(QCH_CON_SSMT_D2_G2D_QCH, 0x3050, CMU_G2D), + SFR(QCH_CON_SYSMMU_D0_G2D_QCH_0, 0x3054, CMU_G2D), + SFR(QCH_CON_SYSMMU_D0_G2D_QCH_1, 0x3058, CMU_G2D), + SFR(QCH_CON_SYSMMU_D1_G2D_QCH_0, 0x305c, CMU_G2D), + SFR(QCH_CON_SYSMMU_D1_G2D_QCH_1, 0x3060, CMU_G2D), + SFR(QCH_CON_SYSMMU_D2_G2D_QCH_0, 0x3064, CMU_G2D), + SFR(QCH_CON_SYSMMU_D2_G2D_QCH_1, 0x3068, CMU_G2D), + SFR(QCH_CON_SYSREG_G2D_QCH, 0x306c, CMU_G2D), + SFR(QCH_CON_D_TZPC_G3AA_QCH, 0x3024, CMU_G3AA), + SFR(DMYQCH_CON_G3AA_QCH, 0x3000, CMU_G3AA), + SFR(QCH_CON_G3AA_CMU_G3AA_QCH, 0x3028, CMU_G3AA), + SFR(QCH_CON_GPC_G3AA_QCH, 0x302c, CMU_G3AA), + SFR(QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH, 0x3030, CMU_G3AA), + SFR(QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH, 0x3034, CMU_G3AA), + SFR(QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH, 0x3038, CMU_G3AA), + SFR(QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH, 0x303c, CMU_G3AA), + SFR(QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH, 0x3040, CMU_G3AA), + SFR(QCH_CON_LH_AXI_SI_D_G3AA_QCH, 0x3044, CMU_G3AA), + SFR(QCH_CON_PPMU_G3AA_QCH, 0x304c, CMU_G3AA), + SFR(QCH_CON_SLH_AXI_MI_P_G3AA_QCH, 0x3050, CMU_G3AA), + SFR(QCH_CON_SSMT_G3AA_QCH, 0x3054, CMU_G3AA), + SFR(QCH_CON_SYSMMU_G3AA_QCH_S1, 0x3058, CMU_G3AA), + SFR(QCH_CON_SYSMMU_G3AA_QCH_S2, 0x305c, CMU_G3AA), + SFR(QCH_CON_SYSREG_G3AA_QCH, 0x3060, CMU_G3AA), + SFR(QCH_CON_ADD_APBIF_G3D_QCH, 0x302c, CMU_G3D), + SFR(DMYQCH_CON_ADD_G3D_QCH, 0x3000, CMU_G3D), + SFR(QCH_CON_ADM_AHB_G_GPU_QCH, 0x3030, CMU_G3D), + SFR(QCH_CON_ASB_G3D_QCH_LH_D0_G3D, 0x3034, CMU_G3D), + SFR(QCH_CON_ASB_G3D_QCH_LH_D1_G3D, 0x3038, CMU_G3D), + SFR(QCH_CON_ASB_G3D_QCH_LH_D2_G3D, 0x303c, CMU_G3D), + SFR(QCH_CON_ASB_G3D_QCH_LH_D3_G3D, 0x3040, CMU_G3D), + SFR(QCH_CON_BUSIF_HPMG3D_QCH, 0x3044, CMU_G3D), + SFR(QCH_CON_D_TZPC_G3D_QCH, 0x3048, CMU_G3D), + SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x304c, CMU_G3D), + SFR(QCH_CON_GPC_G3D_QCH, 0x3050, CMU_G3D), + SFR(QCH_CON_GPU_QCH, 0x3054, CMU_G3D), + SFR(QCH_CON_LH_AXI_MI_IP_G3D_QCH, 0x3058, CMU_G3D), + SFR(QCH_CON_LH_AXI_MI_P_G3D_CU_QCH, 0x305c, CMU_G3D), + SFR(QCH_CON_LH_AXI_SI_IP_G3D_QCH, 0x3060, CMU_G3D), + SFR(QCH_CON_LH_AXI_SI_P_G3D_CU_QCH, 0x3064, CMU_G3D), + SFR(QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH, 0x3068, CMU_G3D), + SFR(QCH_CON_SLH_AXI_MI_P_G3D_QCH, 0x306c, CMU_G3D), + SFR(QCH_CON_SYSREG_G3D_QCH, 0x3070, CMU_G3D), + SFR(QCH_CON_UASC_G3D_QCH, 0x3074, CMU_G3D), + SFR(QCH_CON_D_TZPC_GDC_QCH, 0x303c, CMU_GDC), + SFR(QCH_CON_GDC0_QCH_CLK, 0x3044, CMU_GDC), + SFR(QCH_CON_GDC0_QCH_C2CLK, 0x3040, CMU_GDC), + SFR(QCH_CON_GDC1_QCH_CLK, 0x304c, CMU_GDC), + SFR(QCH_CON_GDC1_QCH_C2CLK, 0x3048, CMU_GDC), + SFR(QCH_CON_GDC_CMU_GDC_QCH, 0x3050, CMU_GDC), + SFR(QCH_CON_GPC_GDC_QCH, 0x3054, CMU_GDC), + SFR(QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH, 0x3058, CMU_GDC), + SFR(QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH, 0x305c, CMU_GDC), + SFR(QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH, 0x3060, CMU_GDC), + SFR(QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH, 0x3064, CMU_GDC), + SFR(QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH, 0x3068, CMU_GDC), + SFR(QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH, 0x306c, CMU_GDC), + SFR(QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH, 0x3070, CMU_GDC), + SFR(QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH, 0x3074, CMU_GDC), + SFR(QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH, 0x3078, CMU_GDC), + SFR(QCH_CON_LH_AXI_SI_D0_GDC_QCH, 0x307c, CMU_GDC), + SFR(QCH_CON_LH_AXI_SI_D1_GDC_QCH, 0x3080, CMU_GDC), + SFR(QCH_CON_LH_AXI_SI_D2_GDC_QCH, 0x3084, CMU_GDC), + SFR(QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH, 0x3088, CMU_GDC), + SFR(QCH_CON_PPMU_D0_GDC_QCH, 0x3090, CMU_GDC), + SFR(QCH_CON_PPMU_D0_SCSC_QCH, 0x3094, CMU_GDC), + SFR(QCH_CON_PPMU_D1_GDC_QCH, 0x3098, CMU_GDC), + SFR(QCH_CON_PPMU_D1_SCSC_QCH, 0x309c, CMU_GDC), + SFR(QCH_CON_PPMU_D2_GDC_QCH, 0x30a0, CMU_GDC), + SFR(QCH_CON_PPMU_D2_SCSC_QCH, 0x30a4, CMU_GDC), + SFR(QCH_CON_PPMU_D3_GDC_QCH, 0x30a8, CMU_GDC), + SFR(QCH_CON_QE_D0_GDC_QCH, 0x30ac, CMU_GDC), + SFR(QCH_CON_QE_D0_SCSC_QCH, 0x30b0, CMU_GDC), + SFR(QCH_CON_QE_D1_GDC_QCH, 0x30b4, CMU_GDC), + SFR(QCH_CON_QE_D1_SCSC_QCH, 0x30b8, CMU_GDC), + SFR(QCH_CON_QE_D2_GDC_QCH, 0x30bc, CMU_GDC), + SFR(QCH_CON_QE_D2_SCSC_QCH, 0x30c0, CMU_GDC), + SFR(QCH_CON_QE_D3_GDC_QCH, 0x30c4, CMU_GDC), + SFR(QCH_CON_SCSC_QCH_CLK, 0x30cc, CMU_GDC), + SFR(QCH_CON_SCSC_QCH_C2CLK, 0x30c8, CMU_GDC), + SFR(QCH_CON_SLH_AXI_MI_P_GDC_QCH, 0x30d0, CMU_GDC), + SFR(QCH_CON_SSMT_D0_GDC_QCH, 0x30d4, CMU_GDC), + SFR(QCH_CON_SSMT_D0_SCSC_QCH, 0x30d8, CMU_GDC), + SFR(QCH_CON_SSMT_D1_GDC_QCH, 0x30dc, CMU_GDC), + SFR(QCH_CON_SSMT_D1_SCSC_QCH, 0x30e0, CMU_GDC), + SFR(QCH_CON_SSMT_D2_GDC_QCH, 0x30e4, CMU_GDC), + SFR(QCH_CON_SSMT_D2_SCSC_QCH, 0x30e8, CMU_GDC), + SFR(QCH_CON_SSMT_D3_GDC_QCH, 0x30ec, CMU_GDC), + SFR(QCH_CON_SYSMMU_D0_GDC_QCH_S1, 0x30f0, CMU_GDC), + SFR(QCH_CON_SYSMMU_D0_GDC_QCH_S2, 0x30f4, CMU_GDC), + SFR(QCH_CON_SYSMMU_D1_GDC_QCH_S1, 0x30f8, CMU_GDC), + SFR(QCH_CON_SYSMMU_D1_GDC_QCH_S2, 0x30fc, CMU_GDC), + SFR(QCH_CON_SYSMMU_D2_GDC_QCH_S1, 0x3100, CMU_GDC), + SFR(QCH_CON_SYSMMU_D2_GDC_QCH_S2, 0x3104, CMU_GDC), + SFR(QCH_CON_SYSREG_GDC_QCH, 0x3108, CMU_GDC), + SFR(DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH, 0x3000, CMU_GSACORE), + SFR(QCH_CON_BAAW_GSACORE_QCH, 0x304c, CMU_GSACORE), + SFR(DMYQCH_CON_CA32_GSACORE_QCH, 0x3004, CMU_GSACORE), + SFR(QCH_CON_DMA_GSACORE_QCH, 0x3050, CMU_GSACORE), + SFR(QCH_CON_GIC_GSACORE_QCH, 0x3054, CMU_GSACORE), + SFR(QCH_CON_GPIO_GSACORE_QCH, 0x3058, CMU_GSACORE), + SFR(QCH_CON_GSACORE_CMU_GSACORE_QCH, 0x305c, CMU_GSACORE), + SFR(QCH_CON_INTMEM_GSACORE_QCH, 0x3060, CMU_GSACORE), + SFR(QCH_CON_KDN_GSACORE_QCH, 0x3064, CMU_GSACORE), + SFR(QCH_CON_LH_AST_MI_I_CA32_GIC_QCH, 0x3068, CMU_GSACORE), + SFR(QCH_CON_LH_AST_MI_I_GIC_CA32_QCH, 0x306c, CMU_GSACORE), + SFR(QCH_CON_LH_AST_SI_I_CA32_GIC_QCH, 0x3070, CMU_GSACORE), + SFR(QCH_CON_LH_AST_SI_I_GIC_CA32_QCH, 0x3074, CMU_GSACORE), + SFR(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH, 0x3078, CMU_GSACORE), + SFR(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH, 0x3080, CMU_GSACORE), + SFR(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH, 0x307c, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH, 0x3084, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH, 0x3088, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_MI_IP_GME_QCH, 0x308c, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH, 0x3090, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_SI_D_GSA_QCH, 0x3094, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH, 0x3098, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH, 0x309c, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_SI_IP_GME_QCH, 0x30a0, CMU_GSACORE), + SFR(QCH_CON_LH_AXI_SI_IP_GSA_QCH, 0x30a4, CMU_GSACORE), + SFR(QCH_CON_OTP_CON_GSACORE_QCH, 0x30a8, CMU_GSACORE), + SFR(QCH_CON_PPMU_GSACORE_QCH, 0x30ac, CMU_GSACORE), + SFR(DMYQCH_CON_PUF_GSACORE_QCH, 0x3008, CMU_GSACORE), + SFR(QCH_CON_QE_CA32_GSACORE_QCH, 0x30b0, CMU_GSACORE), + SFR(QCH_CON_QE_DMA_GSACORE_QCH, 0x30b4, CMU_GSACORE), + SFR(QCH_CON_QE_SSS_GSACORE_QCH, 0x30b8, CMU_GSACORE), + SFR(QCH_CON_RESETMON_GSACORE_QCH, 0x30bc, CMU_GSACORE), + SFR(QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH, 0x30c0, CMU_GSACORE), + SFR(QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH, 0x30c4, CMU_GSACORE), + SFR(QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH, 0x30c8, CMU_GSACORE), + SFR(QCH_CON_SPI_FPS_GSACORE_QCH, 0x30cc, CMU_GSACORE), + SFR(QCH_CON_SPI_GSC_GSACORE_QCH, 0x30d0, CMU_GSACORE), + SFR(QCH_CON_SSMT_GSACORE_QCH, 0x30d4, CMU_GSACORE), + SFR(QCH_CON_SSS_GSACORE_QCH, 0x30d8, CMU_GSACORE), + SFR(QCH_CON_SYSMMU_GSACORE_QCH_S1, 0x30dc, CMU_GSACORE), + SFR(QCH_CON_SYSMMU_GSACORE_QCH_S2, 0x30e0, CMU_GSACORE), + SFR(QCH_CON_SYSREG_GSACORE_QCH, 0x30e4, CMU_GSACORE), + SFR(QCH_CON_UART_GSACORE_QCH, 0x30e8, CMU_GSACORE), + SFR(QCH_CON_WDT_GSACORE_QCH, 0x30f4, CMU_GSACORE), + SFR(QCH_CON_UDAP_SSS_AHB_ASYNC_QCH, 0x30ec, CMU_GSACORE), + SFR(QCH_CON_UGME_QCH, 0x30f0, CMU_GSACORE), + SFR(QCH_CON_APBIF_GPIO_GSACTRL_QCH, 0x3020, CMU_GSACTRL), + SFR(DMYQCH_CON_DAP_GSACTRL_QCH, 0x3000, CMU_GSACTRL), + SFR(QCH_CON_GPC_GSACTRL_QCH, 0x3024, CMU_GSACTRL), + SFR(QCH_CON_GSACTRL_CMU_GSACTRL_QCH, 0x3028, CMU_GSACTRL), + SFR(QCH_CON_INTMEM_GSACTRL_QCH, 0x302c, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH, 0x3030, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_MI_IP_GSA_QCH, 0x3038, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_MI_P_GSA_CU_QCH, 0x303c, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH, 0x3040, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH, 0x3044, CMU_GSACTRL), + SFR(QCH_CON_LH_AXI_SI_P_GSA_CU_QCH, 0x3048, CMU_GSACTRL), + SFR(QCH_CON_MAILBOX_GSA2AOC_QCH, 0x304c, CMU_GSACTRL), + SFR(QCH_CON_MAILBOX_GSA2AUR_QCH, 0x3050, CMU_GSACTRL), + SFR(QCH_CON_MAILBOX_GSA2NONTZ_QCH, 0x3054, CMU_GSACTRL), + SFR(QCH_CON_MAILBOX_GSA2TPU_QCH, 0x3058, CMU_GSACTRL), + SFR(QCH_CON_MAILBOX_GSA2TZ_QCH, 0x305c, CMU_GSACTRL), + SFR(QCH_CON_PMU_GSA_QCH, 0x3060, CMU_GSACTRL), + SFR(QCH_CON_SECJTAG_GSACTRL_QCH, 0x3064, CMU_GSACTRL), + SFR(QCH_CON_SLH_AXI_MI_P_GSA_QCH, 0x3068, CMU_GSACTRL), + SFR(QCH_CON_SYSREG_GSACTRL_QCH, 0x3070, CMU_GSACTRL), + SFR(QCH_CON_SYSREG_GSACTRLEXT_QCH, 0x306c, CMU_GSACTRL), + SFR(QCH_CON_TIMER_GSACTRL_QCH, 0x3074, CMU_GSACTRL), + SFR(QCH_CON_TZPC_GSACTRL_QCH, 0x3078, CMU_GSACTRL), + SFR(QCH_CON_DP_LINK_QCH_PCLK, 0x3038, CMU_HSI0), + SFR(QCH_CON_DP_LINK_QCH_GTC_CLK, 0x3034, CMU_HSI0), + SFR(QCH_CON_D_TZPC_HSI0_QCH, 0x303c, CMU_HSI0), + SFR(QCH_CON_ETR_MIU_QCH_ACLK, 0x3040, CMU_HSI0), + SFR(QCH_CON_ETR_MIU_QCH_PCLK, 0x3044, CMU_HSI0), + SFR(QCH_CON_GPC_HSI0_QCH, 0x3048, CMU_HSI0), + SFR(QCH_CON_HSI0_CMU_HSI0_QCH, 0x304c, CMU_HSI0), + SFR(QCH_CON_LH_ACEL_SI_D_HSI0_QCH, 0x3050, CMU_HSI0), + SFR(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH, 0x3054, CMU_HSI0), + SFR(QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH, 0x3058, CMU_HSI0), + SFR(QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH, 0x305c, CMU_HSI0), + SFR(QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH, 0x3060, CMU_HSI0), + SFR(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH, 0x3064, CMU_HSI0), + SFR(QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH, 0x3068, CMU_HSI0), + SFR(QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH, 0x306c, CMU_HSI0), + SFR(QCH_CON_PPMU_HSI0_AOC_QCH, 0x3070, CMU_HSI0), + SFR(QCH_CON_PPMU_HSI0_NOCL1B_QCH, 0x3074, CMU_HSI0), + SFR(QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH, 0x3078, CMU_HSI0), + SFR(QCH_CON_SLH_AXI_MI_LP1_AOC_QCH, 0x307c, CMU_HSI0), + SFR(QCH_CON_SLH_AXI_MI_P_HSI0_QCH, 0x3080, CMU_HSI0), + SFR(QCH_CON_SSMT_USB_QCH, 0x3084, CMU_HSI0), + SFR(QCH_CON_SYSMMU_USB_QCH_S2, 0x308c, CMU_HSI0), + SFR(QCH_CON_SYSMMU_USB_QCH_S1, 0x3088, CMU_HSI0), + SFR(QCH_CON_SYSREG_HSI0_QCH, 0x3090, CMU_HSI0), + SFR(QCH_CON_UASC_HSI0_CTRL_QCH, 0x3094, CMU_HSI0), + SFR(QCH_CON_UASC_HSI0_LINK_QCH, 0x3098, CMU_HSI0), + SFR(DMYQCH_CON_USB31DRD_QCH_REF, 0x3004, CMU_HSI0), + SFR(QCH_CON_USB31DRD_QCH_SLV_CTRL, 0x30a8, CMU_HSI0), + SFR(QCH_CON_USB31DRD_QCH_SLV_LINK, 0x30ac, CMU_HSI0), + SFR(QCH_CON_USB31DRD_QCH_APB, 0x309c, CMU_HSI0), + SFR(QCH_CON_USB31DRD_QCH_PCS, 0x30a4, CMU_HSI0), + SFR(QCH_CON_USB31DRD_QCH_DBG, 0x30a0, CMU_HSI0), + SFR(DMYQCH_CON_USB31DRD_QCH, 0x3000, CMU_HSI0), + SFR(QCH_CON_D_TZPC_HSI1_QCH, 0x3018, CMU_HSI1), + SFR(QCH_CON_GPC_HSI1_QCH, 0x301c, CMU_HSI1), + SFR(QCH_CON_GPIO_HSI1_QCH, 0x3020, CMU_HSI1), + SFR(QCH_CON_HSI1_CMU_HSI1_QCH, 0x3024, CMU_HSI1), + SFR(QCH_CON_LH_ACEL_SI_D_HSI1_QCH, 0x3028, CMU_HSI1), + SFR(QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH, 0x302c, CMU_HSI1), + SFR(QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH, 0x3030, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_DBG_1, 0x3044, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_AXI_1, 0x303c, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_APB_1, 0x3034, CMU_HSI1), + SFR(DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1, 0x3004, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB, 0x304c, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB, 0x3050, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_DBG_2, 0x3048, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_AXI_2, 0x3040, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_APB_2, 0x3038, CMU_HSI1), + SFR(QCH_CON_PCIE_GEN4_0_QCH_UDBG, 0x3054, CMU_HSI1), + SFR(DMYQCH_CON_PCIE_GEN4_0_QCH, 0x3000, CMU_HSI1), + SFR(QCH_CON_PCIE_IA_GEN4A_0_QCH, 0x3058, CMU_HSI1), + SFR(QCH_CON_PCIE_IA_GEN4B_0_QCH, 0x305c, CMU_HSI1), + SFR(QCH_CON_PPMU_HSI1_QCH, 0x3060, CMU_HSI1), + SFR(QCH_CON_QE_PCIE_GEN4A_HSI1_QCH, 0x3064, CMU_HSI1), + SFR(QCH_CON_QE_PCIE_GEN4B_HSI1_QCH, 0x3068, CMU_HSI1), + SFR(QCH_CON_SLH_AXI_MI_P_HSI1_QCH, 0x306c, CMU_HSI1), + SFR(QCH_CON_SSMT_HSI1_QCH, 0x3070, CMU_HSI1), + SFR(QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH, 0x3074, CMU_HSI1), + SFR(QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH, 0x3078, CMU_HSI1), + SFR(QCH_CON_SYSMMU_HSI1_QCH_S2, 0x3080, CMU_HSI1), + SFR(QCH_CON_SYSMMU_HSI1_QCH_S1, 0x307c, CMU_HSI1), + SFR(QCH_CON_SYSREG_HSI1_QCH, 0x3084, CMU_HSI1), + SFR(QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH, 0x3088, CMU_HSI1), + SFR(QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH, 0x308c, CMU_HSI1), + SFR(QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH, 0x3090, CMU_HSI1), + SFR(QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH, 0x3094, CMU_HSI1), + SFR(QCH_CON_D_TZPC_HSI2_QCH, 0x3018, CMU_HSI2), + SFR(QCH_CON_GPC_HSI2_QCH, 0x301c, CMU_HSI2), + SFR(QCH_CON_GPIO_HSI2_QCH, 0x3024, CMU_HSI2), + SFR(QCH_CON_GPIO_HSI2UFS_QCH, 0x3020, CMU_HSI2), + SFR(QCH_CON_HSI2_CMU_HSI2_QCH, 0x3028, CMU_HSI2), + SFR(QCH_CON_LH_ACEL_SI_D_HSI2_QCH, 0x302c, CMU_HSI2), + SFR(QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH, 0x3030, CMU_HSI2), + SFR(QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH, 0x3034, CMU_HSI2), + SFR(QCH_CON_MMC_CARD_QCH, 0x3038, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_AXI_1, 0x3048, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_APB_1, 0x3040, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_DBG_1, 0x3050, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_PCS_APB, 0x3058, CMU_HSI2), + SFR(DMYQCH_CON_PCIE_GEN4_1_QCH_REF0, 0x3000, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_PMA_APB, 0x305c, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_AXI_2, 0x304c, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_DBG_2, 0x3054, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_APB_2, 0x3044, CMU_HSI2), + SFR(QCH_CON_PCIE_GEN4_1_QCH_UDBG, 0x3060, CMU_HSI2), + SFR(DMYQCH_CON_PCIE_GEN4_1_QCH_REF1, 0x3004, CMU_HSI2), + SFR(QCH_CON_PCIE_IA_GEN4A_1_QCH, 0x3064, CMU_HSI2), + SFR(QCH_CON_PCIE_IA_GEN4B_1_QCH, 0x3068, CMU_HSI2), + SFR(QCH_CON_PPMU_HSI2_QCH, 0x306c, CMU_HSI2), + SFR(QCH_CON_QE_MMC_CARD_HSI2_QCH, 0x3070, CMU_HSI2), + SFR(QCH_CON_QE_PCIE_GEN4A_HSI2_QCH, 0x3074, CMU_HSI2), + SFR(QCH_CON_QE_PCIE_GEN4B_HSI2_QCH, 0x3078, CMU_HSI2), + SFR(QCH_CON_QE_UFS_EMBD_HSI2_QCH, 0x307c, CMU_HSI2), + SFR(QCH_CON_SLH_AXI_MI_P_HSI2_QCH, 0x3080, CMU_HSI2), + SFR(QCH_CON_SSMT_HSI2_QCH, 0x3084, CMU_HSI2), + SFR(QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH, 0x3088, CMU_HSI2), + SFR(QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH, 0x308c, CMU_HSI2), + SFR(QCH_CON_SYSMMU_HSI2_QCH_S2, 0x3094, CMU_HSI2), + SFR(QCH_CON_SYSMMU_HSI2_QCH_S1, 0x3090, CMU_HSI2), + SFR(QCH_CON_SYSREG_HSI2_QCH, 0x3098, CMU_HSI2), + SFR(QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH, 0x309c, CMU_HSI2), + SFR(QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH, 0x30a0, CMU_HSI2), + SFR(QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH, 0x30a4, CMU_HSI2), + SFR(QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH, 0x30a8, CMU_HSI2), + SFR(QCH_CON_UFS_EMBD_QCH, 0x30ac, CMU_HSI2), + SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x30b0, CMU_HSI2), + SFR(QCH_CON_D_TZPC_IPP_QCH, 0x3040, CMU_IPP), + SFR(QCH_CON_GPC_IPP_QCH, 0x3044, CMU_IPP), + SFR(QCH_CON_IPP_CMU_IPP_QCH, 0x3048, CMU_IPP), + SFR(QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH, 0x304c, CMU_IPP), + SFR(QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH, 0x3050, CMU_IPP), + SFR(QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH, 0x3054, CMU_IPP), + SFR(QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH, 0x3058, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH, 0x305c, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH, 0x3060, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH, 0x3064, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH, 0x3068, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH, 0x306c, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH, 0x3070, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH, 0x3074, CMU_IPP), + SFR(QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH, 0x3078, CMU_IPP), + SFR(QCH_CON_LH_AXI_SI_D_IPP_QCH, 0x307c, CMU_IPP), + SFR(QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH, 0x3080, CMU_IPP), + SFR(QCH_CON_PPMU_IPP_QCH, 0x3088, CMU_IPP), + SFR(QCH_CON_PPMU_MSA_QCH, 0x308c, CMU_IPP), + SFR(QCH_CON_QE_ALIGN0_QCH, 0x3090, CMU_IPP), + SFR(QCH_CON_QE_ALIGN1_QCH, 0x3094, CMU_IPP), + SFR(QCH_CON_QE_ALIGN2_QCH, 0x3098, CMU_IPP), + SFR(QCH_CON_QE_ALIGN3_QCH, 0x309c, CMU_IPP), + SFR(QCH_CON_QE_ALN_STAT_QCH, 0x30a0, CMU_IPP), + SFR(QCH_CON_QE_FDPIG_QCH, 0x30a4, CMU_IPP), + SFR(QCH_CON_QE_RGBH0_QCH, 0x30a8, CMU_IPP), + SFR(QCH_CON_QE_RGBH1_QCH, 0x30ac, CMU_IPP), + SFR(QCH_CON_QE_RGBH2_QCH, 0x30b0, CMU_IPP), + SFR(QCH_CON_QE_THSTAT_QCH, 0x30b4, CMU_IPP), + SFR(QCH_CON_QE_TNR_MSA0_QCH, 0x30b8, CMU_IPP), + SFR(QCH_CON_QE_TNR_MSA1_QCH, 0x30bc, CMU_IPP), + SFR(QCH_CON_SIPU_IPP_QCH, 0x30c0, CMU_IPP), + SFR(QCH_CON_SLH_AXI_MI_P_IPP_QCH, 0x30c4, CMU_IPP), + SFR(QCH_CON_SSMT_ALIGN0_QCH, 0x30c8, CMU_IPP), + SFR(QCH_CON_SSMT_ALIGN1_QCH, 0x30cc, CMU_IPP), + SFR(QCH_CON_SSMT_ALIGN2_QCH, 0x30d0, CMU_IPP), + SFR(QCH_CON_SSMT_ALIGN3_QCH, 0x30d4, CMU_IPP), + SFR(QCH_CON_SSMT_ALN_STAT_QCH, 0x30d8, CMU_IPP), + SFR(QCH_CON_SSMT_FDPIG_QCH, 0x30dc, CMU_IPP), + SFR(QCH_CON_SSMT_RGBH0_QCH, 0x30e0, CMU_IPP), + SFR(QCH_CON_SSMT_RGBH1_QCH, 0x30e4, CMU_IPP), + SFR(QCH_CON_SSMT_RGBH2_QCH, 0x30e8, CMU_IPP), + SFR(QCH_CON_SSMT_THSTAT_QCH, 0x30ec, CMU_IPP), + SFR(QCH_CON_SSMT_TNR_MSA0_QCH, 0x30f0, CMU_IPP), + SFR(QCH_CON_SSMT_TNR_MSA1_QCH, 0x30f4, CMU_IPP), + SFR(QCH_CON_SYSMMU_IPP_QCH_S1, 0x30f8, CMU_IPP), + SFR(QCH_CON_SYSMMU_IPP_QCH_S2, 0x30fc, CMU_IPP), + SFR(QCH_CON_SYSREG_IPP_QCH, 0x3100, CMU_IPP), + SFR(QCH_CON_TNR_A_QCH, 0x3104, CMU_IPP), + SFR(QCH_CON_D_TZPC_ITP_QCH, 0x3018, CMU_ITP), + SFR(QCH_CON_GPC_ITP_QCH, 0x301c, CMU_ITP), + SFR(QCH_CON_ITP_QCH, 0x3024, CMU_ITP), + SFR(QCH_CON_ITP_CMU_ITP_QCH, 0x3020, CMU_ITP), + SFR(QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH, 0x3028, CMU_ITP), + SFR(QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH, 0x302c, CMU_ITP), + SFR(QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH, 0x3030, CMU_ITP), + SFR(QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH, 0x3034, CMU_ITP), + SFR(QCH_CON_PPMU_ITP_QCH, 0x303c, CMU_ITP), + SFR(QCH_CON_QE_ITP_QCH, 0x3040, CMU_ITP), + SFR(QCH_CON_SLH_AXI_MI_P_ITP_QCH, 0x3044, CMU_ITP), + SFR(QCH_CON_SSMT_ITP_QCH, 0x3048, CMU_ITP), + SFR(QCH_CON_SYSREG_ITP_QCH, 0x304c, CMU_ITP), + SFR(QCH_CON_C2R_MCSC_QCH, 0x303c, CMU_MCSC), + SFR(QCH_CON_D_TZPC_MCSC_QCH, 0x3040, CMU_MCSC), + SFR(QCH_CON_GPC_MCSC_QCH, 0x3044, CMU_MCSC), + SFR(QCH_CON_ITSC_QCH_CLK, 0x304c, CMU_MCSC), + SFR(QCH_CON_ITSC_QCH_C2, 0x3048, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH, 0x3050, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH, 0x3054, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH, 0x3058, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH, 0x305c, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH, 0x3060, CMU_MCSC), + SFR(QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH, 0x3064, CMU_MCSC), + SFR(QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH, 0x3068, CMU_MCSC), + SFR(QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH, 0x306c, CMU_MCSC), + SFR(QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH, 0x3070, CMU_MCSC), + SFR(QCH_CON_LH_AXI_SI_D0_MCSC_QCH, 0x3074, CMU_MCSC), + SFR(QCH_CON_LH_AXI_SI_D1_MCSC_QCH, 0x3078, CMU_MCSC), + SFR(QCH_CON_LH_AXI_SI_D2_MCSC_QCH, 0x307c, CMU_MCSC), + SFR(QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH, 0x3080, CMU_MCSC), + SFR(QCH_CON_MCSC_QCH_CLK, 0x3090, CMU_MCSC), + SFR(QCH_CON_MCSC_QCH_C2CLK, 0x308c, CMU_MCSC), + SFR(QCH_CON_MCSC_CMU_MCSC_QCH, 0x3088, CMU_MCSC), + SFR(QCH_CON_PPMU_D0_ITSC_QCH, 0x3094, CMU_MCSC), + SFR(QCH_CON_PPMU_D0_MCSC_QCH, 0x3098, CMU_MCSC), + SFR(QCH_CON_PPMU_D1_ITSC_QCH, 0x309c, CMU_MCSC), + SFR(QCH_CON_PPMU_D1_MCSC_QCH, 0x30a0, CMU_MCSC), + SFR(QCH_CON_QE_D0_MCSC_QCH, 0x30a4, CMU_MCSC), + SFR(QCH_CON_QE_D1_ITSC_QCH, 0x30a8, CMU_MCSC), + SFR(QCH_CON_QE_D1_MCSC_QCH, 0x30ac, CMU_MCSC), + SFR(QCH_CON_QE_D2_ITSC_QCH, 0x30b0, CMU_MCSC), + SFR(QCH_CON_QE_D2_MCSC_QCH, 0x30b4, CMU_MCSC), + SFR(QCH_CON_QE_D3_ITSC_QCH, 0x30b8, CMU_MCSC), + SFR(QCH_CON_QE_D3_MCSC_QCH, 0x30bc, CMU_MCSC), + SFR(QCH_CON_QE_D4_MCSC_QCH, 0x30c0, CMU_MCSC), + SFR(QCH_CON_QE_D5_MCSC_QCH, 0x30c4, CMU_MCSC), + SFR(QCH_CON_SLH_AXI_MI_P_MCSC_QCH, 0x30c8, CMU_MCSC), + SFR(QCH_CON_SSMT_D0_ITSC_QCH, 0x30cc, CMU_MCSC), + SFR(QCH_CON_SSMT_D0_MCSC_QCH, 0x30d0, CMU_MCSC), + SFR(QCH_CON_SSMT_D1_ITSC_QCH, 0x30d4, CMU_MCSC), + SFR(QCH_CON_SSMT_D1_MCSC_QCH, 0x30d8, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S1, 0x30dc, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D0_MCSC_QCH_S2, 0x30e0, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S1, 0x30e4, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D1_MCSC_QCH_S2, 0x30e8, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S1, 0x30ec, CMU_MCSC), + SFR(QCH_CON_SYSMMU_D2_MCSC_QCH_S2, 0x30f0, CMU_MCSC), + SFR(QCH_CON_SYSREG_MCSC_QCH, 0x30f4, CMU_MCSC), + SFR(QCH_CON_D_TZPC_MFC_QCH, 0x3010, CMU_MFC), + SFR(QCH_CON_GPC_MFC_QCH, 0x3014, CMU_MFC), + SFR(QCH_CON_LH_AXI_SI_D0_MFC_QCH, 0x3018, CMU_MFC), + SFR(QCH_CON_LH_AXI_SI_D1_MFC_QCH, 0x301c, CMU_MFC), + SFR(QCH_CON_MFC_QCH, 0x3028, CMU_MFC), + SFR(QCH_CON_MFC_CMU_MFC_QCH, 0x3024, CMU_MFC), + SFR(QCH_CON_PPMU_D0_MFC_QCH, 0x302c, CMU_MFC), + SFR(QCH_CON_PPMU_D1_MFC_QCH, 0x3030, CMU_MFC), + SFR(QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH, 0x3034, CMU_MFC), + SFR(QCH_CON_SLH_AXI_MI_P_MFC_QCH, 0x3038, CMU_MFC), + SFR(QCH_CON_SSMT_D0_MFC_QCH, 0x303c, CMU_MFC), + SFR(QCH_CON_SSMT_D1_MFC_QCH, 0x3040, CMU_MFC), + SFR(QCH_CON_SYSMMU_D0_MFC_QCH_0, 0x3044, CMU_MFC), + SFR(QCH_CON_SYSMMU_D0_MFC_QCH_1, 0x3048, CMU_MFC), + SFR(QCH_CON_SYSMMU_D1_MFC_QCH_0, 0x304c, CMU_MFC), + SFR(QCH_CON_SYSMMU_D1_MFC_QCH_1, 0x3050, CMU_MFC), + SFR(QCH_CON_SYSREG_MFC_QCH, 0x3054, CMU_MFC), + SFR(QCH_CON_APBBR_DDRPHY_QCH, 0x301c, CMU_MIF), + SFR(QCH_CON_APBBR_DMC_QCH, 0x3020, CMU_MIF), + SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, CMU_MIF), + SFR(QCH_CON_DMC_QCH, 0x3024, CMU_MIF), + SFR(QCH_CON_D_TZPC_MIF_QCH, 0x3028, CMU_MIF), + SFR(QCH_CON_GEN_WREN_SECURE_QCH, 0x302c, CMU_MIF), + SFR(QCH_CON_GPC_MIF_QCH, 0x3030, CMU_MIF), + SFR(QCH_CON_LH_AST_MI_G_DMC_CD_QCH, 0x3034, CMU_MIF), + SFR(QCH_CON_LH_AST_SI_G_DMC_QCH, 0x303c, CMU_MIF), + SFR(QCH_CON_LH_AST_SI_G_DMC_CD_QCH, 0x3038, CMU_MIF), + SFR(QCH_CON_LH_AXI_MI_P_MIF_CU_QCH, 0x3040, CMU_MIF), + SFR(QCH_CON_LH_AXI_SI_P_MIF_CU_QCH, 0x3044, CMU_MIF), + SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3048, CMU_MIF), + SFR(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH, 0x304c, CMU_MIF), + SFR(QCH_CON_SLH_AXI_MI_P_MIF_QCH, 0x3050, CMU_MIF), + SFR(QCH_CON_SYSREG_MIF_QCH, 0x3054, CMU_MIF), + SFR(QCH_CON_ADM_AHB_G_SSS_QCH, 0x3040, CMU_MISC), + SFR(QCH_CON_DIT_QCH, 0x3044, CMU_MISC), + SFR(QCH_CON_D_TZPC_MISC_QCH, 0x3048, CMU_MISC), + SFR(QCH_CON_GIC_QCH, 0x304c, CMU_MISC), + SFR(QCH_CON_GPC_MISC_QCH, 0x3050, CMU_MISC), + SFR(QCH_CON_LH_ACEL_SI_D_MISC_QCH, 0x3054, CMU_MISC), + SFR(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH, 0x305c, CMU_MISC), + SFR(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH, 0x3058, CMU_MISC), + SFR(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH, 0x3060, CMU_MISC), + SFR(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH, 0x3064, CMU_MISC), + SFR(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH, 0x306c, CMU_MISC), + SFR(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH, 0x3068, CMU_MISC), + SFR(QCH_CON_LH_AXI_MI_ID_SSS_QCH, 0x3070, CMU_MISC), + SFR(QCH_CON_LH_AXI_MI_P_GIC_CU_QCH, 0x3074, CMU_MISC), + SFR(QCH_CON_LH_AXI_MI_P_MISC_CU_QCH, 0x3078, CMU_MISC), + SFR(QCH_CON_LH_AXI_SI_ID_SSS_QCH, 0x307c, CMU_MISC), + SFR(QCH_CON_LH_AXI_SI_P_GIC_CU_QCH, 0x3080, CMU_MISC), + SFR(QCH_CON_LH_AXI_SI_P_MISC_CU_QCH, 0x3084, CMU_MISC), + SFR(QCH_CON_MCT_QCH, 0x3088, CMU_MISC), + SFR(QCH_CON_MISC_CMU_MISC_QCH, 0x308c, CMU_MISC), + SFR(QCH_CON_OTP_CON_BIRA_QCH, 0x3090, CMU_MISC), + SFR(QCH_CON_OTP_CON_BISR_QCH, 0x3094, CMU_MISC), + SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3098, CMU_MISC), + SFR(QCH_CON_PDMA0_QCH, 0x309c, CMU_MISC), + SFR(QCH_CON_PDMA1_QCH, 0x30a0, CMU_MISC), + SFR(QCH_CON_PPMU_MISC_QCH, 0x30a4, CMU_MISC), + SFR(DMYQCH_CON_PUF_QCH, 0x3000, CMU_MISC), + SFR(QCH_CON_QE_DIT_QCH, 0x30a8, CMU_MISC), + SFR(QCH_CON_QE_PDMA0_QCH, 0x30ac, CMU_MISC), + SFR(QCH_CON_QE_PDMA1_QCH, 0x30b0, CMU_MISC), + SFR(QCH_CON_QE_RTIC_QCH, 0x30b4, CMU_MISC), + SFR(QCH_CON_QE_SPDMA0_QCH, 0x30b8, CMU_MISC), + SFR(QCH_CON_QE_SPDMA1_QCH, 0x30bc, CMU_MISC), + SFR(QCH_CON_QE_SSS_QCH, 0x30c0, CMU_MISC), + SFR(QCH_CON_RTIC_QCH, 0x30c4, CMU_MISC), + SFR(QCH_CON_SLH_AXI_MI_P_GIC_QCH, 0x30c8, CMU_MISC), + SFR(QCH_CON_SLH_AXI_MI_P_MISC_QCH, 0x30cc, CMU_MISC), + SFR(QCH_CON_SPDMA0_QCH, 0x30d0, CMU_MISC), + SFR(QCH_CON_SPDMA1_QCH, 0x30d4, CMU_MISC), + SFR(QCH_CON_SSMT_DIT_QCH, 0x30d8, CMU_MISC), + SFR(QCH_CON_SSMT_PDMA0_QCH, 0x30dc, CMU_MISC), + SFR(QCH_CON_SSMT_PDMA1_QCH, 0x30e0, CMU_MISC), + SFR(QCH_CON_SSMT_RTIC_QCH, 0x30e4, CMU_MISC), + SFR(QCH_CON_SSMT_SPDMA0_QCH, 0x30e8, CMU_MISC), + SFR(QCH_CON_SSMT_SPDMA1_QCH, 0x30ec, CMU_MISC), + SFR(QCH_CON_SSMT_SSS_QCH, 0x30f0, CMU_MISC), + SFR(QCH_CON_SSS_QCH, 0x30f4, CMU_MISC), + SFR(QCH_CON_SYSMMU_MISC_QCH, 0x30f8, CMU_MISC), + SFR(QCH_CON_SYSMMU_SSS_QCH, 0x30fc, CMU_MISC), + SFR(QCH_CON_SYSREG_MISC_QCH, 0x3100, CMU_MISC), + SFR(QCH_CON_TMU_SUB_QCH, 0x3104, CMU_MISC), + SFR(QCH_CON_TMU_TOP_QCH, 0x3108, CMU_MISC), + SFR(QCH_CON_WDT_CLUSTER0_QCH, 0x310c, CMU_MISC), + SFR(QCH_CON_WDT_CLUSTER1_QCH, 0x3110, CMU_MISC), + SFR(QCH_CON_ASYNCSFR_WR_SMC_QCH, 0x3124, CMU_NOCL0), + SFR(QCH_CON_BDU_QCH, 0x3128, CMU_NOCL0), + SFR(QCH_CON_CCI_QCH, 0x312c, CMU_NOCL0), + SFR(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH, 0x3000, CMU_NOCL0), + SFR(QCH_CON_CPE425_QCH, 0x3130, CMU_NOCL0), + SFR(QCH_CON_D_TZPC_NOCL0_QCH, 0x3134, CMU_NOCL0), + SFR(QCH_CON_GPC_NOCL0_QCH, 0x3138, CMU_NOCL0), + SFR(QCH_CON_LH_ACEL_MI_D_EH_QCH, 0x313c, CMU_NOCL0), + SFR(QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH, 0x3140, CMU_NOCL0), + SFR(QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH, 0x3144, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC0_QCH, 0x314c, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC0_CU_QCH, 0x3148, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC1_QCH, 0x3154, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC1_CU_QCH, 0x3150, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC2_QCH, 0x315c, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC2_CU_QCH, 0x3158, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC3_QCH, 0x3164, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_DMC3_CU_QCH, 0x3160, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL1A_QCH, 0x316c, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH, 0x3168, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL1B_QCH, 0x3174, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH, 0x3170, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL2A_QCH, 0x317c, CMU_NOCL0), + SFR(QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH, 0x3178, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_DMC0_CU_QCH, 0x3180, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_DMC1_CU_QCH, 0x3184, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_DMC2_CU_QCH, 0x3188, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_DMC3_CU_QCH, 0x318c, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH, 0x3190, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH, 0x3194, CMU_NOCL0), + SFR(QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH, 0x3198, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_MI_T_BDU_CD_QCH, 0x319c, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_MI_T_SLC_CD_QCH, 0x31a0, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_SI_T_BDU_QCH, 0x31a8, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_SI_T_BDU_CD_QCH, 0x31a4, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_SI_T_SLC_QCH, 0x31b0, CMU_NOCL0), + SFR(QCH_CON_LH_ATB_SI_T_SLC_CD_QCH, 0x31ac, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH, 0x31b4, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH, 0x31b8, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_EH_CD_QCH, 0x31bc, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_GIC_CD_QCH, 0x31c0, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH, 0x31c4, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH, 0x31c8, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH, 0x31cc, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH, 0x31d0, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_MISC_CD_QCH, 0x31d4, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH, 0x31d8, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH, 0x31dc, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH, 0x31e0, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH, 0x31e4, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_EH_CD_QCH, 0x31e8, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_GIC_CD_QCH, 0x31ec, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH, 0x31f0, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH, 0x31f4, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH, 0x31f8, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH, 0x31fc, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_MISC_CD_QCH, 0x3200, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH, 0x3204, CMU_NOCL0), + SFR(QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH, 0x3208, CMU_NOCL0), + SFR(QCH_CON_NOCL0_CMU_NOCL0_QCH, 0x320c, CMU_NOCL0), + SFR(QCH_CON_PPC_CCI_M1_CYCLE_QCH, 0x3210, CMU_NOCL0), + SFR(QCH_CON_PPC_CCI_M1_EVENT_QCH, 0x3214, CMU_NOCL0), + SFR(QCH_CON_PPC_CCI_M2_EVENT_QCH, 0x3218, CMU_NOCL0), + SFR(QCH_CON_PPC_CCI_M3_EVENT_QCH, 0x321c, CMU_NOCL0), + SFR(QCH_CON_PPC_CCI_M4_EVENT_QCH, 0x3220, CMU_NOCL0), + SFR(QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH, 0x3224, CMU_NOCL0), + SFR(QCH_CON_PPC_CPUCL0_D0_EVENT_QCH, 0x3228, CMU_NOCL0), + SFR(QCH_CON_PPC_CPUCL0_D1_EVENT_QCH, 0x322c, CMU_NOCL0), + SFR(DMYQCH_CON_PPC_DBG_CC_QCH, 0x3004, CMU_NOCL0), + SFR(QCH_CON_PPC_EH_CYCLE_QCH, 0x3230, CMU_NOCL0), + SFR(QCH_CON_PPC_EH_EVENT_QCH, 0x3234, CMU_NOCL0), + SFR(QCH_CON_PPC_IO_CYCLE_QCH, 0x3238, CMU_NOCL0), + SFR(QCH_CON_PPC_IO_EVENT_QCH, 0x323c, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH, 0x3240, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1A_M0_EVENT_QCH, 0x3244, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1A_M1_EVENT_QCH, 0x3248, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1A_M2_EVENT_QCH, 0x324c, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1A_M3_EVENT_QCH, 0x3250, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH, 0x3254, CMU_NOCL0), + SFR(QCH_CON_PPC_NOCL1B_M0_EVENT_QCH, 0x3258, CMU_NOCL0), + SFR(QCH_CON_PPMU_ACE_CPUCL0_D0_QCH, 0x325c, CMU_NOCL0), + SFR(QCH_CON_PPMU_ACE_CPUCL0_D1_QCH, 0x3260, CMU_NOCL0), + SFR(QCH_CON_SFR_APBIF_CMU_TOPC_QCH, 0x3264, CMU_NOCL0), + SFR(QCH_CON_SLC_CB_TOP_QCH, 0x3268, CMU_NOCL0), + SFR(DMYQCH_CON_SLC_CH1_QCH, 0x3008, CMU_NOCL0), + SFR(DMYQCH_CON_SLC_CH2_QCH, 0x300c, CMU_NOCL0), + SFR(DMYQCH_CON_SLC_CH3_QCH, 0x3010, CMU_NOCL0), + SFR(DMYQCH_CON_SLC_CH_TOP_QCH, 0x3014, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_MI_G_NOCL0_QCH, 0x326c, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_ALIVE_QCH, 0x3270, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH, 0x3274, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_EH_QCH, 0x3278, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_GIC_QCH, 0x327c, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_MIF0_QCH, 0x3280, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_MIF1_QCH, 0x3284, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_MIF2_QCH, 0x3288, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_MIF3_QCH, 0x328c, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_MISC_QCH, 0x3290, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH, 0x3294, CMU_NOCL0), + SFR(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH, 0x3298, CMU_NOCL0), + SFR(QCH_CON_SYSREG_NOCL0_QCH, 0x329c, CMU_NOCL0), + SFR(QCH_CON_TREX_D_NOCL0_QCH, 0x32a0, CMU_NOCL0), + SFR(QCH_CON_TREX_P_NOCL0_QCH, 0x32a4, CMU_NOCL0), + SFR(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH, 0x3000, CMU_NOCL1A), + SFR(QCH_CON_D_TZPC_NOCL1A_QCH, 0x3058, CMU_NOCL1A), + SFR(QCH_CON_GPC_NOCL1A_QCH, 0x305c, CMU_NOCL1A), + SFR(QCH_CON_LH_ACEL_MI_D0_G3D_QCH, 0x3060, CMU_NOCL1A), + SFR(QCH_CON_LH_ACEL_MI_D1_G3D_QCH, 0x3064, CMU_NOCL1A), + SFR(QCH_CON_LH_ACEL_MI_D2_G3D_QCH, 0x3068, CMU_NOCL1A), + SFR(QCH_CON_LH_ACEL_MI_D3_G3D_QCH, 0x306c, CMU_NOCL1A), + SFR(QCH_CON_LH_ACEL_MI_D_TPU_QCH, 0x3070, CMU_NOCL1A), + SFR(QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH, 0x3074, CMU_NOCL1A), + SFR(QCH_CON_LH_AST_SI_G_NOCL1A_QCH, 0x307c, CMU_NOCL1A), + SFR(QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH, 0x3078, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_MI_D0_AUR_QCH, 0x3080, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_MI_D1_AUR_QCH, 0x3084, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_MI_P_AUR_CD_QCH, 0x3088, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_MI_P_G3D_CD_QCH, 0x308c, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_MI_P_TPU_CD_QCH, 0x3090, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_SI_P_AUR_CD_QCH, 0x3094, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_SI_P_G3D_CD_QCH, 0x3098, CMU_NOCL1A), + SFR(QCH_CON_LH_AXI_SI_P_TPU_CD_QCH, 0x309c, CMU_NOCL1A), + SFR(QCH_CON_NOCL1A_CMU_NOCL1A_QCH, 0x30a0, CMU_NOCL1A), + SFR(QCH_CON_PPCFW_G3D0_QCH, 0x30a4, CMU_NOCL1A), + SFR(QCH_CON_PPCFW_G3D1_QCH, 0x30a8, CMU_NOCL1A), + SFR(QCH_CON_PPC_AUR_D0_CYCLE_QCH, 0x30ac, CMU_NOCL1A), + SFR(QCH_CON_PPC_AUR_D0_EVENT_QCH, 0x30b0, CMU_NOCL1A), + SFR(QCH_CON_PPC_AUR_D1_EVENT_QCH, 0x30b4, CMU_NOCL1A), + SFR(QCH_CON_PPC_G3D_D0_CYCLE_QCH, 0x30b8, CMU_NOCL1A), + SFR(QCH_CON_PPC_G3D_D0_EVENT_QCH, 0x30bc, CMU_NOCL1A), + SFR(QCH_CON_PPC_G3D_D1_EVENT_QCH, 0x30c0, CMU_NOCL1A), + SFR(QCH_CON_PPC_G3D_D2_EVENT_QCH, 0x30c4, CMU_NOCL1A), + SFR(QCH_CON_PPC_G3D_D3_EVENT_QCH, 0x30c8, CMU_NOCL1A), + SFR(QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH, 0x30cc, CMU_NOCL1A), + SFR(QCH_CON_PPC_NOCL2A_M0_EVENT_QCH, 0x30d0, CMU_NOCL1A), + SFR(QCH_CON_PPC_NOCL2A_M1_EVENT_QCH, 0x30d4, CMU_NOCL1A), + SFR(QCH_CON_PPC_NOCL2A_M2_EVENT_QCH, 0x30d8, CMU_NOCL1A), + SFR(QCH_CON_PPC_NOCL2A_M3_EVENT_QCH, 0x30dc, CMU_NOCL1A), + SFR(QCH_CON_PPC_TPU_CYCLE_QCH, 0x30e0, CMU_NOCL1A), + SFR(QCH_CON_PPC_TPU_EVENT_QCH, 0x30e4, CMU_NOCL1A), + SFR(QCH_CON_SLH_AXI_SI_P_AUR_QCH, 0x30e8, CMU_NOCL1A), + SFR(QCH_CON_SLH_AXI_SI_P_G3D_QCH, 0x30ec, CMU_NOCL1A), + SFR(QCH_CON_SLH_AXI_SI_P_TPU_QCH, 0x30f0, CMU_NOCL1A), + SFR(QCH_CON_SSMT_G3D0_QCH, 0x30f4, CMU_NOCL1A), + SFR(QCH_CON_SSMT_G3D1_QCH, 0x30f8, CMU_NOCL1A), + SFR(QCH_CON_SSMT_G3D2_QCH, 0x30fc, CMU_NOCL1A), + SFR(QCH_CON_SSMT_G3D3_QCH, 0x3100, CMU_NOCL1A), + SFR(QCH_CON_SYSMMU_G3D_QCH_D0, 0x3104, CMU_NOCL1A), + SFR(QCH_CON_SYSMMU_G3D_QCH_D1, 0x3108, CMU_NOCL1A), + SFR(QCH_CON_SYSMMU_G3D_QCH_D2, 0x310c, CMU_NOCL1A), + SFR(QCH_CON_SYSMMU_G3D_QCH_D3, 0x3110, CMU_NOCL1A), + SFR(QCH_CON_SYSMMU_G3D_QCH_MPTW, 0x3114, CMU_NOCL1A), + SFR(QCH_CON_SYSREG_NOCL1A_QCH, 0x3118, CMU_NOCL1A), + SFR(QCH_CON_TREX_D_NOCL1A_QCH, 0x311c, CMU_NOCL1A), + SFR(QCH_CON_TREX_P_NOCL1A_QCH, 0x3120, CMU_NOCL1A), + SFR(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH, 0x3000, CMU_NOCL1B), + SFR(QCH_CON_D_TZPC_NOCL1B_QCH, 0x3068, CMU_NOCL1B), + SFR(QCH_CON_GPC_NOCL1B_QCH, 0x306c, CMU_NOCL1B), + SFR(QCH_CON_LH_ACEL_MI_D_HSI0_QCH, 0x3070, CMU_NOCL1B), + SFR(QCH_CON_LH_ACEL_MI_D_HSI1_QCH, 0x3074, CMU_NOCL1B), + SFR(QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH, 0x3078, CMU_NOCL1B), + SFR(QCH_CON_LH_AST_SI_G_NOCL1B_QCH, 0x3080, CMU_NOCL1B), + SFR(QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH, 0x307c, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_D_AOC_QCH, 0x3084, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_D_APM_QCH, 0x3088, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_D_GSA_QCH, 0x308c, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH, 0x3090, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_P_AOC_CD_QCH, 0x3094, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_P_GSA_CD_QCH, 0x3098, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH, 0x309c, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH, 0x30a0, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH, 0x30a4, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_SI_P_AOC_CD_QCH, 0x30a8, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_SI_P_GSA_CD_QCH, 0x30ac, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH, 0x30b0, CMU_NOCL1B), + SFR(QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH, 0x30b4, CMU_NOCL1B), + SFR(QCH_CON_NOCL1B_CMU_NOCL1B_QCH, 0x30b8, CMU_NOCL1B), + SFR(QCH_CON_PPC_AOC_CYCLE_QCH, 0x30bc, CMU_NOCL1B), + SFR(QCH_CON_PPC_AOC_EVENT_QCH, 0x30c0, CMU_NOCL1B), + SFR(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH, 0x30c4, CMU_NOCL1B), + SFR(QCH_CON_SLH_AXI_SI_P_AOC_QCH, 0x30c8, CMU_NOCL1B), + SFR(QCH_CON_SLH_AXI_SI_P_GSA_QCH, 0x30cc, CMU_NOCL1B), + SFR(QCH_CON_SLH_AXI_SI_P_HSI0_QCH, 0x30d0, CMU_NOCL1B), + SFR(QCH_CON_SLH_AXI_SI_P_HSI1_QCH, 0x30d4, CMU_NOCL1B), + SFR(QCH_CON_SYSREG_NOCL1B_QCH, 0x30d8, CMU_NOCL1B), + SFR(QCH_CON_TREX_D_NOCL1B_QCH, 0x30dc, CMU_NOCL1B), + SFR(QCH_CON_TREX_P_NOCL1B_QCH, 0x30e0, CMU_NOCL1B), + SFR(DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH, 0x3000, CMU_NOCL2A), + SFR(QCH_CON_D_TZPC_NOCL2A_QCH, 0x3130, CMU_NOCL2A), + SFR(QCH_CON_GPC_NOCL2A_QCH, 0x3134, CMU_NOCL2A), + SFR(QCH_CON_LH_ACEL_MI_D2_G2D_QCH, 0x3138, CMU_NOCL2A), + SFR(QCH_CON_LH_ACEL_MI_D_HSI2_QCH, 0x313c, CMU_NOCL2A), + SFR(QCH_CON_LH_ACEL_MI_D_MISC_QCH, 0x3140, CMU_NOCL2A), + SFR(QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH, 0x3144, CMU_NOCL2A), + SFR(QCH_CON_LH_AST_SI_G_NOCL2A_QCH, 0x314c, CMU_NOCL2A), + SFR(QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH, 0x3148, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_CSIS_QCH, 0x3150, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_DPU_QCH, 0x3154, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_G2D_QCH, 0x3158, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_GDC_QCH, 0x315c, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_MCSC_QCH, 0x3160, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_MFC_QCH, 0x3164, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D0_TNR_QCH, 0x3168, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_CSIS_QCH, 0x316c, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_DPU_QCH, 0x3170, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_G2D_QCH, 0x3174, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_GDC_QCH, 0x3178, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_MCSC_QCH, 0x317c, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_MFC_QCH, 0x3180, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D1_TNR_QCH, 0x3184, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D2_DPU_QCH, 0x3188, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D2_GDC_QCH, 0x318c, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D2_MCSC_QCH, 0x3190, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D2_TNR_QCH, 0x3194, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D3_TNR_QCH, 0x3198, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D4_TNR_QCH, 0x319c, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D_BO_QCH, 0x31a0, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D_DNS_QCH, 0x31a4, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D_G3AA_QCH, 0x31a8, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_D_IPP_QCH, 0x31ac, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH, 0x31cc, CMU_NOCL2A), + SFR(QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH, 0x3204, CMU_NOCL2A), + SFR(QCH_CON_NOCL2A_CMU_NOCL2A_QCH, 0x3220, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_BO_QCH, 0x3224, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_CSIS_QCH, 0x3228, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_DISP_QCH, 0x322c, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_DNS_QCH, 0x3230, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_DPU_QCH, 0x3234, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_G2D_QCH, 0x3238, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_G3AA_QCH, 0x323c, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_GDC_QCH, 0x3240, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_HSI2_QCH, 0x3244, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_IPP_QCH, 0x3248, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_ITP_QCH, 0x324c, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_MCSC_QCH, 0x3250, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_MFC_QCH, 0x3254, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_PDP_QCH, 0x3258, CMU_NOCL2A), + SFR(QCH_CON_SLH_AXI_SI_P_TNR_QCH, 0x325c, CMU_NOCL2A), + SFR(QCH_CON_SYSREG_NOCL2A_QCH, 0x3260, CMU_NOCL2A), + SFR(QCH_CON_TREX_D_NOCL2A_QCH, 0x3264, CMU_NOCL2A), + SFR(QCH_CON_TREX_P_NOCL2A_QCH, 0x3268, CMU_NOCL2A), + SFR(QCH_CON_D_TZPC_PDP_QCH, 0x3050, CMU_PDP), + SFR(QCH_CON_GPC_PDP_QCH, 0x3054, CMU_PDP), + SFR(QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH, 0x3058, CMU_PDP), + SFR(QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH, 0x305c, CMU_PDP), + SFR(QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH, 0x3060, CMU_PDP), + SFR(QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH, 0x3064, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH, 0x3068, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH, 0x306c, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH, 0x3070, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH, 0x3074, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH, 0x3078, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH, 0x307c, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH, 0x3080, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH, 0x3084, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH, 0x3088, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH, 0x308c, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH, 0x3090, CMU_PDP), + SFR(QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH, 0x3094, CMU_PDP), + SFR(QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH, 0x3098, CMU_PDP), + SFR(QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH, 0x309c, CMU_PDP), + SFR(QCH_CON_PDP_CMU_PDP_QCH, 0x30a4, CMU_PDP), + SFR(QCH_CON_PDP_TOP_QCH_C2_PDP, 0x30a8, CMU_PDP), + SFR(QCH_CON_PDP_TOP_QCH_PDP_TOP, 0x30ac, CMU_PDP), + SFR(QCH_CON_PPMU_VRA_QCH, 0x30b0, CMU_PDP), + SFR(QCH_CON_QE_PDP_AF0_QCH, 0x30b4, CMU_PDP), + SFR(QCH_CON_QE_PDP_AF1_QCH, 0x30b8, CMU_PDP), + SFR(QCH_CON_QE_PDP_STAT0_QCH, 0x30bc, CMU_PDP), + SFR(QCH_CON_QE_PDP_STAT1_QCH, 0x30c0, CMU_PDP), + SFR(QCH_CON_QE_VRA_QCH, 0x30c4, CMU_PDP), + SFR(QCH_CON_SLH_AXI_MI_P_PDP_QCH, 0x30c8, CMU_PDP), + SFR(QCH_CON_SSMT_PDP_STAT_QCH, 0x30cc, CMU_PDP), + SFR(QCH_CON_SSMT_VRA_QCH, 0x30d0, CMU_PDP), + SFR(QCH_CON_SYSREG_PDP_QCH, 0x30d4, CMU_PDP), + SFR(QCH_CON_VRA_QCH, 0x30d8, CMU_PDP), + SFR(QCH_CON_D_TZPC_PERIC0_QCH, 0x302c, CMU_PERIC0), + SFR(QCH_CON_GPC_PERIC0_QCH, 0x3030, CMU_PERIC0), + SFR(QCH_CON_GPIO_PERIC0_QCH, 0x3034, CMU_PERIC0), + SFR(DMYQCH_CON_I3C1_QCH_SCLK, 0x3000, CMU_PERIC0), + SFR(QCH_CON_I3C1_QCH_PCLK, 0x3038, CMU_PERIC0), + SFR(DMYQCH_CON_I3C2_QCH_SCLK, 0x3004, CMU_PERIC0), + SFR(QCH_CON_I3C2_QCH_PCLK, 0x303c, CMU_PERIC0), + SFR(DMYQCH_CON_I3C3_QCH_SCLK, 0x3008, CMU_PERIC0), + SFR(QCH_CON_I3C3_QCH_PCLK, 0x3040, CMU_PERIC0), + SFR(DMYQCH_CON_I3C4_QCH_SCLK, 0x300c, CMU_PERIC0), + SFR(QCH_CON_I3C4_QCH_PCLK, 0x3044, CMU_PERIC0), + SFR(DMYQCH_CON_I3C5_QCH_SCLK, 0x3010, CMU_PERIC0), + SFR(QCH_CON_I3C5_QCH_PCLK, 0x3048, CMU_PERIC0), + SFR(DMYQCH_CON_I3C6_QCH_SCLK, 0x3014, CMU_PERIC0), + SFR(QCH_CON_I3C6_QCH_PCLK, 0x304c, CMU_PERIC0), + SFR(DMYQCH_CON_I3C7_QCH_SCLK, 0x3018, CMU_PERIC0), + SFR(QCH_CON_I3C7_QCH_PCLK, 0x3050, CMU_PERIC0), + SFR(DMYQCH_CON_I3C8_QCH_SCLK, 0x301c, CMU_PERIC0), + SFR(QCH_CON_I3C8_QCH_PCLK, 0x3054, CMU_PERIC0), + SFR(QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH, 0x3058, CMU_PERIC0), + SFR(QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH, 0x305c, CMU_PERIC0), + SFR(QCH_CON_PERIC0_CMU_PERIC0_QCH, 0x3060, CMU_PERIC0), + SFR(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH, 0x3064, CMU_PERIC0), + SFR(QCH_CON_SYSREG_PERIC0_QCH, 0x3068, CMU_PERIC0), + SFR(QCH_CON_USI0_UART_QCH, 0x306c, CMU_PERIC0), + SFR(QCH_CON_USI14_USI_QCH, 0x3070, CMU_PERIC0), + SFR(QCH_CON_USI1_USI_QCH, 0x3074, CMU_PERIC0), + SFR(QCH_CON_USI2_USI_QCH, 0x3078, CMU_PERIC0), + SFR(QCH_CON_USI3_USI_QCH, 0x307c, CMU_PERIC0), + SFR(QCH_CON_USI4_USI_QCH, 0x3080, CMU_PERIC0), + SFR(QCH_CON_USI5_USI_QCH, 0x3084, CMU_PERIC0), + SFR(QCH_CON_USI6_USI_QCH, 0x3088, CMU_PERIC0), + SFR(QCH_CON_USI7_USI_QCH, 0x308c, CMU_PERIC0), + SFR(QCH_CON_USI8_USI_QCH, 0x3090, CMU_PERIC0), + SFR(QCH_CON_D_TZPC_PERIC1_QCH, 0x3010, CMU_PERIC1), + SFR(QCH_CON_GPC_PERIC1_QCH, 0x3014, CMU_PERIC1), + SFR(QCH_CON_GPIO_PERIC1_QCH, 0x3018, CMU_PERIC1), + SFR(DMYQCH_CON_I3C0_QCH_SCLK, 0x3000, CMU_PERIC1), + SFR(QCH_CON_I3C0_QCH_PCLK, 0x301c, CMU_PERIC1), + SFR(QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH, 0x3020, CMU_PERIC1), + SFR(QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH, 0x3024, CMU_PERIC1), + SFR(QCH_CON_PERIC1_CMU_PERIC1_QCH, 0x3028, CMU_PERIC1), + SFR(QCH_CON_PWM_QCH, 0x302c, CMU_PERIC1), + SFR(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH, 0x3030, CMU_PERIC1), + SFR(QCH_CON_SYSREG_PERIC1_QCH, 0x3034, CMU_PERIC1), + SFR(QCH_CON_USI0_USI_QCH, 0x3038, CMU_PERIC1), + SFR(QCH_CON_USI10_USI_QCH, 0x303c, CMU_PERIC1), + SFR(QCH_CON_USI11_USI_QCH, 0x3040, CMU_PERIC1), + SFR(QCH_CON_USI12_USI_QCH, 0x3044, CMU_PERIC1), + SFR(QCH_CON_USI13_USI_QCH, 0x3048, CMU_PERIC1), + SFR(QCH_CON_USI15_USI_QCH, 0x304c, CMU_PERIC1), + SFR(QCH_CON_USI16_USI_QCH, 0x3050, CMU_PERIC1), + SFR(QCH_CON_USI9_USI_QCH, 0x3054, CMU_PERIC1), + SFR(DMYQCH_CON_BIS_S2D_QCH, 0x3000, CMU_S2D), + SFR(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH, 0x3010, CMU_S2D), + SFR(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH, 0x3014, CMU_S2D), + SFR(QCH_CON_S2D_CMU_S2D_QCH, 0x3018, CMU_S2D), + SFR(QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH, 0x301c, CMU_S2D), + SFR(QCH_CON_D_TZPC_TNR_QCH, 0x3030, CMU_TNR), + SFR(QCH_CON_GPC_TNR_QCH, 0x3034, CMU_TNR), + SFR(QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH, 0x3038, CMU_TNR), + SFR(QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH, 0x303c, CMU_TNR), + SFR(QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH, 0x3040, CMU_TNR), + SFR(QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH, 0x3044, CMU_TNR), + SFR(QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH, 0x3048, CMU_TNR), + SFR(QCH_CON_LH_AXI_SI_D0_TNR_QCH, 0x304c, CMU_TNR), + SFR(QCH_CON_LH_AXI_SI_D1_TNR_QCH, 0x3050, CMU_TNR), + SFR(QCH_CON_LH_AXI_SI_D2_TNR_QCH, 0x3054, CMU_TNR), + SFR(QCH_CON_LH_AXI_SI_D3_TNR_QCH, 0x3058, CMU_TNR), + SFR(QCH_CON_LH_AXI_SI_D4_TNR_QCH, 0x305c, CMU_TNR), + SFR(QCH_CON_PPMU_D0_TNR_QCH, 0x3064, CMU_TNR), + SFR(QCH_CON_PPMU_D1_TNR_QCH, 0x3068, CMU_TNR), + SFR(QCH_CON_PPMU_D2_TNR_QCH, 0x306c, CMU_TNR), + SFR(QCH_CON_PPMU_D3_TNR_QCH, 0x3070, CMU_TNR), + SFR(QCH_CON_PPMU_D4_TNR_QCH, 0x3074, CMU_TNR), + SFR(QCH_CON_PPMU_D5_TNR_QCH, 0x3078, CMU_TNR), + SFR(QCH_CON_PPMU_D6_TNR_QCH, 0x307c, CMU_TNR), + SFR(QCH_CON_PPMU_D7_TNR_QCH, 0x3080, CMU_TNR), + SFR(QCH_CON_PPMU_D8_TNR_QCH, 0x3084, CMU_TNR), + SFR(QCH_CON_QE_D0_TNR_QCH, 0x3088, CMU_TNR), + SFR(QCH_CON_QE_D1_TNR_QCH, 0x308c, CMU_TNR), + SFR(QCH_CON_QE_D5_TNR_QCH, 0x3090, CMU_TNR), + SFR(QCH_CON_QE_D6_TNR_QCH, 0x3094, CMU_TNR), + SFR(QCH_CON_QE_D7_TNR_QCH, 0x3098, CMU_TNR), + SFR(QCH_CON_QE_D8_TNR_QCH, 0x309c, CMU_TNR), + SFR(QCH_CON_SLH_AXI_MI_P_TNR_QCH, 0x30a0, CMU_TNR), + SFR(QCH_CON_SSMT_D0_TNR_QCH, 0x30a4, CMU_TNR), + SFR(QCH_CON_SSMT_D1_TNR_QCH, 0x30a8, CMU_TNR), + SFR(QCH_CON_SSMT_D2_TNR_QCH, 0x30ac, CMU_TNR), + SFR(QCH_CON_SSMT_D3_TNR_QCH, 0x30b0, CMU_TNR), + SFR(QCH_CON_SSMT_D4_TNR_QCH, 0x30b4, CMU_TNR), + SFR(QCH_CON_SSMT_D5_TNR_QCH, 0x30b8, CMU_TNR), + SFR(QCH_CON_SSMT_D6_TNR_QCH, 0x30bc, CMU_TNR), + SFR(QCH_CON_SSMT_D7_TNR_QCH, 0x30c0, CMU_TNR), + SFR(QCH_CON_SSMT_D8_TNR_QCH, 0x30c4, CMU_TNR), + SFR(QCH_CON_SYSMMU_D0_TNR_QCH_S1, 0x30c8, CMU_TNR), + SFR(QCH_CON_SYSMMU_D0_TNR_QCH_S2, 0x30cc, CMU_TNR), + SFR(QCH_CON_SYSMMU_D1_TNR_QCH_S1, 0x30d0, CMU_TNR), + SFR(QCH_CON_SYSMMU_D1_TNR_QCH_S2, 0x30d4, CMU_TNR), + SFR(QCH_CON_SYSMMU_D2_TNR_QCH_S2, 0x30dc, CMU_TNR), + SFR(QCH_CON_SYSMMU_D2_TNR_QCH_S1, 0x30d8, CMU_TNR), + SFR(QCH_CON_SYSMMU_D3_TNR_QCH_S2, 0x30e4, CMU_TNR), + SFR(QCH_CON_SYSMMU_D3_TNR_QCH_S1, 0x30e0, CMU_TNR), + SFR(QCH_CON_SYSMMU_D4_TNR_QCH_S1, 0x30e8, CMU_TNR), + SFR(QCH_CON_SYSMMU_D4_TNR_QCH_S2, 0x30ec, CMU_TNR), + SFR(QCH_CON_SYSREG_TNR_QCH, 0x30f0, CMU_TNR), + SFR(QCH_CON_TNR_QCH_C2, 0x30fc, CMU_TNR), + SFR(QCH_CON_TNR_QCH_ACLK, 0x30f8, CMU_TNR), + SFR(QCH_CON_TNR_CMU_TNR_QCH, 0x30f4, CMU_TNR), + SFR(QCH_CON_BUSIF_HPMTPU_QCH, 0x302c, CMU_TPU), + SFR(QCH_CON_D_TZPC_TPU_QCH, 0x3030, CMU_TPU), + SFR(QCH_CON_GPC_TPU_QCH, 0x3034, CMU_TPU), + SFR(QCH_CON_LH_ACEL_SI_D_TPU_QCH, 0x3038, CMU_TPU), + SFR(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH, 0x303c, CMU_TPU), + SFR(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH, 0x3040, CMU_TPU), + SFR(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH, 0x3048, CMU_TPU), + SFR(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH, 0x3044, CMU_TPU), + SFR(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH, 0x3050, CMU_TPU), + SFR(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH, 0x304c, CMU_TPU), + SFR(QCH_CON_LH_AXI_MI_P_TPU_CU_QCH, 0x3054, CMU_TPU), + SFR(QCH_CON_LH_AXI_SI_P_TPU_CU_QCH, 0x3058, CMU_TPU), + SFR(QCH_CON_PPMU_TPU_QCH, 0x305c, CMU_TPU), + SFR(QCH_CON_SLH_AXI_MI_P_TPU_QCH, 0x3068, CMU_TPU), + SFR(QCH_CON_SSMT_TPU_QCH, 0x306c, CMU_TPU), + SFR(QCH_CON_SYSMMU_TPU_QCH_S1, 0x3070, CMU_TPU), + SFR(QCH_CON_SYSMMU_TPU_QCH_S2, 0x3074, CMU_TPU), + SFR(QCH_CON_SYSREG_TPU_QCH, 0x3078, CMU_TPU), + SFR(DMYQCH_CON_TPU_QCH, 0x3000, CMU_TPU), + SFR(QCH_CON_TPU_CMU_TPU_QCH, 0x307c, CMU_TPU), + SFR(AOC_CMU_AOC_CONTROLLER_OPTION, 0x800, CMU_AOC), + SFR(APM_CMU_APM_CONTROLLER_OPTION, 0x800, CMU_APM), + SFR(AUR_CMU_AUR_CONTROLLER_OPTION, 0x800, CMU_AUR), + SFR(BO_CMU_BO_CONTROLLER_OPTION, 0x800, CMU_BO), + SFR(CMU_CMU_TOP_CONTROLLER_OPTION, 0x800, CMU_TOP), + SFR(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, 0x800, CMU_CPUCL0), + SFR(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION, 0x804, CMU_CPUCL0), + SFR(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, 0x800, CMU_CPUCL1), + SFR(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION, 0x800, CMU_CPUCL2), + SFR(CSIS_CMU_CSIS_CONTROLLER_OPTION, 0x800, CMU_CSIS), + SFR(DISP_CMU_DISP_CONTROLLER_OPTION, 0x800, CMU_DISP), + SFR(DNS_CMU_DNS_CONTROLLER_OPTION, 0x800, CMU_DNS), + SFR(DPU_CMU_DPU_CONTROLLER_OPTION, 0x800, CMU_DPU), + SFR(EH_CMU_EH_CONTROLLER_OPTION, 0x800, CMU_EH), + SFR(G2D_CMU_G2D_CONTROLLER_OPTION, 0x800, CMU_G2D), + SFR(G3AA_CMU_G3AA_CONTROLLER_OPTION, 0x800, CMU_G3AA), + SFR(G3D_CMU_G3D_CONTROLLER_OPTION, 0x800, CMU_G3D), + SFR(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION, 0x804, CMU_G3D), + SFR(GDC_CMU_GDC_CONTROLLER_OPTION, 0x800, CMU_GDC), + SFR(GSACORE_CMU_GSACORE_CONTROLLER_OPTION, 0x800, CMU_GSACORE), + SFR(GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION, 0x800, CMU_GSACTRL), + SFR(HSI0_CMU_HSI0_CONTROLLER_OPTION, 0x800, CMU_HSI0), + SFR(HSI1_CMU_HSI1_CONTROLLER_OPTION, 0x800, CMU_HSI1), + SFR(HSI2_CMU_HSI2_CONTROLLER_OPTION, 0x800, CMU_HSI2), + SFR(IPP_CMU_IPP_CONTROLLER_OPTION, 0x800, CMU_IPP), + SFR(ITP_CMU_ITP_CONTROLLER_OPTION, 0x800, CMU_ITP), + SFR(MCSC_CMU_MCSC_CONTROLLER_OPTION, 0x800, CMU_MCSC), + SFR(MFC_CMU_MFC_CONTROLLER_OPTION, 0x800, CMU_MFC), + SFR(MIF_CMU_MIF_CONTROLLER_OPTION, 0x800, CMU_MIF), + SFR(MISC_CMU_MISC_CONTROLLER_OPTION, 0x800, CMU_MISC), + SFR(NOCL0_CMU_NOCL0_CONTROLLER_OPTION, 0x800, CMU_NOCL0), + SFR(NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION, 0x804, CMU_NOCL0), + SFR(NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION, 0x808, CMU_NOCL0), + SFR(NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION, 0x80c, CMU_NOCL0), + SFR(NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION, 0x810, CMU_NOCL0), + SFR(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION, 0x800, CMU_NOCL1A), + SFR(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION, 0x800, CMU_NOCL1B), + SFR(NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION, 0x800, CMU_NOCL2A), + SFR(PDP_CMU_PDP_CONTROLLER_OPTION, 0x800, CMU_PDP), + SFR(PERIC0_CMU_PERIC0_CONTROLLER_OPTION, 0x800, CMU_PERIC0), + SFR(PERIC1_CMU_PERIC1_CONTROLLER_OPTION, 0x800, CMU_PERIC1), + SFR(S2D_CMU_S2D_CONTROLLER_OPTION, 0x800, CMU_S2D), + SFR(TNR_CMU_TNR_CONTROLLER_OPTION, 0x800, CMU_TNR), + SFR(TPU_CMU_TPU_CONTROLLER_OPTION, 0x800, CMU_TPU), +}; + +unsigned int cmucal_sfr_access_size = 13236; +struct sfr_access cmucal_sfr_access_list[] = { + SFR_ACCESS(PLL_LOCKTIME_PLL_AUR_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_ENABLE, 31, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_STABLE, 29, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_DIV_P, 8, 6, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_DIV_M, 16, 10, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_DIV_S, 0, 3, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_ICP, 6, 2, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_AFC_ENB, 20, 1, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_EXT_AFC, 0, 5, PLL_CON4_PLL_AUR), + SFR_ACCESS(DBG_NFO_PLL_AUR_AFC_CODE, 16, 5, DBG_NFO_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_FOUT_MASK, 25, 1, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_RSEL, 28, 4, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_BYPASS, 22, 1, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON0_PLL_AUR_MUX_SEL, 4, 1, PLL_CON0_PLL_AUR), + SFR_ACCESS(PLL_CON0_PLL_AUR_MUX_BUSY, 16, 1, PLL_CON0_PLL_AUR), + SFR_ACCESS(PLL_LOCKTIME_PLL_AUR_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON4_PLL_AUR_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_LOCK_FAIL, 27, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(DBG_NFO_PLL_AUR_DEBUG_INFO, 0, 16, DBG_NFO_PLL_AUR), + SFR_ACCESS(PLL_CON2_PLL_AUR_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_AUR), + SFR_ACCESS(PLL_CON2_PLL_AUR_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_AUR), + SFR_ACCESS(PLL_CON1_PLL_AUR_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_AUR), + SFR_ACCESS(PLL_CON3_PLL_AUR_LOCK_EN, 26, 1, PLL_CON3_PLL_AUR), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_ENABLE, 31, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_STABLE, 29, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_P, 8, 6, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_M, 16, 10, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_DIV_S, 0, 3, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_ICP, 6, 2, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_EXT_AFC, 0, 5, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_AFC_CODE, 16, 5, DBG_NFO_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_FOUT_MASK, 25, 1, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_RSEL, 28, 4, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_BYPASS, 22, 1, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON0_PLL_SHARED0_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED0), + SFR_ACCESS(PLL_CON0_PLL_SHARED0_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED0), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON4_PLL_SHARED0_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0), + SFR_ACCESS(PLL_CON2_PLL_SHARED0_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED0), + SFR_ACCESS(PLL_CON2_PLL_SHARED0_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED0), + SFR_ACCESS(PLL_CON1_PLL_SHARED0_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED0), + SFR_ACCESS(PLL_CON3_PLL_SHARED0_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED0), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_ENABLE, 31, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_STABLE, 29, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_P, 8, 6, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_M, 16, 10, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_DIV_S, 0, 3, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_ICP, 6, 2, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_EXT_AFC, 0, 5, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(DBG_NFO_PLL_SHARED1_AFC_CODE, 16, 5, DBG_NFO_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_FOUT_MASK, 25, 1, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_RSEL, 28, 4, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_BYPASS, 22, 1, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON0_PLL_SHARED1_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED1), + SFR_ACCESS(PLL_CON0_PLL_SHARED1_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED1), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON4_PLL_SHARED1_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(DBG_NFO_PLL_SHARED1_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED1), + SFR_ACCESS(PLL_CON2_PLL_SHARED1_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED1), + SFR_ACCESS(PLL_CON2_PLL_SHARED1_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED1), + SFR_ACCESS(PLL_CON1_PLL_SHARED1_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED1), + SFR_ACCESS(PLL_CON3_PLL_SHARED1_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED1), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_ENABLE, 31, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_STABLE, 29, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_P, 8, 6, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_M, 16, 10, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_DIV_S, 0, 3, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_ICP, 6, 2, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_EXT_AFC, 0, 5, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(DBG_NFO_PLL_SHARED2_AFC_CODE, 16, 5, DBG_NFO_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_FOUT_MASK, 25, 1, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_RSEL, 28, 4, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_BYPASS, 22, 1, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON0_PLL_SHARED2_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED2), + SFR_ACCESS(PLL_CON0_PLL_SHARED2_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED2), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON4_PLL_SHARED2_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(DBG_NFO_PLL_SHARED2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED2), + SFR_ACCESS(PLL_CON2_PLL_SHARED2_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED2), + SFR_ACCESS(PLL_CON2_PLL_SHARED2_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED2), + SFR_ACCESS(PLL_CON1_PLL_SHARED2_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED2), + SFR_ACCESS(PLL_CON3_PLL_SHARED2_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED2), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_ENABLE, 31, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_STABLE, 29, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_P, 8, 6, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_M, 16, 10, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_DIV_S, 0, 3, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_ICP, 6, 2, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_AFC_ENB, 20, 1, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_EXT_AFC, 0, 5, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(DBG_NFO_PLL_SHARED3_AFC_CODE, 16, 5, DBG_NFO_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_FOUT_MASK, 25, 1, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_RSEL, 28, 4, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_BYPASS, 22, 1, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON0_PLL_SHARED3_MUX_SEL, 4, 1, PLL_CON0_PLL_SHARED3), + SFR_ACCESS(PLL_CON0_PLL_SHARED3_MUX_BUSY, 16, 1, PLL_CON0_PLL_SHARED3), + SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON4_PLL_SHARED3_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(DBG_NFO_PLL_SHARED3_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED3), + SFR_ACCESS(PLL_CON2_PLL_SHARED3_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SHARED3), + SFR_ACCESS(PLL_CON2_PLL_SHARED3_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SHARED3), + SFR_ACCESS(PLL_CON1_PLL_SHARED3_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SHARED3), + SFR_ACCESS(PLL_CON3_PLL_SHARED3_LOCK_EN, 26, 1, PLL_CON3_PLL_SHARED3), + SFR_ACCESS(PLL_LOCKTIME_PLL_SPARE_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_ENABLE, 31, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_STABLE, 29, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_DIV_P, 8, 6, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_DIV_M, 16, 10, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_DIV_S, 0, 3, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_ICP, 6, 2, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_AFC_ENB, 20, 1, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_EXT_AFC, 0, 5, PLL_CON4_PLL_SPARE), + SFR_ACCESS(DBG_NFO_PLL_SPARE_AFC_CODE, 16, 5, DBG_NFO_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_FOUT_MASK, 25, 1, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_RSEL, 28, 4, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_BYPASS, 22, 1, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON0_PLL_SPARE_MUX_SEL, 4, 1, PLL_CON0_PLL_SPARE), + SFR_ACCESS(PLL_CON0_PLL_SPARE_MUX_BUSY, 16, 1, PLL_CON0_PLL_SPARE), + SFR_ACCESS(PLL_LOCKTIME_PLL_SPARE_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON4_PLL_SPARE_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_LOCK_FAIL, 27, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(DBG_NFO_PLL_SPARE_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SPARE), + SFR_ACCESS(PLL_CON2_PLL_SPARE_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_SPARE), + SFR_ACCESS(PLL_CON2_PLL_SPARE_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_SPARE), + SFR_ACCESS(PLL_CON1_PLL_SPARE_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_SPARE), + SFR_ACCESS(PLL_CON3_PLL_SPARE_LOCK_EN, 26, 1, PLL_CON3_PLL_SPARE), + SFR_ACCESS(PLL_LOCKTIME_PLL_LF_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_ENABLE, 31, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_STABLE, 29, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_DIV_P, 8, 6, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_DIV_M, 16, 10, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_DIV_S, 0, 3, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_ICP, 6, 2, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_AFC_ENB, 20, 1, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_EXT_AFC, 0, 5, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(DBG_NFO_PLL_LF_MIF_AFC_CODE, 16, 5, DBG_NFO_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_FOUT_MASK, 25, 1, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_RSEL, 28, 4, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_BYPASS, 22, 1, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON0_PLL_LF_MIF_MUX_SEL, 4, 1, PLL_CON0_PLL_LF_MIF), + SFR_ACCESS(PLL_CON0_PLL_LF_MIF_MUX_BUSY, 16, 1, PLL_CON0_PLL_LF_MIF), + SFR_ACCESS(PLL_LOCKTIME_PLL_LF_MIF_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON4_PLL_LF_MIF_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_LOCK_FAIL, 27, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(DBG_NFO_PLL_LF_MIF_DEBUG_INFO, 0, 16, DBG_NFO_PLL_LF_MIF), + SFR_ACCESS(PLL_CON2_PLL_LF_MIF_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_LF_MIF), + SFR_ACCESS(PLL_CON2_PLL_LF_MIF_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_LF_MIF), + SFR_ACCESS(PLL_CON1_PLL_LF_MIF_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_LF_MIF), + SFR_ACCESS(PLL_CON3_PLL_LF_MIF_LOCK_EN, 26, 1, PLL_CON3_PLL_LF_MIF), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_STABLE, 29, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_ICP, 6, 2, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_AFC_ENB, 20, 1, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_EXT_AFC, 0, 5, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(DBG_NFO_PLL_CPUCL0_AFC_CODE, 16, 5, DBG_NFO_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_FOUT_MASK, 25, 1, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_RSEL, 28, 4, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_BYPASS, 22, 1, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON0_PLL_CPUCL0_MUX_SEL, 4, 1, PLL_CON0_PLL_CPUCL0), + SFR_ACCESS(PLL_CON0_PLL_CPUCL0_MUX_BUSY, 16, 1, PLL_CON0_PLL_CPUCL0), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON4_PLL_CPUCL0_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_LOCK_FAIL, 27, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(DBG_NFO_PLL_CPUCL0_DEBUG_INFO, 0, 16, DBG_NFO_PLL_CPUCL0), + SFR_ACCESS(PLL_CON2_PLL_CPUCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_CPUCL0), + SFR_ACCESS(PLL_CON2_PLL_CPUCL0_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_CPUCL0), + SFR_ACCESS(PLL_CON1_PLL_CPUCL0_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_CPUCL0), + SFR_ACCESS(PLL_CON3_PLL_CPUCL0_LOCK_EN, 26, 1, PLL_CON3_PLL_CPUCL0), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_STABLE, 29, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_ICP, 6, 2, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_AFC_ENB, 20, 1, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_EXT_AFC, 0, 5, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(DBG_NFO_PLL_CPUCL1_AFC_CODE, 16, 5, DBG_NFO_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_FOUT_MASK, 25, 1, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_RSEL, 28, 4, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_BYPASS, 22, 1, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON0_PLL_CPUCL1_MUX_SEL, 4, 1, PLL_CON0_PLL_CPUCL1), + SFR_ACCESS(PLL_CON0_PLL_CPUCL1_MUX_BUSY, 16, 1, PLL_CON0_PLL_CPUCL1), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON4_PLL_CPUCL1_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_LOCK_FAIL, 27, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(DBG_NFO_PLL_CPUCL1_DEBUG_INFO, 0, 16, DBG_NFO_PLL_CPUCL1), + SFR_ACCESS(PLL_CON2_PLL_CPUCL1_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_CPUCL1), + SFR_ACCESS(PLL_CON2_PLL_CPUCL1_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_CPUCL1), + SFR_ACCESS(PLL_CON1_PLL_CPUCL1_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_CPUCL1), + SFR_ACCESS(PLL_CON3_PLL_CPUCL1_LOCK_EN, 26, 1, PLL_CON3_PLL_CPUCL1), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_ENABLE, 31, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_STABLE, 29, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_P, 8, 6, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_M, 16, 10, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_DIV_S, 0, 3, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_ICP, 6, 2, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_AFC_ENB, 20, 1, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_EXT_AFC, 0, 5, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(DBG_NFO_PLL_CPUCL2_AFC_CODE, 16, 5, DBG_NFO_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_FOUT_MASK, 25, 1, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_RSEL, 28, 4, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_BYPASS, 22, 1, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON0_PLL_CPUCL2_MUX_SEL, 4, 1, PLL_CON0_PLL_CPUCL2), + SFR_ACCESS(PLL_CON0_PLL_CPUCL2_MUX_BUSY, 16, 1, PLL_CON0_PLL_CPUCL2), + SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL2_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON4_PLL_CPUCL2_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_LOCK_FAIL, 27, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(DBG_NFO_PLL_CPUCL2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_CPUCL2), + SFR_ACCESS(PLL_CON2_PLL_CPUCL2_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_CPUCL2), + SFR_ACCESS(PLL_CON2_PLL_CPUCL2_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_CPUCL2), + SFR_ACCESS(PLL_CON1_PLL_CPUCL2_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_CPUCL2), + SFR_ACCESS(PLL_CON3_PLL_CPUCL2_LOCK_EN, 26, 1, PLL_CON3_PLL_CPUCL2), + SFR_ACCESS(PLL_CON6_PLL_CPUCL2_RESETB_REG, 31, 1, PLL_CON6_PLL_CPUCL2), + SFR_ACCESS(PLL_CON6_PLL_CPUCL2_VREG_CON, 8, 3, PLL_CON6_PLL_CPUCL2), + SFR_ACCESS(PLL_CON6_PLL_CPUCL2_VBGR_CON, 0, 8, PLL_CON6_PLL_CPUCL2), + SFR_ACCESS(PLL_CON6_PLL_CPUCL2_STABLE_REG, 29, 1, PLL_CON6_PLL_CPUCL2), + SFR_ACCESS(PLL_LOCKTIME_REG_PLL_CPUCL2_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_CPUCL2), + SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_ENABLE, 31, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_STABLE, 29, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_P, 8, 6, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_M, 16, 10, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_DIV_S, 0, 3, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_ICP, 6, 2, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_AFC_ENB, 20, 1, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_EXT_AFC, 0, 5, PLL_CON4_PLL_G3D), + SFR_ACCESS(DBG_NFO_PLL_G3D_AFC_CODE, 16, 5, DBG_NFO_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_FOUT_MASK, 25, 1, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_RSEL, 28, 4, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_BYPASS, 22, 1, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON0_PLL_G3D_MUX_SEL, 4, 1, PLL_CON0_PLL_G3D), + SFR_ACCESS(PLL_CON0_PLL_G3D_MUX_BUSY, 16, 1, PLL_CON0_PLL_G3D), + SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON4_PLL_G3D_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_LOCK_FAIL, 27, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(DBG_NFO_PLL_G3D_DEBUG_INFO, 0, 16, DBG_NFO_PLL_G3D), + SFR_ACCESS(PLL_CON2_PLL_G3D_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_G3D), + SFR_ACCESS(PLL_CON2_PLL_G3D_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_G3D), + SFR_ACCESS(PLL_CON1_PLL_G3D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_G3D), + SFR_ACCESS(PLL_CON3_PLL_G3D_LOCK_EN, 26, 1, PLL_CON3_PLL_G3D), + SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_L2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_ENABLE, 31, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_STABLE, 29, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_DIV_P, 8, 6, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_DIV_M, 16, 10, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_DIV_S, 0, 3, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_ICP, 6, 2, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_AFC_ENB, 20, 1, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_EXT_AFC, 0, 5, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(DBG_NFO_PLL_G3D_L2_AFC_CODE, 16, 5, DBG_NFO_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_FOUT_MASK, 25, 1, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_RSEL, 28, 4, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_BYPASS, 22, 1, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON0_PLL_G3D_L2_MUX_SEL, 4, 1, PLL_CON0_PLL_G3D_L2), + SFR_ACCESS(PLL_CON0_PLL_G3D_L2_MUX_BUSY, 16, 1, PLL_CON0_PLL_G3D_L2), + SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_L2_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON4_PLL_G3D_L2_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_LOCK_FAIL, 27, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(DBG_NFO_PLL_G3D_L2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_G3D_L2), + SFR_ACCESS(PLL_CON2_PLL_G3D_L2_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_G3D_L2), + SFR_ACCESS(PLL_CON2_PLL_G3D_L2_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_G3D_L2), + SFR_ACCESS(PLL_CON1_PLL_G3D_L2_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_G3D_L2), + SFR_ACCESS(PLL_CON3_PLL_G3D_L2_LOCK_EN, 26, 1, PLL_CON3_PLL_G3D_L2), + SFR_ACCESS(PLL_LOCKTIME_PLL_USB_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_ENABLE, 31, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_STABLE, 29, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_DIV_P, 8, 6, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_DIV_M, 16, 10, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_DIV_S, 0, 3, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_ICP, 6, 2, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_AFC_ENB, 20, 1, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_EXT_AFC, 0, 5, PLL_CON4_PLL_USB), + SFR_ACCESS(DBG_NFO_PLL_USB_AFC_CODE, 16, 5, DBG_NFO_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_FOUT_MASK, 25, 1, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_RSEL, 28, 4, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_BYPASS, 22, 1, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON0_PLL_USB_MUX_SEL, 4, 1, PLL_CON0_PLL_USB), + SFR_ACCESS(PLL_CON0_PLL_USB_MUX_BUSY, 16, 1, PLL_CON0_PLL_USB), + SFR_ACCESS(PLL_LOCKTIME_PLL_USB_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON4_PLL_USB_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_LOCK_FAIL, 27, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(DBG_NFO_PLL_USB_DEBUG_INFO, 0, 16, DBG_NFO_PLL_USB), + SFR_ACCESS(PLL_CON2_PLL_USB_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_USB), + SFR_ACCESS(PLL_CON2_PLL_USB_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_USB), + SFR_ACCESS(PLL_CON1_PLL_USB_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_USB), + SFR_ACCESS(PLL_CON3_PLL_USB_LOCK_EN, 26, 1, PLL_CON3_PLL_USB), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_ENABLE, 31, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_STABLE, 29, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_P, 8, 6, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_M, 16, 10, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_DIV_S, 0, 3, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_ICP, 6, 2, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_AFC_ENB, 20, 1, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_EXT_AFC, 0, 5, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(DBG_NFO_PLL_MIF_MAIN_AFC_CODE, 16, 5, DBG_NFO_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_FOUT_MASK, 25, 1, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_RSEL, 28, 4, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_BYPASS, 22, 1, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON0_PLL_MIF_MAIN_MUX_SEL, 4, 1, PLL_CON0_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON0_PLL_MIF_MAIN_MUX_BUSY, 16, 1, PLL_CON0_PLL_MIF_MAIN), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_MAIN_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON4_PLL_MIF_MAIN_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(DBG_NFO_PLL_MIF_MAIN_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON2_PLL_MIF_MAIN_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON2_PLL_MIF_MAIN_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON1_PLL_MIF_MAIN_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON3_PLL_MIF_MAIN_LOCK_EN, 26, 1, PLL_CON3_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON6_PLL_MIF_MAIN_RESETB_REG, 31, 1, PLL_CON6_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON6_PLL_MIF_MAIN_VREG_CON, 8, 3, PLL_CON6_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON6_PLL_MIF_MAIN_VBGR_CON, 0, 8, PLL_CON6_PLL_MIF_MAIN), + SFR_ACCESS(PLL_CON6_PLL_MIF_MAIN_STABLE_REG, 29, 1, PLL_CON6_PLL_MIF_MAIN), + SFR_ACCESS(PLL_LOCKTIME_REG_PLL_MIF_MAIN_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_MIF_MAIN), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_ENABLE, 31, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_STABLE, 29, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_P, 8, 6, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_M, 16, 10, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_DIV_S, 0, 3, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_ICP, 6, 2, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_AFC_ENB, 20, 1, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_EXT_AFC, 0, 5, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(DBG_NFO_PLL_MIF_SUB_AFC_CODE, 16, 5, DBG_NFO_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_FOUT_MASK, 25, 1, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_RSEL, 28, 4, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_BYPASS, 22, 1, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON0_PLL_MIF_SUB_MUX_SEL, 4, 1, PLL_CON0_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON0_PLL_MIF_SUB_MUX_BUSY, 16, 1, PLL_CON0_PLL_MIF_SUB), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_SUB_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON4_PLL_MIF_SUB_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(DBG_NFO_PLL_MIF_SUB_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON2_PLL_MIF_SUB_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON2_PLL_MIF_SUB_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON1_PLL_MIF_SUB_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON3_PLL_MIF_SUB_LOCK_EN, 26, 1, PLL_CON3_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON6_PLL_MIF_SUB_RESETB_REG, 31, 1, PLL_CON6_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON6_PLL_MIF_SUB_VREG_CON, 8, 3, PLL_CON6_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON6_PLL_MIF_SUB_VBGR_CON, 0, 8, PLL_CON6_PLL_MIF_SUB), + SFR_ACCESS(PLL_CON6_PLL_MIF_SUB_STABLE_REG, 29, 1, PLL_CON6_PLL_MIF_SUB), + SFR_ACCESS(PLL_LOCKTIME_REG_PLL_MIF_SUB_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_MIF_SUB), + SFR_ACCESS(PLL_LOCKTIME_PLL_NOCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_ENABLE, 31, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_STABLE, 29, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_DIV_P, 8, 6, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_DIV_M, 16, 10, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_DIV_S, 0, 3, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_ICP, 6, 2, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_AFC_ENB, 20, 1, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_EXT_AFC, 0, 5, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(DBG_NFO_PLL_NOCL0_AFC_CODE, 16, 5, DBG_NFO_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_FOUT_MASK, 25, 1, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_RSEL, 28, 4, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_BYPASS, 22, 1, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON0_PLL_NOCL0_MUX_SEL, 4, 1, PLL_CON0_PLL_NOCL0), + SFR_ACCESS(PLL_CON0_PLL_NOCL0_MUX_BUSY, 16, 1, PLL_CON0_PLL_NOCL0), + SFR_ACCESS(PLL_LOCKTIME_PLL_NOCL0_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON4_PLL_NOCL0_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_LOCK_FAIL, 27, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(DBG_NFO_PLL_NOCL0_DEBUG_INFO, 0, 16, DBG_NFO_PLL_NOCL0), + SFR_ACCESS(PLL_CON2_PLL_NOCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_NOCL0), + SFR_ACCESS(PLL_CON2_PLL_NOCL0_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_NOCL0), + SFR_ACCESS(PLL_CON1_PLL_NOCL0_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_NOCL0), + SFR_ACCESS(PLL_CON3_PLL_NOCL0_LOCK_EN, 26, 1, PLL_CON3_PLL_NOCL0), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_ENABLE, 31, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_STABLE, 29, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_P, 8, 6, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_M, 16, 10, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_DIV_S, 0, 3, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_ICP, 6, 2, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_AFC_ENB, 20, 1, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_EXT_AFC, 0, 5, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(DBG_NFO_PLL_MIF_S2D_AFC_CODE, 16, 5, DBG_NFO_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_FOUT_MASK, 25, 1, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_RSEL, 28, 4, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_BYPASS, 22, 1, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_MUX_SEL, 4, 1, PLL_CON0_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON0_PLL_MIF_S2D_MUX_BUSY, 16, 1, PLL_CON0_PLL_MIF_S2D), + SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_S2D_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON4_PLL_MIF_S2D_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_LOCK_FAIL, 27, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(DBG_NFO_PLL_MIF_S2D_DEBUG_INFO, 0, 16, DBG_NFO_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON2_PLL_MIF_S2D_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON2_PLL_MIF_S2D_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON1_PLL_MIF_S2D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON3_PLL_MIF_S2D_LOCK_EN, 26, 1, PLL_CON3_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON6_PLL_MIF_S2D_RESETB_REG, 31, 1, PLL_CON6_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON6_PLL_MIF_S2D_VREG_CON, 8, 3, PLL_CON6_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON6_PLL_MIF_S2D_VBGR_CON, 0, 8, PLL_CON6_PLL_MIF_S2D), + SFR_ACCESS(PLL_CON6_PLL_MIF_S2D_STABLE_REG, 29, 1, PLL_CON6_PLL_MIF_S2D), + SFR_ACCESS(PLL_LOCKTIME_REG_PLL_MIF_S2D_PLL_LOCK_TIME_REG, 0, 12, PLL_LOCKTIME_REG_PLL_MIF_S2D), + SFR_ACCESS(PLL_LOCKTIME_PLL_TPU_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_ENABLE, 31, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_STABLE, 29, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_DIV_P, 8, 6, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_DIV_M, 16, 10, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_DIV_S, 0, 3, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_ICP, 6, 2, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_LOCK_CON_IN, 12, 2, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_LOCK_CON_OUT, 14, 2, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_LOCK_CON_DLY, 8, 2, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_AFC_ENB, 20, 1, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_EXT_AFC, 0, 5, PLL_CON4_PLL_TPU), + SFR_ACCESS(DBG_NFO_PLL_TPU_AFC_CODE, 16, 5, DBG_NFO_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_FOUT_MASK, 25, 1, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_RSEL, 28, 4, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_BYPASS, 22, 1, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON0_PLL_TPU_MUX_SEL, 4, 1, PLL_CON0_PLL_TPU), + SFR_ACCESS(PLL_CON0_PLL_TPU_MUX_BUSY, 16, 1, PLL_CON0_PLL_TPU), + SFR_ACCESS(PLL_LOCKTIME_PLL_TPU_RESET_REQ_TIME, 24, 6, PLL_LOCKTIME_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_DISABLE_ALL_CLOCK_STOP, 11, 1, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON4_PLL_TPU_DISABLE_SDIV_CLOCK_STOP, 10, 1, PLL_CON4_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_USE_HW_LOCK_DET, 28, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_LOCK_FAIL, 27, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_USE_LOCK_FAIL, 30, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_ENABLE_AUTOMATIC_BYPASS, 29, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_MANUAL_PLL_CTRL, 1, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_AUTO_PLL_CTRL, 0, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(DBG_NFO_PLL_TPU_DEBUG_INFO, 0, 16, DBG_NFO_PLL_TPU), + SFR_ACCESS(PLL_CON2_PLL_TPU_ENABLE_FILTER_AUTOMATIC_CLKGATING, 31, 1, PLL_CON2_PLL_TPU), + SFR_ACCESS(PLL_CON2_PLL_TPU_FILTER_CNT_EXPIRE_VALUE, 0, 8, PLL_CON2_PLL_TPU), + SFR_ACCESS(PLL_CON1_PLL_TPU_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_PLL_TPU), + SFR_ACCESS(PLL_CON3_PLL_TPU_LOCK_EN, 26, 1, PLL_CON3_PLL_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_APM_FUNC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_APM_FUNCSRC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_APM_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUR_AUR_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUR_AUR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_AUR_AUR_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_AUR_AUR), + SFR_ACCESS(DBG_NFO_MUX_CLK_AUR_AUR_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MFC_MFC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G2D_G2D_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CSIS_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_ITP_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ITP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3AA_G3AA_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_ITSC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G2D_MSCL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HPM), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HPM_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI1_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK2_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK3_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BO_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BO_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BO_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_BO_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_BO_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CMU_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_CMU_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CMU_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MISC_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_PCIE_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_IP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_IP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_USBDPDBG_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_VRA), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PDP_VRA_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI1_PCIE_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TOP_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_IPP_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_IPP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK4_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMU_BOOST_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TNR_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TNR_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK5_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK6_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DNS_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DNS_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_GDC0_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_GDC1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPU), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_TPU_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CIS_CLK7_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_GLB), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_GLB_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_SCSC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_MISC_SSS), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MISC_SSS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_DISP_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DISP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_EH_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_EH_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_EH_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_EH_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EH_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CMU_BOOST_OPTION1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TOP_BOOST_OPTION1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TOP_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_PDP_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PDP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_UART_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_UART_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_UART), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_UART_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_NOCD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AUR), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_AUR_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_AURCTL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), + SFR_ACCESS(DBG_NFO_MUX_CLK_CPUCL0_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CPUCL0_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL0_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CPUCL0_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_CPUCL0_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL1_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CPUCL1_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_CPUCL1_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), + SFR_ACCESS(DBG_NFO_MUX_CLK_CPUCL1_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CPUCL1_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_CPUCL2_PLL), + SFR_ACCESS(DBG_NFO_MUX_CLK_CPUCL2_PLL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_CPUCL2_PLL), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CPUCL2_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CPUCL2_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_CPUCL2_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_EH_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_EH_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_EH_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_EH_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLK_EH_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_EH_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STACKS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STACKS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_STACKS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_G3D_STACKS), + SFR_ACCESS(DBG_NFO_MUX_CLK_G3D_STACKS_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_G3D_L2_GLB), + SFR_ACCESS(DBG_NFO_MUX_CLK_G3D_L2_GLB_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_TOP_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_TOP_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_TOP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_G3D_TOP), + SFR_ACCESS(DBG_NFO_MUX_CLK_G3D_TOP_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH), + SFR_ACCESS(DBG_NFO_MUX_CLK_GSACORE_CPU_HCH_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_GSACORE_CPU_HCH), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GSA_FUNC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GSA_FUNC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GSA_FUNCSRC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GSA_FUNCSRC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD), + SFR_ACCESS(DBG_NFO_MUX_CLK_HSI0_USB31DRD_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_HSI0_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLK_HSI0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_HSI0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF), + SFR_ACCESS(DBG_NFO_MUX_CLK_HSI0_USB20_REF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_HSI0_USB20_REF), + SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_MIF_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_MIF_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_MIF_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL0_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_NOCL0_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_NOCL0_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_NOCL0_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC), + SFR_ACCESS(DBG_NFO_MUX_CLK_NOCL0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_NOCL0_NOC), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1), + SFR_ACCESS(DBG_NFO_MUX_CLK_NOCL0_NOC_OPTION1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_NOCL0_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1A_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_NOCL1A_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_NOCL1A_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_NOCL1A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL1B_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_NOCL1B_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_NOCL1B_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_NOCL1B_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1), + SFR_ACCESS(DBG_NFO_MUX_CLK_NOCL1B_NOC_OPTION1_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_NOCL1B_NOC_OPTION1), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL2A_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_NOCL2A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL2A_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_NOCL2A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL2A_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_NOCL2A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_NOCL2A_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_NOCL2A_CMUREF), + SFR_ACCESS(DBG_NFO_MUX_NOCL2A_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_MUX_NOCL2A_CMUREF), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_S2D_CORE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_S2D_CORE), + SFR_ACCESS(DBG_NFO_MUX_CLK_S2D_CORE_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_S2D_CORE), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_TPU_TPU), + SFR_ACCESS(DBG_NFO_MUX_CLK_TPU_TPU_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_MUX_MUX_CLK_TPU_TPUCTL), + SFR_ACCESS(DBG_NFO_MUX_CLK_TPU_TPUCTL_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLK_TPU_TPUCTL), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_AURCTL_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_AUR_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_AUR_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BO_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BO_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BO_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BO_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_BO_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_BO_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_BO_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_CSIS_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DISP_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DISP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DNS_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DNS_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_DPU_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_DPU_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EH_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EH_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EH_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_EH_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EH_PLL_NOCL0_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G2D_G2D_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G2D_G2D_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G2D_MSCL_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3AA_G3AA_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_SWITCH_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_GLB_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G3D_GLB_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_G3D_NOCD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_SCSC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_GDC0_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_GDC_GDC1_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_USPDPDBG_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_ALT_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_USB20_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI0_TCXO_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI1_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI1_PCIE_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_PCIE_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_IPP_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_IPP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_ITP_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_ITP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_ITSC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MFC_MFC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MFC_MFC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MIF_NOCP_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER), + SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, 4, 2, PLL_CON0_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, PLL_CON0_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(DBG_NFO_CLKMUX_MIF_DDRPHY2X_DEBUG_INFO, 0, 16, DBG_NFO_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(PLL_CON1_CLKMUX_MIF_DDRPHY2X_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_CLKMUX_MIF_DDRPHY2X), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MISC_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MISC_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_MISC_SSS_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_MISC_SSS_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL0_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PDP_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PDP_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PDP_VRA_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PDP_VRA_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI6_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI3_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI4_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI5_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI14_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_I3C_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI7_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI8_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI1_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI0_UART_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC0_USI2_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI11_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI12_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI0_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_I3C_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI9_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI10_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI13_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI15_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_PERIC1_USI16_USI_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER), + SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, 4, 2, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, 16, 1, PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TNR_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TNR_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_NOC_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TPU_NOC_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_TPU_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TPU_TPU_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_UART_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(PLL_CON0_MUX_CLKCMU_TPU_UART_USER_BUSY, 16, 1, PLL_CON0_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_UART_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON1_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_UART_USER_IGNORE_REQ_SYSCLK, 5, 1, PLL_CON1_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(DBG_NFO_MUX_CLKCMU_TPU_UART_USER_DEBUG_INFO, 0, 16, DBG_NFO_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(PLL_CON1_MUX_CLKCMU_TPU_UART_USER_OVERRIDE_BY_HCH, 30, 1, PLL_CON1_MUX_CLKCMU_TPU_UART_USER), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AOC_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_AOC_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AOC_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_AOC_TRACE_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AOC_TRACE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BOOST_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_APM_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BOOST_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_BOOST_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_BOOST), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_BOOST_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_USI_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_APM_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_USI0_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_UART_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_APM_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI0_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_USI0_UART), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_USI0_UART_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI1_UART_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_APM_USI1_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI1_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_USI1_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI1_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_USI1_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_USI1_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_USI1_UART), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_USI1_UART_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_USI1_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_I3C_PMIC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_I3C_PMIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_NOC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_APM_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_APM_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_APM_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_APM_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_APM_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_APM_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_APM_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_AUR_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUR_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLK_AUR_ADD_CH_CLK), + SFR_ACCESS(DBG_NFO_CLK_AUR_ADD_CH_CLK_DEBUG_INFO, 0, 16, DBG_NFO_CLK_AUR_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_AUR_AURCTL_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUR_AURCTL_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_AUR_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUR_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BO_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BO_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BO_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BO_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BO_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BO_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BO_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_BO_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_BO_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_BO_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), + SFR_ACCESS(DBG_NFO_CLKCMU_G3D_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERIC0_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_PERIC0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MISC_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_MISC_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI1_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI1_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DPU_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_DPU_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MFC_MFC), + SFR_ACCESS(DBG_NFO_CLKCMU_MFC_MFC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G2D_G2D), + SFR_ACCESS(DBG_NFO_CLKCMU_G2D_G2D_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI0_USB31DRD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CSIS_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CSIS_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_CSIS_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERIC1_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_PERIC1_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NOCL0_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_NOCL0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_ITP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_ITP_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_ITP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3AA_G3AA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3AA_G3AA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3AA_G3AA_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G3AA_G3AA), + SFR_ACCESS(DBG_NFO_CLKCMU_G3AA_G3AA_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_ITSC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_ITSC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_ITSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MCSC_ITSC), + SFR_ACCESS(DBG_NFO_CLKCMU_MCSC_ITSC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_MSCL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G2D_MSCL), + SFR_ACCESS(DBG_NFO_CLKCMU_G2D_MSCL_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HPM), + SFR_ACCESS(DBG_NFO_CLKCMU_HPM_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_PCIE_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_PCIE_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_PCIE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI2_PCIE), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI2_PCIE_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_DBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL0_DBG_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL0_DBG), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK0_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK1_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK2_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK3_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_BO_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_BO_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_BO_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_BO_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_BO_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI2_UFS_EMBD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_DPGTC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI0_DPGTC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), + SFR_ACCESS(DBG_NFO_DIV_CLK_CMU_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CMU_CMUREF), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MIF_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MIF_NOCP), + SFR_ACCESS(DBG_NFO_CLKCMU_MIF_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERIC0_IP), + SFR_ACCESS(DBG_NFO_CLKCMU_PERIC0_IP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_IP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PERIC1_IP), + SFR_ACCESS(DBG_NFO_CLKCMU_PERIC1_IP_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TPU_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_TPU_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_VRA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_VRA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_VRA_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PDP_VRA), + SFR_ACCESS(DBG_NFO_CLKCMU_PDP_VRA_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI1_PCIE_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI1_PCIE), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI1_PCIE_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI0_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI0_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_IPP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_IPP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_IPP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_IPP_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_IPP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK4), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK4_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST), + SFR_ACCESS(DBG_NFO_DIV_CLKCMU_CMU_BOOST_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TNR_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TNR_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_TNR_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL2A_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL2A_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL2A_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_NOCL2A_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1A_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1A_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_NOCL1A_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_NOCL1B_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_NOCL1B_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK5), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK5_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK6_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK6_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK6_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK6), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK6_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK7_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK7_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK7_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CIS_CLK7), + SFR_ACCESS(DBG_NFO_CLKCMU_CIS_CLK7_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DNS_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DNS_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_DNS_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC0_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_GDC_GDC0), + SFR_ACCESS(DBG_NFO_CLKCMU_GDC_GDC0_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_GDC1_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_GDC_GDC1), + SFR_ACCESS(DBG_NFO_CLKCMU_GDC_GDC1_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MCSC_MCSC), + SFR_ACCESS(DBG_NFO_CLKCMU_MCSC_MCSC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPU_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPU_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TPU_TPU), + SFR_ACCESS(DBG_NFO_CLKCMU_TPU_TPU_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI2_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI2_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(DBG_NFO_CLKCMU_HSI2_MMC_CARD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_HSI2_MMC_CARD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_GLB_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_GLB_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_GLB_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G3D_GLB), + SFR_ACCESS(DBG_NFO_CLKCMU_G3D_GLB_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(DBG_NFO_CLKCMU_CPUCL2_SWITCH_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_SCSC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_SCSC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_GDC_SCSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_GDC_SCSC), + SFR_ACCESS(DBG_NFO_CLKCMU_GDC_SCSC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_SSS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_SSS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_MISC_SSS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_MISC_SSS), + SFR_ACCESS(DBG_NFO_CLKCMU_MISC_SSS_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_DISP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_DISP_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_DISP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_EH_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_EH_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_EH_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_EH_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_EH_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_PDP_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_PDP_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_PDP_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_UART_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_UART_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TPU_UART), + SFR_ACCESS(DBG_NFO_CLKCMU_TPU_UART_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPUCTL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPUCTL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_TPU_TPUCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(DBG_NFO_CLKCMU_TPU_TPUCTL_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV5_DIVRATIO, 0, 3, CLK_CON_DIV_PLL_SHARED0_DIV5), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV5_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV5), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV5), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV5_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED0_DIV5), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_DIV5_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0_DIV5), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_NOCD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_G3D_NOCD), + SFR_ACCESS(DBG_NFO_CLKCMU_G3D_NOCD_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AUR_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AUR_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AUR_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_AUR_AUR), + SFR_ACCESS(DBG_NFO_CLKCMU_AUR_AUR_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_NOC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_AUR_NOC), + SFR_ACCESS(DBG_NFO_CLKCMU_AUR_NOC_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AURCTL_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AURCTL_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_AUR_AURCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLKCMU_AUR_AURCTL), + SFR_ACCESS(DBG_NFO_CLKCMU_AUR_AURCTL_DEBUG_INFO, 0, 16, DBG_NFO_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED0_DIV2), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED0_DIV4), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_DIV4_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_PLL_SHARED0_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED0_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED0_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED0_DIV3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED0_DIV3), + SFR_ACCESS(DBG_NFO_PLL_SHARED0_DIV3_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED0_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED1_DIV2), + SFR_ACCESS(DBG_NFO_PLL_SHARED1_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED1_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV4_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED1_DIV4), + SFR_ACCESS(DBG_NFO_PLL_SHARED1_DIV4_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED1_DIV4), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, 0, 2, CLK_CON_DIV_PLL_SHARED1_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED1_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED1_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED1_DIV3_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED1_DIV3), + SFR_ACCESS(DBG_NFO_PLL_SHARED1_DIV3_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED1_DIV3), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED2_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED2_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED2_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED2_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED2_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED2_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED2_DIV2), + SFR_ACCESS(DBG_NFO_PLL_SHARED2_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED2_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED3_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_PLL_SHARED3_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED3_DIV2_BUSY, 16, 1, CLK_CON_DIV_PLL_SHARED3_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_PLL_SHARED3_DIV2), + SFR_ACCESS(CLK_CON_DIV_PLL_SHARED3_DIV2_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_PLL_SHARED3_DIV2), + SFR_ACCESS(DBG_NFO_PLL_SHARED3_DIV2_DEBUG_INFO, 0, 16, DBG_NFO_PLL_SHARED3_DIV2), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_ACLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_ACLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_ATCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG), + SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_PCLKDBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_PCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_PCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_DBG_ATCLK_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_DBG_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_PCLK_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_PCLK_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL1_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL1_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL2_CMUREF_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL2_CMUREF), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CSIS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CSIS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CSIS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CSIS_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CSIS_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_CSIS_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CSIS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DISP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DISP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DISP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DISP_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DISP_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_DISP_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DISP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_DNS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DNS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DNS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DNS_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DNS_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_DNS_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DNS_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_DPU_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_DPU_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_DPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_EH_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_EH_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_EH_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_EH_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_EH_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_EH_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G2D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G2D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G2D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G2D_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_G2D_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G2D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3AA_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3AA_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3AA_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3AA_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3AA_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3AA_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3AA_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3AA_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3AA_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3AA_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_NOCP), + SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO, 0, 4, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY, 16, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_CLK_G3D_ADD_CH_CLK), + SFR_ACCESS(DBG_NFO_CLK_G3D_ADD_CH_CLK_DEBUG_INFO, 0, 16, DBG_NFO_CLK_G3D_ADD_CH_CLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_TOP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_TOP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_TOP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_TOP), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_TOP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_TOP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GDC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_GDC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GDC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GDC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GDC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GDC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GDC_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GDC_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_GDC_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GDC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOCD), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_NOCD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_SPI_FPS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_SPI_FPS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_DIVRATIO, 0, 7, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_SPI_GSC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_SPI_GSC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_UART_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACORE_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_UART), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_UART_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOC_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACORE_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_NOC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_NOC), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_NOC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_NOC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACORE_CPU_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACORE_CPU_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACTRL_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACTRL_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACTRL_NOCD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACTRL_NOCD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_GSACTRL_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_GSACTRL_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI0_USB31DRD_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLK_HSI0_USB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_USB_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI0_USB), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI0_USB_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI0_USB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI0_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI0_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_HSI1_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI1_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI1_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI1_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI1_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_HSI2_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI2_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI2_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_HSI2_NOC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_HSI2_NOC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IPP_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_IPP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IPP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IPP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IPP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IPP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IPP_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_IPP_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_IPP_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_IPP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ITP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ITP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ITP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ITP_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_ITP_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_ITP_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_ITP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MCSC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MCSC_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MCSC_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_MCSC_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MCSC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MFC_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_MFC_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MFC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_MIF_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MIF_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_MIF_NOCD_DBG_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MIF_NOCD_DBG_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MISC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_MISC_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MISC_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MISC_GIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC), + SFR_ACCESS(DBG_NFO_DIV_CLK_MISC_GIC_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MISC_GIC), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MISC_GIC_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_MISC_GIC_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MISC_GIC_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_MISC_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_MISC_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL0_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL0_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC_DCLK_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_SLC_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC_DCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SLC_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SLC_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC_DCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_SLC_DCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_SLC_DCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_SLC_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC1_DCLK_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_SLC1_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC1_DCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SLC1_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC1_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SLC1_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC1_DCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_SLC1_DCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_SLC1_DCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_SLC1_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC2_DCLK_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_SLC2_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC2_DCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SLC2_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC2_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SLC2_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC2_DCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_SLC2_DCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_SLC2_DCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_SLC2_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC3_DCLK_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_SLC3_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC3_DCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SLC3_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC3_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SLC3_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SLC3_DCLK_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_SLC3_DCLK), + SFR_ACCESS(DBG_NFO_DIV_CLK_SLC3_DCLK_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_SLC3_DCLK), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL0_NOCD_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL0_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL0_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1A_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1A_NOCD_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1A_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1B_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1B_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1B_NOCD_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1B_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL1B_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL1B_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL2A_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL2A_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL2A_NOCD_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL2A_NOCD_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_NOCL2A_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_NOCL2A_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PDP_NOCP_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PDP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PDP_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PDP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PDP_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PDP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PDP_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PDP_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_PDP_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PDP_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI6_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI6_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI3_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI3_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI4_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI4_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI5_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI5_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI14_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI14_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I3C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I3C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_I3C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_I3C), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_I3C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI7_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI7_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI8_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI8_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI1_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI1_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI0_UART_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI0_UART), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_USI2_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_USI2_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC0_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC0_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI11_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI11_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I3C_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I3C_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I3C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_I3C_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_I3C), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_I3C_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_I3C), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI12_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI12_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI0_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI0_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI9_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI9_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI10_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI10_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI13_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI13_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI15_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI15_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI), + SFR_ACCESS(DBG_NFO_DIV_CLK_PERIC1_USI16_USI_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_PERIC1_USI16_USI), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_S2D_CORE_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_S2D_CORE_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_S2D_CORE_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TNR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TNR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TNR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TNR_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TNR_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_TNR_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TNR_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP), + SFR_ACCESS(DBG_NFO_DIV_CLK_TPU_NOCP_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TPU_NOCP), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG), + SFR_ACCESS(DBG_NFO_DIV_CLK_TPU_TPUCTL_DBG_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TPU_TPUCTL_DBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH), + SFR_ACCESS(DBG_NFO_DIV_CLK_TPU_NOCP_LH_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TPU_NOCP_LH), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AUR_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_AUR_AUR_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_AUR_AUR), + SFR_ACCESS(DBG_NFO_DIV_CLK_AUR_AUR_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_AUR_AUR), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL0_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL0_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL1_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL1_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_CPUCL2_CPU), + SFR_ACCESS(DBG_NFO_DIV_CLK_CPUCL2_CPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_CPUCL2_CPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_STACKS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_STACKS_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_STACKS), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_STACKS_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_STACKS), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_G3D_L2_GLB), + SFR_ACCESS(DBG_NFO_DIV_CLK_G3D_L2_GLB_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_G3D_L2_GLB), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPU_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TPU_TPU), + SFR_ACCESS(DBG_NFO_DIV_CLK_TPU_TPU_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TPU_TPU), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_OVERRIDE_BY_HCH, 30, 1, CLK_CON_DIV_DIV_CLK_TPU_TPUCTL), + SFR_ACCESS(DBG_NFO_DIV_CLK_TPU_TPUCTL_DEBUG_INFO, 0, 16, DBG_NFO_DIV_CLK_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_FUNC), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_MANUAL, 20, 1, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_MANUAL, 20, 1, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_MANUAL, 20, 1, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_CMU_BOOST_OPTION1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_MFC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ITP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BO_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BO_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BO_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_VRA), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IPP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TNR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CPUCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CPUCL1_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_NOCL1B_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_NOCL2A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_NOCL1A_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL0_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_NOCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL0_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_NOCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_NOCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_NOCL0_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_BOOST), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DNS_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPU), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_GLB), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST), + SFR_ACCESS(CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_CPUCL2_BOOST), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MISC_SSS), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DISP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_EH_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_EH_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_EH_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PDP_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_UART_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_UART_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_UART), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AUR), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_NOC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_GSACORE_CG_VAL, 21, 1, CLK_CON_GAT_CLK_GSACORE), + SFR_ACCESS(CLK_CON_GAT_CLK_GSACORE_MANUAL, 20, 1, CLK_CON_GAT_CLK_GSACORE), + SFR_ACCESS(CLK_CON_GAT_CLK_GSACORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_GSACORE), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSA_FUNC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_GSA_FUNC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSA_FUNC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_GSA_FUNC), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_GSA_FUNC), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE), + SFR_ACCESS(CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_GSACTRL2CORE), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26), + SFR_ACCESS(CLK_CON_GAT_CLK_HSI0_ALT_CG_VAL, 21, 1, CLK_CON_GAT_CLK_HSI0_ALT), + SFR_ACCESS(CLK_CON_GAT_CLK_HSI0_ALT_MANUAL, 20, 1, CLK_CON_GAT_CLK_HSI0_ALT), + SFR_ACCESS(CLK_CON_GAT_CLK_HSI0_ALT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_HSI0_ALT), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP), + SFR_ACCESS(CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG), + SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_NOCD), + SFR_ACCESS(CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_NOCD_S2D), + SFR_ACCESS(QCH_CON_AOC_CMU_AOC_QCH_ENABLE, 0, 1, QCH_CON_AOC_CMU_AOC_QCH), + SFR_ACCESS(QCH_CON_AOC_CMU_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_AOC_CMU_AOC_QCH), + SFR_ACCESS(QCH_CON_AOC_CMU_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AOC_CMU_AOC_QCH), + SFR_ACCESS(QCH_CON_AOC_CMU_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AOC_CMU_AOC_QCH), + SFR_ACCESS(QCH_CON_AOC_SYSCTRL_APB_QCH_ENABLE, 0, 1, QCH_CON_AOC_SYSCTRL_APB_QCH), + SFR_ACCESS(QCH_CON_AOC_SYSCTRL_APB_QCH_CLOCK_REQ, 1, 1, QCH_CON_AOC_SYSCTRL_APB_QCH), + SFR_ACCESS(QCH_CON_AOC_SYSCTRL_APB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AOC_SYSCTRL_APB_QCH), + SFR_ACCESS(QCH_CON_AOC_SYSCTRL_APB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AOC_SYSCTRL_APB_QCH), + SFR_ACCESS(QCH_CON_BAAW_AOC_QCH_ENABLE, 0, 1, QCH_CON_BAAW_AOC_QCH), + SFR_ACCESS(QCH_CON_BAAW_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_AOC_QCH), + SFR_ACCESS(QCH_CON_BAAW_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_AOC_QCH), + SFR_ACCESS(QCH_CON_BAAW_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_AOC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AOC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_AOC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_AOC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_AOC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_AOC_QCH), + SFR_ACCESS(QCH_CON_GPC_AOC_QCH_ENABLE, 0, 1, QCH_CON_GPC_AOC_QCH), + SFR_ACCESS(QCH_CON_GPC_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_AOC_QCH), + SFR_ACCESS(QCH_CON_GPC_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_AOC_QCH), + SFR_ACCESS(QCH_CON_GPC_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_PPMU_AOC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_USB_QCH_ENABLE, 0, 1, QCH_CON_PPMU_USB_QCH), + SFR_ACCESS(QCH_CON_PPMU_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_USB_QCH), + SFR_ACCESS(QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_USB_QCH), + SFR_ACCESS(QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_USB_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LG_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LG_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LG_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LG_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SSMT_AOC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_AOC_QCH), + SFR_ACCESS(QCH_CON_SSMT_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_AOC_QCH), + SFR_ACCESS(QCH_CON_SSMT_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_AOC_QCH), + SFR_ACCESS(QCH_CON_SSMT_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_AOC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_AOC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AOC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AOC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AOC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_AOC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_AOC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_AOC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_AOC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_AOC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_AOC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AOC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AOC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_AOC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_AOC_QCH_ENABLE, 0, 1, QCH_CON_UASC_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_AOC_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE, 0, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH), + SFR_ACCESS(QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH), + SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_APBIF_PMU_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_PMU_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_PMU_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_PMU_ALIVE_QCH), + SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_RTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_RTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_RTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_RTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_TRTC_QCH_ENABLE, 0, 1, QCH_CON_APBIF_TRTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_TRTC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_TRTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_TRTC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_TRTC_QCH), + SFR_ACCESS(QCH_CON_APBIF_TRTC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_TRTC_QCH), + SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_ENABLE, 0, 1, QCH_CON_APM_CMU_APM_QCH), + SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_CMU_APM_QCH), + SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_CMU_APM_QCH), + SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_CMU_APM_QCH), + SFR_ACCESS(QCH_CON_APM_I3C_PMIC_QCH_P_ENABLE, 0, 1, QCH_CON_APM_I3C_PMIC_QCH_P), + SFR_ACCESS(QCH_CON_APM_I3C_PMIC_QCH_P_CLOCK_REQ, 1, 1, QCH_CON_APM_I3C_PMIC_QCH_P), + SFR_ACCESS(QCH_CON_APM_I3C_PMIC_QCH_P_EXPIRE_VAL, 16, 10, QCH_CON_APM_I3C_PMIC_QCH_P), + SFR_ACCESS(QCH_CON_APM_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_I3C_PMIC_QCH_P), + SFR_ACCESS(DMYQCH_CON_APM_I3C_PMIC_QCH_S_ENABLE, 0, 1, DMYQCH_CON_APM_I3C_PMIC_QCH_S), + SFR_ACCESS(DMYQCH_CON_APM_I3C_PMIC_QCH_S_CLOCK_REQ, 1, 1, DMYQCH_CON_APM_I3C_PMIC_QCH_S), + SFR_ACCESS(DMYQCH_CON_APM_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_APM_I3C_PMIC_QCH_S), + SFR_ACCESS(QCH_CON_APM_USI0_UART_QCH_ENABLE, 0, 1, QCH_CON_APM_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_USI_QCH_ENABLE, 0, 1, QCH_CON_APM_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_APM_USI0_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_APM_USI1_UART_QCH_ENABLE, 0, 1, QCH_CON_APM_USI1_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI1_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_USI1_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI1_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_USI1_UART_QCH), + SFR_ACCESS(QCH_CON_APM_USI1_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APM_USI1_UART_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_APM_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_APM_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_APM_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_APM_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_APM_QCH), + SFR_ACCESS(QCH_CON_GPC_APM_QCH_ENABLE, 0, 1, QCH_CON_GPC_APM_QCH), + SFR_ACCESS(QCH_CON_GPC_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_APM_QCH), + SFR_ACCESS(QCH_CON_GPC_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_APM_QCH), + SFR_ACCESS(QCH_CON_GPC_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_APM_QCH), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_GREBE), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_GREBE), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, 0, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_GREBEINTEGRATION_QCH_DBG), + SFR_ACCESS(QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GREBEINTEGRATION_QCH_DBG), + SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH), + SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH), + SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH), + SFR_ACCESS(QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_SWD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_SWD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_SWD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_SWD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AOC_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AP_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AP_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_AP_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AP_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AUR_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_GSA_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_GSA_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_GSA_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_GSA_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_GSA_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_SWD_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_SWD_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_SWD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_SWD_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_SWD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_SWD_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_SWD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_SWD_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_TPU_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM_TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM_TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM_TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_APM_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_APM_TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCA32_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AOCA32_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCA32_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AOCA32_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCA32_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AOCA32_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCA32_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AOCA32_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCF1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AOCF1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AOCF1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AOCF1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AOCF1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCP6_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AOCP6_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCP6_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AOCP6_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCP6_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AOCP6_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AOCP6_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AOCP6_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR0_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AUR0_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR0_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AUR0_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AUR0_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AUR0_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR1_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AUR1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AUR1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AUR1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AUR1_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR2_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AUR2_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR2_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AUR2_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AUR2_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AUR2_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR3_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_AUR3_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR3_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_AUR3_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_AUR3_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_AUR3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_AUR3_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_AP_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_AP_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_ENABLE, 0, 1, QCH_CON_PMU_INTR_GEN_QCH), + SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_INTR_GEN_QCH), + SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_INTR_GEN_QCH), + SFR_ACCESS(QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_INTR_GEN_QCH), + SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, 0, 1, QCH_CON_ROM_CRC32_HOST_QCH), + SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, 1, 1, QCH_CON_ROM_CRC32_HOST_QCH), + SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ROM_CRC32_HOST_QCH), + SFR_ACCESS(QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ROM_CRC32_HOST_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SSMT_D_APM_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D_APM_QCH), + SFR_ACCESS(QCH_CON_SSMT_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D_APM_QCH), + SFR_ACCESS(QCH_CON_SSMT_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D_APM_QCH), + SFR_ACCESS(QCH_CON_SSMT_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D_APM_QCH), + SFR_ACCESS(QCH_CON_SSMT_LG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SSMT_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_LG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_LG_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_GREBE), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_GREBE), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_GREBE), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_GREBE), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, 0, 1, QCH_CON_SS_DBGCORE_QCH_DBG), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_SS_DBGCORE_QCH_DBG), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_SS_DBGCORE_QCH_DBG), + SFR_ACCESS(QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SS_DBGCORE_QCH_DBG), + SFR_ACCESS(QCH_CON_SYSMMU_D_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_D_APM_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D_APM_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D_APM_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D_APM_QCH), + SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_APM_QCH), + SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_APM_QCH), + SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_APM_QCH), + SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_APM_QCH), + SFR_ACCESS(QCH_CON_UASC_APM_QCH_ENABLE, 0, 1, QCH_CON_UASC_APM_QCH), + SFR_ACCESS(QCH_CON_UASC_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_APM_QCH), + SFR_ACCESS(QCH_CON_UASC_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_APM_QCH), + SFR_ACCESS(QCH_CON_UASC_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_APM_QCH), + SFR_ACCESS(QCH_CON_UASC_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_UASC_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_UASC_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_UASC_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_UASC_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_UASC_IG_SWD_QCH_ENABLE, 0, 1, QCH_CON_UASC_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_UASC_IG_SWD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_UASC_IG_SWD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_UASC_IG_SWD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_IG_SWD_QCH), + SFR_ACCESS(QCH_CON_UASC_LP0_AOC_QCH_ENABLE, 0, 1, QCH_CON_UASC_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_LP0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_LP0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_LP0_AOC_QCH), + SFR_ACCESS(QCH_CON_UASC_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_UASC_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_UASC_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_UASC_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_UASC_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_WDT_APM_QCH_ENABLE, 0, 1, QCH_CON_WDT_APM_QCH), + SFR_ACCESS(QCH_CON_WDT_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_APM_QCH), + SFR_ACCESS(QCH_CON_WDT_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_APM_QCH), + SFR_ACCESS(QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_APM_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_AUR_QCH_ENABLE, 0, 1, QCH_CON_ADD_APBIF_AUR_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADD_APBIF_AUR_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADD_APBIF_AUR_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADD_APBIF_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_AUR_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_AUR_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_AUR_QCH_ENABLE, 0, 1, DMYQCH_CON_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_AUR_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_AUR_QCH), + SFR_ACCESS(QCH_CON_AUR_CMU_AUR_QCH_ENABLE, 0, 1, QCH_CON_AUR_CMU_AUR_QCH), + SFR_ACCESS(QCH_CON_AUR_CMU_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_AUR_CMU_AUR_QCH), + SFR_ACCESS(QCH_CON_AUR_CMU_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_AUR_CMU_AUR_QCH), + SFR_ACCESS(QCH_CON_AUR_CMU_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_AUR_CMU_AUR_QCH), + SFR_ACCESS(QCH_CON_BAAW_AUR_QCH_ENABLE, 0, 1, QCH_CON_BAAW_AUR_QCH), + SFR_ACCESS(QCH_CON_BAAW_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_AUR_QCH), + SFR_ACCESS(QCH_CON_BAAW_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_AUR_QCH), + SFR_ACCESS(QCH_CON_BAAW_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_AUR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AUR_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_AUR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_AUR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_AUR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_AUR_QCH), + SFR_ACCESS(QCH_CON_GPC_AUR_QCH_ENABLE, 0, 1, QCH_CON_GPC_AUR_QCH), + SFR_ACCESS(QCH_CON_GPC_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_AUR_QCH), + SFR_ACCESS(QCH_CON_GPC_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_AUR_QCH), + SFR_ACCESS(QCH_CON_GPC_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_AUR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_AUR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_AUR_CU_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_AUR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_AUR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_AUR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_AUR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_AUR_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_AUR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_AUR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_AUR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_AUR_QCH), + SFR_ACCESS(QCH_CON_UASC_AUR_QCH_ENABLE, 0, 1, QCH_CON_UASC_AUR_QCH), + SFR_ACCESS(QCH_CON_UASC_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_AUR_QCH), + SFR_ACCESS(QCH_CON_UASC_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_AUR_QCH), + SFR_ACCESS(QCH_CON_UASC_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_AUR_QCH), + SFR_ACCESS(DMYQCH_CON_BO_QCH_ENABLE, 0, 1, DMYQCH_CON_BO_QCH), + SFR_ACCESS(DMYQCH_CON_BO_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_BO_QCH), + SFR_ACCESS(DMYQCH_CON_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_BO_QCH), + SFR_ACCESS(QCH_CON_BO_CMU_BO_QCH_ENABLE, 0, 1, QCH_CON_BO_CMU_BO_QCH), + SFR_ACCESS(QCH_CON_BO_CMU_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_BO_CMU_BO_QCH), + SFR_ACCESS(QCH_CON_BO_CMU_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BO_CMU_BO_QCH), + SFR_ACCESS(QCH_CON_BO_CMU_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BO_CMU_BO_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_BO_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_BO_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_BO_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_BO_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_BO_QCH), + SFR_ACCESS(QCH_CON_GPC_BO_QCH_ENABLE, 0, 1, QCH_CON_GPC_BO_QCH), + SFR_ACCESS(QCH_CON_GPC_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_BO_QCH), + SFR_ACCESS(QCH_CON_GPC_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_BO_QCH), + SFR_ACCESS(QCH_CON_GPC_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_BO_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_BO_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_BO_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_BO_QCH), + SFR_ACCESS(QCH_CON_PPMU_BO_QCH_ENABLE, 0, 1, QCH_CON_PPMU_BO_QCH), + SFR_ACCESS(QCH_CON_PPMU_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_BO_QCH), + SFR_ACCESS(QCH_CON_PPMU_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_BO_QCH), + SFR_ACCESS(QCH_CON_PPMU_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BO_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SSMT_BO_QCH_ENABLE, 0, 1, QCH_CON_SSMT_BO_QCH), + SFR_ACCESS(QCH_CON_SSMT_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_BO_QCH), + SFR_ACCESS(QCH_CON_SSMT_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_BO_QCH), + SFR_ACCESS(QCH_CON_SSMT_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_BO_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_BO_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_BO_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_BO_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_BO_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_BO_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_BO_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_BO_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_BO_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_BO_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_BO_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BO_QCH), + SFR_ACCESS(QCH_CON_SYSREG_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BO_QCH), + SFR_ACCESS(QCH_CON_SYSREG_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BO_QCH), + SFR_ACCESS(QCH_CON_SYSREG_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_BO_QCH), + SFR_ACCESS(QCH_CON_UASC_BO_QCH_ENABLE, 0, 1, QCH_CON_UASC_BO_QCH), + SFR_ACCESS(QCH_CON_UASC_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_BO_QCH), + SFR_ACCESS(QCH_CON_UASC_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_BO_QCH), + SFR_ACCESS(QCH_CON_UASC_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_BO_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_TOP_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7), + SFR_ACCESS(DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7), + SFR_ACCESS(DMYQCH_CON_OTP_QCH_ENABLE, 0, 1, DMYQCH_CON_OTP_QCH), + SFR_ACCESS(DMYQCH_CON_OTP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_OTP_QCH), + SFR_ACCESS(DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_OTP_QCH), + SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, 0, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH), + SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH), + SFR_ACCESS(DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BPS_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BPS_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BPS_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BPS_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_SCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_SCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_SCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_SCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_ATCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_ATCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_ATCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_ATCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_GIC), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_GIC), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_GIC), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_GIC), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK), + SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK), + SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_DBG_PD), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_DBG_PD), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, 16, 4, QCH_CON_CLUSTER0_QCH_DBG_PD), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_DBG_PD), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_PDBGCLK), + SFR_ACCESS(QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CLUSTER0_QCH_PDBGCLK), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_CSSYS_QCH), + SFR_ACCESS(QCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSSYS_QCH), + SFR_ACCESS(QCH_CON_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSSYS_QCH), + SFR_ACCESS(QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSSYS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_GPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_HPM_APBIF_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_HPM_APBIF_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_HPM_APBIF_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HPM_APBIF_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_HPM_APBIF_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HPM_APBIF_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_HPM_APBIF_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HPM_APBIF_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_BDU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_SLC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_STM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_STM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IG_CSSYS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IG_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_STM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_STM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_STM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IG_STM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SSMT_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SSMT_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SSMT_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SSMT_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_S2_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_S2_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_S2_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_S2_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_S2_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_S2_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_S2_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_S2_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CPUCL0_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), + SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_MID_ENABLE, 0, 1, DMYQCH_CON_CPUCL1_QCH_MID), + SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_MID_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL1_QCH_MID), + SFR_ACCESS(DMYQCH_CON_CPUCL1_QCH_MID_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL1_QCH_MID), + SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), + SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), + SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), + SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH), + SFR_ACCESS(QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH), + SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_BIG_ENABLE, 0, 1, DMYQCH_CON_CPUCL2_QCH_BIG), + SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_BIG_CLOCK_REQ, 1, 1, DMYQCH_CON_CPUCL2_QCH_BIG), + SFR_ACCESS(DMYQCH_CON_CPUCL2_QCH_BIG_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CPUCL2_QCH_BIG), + SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, 0, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH), + SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH), + SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL2_CMU_CPUCL2_QCH), + SFR_ACCESS(QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPUCL2_CMU_CPUCL2_QCH), + SFR_ACCESS(QCH_CON_CSISX8_QCH_C2_CSIS_ENABLE, 0, 1, QCH_CON_CSISX8_QCH_C2_CSIS), + SFR_ACCESS(QCH_CON_CSISX8_QCH_C2_CSIS_CLOCK_REQ, 1, 1, QCH_CON_CSISX8_QCH_C2_CSIS), + SFR_ACCESS(QCH_CON_CSISX8_QCH_C2_CSIS_EXPIRE_VAL, 16, 10, QCH_CON_CSISX8_QCH_C2_CSIS), + SFR_ACCESS(QCH_CON_CSISX8_QCH_C2_CSIS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX8_QCH_C2_CSIS), + SFR_ACCESS(QCH_CON_CSISX8_QCH_CSIS_DMA_ENABLE, 0, 1, QCH_CON_CSISX8_QCH_CSIS_DMA), + SFR_ACCESS(QCH_CON_CSISX8_QCH_CSIS_DMA_CLOCK_REQ, 1, 1, QCH_CON_CSISX8_QCH_CSIS_DMA), + SFR_ACCESS(QCH_CON_CSISX8_QCH_CSIS_DMA_EXPIRE_VAL, 16, 10, QCH_CON_CSISX8_QCH_CSIS_DMA), + SFR_ACCESS(QCH_CON_CSISX8_QCH_CSIS_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX8_QCH_CSIS_DMA), + SFR_ACCESS(QCH_CON_CSISX8_QCH_EBUF_ENABLE, 0, 1, QCH_CON_CSISX8_QCH_EBUF), + SFR_ACCESS(QCH_CON_CSISX8_QCH_EBUF_CLOCK_REQ, 1, 1, QCH_CON_CSISX8_QCH_EBUF), + SFR_ACCESS(QCH_CON_CSISX8_QCH_EBUF_EXPIRE_VAL, 16, 10, QCH_CON_CSISX8_QCH_EBUF), + SFR_ACCESS(QCH_CON_CSISX8_QCH_EBUF_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSISX8_QCH_EBUF), + SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, 0, 1, QCH_CON_CSIS_CMU_CSIS_QCH), + SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSIS_CMU_CSIS_QCH), + SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSIS_CMU_CSIS_QCH), + SFR_ACCESS(QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CSIS_CMU_CSIS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_GPC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_GPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_GPC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_GPC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_GPC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_ENABLE, 0, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_CLOCK_REQ, 1, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_EXPIRE_VAL, 16, 10, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7), + SFR_ACCESS(QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7), + SFR_ACCESS(QCH_CON_PPMU_D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA0_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA0_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA0_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA0_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA1_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA1_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA1_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA1_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA2_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA2_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA2_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA2_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, 0, 1, QCH_CON_QE_CSIS_DMA3_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CSIS_DMA3_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CSIS_DMA3_QCH), + SFR_ACCESS(QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CSIS_DMA3_QCH), + SFR_ACCESS(QCH_CON_QE_STRP0_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP0_QCH), + SFR_ACCESS(QCH_CON_QE_STRP0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP0_QCH), + SFR_ACCESS(QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP0_QCH), + SFR_ACCESS(QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP0_QCH), + SFR_ACCESS(QCH_CON_QE_STRP1_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP1_QCH), + SFR_ACCESS(QCH_CON_QE_STRP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP1_QCH), + SFR_ACCESS(QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP1_QCH), + SFR_ACCESS(QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP1_QCH), + SFR_ACCESS(QCH_CON_QE_STRP2_QCH_ENABLE, 0, 1, QCH_CON_QE_STRP2_QCH), + SFR_ACCESS(QCH_CON_QE_STRP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_STRP2_QCH), + SFR_ACCESS(QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_STRP2_QCH), + SFR_ACCESS(QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_STRP2_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL0_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL0_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL0_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL0_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL1_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL1_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL1_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL1_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_ENABLE, 0, 1, QCH_CON_QE_ZSL2_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ZSL2_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ZSL2_QCH), + SFR_ACCESS(QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ZSL2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_CSIS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CSIS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CSIS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CSIS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_CSIS_QCH), + SFR_ACCESS(QCH_CON_DISP_CMU_DISP_QCH_ENABLE, 0, 1, QCH_CON_DISP_CMU_DISP_QCH), + SFR_ACCESS(QCH_CON_DISP_CMU_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DISP_CMU_DISP_QCH), + SFR_ACCESS(QCH_CON_DISP_CMU_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DISP_CMU_DISP_QCH), + SFR_ACCESS(QCH_CON_DISP_CMU_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DISP_CMU_DISP_QCH), + SFR_ACCESS(QCH_CON_DPUB_QCH_ENABLE, 0, 1, QCH_CON_DPUB_QCH), + SFR_ACCESS(QCH_CON_DPUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPUB_QCH), + SFR_ACCESS(QCH_CON_DPUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPUB_QCH), + SFR_ACCESS(QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUB_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DISP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DISP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DISP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DISP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DISP_QCH), + SFR_ACCESS(QCH_CON_GPC_DISP_QCH_ENABLE, 0, 1, QCH_CON_GPC_DISP_QCH), + SFR_ACCESS(QCH_CON_GPC_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_DISP_QCH), + SFR_ACCESS(QCH_CON_GPC_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_DISP_QCH), + SFR_ACCESS(QCH_CON_GPC_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DISP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DISP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DISP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DISP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DISP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DISP_QCH), + SFR_ACCESS(QCH_CON_DNS_QCH_00_ENABLE, 0, 1, QCH_CON_DNS_QCH_00), + SFR_ACCESS(QCH_CON_DNS_QCH_00_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH_00), + SFR_ACCESS(QCH_CON_DNS_QCH_00_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH_00), + SFR_ACCESS(QCH_CON_DNS_QCH_00_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH_00), + SFR_ACCESS(QCH_CON_DNS_QCH_01_ENABLE, 0, 1, QCH_CON_DNS_QCH_01), + SFR_ACCESS(QCH_CON_DNS_QCH_01_CLOCK_REQ, 1, 1, QCH_CON_DNS_QCH_01), + SFR_ACCESS(QCH_CON_DNS_QCH_01_EXPIRE_VAL, 16, 10, QCH_CON_DNS_QCH_01), + SFR_ACCESS(QCH_CON_DNS_QCH_01_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_QCH_01), + SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_ENABLE, 0, 1, QCH_CON_DNS_CMU_DNS_QCH), + SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_DNS_CMU_DNS_QCH), + SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DNS_CMU_DNS_QCH), + SFR_ACCESS(QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DNS_CMU_DNS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DNS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DNS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DNS_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DNS_QCH), + SFR_ACCESS(QCH_CON_GPC_DNS_QCH_ENABLE, 0, 1, QCH_CON_GPC_DNS_QCH), + SFR_ACCESS(QCH_CON_GPC_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_DNS_QCH), + SFR_ACCESS(QCH_CON_GPC_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_DNS_QCH), + SFR_ACCESS(QCH_CON_GPC_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_QE_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_DNS_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_DNS_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_DNS_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DNS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DNS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DNS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DNS_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DNS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DNS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DNS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DNS_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DNS_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DNS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DNS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DNS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DNS_QCH), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DMA_ENABLE, 0, 1, QCH_CON_DPUF_QCH_DPU_DMA), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DMA_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_DPU_DMA), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DMA_EXPIRE_VAL, 16, 10, QCH_CON_DPUF_QCH_DPU_DMA), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DMA_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_DPU_DMA), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DPP_ENABLE, 0, 1, QCH_CON_DPUF_QCH_DPU_DPP), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DPP_CLOCK_REQ, 1, 1, QCH_CON_DPUF_QCH_DPU_DPP), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DPP_EXPIRE_VAL, 16, 10, QCH_CON_DPUF_QCH_DPU_DPP), + SFR_ACCESS(QCH_CON_DPUF_QCH_DPU_DPP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPUF_QCH_DPU_DPP), + SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_ENABLE, 0, 1, QCH_CON_DPU_CMU_DPU_QCH), + SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU_CMU_DPU_QCH), + SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU_CMU_DPU_QCH), + SFR_ACCESS(QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DPU_CMU_DPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_DPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_DPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_DPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_DPU_QCH), + SFR_ACCESS(QCH_CON_GPC_DPU_QCH_ENABLE, 0, 1, QCH_CON_GPC_DPU_QCH), + SFR_ACCESS(QCH_CON_GPC_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_DPU_QCH), + SFR_ACCESS(QCH_CON_GPC_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_DPU_QCH), + SFR_ACCESS(QCH_CON_GPC_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD0_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD0_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD0_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD0_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD1_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD1_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD1_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD1_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_DPUD2_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_DPUD2_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_DPUD2_QCH), + SFR_ACCESS(QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_DPUD2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_DPU0_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_DPU0_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_DPU0_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_DPU0_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_DPU1_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_DPU1_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_DPU1_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_DPU1_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU2_QCH_ENABLE, 0, 1, QCH_CON_SSMT_DPU2_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_DPU2_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_DPU2_QCH), + SFR_ACCESS(QCH_CON_SSMT_DPU2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_DPU2_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD0_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD0_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD0_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD0_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD0_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD0_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD0_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD0_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_DPUD2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_DPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_EH_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_EH_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_EH_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_EH_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_EH_QCH), + SFR_ACCESS(QCH_CON_EH_QCH_ENABLE, 0, 1, QCH_CON_EH_QCH), + SFR_ACCESS(QCH_CON_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_EH_QCH), + SFR_ACCESS(QCH_CON_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_EH_QCH), + SFR_ACCESS(QCH_CON_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_EH_QCH), + SFR_ACCESS(QCH_CON_EH_CMU_EH_QCH_ENABLE, 0, 1, QCH_CON_EH_CMU_EH_QCH), + SFR_ACCESS(QCH_CON_EH_CMU_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_EH_CMU_EH_QCH), + SFR_ACCESS(QCH_CON_EH_CMU_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_EH_CMU_EH_QCH), + SFR_ACCESS(QCH_CON_EH_CMU_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_EH_CMU_EH_QCH), + SFR_ACCESS(QCH_CON_GPC_EH_QCH_ENABLE, 0, 1, QCH_CON_GPC_EH_QCH), + SFR_ACCESS(QCH_CON_GPC_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_EH_QCH), + SFR_ACCESS(QCH_CON_GPC_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_EH_QCH), + SFR_ACCESS(QCH_CON_GPC_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_EH_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_EH_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_EH_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_EH_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_EH_CU_QCH), + SFR_ACCESS(QCH_CON_PPMU_EH_QCH_ENABLE, 0, 1, QCH_CON_PPMU_EH_QCH), + SFR_ACCESS(QCH_CON_PPMU_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_EH_QCH), + SFR_ACCESS(QCH_CON_PPMU_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_EH_QCH), + SFR_ACCESS(QCH_CON_PPMU_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_EH_QCH), + SFR_ACCESS(QCH_CON_QE_EH_QCH_ENABLE, 0, 1, QCH_CON_QE_EH_QCH), + SFR_ACCESS(QCH_CON_QE_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_EH_QCH), + SFR_ACCESS(QCH_CON_QE_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_EH_QCH), + SFR_ACCESS(QCH_CON_QE_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_EH_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SSMT_EH_QCH_ENABLE, 0, 1, QCH_CON_SSMT_EH_QCH), + SFR_ACCESS(QCH_CON_SSMT_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_EH_QCH), + SFR_ACCESS(QCH_CON_SSMT_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_EH_QCH), + SFR_ACCESS(QCH_CON_SSMT_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_EH_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_EH_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_EH_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_EH_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_EH_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_EH_QCH), + SFR_ACCESS(QCH_CON_SYSREG_EH_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_EH_QCH), + SFR_ACCESS(QCH_CON_SYSREG_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_EH_QCH), + SFR_ACCESS(QCH_CON_SYSREG_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_EH_QCH), + SFR_ACCESS(QCH_CON_SYSREG_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_EH_QCH), + SFR_ACCESS(QCH_CON_UASC_EH_QCH_ENABLE, 0, 1, QCH_CON_UASC_EH_QCH), + SFR_ACCESS(QCH_CON_UASC_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_EH_QCH), + SFR_ACCESS(QCH_CON_UASC_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_EH_QCH), + SFR_ACCESS(QCH_CON_UASC_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_EH_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G2D_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G2D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G2D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_G2D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_CMU_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_CMU_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_CMU_G2D_QCH), + SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G2D_CMU_G2D_QCH), + SFR_ACCESS(QCH_CON_GPC_G2D_QCH_ENABLE, 0, 1, QCH_CON_GPC_G2D_QCH), + SFR_ACCESS(QCH_CON_GPC_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_G2D_QCH), + SFR_ACCESS(QCH_CON_GPC_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_G2D_QCH), + SFR_ACCESS(QCH_CON_GPC_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_G2D_QCH), + SFR_ACCESS(QCH_CON_JPEG_QCH_ENABLE, 0, 1, QCH_CON_JPEG_QCH), + SFR_ACCESS(QCH_CON_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG_QCH), + SFR_ACCESS(QCH_CON_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG_QCH), + SFR_ACCESS(QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_JPEG_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_0_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_G2D_QCH_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_0_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_G2D_QCH_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_0_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_G2D_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_G2D_QCH_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_G2D_QCH_1), + SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G2D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G2D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G2D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G2D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3AA_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G3AA_QCH), + SFR_ACCESS(DMYQCH_CON_G3AA_QCH_ENABLE, 0, 1, DMYQCH_CON_G3AA_QCH), + SFR_ACCESS(DMYQCH_CON_G3AA_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_G3AA_QCH), + SFR_ACCESS(DMYQCH_CON_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_G3AA_QCH), + SFR_ACCESS(QCH_CON_G3AA_CMU_G3AA_QCH_ENABLE, 0, 1, QCH_CON_G3AA_CMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_G3AA_CMU_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3AA_CMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_G3AA_CMU_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3AA_CMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_G3AA_CMU_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3AA_CMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_GPC_G3AA_QCH_ENABLE, 0, 1, QCH_CON_GPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_GPC_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_GPC_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_GPC_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_PPMU_G3AA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_PPMU_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_PPMU_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_PPMU_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3AA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3AA_QCH_ENABLE, 0, 1, QCH_CON_SSMT_G3AA_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_G3AA_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_G3AA_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_G3AA_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_G3AA_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3AA_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3AA_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3AA_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_G3AA_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3AA_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3AA_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_G3AA_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3AA_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_G3AA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3AA_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3AA_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3AA_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3AA_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, 0, 1, QCH_CON_ADD_APBIF_G3D_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADD_APBIF_G3D_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADD_APBIF_G3D_QCH), + SFR_ACCESS(QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADD_APBIF_G3D_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_ENABLE, 0, 1, DMYQCH_CON_ADD_G3D_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ADD_G3D_QCH), + SFR_ACCESS(DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_ADD_G3D_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_GPU_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_G_GPU_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_GPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_G_GPU_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_GPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_G_GPU_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_GPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADM_AHB_G_GPU_QCH), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D0_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D0_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D1_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D1_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D2_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D2_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, 0, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, 1, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL, 16, 10, QCH_CON_ASB_G3D_QCH_LH_D3_G3D), + SFR_ACCESS(QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASB_G3D_QCH_LH_D3_G3D), + SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMG3D_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMG3D_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMG3D_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMG3D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_G3D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_G3D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_G3D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_G3D_QCH), + SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH), + SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH), + SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH), + SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_G3D_CMU_G3D_QCH), + SFR_ACCESS(QCH_CON_GPC_G3D_QCH_ENABLE, 0, 1, QCH_CON_GPC_G3D_QCH), + SFR_ACCESS(QCH_CON_GPC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_G3D_QCH), + SFR_ACCESS(QCH_CON_GPC_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_G3D_QCH), + SFR_ACCESS(QCH_CON_GPC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_G3D_QCH), + SFR_ACCESS(QCH_CON_GPU_QCH_ENABLE, 0, 1, QCH_CON_GPU_QCH), + SFR_ACCESS(QCH_CON_GPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPU_QCH), + SFR_ACCESS(QCH_CON_GPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPU_QCH), + SFR_ACCESS(QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_G3D_CU_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH), + SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_G3D_QCH), + SFR_ACCESS(QCH_CON_UASC_G3D_QCH_ENABLE, 0, 1, QCH_CON_UASC_G3D_QCH), + SFR_ACCESS(QCH_CON_UASC_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_G3D_QCH), + SFR_ACCESS(QCH_CON_UASC_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_G3D_QCH), + SFR_ACCESS(QCH_CON_UASC_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_G3D_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_GDC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_GDC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_GDC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_GDC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_GDC_QCH), + SFR_ACCESS(QCH_CON_GDC0_QCH_CLK_ENABLE, 0, 1, QCH_CON_GDC0_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_GDC0_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_GDC0_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC0_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_C2CLK_ENABLE, 0, 1, QCH_CON_GDC0_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_C2CLK_CLOCK_REQ, 1, 1, QCH_CON_GDC0_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_C2CLK_EXPIRE_VAL, 16, 10, QCH_CON_GDC0_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC0_QCH_C2CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC0_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_CLK_ENABLE, 0, 1, QCH_CON_GDC1_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_GDC1_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_GDC1_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC1_QCH_CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_C2CLK_ENABLE, 0, 1, QCH_CON_GDC1_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_C2CLK_CLOCK_REQ, 1, 1, QCH_CON_GDC1_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_C2CLK_EXPIRE_VAL, 16, 10, QCH_CON_GDC1_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC1_QCH_C2CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC1_QCH_C2CLK), + SFR_ACCESS(QCH_CON_GDC_CMU_GDC_QCH_ENABLE, 0, 1, QCH_CON_GDC_CMU_GDC_QCH), + SFR_ACCESS(QCH_CON_GDC_CMU_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GDC_CMU_GDC_QCH), + SFR_ACCESS(QCH_CON_GDC_CMU_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GDC_CMU_GDC_QCH), + SFR_ACCESS(QCH_CON_GDC_CMU_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GDC_CMU_GDC_QCH), + SFR_ACCESS(QCH_CON_GPC_GDC_QCH_ENABLE, 0, 1, QCH_CON_GPC_GDC_QCH), + SFR_ACCESS(QCH_CON_GPC_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_GDC_QCH), + SFR_ACCESS(QCH_CON_GPC_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_GDC_QCH), + SFR_ACCESS(QCH_CON_GPC_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_GDC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_SCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_GDC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_SCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_GDC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_SCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_GDC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_GDC_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_SCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_GDC_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_SCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_GDC_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_SCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_GDC_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_SCSC_QCH_CLK_ENABLE, 0, 1, QCH_CON_SCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_SCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_SCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_C2CLK_ENABLE, 0, 1, QCH_CON_SCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_C2CLK_CLOCK_REQ, 1, 1, QCH_CON_SCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_C2CLK_EXPIRE_VAL, 16, 10, QCH_CON_SCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_SCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GDC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_GDC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_SCSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_GDC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_SCSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_GDC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_SCSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_SCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_SCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D2_SCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_GDC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D3_GDC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_GDC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_GDC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_GDC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_GDC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_GDC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_GDC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_GDC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_GDC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_GDC_QCH), + SFR_ACCESS(DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_ENABLE, 0, 1, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH), + SFR_ACCESS(DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH), + SFR_ACCESS(DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH), + SFR_ACCESS(QCH_CON_BAAW_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_BAAW_GSACORE_QCH), + SFR_ACCESS(QCH_CON_BAAW_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BAAW_GSACORE_QCH), + SFR_ACCESS(QCH_CON_BAAW_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BAAW_GSACORE_QCH), + SFR_ACCESS(QCH_CON_BAAW_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BAAW_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_CA32_GSACORE_QCH_ENABLE, 0, 1, DMYQCH_CON_CA32_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_CA32_GSACORE_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CA32_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CA32_GSACORE_QCH), + SFR_ACCESS(QCH_CON_DMA_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_DMA_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_DMA_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GIC_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_GIC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GIC_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GIC_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GIC_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GPIO_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_GPIO_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GPIO_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GPIO_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GPIO_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GSACORE_CMU_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_GSACORE_CMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GSACORE_CMU_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_GSACORE_CMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GSACORE_CMU_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GSACORE_CMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_GSACORE_CMU_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GSACORE_CMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_GSACORE_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_GSACORE_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_GSACORE_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_GSACORE_QCH), + SFR_ACCESS(QCH_CON_KDN_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_KDN_GSACORE_QCH), + SFR_ACCESS(QCH_CON_KDN_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_KDN_GSACORE_QCH), + SFR_ACCESS(QCH_CON_KDN_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_KDN_GSACORE_QCH), + SFR_ACCESS(QCH_CON_KDN_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_KDN_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_I_CA32_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_I_GIC_CA32_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GME_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GME_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GME_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_GME_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_PPMU_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_PPMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_PPMU_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_PPMU_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_GSACORE_QCH), + SFR_ACCESS(QCH_CON_PPMU_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_GSACORE_QCH_ENABLE, 0, 1, DMYQCH_CON_PUF_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_GSACORE_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PUF_GSACORE_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PUF_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_CA32_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_QE_CA32_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_CA32_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_CA32_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_CA32_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_CA32_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_CA32_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_DMA_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_QE_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_DMA_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_DMA_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_DMA_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_QE_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_RESETMON_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_RESETMON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_RESETMON_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_RESETMON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_RESETMON_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RESETMON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_RESETMON_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RESETMON_GSACORE_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH), + SFR_ACCESS(QCH_CON_SPI_FPS_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_SPI_FPS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_FPS_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_FPS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_FPS_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_FPS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_FPS_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_FPS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_GSC_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_SPI_GSC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_GSC_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_GSC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_GSC_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_GSC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SPI_GSC_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPI_GSC_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_SSMT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSMT_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSS_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSS_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSS_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_GSACORE_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_GSACORE_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_GSACORE_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_GSACORE_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_GSACORE_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_GSACORE_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_GSACORE_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_GSACORE_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_GSACORE_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_GSACORE_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_GSACORE_QCH), + SFR_ACCESS(QCH_CON_UART_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_UART_GSACORE_QCH), + SFR_ACCESS(QCH_CON_UART_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_GSACORE_QCH), + SFR_ACCESS(QCH_CON_UART_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_GSACORE_QCH), + SFR_ACCESS(QCH_CON_UART_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UART_GSACORE_QCH), + SFR_ACCESS(QCH_CON_WDT_GSACORE_QCH_ENABLE, 0, 1, QCH_CON_WDT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_WDT_GSACORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_WDT_GSACORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_WDT_GSACORE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_GSACORE_QCH), + SFR_ACCESS(QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_ENABLE, 0, 1, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH), + SFR_ACCESS(QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_CLOCK_REQ, 1, 1, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH), + SFR_ACCESS(QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH), + SFR_ACCESS(QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UDAP_SSS_AHB_ASYNC_QCH), + SFR_ACCESS(QCH_CON_UGME_QCH_ENABLE, 0, 1, QCH_CON_UGME_QCH), + SFR_ACCESS(QCH_CON_UGME_QCH_CLOCK_REQ, 1, 1, QCH_CON_UGME_QCH), + SFR_ACCESS(QCH_CON_UGME_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UGME_QCH), + SFR_ACCESS(QCH_CON_UGME_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UGME_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_APBIF_GPIO_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBIF_GPIO_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBIF_GPIO_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_APBIF_GPIO_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBIF_GPIO_GSACTRL_QCH), + SFR_ACCESS(DMYQCH_CON_DAP_GSACTRL_QCH_ENABLE, 0, 1, DMYQCH_CON_DAP_GSACTRL_QCH), + SFR_ACCESS(DMYQCH_CON_DAP_GSACTRL_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DAP_GSACTRL_QCH), + SFR_ACCESS(DMYQCH_CON_DAP_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_DAP_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GPC_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_GPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GPC_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GPC_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GSACTRL_CMU_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_GSACTRL_CMU_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GSACTRL_CMU_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_GSACTRL_CMU_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GSACTRL_CMU_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GSACTRL_CMU_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_GSACTRL_CMU_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GSACTRL_CMU_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_INTMEM_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_INTMEM_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_IP_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_IP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_GSA_CU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AOC_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GSA2AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GSA2AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GSA2AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GSA2AOC_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AUR_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GSA2AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GSA2AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GSA2AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GSA2AUR_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2NONTZ_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GSA2NONTZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2NONTZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GSA2NONTZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2NONTZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GSA2NONTZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2NONTZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GSA2NONTZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TPU_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GSA2TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GSA2TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GSA2TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GSA2TPU_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TZ_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_GSA2TZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_GSA2TZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_GSA2TZ_QCH), + SFR_ACCESS(QCH_CON_MAILBOX_GSA2TZ_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MAILBOX_GSA2TZ_QCH), + SFR_ACCESS(QCH_CON_PMU_GSA_QCH_ENABLE, 0, 1, QCH_CON_PMU_GSA_QCH), + SFR_ACCESS(QCH_CON_PMU_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_GSA_QCH), + SFR_ACCESS(QCH_CON_PMU_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_GSA_QCH), + SFR_ACCESS(QCH_CON_PMU_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PMU_GSA_QCH), + SFR_ACCESS(QCH_CON_SECJTAG_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SECJTAG_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SECJTAG_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SECJTAG_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SECJTAG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GSA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRLEXT_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_GSACTRLEXT_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRLEXT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_GSACTRLEXT_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRLEXT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_GSACTRLEXT_QCH), + SFR_ACCESS(QCH_CON_SYSREG_GSACTRLEXT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_GSACTRLEXT_QCH), + SFR_ACCESS(QCH_CON_TIMER_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_TIMER_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TIMER_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_TIMER_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TIMER_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TIMER_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TIMER_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TIMER_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TZPC_GSACTRL_QCH_ENABLE, 0, 1, QCH_CON_TZPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TZPC_GSACTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TZPC_GSACTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_TZPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TZPC_GSACTRL_QCH), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_PCLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_PCLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_PCLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_PCLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH_GTC_CLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH_GTC_CLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH_GTC_CLK), + SFR_ACCESS(QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DP_LINK_QCH_GTC_CLK), + SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_ACLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_ACLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_ACLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ETR_MIU_QCH_ACLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_PCLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_PCLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_PCLK), + SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ETR_MIU_QCH_PCLK), + SFR_ACCESS(QCH_CON_GPC_HSI0_QCH_ENABLE, 0, 1, QCH_CON_GPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_HSI0_QCH), + SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, 0, 1, QCH_CON_HSI0_CMU_HSI0_QCH), + SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI0_CMU_HSI0_QCH), + SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI0_CMU_HSI0_QCH), + SFR_ACCESS(QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI0_CMU_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_AOC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI0_AOC_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI0_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI0_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI0_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI0_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI0_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LP1_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SSMT_USB_QCH_ENABLE, 0, 1, QCH_CON_SSMT_USB_QCH), + SFR_ACCESS(QCH_CON_SSMT_USB_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_USB_QCH), + SFR_ACCESS(QCH_CON_SSMT_USB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_USB_QCH), + SFR_ACCESS(QCH_CON_SSMT_USB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_USB_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_USB_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_USB_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_USB_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_USB_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_USB_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_USB_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_USB_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_USB_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_USB_QCH_S1), + SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI0_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_CTRL_QCH_ENABLE, 0, 1, QCH_CON_UASC_HSI0_CTRL_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_CTRL_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_HSI0_CTRL_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_CTRL_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_HSI0_CTRL_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_CTRL_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_HSI0_CTRL_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_LINK_QCH_ENABLE, 0, 1, QCH_CON_UASC_HSI0_LINK_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_LINK_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_HSI0_LINK_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_LINK_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_HSI0_LINK_QCH), + SFR_ACCESS(QCH_CON_UASC_HSI0_LINK_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_HSI0_LINK_QCH), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, 0, 1, DMYQCH_CON_USB31DRD_QCH_REF), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, 1, 1, DMYQCH_CON_USB31DRD_QCH_REF), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USB31DRD_QCH_REF), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_SLV_CTRL), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_SLV_CTRL), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_SLV_LINK), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_SLV_LINK), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_SLV_LINK), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_SLV_LINK), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_APB), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_APB), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_APB), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_APB), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_PCS), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_PCS), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_PCS), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_PCS), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_ENABLE, 0, 1, QCH_CON_USB31DRD_QCH_DBG), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ, 1, 1, QCH_CON_USB31DRD_QCH_DBG), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL, 16, 10, QCH_CON_USB31DRD_QCH_DBG), + SFR_ACCESS(QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USB31DRD_QCH_DBG), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_ENABLE, 0, 1, DMYQCH_CON_USB31DRD_QCH), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_USB31DRD_QCH), + SFR_ACCESS(DMYQCH_CON_USB31DRD_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_USB31DRD_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI1_QCH_ENABLE, 0, 1, QCH_CON_GPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI1_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI1_QCH), + SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_HSI1_CMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI1_CMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI1_CMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI1_CMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_1), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_DBG_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_AXI_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_APB_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_0_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_0_QCH_UDBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_0_QCH_UDBG), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN4_0_QCH), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN4_0_QCH), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN4_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_0_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_0_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_ENABLE, 0, 1, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PCIE_GEN4A_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_ENABLE, 0, 1, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PCIE_GEN4B_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_HSI1_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_HSI1_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_HSI1_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_HSI1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_HSI1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI1_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_HSI1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI1_QCH_S1), + SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI2_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI2_QCH_ENABLE, 0, 1, QCH_CON_GPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPC_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI2_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2UFS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_HSI2UFS_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2UFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_HSI2UFS_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2UFS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_HSI2UFS_QCH), + SFR_ACCESS(QCH_CON_GPIO_HSI2UFS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_HSI2UFS_QCH), + SFR_ACCESS(QCH_CON_HSI2_CMU_HSI2_QCH_ENABLE, 0, 1, QCH_CON_HSI2_CMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_HSI2_CMU_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2_CMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_HSI2_CMU_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2_CMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_HSI2_CMU_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_HSI2_CMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI2_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH), + SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH), + SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH), + SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH), + SFR_ACCESS(QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MMC_CARD_QCH), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_1_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_1_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_1_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_1), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_PCS_APB), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF0), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_PMA_APB), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_AXI_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_AXI_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_DBG_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_DBG_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_2_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_2_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_2_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_APB_2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_APB_2), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_UDBG_ENABLE, 0, 1, QCH_CON_PCIE_GEN4_1_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_UDBG_CLOCK_REQ, 1, 1, QCH_CON_PCIE_GEN4_1_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_UDBG_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_GEN4_1_QCH_UDBG), + SFR_ACCESS(QCH_CON_PCIE_GEN4_1_QCH_UDBG_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_GEN4_1_QCH_UDBG), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_ENABLE, 0, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1), + SFR_ACCESS(DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PCIE_GEN4_1_QCH_REF1), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_1_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_1_QCH_ENABLE, 0, 1, QCH_CON_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI2_QCH_ENABLE, 0, 1, QCH_CON_PPMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_PPMU_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_MMC_CARD_HSI2_QCH_ENABLE, 0, 1, QCH_CON_QE_MMC_CARD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_MMC_CARD_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_MMC_CARD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_MMC_CARD_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_MMC_CARD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_MMC_CARD_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_MMC_CARD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_ENABLE, 0, 1, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PCIE_GEN4A_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_ENABLE, 0, 1, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PCIE_GEN4B_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_UFS_EMBD_HSI2_QCH_ENABLE, 0, 1, QCH_CON_QE_UFS_EMBD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_UFS_EMBD_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_UFS_EMBD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_UFS_EMBD_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_UFS_EMBD_HSI2_QCH), + SFR_ACCESS(QCH_CON_QE_UFS_EMBD_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_UFS_EMBD_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI2_QCH_ENABLE, 0, 1, QCH_CON_SSMT_HSI2_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_HSI2_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_HSI2_QCH), + SFR_ACCESS(QCH_CON_SSMT_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_HSI2_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_HSI2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI2_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_HSI2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_HSI2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_HSI2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_HSI2_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_HSI2_QCH_S1), + SFR_ACCESS(QCH_CON_SYSREG_HSI2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_HSI2_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_HSI2_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_HSI2_QCH), + SFR_ACCESS(QCH_CON_SYSREG_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_HSI2_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_ENABLE, 0, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_CLOCK_REQ, 1, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP), + SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_UFS_EMBD_QCH_FMP), + SFR_ACCESS(QCH_CON_D_TZPC_IPP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_IPP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_IPP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_IPP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_IPP_QCH), + SFR_ACCESS(QCH_CON_GPC_IPP_QCH_ENABLE, 0, 1, QCH_CON_GPC_IPP_QCH), + SFR_ACCESS(QCH_CON_GPC_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_IPP_QCH), + SFR_ACCESS(QCH_CON_GPC_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_IPP_QCH), + SFR_ACCESS(QCH_CON_GPC_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_IPP_QCH), + SFR_ACCESS(QCH_CON_IPP_CMU_IPP_QCH_ENABLE, 0, 1, QCH_CON_IPP_CMU_IPP_QCH), + SFR_ACCESS(QCH_CON_IPP_CMU_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_IPP_CMU_IPP_QCH), + SFR_ACCESS(QCH_CON_IPP_CMU_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IPP_CMU_IPP_QCH), + SFR_ACCESS(QCH_CON_IPP_CMU_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_IPP_CMU_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_IPP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_IPP_QCH), + SFR_ACCESS(QCH_CON_PPMU_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_IPP_QCH), + SFR_ACCESS(QCH_CON_PPMU_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_IPP_QCH), + SFR_ACCESS(QCH_CON_PPMU_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_IPP_QCH), + SFR_ACCESS(QCH_CON_PPMU_MSA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MSA_QCH), + SFR_ACCESS(QCH_CON_PPMU_MSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MSA_QCH), + SFR_ACCESS(QCH_CON_PPMU_MSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MSA_QCH), + SFR_ACCESS(QCH_CON_PPMU_MSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MSA_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN0_QCH_ENABLE, 0, 1, QCH_CON_QE_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN1_QCH_ENABLE, 0, 1, QCH_CON_QE_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN2_QCH_ENABLE, 0, 1, QCH_CON_QE_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN3_QCH_ENABLE, 0, 1, QCH_CON_QE_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN3_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_QE_ALIGN3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_QE_ALN_STAT_QCH_ENABLE, 0, 1, QCH_CON_QE_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_QE_ALN_STAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_QE_ALN_STAT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_QE_ALN_STAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_QE_FDPIG_QCH_ENABLE, 0, 1, QCH_CON_QE_FDPIG_QCH), + SFR_ACCESS(QCH_CON_QE_FDPIG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_FDPIG_QCH), + SFR_ACCESS(QCH_CON_QE_FDPIG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_FDPIG_QCH), + SFR_ACCESS(QCH_CON_QE_FDPIG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_FDPIG_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH0_QCH_ENABLE, 0, 1, QCH_CON_QE_RGBH0_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_RGBH0_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_RGBH0_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_RGBH0_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH1_QCH_ENABLE, 0, 1, QCH_CON_QE_RGBH1_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_RGBH1_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_RGBH1_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_RGBH1_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH2_QCH_ENABLE, 0, 1, QCH_CON_QE_RGBH2_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH2_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_RGBH2_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_RGBH2_QCH), + SFR_ACCESS(QCH_CON_QE_RGBH2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_RGBH2_QCH), + SFR_ACCESS(QCH_CON_QE_THSTAT_QCH_ENABLE, 0, 1, QCH_CON_QE_THSTAT_QCH), + SFR_ACCESS(QCH_CON_QE_THSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_THSTAT_QCH), + SFR_ACCESS(QCH_CON_QE_THSTAT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_THSTAT_QCH), + SFR_ACCESS(QCH_CON_QE_THSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_THSTAT_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA0_QCH_ENABLE, 0, 1, QCH_CON_QE_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA1_QCH_ENABLE, 0, 1, QCH_CON_QE_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_QE_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_SIPU_IPP_QCH_ENABLE, 0, 1, QCH_CON_SIPU_IPP_QCH), + SFR_ACCESS(QCH_CON_SIPU_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SIPU_IPP_QCH), + SFR_ACCESS(QCH_CON_SIPU_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SIPU_IPP_QCH), + SFR_ACCESS(QCH_CON_SIPU_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SIPU_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_IPP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ALIGN0_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ALIGN1_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN2_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ALIGN2_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN3_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALIGN3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ALIGN3_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALN_STAT_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALN_STAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALN_STAT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_ALN_STAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ALN_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_FDPIG_QCH_ENABLE, 0, 1, QCH_CON_SSMT_FDPIG_QCH), + SFR_ACCESS(QCH_CON_SSMT_FDPIG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_FDPIG_QCH), + SFR_ACCESS(QCH_CON_SSMT_FDPIG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_FDPIG_QCH), + SFR_ACCESS(QCH_CON_SSMT_FDPIG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_FDPIG_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_RGBH0_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_RGBH0_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_RGBH0_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_RGBH0_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_RGBH1_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_RGBH1_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_RGBH1_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_RGBH1_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH2_QCH_ENABLE, 0, 1, QCH_CON_SSMT_RGBH2_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_RGBH2_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_RGBH2_QCH), + SFR_ACCESS(QCH_CON_SSMT_RGBH2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_RGBH2_QCH), + SFR_ACCESS(QCH_CON_SSMT_THSTAT_QCH_ENABLE, 0, 1, QCH_CON_SSMT_THSTAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_THSTAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_THSTAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_THSTAT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_THSTAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_THSTAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_THSTAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_TNR_MSA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_TNR_MSA1_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_IPP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_IPP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_IPP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_IPP_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_IPP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_IPP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_IPP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_IPP_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_IPP_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_IPP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_IPP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_IPP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_IPP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_IPP_QCH), + SFR_ACCESS(QCH_CON_TNR_A_QCH_ENABLE, 0, 1, QCH_CON_TNR_A_QCH), + SFR_ACCESS(QCH_CON_TNR_A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TNR_A_QCH), + SFR_ACCESS(QCH_CON_TNR_A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TNR_A_QCH), + SFR_ACCESS(QCH_CON_TNR_A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_ITP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_ITP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_ITP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_ITP_QCH), + SFR_ACCESS(QCH_CON_GPC_ITP_QCH_ENABLE, 0, 1, QCH_CON_GPC_ITP_QCH), + SFR_ACCESS(QCH_CON_GPC_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_ITP_QCH), + SFR_ACCESS(QCH_CON_GPC_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_ITP_QCH), + SFR_ACCESS(QCH_CON_GPC_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_QCH_ENABLE, 0, 1, QCH_CON_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_ENABLE, 0, 1, QCH_CON_ITP_CMU_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ITP_CMU_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ITP_CMU_ITP_QCH), + SFR_ACCESS(QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITP_CMU_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH), + SFR_ACCESS(QCH_CON_PPMU_ITP_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ITP_QCH), + SFR_ACCESS(QCH_CON_PPMU_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ITP_QCH), + SFR_ACCESS(QCH_CON_PPMU_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ITP_QCH), + SFR_ACCESS(QCH_CON_PPMU_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ITP_QCH), + SFR_ACCESS(QCH_CON_QE_ITP_QCH_ENABLE, 0, 1, QCH_CON_QE_ITP_QCH), + SFR_ACCESS(QCH_CON_QE_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_ITP_QCH), + SFR_ACCESS(QCH_CON_QE_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_ITP_QCH), + SFR_ACCESS(QCH_CON_QE_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ITP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SSMT_ITP_QCH_ENABLE, 0, 1, QCH_CON_SSMT_ITP_QCH), + SFR_ACCESS(QCH_CON_SSMT_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_ITP_QCH), + SFR_ACCESS(QCH_CON_SSMT_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_ITP_QCH), + SFR_ACCESS(QCH_CON_SSMT_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_ITP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ITP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ITP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ITP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_ITP_QCH), + SFR_ACCESS(QCH_CON_C2R_MCSC_QCH_ENABLE, 0, 1, QCH_CON_C2R_MCSC_QCH), + SFR_ACCESS(QCH_CON_C2R_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_C2R_MCSC_QCH), + SFR_ACCESS(QCH_CON_C2R_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_C2R_MCSC_QCH), + SFR_ACCESS(QCH_CON_C2R_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_C2R_MCSC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_GPC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_GPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_GPC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_GPC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_GPC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_MCSC_QCH), + SFR_ACCESS(QCH_CON_ITSC_QCH_CLK_ENABLE, 0, 1, QCH_CON_ITSC_QCH_CLK), + SFR_ACCESS(QCH_CON_ITSC_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_ITSC_QCH_CLK), + SFR_ACCESS(QCH_CON_ITSC_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_ITSC_QCH_CLK), + SFR_ACCESS(QCH_CON_ITSC_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITSC_QCH_CLK), + SFR_ACCESS(QCH_CON_ITSC_QCH_C2_ENABLE, 0, 1, QCH_CON_ITSC_QCH_C2), + SFR_ACCESS(QCH_CON_ITSC_QCH_C2_CLOCK_REQ, 1, 1, QCH_CON_ITSC_QCH_C2), + SFR_ACCESS(QCH_CON_ITSC_QCH_C2_EXPIRE_VAL, 16, 10, QCH_CON_ITSC_QCH_C2), + SFR_ACCESS(QCH_CON_ITSC_QCH_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ITSC_QCH_C2), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH), + SFR_ACCESS(QCH_CON_MCSC_QCH_CLK_ENABLE, 0, 1, QCH_CON_MCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_CLK_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_CLK_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_C2CLK_ENABLE, 0, 1, QCH_CON_MCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_C2CLK_CLOCK_REQ, 1, 1, QCH_CON_MCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_C2CLK_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_MCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_QCH_C2CLK), + SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, 0, 1, QCH_CON_MCSC_CMU_MCSC_QCH), + SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCSC_CMU_MCSC_QCH), + SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCSC_CMU_MCSC_QCH), + SFR_ACCESS(QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCSC_CMU_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_ITSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_ITSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_ITSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_ITSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_ITSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_ITSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D3_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D3_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D3_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D3_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D3_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D4_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D4_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D4_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D4_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D4_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D4_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D4_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D4_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D5_MCSC_QCH_ENABLE, 0, 1, QCH_CON_QE_D5_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D5_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D5_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D5_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D5_MCSC_QCH), + SFR_ACCESS(QCH_CON_QE_D5_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D5_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_ITSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_ITSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_ITSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_ITSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_ITSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_MCSC_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MCSC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MCSC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MCSC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MCSC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MFC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MFC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MFC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MFC_QCH), + SFR_ACCESS(QCH_CON_GPC_MFC_QCH_ENABLE, 0, 1, QCH_CON_GPC_MFC_QCH), + SFR_ACCESS(QCH_CON_GPC_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_MFC_QCH), + SFR_ACCESS(QCH_CON_GPC_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_MFC_QCH), + SFR_ACCESS(QCH_CON_GPC_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_CMU_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_CMU_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_CMU_MFC_QCH), + SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MFC_CMU_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_ENABLE, 0, 1, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_CLOCK_REQ, 1, 1, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH), + SFR_ACCESS(QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_0_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_MFC_QCH_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_0_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MFC_QCH_0), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_MFC_QCH_1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_MFC_QCH_1), + SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MFC_QCH), + SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY_QCH), + SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY_QCH), + SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY_QCH), + SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DDRPHY_QCH), + SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC_QCH), + SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC_QCH), + SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC_QCH), + SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_APBBR_DMC_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), + SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH), + SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH), + SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH), + SFR_ACCESS(QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DMC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MIF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MIF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MIF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MIF_QCH), + SFR_ACCESS(QCH_CON_GEN_WREN_SECURE_QCH_ENABLE, 0, 1, QCH_CON_GEN_WREN_SECURE_QCH), + SFR_ACCESS(QCH_CON_GEN_WREN_SECURE_QCH_CLOCK_REQ, 1, 1, QCH_CON_GEN_WREN_SECURE_QCH), + SFR_ACCESS(QCH_CON_GEN_WREN_SECURE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GEN_WREN_SECURE_QCH), + SFR_ACCESS(QCH_CON_GEN_WREN_SECURE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GEN_WREN_SECURE_QCH), + SFR_ACCESS(QCH_CON_GPC_MIF_QCH_ENABLE, 0, 1, QCH_CON_GPC_MIF_QCH), + SFR_ACCESS(QCH_CON_GPC_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_MIF_QCH), + SFR_ACCESS(QCH_CON_GPC_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_MIF_QCH), + SFR_ACCESS(QCH_CON_GPC_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_MIF_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MIF_CU_QCH), + SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH), + SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH), + SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH), + SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MIF_CMU_MIF_QCH), + SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, 0, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH), + SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH), + SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH), + SFR_ACCESS(QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MIF_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MIF_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MIF_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_SSS_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_G_SSS_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_G_SSS_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_G_SSS_QCH), + SFR_ACCESS(QCH_CON_ADM_AHB_G_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ADM_AHB_G_SSS_QCH), + SFR_ACCESS(QCH_CON_DIT_QCH_ENABLE, 0, 1, QCH_CON_DIT_QCH), + SFR_ACCESS(QCH_CON_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_DIT_QCH), + SFR_ACCESS(QCH_CON_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DIT_QCH), + SFR_ACCESS(QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_DIT_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MISC_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_MISC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_MISC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_MISC_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_MISC_QCH), + SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH), + SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH), + SFR_ACCESS(QCH_CON_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_QCH), + SFR_ACCESS(QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GIC_QCH), + SFR_ACCESS(QCH_CON_GPC_MISC_QCH_ENABLE, 0, 1, QCH_CON_GPC_MISC_QCH), + SFR_ACCESS(QCH_CON_GPC_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_MISC_QCH), + SFR_ACCESS(QCH_CON_GPC_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_MISC_QCH), + SFR_ACCESS(QCH_CON_GPC_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_MISC_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SSS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_ID_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SSS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_ID_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_ID_SSS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_GIC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MISC_CU_QCH), + SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH), + SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH), + SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH), + SFR_ACCESS(QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MCT_QCH), + SFR_ACCESS(QCH_CON_MISC_CMU_MISC_QCH_ENABLE, 0, 1, QCH_CON_MISC_CMU_MISC_QCH), + SFR_ACCESS(QCH_CON_MISC_CMU_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MISC_CMU_MISC_QCH), + SFR_ACCESS(QCH_CON_MISC_CMU_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MISC_CMU_MISC_QCH), + SFR_ACCESS(QCH_CON_MISC_CMU_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_MISC_CMU_MISC_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BIRA_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BIRA_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BIRA_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BIRA_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BISR_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BISR_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BISR_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_BISR_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH), + SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_OTP_CON_TOP_QCH), + SFR_ACCESS(QCH_CON_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_PDMA0_QCH), + SFR_ACCESS(QCH_CON_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA0_QCH), + SFR_ACCESS(QCH_CON_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA0_QCH), + SFR_ACCESS(QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA0_QCH), + SFR_ACCESS(QCH_CON_PDMA1_QCH_ENABLE, 0, 1, QCH_CON_PDMA1_QCH), + SFR_ACCESS(QCH_CON_PDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA1_QCH), + SFR_ACCESS(QCH_CON_PDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA1_QCH), + SFR_ACCESS(QCH_CON_PDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDMA1_QCH), + SFR_ACCESS(QCH_CON_PPMU_MISC_QCH_ENABLE, 0, 1, QCH_CON_PPMU_MISC_QCH), + SFR_ACCESS(QCH_CON_PPMU_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_MISC_QCH), + SFR_ACCESS(QCH_CON_PPMU_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_MISC_QCH), + SFR_ACCESS(QCH_CON_PPMU_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_MISC_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_QCH_ENABLE, 0, 1, DMYQCH_CON_PUF_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PUF_QCH), + SFR_ACCESS(DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PUF_QCH), + SFR_ACCESS(QCH_CON_QE_DIT_QCH_ENABLE, 0, 1, QCH_CON_QE_DIT_QCH), + SFR_ACCESS(QCH_CON_QE_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_DIT_QCH), + SFR_ACCESS(QCH_CON_QE_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_DIT_QCH), + SFR_ACCESS(QCH_CON_QE_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_DIT_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_PDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_RTIC_QCH_ENABLE, 0, 1, QCH_CON_QE_RTIC_QCH), + SFR_ACCESS(QCH_CON_QE_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_RTIC_QCH), + SFR_ACCESS(QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_RTIC_QCH), + SFR_ACCESS(QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_RTIC_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA0_QCH_ENABLE, 0, 1, QCH_CON_QE_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA1_QCH_ENABLE, 0, 1, QCH_CON_QE_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_SPDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_QCH_ENABLE, 0, 1, QCH_CON_QE_SSS_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_SSS_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_SSS_QCH), + SFR_ACCESS(QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_SSS_QCH), + SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH), + SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH), + SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH), + SFR_ACCESS(QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_RTIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GIC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MISC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SPDMA0_QCH_ENABLE, 0, 1, QCH_CON_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SPDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SPDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SPDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SPDMA1_QCH_ENABLE, 0, 1, QCH_CON_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SPDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SPDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SPDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_DIT_QCH_ENABLE, 0, 1, QCH_CON_SSMT_DIT_QCH), + SFR_ACCESS(QCH_CON_SSMT_DIT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_DIT_QCH), + SFR_ACCESS(QCH_CON_SSMT_DIT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_DIT_QCH), + SFR_ACCESS(QCH_CON_SSMT_DIT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_DIT_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_RTIC_QCH_ENABLE, 0, 1, QCH_CON_SSMT_RTIC_QCH), + SFR_ACCESS(QCH_CON_SSMT_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_RTIC_QCH), + SFR_ACCESS(QCH_CON_SSMT_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_RTIC_QCH), + SFR_ACCESS(QCH_CON_SSMT_RTIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_RTIC_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_SPDMA0_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_SPDMA1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_SPDMA1_QCH), + SFR_ACCESS(QCH_CON_SSMT_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSMT_SSS_QCH), + SFR_ACCESS(QCH_CON_SSMT_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_SSS_QCH), + SFR_ACCESS(QCH_CON_SSMT_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_SSS_QCH), + SFR_ACCESS(QCH_CON_SSMT_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_SSS_QCH), + SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH), + SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH), + SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH), + SFR_ACCESS(QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSS_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_MISC_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_SSS_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_SSS_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_SSS_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_SSS_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_SSS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_SSS_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MISC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MISC_QCH), + SFR_ACCESS(QCH_CON_SYSREG_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_MISC_QCH), + SFR_ACCESS(QCH_CON_TMU_SUB_QCH_ENABLE, 0, 1, QCH_CON_TMU_SUB_QCH), + SFR_ACCESS(QCH_CON_TMU_SUB_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_SUB_QCH), + SFR_ACCESS(QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TMU_SUB_QCH), + SFR_ACCESS(QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_SUB_QCH), + SFR_ACCESS(QCH_CON_TMU_TOP_QCH_ENABLE, 0, 1, QCH_CON_TMU_TOP_QCH), + SFR_ACCESS(QCH_CON_TMU_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_TMU_TOP_QCH), + SFR_ACCESS(QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TMU_TOP_QCH), + SFR_ACCESS(QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TMU_TOP_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER0_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER1_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER1_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER1_QCH), + SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_WDT_CLUSTER1_QCH), + SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE, 0, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH), + SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH), + SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ASYNCSFR_WR_SMC_QCH), + SFR_ACCESS(QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_ASYNCSFR_WR_SMC_QCH), + SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH), + SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH), + SFR_ACCESS(QCH_CON_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BDU_QCH), + SFR_ACCESS(QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BDU_QCH), + SFR_ACCESS(QCH_CON_CCI_QCH_ENABLE, 0, 1, QCH_CON_CCI_QCH), + SFR_ACCESS(QCH_CON_CCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_CCI_QCH), + SFR_ACCESS(QCH_CON_CCI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CCI_QCH), + SFR_ACCESS(QCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CCI_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL0_CMUREF_QCH), + SFR_ACCESS(QCH_CON_CPE425_QCH_ENABLE, 0, 1, QCH_CON_CPE425_QCH), + SFR_ACCESS(QCH_CON_CPE425_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPE425_QCH), + SFR_ACCESS(QCH_CON_CPE425_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPE425_QCH), + SFR_ACCESS(QCH_CON_CPE425_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_CPE425_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_GPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_NOCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_EH_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_EH_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC0_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC2_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC2_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC2_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC2_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC3_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC3_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC3_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC3_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC2_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_DMC3_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_BDU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_BDU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_SLC_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_T_SLC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_EH_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_GIC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_MISC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH), + SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH), + SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH), + SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NOCL0_CMU_NOCL0_QCH), + SFR_ACCESS(QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL0_CMU_NOCL0_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_CCI_M1_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CCI_M1_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CCI_M1_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CCI_M1_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CCI_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CCI_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CCI_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CCI_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M2_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CCI_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M2_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CCI_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M2_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CCI_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CCI_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M3_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CCI_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M3_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CCI_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M3_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CCI_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CCI_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M4_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CCI_M4_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M4_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CCI_M4_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M4_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CCI_M4_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CCI_M4_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CCI_M4_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CPUCL0_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_CPUCL0_D1_EVENT_QCH), + SFR_ACCESS(DMYQCH_CON_PPC_DBG_CC_QCH_ENABLE, 0, 1, DMYQCH_CON_PPC_DBG_CC_QCH), + SFR_ACCESS(DMYQCH_CON_PPC_DBG_CC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_PPC_DBG_CC_QCH), + SFR_ACCESS(DMYQCH_CON_PPC_DBG_CC_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_PPC_DBG_CC_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_EH_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_EH_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_EH_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_EH_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_EH_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_EH_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_EH_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_EH_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_EH_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_IO_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IO_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IO_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IO_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_IO_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_IO_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_IO_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_IO_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_IO_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL1B_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ACE_CPUCL0_D0_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_ENABLE, 0, 1, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH), + SFR_ACCESS(QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_ACE_CPUCL0_D1_QCH), + SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, 0, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH), + SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH), + SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SFR_APBIF_CMU_TOPC_QCH), + SFR_ACCESS(QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SFR_APBIF_CMU_TOPC_QCH), + SFR_ACCESS(QCH_CON_SLC_CB_TOP_QCH_ENABLE, 0, 1, QCH_CON_SLC_CB_TOP_QCH), + SFR_ACCESS(QCH_CON_SLC_CB_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLC_CB_TOP_QCH), + SFR_ACCESS(QCH_CON_SLC_CB_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLC_CB_TOP_QCH), + SFR_ACCESS(QCH_CON_SLC_CB_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLC_CB_TOP_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH1_QCH_ENABLE, 0, 1, DMYQCH_CON_SLC_CH1_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH1_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_SLC_CH1_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH1_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SLC_CH1_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH2_QCH_ENABLE, 0, 1, DMYQCH_CON_SLC_CH2_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH2_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_SLC_CH2_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH2_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SLC_CH2_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH3_QCH_ENABLE, 0, 1, DMYQCH_CON_SLC_CH3_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH3_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_SLC_CH3_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH3_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SLC_CH3_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH_TOP_QCH_ENABLE, 0, 1, DMYQCH_CON_SLC_CH_TOP_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH_TOP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_SLC_CH_TOP_QCH), + SFR_ACCESS(DMYQCH_CON_SLC_CH_TOP_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_SLC_CH_TOP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_ALIVE_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_EH_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_EH_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_EH_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_EH_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_EH_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GIC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GIC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_GIC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MIF3_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MIF3_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MISC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MISC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NOCL0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_NOCL0_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL0_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_GPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D0_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D0_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D1_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D1_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D2_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D2_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D3_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D3_G3D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_TPU_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_AUR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_AUR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_AUR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_AUR_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_G3D_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_TPU_CD_QCH), + SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NOCL1A_CMU_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL1A_CMU_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D0_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D0_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D0_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D0_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPCFW_G3D0_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D1_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D1_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D1_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D1_QCH), + SFR_ACCESS(QCH_CON_PPCFW_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPCFW_G3D1_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_AUR_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_AUR_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_AUR_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_AUR_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_AUR_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_AUR_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_AUR_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_AUR_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_AUR_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_AUR_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_AUR_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AUR_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_AUR_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D_D0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D_D0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D_D1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D2_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D_D2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D2_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D_D2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D2_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D_D2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D2_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D_D2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D3_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_G3D_D3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D3_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_G3D_D3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D3_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_G3D_D3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_G3D_D3_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_G3D_D3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL2A_M0_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL2A_M1_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL2A_M2_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_NOCL2A_M3_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_TPU_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_TPU_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_TPU_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_TPU_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_TPU_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_TPU_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_TPU_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_TPU_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_TPU_EVENT_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AUR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_AUR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_G3D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D0_QCH_ENABLE, 0, 1, QCH_CON_SSMT_G3D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_G3D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_G3D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_G3D0_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D1_QCH_ENABLE, 0, 1, QCH_CON_SSMT_G3D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_G3D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_G3D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_G3D1_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D2_QCH_ENABLE, 0, 1, QCH_CON_SSMT_G3D2_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_G3D2_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_G3D2_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_G3D2_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D3_QCH_ENABLE, 0, 1, QCH_CON_SSMT_G3D3_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_G3D3_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_G3D3_QCH), + SFR_ACCESS(QCH_CON_SSMT_G3D3_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_G3D3_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D0_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D_QCH_D0), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D0_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D_QCH_D0), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D0_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D_QCH_D0), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D0_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D_QCH_D0), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D1_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D_QCH_D1), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D_QCH_D1), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D_QCH_D1), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D_QCH_D1), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D2_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D_QCH_D2), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D_QCH_D2), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D_QCH_D2), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D_QCH_D2), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D3_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D_QCH_D3), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D3_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D_QCH_D3), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D3_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D_QCH_D3), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_D3_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D_QCH_D3), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_MPTW_ENABLE, 0, 1, QCH_CON_SYSMMU_G3D_QCH_MPTW), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_MPTW_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_G3D_QCH_MPTW), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_MPTW_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_G3D_QCH_MPTW), + SFR_ACCESS(QCH_CON_SYSMMU_G3D_QCH_MPTW_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_G3D_QCH_MPTW), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_NOCL1A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL1A_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_GPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI0_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_HSI0_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_HSI1_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AOC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_AOC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_APM_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_GSA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_GSA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_AOC_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_GSA_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH), + SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NOCL1B_CMU_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL1B_CMU_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_CYCLE_QCH_ENABLE, 0, 1, QCH_CON_PPC_AOC_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_CYCLE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_AOC_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_CYCLE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_AOC_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_CYCLE_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_AOC_CYCLE_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_EVENT_QCH_ENABLE, 0, 1, QCH_CON_PPC_AOC_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_EVENT_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPC_AOC_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_EVENT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPC_AOC_EVENT_QCH), + SFR_ACCESS(QCH_CON_PPC_AOC_EVENT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPC_AOC_EVENT_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_G_CSSYS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AOC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AOC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AOC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_AOC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_AOC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GSA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GSA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GSA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GSA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_GSA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_NOCL1B_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL1B_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH), + SFR_ACCESS(DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_GPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_GPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D2_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D2_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI2_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_HSI2_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_MISC_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_MI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_MISC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_MI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_MISC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_MI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_MI_D_MISC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_MI_D_MISC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_G2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_MFC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_DPU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D2_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D3_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D4_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_BO_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_BO_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_D_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_D_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH), + SFR_ACCESS(QCH_CON_NOCL2A_CMU_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_NOCL2A_CMU_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_NOCL2A_CMU_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_NOCL2A_CMU_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_NOCL2A_CMU_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_NOCL2A_CMU_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_NOCL2A_CMU_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_NOCL2A_CMU_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BO_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BO_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BO_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_BO_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_BO_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_CSIS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DISP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DISP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DISP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DISP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DISP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNS_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DNS_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_DPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_G2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3AA_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_G3AA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GDC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_GDC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI2_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_HSI2_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_HSI2_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_IPP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_IPP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ITP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ITP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ITP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_ITP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_ITP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MCSC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_MFC_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PDP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_SI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_SI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_SYSREG_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_D_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_D_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL2A_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL2A_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL2A_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_TREX_P_NOCL2A_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TREX_P_NOCL2A_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PDP_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PDP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PDP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PDP_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PDP_QCH), + SFR_ACCESS(QCH_CON_GPC_PDP_QCH_ENABLE, 0, 1, QCH_CON_GPC_PDP_QCH), + SFR_ACCESS(QCH_CON_GPC_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_PDP_QCH), + SFR_ACCESS(QCH_CON_GPC_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_PDP_QCH), + SFR_ACCESS(QCH_CON_GPC_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH), + SFR_ACCESS(QCH_CON_PDP_CMU_PDP_QCH_ENABLE, 0, 1, QCH_CON_PDP_CMU_PDP_QCH), + SFR_ACCESS(QCH_CON_PDP_CMU_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDP_CMU_PDP_QCH), + SFR_ACCESS(QCH_CON_PDP_CMU_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDP_CMU_PDP_QCH), + SFR_ACCESS(QCH_CON_PDP_CMU_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDP_CMU_PDP_QCH), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE, 0, 1, QCH_CON_PDP_TOP_QCH_C2_PDP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ, 1, 1, QCH_CON_PDP_TOP_QCH_C2_PDP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL, 16, 10, QCH_CON_PDP_TOP_QCH_C2_PDP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDP_TOP_QCH_C2_PDP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE, 0, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ, 1, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL, 16, 10, QCH_CON_PDP_TOP_QCH_PDP_TOP), + SFR_ACCESS(QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PDP_TOP_QCH_PDP_TOP), + SFR_ACCESS(QCH_CON_PPMU_VRA_QCH_ENABLE, 0, 1, QCH_CON_PPMU_VRA_QCH), + SFR_ACCESS(QCH_CON_PPMU_VRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_VRA_QCH), + SFR_ACCESS(QCH_CON_PPMU_VRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_VRA_QCH), + SFR_ACCESS(QCH_CON_PPMU_VRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_VRA_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_AF1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_AF1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_AF1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_AF1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT0_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT0_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT0_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT1_QCH_ENABLE, 0, 1, QCH_CON_QE_PDP_STAT1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT1_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_PDP_STAT1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_PDP_STAT1_QCH), + SFR_ACCESS(QCH_CON_QE_PDP_STAT1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_PDP_STAT1_QCH), + SFR_ACCESS(QCH_CON_QE_VRA_QCH_ENABLE, 0, 1, QCH_CON_QE_VRA_QCH), + SFR_ACCESS(QCH_CON_QE_VRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_VRA_QCH), + SFR_ACCESS(QCH_CON_QE_VRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_VRA_QCH), + SFR_ACCESS(QCH_CON_QE_VRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_VRA_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PDP_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PDP_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDP_STAT_QCH_ENABLE, 0, 1, QCH_CON_SSMT_PDP_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDP_STAT_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_PDP_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDP_STAT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_PDP_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_PDP_STAT_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_PDP_STAT_QCH), + SFR_ACCESS(QCH_CON_SSMT_VRA_QCH_ENABLE, 0, 1, QCH_CON_SSMT_VRA_QCH), + SFR_ACCESS(QCH_CON_SSMT_VRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_VRA_QCH), + SFR_ACCESS(QCH_CON_SSMT_VRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_VRA_QCH), + SFR_ACCESS(QCH_CON_SSMT_VRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_VRA_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PDP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PDP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PDP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PDP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PDP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PDP_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PDP_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PDP_QCH), + SFR_ACCESS(QCH_CON_VRA_QCH_ENABLE, 0, 1, QCH_CON_VRA_QCH), + SFR_ACCESS(QCH_CON_VRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_VRA_QCH), + SFR_ACCESS(QCH_CON_VRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VRA_QCH), + SFR_ACCESS(QCH_CON_VRA_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_VRA_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC0_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC0_QCH), + SFR_ACCESS(DMYQCH_CON_I3C1_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C1_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C1_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C1_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C1_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C1_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C1_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C1_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C1_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C1_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C1_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C1_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C1_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C1_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C2_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C2_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C2_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C2_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C2_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C2_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C2_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C2_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C2_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C2_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C2_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C2_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C2_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C2_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C3_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C3_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C3_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C3_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C3_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C3_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C3_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C3_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C3_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C3_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C3_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C3_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C3_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C3_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C4_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C4_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C4_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C4_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C4_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C4_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C4_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C4_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C4_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C4_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C4_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C4_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C4_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C4_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C5_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C5_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C5_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C5_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C5_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C5_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C5_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C5_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C5_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C5_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C5_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C5_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C5_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C5_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C6_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C6_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C6_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C6_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C6_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C6_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C6_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C6_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C6_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C6_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C6_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C6_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C6_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C6_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C7_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C7_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C7_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C7_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C7_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C7_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C7_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C7_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C7_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C7_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C7_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C7_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C7_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C7_QCH_PCLK), + SFR_ACCESS(DMYQCH_CON_I3C8_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C8_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C8_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C8_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C8_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C8_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C8_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C8_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C8_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C8_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C8_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C8_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C8_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C8_QCH_PCLK), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH), + SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH), + SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH), + SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_CMU_PERIC0_QCH), + SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC0_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC0_QCH), + SFR_ACCESS(QCH_CON_USI0_UART_QCH_ENABLE, 0, 1, QCH_CON_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_USI0_UART_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_USI0_UART_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_USI0_UART_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI0_UART_QCH), + SFR_ACCESS(QCH_CON_USI14_USI_QCH_ENABLE, 0, 1, QCH_CON_USI14_USI_QCH), + SFR_ACCESS(QCH_CON_USI14_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI14_USI_QCH), + SFR_ACCESS(QCH_CON_USI14_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI14_USI_QCH), + SFR_ACCESS(QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI14_USI_QCH), + SFR_ACCESS(QCH_CON_USI1_USI_QCH_ENABLE, 0, 1, QCH_CON_USI1_USI_QCH), + SFR_ACCESS(QCH_CON_USI1_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI1_USI_QCH), + SFR_ACCESS(QCH_CON_USI1_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI1_USI_QCH), + SFR_ACCESS(QCH_CON_USI1_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI1_USI_QCH), + SFR_ACCESS(QCH_CON_USI2_USI_QCH_ENABLE, 0, 1, QCH_CON_USI2_USI_QCH), + SFR_ACCESS(QCH_CON_USI2_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI2_USI_QCH), + SFR_ACCESS(QCH_CON_USI2_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI2_USI_QCH), + SFR_ACCESS(QCH_CON_USI2_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI2_USI_QCH), + SFR_ACCESS(QCH_CON_USI3_USI_QCH_ENABLE, 0, 1, QCH_CON_USI3_USI_QCH), + SFR_ACCESS(QCH_CON_USI3_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI3_USI_QCH), + SFR_ACCESS(QCH_CON_USI3_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI3_USI_QCH), + SFR_ACCESS(QCH_CON_USI3_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI3_USI_QCH), + SFR_ACCESS(QCH_CON_USI4_USI_QCH_ENABLE, 0, 1, QCH_CON_USI4_USI_QCH), + SFR_ACCESS(QCH_CON_USI4_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI4_USI_QCH), + SFR_ACCESS(QCH_CON_USI4_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI4_USI_QCH), + SFR_ACCESS(QCH_CON_USI4_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI4_USI_QCH), + SFR_ACCESS(QCH_CON_USI5_USI_QCH_ENABLE, 0, 1, QCH_CON_USI5_USI_QCH), + SFR_ACCESS(QCH_CON_USI5_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI5_USI_QCH), + SFR_ACCESS(QCH_CON_USI5_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI5_USI_QCH), + SFR_ACCESS(QCH_CON_USI5_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI5_USI_QCH), + SFR_ACCESS(QCH_CON_USI6_USI_QCH_ENABLE, 0, 1, QCH_CON_USI6_USI_QCH), + SFR_ACCESS(QCH_CON_USI6_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI6_USI_QCH), + SFR_ACCESS(QCH_CON_USI6_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI6_USI_QCH), + SFR_ACCESS(QCH_CON_USI6_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI6_USI_QCH), + SFR_ACCESS(QCH_CON_USI7_USI_QCH_ENABLE, 0, 1, QCH_CON_USI7_USI_QCH), + SFR_ACCESS(QCH_CON_USI7_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI7_USI_QCH), + SFR_ACCESS(QCH_CON_USI7_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI7_USI_QCH), + SFR_ACCESS(QCH_CON_USI7_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI7_USI_QCH), + SFR_ACCESS(QCH_CON_USI8_USI_QCH_ENABLE, 0, 1, QCH_CON_USI8_USI_QCH), + SFR_ACCESS(QCH_CON_USI8_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI8_USI_QCH), + SFR_ACCESS(QCH_CON_USI8_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI8_USI_QCH), + SFR_ACCESS(QCH_CON_USI8_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI8_USI_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC1_QCH), + SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPIO_PERIC1_QCH), + SFR_ACCESS(DMYQCH_CON_I3C0_QCH_SCLK_ENABLE, 0, 1, DMYQCH_CON_I3C0_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C0_QCH_SCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_I3C0_QCH_SCLK), + SFR_ACCESS(DMYQCH_CON_I3C0_QCH_SCLK_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_I3C0_QCH_SCLK), + SFR_ACCESS(QCH_CON_I3C0_QCH_PCLK_ENABLE, 0, 1, QCH_CON_I3C0_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C0_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_I3C0_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C0_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_I3C0_QCH_PCLK), + SFR_ACCESS(QCH_CON_I3C0_QCH_PCLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_I3C0_QCH_PCLK), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH), + SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH), + SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH), + SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_CMU_PERIC1_QCH), + SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH), + SFR_ACCESS(QCH_CON_PWM_QCH_ENABLE, 0, 1, QCH_CON_PWM_QCH), + SFR_ACCESS(QCH_CON_PWM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_QCH), + SFR_ACCESS(QCH_CON_PWM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_QCH), + SFR_ACCESS(QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PWM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC1_QCH), + SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_PERIC1_QCH), + SFR_ACCESS(QCH_CON_USI0_USI_QCH_ENABLE, 0, 1, QCH_CON_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_USI0_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_USI0_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_USI0_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI0_USI_QCH), + SFR_ACCESS(QCH_CON_USI10_USI_QCH_ENABLE, 0, 1, QCH_CON_USI10_USI_QCH), + SFR_ACCESS(QCH_CON_USI10_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_USI_QCH), + SFR_ACCESS(QCH_CON_USI10_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI10_USI_QCH), + SFR_ACCESS(QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI10_USI_QCH), + SFR_ACCESS(QCH_CON_USI11_USI_QCH_ENABLE, 0, 1, QCH_CON_USI11_USI_QCH), + SFR_ACCESS(QCH_CON_USI11_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_USI_QCH), + SFR_ACCESS(QCH_CON_USI11_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI11_USI_QCH), + SFR_ACCESS(QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI11_USI_QCH), + SFR_ACCESS(QCH_CON_USI12_USI_QCH_ENABLE, 0, 1, QCH_CON_USI12_USI_QCH), + SFR_ACCESS(QCH_CON_USI12_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI12_USI_QCH), + SFR_ACCESS(QCH_CON_USI12_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI12_USI_QCH), + SFR_ACCESS(QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI12_USI_QCH), + SFR_ACCESS(QCH_CON_USI13_USI_QCH_ENABLE, 0, 1, QCH_CON_USI13_USI_QCH), + SFR_ACCESS(QCH_CON_USI13_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI13_USI_QCH), + SFR_ACCESS(QCH_CON_USI13_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI13_USI_QCH), + SFR_ACCESS(QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI13_USI_QCH), + SFR_ACCESS(QCH_CON_USI15_USI_QCH_ENABLE, 0, 1, QCH_CON_USI15_USI_QCH), + SFR_ACCESS(QCH_CON_USI15_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI15_USI_QCH), + SFR_ACCESS(QCH_CON_USI15_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI15_USI_QCH), + SFR_ACCESS(QCH_CON_USI15_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI15_USI_QCH), + SFR_ACCESS(QCH_CON_USI16_USI_QCH_ENABLE, 0, 1, QCH_CON_USI16_USI_QCH), + SFR_ACCESS(QCH_CON_USI16_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI16_USI_QCH), + SFR_ACCESS(QCH_CON_USI16_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI16_USI_QCH), + SFR_ACCESS(QCH_CON_USI16_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI16_USI_QCH), + SFR_ACCESS(QCH_CON_USI9_USI_QCH_ENABLE, 0, 1, QCH_CON_USI9_USI_QCH), + SFR_ACCESS(QCH_CON_USI9_USI_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI9_USI_QCH), + SFR_ACCESS(QCH_CON_USI9_USI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI9_USI_QCH), + SFR_ACCESS(QCH_CON_USI9_USI_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_USI9_USI_QCH), + SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_ENABLE, 0, 1, DMYQCH_CON_BIS_S2D_QCH), + SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_BIS_S2D_QCH), + SFR_ACCESS(DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_BIS_S2D_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH), + SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_ENABLE, 0, 1, QCH_CON_S2D_CMU_S2D_QCH), + SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_S2D_CMU_S2D_QCH), + SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_S2D_CMU_S2D_QCH), + SFR_ACCESS(QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_S2D_CMU_S2D_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_TNR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_TNR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_TNR_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_TNR_QCH), + SFR_ACCESS(QCH_CON_GPC_TNR_QCH_ENABLE, 0, 1, QCH_CON_GPC_TNR_QCH), + SFR_ACCESS(QCH_CON_GPC_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_TNR_QCH), + SFR_ACCESS(QCH_CON_GPC_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_TNR_QCH), + SFR_ACCESS(QCH_CON_GPC_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_ENABLE, 0, 1, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D2_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D3_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_TNR_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_D4_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D2_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D3_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D4_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D4_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D4_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D4_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D5_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D5_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D5_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D5_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D6_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D6_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D6_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D6_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D7_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D7_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D7_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D7_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D8_TNR_QCH_ENABLE, 0, 1, QCH_CON_PPMU_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D8_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D8_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_PPMU_D8_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D5_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D5_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D5_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D5_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D6_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D6_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D6_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D6_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D7_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D7_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D7_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D7_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D8_TNR_QCH_ENABLE, 0, 1, QCH_CON_QE_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D8_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D8_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_QE_D8_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_QE_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D0_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D0_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D1_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D1_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D2_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D2_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D3_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D3_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D4_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D4_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D4_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D4_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D4_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D5_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D5_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D5_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D5_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D5_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D6_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D6_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D6_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D6_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D6_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D7_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D7_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D7_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D7_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D7_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D8_TNR_QCH_ENABLE, 0, 1, QCH_CON_SSMT_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D8_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D8_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_SSMT_D8_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_D8_TNR_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D0_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D0_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D1_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D1_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D2_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D2_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D2_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D3_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D3_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D3_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D4_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_D4_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_D4_TNR_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_D4_TNR_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_TNR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_TNR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_TNR_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_TNR_QCH), + SFR_ACCESS(QCH_CON_TNR_QCH_C2_ENABLE, 0, 1, QCH_CON_TNR_QCH_C2), + SFR_ACCESS(QCH_CON_TNR_QCH_C2_CLOCK_REQ, 1, 1, QCH_CON_TNR_QCH_C2), + SFR_ACCESS(QCH_CON_TNR_QCH_C2_EXPIRE_VAL, 16, 10, QCH_CON_TNR_QCH_C2), + SFR_ACCESS(QCH_CON_TNR_QCH_C2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_QCH_C2), + SFR_ACCESS(QCH_CON_TNR_QCH_ACLK_ENABLE, 0, 1, QCH_CON_TNR_QCH_ACLK), + SFR_ACCESS(QCH_CON_TNR_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_TNR_QCH_ACLK), + SFR_ACCESS(QCH_CON_TNR_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_TNR_QCH_ACLK), + SFR_ACCESS(QCH_CON_TNR_QCH_ACLK_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_QCH_ACLK), + SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_ENABLE, 0, 1, QCH_CON_TNR_CMU_TNR_QCH), + SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, 1, 1, QCH_CON_TNR_CMU_TNR_QCH), + SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TNR_CMU_TNR_QCH), + SFR_ACCESS(QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TNR_CMU_TNR_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMTPU_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMTPU_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMTPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMTPU_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMTPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMTPU_QCH), + SFR_ACCESS(QCH_CON_BUSIF_HPMTPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_BUSIF_HPMTPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TPU_QCH_ENABLE, 0, 1, QCH_CON_D_TZPC_TPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_D_TZPC_TPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_D_TZPC_TPU_QCH), + SFR_ACCESS(QCH_CON_D_TZPC_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_D_TZPC_TPU_QCH), + SFR_ACCESS(QCH_CON_GPC_TPU_QCH_ENABLE, 0, 1, QCH_CON_GPC_TPU_QCH), + SFR_ACCESS(QCH_CON_GPC_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPC_TPU_QCH), + SFR_ACCESS(QCH_CON_GPC_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPC_TPU_QCH), + SFR_ACCESS(QCH_CON_GPC_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_GPC_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_TPU_QCH_ENABLE, 0, 1, QCH_CON_LH_ACEL_SI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ACEL_SI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ACEL_SI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ACEL_SI_D_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ACEL_SI_D_TPU_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, 0, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_MI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_ENABLE, 0, 1, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_LH_AXI_SI_P_TPU_CU_QCH), + SFR_ACCESS(QCH_CON_PPMU_TPU_QCH_ENABLE, 0, 1, QCH_CON_PPMU_TPU_QCH), + SFR_ACCESS(QCH_CON_PPMU_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPMU_TPU_QCH), + SFR_ACCESS(QCH_CON_PPMU_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPMU_TPU_QCH), + SFR_ACCESS(QCH_CON_PPMU_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_PPMU_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TPU_QCH_ENABLE, 0, 1, QCH_CON_SLH_AXI_MI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SLH_AXI_MI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SLH_AXI_MI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SLH_AXI_MI_P_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SLH_AXI_MI_P_TPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_TPU_QCH_ENABLE, 0, 1, QCH_CON_SSMT_TPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSMT_TPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSMT_TPU_QCH), + SFR_ACCESS(QCH_CON_SSMT_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SSMT_TPU_QCH), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S1_ENABLE, 0, 1, QCH_CON_SYSMMU_TPU_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_TPU_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_TPU_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S1_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_TPU_QCH_S1), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S2_ENABLE, 0, 1, QCH_CON_SYSMMU_TPU_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S2_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_TPU_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S2_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_TPU_QCH_S2), + SFR_ACCESS(QCH_CON_SYSMMU_TPU_QCH_S2_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSMMU_TPU_QCH_S2), + SFR_ACCESS(QCH_CON_SYSREG_TPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_TPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_TPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_TPU_QCH), + SFR_ACCESS(QCH_CON_SYSREG_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_SYSREG_TPU_QCH), + SFR_ACCESS(DMYQCH_CON_TPU_QCH_ENABLE, 0, 1, DMYQCH_CON_TPU_QCH), + SFR_ACCESS(DMYQCH_CON_TPU_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_TPU_QCH), + SFR_ACCESS(DMYQCH_CON_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, DMYQCH_CON_TPU_QCH), + SFR_ACCESS(QCH_CON_TPU_CMU_TPU_QCH_ENABLE, 0, 1, QCH_CON_TPU_CMU_TPU_QCH), + SFR_ACCESS(QCH_CON_TPU_CMU_TPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_TPU_CMU_TPU_QCH), + SFR_ACCESS(QCH_CON_TPU_CMU_TPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TPU_CMU_TPU_QCH), + SFR_ACCESS(QCH_CON_TPU_CMU_TPU_QCH_IGNORE_FORCE_PM_EN, 2, 1, QCH_CON_TPU_CMU_TPU_QCH), + SFR_ACCESS(AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, AOC_CMU_AOC_CONTROLLER_OPTION), + SFR_ACCESS(AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AOC_CMU_AOC_CONTROLLER_OPTION), + SFR_ACCESS(APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, APM_CMU_APM_CONTROLLER_OPTION), + SFR_ACCESS(APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, APM_CMU_APM_CONTROLLER_OPTION), + SFR_ACCESS(AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, AUR_CMU_AUR_CONTROLLER_OPTION), + SFR_ACCESS(AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, AUR_CMU_AUR_CONTROLLER_OPTION), + SFR_ACCESS(BO_CMU_BO_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, BO_CMU_BO_CONTROLLER_OPTION), + SFR_ACCESS(BO_CMU_BO_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BO_CMU_BO_CONTROLLER_OPTION), + SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_TOP_CONTROLLER_OPTION), + SFR_ACCESS(CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_TOP_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION), + SFR_ACCESS(CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION), + SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION), + SFR_ACCESS(CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CSIS_CMU_CSIS_CONTROLLER_OPTION), + SFR_ACCESS(DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DISP_CMU_DISP_CONTROLLER_OPTION), + SFR_ACCESS(DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DISP_CMU_DISP_CONTROLLER_OPTION), + SFR_ACCESS(DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DNS_CMU_DNS_CONTROLLER_OPTION), + SFR_ACCESS(DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DNS_CMU_DNS_CONTROLLER_OPTION), + SFR_ACCESS(DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, DPU_CMU_DPU_CONTROLLER_OPTION), + SFR_ACCESS(DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPU_CMU_DPU_CONTROLLER_OPTION), + SFR_ACCESS(EH_CMU_EH_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, EH_CMU_EH_CONTROLLER_OPTION), + SFR_ACCESS(EH_CMU_EH_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, EH_CMU_EH_CONTROLLER_OPTION), + SFR_ACCESS(G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G2D_CMU_G2D_CONTROLLER_OPTION), + SFR_ACCESS(G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G2D_CMU_G2D_CONTROLLER_OPTION), + SFR_ACCESS(G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3AA_CMU_G3AA_CONTROLLER_OPTION), + SFR_ACCESS(G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3AA_CMU_G3AA_CONTROLLER_OPTION), + SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_G3D_CONTROLLER_OPTION), + SFR_ACCESS(G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_G3D_CONTROLLER_OPTION), + SFR_ACCESS(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION), + SFR_ACCESS(G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION), + SFR_ACCESS(GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GDC_CMU_GDC_CONTROLLER_OPTION), + SFR_ACCESS(GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GDC_CMU_GDC_CONTROLLER_OPTION), + SFR_ACCESS(GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GSACORE_CMU_GSACORE_CONTROLLER_OPTION), + SFR_ACCESS(GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GSACORE_CMU_GSACORE_CONTROLLER_OPTION), + SFR_ACCESS(GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION), + SFR_ACCESS(GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION), + SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION), + SFR_ACCESS(HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI0_CMU_HSI0_CONTROLLER_OPTION), + SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION), + SFR_ACCESS(HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI1_CMU_HSI1_CONTROLLER_OPTION), + SFR_ACCESS(HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, HSI2_CMU_HSI2_CONTROLLER_OPTION), + SFR_ACCESS(HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, HSI2_CMU_HSI2_CONTROLLER_OPTION), + SFR_ACCESS(IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, IPP_CMU_IPP_CONTROLLER_OPTION), + SFR_ACCESS(IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, IPP_CMU_IPP_CONTROLLER_OPTION), + SFR_ACCESS(ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, ITP_CMU_ITP_CONTROLLER_OPTION), + SFR_ACCESS(ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ITP_CMU_ITP_CONTROLLER_OPTION), + SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION), + SFR_ACCESS(MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MCSC_CMU_MCSC_CONTROLLER_OPTION), + SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MFC_CMU_MFC_CONTROLLER_OPTION), + SFR_ACCESS(MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC_CMU_MFC_CONTROLLER_OPTION), + SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_MIF_CONTROLLER_OPTION), + SFR_ACCESS(MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_MIF_CONTROLLER_OPTION), + SFR_ACCESS(MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, MISC_CMU_MISC_CONTROLLER_OPTION), + SFR_ACCESS(MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MISC_CMU_MISC_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_CMU_NOCL0_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_CMU_NOCL0_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION), + SFR_ACCESS(NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION), + SFR_ACCESS(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION), + SFR_ACCESS(NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION), + SFR_ACCESS(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION), + SFR_ACCESS(NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION), + SFR_ACCESS(NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION), + SFR_ACCESS(NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION), + SFR_ACCESS(PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PDP_CMU_PDP_CONTROLLER_OPTION), + SFR_ACCESS(PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PDP_CMU_PDP_CONTROLLER_OPTION), + SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION), + SFR_ACCESS(PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC0_CMU_PERIC0_CONTROLLER_OPTION), + SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION), + SFR_ACCESS(PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION), + SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, S2D_CMU_S2D_CONTROLLER_OPTION), + SFR_ACCESS(S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, S2D_CMU_S2D_CONTROLLER_OPTION), + SFR_ACCESS(TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, TNR_CMU_TNR_CONTROLLER_OPTION), + SFR_ACCESS(TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, TNR_CMU_TNR_CONTROLLER_OPTION), + SFR_ACCESS(TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, 29, 1, TPU_CMU_TPU_CONTROLLER_OPTION), + SFR_ACCESS(TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, 28, 1, TPU_CMU_TPU_CONTROLLER_OPTION), +}; diff --git a/drivers/soc/google/cal-if/gs201/cmucal-sfr.h b/drivers/soc/google/cal-if/gs201/cmucal-sfr.h new file mode 100644 index 000000000000..e80376124b5b --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-sfr.h @@ -0,0 +1,17440 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMUCAL_SFR_H__ +#define __CMUCAL_SFR_H__ + +#include "../cmucal.h" + +enum sfr_block_id { + CMU_AUR = SFR_BLOCK_TYPE, + CMU_TOP, + CMU_CPUCL0, + CMU_CPUCL1, + CMU_CPUCL2, + CMU_G3D, + CMU_HSI0, + CMU_MIF, + CMU_NOCL0, + CMU_S2D, + CMU_TPU, + CMU_APM, + CMU_EH, + CMU_GSACORE, + CMU_GSACTRL, + CMU_NOCL1A, + CMU_NOCL1B, + CMU_NOCL2A, + CMU_BO, + CMU_CSIS, + CMU_DISP, + CMU_DNS, + CMU_DPU, + CMU_G2D, + CMU_G3AA, + CMU_GDC, + CMU_HSI1, + CMU_HSI2, + CMU_IPP, + CMU_ITP, + CMU_MCSC, + CMU_MFC, + CMU_MISC, + CMU_PDP, + CMU_PERIC0, + CMU_PERIC1, + CMU_TNR, + CMU_AOC, + end_of_sfr_block, + num_of_sfr_block = end_of_sfr_block - SFR_BLOCK_TYPE, +}; + +enum sfr_id { + PLL_LOCKTIME_PLL_AUR = SFR_TYPE, + PLL_CON3_PLL_AUR, + PLL_CON4_PLL_AUR, + DBG_NFO_PLL_AUR, + PLL_CON0_PLL_AUR, + PLL_CON1_PLL_AUR, + PLL_CON2_PLL_AUR, + PLL_LOCKTIME_PLL_SHARED0, + PLL_CON3_PLL_SHARED0, + PLL_CON4_PLL_SHARED0, + DBG_NFO_PLL_SHARED0, + PLL_CON0_PLL_SHARED0, + PLL_CON1_PLL_SHARED0, + PLL_CON2_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_CON3_PLL_SHARED1, + PLL_CON4_PLL_SHARED1, + DBG_NFO_PLL_SHARED1, + PLL_CON0_PLL_SHARED1, + PLL_CON1_PLL_SHARED1, + PLL_CON2_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_CON3_PLL_SHARED2, + PLL_CON4_PLL_SHARED2, + DBG_NFO_PLL_SHARED2, + PLL_CON0_PLL_SHARED2, + PLL_CON1_PLL_SHARED2, + PLL_CON2_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_CON3_PLL_SHARED3, + PLL_CON4_PLL_SHARED3, + DBG_NFO_PLL_SHARED3, + PLL_CON0_PLL_SHARED3, + PLL_CON1_PLL_SHARED3, + PLL_CON2_PLL_SHARED3, + PLL_LOCKTIME_PLL_SPARE, + PLL_CON3_PLL_SPARE, + PLL_CON4_PLL_SPARE, + DBG_NFO_PLL_SPARE, + PLL_CON0_PLL_SPARE, + PLL_CON1_PLL_SPARE, + PLL_CON2_PLL_SPARE, + PLL_LOCKTIME_PLL_LF_MIF, + PLL_CON3_PLL_LF_MIF, + PLL_CON4_PLL_LF_MIF, + DBG_NFO_PLL_LF_MIF, + PLL_CON0_PLL_LF_MIF, + PLL_CON1_PLL_LF_MIF, + PLL_CON2_PLL_LF_MIF, + PLL_LOCKTIME_PLL_CPUCL0, + PLL_CON3_PLL_CPUCL0, + PLL_CON4_PLL_CPUCL0, + DBG_NFO_PLL_CPUCL0, + PLL_CON0_PLL_CPUCL0, + PLL_CON1_PLL_CPUCL0, + PLL_CON2_PLL_CPUCL0, + PLL_LOCKTIME_PLL_CPUCL1, + PLL_CON3_PLL_CPUCL1, + PLL_CON4_PLL_CPUCL1, + DBG_NFO_PLL_CPUCL1, + PLL_CON0_PLL_CPUCL1, + PLL_CON1_PLL_CPUCL1, + PLL_CON2_PLL_CPUCL1, + PLL_LOCKTIME_PLL_CPUCL2, + PLL_CON3_PLL_CPUCL2, + PLL_CON4_PLL_CPUCL2, + DBG_NFO_PLL_CPUCL2, + PLL_CON0_PLL_CPUCL2, + PLL_CON1_PLL_CPUCL2, + PLL_CON2_PLL_CPUCL2, + PLL_CON6_PLL_CPUCL2, + PLL_LOCKTIME_REG_PLL_CPUCL2, + PLL_LOCKTIME_PLL_G3D, + PLL_CON3_PLL_G3D, + PLL_CON4_PLL_G3D, + DBG_NFO_PLL_G3D, + PLL_CON0_PLL_G3D, + PLL_CON1_PLL_G3D, + PLL_CON2_PLL_G3D, + PLL_LOCKTIME_PLL_G3D_L2, + PLL_CON3_PLL_G3D_L2, + PLL_CON4_PLL_G3D_L2, + DBG_NFO_PLL_G3D_L2, + PLL_CON0_PLL_G3D_L2, + PLL_CON1_PLL_G3D_L2, + PLL_CON2_PLL_G3D_L2, + PLL_LOCKTIME_PLL_USB, + PLL_CON3_PLL_USB, + PLL_CON4_PLL_USB, + DBG_NFO_PLL_USB, + PLL_CON0_PLL_USB, + PLL_CON1_PLL_USB, + PLL_CON2_PLL_USB, + PLL_LOCKTIME_PLL_MIF_MAIN, + PLL_CON3_PLL_MIF_MAIN, + PLL_CON4_PLL_MIF_MAIN, + DBG_NFO_PLL_MIF_MAIN, + PLL_CON0_PLL_MIF_MAIN, + PLL_CON1_PLL_MIF_MAIN, + PLL_CON2_PLL_MIF_MAIN, + PLL_CON6_PLL_MIF_MAIN, + PLL_LOCKTIME_REG_PLL_MIF_MAIN, + PLL_LOCKTIME_PLL_MIF_SUB, + PLL_CON3_PLL_MIF_SUB, + PLL_CON4_PLL_MIF_SUB, + DBG_NFO_PLL_MIF_SUB, + PLL_CON0_PLL_MIF_SUB, + PLL_CON1_PLL_MIF_SUB, + PLL_CON2_PLL_MIF_SUB, + PLL_CON6_PLL_MIF_SUB, + PLL_LOCKTIME_REG_PLL_MIF_SUB, + PLL_LOCKTIME_PLL_NOCL0, + PLL_CON3_PLL_NOCL0, + PLL_CON4_PLL_NOCL0, + DBG_NFO_PLL_NOCL0, + PLL_CON0_PLL_NOCL0, + PLL_CON1_PLL_NOCL0, + PLL_CON2_PLL_NOCL0, + PLL_LOCKTIME_PLL_MIF_S2D, + PLL_CON3_PLL_MIF_S2D, + PLL_CON4_PLL_MIF_S2D, + DBG_NFO_PLL_MIF_S2D, + PLL_CON0_PLL_MIF_S2D, + PLL_CON1_PLL_MIF_S2D, + PLL_CON2_PLL_MIF_S2D, + PLL_CON6_PLL_MIF_S2D, + PLL_LOCKTIME_REG_PLL_MIF_S2D, + PLL_LOCKTIME_PLL_TPU, + PLL_CON3_PLL_TPU, + PLL_CON4_PLL_TPU, + DBG_NFO_PLL_TPU, + PLL_CON0_PLL_TPU, + PLL_CON1_PLL_TPU, + PLL_CON2_PLL_TPU, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, + DBG_NFO_MUX_CLKCMU_APM_FUNC, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, + DBG_NFO_MUX_CLKCMU_APM_FUNCSRC, + CLK_CON_MUX_MUX_CLK_AUR_AUR, + DBG_NFO_MUX_CLK_AUR_AUR, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, + DBG_NFO_MUX_CLKCMU_MFC_MFC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD, + DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, + DBG_NFO_MUX_CLKCMU_G2D_G2D, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC, + DBG_NFO_MUX_CLKCMU_CSIS_NOC, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC, + DBG_NFO_MUX_CLKCMU_NOCL0_NOC, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + DBG_NFO_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_ITP_NOC, + DBG_NFO_MUX_CLKCMU_ITP_NOC, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, + DBG_NFO_MUX_CLKCMU_G3AA_G3AA, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, + DBG_NFO_MUX_CLKCMU_MCSC_ITSC, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, + DBG_NFO_MUX_CLKCMU_G2D_MSCL, + CLK_CON_MUX_MUX_CLKCMU_HPM, + DBG_NFO_MUX_CLKCMU_HPM, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, + DBG_NFO_MUX_CLKCMU_CPUCL0_DBG, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC, + DBG_NFO_MUX_CLKCMU_HSI1_NOC, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, + DBG_NFO_MUX_CLKCMU_CIS_CLK0, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, + DBG_NFO_MUX_CLKCMU_CIS_CLK1, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, + DBG_NFO_MUX_CLKCMU_CIS_CLK2, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, + DBG_NFO_MUX_CLKCMU_CIS_CLK3, + CLK_CON_MUX_MUX_CLKCMU_BO_NOC, + DBG_NFO_MUX_CLKCMU_BO_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD, + DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_MUX_MUX_CMU_CMUREF, + DBG_NFO_MUX_CMU_CMUREF, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC, + DBG_NFO_MUX_CLKCMU_PERIC0_NOC, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC, + DBG_NFO_MUX_CLKCMU_PERIC1_NOC, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC, + DBG_NFO_MUX_CLKCMU_MISC_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, + DBG_NFO_MUX_CLKCMU_HSI0_DPGTC, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, + DBG_NFO_MUX_CLKCMU_HSI2_PCIE, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC, + DBG_NFO_MUX_CLKCMU_HSI2_NOC, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP, + DBG_NFO_MUX_CLKCMU_MIF_NOCP, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, + DBG_NFO_MUX_CLKCMU_PERIC0_IP, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, + DBG_NFO_MUX_CLKCMU_PERIC1_IP, + CLK_CON_MUX_MUX_CLKCMU_TPU_NOC, + DBG_NFO_MUX_CLKCMU_TPU_NOC, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG, + DBG_NFO_MUX_CLKCMU_HSI0_USBDPDBG, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, + DBG_NFO_MUX_CLKCMU_PDP_VRA, + CLK_CON_MUX_MUX_CLKCMU_DPU_NOC, + DBG_NFO_MUX_CLKCMU_DPU_NOC, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, + DBG_NFO_MUX_CLKCMU_HSI1_PCIE, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC, + DBG_NFO_MUX_CLKCMU_HSI0_NOC, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, + DBG_NFO_MUX_CLKCMU_TOP_CMUREF, + CLK_CON_MUX_MUX_CLKCMU_IPP_NOC, + DBG_NFO_MUX_CLKCMU_IPP_NOC, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, + DBG_NFO_MUX_CLKCMU_CIS_CLK4, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, + DBG_NFO_MUX_CLKCMU_CMU_BOOST, + CLK_CON_MUX_MUX_CLKCMU_TNR_NOC, + DBG_NFO_MUX_CLKCMU_TNR_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC, + DBG_NFO_MUX_CLKCMU_NOCL2A_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC, + DBG_NFO_MUX_CLKCMU_NOCL1A_NOC, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC, + DBG_NFO_MUX_CLKCMU_NOCL1B_NOC, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, + DBG_NFO_MUX_CLKCMU_CIS_CLK5, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, + DBG_NFO_MUX_CLKCMU_CIS_CLK6, + CLK_CON_MUX_MUX_CLKCMU_DNS_NOC, + DBG_NFO_MUX_CLKCMU_DNS_NOC, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, + DBG_NFO_MUX_CLKCMU_GDC_GDC0, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, + DBG_NFO_MUX_CLKCMU_GDC_GDC1, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, + DBG_NFO_MUX_CLKCMU_MCSC_MCSC, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, + DBG_NFO_MUX_CLKCMU_TPU_TPU, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD, + DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, + DBG_NFO_MUX_CLKCMU_CIS_CLK7, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, + DBG_NFO_MUX_CLKCMU_G3D_GLB, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH, + DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, + DBG_NFO_MUX_CLKCMU_GDC_SCSC, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, + DBG_NFO_MUX_CLKCMU_MISC_SSS, + CLK_CON_MUX_MUX_CLKCMU_DISP_NOC, + DBG_NFO_MUX_CLKCMU_DISP_NOC, + CLK_CON_MUX_MUX_CLKCMU_EH_NOC, + DBG_NFO_MUX_CLKCMU_EH_NOC, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, + DBG_NFO_MUX_CLKCMU_CMU_BOOST_OPTION1, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, + DBG_NFO_MUX_CLKCMU_TOP_BOOST_OPTION1, + CLK_CON_MUX_MUX_CLKCMU_PDP_NOC, + DBG_NFO_MUX_CLKCMU_PDP_NOC, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART, + DBG_NFO_MUX_CLKCMU_TPU_UART, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, + DBG_NFO_MUX_CLKCMU_TPU_TPUCTL, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + DBG_NFO_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD, + DBG_NFO_MUX_CLKCMU_G3D_NOCD, + CLK_CON_MUX_MUX_CLKCMU_AUR_AUR, + DBG_NFO_MUX_CLKCMU_AUR_AUR, + CLK_CON_MUX_MUX_CLKCMU_AUR_NOC, + DBG_NFO_MUX_CLKCMU_AUR_NOC, + CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL, + DBG_NFO_MUX_CLKCMU_AUR_AURCTL, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, + DBG_NFO_MUX_CLK_CPUCL0_PLL, + CLK_CON_MUX_MUX_CPUCL0_CMUREF, + DBG_NFO_MUX_CPUCL0_CMUREF, + CLK_CON_MUX_MUX_CPUCL1_CMUREF, + DBG_NFO_MUX_CPUCL1_CMUREF, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, + DBG_NFO_MUX_CLK_CPUCL1_PLL, + CLK_CON_MUX_MUX_CLK_CPUCL2_PLL, + DBG_NFO_MUX_CLK_CPUCL2_PLL, + CLK_CON_MUX_MUX_CPUCL2_CMUREF, + DBG_NFO_MUX_CPUCL2_CMUREF, + CLK_CON_MUX_MUX_CLK_EH_NOC, + DBG_NFO_MUX_CLK_EH_NOC, + CLK_CON_MUX_MUX_CLK_G3D_STACKS, + DBG_NFO_MUX_CLK_G3D_STACKS, + CLK_CON_MUX_MUX_CLK_G3D_L2_GLB, + DBG_NFO_MUX_CLK_G3D_L2_GLB, + CLK_CON_MUX_MUX_CLK_G3D_TOP, + DBG_NFO_MUX_CLK_G3D_TOP, + CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH, + DBG_NFO_MUX_CLK_GSACORE_CPU_HCH, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC, + DBG_NFO_MUX_CLKCMU_GSA_FUNC, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC, + DBG_NFO_MUX_CLKCMU_GSA_FUNCSRC, + CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, + DBG_NFO_MUX_CLK_HSI0_USB31DRD, + CLK_CON_MUX_MUX_CLK_HSI0_NOC, + DBG_NFO_MUX_CLK_HSI0_NOC, + CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, + DBG_NFO_MUX_CLK_HSI0_USB20_REF, + CLK_CON_MUX_MUX_MIF_CMUREF, + DBG_NFO_MUX_MIF_CMUREF, + CLK_CON_MUX_MUX_NOCL0_CMUREF, + DBG_NFO_MUX_NOCL0_CMUREF, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC, + DBG_NFO_MUX_CLK_NOCL0_NOC, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1, + DBG_NFO_MUX_CLK_NOCL0_NOC_OPTION1, + CLK_CON_MUX_MUX_NOCL1A_CMUREF, + DBG_NFO_MUX_NOCL1A_CMUREF, + CLK_CON_MUX_MUX_NOCL1B_CMUREF, + DBG_NFO_MUX_NOCL1B_CMUREF, + CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1, + DBG_NFO_MUX_CLK_NOCL1B_NOC_OPTION1, + CLK_CON_MUX_MUX_NOCL2A_CMUREF, + DBG_NFO_MUX_NOCL2A_CMUREF, + CLK_CON_MUX_MUX_CLK_S2D_CORE, + DBG_NFO_MUX_CLK_S2D_CORE, + CLK_CON_MUX_MUX_CLK_TPU_TPU, + DBG_NFO_MUX_CLK_TPU_TPU, + CLK_CON_MUX_MUX_CLK_TPU_TPUCTL, + DBG_NFO_MUX_CLK_TPU_TPUCTL, + PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER, + PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER, + DBG_NFO_MUX_CLKCMU_AUR_SWITCH_USER, + PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER, + PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER, + DBG_NFO_MUX_CLKCMU_AUR_AURCTL_USER, + PLL_CON0_MUX_CLKCMU_AUR_NOC_USER, + PLL_CON1_MUX_CLKCMU_AUR_NOC_USER, + DBG_NFO_MUX_CLKCMU_AUR_NOC_USER, + PLL_CON0_MUX_CLKCMU_BO_NOC_USER, + PLL_CON1_MUX_CLKCMU_BO_NOC_USER, + DBG_NFO_MUX_CLKCMU_BO_NOC_USER, + PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, + PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER, + DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER, + PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, + PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, + DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_NOC_USER, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, + PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER, + DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER, + PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER, + PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER, + DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_USER, + PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER, + PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER, + DBG_NFO_MUX_CLKCMU_CSIS_NOC_USER, + PLL_CON0_MUX_CLKCMU_DISP_NOC_USER, + PLL_CON1_MUX_CLKCMU_DISP_NOC_USER, + DBG_NFO_MUX_CLKCMU_DISP_NOC_USER, + PLL_CON0_MUX_CLKCMU_DNS_NOC_USER, + PLL_CON1_MUX_CLKCMU_DNS_NOC_USER, + DBG_NFO_MUX_CLKCMU_DNS_NOC_USER, + PLL_CON0_MUX_CLKCMU_DPU_NOC_USER, + PLL_CON1_MUX_CLKCMU_DPU_NOC_USER, + DBG_NFO_MUX_CLKCMU_DPU_NOC_USER, + PLL_CON0_MUX_CLKCMU_EH_NOC_USER, + PLL_CON1_MUX_CLKCMU_EH_NOC_USER, + DBG_NFO_MUX_CLKCMU_EH_NOC_USER, + PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER, + PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER, + DBG_NFO_MUX_CLKCMU_EH_PLL_NOCL0_USER, + PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, + PLL_CON1_MUX_CLKCMU_G2D_G2D_USER, + DBG_NFO_MUX_CLKCMU_G2D_G2D_USER, + PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, + PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER, + DBG_NFO_MUX_CLKCMU_G2D_MSCL_USER, + PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER, + PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER, + DBG_NFO_MUX_CLKCMU_G3AA_G3AA_USER, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, + PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER, + DBG_NFO_MUX_CLKCMU_G3D_SWITCH_USER, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER, + PLL_CON0_MUX_CLKCMU_G3D_GLB_USER, + PLL_CON1_MUX_CLKCMU_G3D_GLB_USER, + DBG_NFO_MUX_CLKCMU_G3D_GLB_USER, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER, + PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER, + PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER, + DBG_NFO_MUX_CLKCMU_G3D_NOCD_USER, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER, + PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER, + PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER, + DBG_NFO_MUX_CLKCMU_GDC_SCSC_USER, + PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER, + PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER, + DBG_NFO_MUX_CLKCMU_GDC_GDC0_USER, + PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER, + PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER, + DBG_NFO_MUX_CLKCMU_GDC_GDC1_USER, + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, + PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER, + DBG_NFO_MUX_CLKCMU_HSI0_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, + PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER, + DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_USER, + PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, + PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER, + DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_USER, + PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, + PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER, + DBG_NFO_MUX_CLKCMU_HSI0_USPDPDBG_USER, + PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, + PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER, + DBG_NFO_MUX_CLKCMU_HSI0_ALT_USER, + PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, + PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER, + DBG_NFO_MUX_CLKCMU_HSI0_USB20_USER, + PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, + PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER, + DBG_NFO_MUX_CLKCMU_HSI0_TCXO_USER, + PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, + PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER, + DBG_NFO_MUX_CLKCMU_HSI1_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER, + PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER, + DBG_NFO_MUX_CLKCMU_HSI1_PCIE_USER, + PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER, + PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER, + DBG_NFO_MUX_CLKCMU_HSI2_NOC_USER, + PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER, + PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER, + DBG_NFO_MUX_CLKCMU_HSI2_PCIE_USER, + PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, + PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER, + DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_USER, + PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER, + PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER, + DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_IPP_NOC_USER, + PLL_CON1_MUX_CLKCMU_IPP_NOC_USER, + DBG_NFO_MUX_CLKCMU_IPP_NOC_USER, + PLL_CON0_MUX_CLKCMU_ITP_NOC_USER, + PLL_CON1_MUX_CLKCMU_ITP_NOC_USER, + DBG_NFO_MUX_CLKCMU_ITP_NOC_USER, + PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER, + PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER, + DBG_NFO_MUX_CLKCMU_MCSC_ITSC_USER, + PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER, + PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER, + DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER, + PLL_CON0_MUX_CLKCMU_MFC_MFC_USER, + PLL_CON1_MUX_CLKCMU_MFC_MFC_USER, + DBG_NFO_MUX_CLKCMU_MFC_MFC_USER, + PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER, + PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER, + DBG_NFO_MUX_CLKCMU_MIF_NOCP_USER, + PLL_CON0_CLKMUX_MIF_DDRPHY2X, + PLL_CON1_CLKMUX_MIF_DDRPHY2X, + DBG_NFO_CLKMUX_MIF_DDRPHY2X, + PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, + PLL_CON1_MUX_CLKCMU_MISC_NOC_USER, + DBG_NFO_MUX_CLKCMU_MISC_NOC_USER, + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER, + DBG_NFO_MUX_CLKCMU_MISC_SSS_USER, + PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER, + PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER, + DBG_NFO_MUX_CLKCMU_NOCL0_NOC_USER, + PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER, + PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER, + DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_USER, + PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER, + PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER, + DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_USER, + PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER, + PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER, + DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_USER, + PLL_CON0_MUX_CLKCMU_PDP_NOC_USER, + PLL_CON1_MUX_CLKCMU_PDP_NOC_USER, + DBG_NFO_MUX_CLKCMU_PDP_NOC_USER, + PLL_CON0_MUX_CLKCMU_PDP_VRA_USER, + PLL_CON1_MUX_CLKCMU_PDP_VRA_USER, + DBG_NFO_MUX_CLKCMU_PDP_VRA_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_NOC_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI6_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI3_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI4_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI5_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI14_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI7_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI8_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI1_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI0_UART_USER, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC0_USI2_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_NOC_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI11_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI12_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI0_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_I3C_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI9_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI10_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI13_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI15_USI_USER, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER, + DBG_NFO_MUX_CLKCMU_PERIC1_USI16_USI_USER, + PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D, + PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D, + DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D, + PLL_CON0_MUX_CLKCMU_TNR_NOC_USER, + PLL_CON1_MUX_CLKCMU_TNR_NOC_USER, + DBG_NFO_MUX_CLKCMU_TNR_NOC_USER, + PLL_CON0_MUX_CLKCMU_TPU_NOC_USER, + PLL_CON1_MUX_CLKCMU_TPU_NOC_USER, + DBG_NFO_MUX_CLKCMU_TPU_NOC_USER, + PLL_CON0_MUX_CLKCMU_TPU_TPU_USER, + PLL_CON1_MUX_CLKCMU_TPU_TPU_USER, + DBG_NFO_MUX_CLKCMU_TPU_TPU_USER, + PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER, + PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER, + DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_USER, + PLL_CON0_MUX_CLKCMU_TPU_UART_USER, + PLL_CON1_MUX_CLKCMU_TPU_UART_USER, + DBG_NFO_MUX_CLKCMU_TPU_UART_USER, + CLK_CON_DIV_DIV_CLK_AOC_NOC_LH, + DBG_NFO_DIV_CLK_AOC_NOC_LH, + CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH, + DBG_NFO_DIV_CLK_AOC_TRACE_LH, + CLK_CON_DIV_DIV_CLK_APM_BOOST, + DBG_NFO_DIV_CLK_APM_BOOST, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI, + DBG_NFO_DIV_CLK_APM_USI0_USI, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART, + DBG_NFO_DIV_CLK_APM_USI0_UART, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART, + DBG_NFO_DIV_CLK_APM_USI1_UART, + CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC, + DBG_NFO_DIV_CLK_APM_I3C_PMIC, + CLK_CON_DIV_DIV_CLK_APM_NOC_LH, + DBG_NFO_DIV_CLK_APM_NOC_LH, + CLK_CON_DIV_DIV_CLK_AUR_NOCP, + DBG_NFO_DIV_CLK_AUR_NOCP, + CLK_CON_DIV_CLK_AUR_ADD_CH_CLK, + DBG_NFO_CLK_AUR_ADD_CH_CLK, + CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH, + DBG_NFO_DIV_CLK_AUR_AURCTL_LH, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH, + DBG_NFO_DIV_CLK_AUR_NOCP_LH, + CLK_CON_DIV_DIV_CLK_BO_NOCP, + DBG_NFO_DIV_CLK_BO_NOCP, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, + DBG_NFO_CLKCMU_G3D_SWITCH, + CLK_CON_DIV_CLKCMU_PERIC0_NOC, + DBG_NFO_CLKCMU_PERIC0_NOC, + CLK_CON_DIV_CLKCMU_MISC_NOC, + DBG_NFO_CLKCMU_MISC_NOC, + CLK_CON_DIV_CLKCMU_HSI1_NOC, + DBG_NFO_CLKCMU_HSI1_NOC, + CLK_CON_DIV_CLKCMU_DPU_NOC, + DBG_NFO_CLKCMU_DPU_NOC, + CLK_CON_DIV_CLKCMU_MFC_MFC, + DBG_NFO_CLKCMU_MFC_MFC, + CLK_CON_DIV_CLKCMU_G2D_G2D, + DBG_NFO_CLKCMU_G2D_G2D, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, + DBG_NFO_CLKCMU_HSI0_USB31DRD, + CLK_CON_DIV_CLKCMU_CSIS_NOC, + DBG_NFO_CLKCMU_CSIS_NOC, + CLK_CON_DIV_CLKCMU_PERIC1_NOC, + DBG_NFO_CLKCMU_PERIC1_NOC, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, + DBG_NFO_CLKCMU_CPUCL0_SWITCH, + CLK_CON_DIV_CLKCMU_NOCL0_NOC, + DBG_NFO_CLKCMU_NOCL0_NOC, + CLK_CON_DIV_CLKCMU_ITP_NOC, + DBG_NFO_CLKCMU_ITP_NOC, + CLK_CON_DIV_CLKCMU_G3AA_G3AA, + DBG_NFO_CLKCMU_G3AA_G3AA, + CLK_CON_DIV_CLKCMU_MCSC_ITSC, + DBG_NFO_CLKCMU_MCSC_ITSC, + CLK_CON_DIV_CLKCMU_G2D_MSCL, + DBG_NFO_CLKCMU_G2D_MSCL, + CLK_CON_DIV_CLKCMU_HPM, + DBG_NFO_CLKCMU_HPM, + CLK_CON_DIV_CLKCMU_HSI2_PCIE, + DBG_NFO_CLKCMU_HSI2_PCIE, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, + DBG_NFO_CLKCMU_CPUCL0_DBG, + CLK_CON_DIV_CLKCMU_CIS_CLK0, + DBG_NFO_CLKCMU_CIS_CLK0, + CLK_CON_DIV_CLKCMU_CIS_CLK1, + DBG_NFO_CLKCMU_CIS_CLK1, + CLK_CON_DIV_CLKCMU_CIS_CLK2, + DBG_NFO_CLKCMU_CIS_CLK2, + CLK_CON_DIV_CLKCMU_CIS_CLK3, + DBG_NFO_CLKCMU_CIS_CLK3, + CLK_CON_DIV_CLKCMU_BO_NOC, + DBG_NFO_CLKCMU_BO_NOC, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, + DBG_NFO_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC, + DBG_NFO_CLKCMU_HSI0_DPGTC, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, + DBG_NFO_DIV_CLK_CMU_CMUREF, + CLK_CON_DIV_CLKCMU_MIF_NOCP, + DBG_NFO_CLKCMU_MIF_NOCP, + CLK_CON_DIV_CLKCMU_PERIC0_IP, + DBG_NFO_CLKCMU_PERIC0_IP, + CLK_CON_DIV_CLKCMU_PERIC1_IP, + DBG_NFO_CLKCMU_PERIC1_IP, + CLK_CON_DIV_CLKCMU_TPU_NOC, + DBG_NFO_CLKCMU_TPU_NOC, + CLK_CON_DIV_CLKCMU_PDP_VRA, + DBG_NFO_CLKCMU_PDP_VRA, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, + DBG_NFO_CLKCMU_CPUCL1_SWITCH, + CLK_CON_DIV_CLKCMU_HSI1_PCIE, + DBG_NFO_CLKCMU_HSI1_PCIE, + CLK_CON_DIV_CLKCMU_HSI0_NOC, + DBG_NFO_CLKCMU_HSI0_NOC, + CLK_CON_DIV_CLKCMU_IPP_NOC, + DBG_NFO_CLKCMU_IPP_NOC, + CLK_CON_DIV_CLKCMU_CIS_CLK4, + DBG_NFO_CLKCMU_CIS_CLK4, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, + DBG_NFO_DIV_CLKCMU_CMU_BOOST, + CLK_CON_DIV_CLKCMU_TNR_NOC, + DBG_NFO_CLKCMU_TNR_NOC, + CLK_CON_DIV_CLKCMU_NOCL2A_NOC, + DBG_NFO_CLKCMU_NOCL2A_NOC, + CLK_CON_DIV_CLKCMU_NOCL1A_NOC, + DBG_NFO_CLKCMU_NOCL1A_NOC, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC, + DBG_NFO_CLKCMU_NOCL1B_NOC, + CLK_CON_DIV_CLKCMU_CIS_CLK5, + DBG_NFO_CLKCMU_CIS_CLK5, + CLK_CON_DIV_CLKCMU_CIS_CLK6, + DBG_NFO_CLKCMU_CIS_CLK6, + CLK_CON_DIV_CLKCMU_CIS_CLK7, + DBG_NFO_CLKCMU_CIS_CLK7, + CLK_CON_DIV_CLKCMU_DNS_NOC, + DBG_NFO_CLKCMU_DNS_NOC, + CLK_CON_DIV_CLKCMU_GDC_GDC0, + DBG_NFO_CLKCMU_GDC_GDC0, + CLK_CON_DIV_CLKCMU_GDC_GDC1, + DBG_NFO_CLKCMU_GDC_GDC1, + CLK_CON_DIV_CLKCMU_MCSC_MCSC, + DBG_NFO_CLKCMU_MCSC_MCSC, + CLK_CON_DIV_CLKCMU_TPU_TPU, + DBG_NFO_CLKCMU_TPU_TPU, + CLK_CON_DIV_CLKCMU_HSI2_NOC, + DBG_NFO_CLKCMU_HSI2_NOC, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, + DBG_NFO_CLKCMU_HSI2_MMC_CARD, + CLK_CON_DIV_CLKCMU_G3D_GLB, + DBG_NFO_CLKCMU_G3D_GLB, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, + DBG_NFO_CLKCMU_CPUCL2_SWITCH, + CLK_CON_DIV_CLKCMU_GDC_SCSC, + DBG_NFO_CLKCMU_GDC_SCSC, + CLK_CON_DIV_CLKCMU_MISC_SSS, + DBG_NFO_CLKCMU_MISC_SSS, + CLK_CON_DIV_CLKCMU_DISP_NOC, + DBG_NFO_CLKCMU_DISP_NOC, + CLK_CON_DIV_CLKCMU_EH_NOC, + DBG_NFO_CLKCMU_EH_NOC, + CLK_CON_DIV_CLKCMU_PDP_NOC, + DBG_NFO_CLKCMU_PDP_NOC, + CLK_CON_DIV_CLKCMU_TPU_UART, + DBG_NFO_CLKCMU_TPU_UART, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL, + DBG_NFO_CLKCMU_TPU_TPUCTL, + CLK_CON_DIV_PLL_SHARED0_DIV5, + DBG_NFO_PLL_SHARED0_DIV5, + CLK_CON_DIV_CLKCMU_G3D_NOCD, + DBG_NFO_CLKCMU_G3D_NOCD, + CLK_CON_DIV_CLKCMU_AUR_AUR, + DBG_NFO_CLKCMU_AUR_AUR, + CLK_CON_DIV_CLKCMU_AUR_NOC, + DBG_NFO_CLKCMU_AUR_NOC, + CLK_CON_DIV_CLKCMU_AUR_AURCTL, + DBG_NFO_CLKCMU_AUR_AURCTL, + CLK_CON_DIV_PLL_SHARED0_DIV2, + DBG_NFO_PLL_SHARED0_DIV2, + CLK_CON_DIV_PLL_SHARED0_DIV4, + DBG_NFO_PLL_SHARED0_DIV4, + CLK_CON_DIV_PLL_SHARED0_DIV3, + DBG_NFO_PLL_SHARED0_DIV3, + CLK_CON_DIV_PLL_SHARED1_DIV2, + DBG_NFO_PLL_SHARED1_DIV2, + CLK_CON_DIV_PLL_SHARED1_DIV4, + DBG_NFO_PLL_SHARED1_DIV4, + CLK_CON_DIV_PLL_SHARED1_DIV3, + DBG_NFO_PLL_SHARED1_DIV3, + CLK_CON_DIV_PLL_SHARED2_DIV2, + DBG_NFO_PLL_SHARED2_DIV2, + CLK_CON_DIV_PLL_SHARED3_DIV2, + DBG_NFO_PLL_SHARED3_DIV2, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, + DBG_NFO_DIV_CLK_CPUCL0_CMUREF, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, + DBG_NFO_DIV_CLK_CLUSTER0_ACLK, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, + DBG_NFO_DIV_CLK_CLUSTER0_ATCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, + DBG_NFO_DIV_CLK_CLUSTER0_PCLKDBG, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, + DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG, + DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, + DBG_NFO_DIV_CLK_CPUCL0_PCLK, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC, + DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_ATCLK_LH, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_LH, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH, + DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_LH, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH, + DBG_NFO_DIV_CLK_CPUCL0_PCLK_LH, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, + DBG_NFO_DIV_CLK_CPUCL1_CMUREF, + CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF, + DBG_NFO_DIV_CLK_CPUCL2_CMUREF, + CLK_CON_DIV_DIV_CLK_CSIS_NOCP, + DBG_NFO_DIV_CLK_CSIS_NOCP, + CLK_CON_DIV_DIV_CLK_DISP_NOCP, + DBG_NFO_DIV_CLK_DISP_NOCP, + CLK_CON_DIV_DIV_CLK_DNS_NOCP, + DBG_NFO_DIV_CLK_DNS_NOCP, + CLK_CON_DIV_DIV_CLK_DPU_NOCP, + DBG_NFO_DIV_CLK_DPU_NOCP, + CLK_CON_DIV_DIV_CLK_EH_NOCP, + DBG_NFO_DIV_CLK_EH_NOCP, + CLK_CON_DIV_DIV_CLK_EH_NOCP_LH, + DBG_NFO_DIV_CLK_EH_NOCP_LH, + CLK_CON_DIV_DIV_CLK_G2D_NOCP, + DBG_NFO_DIV_CLK_G2D_NOCP, + CLK_CON_DIV_DIV_CLK_G3AA_NOCP, + DBG_NFO_DIV_CLK_G3AA_NOCP, + CLK_CON_DIV_DIV_CLK_G3D_NOCP, + DBG_NFO_DIV_CLK_G3D_NOCP, + CLK_CON_DIV_CLK_G3D_ADD_CH_CLK, + DBG_NFO_CLK_G3D_ADD_CH_CLK, + CLK_CON_DIV_DIV_CLK_G3D_TOP, + DBG_NFO_DIV_CLK_G3D_TOP, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH, + DBG_NFO_DIV_CLK_G3D_NOCP_LH, + CLK_CON_DIV_DIV_CLK_GDC_NOCP, + DBG_NFO_DIV_CLK_GDC_NOCP, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCP, + DBG_NFO_DIV_CLK_GSACORE_NOCP, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCD, + DBG_NFO_DIV_CLK_GSACORE_NOCD, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS, + DBG_NFO_DIV_CLK_GSACORE_SPI_FPS, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC, + DBG_NFO_DIV_CLK_GSACORE_SPI_GSC, + CLK_CON_DIV_DIV_CLK_GSACORE_UART, + DBG_NFO_DIV_CLK_GSACORE_UART, + CLK_CON_DIV_DIV_CLK_GSACORE_NOC, + DBG_NFO_DIV_CLK_GSACORE_NOC, + CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH, + DBG_NFO_DIV_CLK_GSACORE_CPU_LH, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP, + DBG_NFO_DIV_CLK_GSACTRL_NOCP, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD, + DBG_NFO_DIV_CLK_GSACTRL_NOCD, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH, + DBG_NFO_DIV_CLK_GSACTRL_NOCP_LH, + CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, + DBG_NFO_DIV_CLK_HSI0_USB31DRD, + CLK_CON_DIV_DIV_CLK_HSI0_USB, + DBG_NFO_DIV_CLK_HSI0_USB, + CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH, + DBG_NFO_DIV_CLK_HSI0_NOC_LH, + CLK_CON_DIV_DIV_CLK_HSI1_NOCP, + DBG_NFO_DIV_CLK_HSI1_NOCP, + CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH, + DBG_NFO_DIV_CLK_HSI1_NOC_LH, + CLK_CON_DIV_DIV_CLK_HSI2_NOCP, + DBG_NFO_DIV_CLK_HSI2_NOCP, + CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH, + DBG_NFO_DIV_CLK_HSI2_NOC_LH, + CLK_CON_DIV_DIV_CLK_IPP_NOCP, + DBG_NFO_DIV_CLK_IPP_NOCP, + CLK_CON_DIV_DIV_CLK_ITP_NOCP, + DBG_NFO_DIV_CLK_ITP_NOCP, + CLK_CON_DIV_DIV_CLK_MCSC_NOCP, + DBG_NFO_DIV_CLK_MCSC_NOCP, + CLK_CON_DIV_DIV_CLK_MFC_NOCP, + DBG_NFO_DIV_CLK_MFC_NOCP, + CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH, + DBG_NFO_DIV_CLK_MIF_NOCP_LH, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH, + DBG_NFO_DIV_CLK_MIF_NOCD_DBG_LH, + CLK_CON_DIV_DIV_CLK_MISC_NOCP, + DBG_NFO_DIV_CLK_MISC_NOCP, + CLK_CON_DIV_DIV_CLK_MISC_GIC, + DBG_NFO_DIV_CLK_MISC_GIC, + CLK_CON_DIV_DIV_CLK_MISC_GIC_LH, + DBG_NFO_DIV_CLK_MISC_GIC_LH, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH, + DBG_NFO_DIV_CLK_MISC_NOCP_LH, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP, + DBG_NFO_DIV_CLK_NOCL0_NOCP, + CLK_CON_DIV_DIV_CLK_SLC_DCLK, + DBG_NFO_DIV_CLK_SLC_DCLK, + CLK_CON_DIV_DIV_CLK_SLC1_DCLK, + DBG_NFO_DIV_CLK_SLC1_DCLK, + CLK_CON_DIV_DIV_CLK_SLC2_DCLK, + DBG_NFO_DIV_CLK_SLC2_DCLK, + CLK_CON_DIV_DIV_CLK_SLC3_DCLK, + DBG_NFO_DIV_CLK_SLC3_DCLK, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH, + DBG_NFO_DIV_CLK_NOCL0_NOCD_LH, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH, + DBG_NFO_DIV_CLK_NOCL0_NOCP_LH, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP, + DBG_NFO_DIV_CLK_NOCL1A_NOCP, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH, + DBG_NFO_DIV_CLK_NOCL1A_NOCD_LH, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH, + DBG_NFO_DIV_CLK_NOCL1A_NOCP_LH, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP, + DBG_NFO_DIV_CLK_NOCL1B_NOCP, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH, + DBG_NFO_DIV_CLK_NOCL1B_NOCD_LH, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH, + DBG_NFO_DIV_CLK_NOCL1B_NOCP_LH, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP, + DBG_NFO_DIV_CLK_NOCL2A_NOCP, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH, + DBG_NFO_DIV_CLK_NOCL2A_NOCD_LH, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH, + DBG_NFO_DIV_CLK_NOCL2A_NOCP_LH, + CLK_CON_DIV_DIV_CLK_PDP_NOCP, + DBG_NFO_DIV_CLK_PDP_NOCP, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, + DBG_NFO_DIV_CLK_PERIC0_USI6_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, + DBG_NFO_DIV_CLK_PERIC0_USI3_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, + DBG_NFO_DIV_CLK_PERIC0_USI4_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, + DBG_NFO_DIV_CLK_PERIC0_USI5_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, + DBG_NFO_DIV_CLK_PERIC0_USI14_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, + DBG_NFO_DIV_CLK_PERIC0_I3C, + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, + DBG_NFO_DIV_CLK_PERIC0_USI7_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, + DBG_NFO_DIV_CLK_PERIC0_USI8_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, + DBG_NFO_DIV_CLK_PERIC0_USI1_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, + DBG_NFO_DIV_CLK_PERIC0_USI0_UART, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, + DBG_NFO_DIV_CLK_PERIC0_USI2_USI, + CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH, + DBG_NFO_DIV_CLK_PERIC0_NOCP_LH, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, + DBG_NFO_DIV_CLK_PERIC1_USI11_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, + DBG_NFO_DIV_CLK_PERIC1_I3C, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, + DBG_NFO_DIV_CLK_PERIC1_USI12_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, + DBG_NFO_DIV_CLK_PERIC1_USI0_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, + DBG_NFO_DIV_CLK_PERIC1_USI9_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, + DBG_NFO_DIV_CLK_PERIC1_USI10_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, + DBG_NFO_DIV_CLK_PERIC1_USI13_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH, + DBG_NFO_DIV_CLK_PERIC1_NOCP_LH, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI, + DBG_NFO_DIV_CLK_PERIC1_USI15_USI, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI, + DBG_NFO_DIV_CLK_PERIC1_USI16_USI, + CLK_CON_DIV_DIV_CLK_S2D_CORE_LH, + DBG_NFO_DIV_CLK_S2D_CORE_LH, + CLK_CON_DIV_DIV_CLK_TNR_NOCP, + DBG_NFO_DIV_CLK_TNR_NOCP, + CLK_CON_DIV_DIV_CLK_TPU_NOCP, + DBG_NFO_DIV_CLK_TPU_NOCP, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG, + DBG_NFO_DIV_CLK_TPU_TPUCTL_DBG, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH, + DBG_NFO_DIV_CLK_TPU_NOCP_LH, + CLK_CON_DIV_DIV_CLK_AUR_AUR, + DBG_NFO_DIV_CLK_AUR_AUR, + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, + DBG_NFO_DIV_CLK_CPUCL0_CPU, + CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, + DBG_NFO_DIV_CLK_CPUCL1_CPU, + CLK_CON_DIV_DIV_CLK_CPUCL2_CPU, + DBG_NFO_DIV_CLK_CPUCL2_CPU, + CLK_CON_DIV_DIV_CLK_G3D_STACKS, + DBG_NFO_DIV_CLK_G3D_STACKS, + CLK_CON_DIV_DIV_CLK_G3D_L2_GLB, + DBG_NFO_DIV_CLK_G3D_L2_GLB, + CLK_CON_DIV_DIV_CLK_TPU_TPU, + DBG_NFO_DIV_CLK_TPU_TPU, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL, + DBG_NFO_DIV_CLK_TPU_TPUCTL, + CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1, + CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1, + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC, + CLK_CON_GAT_CLKCMU_MIF_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD, + CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC, + CLK_CON_GAT_GATE_CLKCMU_DPU_NOC, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_MISC_NOC, + CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC, + CLK_CON_GAT_GATE_CLKCMU_ITP_NOC, + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA, + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, + CLK_CON_GAT_GATE_CLKCMU_HPM, + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, + CLK_CON_GAT_GATE_CLKCMU_BO_NOC, + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC, + CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, + CLK_CON_GAT_GATE_CLKCMU_TPU_NOC, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG, + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, + CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC, + CLK_CON_GAT_GATE_CLKCMU_IPP_NOC, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, + CLK_CON_GAT_GATE_CLKCMU_TNR_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST, + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST, + CLK_CON_GAT_CLKCMU_NOCL1B_BOOST, + CLK_CON_GAT_CLKCMU_NOCL2A_BOOST, + CLK_CON_GAT_CLKCMU_NOCL1A_BOOST, + CLK_CON_GAT_CLKCMU_NOCL0_BOOST, + CLK_CON_GAT_CLKCMU_MIF_BOOST, + CLK_CON_GAT_GATE_CLKCMU_DNS_NOC, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD, + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH, + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST, + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, + CLK_CON_GAT_GATE_CLKCMU_DISP_NOC, + CLK_CON_GAT_GATE_CLKCMU_EH_NOC, + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF, + CLK_CON_GAT_GATE_CLKCMU_PDP_NOC, + CLK_CON_GAT_GATE_CLKCMU_TPU_UART, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL, + CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD, + CLK_CON_GAT_GATE_CLKCMU_AUR_AUR, + CLK_CON_GAT_GATE_CLKCMU_AUR_NOC, + CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON, + CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, + CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, + CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH, + CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM, + CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_GSACORE, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GATE_CLK_GSA_FUNC, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GATE_CLK_GSACTRL2CORE, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, + CLK_CON_GAT_CLK_HSI0_ALT, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, + CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM, + CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2, + CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM, + CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C, + CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG, + CLK_CON_DIV_DIV_CLK_MIF_NOCD, + CLK_CON_DIV_CLK_MIF_NOCD_S2D, + QCH_CON_AOC_CMU_AOC_QCH, + QCH_CON_AOC_SYSCTRL_APB_QCH, + QCH_CON_BAAW_AOC_QCH, + QCH_CON_D_TZPC_AOC_QCH, + QCH_CON_GPC_AOC_QCH, + QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH, + QCH_CON_LH_ATB_SI_LT_AOC_QCH, + QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH, + QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH, + QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH, + QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH, + QCH_CON_LH_AXI_MI_P_AOC_CU_QCH, + QCH_CON_LH_AXI_SI_D_AOC_QCH, + QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH, + QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH, + QCH_CON_LH_AXI_SI_P_AOC_CU_QCH, + QCH_CON_PPMU_AOC_QCH, + QCH_CON_PPMU_USB_QCH, + QCH_CON_SLH_AXI_MI_LG_AOC_QCH, + QCH_CON_SLH_AXI_MI_P_AOC_QCH, + QCH_CON_SLH_AXI_SI_LP0_AOC_QCH, + QCH_CON_SLH_AXI_SI_LP1_AOC_QCH, + QCH_CON_SSMT_AOC_QCH, + QCH_CON_SYSMMU_AOC_QCH_S1, + QCH_CON_SYSMMU_AOC_QCH_S2, + QCH_CON_SYSREG_AOC_QCH, + QCH_CON_UASC_AOC_QCH, + QCH_CON_APBIF_GPIO_ALIVE_QCH, + QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH, + QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH, + QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH, + QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH, + QCH_CON_APBIF_PMU_ALIVE_QCH, + QCH_CON_APBIF_RTC_QCH, + QCH_CON_APBIF_TRTC_QCH, + QCH_CON_APM_CMU_APM_QCH, + QCH_CON_APM_I3C_PMIC_QCH_P, + DMYQCH_CON_APM_I3C_PMIC_QCH_S, + QCH_CON_APM_USI0_UART_QCH, + QCH_CON_APM_USI0_USI_QCH, + QCH_CON_APM_USI1_UART_QCH, + QCH_CON_D_TZPC_APM_QCH, + QCH_CON_GPC_APM_QCH, + QCH_CON_GREBEINTEGRATION_QCH_GREBE, + QCH_CON_GREBEINTEGRATION_QCH_DBG, + QCH_CON_INTMEM_QCH, + QCH_CON_LH_AXI_MI_IG_SWD_QCH, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH, + QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH, + QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH, + QCH_CON_LH_AXI_SI_D_APM_QCH, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH, + QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH, + QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH, + QCH_CON_MAILBOX_APM_AOC_QCH, + QCH_CON_MAILBOX_APM_AP_QCH, + QCH_CON_MAILBOX_APM_AUR_QCH, + QCH_CON_MAILBOX_APM_GSA_QCH, + QCH_CON_MAILBOX_APM_SWD_QCH, + QCH_CON_MAILBOX_APM_TPU_QCH, + QCH_CON_MAILBOX_AP_AOCA32_QCH, + QCH_CON_MAILBOX_AP_AOCF1_QCH, + QCH_CON_MAILBOX_AP_AOCP6_QCH, + QCH_CON_MAILBOX_AP_AUR0_QCH, + QCH_CON_MAILBOX_AP_AUR1_QCH, + QCH_CON_MAILBOX_AP_AUR2_QCH, + QCH_CON_MAILBOX_AP_AUR3_QCH, + QCH_CON_MAILBOX_AP_DBGCORE_QCH, + QCH_CON_PMU_INTR_GEN_QCH, + QCH_CON_ROM_CRC32_HOST_QCH, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH, + QCH_CON_SLH_AXI_MI_LP0_AOC_QCH, + QCH_CON_SLH_AXI_MI_P_ALIVE_QCH, + QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH, + QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH, + QCH_CON_SSMT_D_APM_QCH, + QCH_CON_SSMT_LG_DBGCORE_QCH, + QCH_CON_SS_DBGCORE_QCH_GREBE, + QCH_CON_SS_DBGCORE_QCH_DBG, + QCH_CON_SYSMMU_D_APM_QCH, + QCH_CON_SYSREG_APM_QCH, + QCH_CON_UASC_APM_QCH, + QCH_CON_UASC_DBGCORE_QCH, + QCH_CON_UASC_IG_SWD_QCH, + QCH_CON_UASC_LP0_AOC_QCH, + QCH_CON_UASC_P_ALIVE_QCH, + QCH_CON_WDT_APM_QCH, + QCH_CON_ADD_APBIF_AUR_QCH, + DMYQCH_CON_ADD_AUR_QCH, + DMYQCH_CON_AUR_QCH, + QCH_CON_AUR_CMU_AUR_QCH, + QCH_CON_BAAW_AUR_QCH, + QCH_CON_D_TZPC_AUR_QCH, + QCH_CON_GPC_AUR_QCH, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH, + QCH_CON_LH_AXI_MI_P_AUR_CU_QCH, + QCH_CON_LH_AXI_SI_D0_AUR_QCH, + QCH_CON_LH_AXI_SI_D1_AUR_QCH, + QCH_CON_LH_AXI_SI_P_AUR_CU_QCH, + QCH_CON_PPMU_D0_AUR_QCH, + QCH_CON_PPMU_D1_AUR_QCH, + QCH_CON_SLH_AXI_MI_P_AUR_QCH, + QCH_CON_SSMT_D0_AUR_QCH, + QCH_CON_SSMT_D1_AUR_QCH, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2, + QCH_CON_SYSREG_AUR_QCH, + QCH_CON_UASC_AUR_QCH, + DMYQCH_CON_BO_QCH, + QCH_CON_BO_CMU_BO_QCH, + QCH_CON_D_TZPC_BO_QCH, + QCH_CON_GPC_BO_QCH, + QCH_CON_LH_AXI_MI_IP_BO_QCH, + QCH_CON_LH_AXI_SI_D_BO_QCH, + QCH_CON_LH_AXI_SI_IP_BO_QCH, + QCH_CON_PPMU_BO_QCH, + QCH_CON_SLH_AXI_MI_P_BO_QCH, + QCH_CON_SSMT_BO_QCH, + QCH_CON_SYSMMU_BO_QCH_S1, + QCH_CON_SYSMMU_BO_QCH_S2, + QCH_CON_SYSREG_BO_QCH, + QCH_CON_UASC_BO_QCH, + DMYQCH_CON_CMU_TOP_CMUREF_QCH, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7, + DMYQCH_CON_OTP_QCH, + DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH, + QCH_CON_BPS_CPUCL0_QCH, + QCH_CON_CLUSTER0_QCH_SCLK, + QCH_CON_CLUSTER0_QCH_ATCLK, + QCH_CON_CLUSTER0_QCH_GIC, + QCH_CON_CLUSTER0_QCH_PCLK, + DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK, + QCH_CON_CLUSTER0_QCH_DBG_PD, + QCH_CON_CLUSTER0_QCH_PDBGCLK, + DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH, + QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, + QCH_CON_CPUCL0_CMU_CPUCL0_QCH, + QCH_CON_CSSYS_QCH, + QCH_CON_D_TZPC_CPUCL0_QCH, + QCH_CON_GPC_CPUCL0_QCH, + QCH_CON_HPM_APBIF_CPUCL0_QCH, + QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH, + QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH, + QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_MI_LT_AOC_QCH, + QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_MI_T_BDU_QCH, + QCH_CON_LH_ATB_MI_T_BDU_CU_QCH, + QCH_CON_LH_ATB_MI_T_SLC_QCH, + QCH_CON_LH_ATB_MI_T_SLC_CU_QCH, + QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH, + QCH_CON_LH_ATB_SI_T_BDU_CU_QCH, + QCH_CON_LH_ATB_SI_T_SLC_CU_QCH, + QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH, + QCH_CON_LH_AXI_MI_IG_CSSYS_QCH, + QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH, + QCH_CON_LH_AXI_MI_IG_HSI0_QCH, + QCH_CON_LH_AXI_MI_IG_STM_QCH, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH, + QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH, + QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH, + QCH_CON_LH_AXI_SI_IG_CSSYS_QCH, + QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH, + QCH_CON_LH_AXI_SI_IG_HSI0_QCH, + QCH_CON_LH_AXI_SI_IG_STM_QCH, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH, + QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH, + QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH, + QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH, + QCH_CON_SLH_AXI_SI_G_CSSYS_QCH, + QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH, + QCH_CON_SSMT_CPUCL0_QCH, + QCH_CON_SYSMMU_S2_CPUCL0_QCH, + QCH_CON_SYSREG_CPUCL0_QCH, + DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH, + QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, + DMYQCH_CON_CPUCL1_QCH_MID, + QCH_CON_CPUCL1_CMU_CPUCL1_QCH, + DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH, + QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH, + DMYQCH_CON_CPUCL2_QCH_BIG, + QCH_CON_CPUCL2_CMU_CPUCL2_QCH, + QCH_CON_CSISX8_QCH_C2_CSIS, + QCH_CON_CSISX8_QCH_CSIS_DMA, + QCH_CON_CSISX8_QCH_EBUF, + QCH_CON_CSIS_CMU_CSIS_QCH, + QCH_CON_D_TZPC_CSIS_QCH, + QCH_CON_GPC_CSIS_QCH, + QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH, + QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH, + QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH, + QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH, + QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH, + QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH, + QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH, + QCH_CON_LH_AXI_SI_D0_CSIS_QCH, + QCH_CON_LH_AXI_SI_D1_CSIS_QCH, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7, + QCH_CON_PPMU_D0_QCH, + QCH_CON_PPMU_D1_QCH, + QCH_CON_QE_CSIS_DMA0_QCH, + QCH_CON_QE_CSIS_DMA1_QCH, + QCH_CON_QE_CSIS_DMA2_QCH, + QCH_CON_QE_CSIS_DMA3_QCH, + QCH_CON_QE_STRP0_QCH, + QCH_CON_QE_STRP1_QCH, + QCH_CON_QE_STRP2_QCH, + QCH_CON_QE_ZSL0_QCH, + QCH_CON_QE_ZSL1_QCH, + QCH_CON_QE_ZSL2_QCH, + QCH_CON_SLH_AXI_MI_P_CSIS_QCH, + QCH_CON_SSMT_D0_QCH, + QCH_CON_SSMT_D1_QCH, + QCH_CON_SYSMMU_D0_CSIS_QCH_S1, + QCH_CON_SYSMMU_D0_CSIS_QCH_S2, + QCH_CON_SYSMMU_D1_CSIS_QCH_S1, + QCH_CON_SYSMMU_D1_CSIS_QCH_S2, + QCH_CON_SYSREG_CSIS_QCH, + QCH_CON_DISP_CMU_DISP_QCH, + QCH_CON_DPUB_QCH, + QCH_CON_D_TZPC_DISP_QCH, + QCH_CON_GPC_DISP_QCH, + QCH_CON_SLH_AXI_MI_P_DISP_QCH, + QCH_CON_SYSREG_DISP_QCH, + QCH_CON_DNS_QCH_00, + QCH_CON_DNS_QCH_01, + QCH_CON_DNS_CMU_DNS_QCH, + QCH_CON_D_TZPC_DNS_QCH, + QCH_CON_GPC_DNS_QCH, + QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH, + QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH, + QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH, + QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH, + QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH, + QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH, + QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH, + QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH, + QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH, + QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH, + QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH, + QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH, + QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH, + QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH, + QCH_CON_LH_AXI_SI_D_DNS_QCH, + QCH_CON_PPMU_D0_DNS_QCH, + QCH_CON_PPMU_D1_DNS_QCH, + QCH_CON_QE_D0_DNS_QCH, + QCH_CON_QE_D1_DNS_QCH, + QCH_CON_SLH_AXI_MI_P_DNS_QCH, + QCH_CON_SSMT_D0_DNS_QCH, + QCH_CON_SSMT_D1_DNS_QCH, + QCH_CON_SYSMMU_DNS_QCH_S1, + QCH_CON_SYSMMU_DNS_QCH_S2, + QCH_CON_SYSREG_DNS_QCH, + QCH_CON_DPUF_QCH_DPU_DMA, + QCH_CON_DPUF_QCH_DPU_DPP, + QCH_CON_DPU_CMU_DPU_QCH, + QCH_CON_D_TZPC_DPU_QCH, + QCH_CON_GPC_DPU_QCH, + QCH_CON_LH_AXI_SI_D0_DPU_QCH, + QCH_CON_LH_AXI_SI_D1_DPU_QCH, + QCH_CON_LH_AXI_SI_D2_DPU_QCH, + QCH_CON_PPMU_DPUD0_QCH, + QCH_CON_PPMU_DPUD1_QCH, + QCH_CON_PPMU_DPUD2_QCH, + QCH_CON_SLH_AXI_MI_P_DPU_QCH, + QCH_CON_SSMT_DPU0_QCH, + QCH_CON_SSMT_DPU1_QCH, + QCH_CON_SSMT_DPU2_QCH, + QCH_CON_SYSMMU_DPUD0_QCH_S1, + QCH_CON_SYSMMU_DPUD0_QCH_S2, + QCH_CON_SYSMMU_DPUD1_QCH_S1, + QCH_CON_SYSMMU_DPUD1_QCH_S2, + QCH_CON_SYSMMU_DPUD2_QCH_S1, + QCH_CON_SYSMMU_DPUD2_QCH_S2, + QCH_CON_SYSREG_DPU_QCH, + QCH_CON_D_TZPC_EH_QCH, + QCH_CON_EH_QCH, + QCH_CON_EH_CMU_EH_QCH, + QCH_CON_GPC_EH_QCH, + QCH_CON_LH_ACEL_SI_D_EH_QCH, + QCH_CON_LH_AXI_MI_IP_EH_QCH, + QCH_CON_LH_AXI_MI_P_EH_CU_QCH, + QCH_CON_LH_AXI_SI_IP_EH_QCH, + QCH_CON_LH_AXI_SI_P_EH_CU_QCH, + QCH_CON_PPMU_EH_QCH, + QCH_CON_QE_EH_QCH, + QCH_CON_SLH_AXI_MI_P_EH_QCH, + QCH_CON_SSMT_EH_QCH, + QCH_CON_SYSMMU_EH_QCH, + QCH_CON_SYSREG_EH_QCH, + QCH_CON_UASC_EH_QCH, + QCH_CON_D_TZPC_G2D_QCH, + QCH_CON_G2D_QCH, + QCH_CON_G2D_CMU_G2D_QCH, + QCH_CON_GPC_G2D_QCH, + QCH_CON_JPEG_QCH, + QCH_CON_LH_ACEL_SI_D2_G2D_QCH, + QCH_CON_LH_AXI_SI_D0_G2D_QCH, + QCH_CON_LH_AXI_SI_D1_G2D_QCH, + QCH_CON_PPMU_D0_G2D_QCH, + QCH_CON_PPMU_D1_G2D_QCH, + QCH_CON_PPMU_D2_G2D_QCH, + QCH_CON_SLH_AXI_MI_P_G2D_QCH, + QCH_CON_SSMT_D0_G2D_QCH, + QCH_CON_SSMT_D1_G2D_QCH, + QCH_CON_SSMT_D2_G2D_QCH, + QCH_CON_SYSMMU_D0_G2D_QCH_0, + QCH_CON_SYSMMU_D0_G2D_QCH_1, + QCH_CON_SYSMMU_D1_G2D_QCH_0, + QCH_CON_SYSMMU_D1_G2D_QCH_1, + QCH_CON_SYSMMU_D2_G2D_QCH_0, + QCH_CON_SYSMMU_D2_G2D_QCH_1, + QCH_CON_SYSREG_G2D_QCH, + QCH_CON_D_TZPC_G3AA_QCH, + DMYQCH_CON_G3AA_QCH, + QCH_CON_G3AA_CMU_G3AA_QCH, + QCH_CON_GPC_G3AA_QCH, + QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH, + QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH, + QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH, + QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH, + QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH, + QCH_CON_LH_AXI_SI_D_G3AA_QCH, + QCH_CON_PPMU_G3AA_QCH, + QCH_CON_SLH_AXI_MI_P_G3AA_QCH, + QCH_CON_SSMT_G3AA_QCH, + QCH_CON_SYSMMU_G3AA_QCH_S1, + QCH_CON_SYSMMU_G3AA_QCH_S2, + QCH_CON_SYSREG_G3AA_QCH, + QCH_CON_ADD_APBIF_G3D_QCH, + DMYQCH_CON_ADD_G3D_QCH, + QCH_CON_ADM_AHB_G_GPU_QCH, + QCH_CON_ASB_G3D_QCH_LH_D0_G3D, + QCH_CON_ASB_G3D_QCH_LH_D1_G3D, + QCH_CON_ASB_G3D_QCH_LH_D2_G3D, + QCH_CON_ASB_G3D_QCH_LH_D3_G3D, + QCH_CON_BUSIF_HPMG3D_QCH, + QCH_CON_D_TZPC_G3D_QCH, + QCH_CON_G3D_CMU_G3D_QCH, + QCH_CON_GPC_G3D_QCH, + QCH_CON_GPU_QCH, + QCH_CON_LH_AXI_MI_IP_G3D_QCH, + QCH_CON_LH_AXI_MI_P_G3D_CU_QCH, + QCH_CON_LH_AXI_SI_IP_G3D_QCH, + QCH_CON_LH_AXI_SI_P_G3D_CU_QCH, + QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH, + QCH_CON_SLH_AXI_MI_P_G3D_QCH, + QCH_CON_SYSREG_G3D_QCH, + QCH_CON_UASC_G3D_QCH, + QCH_CON_D_TZPC_GDC_QCH, + QCH_CON_GDC0_QCH_CLK, + QCH_CON_GDC0_QCH_C2CLK, + QCH_CON_GDC1_QCH_CLK, + QCH_CON_GDC1_QCH_C2CLK, + QCH_CON_GDC_CMU_GDC_QCH, + QCH_CON_GPC_GDC_QCH, + QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH, + QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH, + QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH, + QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH, + QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH, + QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH, + QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH, + QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH, + QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH, + QCH_CON_LH_AXI_SI_D0_GDC_QCH, + QCH_CON_LH_AXI_SI_D1_GDC_QCH, + QCH_CON_LH_AXI_SI_D2_GDC_QCH, + QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH, + QCH_CON_PPMU_D0_GDC_QCH, + QCH_CON_PPMU_D0_SCSC_QCH, + QCH_CON_PPMU_D1_GDC_QCH, + QCH_CON_PPMU_D1_SCSC_QCH, + QCH_CON_PPMU_D2_GDC_QCH, + QCH_CON_PPMU_D2_SCSC_QCH, + QCH_CON_PPMU_D3_GDC_QCH, + QCH_CON_QE_D0_GDC_QCH, + QCH_CON_QE_D0_SCSC_QCH, + QCH_CON_QE_D1_GDC_QCH, + QCH_CON_QE_D1_SCSC_QCH, + QCH_CON_QE_D2_GDC_QCH, + QCH_CON_QE_D2_SCSC_QCH, + QCH_CON_QE_D3_GDC_QCH, + QCH_CON_SCSC_QCH_CLK, + QCH_CON_SCSC_QCH_C2CLK, + QCH_CON_SLH_AXI_MI_P_GDC_QCH, + QCH_CON_SSMT_D0_GDC_QCH, + QCH_CON_SSMT_D0_SCSC_QCH, + QCH_CON_SSMT_D1_GDC_QCH, + QCH_CON_SSMT_D1_SCSC_QCH, + QCH_CON_SSMT_D2_GDC_QCH, + QCH_CON_SSMT_D2_SCSC_QCH, + QCH_CON_SSMT_D3_GDC_QCH, + QCH_CON_SYSMMU_D0_GDC_QCH_S1, + QCH_CON_SYSMMU_D0_GDC_QCH_S2, + QCH_CON_SYSMMU_D1_GDC_QCH_S1, + QCH_CON_SYSMMU_D1_GDC_QCH_S2, + QCH_CON_SYSMMU_D2_GDC_QCH_S1, + QCH_CON_SYSMMU_D2_GDC_QCH_S2, + QCH_CON_SYSREG_GDC_QCH, + DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH, + QCH_CON_BAAW_GSACORE_QCH, + DMYQCH_CON_CA32_GSACORE_QCH, + QCH_CON_DMA_GSACORE_QCH, + QCH_CON_GIC_GSACORE_QCH, + QCH_CON_GPIO_GSACORE_QCH, + QCH_CON_GSACORE_CMU_GSACORE_QCH, + QCH_CON_INTMEM_GSACORE_QCH, + QCH_CON_KDN_GSACORE_QCH, + QCH_CON_LH_AST_MI_I_CA32_GIC_QCH, + QCH_CON_LH_AST_MI_I_GIC_CA32_QCH, + QCH_CON_LH_AST_SI_I_CA32_GIC_QCH, + QCH_CON_LH_AST_SI_I_GIC_CA32_QCH, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH, + QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH, + QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH, + QCH_CON_LH_AXI_MI_IP_GME_QCH, + QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH, + QCH_CON_LH_AXI_SI_D_GSA_QCH, + QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH, + QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH, + QCH_CON_LH_AXI_SI_IP_GME_QCH, + QCH_CON_LH_AXI_SI_IP_GSA_QCH, + QCH_CON_OTP_CON_GSACORE_QCH, + QCH_CON_PPMU_GSACORE_QCH, + DMYQCH_CON_PUF_GSACORE_QCH, + QCH_CON_QE_CA32_GSACORE_QCH, + QCH_CON_QE_DMA_GSACORE_QCH, + QCH_CON_QE_SSS_GSACORE_QCH, + QCH_CON_RESETMON_GSACORE_QCH, + QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH, + QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH, + QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH, + QCH_CON_SPI_FPS_GSACORE_QCH, + QCH_CON_SPI_GSC_GSACORE_QCH, + QCH_CON_SSMT_GSACORE_QCH, + QCH_CON_SSS_GSACORE_QCH, + QCH_CON_SYSMMU_GSACORE_QCH_S1, + QCH_CON_SYSMMU_GSACORE_QCH_S2, + QCH_CON_SYSREG_GSACORE_QCH, + QCH_CON_UART_GSACORE_QCH, + QCH_CON_WDT_GSACORE_QCH, + QCH_CON_UDAP_SSS_AHB_ASYNC_QCH, + QCH_CON_UGME_QCH, + QCH_CON_APBIF_GPIO_GSACTRL_QCH, + DMYQCH_CON_DAP_GSACTRL_QCH, + QCH_CON_GPC_GSACTRL_QCH, + QCH_CON_GSACTRL_CMU_GSACTRL_QCH, + QCH_CON_INTMEM_GSACTRL_QCH, + QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH, + QCH_CON_LH_AXI_MI_IP_GSA_QCH, + QCH_CON_LH_AXI_MI_P_GSA_CU_QCH, + QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH, + QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH, + QCH_CON_LH_AXI_SI_P_GSA_CU_QCH, + QCH_CON_MAILBOX_GSA2AOC_QCH, + QCH_CON_MAILBOX_GSA2AUR_QCH, + QCH_CON_MAILBOX_GSA2NONTZ_QCH, + QCH_CON_MAILBOX_GSA2TPU_QCH, + QCH_CON_MAILBOX_GSA2TZ_QCH, + QCH_CON_PMU_GSA_QCH, + QCH_CON_SECJTAG_GSACTRL_QCH, + QCH_CON_SLH_AXI_MI_P_GSA_QCH, + QCH_CON_SYSREG_GSACTRL_QCH, + QCH_CON_SYSREG_GSACTRLEXT_QCH, + QCH_CON_TIMER_GSACTRL_QCH, + QCH_CON_TZPC_GSACTRL_QCH, + QCH_CON_DP_LINK_QCH_PCLK, + QCH_CON_DP_LINK_QCH_GTC_CLK, + QCH_CON_D_TZPC_HSI0_QCH, + QCH_CON_ETR_MIU_QCH_ACLK, + QCH_CON_ETR_MIU_QCH_PCLK, + QCH_CON_GPC_HSI0_QCH, + QCH_CON_HSI0_CMU_HSI0_QCH, + QCH_CON_LH_ACEL_SI_D_HSI0_QCH, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH, + QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH, + QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH, + QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH, + QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH, + QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH, + QCH_CON_PPMU_HSI0_AOC_QCH, + QCH_CON_PPMU_HSI0_NOCL1B_QCH, + QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH, + QCH_CON_SLH_AXI_MI_LP1_AOC_QCH, + QCH_CON_SLH_AXI_MI_P_HSI0_QCH, + QCH_CON_SSMT_USB_QCH, + QCH_CON_SYSMMU_USB_QCH_S2, + QCH_CON_SYSMMU_USB_QCH_S1, + QCH_CON_SYSREG_HSI0_QCH, + QCH_CON_UASC_HSI0_CTRL_QCH, + QCH_CON_UASC_HSI0_LINK_QCH, + DMYQCH_CON_USB31DRD_QCH_REF, + QCH_CON_USB31DRD_QCH_SLV_CTRL, + QCH_CON_USB31DRD_QCH_SLV_LINK, + QCH_CON_USB31DRD_QCH_APB, + QCH_CON_USB31DRD_QCH_PCS, + QCH_CON_USB31DRD_QCH_DBG, + DMYQCH_CON_USB31DRD_QCH, + QCH_CON_D_TZPC_HSI1_QCH, + QCH_CON_GPC_HSI1_QCH, + QCH_CON_GPIO_HSI1_QCH, + QCH_CON_HSI1_CMU_HSI1_QCH, + QCH_CON_LH_ACEL_SI_D_HSI1_QCH, + QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH, + QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH, + QCH_CON_PCIE_GEN4_0_QCH_DBG_1, + QCH_CON_PCIE_GEN4_0_QCH_AXI_1, + QCH_CON_PCIE_GEN4_0_QCH_APB_1, + DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB, + QCH_CON_PCIE_GEN4_0_QCH_DBG_2, + QCH_CON_PCIE_GEN4_0_QCH_AXI_2, + QCH_CON_PCIE_GEN4_0_QCH_APB_2, + QCH_CON_PCIE_GEN4_0_QCH_UDBG, + DMYQCH_CON_PCIE_GEN4_0_QCH, + QCH_CON_PCIE_IA_GEN4A_0_QCH, + QCH_CON_PCIE_IA_GEN4B_0_QCH, + QCH_CON_PPMU_HSI1_QCH, + QCH_CON_QE_PCIE_GEN4A_HSI1_QCH, + QCH_CON_QE_PCIE_GEN4B_HSI1_QCH, + QCH_CON_SLH_AXI_MI_P_HSI1_QCH, + QCH_CON_SSMT_HSI1_QCH, + QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH, + QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH, + QCH_CON_SYSMMU_HSI1_QCH_S2, + QCH_CON_SYSMMU_HSI1_QCH_S1, + QCH_CON_SYSREG_HSI1_QCH, + QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH, + QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH, + QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH, + QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH, + QCH_CON_D_TZPC_HSI2_QCH, + QCH_CON_GPC_HSI2_QCH, + QCH_CON_GPIO_HSI2_QCH, + QCH_CON_GPIO_HSI2UFS_QCH, + QCH_CON_HSI2_CMU_HSI2_QCH, + QCH_CON_LH_ACEL_SI_D_HSI2_QCH, + QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH, + QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH, + QCH_CON_MMC_CARD_QCH, + QCH_CON_PCIE_GEN4_1_QCH_AXI_1, + QCH_CON_PCIE_GEN4_1_QCH_APB_1, + QCH_CON_PCIE_GEN4_1_QCH_DBG_1, + QCH_CON_PCIE_GEN4_1_QCH_PCS_APB, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF0, + QCH_CON_PCIE_GEN4_1_QCH_PMA_APB, + QCH_CON_PCIE_GEN4_1_QCH_AXI_2, + QCH_CON_PCIE_GEN4_1_QCH_DBG_2, + QCH_CON_PCIE_GEN4_1_QCH_APB_2, + QCH_CON_PCIE_GEN4_1_QCH_UDBG, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF1, + QCH_CON_PCIE_IA_GEN4A_1_QCH, + QCH_CON_PCIE_IA_GEN4B_1_QCH, + QCH_CON_PPMU_HSI2_QCH, + QCH_CON_QE_MMC_CARD_HSI2_QCH, + QCH_CON_QE_PCIE_GEN4A_HSI2_QCH, + QCH_CON_QE_PCIE_GEN4B_HSI2_QCH, + QCH_CON_QE_UFS_EMBD_HSI2_QCH, + QCH_CON_SLH_AXI_MI_P_HSI2_QCH, + QCH_CON_SSMT_HSI2_QCH, + QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH, + QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH, + QCH_CON_SYSMMU_HSI2_QCH_S2, + QCH_CON_SYSMMU_HSI2_QCH_S1, + QCH_CON_SYSREG_HSI2_QCH, + QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH, + QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH, + QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH, + QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH, + QCH_CON_UFS_EMBD_QCH, + QCH_CON_UFS_EMBD_QCH_FMP, + QCH_CON_D_TZPC_IPP_QCH, + QCH_CON_GPC_IPP_QCH, + QCH_CON_IPP_CMU_IPP_QCH, + QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH, + QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH, + QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH, + QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH, + QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH, + QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH, + QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH, + QCH_CON_LH_AXI_SI_D_IPP_QCH, + QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH, + QCH_CON_PPMU_IPP_QCH, + QCH_CON_PPMU_MSA_QCH, + QCH_CON_QE_ALIGN0_QCH, + QCH_CON_QE_ALIGN1_QCH, + QCH_CON_QE_ALIGN2_QCH, + QCH_CON_QE_ALIGN3_QCH, + QCH_CON_QE_ALN_STAT_QCH, + QCH_CON_QE_FDPIG_QCH, + QCH_CON_QE_RGBH0_QCH, + QCH_CON_QE_RGBH1_QCH, + QCH_CON_QE_RGBH2_QCH, + QCH_CON_QE_THSTAT_QCH, + QCH_CON_QE_TNR_MSA0_QCH, + QCH_CON_QE_TNR_MSA1_QCH, + QCH_CON_SIPU_IPP_QCH, + QCH_CON_SLH_AXI_MI_P_IPP_QCH, + QCH_CON_SSMT_ALIGN0_QCH, + QCH_CON_SSMT_ALIGN1_QCH, + QCH_CON_SSMT_ALIGN2_QCH, + QCH_CON_SSMT_ALIGN3_QCH, + QCH_CON_SSMT_ALN_STAT_QCH, + QCH_CON_SSMT_FDPIG_QCH, + QCH_CON_SSMT_RGBH0_QCH, + QCH_CON_SSMT_RGBH1_QCH, + QCH_CON_SSMT_RGBH2_QCH, + QCH_CON_SSMT_THSTAT_QCH, + QCH_CON_SSMT_TNR_MSA0_QCH, + QCH_CON_SSMT_TNR_MSA1_QCH, + QCH_CON_SYSMMU_IPP_QCH_S1, + QCH_CON_SYSMMU_IPP_QCH_S2, + QCH_CON_SYSREG_IPP_QCH, + QCH_CON_TNR_A_QCH, + QCH_CON_D_TZPC_ITP_QCH, + QCH_CON_GPC_ITP_QCH, + QCH_CON_ITP_QCH, + QCH_CON_ITP_CMU_ITP_QCH, + QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH, + QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH, + QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH, + QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH, + QCH_CON_PPMU_ITP_QCH, + QCH_CON_QE_ITP_QCH, + QCH_CON_SLH_AXI_MI_P_ITP_QCH, + QCH_CON_SSMT_ITP_QCH, + QCH_CON_SYSREG_ITP_QCH, + QCH_CON_C2R_MCSC_QCH, + QCH_CON_D_TZPC_MCSC_QCH, + QCH_CON_GPC_MCSC_QCH, + QCH_CON_ITSC_QCH_CLK, + QCH_CON_ITSC_QCH_C2, + QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH, + QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH, + QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH, + QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH, + QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH, + QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH, + QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH, + QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH, + QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH, + QCH_CON_LH_AXI_SI_D0_MCSC_QCH, + QCH_CON_LH_AXI_SI_D1_MCSC_QCH, + QCH_CON_LH_AXI_SI_D2_MCSC_QCH, + QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH, + QCH_CON_MCSC_QCH_CLK, + QCH_CON_MCSC_QCH_C2CLK, + QCH_CON_MCSC_CMU_MCSC_QCH, + QCH_CON_PPMU_D0_ITSC_QCH, + QCH_CON_PPMU_D0_MCSC_QCH, + QCH_CON_PPMU_D1_ITSC_QCH, + QCH_CON_PPMU_D1_MCSC_QCH, + QCH_CON_QE_D0_MCSC_QCH, + QCH_CON_QE_D1_ITSC_QCH, + QCH_CON_QE_D1_MCSC_QCH, + QCH_CON_QE_D2_ITSC_QCH, + QCH_CON_QE_D2_MCSC_QCH, + QCH_CON_QE_D3_ITSC_QCH, + QCH_CON_QE_D3_MCSC_QCH, + QCH_CON_QE_D4_MCSC_QCH, + QCH_CON_QE_D5_MCSC_QCH, + QCH_CON_SLH_AXI_MI_P_MCSC_QCH, + QCH_CON_SSMT_D0_ITSC_QCH, + QCH_CON_SSMT_D0_MCSC_QCH, + QCH_CON_SSMT_D1_ITSC_QCH, + QCH_CON_SSMT_D1_MCSC_QCH, + QCH_CON_SYSMMU_D0_MCSC_QCH_S1, + QCH_CON_SYSMMU_D0_MCSC_QCH_S2, + QCH_CON_SYSMMU_D1_MCSC_QCH_S1, + QCH_CON_SYSMMU_D1_MCSC_QCH_S2, + QCH_CON_SYSMMU_D2_MCSC_QCH_S1, + QCH_CON_SYSMMU_D2_MCSC_QCH_S2, + QCH_CON_SYSREG_MCSC_QCH, + QCH_CON_D_TZPC_MFC_QCH, + QCH_CON_GPC_MFC_QCH, + QCH_CON_LH_AXI_SI_D0_MFC_QCH, + QCH_CON_LH_AXI_SI_D1_MFC_QCH, + QCH_CON_MFC_QCH, + QCH_CON_MFC_CMU_MFC_QCH, + QCH_CON_PPMU_D0_MFC_QCH, + QCH_CON_PPMU_D1_MFC_QCH, + QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH, + QCH_CON_SLH_AXI_MI_P_MFC_QCH, + QCH_CON_SSMT_D0_MFC_QCH, + QCH_CON_SSMT_D1_MFC_QCH, + QCH_CON_SYSMMU_D0_MFC_QCH_0, + QCH_CON_SYSMMU_D0_MFC_QCH_1, + QCH_CON_SYSMMU_D1_MFC_QCH_0, + QCH_CON_SYSMMU_D1_MFC_QCH_1, + QCH_CON_SYSREG_MFC_QCH, + QCH_CON_APBBR_DDRPHY_QCH, + QCH_CON_APBBR_DMC_QCH, + DMYQCH_CON_CMU_MIF_CMUREF_QCH, + QCH_CON_DMC_QCH, + QCH_CON_D_TZPC_MIF_QCH, + QCH_CON_GEN_WREN_SECURE_QCH, + QCH_CON_GPC_MIF_QCH, + QCH_CON_LH_AST_MI_G_DMC_CD_QCH, + QCH_CON_LH_AST_SI_G_DMC_QCH, + QCH_CON_LH_AST_SI_G_DMC_CD_QCH, + QCH_CON_LH_AXI_MI_P_MIF_CU_QCH, + QCH_CON_LH_AXI_SI_P_MIF_CU_QCH, + QCH_CON_MIF_CMU_MIF_QCH, + QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH, + QCH_CON_SLH_AXI_MI_P_MIF_QCH, + QCH_CON_SYSREG_MIF_QCH, + QCH_CON_ADM_AHB_G_SSS_QCH, + QCH_CON_DIT_QCH, + QCH_CON_D_TZPC_MISC_QCH, + QCH_CON_GIC_QCH, + QCH_CON_GPC_MISC_QCH, + QCH_CON_LH_ACEL_SI_D_MISC_QCH, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH, + QCH_CON_LH_AXI_MI_ID_SSS_QCH, + QCH_CON_LH_AXI_MI_P_GIC_CU_QCH, + QCH_CON_LH_AXI_MI_P_MISC_CU_QCH, + QCH_CON_LH_AXI_SI_ID_SSS_QCH, + QCH_CON_LH_AXI_SI_P_GIC_CU_QCH, + QCH_CON_LH_AXI_SI_P_MISC_CU_QCH, + QCH_CON_MCT_QCH, + QCH_CON_MISC_CMU_MISC_QCH, + QCH_CON_OTP_CON_BIRA_QCH, + QCH_CON_OTP_CON_BISR_QCH, + QCH_CON_OTP_CON_TOP_QCH, + QCH_CON_PDMA0_QCH, + QCH_CON_PDMA1_QCH, + QCH_CON_PPMU_MISC_QCH, + DMYQCH_CON_PUF_QCH, + QCH_CON_QE_DIT_QCH, + QCH_CON_QE_PDMA0_QCH, + QCH_CON_QE_PDMA1_QCH, + QCH_CON_QE_RTIC_QCH, + QCH_CON_QE_SPDMA0_QCH, + QCH_CON_QE_SPDMA1_QCH, + QCH_CON_QE_SSS_QCH, + QCH_CON_RTIC_QCH, + QCH_CON_SLH_AXI_MI_P_GIC_QCH, + QCH_CON_SLH_AXI_MI_P_MISC_QCH, + QCH_CON_SPDMA0_QCH, + QCH_CON_SPDMA1_QCH, + QCH_CON_SSMT_DIT_QCH, + QCH_CON_SSMT_PDMA0_QCH, + QCH_CON_SSMT_PDMA1_QCH, + QCH_CON_SSMT_RTIC_QCH, + QCH_CON_SSMT_SPDMA0_QCH, + QCH_CON_SSMT_SPDMA1_QCH, + QCH_CON_SSMT_SSS_QCH, + QCH_CON_SSS_QCH, + QCH_CON_SYSMMU_MISC_QCH, + QCH_CON_SYSMMU_SSS_QCH, + QCH_CON_SYSREG_MISC_QCH, + QCH_CON_TMU_SUB_QCH, + QCH_CON_TMU_TOP_QCH, + QCH_CON_WDT_CLUSTER0_QCH, + QCH_CON_WDT_CLUSTER1_QCH, + QCH_CON_ASYNCSFR_WR_SMC_QCH, + QCH_CON_BDU_QCH, + QCH_CON_CCI_QCH, + DMYQCH_CON_CMU_NOCL0_CMUREF_QCH, + QCH_CON_CPE425_QCH, + QCH_CON_D_TZPC_NOCL0_QCH, + QCH_CON_GPC_NOCL0_QCH, + QCH_CON_LH_ACEL_MI_D_EH_QCH, + QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH, + QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH, + QCH_CON_LH_AST_MI_G_DMC0_QCH, + QCH_CON_LH_AST_MI_G_DMC0_CU_QCH, + QCH_CON_LH_AST_MI_G_DMC1_QCH, + QCH_CON_LH_AST_MI_G_DMC1_CU_QCH, + QCH_CON_LH_AST_MI_G_DMC2_QCH, + QCH_CON_LH_AST_MI_G_DMC2_CU_QCH, + QCH_CON_LH_AST_MI_G_DMC3_QCH, + QCH_CON_LH_AST_MI_G_DMC3_CU_QCH, + QCH_CON_LH_AST_MI_G_NOCL1A_QCH, + QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH, + QCH_CON_LH_AST_MI_G_NOCL1B_QCH, + QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH, + QCH_CON_LH_AST_MI_G_NOCL2A_QCH, + QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH, + QCH_CON_LH_AST_SI_G_DMC0_CU_QCH, + QCH_CON_LH_AST_SI_G_DMC1_CU_QCH, + QCH_CON_LH_AST_SI_G_DMC2_CU_QCH, + QCH_CON_LH_AST_SI_G_DMC3_CU_QCH, + QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH, + QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH, + QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH, + QCH_CON_LH_ATB_MI_T_BDU_CD_QCH, + QCH_CON_LH_ATB_MI_T_SLC_CD_QCH, + QCH_CON_LH_ATB_SI_T_BDU_QCH, + QCH_CON_LH_ATB_SI_T_BDU_CD_QCH, + QCH_CON_LH_ATB_SI_T_SLC_QCH, + QCH_CON_LH_ATB_SI_T_SLC_CD_QCH, + QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH, + QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH, + QCH_CON_LH_AXI_MI_P_EH_CD_QCH, + QCH_CON_LH_AXI_MI_P_GIC_CD_QCH, + QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH, + QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH, + QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH, + QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH, + QCH_CON_LH_AXI_MI_P_MISC_CD_QCH, + QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH, + QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH, + QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH, + QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH, + QCH_CON_LH_AXI_SI_P_EH_CD_QCH, + QCH_CON_LH_AXI_SI_P_GIC_CD_QCH, + QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH, + QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH, + QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH, + QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH, + QCH_CON_LH_AXI_SI_P_MISC_CD_QCH, + QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH, + QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH, + QCH_CON_NOCL0_CMU_NOCL0_QCH, + QCH_CON_PPC_CCI_M1_CYCLE_QCH, + QCH_CON_PPC_CCI_M1_EVENT_QCH, + QCH_CON_PPC_CCI_M2_EVENT_QCH, + QCH_CON_PPC_CCI_M3_EVENT_QCH, + QCH_CON_PPC_CCI_M4_EVENT_QCH, + QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH, + QCH_CON_PPC_CPUCL0_D0_EVENT_QCH, + QCH_CON_PPC_CPUCL0_D1_EVENT_QCH, + DMYQCH_CON_PPC_DBG_CC_QCH, + QCH_CON_PPC_EH_CYCLE_QCH, + QCH_CON_PPC_EH_EVENT_QCH, + QCH_CON_PPC_IO_CYCLE_QCH, + QCH_CON_PPC_IO_EVENT_QCH, + QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH, + QCH_CON_PPC_NOCL1A_M0_EVENT_QCH, + QCH_CON_PPC_NOCL1A_M1_EVENT_QCH, + QCH_CON_PPC_NOCL1A_M2_EVENT_QCH, + QCH_CON_PPC_NOCL1A_M3_EVENT_QCH, + QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH, + QCH_CON_PPC_NOCL1B_M0_EVENT_QCH, + QCH_CON_PPMU_ACE_CPUCL0_D0_QCH, + QCH_CON_PPMU_ACE_CPUCL0_D1_QCH, + QCH_CON_SFR_APBIF_CMU_TOPC_QCH, + QCH_CON_SLC_CB_TOP_QCH, + DMYQCH_CON_SLC_CH1_QCH, + DMYQCH_CON_SLC_CH2_QCH, + DMYQCH_CON_SLC_CH3_QCH, + DMYQCH_CON_SLC_CH_TOP_QCH, + QCH_CON_SLH_AXI_MI_G_NOCL0_QCH, + QCH_CON_SLH_AXI_SI_P_ALIVE_QCH, + QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH, + QCH_CON_SLH_AXI_SI_P_EH_QCH, + QCH_CON_SLH_AXI_SI_P_GIC_QCH, + QCH_CON_SLH_AXI_SI_P_MIF0_QCH, + QCH_CON_SLH_AXI_SI_P_MIF1_QCH, + QCH_CON_SLH_AXI_SI_P_MIF2_QCH, + QCH_CON_SLH_AXI_SI_P_MIF3_QCH, + QCH_CON_SLH_AXI_SI_P_MISC_QCH, + QCH_CON_SLH_AXI_SI_P_PERIC0_QCH, + QCH_CON_SLH_AXI_SI_P_PERIC1_QCH, + QCH_CON_SYSREG_NOCL0_QCH, + QCH_CON_TREX_D_NOCL0_QCH, + QCH_CON_TREX_P_NOCL0_QCH, + DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH, + QCH_CON_D_TZPC_NOCL1A_QCH, + QCH_CON_GPC_NOCL1A_QCH, + QCH_CON_LH_ACEL_MI_D0_G3D_QCH, + QCH_CON_LH_ACEL_MI_D1_G3D_QCH, + QCH_CON_LH_ACEL_MI_D2_G3D_QCH, + QCH_CON_LH_ACEL_MI_D3_G3D_QCH, + QCH_CON_LH_ACEL_MI_D_TPU_QCH, + QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH, + QCH_CON_LH_AST_SI_G_NOCL1A_QCH, + QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH, + QCH_CON_LH_AXI_MI_D0_AUR_QCH, + QCH_CON_LH_AXI_MI_D1_AUR_QCH, + QCH_CON_LH_AXI_MI_P_AUR_CD_QCH, + QCH_CON_LH_AXI_MI_P_G3D_CD_QCH, + QCH_CON_LH_AXI_MI_P_TPU_CD_QCH, + QCH_CON_LH_AXI_SI_P_AUR_CD_QCH, + QCH_CON_LH_AXI_SI_P_G3D_CD_QCH, + QCH_CON_LH_AXI_SI_P_TPU_CD_QCH, + QCH_CON_NOCL1A_CMU_NOCL1A_QCH, + QCH_CON_PPCFW_G3D0_QCH, + QCH_CON_PPCFW_G3D1_QCH, + QCH_CON_PPC_AUR_D0_CYCLE_QCH, + QCH_CON_PPC_AUR_D0_EVENT_QCH, + QCH_CON_PPC_AUR_D1_EVENT_QCH, + QCH_CON_PPC_G3D_D0_CYCLE_QCH, + QCH_CON_PPC_G3D_D0_EVENT_QCH, + QCH_CON_PPC_G3D_D1_EVENT_QCH, + QCH_CON_PPC_G3D_D2_EVENT_QCH, + QCH_CON_PPC_G3D_D3_EVENT_QCH, + QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH, + QCH_CON_PPC_NOCL2A_M0_EVENT_QCH, + QCH_CON_PPC_NOCL2A_M1_EVENT_QCH, + QCH_CON_PPC_NOCL2A_M2_EVENT_QCH, + QCH_CON_PPC_NOCL2A_M3_EVENT_QCH, + QCH_CON_PPC_TPU_CYCLE_QCH, + QCH_CON_PPC_TPU_EVENT_QCH, + QCH_CON_SLH_AXI_SI_P_AUR_QCH, + QCH_CON_SLH_AXI_SI_P_G3D_QCH, + QCH_CON_SLH_AXI_SI_P_TPU_QCH, + QCH_CON_SSMT_G3D0_QCH, + QCH_CON_SSMT_G3D1_QCH, + QCH_CON_SSMT_G3D2_QCH, + QCH_CON_SSMT_G3D3_QCH, + QCH_CON_SYSMMU_G3D_QCH_D0, + QCH_CON_SYSMMU_G3D_QCH_D1, + QCH_CON_SYSMMU_G3D_QCH_D2, + QCH_CON_SYSMMU_G3D_QCH_D3, + QCH_CON_SYSMMU_G3D_QCH_MPTW, + QCH_CON_SYSREG_NOCL1A_QCH, + QCH_CON_TREX_D_NOCL1A_QCH, + QCH_CON_TREX_P_NOCL1A_QCH, + DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH, + QCH_CON_D_TZPC_NOCL1B_QCH, + QCH_CON_GPC_NOCL1B_QCH, + QCH_CON_LH_ACEL_MI_D_HSI0_QCH, + QCH_CON_LH_ACEL_MI_D_HSI1_QCH, + QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH, + QCH_CON_LH_AST_SI_G_NOCL1B_QCH, + QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH, + QCH_CON_LH_AXI_MI_D_AOC_QCH, + QCH_CON_LH_AXI_MI_D_APM_QCH, + QCH_CON_LH_AXI_MI_D_GSA_QCH, + QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH, + QCH_CON_LH_AXI_MI_P_AOC_CD_QCH, + QCH_CON_LH_AXI_MI_P_GSA_CD_QCH, + QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH, + QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH, + QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH, + QCH_CON_LH_AXI_SI_P_AOC_CD_QCH, + QCH_CON_LH_AXI_SI_P_GSA_CD_QCH, + QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH, + QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH, + QCH_CON_NOCL1B_CMU_NOCL1B_QCH, + QCH_CON_PPC_AOC_CYCLE_QCH, + QCH_CON_PPC_AOC_EVENT_QCH, + QCH_CON_SLH_AXI_MI_G_CSSYS_QCH, + QCH_CON_SLH_AXI_SI_P_AOC_QCH, + QCH_CON_SLH_AXI_SI_P_GSA_QCH, + QCH_CON_SLH_AXI_SI_P_HSI0_QCH, + QCH_CON_SLH_AXI_SI_P_HSI1_QCH, + QCH_CON_SYSREG_NOCL1B_QCH, + QCH_CON_TREX_D_NOCL1B_QCH, + QCH_CON_TREX_P_NOCL1B_QCH, + DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH, + QCH_CON_D_TZPC_NOCL2A_QCH, + QCH_CON_GPC_NOCL2A_QCH, + QCH_CON_LH_ACEL_MI_D2_G2D_QCH, + QCH_CON_LH_ACEL_MI_D_HSI2_QCH, + QCH_CON_LH_ACEL_MI_D_MISC_QCH, + QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH, + QCH_CON_LH_AST_SI_G_NOCL2A_QCH, + QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH, + QCH_CON_LH_AXI_MI_D0_CSIS_QCH, + QCH_CON_LH_AXI_MI_D0_DPU_QCH, + QCH_CON_LH_AXI_MI_D0_G2D_QCH, + QCH_CON_LH_AXI_MI_D0_GDC_QCH, + QCH_CON_LH_AXI_MI_D0_MCSC_QCH, + QCH_CON_LH_AXI_MI_D0_MFC_QCH, + QCH_CON_LH_AXI_MI_D0_TNR_QCH, + QCH_CON_LH_AXI_MI_D1_CSIS_QCH, + QCH_CON_LH_AXI_MI_D1_DPU_QCH, + QCH_CON_LH_AXI_MI_D1_G2D_QCH, + QCH_CON_LH_AXI_MI_D1_GDC_QCH, + QCH_CON_LH_AXI_MI_D1_MCSC_QCH, + QCH_CON_LH_AXI_MI_D1_MFC_QCH, + QCH_CON_LH_AXI_MI_D1_TNR_QCH, + QCH_CON_LH_AXI_MI_D2_DPU_QCH, + QCH_CON_LH_AXI_MI_D2_GDC_QCH, + QCH_CON_LH_AXI_MI_D2_MCSC_QCH, + QCH_CON_LH_AXI_MI_D2_TNR_QCH, + QCH_CON_LH_AXI_MI_D3_TNR_QCH, + QCH_CON_LH_AXI_MI_D4_TNR_QCH, + QCH_CON_LH_AXI_MI_D_BO_QCH, + QCH_CON_LH_AXI_MI_D_DNS_QCH, + QCH_CON_LH_AXI_MI_D_G3AA_QCH, + QCH_CON_LH_AXI_MI_D_IPP_QCH, + QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH, + QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH, + QCH_CON_NOCL2A_CMU_NOCL2A_QCH, + QCH_CON_SLH_AXI_SI_P_BO_QCH, + QCH_CON_SLH_AXI_SI_P_CSIS_QCH, + QCH_CON_SLH_AXI_SI_P_DISP_QCH, + QCH_CON_SLH_AXI_SI_P_DNS_QCH, + QCH_CON_SLH_AXI_SI_P_DPU_QCH, + QCH_CON_SLH_AXI_SI_P_G2D_QCH, + QCH_CON_SLH_AXI_SI_P_G3AA_QCH, + QCH_CON_SLH_AXI_SI_P_GDC_QCH, + QCH_CON_SLH_AXI_SI_P_HSI2_QCH, + QCH_CON_SLH_AXI_SI_P_IPP_QCH, + QCH_CON_SLH_AXI_SI_P_ITP_QCH, + QCH_CON_SLH_AXI_SI_P_MCSC_QCH, + QCH_CON_SLH_AXI_SI_P_MFC_QCH, + QCH_CON_SLH_AXI_SI_P_PDP_QCH, + QCH_CON_SLH_AXI_SI_P_TNR_QCH, + QCH_CON_SYSREG_NOCL2A_QCH, + QCH_CON_TREX_D_NOCL2A_QCH, + QCH_CON_TREX_P_NOCL2A_QCH, + QCH_CON_D_TZPC_PDP_QCH, + QCH_CON_GPC_PDP_QCH, + QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH, + QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH, + QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH, + QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH, + QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH, + QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH, + QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH, + QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH, + QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH, + QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH, + QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH, + QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH, + QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH, + QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH, + QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH, + QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH, + QCH_CON_PDP_CMU_PDP_QCH, + QCH_CON_PDP_TOP_QCH_C2_PDP, + QCH_CON_PDP_TOP_QCH_PDP_TOP, + QCH_CON_PPMU_VRA_QCH, + QCH_CON_QE_PDP_AF0_QCH, + QCH_CON_QE_PDP_AF1_QCH, + QCH_CON_QE_PDP_STAT0_QCH, + QCH_CON_QE_PDP_STAT1_QCH, + QCH_CON_QE_VRA_QCH, + QCH_CON_SLH_AXI_MI_P_PDP_QCH, + QCH_CON_SSMT_PDP_STAT_QCH, + QCH_CON_SSMT_VRA_QCH, + QCH_CON_SYSREG_PDP_QCH, + QCH_CON_VRA_QCH, + QCH_CON_D_TZPC_PERIC0_QCH, + QCH_CON_GPC_PERIC0_QCH, + QCH_CON_GPIO_PERIC0_QCH, + DMYQCH_CON_I3C1_QCH_SCLK, + QCH_CON_I3C1_QCH_PCLK, + DMYQCH_CON_I3C2_QCH_SCLK, + QCH_CON_I3C2_QCH_PCLK, + DMYQCH_CON_I3C3_QCH_SCLK, + QCH_CON_I3C3_QCH_PCLK, + DMYQCH_CON_I3C4_QCH_SCLK, + QCH_CON_I3C4_QCH_PCLK, + DMYQCH_CON_I3C5_QCH_SCLK, + QCH_CON_I3C5_QCH_PCLK, + DMYQCH_CON_I3C6_QCH_SCLK, + QCH_CON_I3C6_QCH_PCLK, + DMYQCH_CON_I3C7_QCH_SCLK, + QCH_CON_I3C7_QCH_PCLK, + DMYQCH_CON_I3C8_QCH_SCLK, + QCH_CON_I3C8_QCH_PCLK, + QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH, + QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH, + QCH_CON_PERIC0_CMU_PERIC0_QCH, + QCH_CON_SLH_AXI_MI_P_PERIC0_QCH, + QCH_CON_SYSREG_PERIC0_QCH, + QCH_CON_USI0_UART_QCH, + QCH_CON_USI14_USI_QCH, + QCH_CON_USI1_USI_QCH, + QCH_CON_USI2_USI_QCH, + QCH_CON_USI3_USI_QCH, + QCH_CON_USI4_USI_QCH, + QCH_CON_USI5_USI_QCH, + QCH_CON_USI6_USI_QCH, + QCH_CON_USI7_USI_QCH, + QCH_CON_USI8_USI_QCH, + QCH_CON_D_TZPC_PERIC1_QCH, + QCH_CON_GPC_PERIC1_QCH, + QCH_CON_GPIO_PERIC1_QCH, + DMYQCH_CON_I3C0_QCH_SCLK, + QCH_CON_I3C0_QCH_PCLK, + QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH, + QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH, + QCH_CON_PERIC1_CMU_PERIC1_QCH, + QCH_CON_PWM_QCH, + QCH_CON_SLH_AXI_MI_P_PERIC1_QCH, + QCH_CON_SYSREG_PERIC1_QCH, + QCH_CON_USI0_USI_QCH, + QCH_CON_USI10_USI_QCH, + QCH_CON_USI11_USI_QCH, + QCH_CON_USI12_USI_QCH, + QCH_CON_USI13_USI_QCH, + QCH_CON_USI15_USI_QCH, + QCH_CON_USI16_USI_QCH, + QCH_CON_USI9_USI_QCH, + DMYQCH_CON_BIS_S2D_QCH, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH, + QCH_CON_S2D_CMU_S2D_QCH, + QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH, + QCH_CON_D_TZPC_TNR_QCH, + QCH_CON_GPC_TNR_QCH, + QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH, + QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH, + QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH, + QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH, + QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH, + QCH_CON_LH_AXI_SI_D0_TNR_QCH, + QCH_CON_LH_AXI_SI_D1_TNR_QCH, + QCH_CON_LH_AXI_SI_D2_TNR_QCH, + QCH_CON_LH_AXI_SI_D3_TNR_QCH, + QCH_CON_LH_AXI_SI_D4_TNR_QCH, + QCH_CON_PPMU_D0_TNR_QCH, + QCH_CON_PPMU_D1_TNR_QCH, + QCH_CON_PPMU_D2_TNR_QCH, + QCH_CON_PPMU_D3_TNR_QCH, + QCH_CON_PPMU_D4_TNR_QCH, + QCH_CON_PPMU_D5_TNR_QCH, + QCH_CON_PPMU_D6_TNR_QCH, + QCH_CON_PPMU_D7_TNR_QCH, + QCH_CON_PPMU_D8_TNR_QCH, + QCH_CON_QE_D0_TNR_QCH, + QCH_CON_QE_D1_TNR_QCH, + QCH_CON_QE_D5_TNR_QCH, + QCH_CON_QE_D6_TNR_QCH, + QCH_CON_QE_D7_TNR_QCH, + QCH_CON_QE_D8_TNR_QCH, + QCH_CON_SLH_AXI_MI_P_TNR_QCH, + QCH_CON_SSMT_D0_TNR_QCH, + QCH_CON_SSMT_D1_TNR_QCH, + QCH_CON_SSMT_D2_TNR_QCH, + QCH_CON_SSMT_D3_TNR_QCH, + QCH_CON_SSMT_D4_TNR_QCH, + QCH_CON_SSMT_D5_TNR_QCH, + QCH_CON_SSMT_D6_TNR_QCH, + QCH_CON_SSMT_D7_TNR_QCH, + QCH_CON_SSMT_D8_TNR_QCH, + QCH_CON_SYSMMU_D0_TNR_QCH_S1, + QCH_CON_SYSMMU_D0_TNR_QCH_S2, + QCH_CON_SYSMMU_D1_TNR_QCH_S1, + QCH_CON_SYSMMU_D1_TNR_QCH_S2, + QCH_CON_SYSMMU_D2_TNR_QCH_S2, + QCH_CON_SYSMMU_D2_TNR_QCH_S1, + QCH_CON_SYSMMU_D3_TNR_QCH_S2, + QCH_CON_SYSMMU_D3_TNR_QCH_S1, + QCH_CON_SYSMMU_D4_TNR_QCH_S1, + QCH_CON_SYSMMU_D4_TNR_QCH_S2, + QCH_CON_SYSREG_TNR_QCH, + QCH_CON_TNR_QCH_C2, + QCH_CON_TNR_QCH_ACLK, + QCH_CON_TNR_CMU_TNR_QCH, + QCH_CON_BUSIF_HPMTPU_QCH, + QCH_CON_D_TZPC_TPU_QCH, + QCH_CON_GPC_TPU_QCH, + QCH_CON_LH_ACEL_SI_D_TPU_QCH, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH, + QCH_CON_LH_AXI_MI_P_TPU_CU_QCH, + QCH_CON_LH_AXI_SI_P_TPU_CU_QCH, + QCH_CON_PPMU_TPU_QCH, + QCH_CON_SLH_AXI_MI_P_TPU_QCH, + QCH_CON_SSMT_TPU_QCH, + QCH_CON_SYSMMU_TPU_QCH_S1, + QCH_CON_SYSMMU_TPU_QCH_S2, + QCH_CON_SYSREG_TPU_QCH, + DMYQCH_CON_TPU_QCH, + QCH_CON_TPU_CMU_TPU_QCH, + AOC_CMU_AOC_CONTROLLER_OPTION, + APM_CMU_APM_CONTROLLER_OPTION, + AUR_CMU_AUR_CONTROLLER_OPTION, + BO_CMU_BO_CONTROLLER_OPTION, + CMU_CMU_TOP_CONTROLLER_OPTION, + CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION, + CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION, + CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION, + CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION, + CSIS_CMU_CSIS_CONTROLLER_OPTION, + DISP_CMU_DISP_CONTROLLER_OPTION, + DNS_CMU_DNS_CONTROLLER_OPTION, + DPU_CMU_DPU_CONTROLLER_OPTION, + EH_CMU_EH_CONTROLLER_OPTION, + G2D_CMU_G2D_CONTROLLER_OPTION, + G3AA_CMU_G3AA_CONTROLLER_OPTION, + G3D_CMU_G3D_CONTROLLER_OPTION, + G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION, + GDC_CMU_GDC_CONTROLLER_OPTION, + GSACORE_CMU_GSACORE_CONTROLLER_OPTION, + GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION, + HSI0_CMU_HSI0_CONTROLLER_OPTION, + HSI1_CMU_HSI1_CONTROLLER_OPTION, + HSI2_CMU_HSI2_CONTROLLER_OPTION, + IPP_CMU_IPP_CONTROLLER_OPTION, + ITP_CMU_ITP_CONTROLLER_OPTION, + MCSC_CMU_MCSC_CONTROLLER_OPTION, + MFC_CMU_MFC_CONTROLLER_OPTION, + MIF_CMU_MIF_CONTROLLER_OPTION, + MISC_CMU_MISC_CONTROLLER_OPTION, + NOCL0_CMU_NOCL0_CONTROLLER_OPTION, + NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION, + NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION, + NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION, + NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION, + NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION, + NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION, + NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION, + PDP_CMU_PDP_CONTROLLER_OPTION, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION, + PERIC1_CMU_PERIC1_CONTROLLER_OPTION, + S2D_CMU_S2D_CONTROLLER_OPTION, + TNR_CMU_TNR_CONTROLLER_OPTION, + TPU_CMU_TPU_CONTROLLER_OPTION, + end_of_sfr, + num_of_sfr = end_of_sfr - SFR_TYPE, +}; + +enum sfr_access_id { + PLL_LOCKTIME_PLL_AUR_PLL_LOCK_TIME = SFR_ACCESS_TYPE, + PLL_CON3_PLL_AUR_ENABLE, + PLL_CON3_PLL_AUR_STABLE, + PLL_CON3_PLL_AUR_DIV_P, + PLL_CON3_PLL_AUR_DIV_M, + PLL_CON3_PLL_AUR_DIV_S, + PLL_CON4_PLL_AUR_ICP, + PLL_CON4_PLL_AUR_LOCK_CON_IN, + PLL_CON4_PLL_AUR_LOCK_CON_OUT, + PLL_CON4_PLL_AUR_LOCK_CON_DLY, + PLL_CON4_PLL_AUR_AFC_ENB, + PLL_CON4_PLL_AUR_EXT_AFC, + DBG_NFO_PLL_AUR_AFC_CODE, + PLL_CON4_PLL_AUR_FOUT_MASK, + PLL_CON4_PLL_AUR_RSEL, + PLL_CON4_PLL_AUR_BYPASS, + PLL_CON0_PLL_AUR_MUX_SEL, + PLL_CON0_PLL_AUR_MUX_BUSY, + PLL_LOCKTIME_PLL_AUR_RESET_REQ_TIME, + PLL_CON1_PLL_AUR_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_AUR_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_AUR_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_AUR_USE_HW_LOCK_DET, + PLL_CON3_PLL_AUR_LOCK_FAIL, + PLL_CON3_PLL_AUR_USE_LOCK_FAIL, + PLL_CON1_PLL_AUR_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_AUR_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_AUR_MANUAL_PLL_CTRL, + PLL_CON1_PLL_AUR_AUTO_PLL_CTRL, + DBG_NFO_PLL_AUR_DEBUG_INFO, + PLL_CON2_PLL_AUR_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_AUR_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_AUR_OVERRIDE_BY_HCH, + PLL_CON3_PLL_AUR_LOCK_EN, + PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, + PLL_CON3_PLL_SHARED0_ENABLE, + PLL_CON3_PLL_SHARED0_STABLE, + PLL_CON3_PLL_SHARED0_DIV_P, + PLL_CON3_PLL_SHARED0_DIV_M, + PLL_CON3_PLL_SHARED0_DIV_S, + PLL_CON4_PLL_SHARED0_ICP, + PLL_CON4_PLL_SHARED0_LOCK_CON_IN, + PLL_CON4_PLL_SHARED0_LOCK_CON_OUT, + PLL_CON4_PLL_SHARED0_LOCK_CON_DLY, + PLL_CON4_PLL_SHARED0_AFC_ENB, + PLL_CON4_PLL_SHARED0_EXT_AFC, + DBG_NFO_PLL_SHARED0_AFC_CODE, + PLL_CON4_PLL_SHARED0_FOUT_MASK, + PLL_CON4_PLL_SHARED0_RSEL, + PLL_CON4_PLL_SHARED0_BYPASS, + PLL_CON0_PLL_SHARED0_MUX_SEL, + PLL_CON0_PLL_SHARED0_MUX_BUSY, + PLL_LOCKTIME_PLL_SHARED0_RESET_REQ_TIME, + PLL_CON1_PLL_SHARED0_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_SHARED0_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_SHARED0_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_SHARED0_USE_HW_LOCK_DET, + PLL_CON3_PLL_SHARED0_LOCK_FAIL, + PLL_CON3_PLL_SHARED0_USE_LOCK_FAIL, + PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_SHARED0_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_SHARED0_MANUAL_PLL_CTRL, + PLL_CON1_PLL_SHARED0_AUTO_PLL_CTRL, + DBG_NFO_PLL_SHARED0_DEBUG_INFO, + PLL_CON2_PLL_SHARED0_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_SHARED0_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_SHARED0_OVERRIDE_BY_HCH, + PLL_CON3_PLL_SHARED0_LOCK_EN, + PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, + PLL_CON3_PLL_SHARED1_ENABLE, + PLL_CON3_PLL_SHARED1_STABLE, + PLL_CON3_PLL_SHARED1_DIV_P, + PLL_CON3_PLL_SHARED1_DIV_M, + PLL_CON3_PLL_SHARED1_DIV_S, + PLL_CON4_PLL_SHARED1_ICP, + PLL_CON4_PLL_SHARED1_LOCK_CON_IN, + PLL_CON4_PLL_SHARED1_LOCK_CON_OUT, + PLL_CON4_PLL_SHARED1_LOCK_CON_DLY, + PLL_CON4_PLL_SHARED1_AFC_ENB, + PLL_CON4_PLL_SHARED1_EXT_AFC, + DBG_NFO_PLL_SHARED1_AFC_CODE, + PLL_CON4_PLL_SHARED1_FOUT_MASK, + PLL_CON4_PLL_SHARED1_RSEL, + PLL_CON4_PLL_SHARED1_BYPASS, + PLL_CON0_PLL_SHARED1_MUX_SEL, + PLL_CON0_PLL_SHARED1_MUX_BUSY, + PLL_LOCKTIME_PLL_SHARED1_RESET_REQ_TIME, + PLL_CON1_PLL_SHARED1_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_SHARED1_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_SHARED1_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_SHARED1_USE_HW_LOCK_DET, + PLL_CON3_PLL_SHARED1_LOCK_FAIL, + PLL_CON3_PLL_SHARED1_USE_LOCK_FAIL, + PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_SHARED1_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_SHARED1_MANUAL_PLL_CTRL, + PLL_CON1_PLL_SHARED1_AUTO_PLL_CTRL, + DBG_NFO_PLL_SHARED1_DEBUG_INFO, + PLL_CON2_PLL_SHARED1_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_SHARED1_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_SHARED1_OVERRIDE_BY_HCH, + PLL_CON3_PLL_SHARED1_LOCK_EN, + PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, + PLL_CON3_PLL_SHARED2_ENABLE, + PLL_CON3_PLL_SHARED2_STABLE, + PLL_CON3_PLL_SHARED2_DIV_P, + PLL_CON3_PLL_SHARED2_DIV_M, + PLL_CON3_PLL_SHARED2_DIV_S, + PLL_CON4_PLL_SHARED2_ICP, + PLL_CON4_PLL_SHARED2_LOCK_CON_IN, + PLL_CON4_PLL_SHARED2_LOCK_CON_OUT, + PLL_CON4_PLL_SHARED2_LOCK_CON_DLY, + PLL_CON4_PLL_SHARED2_AFC_ENB, + PLL_CON4_PLL_SHARED2_EXT_AFC, + DBG_NFO_PLL_SHARED2_AFC_CODE, + PLL_CON4_PLL_SHARED2_FOUT_MASK, + PLL_CON4_PLL_SHARED2_RSEL, + PLL_CON4_PLL_SHARED2_BYPASS, + PLL_CON0_PLL_SHARED2_MUX_SEL, + PLL_CON0_PLL_SHARED2_MUX_BUSY, + PLL_LOCKTIME_PLL_SHARED2_RESET_REQ_TIME, + PLL_CON1_PLL_SHARED2_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_SHARED2_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_SHARED2_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_SHARED2_USE_HW_LOCK_DET, + PLL_CON3_PLL_SHARED2_LOCK_FAIL, + PLL_CON3_PLL_SHARED2_USE_LOCK_FAIL, + PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_SHARED2_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_SHARED2_MANUAL_PLL_CTRL, + PLL_CON1_PLL_SHARED2_AUTO_PLL_CTRL, + DBG_NFO_PLL_SHARED2_DEBUG_INFO, + PLL_CON2_PLL_SHARED2_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_SHARED2_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_SHARED2_OVERRIDE_BY_HCH, + PLL_CON3_PLL_SHARED2_LOCK_EN, + PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, + PLL_CON3_PLL_SHARED3_ENABLE, + PLL_CON3_PLL_SHARED3_STABLE, + PLL_CON3_PLL_SHARED3_DIV_P, + PLL_CON3_PLL_SHARED3_DIV_M, + PLL_CON3_PLL_SHARED3_DIV_S, + PLL_CON4_PLL_SHARED3_ICP, + PLL_CON4_PLL_SHARED3_LOCK_CON_IN, + PLL_CON4_PLL_SHARED3_LOCK_CON_OUT, + PLL_CON4_PLL_SHARED3_LOCK_CON_DLY, + PLL_CON4_PLL_SHARED3_AFC_ENB, + PLL_CON4_PLL_SHARED3_EXT_AFC, + DBG_NFO_PLL_SHARED3_AFC_CODE, + PLL_CON4_PLL_SHARED3_FOUT_MASK, + PLL_CON4_PLL_SHARED3_RSEL, + PLL_CON4_PLL_SHARED3_BYPASS, + PLL_CON0_PLL_SHARED3_MUX_SEL, + PLL_CON0_PLL_SHARED3_MUX_BUSY, + PLL_LOCKTIME_PLL_SHARED3_RESET_REQ_TIME, + PLL_CON1_PLL_SHARED3_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_SHARED3_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_SHARED3_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_SHARED3_USE_HW_LOCK_DET, + PLL_CON3_PLL_SHARED3_LOCK_FAIL, + PLL_CON3_PLL_SHARED3_USE_LOCK_FAIL, + PLL_CON1_PLL_SHARED3_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_SHARED3_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_SHARED3_MANUAL_PLL_CTRL, + PLL_CON1_PLL_SHARED3_AUTO_PLL_CTRL, + DBG_NFO_PLL_SHARED3_DEBUG_INFO, + PLL_CON2_PLL_SHARED3_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_SHARED3_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_SHARED3_OVERRIDE_BY_HCH, + PLL_CON3_PLL_SHARED3_LOCK_EN, + PLL_LOCKTIME_PLL_SPARE_PLL_LOCK_TIME, + PLL_CON3_PLL_SPARE_ENABLE, + PLL_CON3_PLL_SPARE_STABLE, + PLL_CON3_PLL_SPARE_DIV_P, + PLL_CON3_PLL_SPARE_DIV_M, + PLL_CON3_PLL_SPARE_DIV_S, + PLL_CON4_PLL_SPARE_ICP, + PLL_CON4_PLL_SPARE_LOCK_CON_IN, + PLL_CON4_PLL_SPARE_LOCK_CON_OUT, + PLL_CON4_PLL_SPARE_LOCK_CON_DLY, + PLL_CON4_PLL_SPARE_AFC_ENB, + PLL_CON4_PLL_SPARE_EXT_AFC, + DBG_NFO_PLL_SPARE_AFC_CODE, + PLL_CON4_PLL_SPARE_FOUT_MASK, + PLL_CON4_PLL_SPARE_RSEL, + PLL_CON4_PLL_SPARE_BYPASS, + PLL_CON0_PLL_SPARE_MUX_SEL, + PLL_CON0_PLL_SPARE_MUX_BUSY, + PLL_LOCKTIME_PLL_SPARE_RESET_REQ_TIME, + PLL_CON1_PLL_SPARE_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_SPARE_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_SPARE_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_SPARE_USE_HW_LOCK_DET, + PLL_CON3_PLL_SPARE_LOCK_FAIL, + PLL_CON3_PLL_SPARE_USE_LOCK_FAIL, + PLL_CON1_PLL_SPARE_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_SPARE_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_SPARE_MANUAL_PLL_CTRL, + PLL_CON1_PLL_SPARE_AUTO_PLL_CTRL, + DBG_NFO_PLL_SPARE_DEBUG_INFO, + PLL_CON2_PLL_SPARE_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_SPARE_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_SPARE_OVERRIDE_BY_HCH, + PLL_CON3_PLL_SPARE_LOCK_EN, + PLL_LOCKTIME_PLL_LF_MIF_PLL_LOCK_TIME, + PLL_CON3_PLL_LF_MIF_ENABLE, + PLL_CON3_PLL_LF_MIF_STABLE, + PLL_CON3_PLL_LF_MIF_DIV_P, + PLL_CON3_PLL_LF_MIF_DIV_M, + PLL_CON3_PLL_LF_MIF_DIV_S, + PLL_CON4_PLL_LF_MIF_ICP, + PLL_CON4_PLL_LF_MIF_LOCK_CON_IN, + PLL_CON4_PLL_LF_MIF_LOCK_CON_OUT, + PLL_CON4_PLL_LF_MIF_LOCK_CON_DLY, + PLL_CON4_PLL_LF_MIF_AFC_ENB, + PLL_CON4_PLL_LF_MIF_EXT_AFC, + DBG_NFO_PLL_LF_MIF_AFC_CODE, + PLL_CON4_PLL_LF_MIF_FOUT_MASK, + PLL_CON4_PLL_LF_MIF_RSEL, + PLL_CON4_PLL_LF_MIF_BYPASS, + PLL_CON0_PLL_LF_MIF_MUX_SEL, + PLL_CON0_PLL_LF_MIF_MUX_BUSY, + PLL_LOCKTIME_PLL_LF_MIF_RESET_REQ_TIME, + PLL_CON1_PLL_LF_MIF_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_LF_MIF_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_LF_MIF_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_LF_MIF_USE_HW_LOCK_DET, + PLL_CON3_PLL_LF_MIF_LOCK_FAIL, + PLL_CON3_PLL_LF_MIF_USE_LOCK_FAIL, + PLL_CON1_PLL_LF_MIF_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_LF_MIF_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_LF_MIF_MANUAL_PLL_CTRL, + PLL_CON1_PLL_LF_MIF_AUTO_PLL_CTRL, + DBG_NFO_PLL_LF_MIF_DEBUG_INFO, + PLL_CON2_PLL_LF_MIF_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_LF_MIF_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_LF_MIF_OVERRIDE_BY_HCH, + PLL_CON3_PLL_LF_MIF_LOCK_EN, + PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, + PLL_CON3_PLL_CPUCL0_ENABLE, + PLL_CON3_PLL_CPUCL0_STABLE, + PLL_CON3_PLL_CPUCL0_DIV_P, + PLL_CON3_PLL_CPUCL0_DIV_M, + PLL_CON3_PLL_CPUCL0_DIV_S, + PLL_CON4_PLL_CPUCL0_ICP, + PLL_CON4_PLL_CPUCL0_LOCK_CON_IN, + PLL_CON4_PLL_CPUCL0_LOCK_CON_OUT, + PLL_CON4_PLL_CPUCL0_LOCK_CON_DLY, + PLL_CON4_PLL_CPUCL0_AFC_ENB, + PLL_CON4_PLL_CPUCL0_EXT_AFC, + DBG_NFO_PLL_CPUCL0_AFC_CODE, + PLL_CON4_PLL_CPUCL0_FOUT_MASK, + PLL_CON4_PLL_CPUCL0_RSEL, + PLL_CON4_PLL_CPUCL0_BYPASS, + PLL_CON0_PLL_CPUCL0_MUX_SEL, + PLL_CON0_PLL_CPUCL0_MUX_BUSY, + PLL_LOCKTIME_PLL_CPUCL0_RESET_REQ_TIME, + PLL_CON1_PLL_CPUCL0_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_CPUCL0_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_CPUCL0_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_CPUCL0_USE_HW_LOCK_DET, + PLL_CON3_PLL_CPUCL0_LOCK_FAIL, + PLL_CON3_PLL_CPUCL0_USE_LOCK_FAIL, + PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_CPUCL0_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_CPUCL0_MANUAL_PLL_CTRL, + PLL_CON1_PLL_CPUCL0_AUTO_PLL_CTRL, + DBG_NFO_PLL_CPUCL0_DEBUG_INFO, + PLL_CON2_PLL_CPUCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_CPUCL0_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_CPUCL0_OVERRIDE_BY_HCH, + PLL_CON3_PLL_CPUCL0_LOCK_EN, + PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, + PLL_CON3_PLL_CPUCL1_ENABLE, + PLL_CON3_PLL_CPUCL1_STABLE, + PLL_CON3_PLL_CPUCL1_DIV_P, + PLL_CON3_PLL_CPUCL1_DIV_M, + PLL_CON3_PLL_CPUCL1_DIV_S, + PLL_CON4_PLL_CPUCL1_ICP, + PLL_CON4_PLL_CPUCL1_LOCK_CON_IN, + PLL_CON4_PLL_CPUCL1_LOCK_CON_OUT, + PLL_CON4_PLL_CPUCL1_LOCK_CON_DLY, + PLL_CON4_PLL_CPUCL1_AFC_ENB, + PLL_CON4_PLL_CPUCL1_EXT_AFC, + DBG_NFO_PLL_CPUCL1_AFC_CODE, + PLL_CON4_PLL_CPUCL1_FOUT_MASK, + PLL_CON4_PLL_CPUCL1_RSEL, + PLL_CON4_PLL_CPUCL1_BYPASS, + PLL_CON0_PLL_CPUCL1_MUX_SEL, + PLL_CON0_PLL_CPUCL1_MUX_BUSY, + PLL_LOCKTIME_PLL_CPUCL1_RESET_REQ_TIME, + PLL_CON1_PLL_CPUCL1_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_CPUCL1_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_CPUCL1_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_CPUCL1_USE_HW_LOCK_DET, + PLL_CON3_PLL_CPUCL1_LOCK_FAIL, + PLL_CON3_PLL_CPUCL1_USE_LOCK_FAIL, + PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_CPUCL1_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_CPUCL1_MANUAL_PLL_CTRL, + PLL_CON1_PLL_CPUCL1_AUTO_PLL_CTRL, + DBG_NFO_PLL_CPUCL1_DEBUG_INFO, + PLL_CON2_PLL_CPUCL1_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_CPUCL1_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_CPUCL1_OVERRIDE_BY_HCH, + PLL_CON3_PLL_CPUCL1_LOCK_EN, + PLL_LOCKTIME_PLL_CPUCL2_PLL_LOCK_TIME, + PLL_CON3_PLL_CPUCL2_ENABLE, + PLL_CON3_PLL_CPUCL2_STABLE, + PLL_CON3_PLL_CPUCL2_DIV_P, + PLL_CON3_PLL_CPUCL2_DIV_M, + PLL_CON3_PLL_CPUCL2_DIV_S, + PLL_CON4_PLL_CPUCL2_ICP, + PLL_CON4_PLL_CPUCL2_LOCK_CON_IN, + PLL_CON4_PLL_CPUCL2_LOCK_CON_OUT, + PLL_CON4_PLL_CPUCL2_LOCK_CON_DLY, + PLL_CON4_PLL_CPUCL2_AFC_ENB, + PLL_CON4_PLL_CPUCL2_EXT_AFC, + DBG_NFO_PLL_CPUCL2_AFC_CODE, + PLL_CON4_PLL_CPUCL2_FOUT_MASK, + PLL_CON4_PLL_CPUCL2_RSEL, + PLL_CON4_PLL_CPUCL2_BYPASS, + PLL_CON0_PLL_CPUCL2_MUX_SEL, + PLL_CON0_PLL_CPUCL2_MUX_BUSY, + PLL_LOCKTIME_PLL_CPUCL2_RESET_REQ_TIME, + PLL_CON1_PLL_CPUCL2_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_CPUCL2_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_CPUCL2_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_CPUCL2_USE_HW_LOCK_DET, + PLL_CON3_PLL_CPUCL2_LOCK_FAIL, + PLL_CON3_PLL_CPUCL2_USE_LOCK_FAIL, + PLL_CON1_PLL_CPUCL2_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_CPUCL2_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_CPUCL2_MANUAL_PLL_CTRL, + PLL_CON1_PLL_CPUCL2_AUTO_PLL_CTRL, + DBG_NFO_PLL_CPUCL2_DEBUG_INFO, + PLL_CON2_PLL_CPUCL2_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_CPUCL2_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_CPUCL2_OVERRIDE_BY_HCH, + PLL_CON3_PLL_CPUCL2_LOCK_EN, + PLL_CON6_PLL_CPUCL2_RESETB_REG, + PLL_CON6_PLL_CPUCL2_VREG_CON, + PLL_CON6_PLL_CPUCL2_VBGR_CON, + PLL_CON6_PLL_CPUCL2_STABLE_REG, + PLL_LOCKTIME_REG_PLL_CPUCL2_PLL_LOCK_TIME_REG, + PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, + PLL_CON3_PLL_G3D_ENABLE, + PLL_CON3_PLL_G3D_STABLE, + PLL_CON3_PLL_G3D_DIV_P, + PLL_CON3_PLL_G3D_DIV_M, + PLL_CON3_PLL_G3D_DIV_S, + PLL_CON4_PLL_G3D_ICP, + PLL_CON4_PLL_G3D_LOCK_CON_IN, + PLL_CON4_PLL_G3D_LOCK_CON_OUT, + PLL_CON4_PLL_G3D_LOCK_CON_DLY, + PLL_CON4_PLL_G3D_AFC_ENB, + PLL_CON4_PLL_G3D_EXT_AFC, + DBG_NFO_PLL_G3D_AFC_CODE, + PLL_CON4_PLL_G3D_FOUT_MASK, + PLL_CON4_PLL_G3D_RSEL, + PLL_CON4_PLL_G3D_BYPASS, + PLL_CON0_PLL_G3D_MUX_SEL, + PLL_CON0_PLL_G3D_MUX_BUSY, + PLL_LOCKTIME_PLL_G3D_RESET_REQ_TIME, + PLL_CON1_PLL_G3D_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_G3D_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_G3D_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_G3D_USE_HW_LOCK_DET, + PLL_CON3_PLL_G3D_LOCK_FAIL, + PLL_CON3_PLL_G3D_USE_LOCK_FAIL, + PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_G3D_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_G3D_MANUAL_PLL_CTRL, + PLL_CON1_PLL_G3D_AUTO_PLL_CTRL, + DBG_NFO_PLL_G3D_DEBUG_INFO, + PLL_CON2_PLL_G3D_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_G3D_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_G3D_OVERRIDE_BY_HCH, + PLL_CON3_PLL_G3D_LOCK_EN, + PLL_LOCKTIME_PLL_G3D_L2_PLL_LOCK_TIME, + PLL_CON3_PLL_G3D_L2_ENABLE, + PLL_CON3_PLL_G3D_L2_STABLE, + PLL_CON3_PLL_G3D_L2_DIV_P, + PLL_CON3_PLL_G3D_L2_DIV_M, + PLL_CON3_PLL_G3D_L2_DIV_S, + PLL_CON4_PLL_G3D_L2_ICP, + PLL_CON4_PLL_G3D_L2_LOCK_CON_IN, + PLL_CON4_PLL_G3D_L2_LOCK_CON_OUT, + PLL_CON4_PLL_G3D_L2_LOCK_CON_DLY, + PLL_CON4_PLL_G3D_L2_AFC_ENB, + PLL_CON4_PLL_G3D_L2_EXT_AFC, + DBG_NFO_PLL_G3D_L2_AFC_CODE, + PLL_CON4_PLL_G3D_L2_FOUT_MASK, + PLL_CON4_PLL_G3D_L2_RSEL, + PLL_CON4_PLL_G3D_L2_BYPASS, + PLL_CON0_PLL_G3D_L2_MUX_SEL, + PLL_CON0_PLL_G3D_L2_MUX_BUSY, + PLL_LOCKTIME_PLL_G3D_L2_RESET_REQ_TIME, + PLL_CON1_PLL_G3D_L2_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_G3D_L2_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_G3D_L2_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_G3D_L2_USE_HW_LOCK_DET, + PLL_CON3_PLL_G3D_L2_LOCK_FAIL, + PLL_CON3_PLL_G3D_L2_USE_LOCK_FAIL, + PLL_CON1_PLL_G3D_L2_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_G3D_L2_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_G3D_L2_MANUAL_PLL_CTRL, + PLL_CON1_PLL_G3D_L2_AUTO_PLL_CTRL, + DBG_NFO_PLL_G3D_L2_DEBUG_INFO, + PLL_CON2_PLL_G3D_L2_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_G3D_L2_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_G3D_L2_OVERRIDE_BY_HCH, + PLL_CON3_PLL_G3D_L2_LOCK_EN, + PLL_LOCKTIME_PLL_USB_PLL_LOCK_TIME, + PLL_CON3_PLL_USB_ENABLE, + PLL_CON3_PLL_USB_STABLE, + PLL_CON3_PLL_USB_DIV_P, + PLL_CON3_PLL_USB_DIV_M, + PLL_CON3_PLL_USB_DIV_S, + PLL_CON4_PLL_USB_ICP, + PLL_CON4_PLL_USB_LOCK_CON_IN, + PLL_CON4_PLL_USB_LOCK_CON_OUT, + PLL_CON4_PLL_USB_LOCK_CON_DLY, + PLL_CON4_PLL_USB_AFC_ENB, + PLL_CON4_PLL_USB_EXT_AFC, + DBG_NFO_PLL_USB_AFC_CODE, + PLL_CON4_PLL_USB_FOUT_MASK, + PLL_CON4_PLL_USB_RSEL, + PLL_CON4_PLL_USB_BYPASS, + PLL_CON0_PLL_USB_MUX_SEL, + PLL_CON0_PLL_USB_MUX_BUSY, + PLL_LOCKTIME_PLL_USB_RESET_REQ_TIME, + PLL_CON1_PLL_USB_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_USB_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_USB_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_USB_USE_HW_LOCK_DET, + PLL_CON3_PLL_USB_LOCK_FAIL, + PLL_CON3_PLL_USB_USE_LOCK_FAIL, + PLL_CON1_PLL_USB_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_USB_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_USB_MANUAL_PLL_CTRL, + PLL_CON1_PLL_USB_AUTO_PLL_CTRL, + DBG_NFO_PLL_USB_DEBUG_INFO, + PLL_CON2_PLL_USB_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_USB_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_USB_OVERRIDE_BY_HCH, + PLL_CON3_PLL_USB_LOCK_EN, + PLL_LOCKTIME_PLL_MIF_MAIN_PLL_LOCK_TIME, + PLL_CON3_PLL_MIF_MAIN_ENABLE, + PLL_CON3_PLL_MIF_MAIN_STABLE, + PLL_CON3_PLL_MIF_MAIN_DIV_P, + PLL_CON3_PLL_MIF_MAIN_DIV_M, + PLL_CON3_PLL_MIF_MAIN_DIV_S, + PLL_CON4_PLL_MIF_MAIN_ICP, + PLL_CON4_PLL_MIF_MAIN_LOCK_CON_IN, + PLL_CON4_PLL_MIF_MAIN_LOCK_CON_OUT, + PLL_CON4_PLL_MIF_MAIN_LOCK_CON_DLY, + PLL_CON4_PLL_MIF_MAIN_AFC_ENB, + PLL_CON4_PLL_MIF_MAIN_EXT_AFC, + DBG_NFO_PLL_MIF_MAIN_AFC_CODE, + PLL_CON4_PLL_MIF_MAIN_FOUT_MASK, + PLL_CON4_PLL_MIF_MAIN_RSEL, + PLL_CON4_PLL_MIF_MAIN_BYPASS, + PLL_CON0_PLL_MIF_MAIN_MUX_SEL, + PLL_CON0_PLL_MIF_MAIN_MUX_BUSY, + PLL_LOCKTIME_PLL_MIF_MAIN_RESET_REQ_TIME, + PLL_CON1_PLL_MIF_MAIN_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_MIF_MAIN_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_MIF_MAIN_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_MIF_MAIN_USE_HW_LOCK_DET, + PLL_CON3_PLL_MIF_MAIN_LOCK_FAIL, + PLL_CON3_PLL_MIF_MAIN_USE_LOCK_FAIL, + PLL_CON1_PLL_MIF_MAIN_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_MIF_MAIN_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_MIF_MAIN_MANUAL_PLL_CTRL, + PLL_CON1_PLL_MIF_MAIN_AUTO_PLL_CTRL, + DBG_NFO_PLL_MIF_MAIN_DEBUG_INFO, + PLL_CON2_PLL_MIF_MAIN_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_MIF_MAIN_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_MIF_MAIN_OVERRIDE_BY_HCH, + PLL_CON3_PLL_MIF_MAIN_LOCK_EN, + PLL_CON6_PLL_MIF_MAIN_RESETB_REG, + PLL_CON6_PLL_MIF_MAIN_VREG_CON, + PLL_CON6_PLL_MIF_MAIN_VBGR_CON, + PLL_CON6_PLL_MIF_MAIN_STABLE_REG, + PLL_LOCKTIME_REG_PLL_MIF_MAIN_PLL_LOCK_TIME_REG, + PLL_LOCKTIME_PLL_MIF_SUB_PLL_LOCK_TIME, + PLL_CON3_PLL_MIF_SUB_ENABLE, + PLL_CON3_PLL_MIF_SUB_STABLE, + PLL_CON3_PLL_MIF_SUB_DIV_P, + PLL_CON3_PLL_MIF_SUB_DIV_M, + PLL_CON3_PLL_MIF_SUB_DIV_S, + PLL_CON4_PLL_MIF_SUB_ICP, + PLL_CON4_PLL_MIF_SUB_LOCK_CON_IN, + PLL_CON4_PLL_MIF_SUB_LOCK_CON_OUT, + PLL_CON4_PLL_MIF_SUB_LOCK_CON_DLY, + PLL_CON4_PLL_MIF_SUB_AFC_ENB, + PLL_CON4_PLL_MIF_SUB_EXT_AFC, + DBG_NFO_PLL_MIF_SUB_AFC_CODE, + PLL_CON4_PLL_MIF_SUB_FOUT_MASK, + PLL_CON4_PLL_MIF_SUB_RSEL, + PLL_CON4_PLL_MIF_SUB_BYPASS, + PLL_CON0_PLL_MIF_SUB_MUX_SEL, + PLL_CON0_PLL_MIF_SUB_MUX_BUSY, + PLL_LOCKTIME_PLL_MIF_SUB_RESET_REQ_TIME, + PLL_CON1_PLL_MIF_SUB_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_MIF_SUB_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_MIF_SUB_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_MIF_SUB_USE_HW_LOCK_DET, + PLL_CON3_PLL_MIF_SUB_LOCK_FAIL, + PLL_CON3_PLL_MIF_SUB_USE_LOCK_FAIL, + PLL_CON1_PLL_MIF_SUB_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_MIF_SUB_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_MIF_SUB_MANUAL_PLL_CTRL, + PLL_CON1_PLL_MIF_SUB_AUTO_PLL_CTRL, + DBG_NFO_PLL_MIF_SUB_DEBUG_INFO, + PLL_CON2_PLL_MIF_SUB_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_MIF_SUB_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_MIF_SUB_OVERRIDE_BY_HCH, + PLL_CON3_PLL_MIF_SUB_LOCK_EN, + PLL_CON6_PLL_MIF_SUB_RESETB_REG, + PLL_CON6_PLL_MIF_SUB_VREG_CON, + PLL_CON6_PLL_MIF_SUB_VBGR_CON, + PLL_CON6_PLL_MIF_SUB_STABLE_REG, + PLL_LOCKTIME_REG_PLL_MIF_SUB_PLL_LOCK_TIME_REG, + PLL_LOCKTIME_PLL_NOCL0_PLL_LOCK_TIME, + PLL_CON3_PLL_NOCL0_ENABLE, + PLL_CON3_PLL_NOCL0_STABLE, + PLL_CON3_PLL_NOCL0_DIV_P, + PLL_CON3_PLL_NOCL0_DIV_M, + PLL_CON3_PLL_NOCL0_DIV_S, + PLL_CON4_PLL_NOCL0_ICP, + PLL_CON4_PLL_NOCL0_LOCK_CON_IN, + PLL_CON4_PLL_NOCL0_LOCK_CON_OUT, + PLL_CON4_PLL_NOCL0_LOCK_CON_DLY, + PLL_CON4_PLL_NOCL0_AFC_ENB, + PLL_CON4_PLL_NOCL0_EXT_AFC, + DBG_NFO_PLL_NOCL0_AFC_CODE, + PLL_CON4_PLL_NOCL0_FOUT_MASK, + PLL_CON4_PLL_NOCL0_RSEL, + PLL_CON4_PLL_NOCL0_BYPASS, + PLL_CON0_PLL_NOCL0_MUX_SEL, + PLL_CON0_PLL_NOCL0_MUX_BUSY, + PLL_LOCKTIME_PLL_NOCL0_RESET_REQ_TIME, + PLL_CON1_PLL_NOCL0_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_NOCL0_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_NOCL0_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_NOCL0_USE_HW_LOCK_DET, + PLL_CON3_PLL_NOCL0_LOCK_FAIL, + PLL_CON3_PLL_NOCL0_USE_LOCK_FAIL, + PLL_CON1_PLL_NOCL0_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_NOCL0_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_NOCL0_MANUAL_PLL_CTRL, + PLL_CON1_PLL_NOCL0_AUTO_PLL_CTRL, + DBG_NFO_PLL_NOCL0_DEBUG_INFO, + PLL_CON2_PLL_NOCL0_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_NOCL0_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_NOCL0_OVERRIDE_BY_HCH, + PLL_CON3_PLL_NOCL0_LOCK_EN, + PLL_LOCKTIME_PLL_MIF_S2D_PLL_LOCK_TIME, + PLL_CON3_PLL_MIF_S2D_ENABLE, + PLL_CON3_PLL_MIF_S2D_STABLE, + PLL_CON3_PLL_MIF_S2D_DIV_P, + PLL_CON3_PLL_MIF_S2D_DIV_M, + PLL_CON3_PLL_MIF_S2D_DIV_S, + PLL_CON4_PLL_MIF_S2D_ICP, + PLL_CON4_PLL_MIF_S2D_LOCK_CON_IN, + PLL_CON4_PLL_MIF_S2D_LOCK_CON_OUT, + PLL_CON4_PLL_MIF_S2D_LOCK_CON_DLY, + PLL_CON4_PLL_MIF_S2D_AFC_ENB, + PLL_CON4_PLL_MIF_S2D_EXT_AFC, + DBG_NFO_PLL_MIF_S2D_AFC_CODE, + PLL_CON4_PLL_MIF_S2D_FOUT_MASK, + PLL_CON4_PLL_MIF_S2D_RSEL, + PLL_CON4_PLL_MIF_S2D_BYPASS, + PLL_CON0_PLL_MIF_S2D_MUX_SEL, + PLL_CON0_PLL_MIF_S2D_MUX_BUSY, + PLL_LOCKTIME_PLL_MIF_S2D_RESET_REQ_TIME, + PLL_CON1_PLL_MIF_S2D_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_MIF_S2D_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_MIF_S2D_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_MIF_S2D_USE_HW_LOCK_DET, + PLL_CON3_PLL_MIF_S2D_LOCK_FAIL, + PLL_CON3_PLL_MIF_S2D_USE_LOCK_FAIL, + PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_MIF_S2D_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_MIF_S2D_MANUAL_PLL_CTRL, + PLL_CON1_PLL_MIF_S2D_AUTO_PLL_CTRL, + DBG_NFO_PLL_MIF_S2D_DEBUG_INFO, + PLL_CON2_PLL_MIF_S2D_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_MIF_S2D_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_MIF_S2D_OVERRIDE_BY_HCH, + PLL_CON3_PLL_MIF_S2D_LOCK_EN, + PLL_CON6_PLL_MIF_S2D_RESETB_REG, + PLL_CON6_PLL_MIF_S2D_VREG_CON, + PLL_CON6_PLL_MIF_S2D_VBGR_CON, + PLL_CON6_PLL_MIF_S2D_STABLE_REG, + PLL_LOCKTIME_REG_PLL_MIF_S2D_PLL_LOCK_TIME_REG, + PLL_LOCKTIME_PLL_TPU_PLL_LOCK_TIME, + PLL_CON3_PLL_TPU_ENABLE, + PLL_CON3_PLL_TPU_STABLE, + PLL_CON3_PLL_TPU_DIV_P, + PLL_CON3_PLL_TPU_DIV_M, + PLL_CON3_PLL_TPU_DIV_S, + PLL_CON4_PLL_TPU_ICP, + PLL_CON4_PLL_TPU_LOCK_CON_IN, + PLL_CON4_PLL_TPU_LOCK_CON_OUT, + PLL_CON4_PLL_TPU_LOCK_CON_DLY, + PLL_CON4_PLL_TPU_AFC_ENB, + PLL_CON4_PLL_TPU_EXT_AFC, + DBG_NFO_PLL_TPU_AFC_CODE, + PLL_CON4_PLL_TPU_FOUT_MASK, + PLL_CON4_PLL_TPU_RSEL, + PLL_CON4_PLL_TPU_BYPASS, + PLL_CON0_PLL_TPU_MUX_SEL, + PLL_CON0_PLL_TPU_MUX_BUSY, + PLL_LOCKTIME_PLL_TPU_RESET_REQ_TIME, + PLL_CON1_PLL_TPU_IGNORE_REQ_SYSCLK, + PLL_CON4_PLL_TPU_DISABLE_ALL_CLOCK_STOP, + PLL_CON4_PLL_TPU_DISABLE_SDIV_CLOCK_STOP, + PLL_CON3_PLL_TPU_USE_HW_LOCK_DET, + PLL_CON3_PLL_TPU_LOCK_FAIL, + PLL_CON3_PLL_TPU_USE_LOCK_FAIL, + PLL_CON1_PLL_TPU_ENABLE_AUTOMATIC_BYPASS, + PLL_CON1_PLL_TPU_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_PLL_TPU_MANUAL_PLL_CTRL, + PLL_CON1_PLL_TPU_AUTO_PLL_CTRL, + DBG_NFO_PLL_TPU_DEBUG_INFO, + PLL_CON2_PLL_TPU_ENABLE_FILTER_AUTOMATIC_CLKGATING, + PLL_CON2_PLL_TPU_FILTER_CNT_EXPIRE_VALUE, + PLL_CON1_PLL_TPU_OVERRIDE_BY_HCH, + PLL_CON3_PLL_TPU_LOCK_EN, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_APM_FUNC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_APM_FUNCSRC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_AUR_AUR_SELECT, + CLK_CON_MUX_MUX_CLK_AUR_AUR_BUSY, + CLK_CON_MUX_MUX_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_AUR_AUR_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_AUR_AUR_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MFC_MFC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G2D_G2D_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CSIS_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CSIS_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_NOCL0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_NOCL0_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MIF_SWITCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_ITP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_ITP_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G3AA_G3AA_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MCSC_ITSC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G2D_MSCL_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HPM_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HPM_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI1_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI1_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK0_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK1_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK2_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK3_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_BO_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_BO_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_BO_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_BO_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_DEBUG_INFO, + CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, + CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, + CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CMU_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CMU_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PERIC0_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PERIC1_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MISC_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MISC_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI2_PCIE_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI2_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI2_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MIF_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MIF_NOCP_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PERIC0_IP_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PERIC1_IP_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TPU_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TPU_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI0_USBDPDBG_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PDP_VRA_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PDP_VRA_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_DPU_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_DPU_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI1_PCIE_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI0_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TOP_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_IPP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_IPP_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK4_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CMU_BOOST_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TNR_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TNR_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_NOCL2A_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_NOCL1A_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_NOCL1B_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK5_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK6_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_DNS_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_DNS_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_SELECT, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_BUSY, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_GDC_GDC0_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_SELECT, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_BUSY, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_GDC_GDC1_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MCSC_MCSC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPU_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TPU_TPU_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_SELECT, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_BUSY, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CIS_CLK7_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G3D_GLB_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G3D_GLB_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_GDC_SCSC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_SELECT, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_BUSY, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_MISC_SSS_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_MISC_SSS_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_DISP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_DISP_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_EH_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_EH_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_EH_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_EH_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_SELECT, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_BUSY, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_CMU_BOOST_OPTION1_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TOP_BOOST_OPTION1_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_PDP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_PDP_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TPU_UART_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TPU_UART_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_SELECT, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_BUSY, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G3D_SWITCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_SELECT, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_BUSY, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_G3D_NOCD_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_G3D_NOCD_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_SELECT, + CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_BUSY, + CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_AUR_AUR_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_AUR_AUR_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_AUR_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_AUR_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_SELECT, + CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_BUSY, + CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_AUR_AURCTL_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_CPUCL0_PLL_DEBUG_INFO, + CLK_CON_MUX_MUX_CPUCL0_CMUREF_SELECT, + CLK_CON_MUX_MUX_CPUCL0_CMUREF_BUSY, + CLK_CON_MUX_MUX_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CPUCL0_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CPUCL0_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CPUCL1_CMUREF_SELECT, + CLK_CON_MUX_MUX_CPUCL1_CMUREF_BUSY, + CLK_CON_MUX_MUX_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CPUCL1_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CPUCL1_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_CPUCL1_PLL_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_SELECT, + CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_BUSY, + CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_CPUCL2_PLL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_CPUCL2_PLL_DEBUG_INFO, + CLK_CON_MUX_MUX_CPUCL2_CMUREF_SELECT, + CLK_CON_MUX_MUX_CPUCL2_CMUREF_BUSY, + CLK_CON_MUX_MUX_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CPUCL2_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CPUCL2_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_EH_NOC_SELECT, + CLK_CON_MUX_MUX_CLK_EH_NOC_BUSY, + CLK_CON_MUX_MUX_CLK_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_EH_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_EH_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_G3D_STACKS_SELECT, + CLK_CON_MUX_MUX_CLK_G3D_STACKS_BUSY, + CLK_CON_MUX_MUX_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_G3D_STACKS_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_G3D_STACKS_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_SELECT, + CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_BUSY, + CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_G3D_L2_GLB_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_G3D_L2_GLB_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_G3D_TOP_SELECT, + CLK_CON_MUX_MUX_CLK_G3D_TOP_BUSY, + CLK_CON_MUX_MUX_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_G3D_TOP_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_G3D_TOP_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_SELECT, + CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_BUSY, + CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_GSACORE_CPU_HCH_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_GSACORE_CPU_HCH_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_GSA_FUNC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_SELECT, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_BUSY, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLKCMU_GSA_FUNCSRC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLKCMU_GSA_FUNCSRC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_SELECT, + CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_BUSY, + CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_HSI0_USB31DRD_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_HSI0_NOC_SELECT, + CLK_CON_MUX_MUX_CLK_HSI0_NOC_BUSY, + CLK_CON_MUX_MUX_CLK_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_HSI0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_HSI0_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_SELECT, + CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_BUSY, + CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_HSI0_USB20_REF_DEBUG_INFO, + CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, + CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, + CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_MIF_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_MIF_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_NOCL0_CMUREF_SELECT, + CLK_CON_MUX_MUX_NOCL0_CMUREF_BUSY, + CLK_CON_MUX_MUX_NOCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_NOCL0_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_NOCL0_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_SELECT, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_BUSY, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_NOCL0_NOC_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_SELECT, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_BUSY, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_NOCL0_NOC_OPTION1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_NOCL0_NOC_OPTION1_DEBUG_INFO, + CLK_CON_MUX_MUX_NOCL1A_CMUREF_SELECT, + CLK_CON_MUX_MUX_NOCL1A_CMUREF_BUSY, + CLK_CON_MUX_MUX_NOCL1A_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_NOCL1A_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_NOCL1A_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_NOCL1B_CMUREF_SELECT, + CLK_CON_MUX_MUX_NOCL1B_CMUREF_BUSY, + CLK_CON_MUX_MUX_NOCL1B_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_NOCL1B_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_NOCL1B_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_SELECT, + CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_BUSY, + CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_NOCL1B_NOC_OPTION1_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_NOCL1B_NOC_OPTION1_DEBUG_INFO, + CLK_CON_MUX_MUX_NOCL2A_CMUREF_SELECT, + CLK_CON_MUX_MUX_NOCL2A_CMUREF_BUSY, + CLK_CON_MUX_MUX_NOCL2A_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_NOCL2A_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_MUX_NOCL2A_CMUREF_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_S2D_CORE_SELECT, + CLK_CON_MUX_MUX_CLK_S2D_CORE_BUSY, + CLK_CON_MUX_MUX_CLK_S2D_CORE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_S2D_CORE_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_S2D_CORE_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_TPU_TPU_SELECT, + CLK_CON_MUX_MUX_CLK_TPU_TPU_BUSY, + CLK_CON_MUX_MUX_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_TPU_TPU_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_TPU_TPU_DEBUG_INFO, + CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_SELECT, + CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_BUSY, + CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_MUX_MUX_CLK_TPU_TPUCTL_OVERRIDE_BY_HCH, + DBG_NFO_MUX_CLK_TPU_TPUCTL_DEBUG_INFO, + PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER_BUSY, + PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_AUR_SWITCH_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_AUR_SWITCH_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER_BUSY, + PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_AUR_AURCTL_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_AUR_AURCTL_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_AUR_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_AUR_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_AUR_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_BO_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_BO_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_BO_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_BO_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_BO_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_BO_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, + PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_CPUCL0_SWITCH_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_CPUCL0_SWITCH_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_CPUCL0_DBG_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, + PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_CPUCL1_SWITCH_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_CPUCL1_SWITCH_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_CPUCL2_SWITCH_USER_BUSY, + PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_CPUCL2_SWITCH_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_CPUCL2_SWITCH_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_CSIS_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_CSIS_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_DISP_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_DISP_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_DISP_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_DNS_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_DNS_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_DNS_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_DPU_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_DPU_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_DPU_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_EH_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_EH_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_EH_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_EH_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_EH_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_EH_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER_BUSY, + PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_EH_PLL_NOCL0_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_EH_PLL_NOCL0_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G2D_G2D_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G2D_G2D_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G2D_MSCL_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G2D_MSCL_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G3AA_G3AA_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G3AA_G3AA_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G3D_SWITCH_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G3D_SWITCH_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_BUSY, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G3D_GLB_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G3D_GLB_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G3D_GLB_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_BUSY, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER_BUSY, + PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_G3D_NOCD_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_G3D_NOCD_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_BUSY, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_GDC_SCSC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_GDC_SCSC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER_BUSY, + PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_GDC_GDC0_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_GDC_GDC0_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER_BUSY, + PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_GDC_GDC1_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_GDC_GDC1_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_USB31DRD_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_DPGTC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_USPDPDBG_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_ALT_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_USB20_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI0_TCXO_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI1_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI1_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI1_PCIE_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI1_PCIE_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI2_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI2_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI2_PCIE_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI2_UFS_EMBD_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER_BUSY, + PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_HSI2_MMC_CARD_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_IPP_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_IPP_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_IPP_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_ITP_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_ITP_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_ITP_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MCSC_ITSC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MCSC_ITSC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MCSC_MCSC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MCSC_MCSC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MFC_MFC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MFC_MFC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MFC_MFC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MIF_NOCP_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MIF_NOCP_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MIF_NOCP_USER_OVERRIDE_BY_HCH, + PLL_CON0_CLKMUX_MIF_DDRPHY2X_MUX_SEL, + PLL_CON0_CLKMUX_MIF_DDRPHY2X_BUSY, + PLL_CON1_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_CLKMUX_MIF_DDRPHY2X_IGNORE_REQ_SYSCLK, + DBG_NFO_CLKMUX_MIF_DDRPHY2X_DEBUG_INFO, + PLL_CON1_CLKMUX_MIF_DDRPHY2X_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MISC_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MISC_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MISC_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_MISC_SSS_USER_BUSY, + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_MISC_SSS_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_MISC_SSS_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_NOCL0_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_NOCL0_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_NOCL1A_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_NOCL1A_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_NOCL1B_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_NOCL1B_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_NOCL2A_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_NOCL2A_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PDP_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PDP_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PDP_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PDP_VRA_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PDP_VRA_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PDP_VRA_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI6_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI3_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI4_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI5_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI14_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_I3C_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI7_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI8_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI1_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI0_UART_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC0_USI2_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI11_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI12_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI0_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_I3C_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI9_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI10_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI13_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI15_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI15_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER_BUSY, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_PERIC1_USI16_USI_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_PERIC1_USI16_USI_USER_OVERRIDE_BY_HCH, + PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_MUX_SEL, + PLL_CON0_CLKCMU_MIF_DDRPHY2X_S2D_BUSY, + PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_IGNORE_REQ_SYSCLK, + DBG_NFO_CLKCMU_MIF_DDRPHY2X_S2D_DEBUG_INFO, + PLL_CON1_CLKCMU_MIF_DDRPHY2X_S2D_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_TNR_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_TNR_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_TNR_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_TPU_NOC_USER_BUSY, + PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_TPU_NOC_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_TPU_NOC_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_TPU_TPU_USER_BUSY, + PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_TPU_TPU_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_TPU_TPU_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER_BUSY, + PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_TPU_TPUCTL_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_TPU_TPUCTL_USER_OVERRIDE_BY_HCH, + PLL_CON0_MUX_CLKCMU_TPU_UART_USER_MUX_SEL, + PLL_CON0_MUX_CLKCMU_TPU_UART_USER_BUSY, + PLL_CON1_MUX_CLKCMU_TPU_UART_USER_ENABLE_AUTOMATIC_CLKGATING, + PLL_CON1_MUX_CLKCMU_TPU_UART_USER_IGNORE_REQ_SYSCLK, + DBG_NFO_MUX_CLKCMU_TPU_UART_USER_DEBUG_INFO, + PLL_CON1_MUX_CLKCMU_TPU_UART_USER_OVERRIDE_BY_HCH, + CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AOC_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AOC_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_BUSY, + CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AOC_TRACE_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AOC_TRACE_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_BOOST_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_BOOST_BUSY, + CLK_CON_DIV_DIV_CLK_APM_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_BOOST_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_BOOST_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI_BUSY, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_USI0_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_USI0_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART_BUSY, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_USI0_UART_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_USI0_UART_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART_BUSY, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_USI1_UART_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_USI1_UART_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_BUSY, + CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_I3C_PMIC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_APM_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_APM_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_APM_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_APM_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_APM_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AUR_NOCP_DEBUG_INFO, + CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_DIVRATIO, + CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_BUSY, + CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLK_AUR_ADD_CH_CLK_OVERRIDE_BY_HCH, + DBG_NFO_CLK_AUR_ADD_CH_CLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_BUSY, + CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AUR_AURCTL_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AUR_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_BO_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_BO_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_BO_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_BO_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_BO_NOCP_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, + CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, + CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G3D_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G3D_SWITCH_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PERIC0_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_PERIC0_NOC_BUSY, + CLK_CON_DIV_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PERIC0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PERIC0_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MISC_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_MISC_NOC_BUSY, + CLK_CON_DIV_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MISC_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MISC_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI1_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI1_NOC_BUSY, + CLK_CON_DIV_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI1_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI1_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_DPU_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_DPU_NOC_BUSY, + CLK_CON_DIV_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_DPU_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_DPU_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MFC_MFC_DIVRATIO, + CLK_CON_DIV_CLKCMU_MFC_MFC_BUSY, + CLK_CON_DIV_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MFC_MFC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MFC_MFC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, + CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, + CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G2D_G2D_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G2D_G2D_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_BUSY, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI0_USB31DRD_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI0_USB31DRD_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CSIS_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_CSIS_NOC_BUSY, + CLK_CON_DIV_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CSIS_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CSIS_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PERIC1_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_PERIC1_NOC_BUSY, + CLK_CON_DIV_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PERIC1_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PERIC1_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CPUCL0_SWITCH_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_NOCL0_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_NOCL0_NOC_BUSY, + CLK_CON_DIV_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_NOCL0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_NOCL0_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_ITP_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_ITP_NOC_BUSY, + CLK_CON_DIV_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_ITP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_ITP_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G3AA_G3AA_DIVRATIO, + CLK_CON_DIV_CLKCMU_G3AA_G3AA_BUSY, + CLK_CON_DIV_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G3AA_G3AA_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G3AA_G3AA_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MCSC_ITSC_DIVRATIO, + CLK_CON_DIV_CLKCMU_MCSC_ITSC_BUSY, + CLK_CON_DIV_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MCSC_ITSC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MCSC_ITSC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G2D_MSCL_DIVRATIO, + CLK_CON_DIV_CLKCMU_G2D_MSCL_BUSY, + CLK_CON_DIV_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G2D_MSCL_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G2D_MSCL_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, + CLK_CON_DIV_CLKCMU_HPM_BUSY, + CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HPM_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HPM_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI2_PCIE_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI2_PCIE_BUSY, + CLK_CON_DIV_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI2_PCIE_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI2_PCIE_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG_DIVRATIO, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUSY, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CPUCL0_DBG_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK0_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK0_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK1_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK1_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK2_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK2_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK3_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK3_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_BO_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_BO_NOC_BUSY, + CLK_CON_DIV_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_BO_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_BO_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_BUSY, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI2_UFS_EMBD_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC_BUSY, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI0_DPGTC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI0_DPGTC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CMU_CMUREF_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MIF_NOCP_DIVRATIO, + CLK_CON_DIV_CLKCMU_MIF_NOCP_BUSY, + CLK_CON_DIV_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MIF_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MIF_NOCP_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PERIC0_IP_DIVRATIO, + CLK_CON_DIV_CLKCMU_PERIC0_IP_BUSY, + CLK_CON_DIV_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PERIC0_IP_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PERIC0_IP_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PERIC1_IP_DIVRATIO, + CLK_CON_DIV_CLKCMU_PERIC1_IP_BUSY, + CLK_CON_DIV_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PERIC1_IP_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PERIC1_IP_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_TPU_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_TPU_NOC_BUSY, + CLK_CON_DIV_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_TPU_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_TPU_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PDP_VRA_DIVRATIO, + CLK_CON_DIV_CLKCMU_PDP_VRA_BUSY, + CLK_CON_DIV_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PDP_VRA_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PDP_VRA_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CPUCL1_SWITCH_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI1_PCIE_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI1_PCIE_BUSY, + CLK_CON_DIV_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI1_PCIE_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI1_PCIE_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI0_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI0_NOC_BUSY, + CLK_CON_DIV_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI0_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI0_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_IPP_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_IPP_NOC_BUSY, + CLK_CON_DIV_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_IPP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_IPP_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK4_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK4_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK4_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK4_DEBUG_INFO, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_DIVRATIO, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_BUSY, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLKCMU_CMU_BOOST_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_TNR_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_TNR_NOC_BUSY, + CLK_CON_DIV_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_TNR_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_TNR_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_NOCL2A_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_NOCL2A_NOC_BUSY, + CLK_CON_DIV_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_NOCL2A_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_NOCL2A_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_NOCL1A_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_NOCL1A_NOC_BUSY, + CLK_CON_DIV_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_NOCL1A_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_NOCL1A_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC_BUSY, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_NOCL1B_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_NOCL1B_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK5_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK5_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK5_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK5_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK6_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK6_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK6_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK6_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CIS_CLK7_DIVRATIO, + CLK_CON_DIV_CLKCMU_CIS_CLK7_BUSY, + CLK_CON_DIV_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CIS_CLK7_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CIS_CLK7_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_DNS_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_DNS_NOC_BUSY, + CLK_CON_DIV_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_DNS_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_DNS_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_GDC_GDC0_DIVRATIO, + CLK_CON_DIV_CLKCMU_GDC_GDC0_BUSY, + CLK_CON_DIV_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_GDC_GDC0_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_GDC_GDC0_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_GDC_GDC1_DIVRATIO, + CLK_CON_DIV_CLKCMU_GDC_GDC1_BUSY, + CLK_CON_DIV_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_GDC_GDC1_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_GDC_GDC1_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MCSC_MCSC_DIVRATIO, + CLK_CON_DIV_CLKCMU_MCSC_MCSC_BUSY, + CLK_CON_DIV_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MCSC_MCSC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MCSC_MCSC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_TPU_TPU_DIVRATIO, + CLK_CON_DIV_CLKCMU_TPU_TPU_BUSY, + CLK_CON_DIV_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_TPU_TPU_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_TPU_TPU_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI2_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI2_NOC_BUSY, + CLK_CON_DIV_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI2_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI2_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_DIVRATIO, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_BUSY, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_HSI2_MMC_CARD_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G3D_GLB_DIVRATIO, + CLK_CON_DIV_CLKCMU_G3D_GLB_BUSY, + CLK_CON_DIV_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G3D_GLB_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G3D_GLB_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_DIVRATIO, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_BUSY, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_CPUCL2_SWITCH_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_GDC_SCSC_DIVRATIO, + CLK_CON_DIV_CLKCMU_GDC_SCSC_BUSY, + CLK_CON_DIV_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_GDC_SCSC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_GDC_SCSC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_MISC_SSS_DIVRATIO, + CLK_CON_DIV_CLKCMU_MISC_SSS_BUSY, + CLK_CON_DIV_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_MISC_SSS_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_MISC_SSS_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_DISP_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_DISP_NOC_BUSY, + CLK_CON_DIV_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_DISP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_DISP_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_EH_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_EH_NOC_BUSY, + CLK_CON_DIV_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_EH_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_EH_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_PDP_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_PDP_NOC_BUSY, + CLK_CON_DIV_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_PDP_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_PDP_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_TPU_UART_DIVRATIO, + CLK_CON_DIV_CLKCMU_TPU_UART_BUSY, + CLK_CON_DIV_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_TPU_UART_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_TPU_UART_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL_DIVRATIO, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL_BUSY, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_TPU_TPUCTL_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_TPU_TPUCTL_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED0_DIV5_DIVRATIO, + CLK_CON_DIV_PLL_SHARED0_DIV5_BUSY, + CLK_CON_DIV_PLL_SHARED0_DIV5_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED0_DIV5_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED0_DIV5_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_G3D_NOCD_DIVRATIO, + CLK_CON_DIV_CLKCMU_G3D_NOCD_BUSY, + CLK_CON_DIV_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_G3D_NOCD_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_G3D_NOCD_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_AUR_AUR_DIVRATIO, + CLK_CON_DIV_CLKCMU_AUR_AUR_BUSY, + CLK_CON_DIV_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_AUR_AUR_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_AUR_AUR_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_AUR_NOC_DIVRATIO, + CLK_CON_DIV_CLKCMU_AUR_NOC_BUSY, + CLK_CON_DIV_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_AUR_NOC_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_AUR_NOC_DEBUG_INFO, + CLK_CON_DIV_CLKCMU_AUR_AURCTL_DIVRATIO, + CLK_CON_DIV_CLKCMU_AUR_AURCTL_BUSY, + CLK_CON_DIV_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_AUR_AURCTL_OVERRIDE_BY_HCH, + DBG_NFO_CLKCMU_AUR_AURCTL_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED0_DIV2_DIVRATIO, + CLK_CON_DIV_PLL_SHARED0_DIV2_BUSY, + CLK_CON_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED0_DIV2_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED0_DIV2_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED0_DIV4_DIVRATIO, + CLK_CON_DIV_PLL_SHARED0_DIV4_BUSY, + CLK_CON_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED0_DIV4_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED0_DIV4_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED0_DIV3_DIVRATIO, + CLK_CON_DIV_PLL_SHARED0_DIV3_BUSY, + CLK_CON_DIV_PLL_SHARED0_DIV3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED0_DIV3_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED0_DIV3_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED1_DIV2_DIVRATIO, + CLK_CON_DIV_PLL_SHARED1_DIV2_BUSY, + CLK_CON_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED1_DIV2_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED1_DIV2_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED1_DIV4_DIVRATIO, + CLK_CON_DIV_PLL_SHARED1_DIV4_BUSY, + CLK_CON_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED1_DIV4_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED1_DIV4_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED1_DIV3_DIVRATIO, + CLK_CON_DIV_PLL_SHARED1_DIV3_BUSY, + CLK_CON_DIV_PLL_SHARED1_DIV3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED1_DIV3_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED1_DIV3_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED2_DIV2_DIVRATIO, + CLK_CON_DIV_PLL_SHARED2_DIV2_BUSY, + CLK_CON_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED2_DIV2_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED2_DIV2_DEBUG_INFO, + CLK_CON_DIV_PLL_SHARED3_DIV2_DIVRATIO, + CLK_CON_DIV_PLL_SHARED3_DIV2_BUSY, + CLK_CON_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_PLL_SHARED3_DIV2_OVERRIDE_BY_HCH, + DBG_NFO_PLL_SHARED3_DIV2_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_CMUREF_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CLUSTER0_ACLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_BUSY, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CLUSTER0_PCLKDBG_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_BUSY, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CLUSTER0_PERIPHCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_PCLKDBG_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_PCLKDBG_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_PCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_ATCLK_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_ATCLK_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_DBG_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_DBG_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_BUSY, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CLUSTER0_ATCLK_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_PCLK_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL1_CMUREF_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL2_CMUREF_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL2_CMUREF_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CSIS_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_CSIS_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_CSIS_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CSIS_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CSIS_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_DISP_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_DISP_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_DISP_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_DISP_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_DISP_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_DNS_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_DNS_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_DNS_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_DNS_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_DNS_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_DPU_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_DPU_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_DPU_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_DPU_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_DPU_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_EH_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_EH_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_EH_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_EH_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_EH_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_EH_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_EH_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G2D_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_G2D_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_G2D_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G2D_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G2D_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3AA_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_G3AA_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_G3AA_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3AA_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3AA_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3D_NOCP_DEBUG_INFO, + CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_DIVRATIO, + CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_BUSY, + CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLK_G3D_ADD_CH_CLK_OVERRIDE_BY_HCH, + DBG_NFO_CLK_G3D_ADD_CH_CLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3D_TOP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_G3D_TOP_BUSY, + CLK_CON_DIV_DIV_CLK_G3D_TOP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3D_TOP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3D_TOP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3D_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GDC_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GDC_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_GDC_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GDC_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GDC_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_NOCD_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_NOCD_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_FPS_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_SPI_FPS_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_SPI_GSC_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_SPI_GSC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_UART_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_UART_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_UART_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_UART_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOC_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_NOC_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_NOC_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_NOC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_BUSY, + CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACORE_CPU_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACORE_CPU_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACTRL_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_BUSY, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCD_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACTRL_NOCD_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_GSACTRL_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_GSACTRL_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_BUSY, + CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI0_USB31DRD_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI0_USB_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI0_USB_BUSY, + CLK_CON_DIV_DIV_CLK_HSI0_USB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI0_USB_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI0_USB_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI0_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI1_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI1_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_HSI1_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI1_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI1_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI1_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI1_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI2_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI2_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_HSI2_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI2_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI2_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_HSI2_NOC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_IPP_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_IPP_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_IPP_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_IPP_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_IPP_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_ITP_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_ITP_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_ITP_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_ITP_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_ITP_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MCSC_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MCSC_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_MCSC_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MCSC_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MCSC_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MFC_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MFC_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_MFC_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MFC_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MFC_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MIF_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MIF_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_BUSY, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_DBG_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MIF_NOCD_DBG_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MISC_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MISC_GIC_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MISC_GIC_BUSY, + CLK_CON_DIV_DIV_CLK_MISC_GIC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MISC_GIC_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MISC_GIC_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_BUSY, + CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MISC_GIC_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MISC_GIC_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MISC_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_MISC_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL0_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_SLC_DCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_SLC_DCLK_BUSY, + CLK_CON_DIV_DIV_CLK_SLC_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_SLC_DCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_SLC_DCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_SLC1_DCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_SLC1_DCLK_BUSY, + CLK_CON_DIV_DIV_CLK_SLC1_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_SLC1_DCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_SLC1_DCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_SLC2_DCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_SLC2_DCLK_BUSY, + CLK_CON_DIV_DIV_CLK_SLC2_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_SLC2_DCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_SLC2_DCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_SLC3_DCLK_DIVRATIO, + CLK_CON_DIV_DIV_CLK_SLC3_DCLK_BUSY, + CLK_CON_DIV_DIV_CLK_SLC3_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_SLC3_DCLK_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_SLC3_DCLK_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL0_NOCD_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL0_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1A_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1A_NOCD_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1A_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1B_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1B_NOCD_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL1B_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL2A_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL2A_NOCD_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_NOCL2A_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PDP_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PDP_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_PDP_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PDP_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PDP_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI6_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI3_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI4_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI5_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI14_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_I3C_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_I3C_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI7_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI8_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI1_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI0_UART_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_USI2_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC0_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI11_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_I3C_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_I3C_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI12_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI0_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI9_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI10_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI13_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI15_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_DIVRATIO, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_BUSY, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_PERIC1_USI16_USI_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_BUSY, + CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_S2D_CORE_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_S2D_CORE_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TNR_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_TNR_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_TNR_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TNR_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TNR_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_DIVRATIO, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_BUSY, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TPU_NOCP_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_DIVRATIO, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_BUSY, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TPU_TPUCTL_DBG_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_DIVRATIO, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_BUSY, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TPU_NOCP_LH_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_AUR_AUR_BUSY, + CLK_CON_DIV_DIV_CLK_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_AUR_AUR_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_AUR_AUR_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL0_CPU_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL1_CPU_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_BUSY, + CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_CPUCL2_CPU_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_CPUCL2_CPU_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3D_STACKS_BUSY, + CLK_CON_DIV_DIV_CLK_G3D_STACKS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3D_STACKS_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3D_STACKS_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_BUSY, + CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_G3D_L2_GLB_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_G3D_L2_GLB_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TPU_TPU_BUSY, + CLK_CON_DIV_DIV_CLK_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TPU_TPU_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TPU_TPU_DEBUG_INFO, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_BUSY, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_OVERRIDE_BY_HCH, + DBG_NFO_DIV_CLK_TPU_TPUCTL_DEBUG_INFO, + CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_RSTNSYNC_CLK_AOC_TRACE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_APM_FUNC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_CG_VAL, + CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_MANUAL, + CLK_CON_GAT_CLK_NOCL1B_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_CG_VAL, + CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_MANUAL, + CLK_CON_GAT_CLK_NOCL0_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_CG_VAL, + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_MANUAL, + CLK_CON_GAT_CLK_CMU_BOOST_OPTION1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_I3C_PMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_GREBE_DBGCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_AURCTL_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_RSTNSYNC_CLK_AUR_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_RSTNSYNC_CLK_BO_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, + CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, + CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_DPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MISC_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CSIS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_ITP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_BO_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_BO_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_BO_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MIF_NOCP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PDP_VRA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI0_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_IPP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TNR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL2A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL1A_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_NOCL1B_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_CPUCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_CPUCL1_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_NOCL1B_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_NOCL2A_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_NOCL1A_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_NOCL0_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_NOCL0_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_NOCL0_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_MIF_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_MIF_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_MIF_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_DNS_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPU_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_GLB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_CG_VAL, + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_MANUAL, + CLK_CON_GAT_CLKCMU_CPUCL2_BOOST_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_MISC_SSS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_DISP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_EH_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_EH_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_EH_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_PDP_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TPU_UART_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_UART_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_UART_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_G3D_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_AUR_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_NOC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_CG_VAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_MANUAL, + CLK_CON_GAT_GATE_CLKCMU_AUR_AURCTL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PERIPHCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_RSTNSYNC_CLK_CSIS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_RSTNSYNC_CLK_DISP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_RSTNSYNC_CLK_DNS_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_MANUAL, + CLK_CON_GAT_GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_RSTNSYNC_CLK_EH_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_NOCD_MSCL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_G3AA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_RSTNSYNC_CLK_G3AA_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_CG_VAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_MANUAL, + CLK_CON_GAT_CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_SCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_RSTNSYNC_CLK_GDC_GDC1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_GSACORE_CG_VAL, + CLK_CON_GAT_CLK_GSACORE_MANUAL, + CLK_CON_GAT_CLK_GSACORE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_FPS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_SPI_GSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_REFCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_GSACORE_CPU_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_CA32_CPUPORESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_PORRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_HRESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_RSTNSYNC_CLK_SSS_ARESETN_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLK_GSA_FUNC_CG_VAL, + CLK_CON_GAT_GATE_CLK_GSA_FUNC_MANUAL, + CLK_CON_GAT_GATE_CLK_GSA_FUNC_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_CG_VAL, + CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_MANUAL, + CLK_CON_GAT_GATE_CLK_GSACTRL2CORE_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_RSTNSYNC_CLK_GSACTRL_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_HSI0_ALT_CG_VAL, + CLK_CON_GAT_CLK_HSI0_ALT_MANUAL, + CLK_CON_GAT_CLK_HSI0_ALT_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI1_UID_RSTNSYNC_CLK_HSI1_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_NOC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_RSTNSYNC_CLK_IPP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_RSTNSYNC_CLK_ITP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_RSTNSYNC_CLK_MCSC_MCSC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_NOCD_DBG_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_ACLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC1_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC2_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_RSTNSYNC_CLK_SLC3_DCLK_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_CLK_NOCL0_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL0_UID_RSTNSYNC_SR_CLK_NOCL0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_CLK_NOCL1A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1A_UID_RSTNSYNC_SR_CLK_NOCL1A_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_CLK_NOCL1B_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL1B_UID_RSTNSYNC_SR_CLK_NOCL1B_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_CG_VAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_MANUAL, + CLK_CON_GAT_GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_RSTNSYNC_CLK_NOCL2A_NOCD_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PDP_UID_RSTNSYNC_CLK_PDP_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI15_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_SCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_RSTNSYNC_CLK_TNR_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_DBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_OSCCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_GOUT_BLK_TPU_UID_RSTNSYNC_CLK_TPU_DD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_TPUCTL_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_NOCP_LH_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_AXI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_CG_VAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_MANUAL, + CLK_CON_GAT_CLK_BLK_TPU_UID_RSTNSYNC_CLK_TPU_APB_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_DIV_CLK_MIF_NOCD_ENABLE_AUTOMATIC_CLKGATING, + CLK_CON_DIV_CLK_MIF_NOCD_S2D_ENABLE_AUTOMATIC_CLKGATING, + QCH_CON_AOC_CMU_AOC_QCH_ENABLE, + QCH_CON_AOC_CMU_AOC_QCH_CLOCK_REQ, + QCH_CON_AOC_CMU_AOC_QCH_EXPIRE_VAL, + QCH_CON_AOC_CMU_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_AOC_SYSCTRL_APB_QCH_ENABLE, + QCH_CON_AOC_SYSCTRL_APB_QCH_CLOCK_REQ, + QCH_CON_AOC_SYSCTRL_APB_QCH_EXPIRE_VAL, + QCH_CON_AOC_SYSCTRL_APB_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BAAW_AOC_QCH_ENABLE, + QCH_CON_BAAW_AOC_QCH_CLOCK_REQ, + QCH_CON_BAAW_AOC_QCH_EXPIRE_VAL, + QCH_CON_BAAW_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_AOC_QCH_ENABLE, + QCH_CON_D_TZPC_AOC_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_AOC_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_AOC_QCH_ENABLE, + QCH_CON_GPC_AOC_QCH_CLOCK_REQ, + QCH_CON_GPC_AOC_QCH_EXPIRE_VAL, + QCH_CON_GPC_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AOC_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_AOC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LP0_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LP1_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_AOC_QCH_ENABLE, + QCH_CON_PPMU_AOC_QCH_CLOCK_REQ, + QCH_CON_PPMU_AOC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_USB_QCH_ENABLE, + QCH_CON_PPMU_USB_QCH_CLOCK_REQ, + QCH_CON_PPMU_USB_QCH_EXPIRE_VAL, + QCH_CON_PPMU_USB_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LG_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LG_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LG_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LG_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_AOC_QCH_ENABLE, + QCH_CON_SSMT_AOC_QCH_CLOCK_REQ, + QCH_CON_SSMT_AOC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_AOC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_AOC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_AOC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_AOC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_AOC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_AOC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_AOC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_AOC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_AOC_QCH_ENABLE, + QCH_CON_SYSREG_AOC_QCH_CLOCK_REQ, + QCH_CON_SYSREG_AOC_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_AOC_QCH_ENABLE, + QCH_CON_UASC_AOC_QCH_CLOCK_REQ, + QCH_CON_UASC_AOC_QCH_EXPIRE_VAL, + QCH_CON_UASC_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, + QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, + QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_ENABLE, + QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_CLOCK_REQ, + QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_ENABLE, + QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_CLOCK_REQ, + QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_EXPIRE_VAL, + QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_ENABLE, + QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_CLOCK_REQ, + QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_EXPIRE_VAL, + QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_ENABLE, + QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_CLOCK_REQ, + QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_EXPIRE_VAL, + QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, + QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, + QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_RTC_QCH_ENABLE, + QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, + QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, + QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_TRTC_QCH_ENABLE, + QCH_CON_APBIF_TRTC_QCH_CLOCK_REQ, + QCH_CON_APBIF_TRTC_QCH_EXPIRE_VAL, + QCH_CON_APBIF_TRTC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APM_CMU_APM_QCH_ENABLE, + QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, + QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, + QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APM_I3C_PMIC_QCH_P_ENABLE, + QCH_CON_APM_I3C_PMIC_QCH_P_CLOCK_REQ, + QCH_CON_APM_I3C_PMIC_QCH_P_EXPIRE_VAL, + QCH_CON_APM_I3C_PMIC_QCH_P_IGNORE_FORCE_PM_EN, + DMYQCH_CON_APM_I3C_PMIC_QCH_S_ENABLE, + DMYQCH_CON_APM_I3C_PMIC_QCH_S_CLOCK_REQ, + DMYQCH_CON_APM_I3C_PMIC_QCH_S_IGNORE_FORCE_PM_EN, + QCH_CON_APM_USI0_UART_QCH_ENABLE, + QCH_CON_APM_USI0_UART_QCH_CLOCK_REQ, + QCH_CON_APM_USI0_UART_QCH_EXPIRE_VAL, + QCH_CON_APM_USI0_UART_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APM_USI0_USI_QCH_ENABLE, + QCH_CON_APM_USI0_USI_QCH_CLOCK_REQ, + QCH_CON_APM_USI0_USI_QCH_EXPIRE_VAL, + QCH_CON_APM_USI0_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APM_USI1_UART_QCH_ENABLE, + QCH_CON_APM_USI1_UART_QCH_CLOCK_REQ, + QCH_CON_APM_USI1_UART_QCH_EXPIRE_VAL, + QCH_CON_APM_USI1_UART_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_APM_QCH_ENABLE, + QCH_CON_D_TZPC_APM_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_APM_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_APM_QCH_ENABLE, + QCH_CON_GPC_APM_QCH_CLOCK_REQ, + QCH_CON_GPC_APM_QCH_EXPIRE_VAL, + QCH_CON_GPC_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, + QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, + QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, + QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN, + QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, + QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, + QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, + QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN, + QCH_CON_INTMEM_QCH_ENABLE, + QCH_CON_INTMEM_QCH_CLOCK_REQ, + QCH_CON_INTMEM_QCH_EXPIRE_VAL, + QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IG_SWD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IG_SWD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IG_SWD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IG_SWD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_APM_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_APM_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_APM_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_AOC_QCH_ENABLE, + QCH_CON_MAILBOX_APM_AOC_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_AOC_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, + QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_AUR_QCH_ENABLE, + QCH_CON_MAILBOX_APM_AUR_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_AUR_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_GSA_QCH_ENABLE, + QCH_CON_MAILBOX_APM_GSA_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_GSA_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_SWD_QCH_ENABLE, + QCH_CON_MAILBOX_APM_SWD_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_SWD_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_SWD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_APM_TPU_QCH_ENABLE, + QCH_CON_MAILBOX_APM_TPU_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_APM_TPU_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_APM_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AOCA32_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AOCA32_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AOCA32_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AOCA32_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AOCF1_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AOCF1_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AOCF1_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AOCF1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AOCP6_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AOCP6_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AOCP6_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AOCP6_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AUR0_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AUR0_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AUR0_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AUR0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AUR1_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AUR1_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AUR1_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AUR1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AUR2_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AUR2_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AUR2_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AUR2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_AUR3_QCH_ENABLE, + QCH_CON_MAILBOX_AP_AUR3_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_AUR3_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_AUR3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, + QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PMU_INTR_GEN_QCH_ENABLE, + QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, + QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, + QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ROM_CRC32_HOST_QCH_ENABLE, + QCH_CON_ROM_CRC32_HOST_QCH_CLOCK_REQ, + QCH_CON_ROM_CRC32_HOST_QCH_EXPIRE_VAL, + QCH_CON_ROM_CRC32_HOST_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D_APM_QCH_ENABLE, + QCH_CON_SSMT_D_APM_QCH_CLOCK_REQ, + QCH_CON_SSMT_D_APM_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_LG_DBGCORE_QCH_ENABLE, + QCH_CON_SSMT_LG_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_SSMT_LG_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_SSMT_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SS_DBGCORE_QCH_GREBE_ENABLE, + QCH_CON_SS_DBGCORE_QCH_GREBE_CLOCK_REQ, + QCH_CON_SS_DBGCORE_QCH_GREBE_EXPIRE_VAL, + QCH_CON_SS_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN, + QCH_CON_SS_DBGCORE_QCH_DBG_ENABLE, + QCH_CON_SS_DBGCORE_QCH_DBG_CLOCK_REQ, + QCH_CON_SS_DBGCORE_QCH_DBG_EXPIRE_VAL, + QCH_CON_SS_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D_APM_QCH_ENABLE, + QCH_CON_SYSMMU_D_APM_QCH_CLOCK_REQ, + QCH_CON_SYSMMU_D_APM_QCH_EXPIRE_VAL, + QCH_CON_SYSMMU_D_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_APM_QCH_ENABLE, + QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, + QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_APM_QCH_ENABLE, + QCH_CON_UASC_APM_QCH_CLOCK_REQ, + QCH_CON_UASC_APM_QCH_EXPIRE_VAL, + QCH_CON_UASC_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_DBGCORE_QCH_ENABLE, + QCH_CON_UASC_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_UASC_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_UASC_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_IG_SWD_QCH_ENABLE, + QCH_CON_UASC_IG_SWD_QCH_CLOCK_REQ, + QCH_CON_UASC_IG_SWD_QCH_EXPIRE_VAL, + QCH_CON_UASC_IG_SWD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_LP0_AOC_QCH_ENABLE, + QCH_CON_UASC_LP0_AOC_QCH_CLOCK_REQ, + QCH_CON_UASC_LP0_AOC_QCH_EXPIRE_VAL, + QCH_CON_UASC_LP0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_P_ALIVE_QCH_ENABLE, + QCH_CON_UASC_P_ALIVE_QCH_CLOCK_REQ, + QCH_CON_UASC_P_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_UASC_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_WDT_APM_QCH_ENABLE, + QCH_CON_WDT_APM_QCH_CLOCK_REQ, + QCH_CON_WDT_APM_QCH_EXPIRE_VAL, + QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ADD_APBIF_AUR_QCH_ENABLE, + QCH_CON_ADD_APBIF_AUR_QCH_CLOCK_REQ, + QCH_CON_ADD_APBIF_AUR_QCH_EXPIRE_VAL, + QCH_CON_ADD_APBIF_AUR_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_ADD_AUR_QCH_ENABLE, + DMYQCH_CON_ADD_AUR_QCH_CLOCK_REQ, + DMYQCH_CON_ADD_AUR_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_AUR_QCH_ENABLE, + DMYQCH_CON_AUR_QCH_CLOCK_REQ, + DMYQCH_CON_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_AUR_CMU_AUR_QCH_ENABLE, + QCH_CON_AUR_CMU_AUR_QCH_CLOCK_REQ, + QCH_CON_AUR_CMU_AUR_QCH_EXPIRE_VAL, + QCH_CON_AUR_CMU_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BAAW_AUR_QCH_ENABLE, + QCH_CON_BAAW_AUR_QCH_CLOCK_REQ, + QCH_CON_BAAW_AUR_QCH_EXPIRE_VAL, + QCH_CON_BAAW_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_AUR_QCH_ENABLE, + QCH_CON_D_TZPC_AUR_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_AUR_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_AUR_QCH_ENABLE, + QCH_CON_GPC_AUR_QCH_CLOCK_REQ, + QCH_CON_GPC_AUR_QCH_EXPIRE_VAL, + QCH_CON_GPC_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_AUR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_AUR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_AUR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_AUR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_AUR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_AUR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_AUR_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_AUR_QCH_ENABLE, + QCH_CON_PPMU_D0_AUR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_AUR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_AUR_QCH_ENABLE, + QCH_CON_PPMU_D1_AUR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_AUR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_AUR_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_AUR_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_AUR_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_AUR_QCH_ENABLE, + QCH_CON_SSMT_D0_AUR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_AUR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_AUR_QCH_ENABLE, + QCH_CON_SSMT_D1_AUR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_AUR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_AUR_QCH_ENABLE, + QCH_CON_SYSREG_AUR_QCH_CLOCK_REQ, + QCH_CON_SYSREG_AUR_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_AUR_QCH_ENABLE, + QCH_CON_UASC_AUR_QCH_CLOCK_REQ, + QCH_CON_UASC_AUR_QCH_EXPIRE_VAL, + QCH_CON_UASC_AUR_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_BO_QCH_ENABLE, + DMYQCH_CON_BO_QCH_CLOCK_REQ, + DMYQCH_CON_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BO_CMU_BO_QCH_ENABLE, + QCH_CON_BO_CMU_BO_QCH_CLOCK_REQ, + QCH_CON_BO_CMU_BO_QCH_EXPIRE_VAL, + QCH_CON_BO_CMU_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_BO_QCH_ENABLE, + QCH_CON_D_TZPC_BO_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_BO_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_BO_QCH_ENABLE, + QCH_CON_GPC_BO_QCH_CLOCK_REQ, + QCH_CON_GPC_BO_QCH_EXPIRE_VAL, + QCH_CON_GPC_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_BO_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_BO_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_BO_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_BO_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_BO_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_BO_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_BO_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_BO_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_BO_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_BO_QCH_ENABLE, + QCH_CON_PPMU_BO_QCH_CLOCK_REQ, + QCH_CON_PPMU_BO_QCH_EXPIRE_VAL, + QCH_CON_PPMU_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_BO_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_BO_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_BO_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_BO_QCH_ENABLE, + QCH_CON_SSMT_BO_QCH_CLOCK_REQ, + QCH_CON_SSMT_BO_QCH_EXPIRE_VAL, + QCH_CON_SSMT_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_BO_QCH_S1_ENABLE, + QCH_CON_SYSMMU_BO_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_BO_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_BO_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_BO_QCH_S2_ENABLE, + QCH_CON_SYSMMU_BO_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_BO_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_BO_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_BO_QCH_ENABLE, + QCH_CON_SYSREG_BO_QCH_CLOCK_REQ, + QCH_CON_SYSREG_BO_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_BO_QCH_ENABLE, + QCH_CON_UASC_BO_QCH_CLOCK_REQ, + QCH_CON_UASC_BO_QCH_EXPIRE_VAL, + QCH_CON_UASC_BO_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_TOP_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_TOP_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_TOP_CMUREF_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_ENABLE, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_CLOCK_REQ, + DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7_IGNORE_FORCE_PM_EN, + DMYQCH_CON_OTP_QCH_ENABLE, + DMYQCH_CON_OTP_QCH_CLOCK_REQ, + DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, + DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, + DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BPS_CPUCL0_QCH_ENABLE, + QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_SCLK_ENABLE, + QCH_CON_CLUSTER0_QCH_SCLK_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_SCLK_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_ATCLK_ENABLE, + QCH_CON_CLUSTER0_QCH_ATCLK_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_ATCLK_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_ATCLK_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_GIC_ENABLE, + QCH_CON_CLUSTER0_QCH_GIC_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_GIC_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_GIC_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_PCLK_ENABLE, + QCH_CON_CLUSTER0_QCH_PCLK_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_PCLK_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_ENABLE, + DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_CLOCK_REQ, + DMYQCH_CON_CLUSTER0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_DBG_PD_ENABLE, + QCH_CON_CLUSTER0_QCH_DBG_PD_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_DBG_PD_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_DBG_PD_IGNORE_FORCE_PM_EN, + QCH_CON_CLUSTER0_QCH_PDBGCLK_ENABLE, + QCH_CON_CLUSTER0_QCH_PDBGCLK_CLOCK_REQ, + QCH_CON_CLUSTER0_QCH_PDBGCLK_EXPIRE_VAL, + QCH_CON_CLUSTER0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, + QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, + QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, + QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, + QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CSSYS_QCH_ENABLE, + QCH_CON_CSSYS_QCH_CLOCK_REQ, + QCH_CON_CSSYS_QCH_EXPIRE_VAL, + QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, + QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_CPUCL0_QCH_ENABLE, + QCH_CON_GPC_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_GPC_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_GPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_HPM_APBIF_CPUCL0_QCH_ENABLE, + QCH_CON_HPM_APBIF_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_HPM_APBIF_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_HPM_APBIF_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACE_SI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACE_SI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AOC_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_BDU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_BDU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_BDU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_BDU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_SLC_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_SLC_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_SLC_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_SLC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT6_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_IT7_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_BDU_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_SLC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IG_HSI0_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IG_HSI0_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IG_HSI0_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IG_STM_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IG_STM_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IG_STM_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IG_STM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_G_CSSYS_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IG_CSSYS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IG_HSI0_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IG_HSI0_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IG_HSI0_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IG_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IG_STM_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IG_STM_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IG_STM_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IG_STM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_DBGCORE_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_CPUCL0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LG_DBGCORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_CPUCL0_QCH_ENABLE, + QCH_CON_SSMT_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_SSMT_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_S2_CPUCL0_QCH_ENABLE, + QCH_CON_SYSMMU_S2_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_SYSMMU_S2_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_SYSMMU_S2_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, + QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, + QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, + QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, + QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CPUCL1_QCH_MID_ENABLE, + DMYQCH_CON_CPUCL1_QCH_MID_CLOCK_REQ, + DMYQCH_CON_CPUCL1_QCH_MID_IGNORE_FORCE_PM_EN, + QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, + QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, + QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, + QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, + QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, + QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, + QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CPUCL2_QCH_BIG_ENABLE, + DMYQCH_CON_CPUCL2_QCH_BIG_CLOCK_REQ, + DMYQCH_CON_CPUCL2_QCH_BIG_IGNORE_FORCE_PM_EN, + QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, + QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, + QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, + QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CSISX8_QCH_C2_CSIS_ENABLE, + QCH_CON_CSISX8_QCH_C2_CSIS_CLOCK_REQ, + QCH_CON_CSISX8_QCH_C2_CSIS_EXPIRE_VAL, + QCH_CON_CSISX8_QCH_C2_CSIS_IGNORE_FORCE_PM_EN, + QCH_CON_CSISX8_QCH_CSIS_DMA_ENABLE, + QCH_CON_CSISX8_QCH_CSIS_DMA_CLOCK_REQ, + QCH_CON_CSISX8_QCH_CSIS_DMA_EXPIRE_VAL, + QCH_CON_CSISX8_QCH_CSIS_DMA_IGNORE_FORCE_PM_EN, + QCH_CON_CSISX8_QCH_EBUF_ENABLE, + QCH_CON_CSISX8_QCH_EBUF_CLOCK_REQ, + QCH_CON_CSISX8_QCH_EBUF_EXPIRE_VAL, + QCH_CON_CSISX8_QCH_EBUF_IGNORE_FORCE_PM_EN, + QCH_CON_CSIS_CMU_CSIS_QCH_ENABLE, + QCH_CON_CSIS_CMU_CSIS_QCH_CLOCK_REQ, + QCH_CON_CSIS_CMU_CSIS_QCH_EXPIRE_VAL, + QCH_CON_CSIS_CMU_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_CSIS_QCH_ENABLE, + QCH_CON_D_TZPC_CSIS_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_CSIS_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_CSIS_QCH_ENABLE, + QCH_CON_GPC_CSIS_QCH_CLOCK_REQ, + QCH_CON_GPC_CSIS_QCH_EXPIRE_VAL, + QCH_CON_GPC_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6_IGNORE_FORCE_PM_EN, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_ENABLE, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_CLOCK_REQ, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_EXPIRE_VAL, + QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_QCH_ENABLE, + QCH_CON_PPMU_D0_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_QCH_ENABLE, + QCH_CON_PPMU_D1_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_CSIS_DMA0_QCH_ENABLE, + QCH_CON_QE_CSIS_DMA0_QCH_CLOCK_REQ, + QCH_CON_QE_CSIS_DMA0_QCH_EXPIRE_VAL, + QCH_CON_QE_CSIS_DMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_CSIS_DMA1_QCH_ENABLE, + QCH_CON_QE_CSIS_DMA1_QCH_CLOCK_REQ, + QCH_CON_QE_CSIS_DMA1_QCH_EXPIRE_VAL, + QCH_CON_QE_CSIS_DMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_CSIS_DMA2_QCH_ENABLE, + QCH_CON_QE_CSIS_DMA2_QCH_CLOCK_REQ, + QCH_CON_QE_CSIS_DMA2_QCH_EXPIRE_VAL, + QCH_CON_QE_CSIS_DMA2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_CSIS_DMA3_QCH_ENABLE, + QCH_CON_QE_CSIS_DMA3_QCH_CLOCK_REQ, + QCH_CON_QE_CSIS_DMA3_QCH_EXPIRE_VAL, + QCH_CON_QE_CSIS_DMA3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_STRP0_QCH_ENABLE, + QCH_CON_QE_STRP0_QCH_CLOCK_REQ, + QCH_CON_QE_STRP0_QCH_EXPIRE_VAL, + QCH_CON_QE_STRP0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_STRP1_QCH_ENABLE, + QCH_CON_QE_STRP1_QCH_CLOCK_REQ, + QCH_CON_QE_STRP1_QCH_EXPIRE_VAL, + QCH_CON_QE_STRP1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_STRP2_QCH_ENABLE, + QCH_CON_QE_STRP2_QCH_CLOCK_REQ, + QCH_CON_QE_STRP2_QCH_EXPIRE_VAL, + QCH_CON_QE_STRP2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ZSL0_QCH_ENABLE, + QCH_CON_QE_ZSL0_QCH_CLOCK_REQ, + QCH_CON_QE_ZSL0_QCH_EXPIRE_VAL, + QCH_CON_QE_ZSL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ZSL1_QCH_ENABLE, + QCH_CON_QE_ZSL1_QCH_CLOCK_REQ, + QCH_CON_QE_ZSL1_QCH_EXPIRE_VAL, + QCH_CON_QE_ZSL1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ZSL2_QCH_ENABLE, + QCH_CON_QE_ZSL2_QCH_CLOCK_REQ, + QCH_CON_QE_ZSL2_QCH_EXPIRE_VAL, + QCH_CON_QE_ZSL2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_CSIS_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_CSIS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_CSIS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_QCH_ENABLE, + QCH_CON_SSMT_D0_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_QCH_ENABLE, + QCH_CON_SSMT_D1_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_CSIS_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D0_CSIS_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_CSIS_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_CSIS_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D0_CSIS_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D0_CSIS_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_CSIS_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D1_CSIS_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_CSIS_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_CSIS_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_CSIS_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D1_CSIS_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D1_CSIS_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_CSIS_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_CSIS_QCH_ENABLE, + QCH_CON_SYSREG_CSIS_QCH_CLOCK_REQ, + QCH_CON_SYSREG_CSIS_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DISP_CMU_DISP_QCH_ENABLE, + QCH_CON_DISP_CMU_DISP_QCH_CLOCK_REQ, + QCH_CON_DISP_CMU_DISP_QCH_EXPIRE_VAL, + QCH_CON_DISP_CMU_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DPUB_QCH_ENABLE, + QCH_CON_DPUB_QCH_CLOCK_REQ, + QCH_CON_DPUB_QCH_EXPIRE_VAL, + QCH_CON_DPUB_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_DISP_QCH_ENABLE, + QCH_CON_D_TZPC_DISP_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_DISP_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_DISP_QCH_ENABLE, + QCH_CON_GPC_DISP_QCH_CLOCK_REQ, + QCH_CON_GPC_DISP_QCH_EXPIRE_VAL, + QCH_CON_GPC_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_DISP_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_DISP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_DISP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_DISP_QCH_ENABLE, + QCH_CON_SYSREG_DISP_QCH_CLOCK_REQ, + QCH_CON_SYSREG_DISP_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DNS_QCH_00_ENABLE, + QCH_CON_DNS_QCH_00_CLOCK_REQ, + QCH_CON_DNS_QCH_00_EXPIRE_VAL, + QCH_CON_DNS_QCH_00_IGNORE_FORCE_PM_EN, + QCH_CON_DNS_QCH_01_ENABLE, + QCH_CON_DNS_QCH_01_CLOCK_REQ, + QCH_CON_DNS_QCH_01_EXPIRE_VAL, + QCH_CON_DNS_QCH_01_IGNORE_FORCE_PM_EN, + QCH_CON_DNS_CMU_DNS_QCH_ENABLE, + QCH_CON_DNS_CMU_DNS_QCH_CLOCK_REQ, + QCH_CON_DNS_CMU_DNS_QCH_EXPIRE_VAL, + QCH_CON_DNS_CMU_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_DNS_QCH_ENABLE, + QCH_CON_D_TZPC_DNS_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_DNS_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_DNS_QCH_ENABLE, + QCH_CON_GPC_DNS_QCH_CLOCK_REQ, + QCH_CON_GPC_DNS_QCH_EXPIRE_VAL, + QCH_CON_GPC_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_DNS_QCH_ENABLE, + QCH_CON_PPMU_D0_DNS_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_DNS_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_DNS_QCH_ENABLE, + QCH_CON_PPMU_D1_DNS_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_DNS_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D0_DNS_QCH_ENABLE, + QCH_CON_QE_D0_DNS_QCH_CLOCK_REQ, + QCH_CON_QE_D0_DNS_QCH_EXPIRE_VAL, + QCH_CON_QE_D0_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_DNS_QCH_ENABLE, + QCH_CON_QE_D1_DNS_QCH_CLOCK_REQ, + QCH_CON_QE_D1_DNS_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_DNS_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_DNS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_DNS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_DNS_QCH_ENABLE, + QCH_CON_SSMT_D0_DNS_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_DNS_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_DNS_QCH_ENABLE, + QCH_CON_SSMT_D1_DNS_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_DNS_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DNS_QCH_S1_ENABLE, + QCH_CON_SYSMMU_DNS_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_DNS_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_DNS_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DNS_QCH_S2_ENABLE, + QCH_CON_SYSMMU_DNS_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_DNS_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_DNS_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_DNS_QCH_ENABLE, + QCH_CON_SYSREG_DNS_QCH_CLOCK_REQ, + QCH_CON_SYSREG_DNS_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DPUF_QCH_DPU_DMA_ENABLE, + QCH_CON_DPUF_QCH_DPU_DMA_CLOCK_REQ, + QCH_CON_DPUF_QCH_DPU_DMA_EXPIRE_VAL, + QCH_CON_DPUF_QCH_DPU_DMA_IGNORE_FORCE_PM_EN, + QCH_CON_DPUF_QCH_DPU_DPP_ENABLE, + QCH_CON_DPUF_QCH_DPU_DPP_CLOCK_REQ, + QCH_CON_DPUF_QCH_DPU_DPP_EXPIRE_VAL, + QCH_CON_DPUF_QCH_DPU_DPP_IGNORE_FORCE_PM_EN, + QCH_CON_DPU_CMU_DPU_QCH_ENABLE, + QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, + QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, + QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_DPU_QCH_ENABLE, + QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_DPU_QCH_ENABLE, + QCH_CON_GPC_DPU_QCH_CLOCK_REQ, + QCH_CON_GPC_DPU_QCH_EXPIRE_VAL, + QCH_CON_GPC_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D2_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D2_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D2_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_DPUD0_QCH_ENABLE, + QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, + QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, + QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_DPUD1_QCH_ENABLE, + QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, + QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, + QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_DPUD2_QCH_ENABLE, + QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, + QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, + QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_DPU_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_DPU_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_DPU_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_DPU0_QCH_ENABLE, + QCH_CON_SSMT_DPU0_QCH_CLOCK_REQ, + QCH_CON_SSMT_DPU0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_DPU0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_DPU1_QCH_ENABLE, + QCH_CON_SSMT_DPU1_QCH_CLOCK_REQ, + QCH_CON_SSMT_DPU1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_DPU1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_DPU2_QCH_ENABLE, + QCH_CON_SSMT_DPU2_QCH_CLOCK_REQ, + QCH_CON_SSMT_DPU2_QCH_EXPIRE_VAL, + QCH_CON_SSMT_DPU2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD0_QCH_S1_ENABLE, + QCH_CON_SYSMMU_DPUD0_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD0_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD0_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD0_QCH_S2_ENABLE, + QCH_CON_SYSMMU_DPUD0_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD0_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD0_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD1_QCH_S1_ENABLE, + QCH_CON_SYSMMU_DPUD1_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD1_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD1_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD1_QCH_S2_ENABLE, + QCH_CON_SYSMMU_DPUD1_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD1_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD1_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD2_QCH_S1_ENABLE, + QCH_CON_SYSMMU_DPUD2_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD2_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD2_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_DPUD2_QCH_S2_ENABLE, + QCH_CON_SYSMMU_DPUD2_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_DPUD2_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_DPUD2_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_DPU_QCH_ENABLE, + QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, + QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_EH_QCH_ENABLE, + QCH_CON_D_TZPC_EH_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_EH_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_EH_QCH_ENABLE, + QCH_CON_EH_QCH_CLOCK_REQ, + QCH_CON_EH_QCH_EXPIRE_VAL, + QCH_CON_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_EH_CMU_EH_QCH_ENABLE, + QCH_CON_EH_CMU_EH_QCH_CLOCK_REQ, + QCH_CON_EH_CMU_EH_QCH_EXPIRE_VAL, + QCH_CON_EH_CMU_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_EH_QCH_ENABLE, + QCH_CON_GPC_EH_QCH_CLOCK_REQ, + QCH_CON_GPC_EH_QCH_EXPIRE_VAL, + QCH_CON_GPC_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_EH_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_EH_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_EH_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_EH_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_EH_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_EH_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_EH_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_EH_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_EH_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_EH_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_EH_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_EH_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_EH_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_EH_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_EH_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_EH_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_EH_QCH_ENABLE, + QCH_CON_PPMU_EH_QCH_CLOCK_REQ, + QCH_CON_PPMU_EH_QCH_EXPIRE_VAL, + QCH_CON_PPMU_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_EH_QCH_ENABLE, + QCH_CON_QE_EH_QCH_CLOCK_REQ, + QCH_CON_QE_EH_QCH_EXPIRE_VAL, + QCH_CON_QE_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_EH_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_EH_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_EH_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_EH_QCH_ENABLE, + QCH_CON_SSMT_EH_QCH_CLOCK_REQ, + QCH_CON_SSMT_EH_QCH_EXPIRE_VAL, + QCH_CON_SSMT_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_EH_QCH_ENABLE, + QCH_CON_SYSMMU_EH_QCH_CLOCK_REQ, + QCH_CON_SYSMMU_EH_QCH_EXPIRE_VAL, + QCH_CON_SYSMMU_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_EH_QCH_ENABLE, + QCH_CON_SYSREG_EH_QCH_CLOCK_REQ, + QCH_CON_SYSREG_EH_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_EH_QCH_ENABLE, + QCH_CON_UASC_EH_QCH_CLOCK_REQ, + QCH_CON_UASC_EH_QCH_EXPIRE_VAL, + QCH_CON_UASC_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_G2D_QCH_ENABLE, + QCH_CON_D_TZPC_G2D_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_G2D_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_G2D_QCH_ENABLE, + QCH_CON_G2D_QCH_CLOCK_REQ, + QCH_CON_G2D_QCH_EXPIRE_VAL, + QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_G2D_CMU_G2D_QCH_ENABLE, + QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, + QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, + QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_G2D_QCH_ENABLE, + QCH_CON_GPC_G2D_QCH_CLOCK_REQ, + QCH_CON_GPC_G2D_QCH_EXPIRE_VAL, + QCH_CON_GPC_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_JPEG_QCH_ENABLE, + QCH_CON_JPEG_QCH_CLOCK_REQ, + QCH_CON_JPEG_QCH_EXPIRE_VAL, + QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D2_G2D_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D2_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D2_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D2_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_G2D_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_G2D_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_G2D_QCH_ENABLE, + QCH_CON_PPMU_D0_G2D_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_G2D_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_G2D_QCH_ENABLE, + QCH_CON_PPMU_D1_G2D_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_G2D_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D2_G2D_QCH_ENABLE, + QCH_CON_PPMU_D2_G2D_QCH_CLOCK_REQ, + QCH_CON_PPMU_D2_G2D_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D2_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_G2D_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_G2D_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_G2D_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_G2D_QCH_ENABLE, + QCH_CON_SSMT_D0_G2D_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_G2D_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_G2D_QCH_ENABLE, + QCH_CON_SSMT_D1_G2D_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_G2D_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D2_G2D_QCH_ENABLE, + QCH_CON_SSMT_D2_G2D_QCH_CLOCK_REQ, + QCH_CON_SSMT_D2_G2D_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D2_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_G2D_QCH_0_ENABLE, + QCH_CON_SYSMMU_D0_G2D_QCH_0_CLOCK_REQ, + QCH_CON_SYSMMU_D0_G2D_QCH_0_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_G2D_QCH_0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_G2D_QCH_1_ENABLE, + QCH_CON_SYSMMU_D0_G2D_QCH_1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_G2D_QCH_1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_G2D_QCH_1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_G2D_QCH_0_ENABLE, + QCH_CON_SYSMMU_D1_G2D_QCH_0_CLOCK_REQ, + QCH_CON_SYSMMU_D1_G2D_QCH_0_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_G2D_QCH_0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_G2D_QCH_1_ENABLE, + QCH_CON_SYSMMU_D1_G2D_QCH_1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_G2D_QCH_1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_G2D_QCH_1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_G2D_QCH_0_ENABLE, + QCH_CON_SYSMMU_D2_G2D_QCH_0_CLOCK_REQ, + QCH_CON_SYSMMU_D2_G2D_QCH_0_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_G2D_QCH_0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_G2D_QCH_1_ENABLE, + QCH_CON_SYSMMU_D2_G2D_QCH_1_CLOCK_REQ, + QCH_CON_SYSMMU_D2_G2D_QCH_1_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_G2D_QCH_1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_G2D_QCH_ENABLE, + QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, + QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_G3AA_QCH_ENABLE, + QCH_CON_D_TZPC_G3AA_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_G3AA_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_G3AA_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_G3AA_QCH_ENABLE, + DMYQCH_CON_G3AA_QCH_CLOCK_REQ, + DMYQCH_CON_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_G3AA_CMU_G3AA_QCH_ENABLE, + QCH_CON_G3AA_CMU_G3AA_QCH_CLOCK_REQ, + QCH_CON_G3AA_CMU_G3AA_QCH_EXPIRE_VAL, + QCH_CON_G3AA_CMU_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_G3AA_QCH_ENABLE, + QCH_CON_GPC_G3AA_QCH_CLOCK_REQ, + QCH_CON_GPC_G3AA_QCH_EXPIRE_VAL, + QCH_CON_GPC_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_G3AA_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_G3AA_QCH_ENABLE, + QCH_CON_PPMU_G3AA_QCH_CLOCK_REQ, + QCH_CON_PPMU_G3AA_QCH_EXPIRE_VAL, + QCH_CON_PPMU_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_G3AA_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_G3AA_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_G3AA_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_G3AA_QCH_ENABLE, + QCH_CON_SSMT_G3AA_QCH_CLOCK_REQ, + QCH_CON_SSMT_G3AA_QCH_EXPIRE_VAL, + QCH_CON_SSMT_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3AA_QCH_S1_ENABLE, + QCH_CON_SYSMMU_G3AA_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_G3AA_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_G3AA_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3AA_QCH_S2_ENABLE, + QCH_CON_SYSMMU_G3AA_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_G3AA_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_G3AA_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_G3AA_QCH_ENABLE, + QCH_CON_SYSREG_G3AA_QCH_CLOCK_REQ, + QCH_CON_SYSREG_G3AA_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ADD_APBIF_G3D_QCH_ENABLE, + QCH_CON_ADD_APBIF_G3D_QCH_CLOCK_REQ, + QCH_CON_ADD_APBIF_G3D_QCH_EXPIRE_VAL, + QCH_CON_ADD_APBIF_G3D_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_ADD_G3D_QCH_ENABLE, + DMYQCH_CON_ADD_G3D_QCH_CLOCK_REQ, + DMYQCH_CON_ADD_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ADM_AHB_G_GPU_QCH_ENABLE, + QCH_CON_ADM_AHB_G_GPU_QCH_CLOCK_REQ, + QCH_CON_ADM_AHB_G_GPU_QCH_EXPIRE_VAL, + QCH_CON_ADM_AHB_G_GPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ASB_G3D_QCH_LH_D0_G3D_ENABLE, + QCH_CON_ASB_G3D_QCH_LH_D0_G3D_CLOCK_REQ, + QCH_CON_ASB_G3D_QCH_LH_D0_G3D_EXPIRE_VAL, + QCH_CON_ASB_G3D_QCH_LH_D0_G3D_IGNORE_FORCE_PM_EN, + QCH_CON_ASB_G3D_QCH_LH_D1_G3D_ENABLE, + QCH_CON_ASB_G3D_QCH_LH_D1_G3D_CLOCK_REQ, + QCH_CON_ASB_G3D_QCH_LH_D1_G3D_EXPIRE_VAL, + QCH_CON_ASB_G3D_QCH_LH_D1_G3D_IGNORE_FORCE_PM_EN, + QCH_CON_ASB_G3D_QCH_LH_D2_G3D_ENABLE, + QCH_CON_ASB_G3D_QCH_LH_D2_G3D_CLOCK_REQ, + QCH_CON_ASB_G3D_QCH_LH_D2_G3D_EXPIRE_VAL, + QCH_CON_ASB_G3D_QCH_LH_D2_G3D_IGNORE_FORCE_PM_EN, + QCH_CON_ASB_G3D_QCH_LH_D3_G3D_ENABLE, + QCH_CON_ASB_G3D_QCH_LH_D3_G3D_CLOCK_REQ, + QCH_CON_ASB_G3D_QCH_LH_D3_G3D_EXPIRE_VAL, + QCH_CON_ASB_G3D_QCH_LH_D3_G3D_IGNORE_FORCE_PM_EN, + QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, + QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, + QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, + QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_G3D_QCH_ENABLE, + QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_G3D_CMU_G3D_QCH_ENABLE, + QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, + QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, + QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_G3D_QCH_ENABLE, + QCH_CON_GPC_G3D_QCH_CLOCK_REQ, + QCH_CON_GPC_G3D_QCH_EXPIRE_VAL, + QCH_CON_GPC_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPU_QCH_ENABLE, + QCH_CON_GPU_QCH_CLOCK_REQ, + QCH_CON_GPU_QCH_EXPIRE_VAL, + QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_G3D_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_G3D_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_G3D_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_G3D_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_G3D_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_G3D_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_G3D_QCH_ENABLE, + QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, + QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_G3D_QCH_ENABLE, + QCH_CON_UASC_G3D_QCH_CLOCK_REQ, + QCH_CON_UASC_G3D_QCH_EXPIRE_VAL, + QCH_CON_UASC_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_GDC_QCH_ENABLE, + QCH_CON_D_TZPC_GDC_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_GDC_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GDC0_QCH_CLK_ENABLE, + QCH_CON_GDC0_QCH_CLK_CLOCK_REQ, + QCH_CON_GDC0_QCH_CLK_EXPIRE_VAL, + QCH_CON_GDC0_QCH_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_GDC0_QCH_C2CLK_ENABLE, + QCH_CON_GDC0_QCH_C2CLK_CLOCK_REQ, + QCH_CON_GDC0_QCH_C2CLK_EXPIRE_VAL, + QCH_CON_GDC0_QCH_C2CLK_IGNORE_FORCE_PM_EN, + QCH_CON_GDC1_QCH_CLK_ENABLE, + QCH_CON_GDC1_QCH_CLK_CLOCK_REQ, + QCH_CON_GDC1_QCH_CLK_EXPIRE_VAL, + QCH_CON_GDC1_QCH_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_GDC1_QCH_C2CLK_ENABLE, + QCH_CON_GDC1_QCH_C2CLK_CLOCK_REQ, + QCH_CON_GDC1_QCH_C2CLK_EXPIRE_VAL, + QCH_CON_GDC1_QCH_C2CLK_IGNORE_FORCE_PM_EN, + QCH_CON_GDC_CMU_GDC_QCH_ENABLE, + QCH_CON_GDC_CMU_GDC_QCH_CLOCK_REQ, + QCH_CON_GDC_CMU_GDC_QCH_EXPIRE_VAL, + QCH_CON_GDC_CMU_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_GDC_QCH_ENABLE, + QCH_CON_GPC_GDC_QCH_CLOCK_REQ, + QCH_CON_GPC_GDC_QCH_EXPIRE_VAL, + QCH_CON_GPC_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_ENABLE, + QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_ENABLE, + QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_ENABLE, + QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D2_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D2_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D2_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D2_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_ENABLE, + QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_GDC_QCH_ENABLE, + QCH_CON_PPMU_D0_GDC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_GDC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_SCSC_QCH_ENABLE, + QCH_CON_PPMU_D0_SCSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_SCSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_GDC_QCH_ENABLE, + QCH_CON_PPMU_D1_GDC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_GDC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_SCSC_QCH_ENABLE, + QCH_CON_PPMU_D1_SCSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_SCSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D2_GDC_QCH_ENABLE, + QCH_CON_PPMU_D2_GDC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D2_GDC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D2_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D2_SCSC_QCH_ENABLE, + QCH_CON_PPMU_D2_SCSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D2_SCSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D3_GDC_QCH_ENABLE, + QCH_CON_PPMU_D3_GDC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D3_GDC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D3_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D0_GDC_QCH_ENABLE, + QCH_CON_QE_D0_GDC_QCH_CLOCK_REQ, + QCH_CON_QE_D0_GDC_QCH_EXPIRE_VAL, + QCH_CON_QE_D0_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D0_SCSC_QCH_ENABLE, + QCH_CON_QE_D0_SCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D0_SCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_GDC_QCH_ENABLE, + QCH_CON_QE_D1_GDC_QCH_CLOCK_REQ, + QCH_CON_QE_D1_GDC_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_SCSC_QCH_ENABLE, + QCH_CON_QE_D1_SCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D1_SCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D2_GDC_QCH_ENABLE, + QCH_CON_QE_D2_GDC_QCH_CLOCK_REQ, + QCH_CON_QE_D2_GDC_QCH_EXPIRE_VAL, + QCH_CON_QE_D2_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D2_SCSC_QCH_ENABLE, + QCH_CON_QE_D2_SCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D2_SCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D3_GDC_QCH_ENABLE, + QCH_CON_QE_D3_GDC_QCH_CLOCK_REQ, + QCH_CON_QE_D3_GDC_QCH_EXPIRE_VAL, + QCH_CON_QE_D3_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SCSC_QCH_CLK_ENABLE, + QCH_CON_SCSC_QCH_CLK_CLOCK_REQ, + QCH_CON_SCSC_QCH_CLK_EXPIRE_VAL, + QCH_CON_SCSC_QCH_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_SCSC_QCH_C2CLK_ENABLE, + QCH_CON_SCSC_QCH_C2CLK_CLOCK_REQ, + QCH_CON_SCSC_QCH_C2CLK_EXPIRE_VAL, + QCH_CON_SCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_GDC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_GDC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_GDC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_GDC_QCH_ENABLE, + QCH_CON_SSMT_D0_GDC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_GDC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_SCSC_QCH_ENABLE, + QCH_CON_SSMT_D0_SCSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_SCSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_GDC_QCH_ENABLE, + QCH_CON_SSMT_D1_GDC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_GDC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_SCSC_QCH_ENABLE, + QCH_CON_SSMT_D1_SCSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_SCSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D2_GDC_QCH_ENABLE, + QCH_CON_SSMT_D2_GDC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D2_GDC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D2_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D2_SCSC_QCH_ENABLE, + QCH_CON_SSMT_D2_SCSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D2_SCSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D2_SCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D3_GDC_QCH_ENABLE, + QCH_CON_SSMT_D3_GDC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D3_GDC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D3_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_GDC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D0_GDC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_GDC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_GDC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_GDC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D0_GDC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D0_GDC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_GDC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_GDC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D1_GDC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_GDC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_GDC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_GDC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D1_GDC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D1_GDC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_GDC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_GDC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D2_GDC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D2_GDC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_GDC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_GDC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D2_GDC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D2_GDC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_GDC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_GDC_QCH_ENABLE, + QCH_CON_SYSREG_GDC_QCH_CLOCK_REQ, + QCH_CON_SYSREG_GDC_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_GDC_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_ENABLE, + DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_CLOCK_REQ, + DMYQCH_CON_AD_APB_SYSMMU_GSACORE_NS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BAAW_GSACORE_QCH_ENABLE, + QCH_CON_BAAW_GSACORE_QCH_CLOCK_REQ, + QCH_CON_BAAW_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_BAAW_GSACORE_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CA32_GSACORE_QCH_ENABLE, + DMYQCH_CON_CA32_GSACORE_QCH_CLOCK_REQ, + DMYQCH_CON_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DMA_GSACORE_QCH_ENABLE, + QCH_CON_DMA_GSACORE_QCH_CLOCK_REQ, + QCH_CON_DMA_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GIC_GSACORE_QCH_ENABLE, + QCH_CON_GIC_GSACORE_QCH_CLOCK_REQ, + QCH_CON_GIC_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_GIC_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_GSACORE_QCH_ENABLE, + QCH_CON_GPIO_GSACORE_QCH_CLOCK_REQ, + QCH_CON_GPIO_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_GPIO_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GSACORE_CMU_GSACORE_QCH_ENABLE, + QCH_CON_GSACORE_CMU_GSACORE_QCH_CLOCK_REQ, + QCH_CON_GSACORE_CMU_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_GSACORE_CMU_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_INTMEM_GSACORE_QCH_ENABLE, + QCH_CON_INTMEM_GSACORE_QCH_CLOCK_REQ, + QCH_CON_INTMEM_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_INTMEM_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_KDN_GSACORE_QCH_ENABLE, + QCH_CON_KDN_GSACORE_QCH_CLOCK_REQ, + QCH_CON_KDN_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_KDN_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_ENABLE, + QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_ENABLE, + QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_ENABLE, + QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_I_CA32_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_ENABLE, + QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_I_GIC_CA32_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT_GSA_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_GME_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_GME_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_GME_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_GME_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_AXI2APB1_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_AXI2APB2_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_GME_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_GME_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_GME_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_GME_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_OTP_CON_GSACORE_QCH_ENABLE, + QCH_CON_OTP_CON_GSACORE_QCH_CLOCK_REQ, + QCH_CON_OTP_CON_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_OTP_CON_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_GSACORE_QCH_ENABLE, + QCH_CON_PPMU_GSACORE_QCH_CLOCK_REQ, + QCH_CON_PPMU_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_PPMU_GSACORE_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PUF_GSACORE_QCH_ENABLE, + DMYQCH_CON_PUF_GSACORE_QCH_CLOCK_REQ, + DMYQCH_CON_PUF_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_CA32_GSACORE_QCH_ENABLE, + QCH_CON_QE_CA32_GSACORE_QCH_CLOCK_REQ, + QCH_CON_QE_CA32_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_QE_CA32_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_DMA_GSACORE_QCH_ENABLE, + QCH_CON_QE_DMA_GSACORE_QCH_CLOCK_REQ, + QCH_CON_QE_DMA_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_QE_DMA_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_SSS_GSACORE_QCH_ENABLE, + QCH_CON_QE_SSS_GSACORE_QCH_CLOCK_REQ, + QCH_CON_QE_SSS_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_QE_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RESETMON_GSACORE_QCH_ENABLE, + QCH_CON_RESETMON_GSACORE_QCH_CLOCK_REQ, + QCH_CON_RESETMON_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_RESETMON_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_SSS_ARESETN_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_SSS_HRESETN_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_SSS_PORRESETN_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SPI_FPS_GSACORE_QCH_ENABLE, + QCH_CON_SPI_FPS_GSACORE_QCH_CLOCK_REQ, + QCH_CON_SPI_FPS_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_SPI_FPS_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SPI_GSC_GSACORE_QCH_ENABLE, + QCH_CON_SPI_GSC_GSACORE_QCH_CLOCK_REQ, + QCH_CON_SPI_GSC_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_SPI_GSC_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_GSACORE_QCH_ENABLE, + QCH_CON_SSMT_GSACORE_QCH_CLOCK_REQ, + QCH_CON_SSMT_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_SSMT_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSS_GSACORE_QCH_ENABLE, + QCH_CON_SSS_GSACORE_QCH_CLOCK_REQ, + QCH_CON_SSS_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_SSS_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_GSACORE_QCH_S1_ENABLE, + QCH_CON_SYSMMU_GSACORE_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_GSACORE_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_GSACORE_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_GSACORE_QCH_S2_ENABLE, + QCH_CON_SYSMMU_GSACORE_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_GSACORE_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_GSACORE_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_GSACORE_QCH_ENABLE, + QCH_CON_SYSREG_GSACORE_QCH_CLOCK_REQ, + QCH_CON_SYSREG_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UART_GSACORE_QCH_ENABLE, + QCH_CON_UART_GSACORE_QCH_CLOCK_REQ, + QCH_CON_UART_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_UART_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_WDT_GSACORE_QCH_ENABLE, + QCH_CON_WDT_GSACORE_QCH_CLOCK_REQ, + QCH_CON_WDT_GSACORE_QCH_EXPIRE_VAL, + QCH_CON_WDT_GSACORE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_ENABLE, + QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_CLOCK_REQ, + QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_EXPIRE_VAL, + QCH_CON_UDAP_SSS_AHB_ASYNC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UGME_QCH_ENABLE, + QCH_CON_UGME_QCH_CLOCK_REQ, + QCH_CON_UGME_QCH_EXPIRE_VAL, + QCH_CON_UGME_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBIF_GPIO_GSACTRL_QCH_ENABLE, + QCH_CON_APBIF_GPIO_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_APBIF_GPIO_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_APBIF_GPIO_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_DAP_GSACTRL_QCH_ENABLE, + DMYQCH_CON_DAP_GSACTRL_QCH_CLOCK_REQ, + DMYQCH_CON_DAP_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_GSACTRL_QCH_ENABLE, + QCH_CON_GPC_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_GPC_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_GPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GSACTRL_CMU_GSACTRL_QCH_ENABLE, + QCH_CON_GSACTRL_CMU_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_GSACTRL_CMU_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_GSACTRL_CMU_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_INTMEM_GSACTRL_QCH_ENABLE, + QCH_CON_INTMEM_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_INTMEM_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_INTMEM_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_IP_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_MI_IP_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_IP_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_IP_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_ENABLE, + QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_IP_AXI2APB0_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_I_DAP_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_GSA_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_GSA2AOC_QCH_ENABLE, + QCH_CON_MAILBOX_GSA2AOC_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_GSA2AOC_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_GSA2AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_GSA2AUR_QCH_ENABLE, + QCH_CON_MAILBOX_GSA2AUR_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_GSA2AUR_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_GSA2AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_GSA2NONTZ_QCH_ENABLE, + QCH_CON_MAILBOX_GSA2NONTZ_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_GSA2NONTZ_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_GSA2NONTZ_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_GSA2TPU_QCH_ENABLE, + QCH_CON_MAILBOX_GSA2TPU_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_GSA2TPU_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_GSA2TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MAILBOX_GSA2TZ_QCH_ENABLE, + QCH_CON_MAILBOX_GSA2TZ_QCH_CLOCK_REQ, + QCH_CON_MAILBOX_GSA2TZ_QCH_EXPIRE_VAL, + QCH_CON_MAILBOX_GSA2TZ_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PMU_GSA_QCH_ENABLE, + QCH_CON_PMU_GSA_QCH_CLOCK_REQ, + QCH_CON_PMU_GSA_QCH_EXPIRE_VAL, + QCH_CON_PMU_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SECJTAG_GSACTRL_QCH_ENABLE, + QCH_CON_SECJTAG_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_SECJTAG_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_SECJTAG_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_GSA_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_GSA_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_GSA_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_GSACTRL_QCH_ENABLE, + QCH_CON_SYSREG_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_SYSREG_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_GSACTRLEXT_QCH_ENABLE, + QCH_CON_SYSREG_GSACTRLEXT_QCH_CLOCK_REQ, + QCH_CON_SYSREG_GSACTRLEXT_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_GSACTRLEXT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TIMER_GSACTRL_QCH_ENABLE, + QCH_CON_TIMER_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_TIMER_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_TIMER_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TZPC_GSACTRL_QCH_ENABLE, + QCH_CON_TZPC_GSACTRL_QCH_CLOCK_REQ, + QCH_CON_TZPC_GSACTRL_QCH_EXPIRE_VAL, + QCH_CON_TZPC_GSACTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DP_LINK_QCH_PCLK_ENABLE, + QCH_CON_DP_LINK_QCH_PCLK_CLOCK_REQ, + QCH_CON_DP_LINK_QCH_PCLK_EXPIRE_VAL, + QCH_CON_DP_LINK_QCH_PCLK_IGNORE_FORCE_PM_EN, + QCH_CON_DP_LINK_QCH_GTC_CLK_ENABLE, + QCH_CON_DP_LINK_QCH_GTC_CLK_CLOCK_REQ, + QCH_CON_DP_LINK_QCH_GTC_CLK_EXPIRE_VAL, + QCH_CON_DP_LINK_QCH_GTC_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_HSI0_QCH_ENABLE, + QCH_CON_D_TZPC_HSI0_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_HSI0_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, + QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, + QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, + QCH_CON_ETR_MIU_QCH_ACLK_IGNORE_FORCE_PM_EN, + QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, + QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, + QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, + QCH_CON_ETR_MIU_QCH_PCLK_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_HSI0_QCH_ENABLE, + QCH_CON_GPC_HSI0_QCH_CLOCK_REQ, + QCH_CON_GPC_HSI0_QCH_EXPIRE_VAL, + QCH_CON_GPC_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_HSI0_CMU_HSI0_QCH_ENABLE, + QCH_CON_HSI0_CMU_HSI0_QCH_CLOCK_REQ, + QCH_CON_HSI0_CMU_HSI0_QCH_EXPIRE_VAL, + QCH_CON_HSI0_CMU_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_HSI0_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_HSI0_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_HSI0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_HSI0_AOC_QCH_ENABLE, + QCH_CON_PPMU_HSI0_AOC_QCH_CLOCK_REQ, + QCH_CON_PPMU_HSI0_AOC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_HSI0_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_HSI0_NOCL1B_QCH_ENABLE, + QCH_CON_PPMU_HSI0_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_PPMU_HSI0_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_PPMU_HSI0_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LP1_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_HSI0_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_HSI0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_HSI0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_USB_QCH_ENABLE, + QCH_CON_SSMT_USB_QCH_CLOCK_REQ, + QCH_CON_SSMT_USB_QCH_EXPIRE_VAL, + QCH_CON_SSMT_USB_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_USB_QCH_S2_ENABLE, + QCH_CON_SYSMMU_USB_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_USB_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_USB_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_USB_QCH_S1_ENABLE, + QCH_CON_SYSMMU_USB_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_USB_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_USB_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_HSI0_QCH_ENABLE, + QCH_CON_SYSREG_HSI0_QCH_CLOCK_REQ, + QCH_CON_SYSREG_HSI0_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_HSI0_CTRL_QCH_ENABLE, + QCH_CON_UASC_HSI0_CTRL_QCH_CLOCK_REQ, + QCH_CON_UASC_HSI0_CTRL_QCH_EXPIRE_VAL, + QCH_CON_UASC_HSI0_CTRL_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_HSI0_LINK_QCH_ENABLE, + QCH_CON_UASC_HSI0_LINK_QCH_CLOCK_REQ, + QCH_CON_UASC_HSI0_LINK_QCH_EXPIRE_VAL, + QCH_CON_UASC_HSI0_LINK_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, + DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, + DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN, + QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, + QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, + QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, + QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN, + QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, + QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, + QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, + QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN, + QCH_CON_USB31DRD_QCH_APB_ENABLE, + QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, + QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, + QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN, + QCH_CON_USB31DRD_QCH_PCS_ENABLE, + QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, + QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, + QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN, + QCH_CON_USB31DRD_QCH_DBG_ENABLE, + QCH_CON_USB31DRD_QCH_DBG_CLOCK_REQ, + QCH_CON_USB31DRD_QCH_DBG_EXPIRE_VAL, + QCH_CON_USB31DRD_QCH_DBG_IGNORE_FORCE_PM_EN, + DMYQCH_CON_USB31DRD_QCH_ENABLE, + DMYQCH_CON_USB31DRD_QCH_CLOCK_REQ, + DMYQCH_CON_USB31DRD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_HSI1_QCH_ENABLE, + QCH_CON_D_TZPC_HSI1_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_HSI1_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_HSI1_QCH_ENABLE, + QCH_CON_GPC_HSI1_QCH_CLOCK_REQ, + QCH_CON_GPC_HSI1_QCH_EXPIRE_VAL, + QCH_CON_GPC_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_HSI1_QCH_ENABLE, + QCH_CON_GPIO_HSI1_QCH_CLOCK_REQ, + QCH_CON_GPIO_HSI1_QCH_EXPIRE_VAL, + QCH_CON_GPIO_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_HSI1_CMU_HSI1_QCH_ENABLE, + QCH_CON_HSI1_CMU_HSI1_QCH_CLOCK_REQ, + QCH_CON_HSI1_CMU_HSI1_QCH_EXPIRE_VAL, + QCH_CON_HSI1_CMU_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_HSI1_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_HSI1_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_HSI1_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_DBG_1_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_DBG_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_DBG_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_DBG_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_AXI_1_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_AXI_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_AXI_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_AXI_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_APB_1_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_APB_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_APB_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_APB_1_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_ENABLE, + DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_CLOCK_REQ, + DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_PCS_APB_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_PMA_APB_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_DBG_2_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_DBG_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_DBG_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_DBG_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_AXI_2_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_AXI_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_AXI_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_AXI_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_APB_2_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_APB_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_APB_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_APB_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_0_QCH_UDBG_ENABLE, + QCH_CON_PCIE_GEN4_0_QCH_UDBG_CLOCK_REQ, + QCH_CON_PCIE_GEN4_0_QCH_UDBG_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_0_QCH_UDBG_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PCIE_GEN4_0_QCH_ENABLE, + DMYQCH_CON_PCIE_GEN4_0_QCH_CLOCK_REQ, + DMYQCH_CON_PCIE_GEN4_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_IA_GEN4A_0_QCH_ENABLE, + QCH_CON_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, + QCH_CON_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, + QCH_CON_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_IA_GEN4B_0_QCH_ENABLE, + QCH_CON_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, + QCH_CON_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, + QCH_CON_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_HSI1_QCH_ENABLE, + QCH_CON_PPMU_HSI1_QCH_CLOCK_REQ, + QCH_CON_PPMU_HSI1_QCH_EXPIRE_VAL, + QCH_CON_PPMU_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_ENABLE, + QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_CLOCK_REQ, + QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_EXPIRE_VAL, + QCH_CON_QE_PCIE_GEN4A_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_ENABLE, + QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_CLOCK_REQ, + QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_EXPIRE_VAL, + QCH_CON_QE_PCIE_GEN4B_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_HSI1_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_HSI1_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_HSI1_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_HSI1_QCH_ENABLE, + QCH_CON_SSMT_HSI1_QCH_CLOCK_REQ, + QCH_CON_SSMT_HSI1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_ENABLE, + QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_CLOCK_REQ, + QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_ENABLE, + QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_CLOCK_REQ, + QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_HSI1_QCH_S2_ENABLE, + QCH_CON_SYSMMU_HSI1_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_HSI1_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_HSI1_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_HSI1_QCH_S1_ENABLE, + QCH_CON_SYSMMU_HSI1_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_HSI1_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_HSI1_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_HSI1_QCH_ENABLE, + QCH_CON_SYSREG_HSI1_QCH_CLOCK_REQ, + QCH_CON_SYSREG_HSI1_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_HSI2_QCH_ENABLE, + QCH_CON_D_TZPC_HSI2_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_HSI2_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_HSI2_QCH_ENABLE, + QCH_CON_GPC_HSI2_QCH_CLOCK_REQ, + QCH_CON_GPC_HSI2_QCH_EXPIRE_VAL, + QCH_CON_GPC_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_HSI2_QCH_ENABLE, + QCH_CON_GPIO_HSI2_QCH_CLOCK_REQ, + QCH_CON_GPIO_HSI2_QCH_EXPIRE_VAL, + QCH_CON_GPIO_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_HSI2UFS_QCH_ENABLE, + QCH_CON_GPIO_HSI2UFS_QCH_CLOCK_REQ, + QCH_CON_GPIO_HSI2UFS_QCH_EXPIRE_VAL, + QCH_CON_GPIO_HSI2UFS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_HSI2_CMU_HSI2_QCH_ENABLE, + QCH_CON_HSI2_CMU_HSI2_QCH_CLOCK_REQ, + QCH_CON_HSI2_CMU_HSI2_QCH_EXPIRE_VAL, + QCH_CON_HSI2_CMU_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_HSI2_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_HSI2_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_HSI2_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MMC_CARD_QCH_ENABLE, + QCH_CON_MMC_CARD_QCH_CLOCK_REQ, + QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, + QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_AXI_1_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_AXI_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_AXI_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_AXI_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_APB_1_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_APB_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_APB_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_APB_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_DBG_1_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_DBG_1_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_DBG_1_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_DBG_1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_PCS_APB_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_ENABLE, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_CLOCK_REQ, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF0_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_PMA_APB_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_AXI_2_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_AXI_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_AXI_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_AXI_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_DBG_2_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_DBG_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_DBG_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_DBG_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_APB_2_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_APB_2_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_APB_2_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_APB_2_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_GEN4_1_QCH_UDBG_ENABLE, + QCH_CON_PCIE_GEN4_1_QCH_UDBG_CLOCK_REQ, + QCH_CON_PCIE_GEN4_1_QCH_UDBG_EXPIRE_VAL, + QCH_CON_PCIE_GEN4_1_QCH_UDBG_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_ENABLE, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_CLOCK_REQ, + DMYQCH_CON_PCIE_GEN4_1_QCH_REF1_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_IA_GEN4A_1_QCH_ENABLE, + QCH_CON_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, + QCH_CON_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, + QCH_CON_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PCIE_IA_GEN4B_1_QCH_ENABLE, + QCH_CON_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, + QCH_CON_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, + QCH_CON_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_HSI2_QCH_ENABLE, + QCH_CON_PPMU_HSI2_QCH_CLOCK_REQ, + QCH_CON_PPMU_HSI2_QCH_EXPIRE_VAL, + QCH_CON_PPMU_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_MMC_CARD_HSI2_QCH_ENABLE, + QCH_CON_QE_MMC_CARD_HSI2_QCH_CLOCK_REQ, + QCH_CON_QE_MMC_CARD_HSI2_QCH_EXPIRE_VAL, + QCH_CON_QE_MMC_CARD_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_ENABLE, + QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_CLOCK_REQ, + QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_EXPIRE_VAL, + QCH_CON_QE_PCIE_GEN4A_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_ENABLE, + QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_CLOCK_REQ, + QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_EXPIRE_VAL, + QCH_CON_QE_PCIE_GEN4B_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_UFS_EMBD_HSI2_QCH_ENABLE, + QCH_CON_QE_UFS_EMBD_HSI2_QCH_CLOCK_REQ, + QCH_CON_QE_UFS_EMBD_HSI2_QCH_EXPIRE_VAL, + QCH_CON_QE_UFS_EMBD_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_HSI2_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_HSI2_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_HSI2_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_HSI2_QCH_ENABLE, + QCH_CON_SSMT_HSI2_QCH_CLOCK_REQ, + QCH_CON_SSMT_HSI2_QCH_EXPIRE_VAL, + QCH_CON_SSMT_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_ENABLE, + QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_CLOCK_REQ, + QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_ENABLE, + QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_CLOCK_REQ, + QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_HSI2_QCH_S2_ENABLE, + QCH_CON_SYSMMU_HSI2_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_HSI2_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_HSI2_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_HSI2_QCH_S1_ENABLE, + QCH_CON_SYSMMU_HSI2_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_HSI2_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_HSI2_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_HSI2_QCH_ENABLE, + QCH_CON_SYSREG_HSI2_QCH_CLOCK_REQ, + QCH_CON_SYSREG_HSI2_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_ENABLE, + QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_CLOCK_REQ, + QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_EXPIRE_VAL, + QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UFS_EMBD_QCH_ENABLE, + QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, + QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, + QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, + QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, + QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, + QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_IPP_QCH_ENABLE, + QCH_CON_D_TZPC_IPP_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_IPP_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_IPP_QCH_ENABLE, + QCH_CON_GPC_IPP_QCH_CLOCK_REQ, + QCH_CON_GPC_IPP_QCH_EXPIRE_VAL, + QCH_CON_GPC_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_IPP_CMU_IPP_QCH_ENABLE, + QCH_CON_IPP_CMU_IPP_QCH_CLOCK_REQ, + QCH_CON_IPP_CMU_IPP_QCH_EXPIRE_VAL, + QCH_CON_IPP_CMU_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D_IPP_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_IPP_QCH_ENABLE, + QCH_CON_PPMU_IPP_QCH_CLOCK_REQ, + QCH_CON_PPMU_IPP_QCH_EXPIRE_VAL, + QCH_CON_PPMU_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_MSA_QCH_ENABLE, + QCH_CON_PPMU_MSA_QCH_CLOCK_REQ, + QCH_CON_PPMU_MSA_QCH_EXPIRE_VAL, + QCH_CON_PPMU_MSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ALIGN0_QCH_ENABLE, + QCH_CON_QE_ALIGN0_QCH_CLOCK_REQ, + QCH_CON_QE_ALIGN0_QCH_EXPIRE_VAL, + QCH_CON_QE_ALIGN0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ALIGN1_QCH_ENABLE, + QCH_CON_QE_ALIGN1_QCH_CLOCK_REQ, + QCH_CON_QE_ALIGN1_QCH_EXPIRE_VAL, + QCH_CON_QE_ALIGN1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ALIGN2_QCH_ENABLE, + QCH_CON_QE_ALIGN2_QCH_CLOCK_REQ, + QCH_CON_QE_ALIGN2_QCH_EXPIRE_VAL, + QCH_CON_QE_ALIGN2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ALIGN3_QCH_ENABLE, + QCH_CON_QE_ALIGN3_QCH_CLOCK_REQ, + QCH_CON_QE_ALIGN3_QCH_EXPIRE_VAL, + QCH_CON_QE_ALIGN3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ALN_STAT_QCH_ENABLE, + QCH_CON_QE_ALN_STAT_QCH_CLOCK_REQ, + QCH_CON_QE_ALN_STAT_QCH_EXPIRE_VAL, + QCH_CON_QE_ALN_STAT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_FDPIG_QCH_ENABLE, + QCH_CON_QE_FDPIG_QCH_CLOCK_REQ, + QCH_CON_QE_FDPIG_QCH_EXPIRE_VAL, + QCH_CON_QE_FDPIG_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_RGBH0_QCH_ENABLE, + QCH_CON_QE_RGBH0_QCH_CLOCK_REQ, + QCH_CON_QE_RGBH0_QCH_EXPIRE_VAL, + QCH_CON_QE_RGBH0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_RGBH1_QCH_ENABLE, + QCH_CON_QE_RGBH1_QCH_CLOCK_REQ, + QCH_CON_QE_RGBH1_QCH_EXPIRE_VAL, + QCH_CON_QE_RGBH1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_RGBH2_QCH_ENABLE, + QCH_CON_QE_RGBH2_QCH_CLOCK_REQ, + QCH_CON_QE_RGBH2_QCH_EXPIRE_VAL, + QCH_CON_QE_RGBH2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_THSTAT_QCH_ENABLE, + QCH_CON_QE_THSTAT_QCH_CLOCK_REQ, + QCH_CON_QE_THSTAT_QCH_EXPIRE_VAL, + QCH_CON_QE_THSTAT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_TNR_MSA0_QCH_ENABLE, + QCH_CON_QE_TNR_MSA0_QCH_CLOCK_REQ, + QCH_CON_QE_TNR_MSA0_QCH_EXPIRE_VAL, + QCH_CON_QE_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_TNR_MSA1_QCH_ENABLE, + QCH_CON_QE_TNR_MSA1_QCH_CLOCK_REQ, + QCH_CON_QE_TNR_MSA1_QCH_EXPIRE_VAL, + QCH_CON_QE_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SIPU_IPP_QCH_ENABLE, + QCH_CON_SIPU_IPP_QCH_CLOCK_REQ, + QCH_CON_SIPU_IPP_QCH_EXPIRE_VAL, + QCH_CON_SIPU_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_IPP_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_IPP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_IPP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ALIGN0_QCH_ENABLE, + QCH_CON_SSMT_ALIGN0_QCH_CLOCK_REQ, + QCH_CON_SSMT_ALIGN0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ALIGN0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ALIGN1_QCH_ENABLE, + QCH_CON_SSMT_ALIGN1_QCH_CLOCK_REQ, + QCH_CON_SSMT_ALIGN1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ALIGN1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ALIGN2_QCH_ENABLE, + QCH_CON_SSMT_ALIGN2_QCH_CLOCK_REQ, + QCH_CON_SSMT_ALIGN2_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ALIGN2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ALIGN3_QCH_ENABLE, + QCH_CON_SSMT_ALIGN3_QCH_CLOCK_REQ, + QCH_CON_SSMT_ALIGN3_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ALIGN3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ALN_STAT_QCH_ENABLE, + QCH_CON_SSMT_ALN_STAT_QCH_CLOCK_REQ, + QCH_CON_SSMT_ALN_STAT_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ALN_STAT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_FDPIG_QCH_ENABLE, + QCH_CON_SSMT_FDPIG_QCH_CLOCK_REQ, + QCH_CON_SSMT_FDPIG_QCH_EXPIRE_VAL, + QCH_CON_SSMT_FDPIG_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_RGBH0_QCH_ENABLE, + QCH_CON_SSMT_RGBH0_QCH_CLOCK_REQ, + QCH_CON_SSMT_RGBH0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_RGBH0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_RGBH1_QCH_ENABLE, + QCH_CON_SSMT_RGBH1_QCH_CLOCK_REQ, + QCH_CON_SSMT_RGBH1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_RGBH1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_RGBH2_QCH_ENABLE, + QCH_CON_SSMT_RGBH2_QCH_CLOCK_REQ, + QCH_CON_SSMT_RGBH2_QCH_EXPIRE_VAL, + QCH_CON_SSMT_RGBH2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_THSTAT_QCH_ENABLE, + QCH_CON_SSMT_THSTAT_QCH_CLOCK_REQ, + QCH_CON_SSMT_THSTAT_QCH_EXPIRE_VAL, + QCH_CON_SSMT_THSTAT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_TNR_MSA0_QCH_ENABLE, + QCH_CON_SSMT_TNR_MSA0_QCH_CLOCK_REQ, + QCH_CON_SSMT_TNR_MSA0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_TNR_MSA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_TNR_MSA1_QCH_ENABLE, + QCH_CON_SSMT_TNR_MSA1_QCH_CLOCK_REQ, + QCH_CON_SSMT_TNR_MSA1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_TNR_MSA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_IPP_QCH_S1_ENABLE, + QCH_CON_SYSMMU_IPP_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_IPP_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_IPP_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_IPP_QCH_S2_ENABLE, + QCH_CON_SYSMMU_IPP_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_IPP_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_IPP_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_IPP_QCH_ENABLE, + QCH_CON_SYSREG_IPP_QCH_CLOCK_REQ, + QCH_CON_SYSREG_IPP_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TNR_A_QCH_ENABLE, + QCH_CON_TNR_A_QCH_CLOCK_REQ, + QCH_CON_TNR_A_QCH_EXPIRE_VAL, + QCH_CON_TNR_A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_ITP_QCH_ENABLE, + QCH_CON_D_TZPC_ITP_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_ITP_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_ITP_QCH_ENABLE, + QCH_CON_GPC_ITP_QCH_CLOCK_REQ, + QCH_CON_GPC_ITP_QCH_EXPIRE_VAL, + QCH_CON_GPC_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ITP_QCH_ENABLE, + QCH_CON_ITP_QCH_CLOCK_REQ, + QCH_CON_ITP_QCH_EXPIRE_VAL, + QCH_CON_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ITP_CMU_ITP_QCH_ENABLE, + QCH_CON_ITP_CMU_ITP_QCH_CLOCK_REQ, + QCH_CON_ITP_CMU_ITP_QCH_EXPIRE_VAL, + QCH_CON_ITP_CMU_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_ITP_QCH_ENABLE, + QCH_CON_PPMU_ITP_QCH_CLOCK_REQ, + QCH_CON_PPMU_ITP_QCH_EXPIRE_VAL, + QCH_CON_PPMU_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_ITP_QCH_ENABLE, + QCH_CON_QE_ITP_QCH_CLOCK_REQ, + QCH_CON_QE_ITP_QCH_EXPIRE_VAL, + QCH_CON_QE_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_ITP_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_ITP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_ITP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_ITP_QCH_ENABLE, + QCH_CON_SSMT_ITP_QCH_CLOCK_REQ, + QCH_CON_SSMT_ITP_QCH_EXPIRE_VAL, + QCH_CON_SSMT_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_ITP_QCH_ENABLE, + QCH_CON_SYSREG_ITP_QCH_CLOCK_REQ, + QCH_CON_SYSREG_ITP_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_C2R_MCSC_QCH_ENABLE, + QCH_CON_C2R_MCSC_QCH_CLOCK_REQ, + QCH_CON_C2R_MCSC_QCH_EXPIRE_VAL, + QCH_CON_C2R_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_MCSC_QCH_ENABLE, + QCH_CON_D_TZPC_MCSC_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_MCSC_QCH_ENABLE, + QCH_CON_GPC_MCSC_QCH_CLOCK_REQ, + QCH_CON_GPC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_GPC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ITSC_QCH_CLK_ENABLE, + QCH_CON_ITSC_QCH_CLK_CLOCK_REQ, + QCH_CON_ITSC_QCH_CLK_EXPIRE_VAL, + QCH_CON_ITSC_QCH_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_ITSC_QCH_C2_ENABLE, + QCH_CON_ITSC_QCH_C2_CLOCK_REQ, + QCH_CON_ITSC_QCH_C2_EXPIRE_VAL, + QCH_CON_ITSC_QCH_C2_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D2_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D2_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D2_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MCSC_QCH_CLK_ENABLE, + QCH_CON_MCSC_QCH_CLK_CLOCK_REQ, + QCH_CON_MCSC_QCH_CLK_EXPIRE_VAL, + QCH_CON_MCSC_QCH_CLK_IGNORE_FORCE_PM_EN, + QCH_CON_MCSC_QCH_C2CLK_ENABLE, + QCH_CON_MCSC_QCH_C2CLK_CLOCK_REQ, + QCH_CON_MCSC_QCH_C2CLK_EXPIRE_VAL, + QCH_CON_MCSC_QCH_C2CLK_IGNORE_FORCE_PM_EN, + QCH_CON_MCSC_CMU_MCSC_QCH_ENABLE, + QCH_CON_MCSC_CMU_MCSC_QCH_CLOCK_REQ, + QCH_CON_MCSC_CMU_MCSC_QCH_EXPIRE_VAL, + QCH_CON_MCSC_CMU_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_ITSC_QCH_ENABLE, + QCH_CON_PPMU_D0_ITSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_ITSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_MCSC_QCH_ENABLE, + QCH_CON_PPMU_D0_MCSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_MCSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_ITSC_QCH_ENABLE, + QCH_CON_PPMU_D1_ITSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_ITSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_MCSC_QCH_ENABLE, + QCH_CON_PPMU_D1_MCSC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_MCSC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D0_MCSC_QCH_ENABLE, + QCH_CON_QE_D0_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D0_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_ITSC_QCH_ENABLE, + QCH_CON_QE_D1_ITSC_QCH_CLOCK_REQ, + QCH_CON_QE_D1_ITSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_MCSC_QCH_ENABLE, + QCH_CON_QE_D1_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D1_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D2_ITSC_QCH_ENABLE, + QCH_CON_QE_D2_ITSC_QCH_CLOCK_REQ, + QCH_CON_QE_D2_ITSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D2_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D2_MCSC_QCH_ENABLE, + QCH_CON_QE_D2_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D2_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D3_ITSC_QCH_ENABLE, + QCH_CON_QE_D3_ITSC_QCH_CLOCK_REQ, + QCH_CON_QE_D3_ITSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D3_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D3_MCSC_QCH_ENABLE, + QCH_CON_QE_D3_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D3_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D3_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D4_MCSC_QCH_ENABLE, + QCH_CON_QE_D4_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D4_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D4_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D5_MCSC_QCH_ENABLE, + QCH_CON_QE_D5_MCSC_QCH_CLOCK_REQ, + QCH_CON_QE_D5_MCSC_QCH_EXPIRE_VAL, + QCH_CON_QE_D5_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_MCSC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_MCSC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_MCSC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_ITSC_QCH_ENABLE, + QCH_CON_SSMT_D0_ITSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_ITSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_MCSC_QCH_ENABLE, + QCH_CON_SSMT_D0_MCSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_MCSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_ITSC_QCH_ENABLE, + QCH_CON_SSMT_D1_ITSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_ITSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_ITSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_MCSC_QCH_ENABLE, + QCH_CON_SSMT_D1_MCSC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_MCSC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_MCSC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D0_MCSC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_MCSC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_MCSC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D0_MCSC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D0_MCSC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_MCSC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D1_MCSC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_MCSC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_MCSC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D1_MCSC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D1_MCSC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_MCSC_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D2_MCSC_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D2_MCSC_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_MCSC_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_MCSC_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D2_MCSC_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D2_MCSC_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_MCSC_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_MCSC_QCH_ENABLE, + QCH_CON_SYSREG_MCSC_QCH_CLOCK_REQ, + QCH_CON_SYSREG_MCSC_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_MFC_QCH_ENABLE, + QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_MFC_QCH_ENABLE, + QCH_CON_GPC_MFC_QCH_CLOCK_REQ, + QCH_CON_GPC_MFC_QCH_EXPIRE_VAL, + QCH_CON_GPC_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_MFC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_MFC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_MFC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_MFC_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_MFC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_MFC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MFC_QCH_ENABLE, + QCH_CON_MFC_QCH_CLOCK_REQ, + QCH_CON_MFC_QCH_EXPIRE_VAL, + QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MFC_CMU_MFC_QCH_ENABLE, + QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, + QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, + QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_MFC_QCH_ENABLE, + QCH_CON_PPMU_D0_MFC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_MFC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_MFC_QCH_ENABLE, + QCH_CON_PPMU_D1_MFC_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_MFC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_ENABLE, + QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_CLOCK_REQ, + QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_EXPIRE_VAL, + QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_MFC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_MFC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_MFC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_MFC_QCH_ENABLE, + QCH_CON_SSMT_D0_MFC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_MFC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_MFC_QCH_ENABLE, + QCH_CON_SSMT_D1_MFC_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_MFC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_MFC_QCH_0_ENABLE, + QCH_CON_SYSMMU_D0_MFC_QCH_0_CLOCK_REQ, + QCH_CON_SYSMMU_D0_MFC_QCH_0_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_MFC_QCH_0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_MFC_QCH_1_ENABLE, + QCH_CON_SYSMMU_D0_MFC_QCH_1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_MFC_QCH_1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_MFC_QCH_1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_MFC_QCH_0_ENABLE, + QCH_CON_SYSMMU_D1_MFC_QCH_0_CLOCK_REQ, + QCH_CON_SYSMMU_D1_MFC_QCH_0_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_MFC_QCH_0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_MFC_QCH_1_ENABLE, + QCH_CON_SYSMMU_D1_MFC_QCH_1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_MFC_QCH_1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_MFC_QCH_1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_MFC_QCH_ENABLE, + QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, + QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBBR_DDRPHY_QCH_ENABLE, + QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, + QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, + QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_APBBR_DMC_QCH_ENABLE, + QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, + QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, + QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DMC_QCH_ENABLE, + QCH_CON_DMC_QCH_CLOCK_REQ, + QCH_CON_DMC_QCH_EXPIRE_VAL, + QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_MIF_QCH_ENABLE, + QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GEN_WREN_SECURE_QCH_ENABLE, + QCH_CON_GEN_WREN_SECURE_QCH_CLOCK_REQ, + QCH_CON_GEN_WREN_SECURE_QCH_EXPIRE_VAL, + QCH_CON_GEN_WREN_SECURE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_MIF_QCH_ENABLE, + QCH_CON_GPC_MIF_QCH_CLOCK_REQ, + QCH_CON_GPC_MIF_QCH_EXPIRE_VAL, + QCH_CON_GPC_MIF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MIF_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MIF_CMU_MIF_QCH_ENABLE, + QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, + QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, + QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, + QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, + QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, + QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_MIF_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_MIF_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_MIF_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_MIF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_MIF_QCH_ENABLE, + QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, + QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ADM_AHB_G_SSS_QCH_ENABLE, + QCH_CON_ADM_AHB_G_SSS_QCH_CLOCK_REQ, + QCH_CON_ADM_AHB_G_SSS_QCH_EXPIRE_VAL, + QCH_CON_ADM_AHB_G_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_DIT_QCH_ENABLE, + QCH_CON_DIT_QCH_CLOCK_REQ, + QCH_CON_DIT_QCH_EXPIRE_VAL, + QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_MISC_QCH_ENABLE, + QCH_CON_D_TZPC_MISC_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_MISC_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GIC_QCH_ENABLE, + QCH_CON_GIC_QCH_CLOCK_REQ, + QCH_CON_GIC_QCH_EXPIRE_VAL, + QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_MISC_QCH_ENABLE, + QCH_CON_GPC_MISC_QCH_CLOCK_REQ, + QCH_CON_GPC_MISC_QCH_EXPIRE_VAL, + QCH_CON_GPC_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_MISC_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_MISC_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_MISC_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_ID_SSS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_ID_SSS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_ID_SSS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_ID_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_ID_SSS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_ID_SSS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_ID_SSS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_ID_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_GIC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MISC_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MCT_QCH_ENABLE, + QCH_CON_MCT_QCH_CLOCK_REQ, + QCH_CON_MCT_QCH_EXPIRE_VAL, + QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_MISC_CMU_MISC_QCH_ENABLE, + QCH_CON_MISC_CMU_MISC_QCH_CLOCK_REQ, + QCH_CON_MISC_CMU_MISC_QCH_EXPIRE_VAL, + QCH_CON_MISC_CMU_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_OTP_CON_BIRA_QCH_ENABLE, + QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, + QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, + QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_OTP_CON_BISR_QCH_ENABLE, + QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, + QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, + QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_OTP_CON_TOP_QCH_ENABLE, + QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, + QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, + QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PDMA0_QCH_ENABLE, + QCH_CON_PDMA0_QCH_CLOCK_REQ, + QCH_CON_PDMA0_QCH_EXPIRE_VAL, + QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PDMA1_QCH_ENABLE, + QCH_CON_PDMA1_QCH_CLOCK_REQ, + QCH_CON_PDMA1_QCH_EXPIRE_VAL, + QCH_CON_PDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_MISC_QCH_ENABLE, + QCH_CON_PPMU_MISC_QCH_CLOCK_REQ, + QCH_CON_PPMU_MISC_QCH_EXPIRE_VAL, + QCH_CON_PPMU_MISC_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PUF_QCH_ENABLE, + DMYQCH_CON_PUF_QCH_CLOCK_REQ, + DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_DIT_QCH_ENABLE, + QCH_CON_QE_DIT_QCH_CLOCK_REQ, + QCH_CON_QE_DIT_QCH_EXPIRE_VAL, + QCH_CON_QE_DIT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDMA0_QCH_ENABLE, + QCH_CON_QE_PDMA0_QCH_CLOCK_REQ, + QCH_CON_QE_PDMA0_QCH_EXPIRE_VAL, + QCH_CON_QE_PDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDMA1_QCH_ENABLE, + QCH_CON_QE_PDMA1_QCH_CLOCK_REQ, + QCH_CON_QE_PDMA1_QCH_EXPIRE_VAL, + QCH_CON_QE_PDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_RTIC_QCH_ENABLE, + QCH_CON_QE_RTIC_QCH_CLOCK_REQ, + QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, + QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_SPDMA0_QCH_ENABLE, + QCH_CON_QE_SPDMA0_QCH_CLOCK_REQ, + QCH_CON_QE_SPDMA0_QCH_EXPIRE_VAL, + QCH_CON_QE_SPDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_SPDMA1_QCH_ENABLE, + QCH_CON_QE_SPDMA1_QCH_CLOCK_REQ, + QCH_CON_QE_SPDMA1_QCH_EXPIRE_VAL, + QCH_CON_QE_SPDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_SSS_QCH_ENABLE, + QCH_CON_QE_SSS_QCH_CLOCK_REQ, + QCH_CON_QE_SSS_QCH_EXPIRE_VAL, + QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_RTIC_QCH_ENABLE, + QCH_CON_RTIC_QCH_CLOCK_REQ, + QCH_CON_RTIC_QCH_EXPIRE_VAL, + QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_GIC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_GIC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_GIC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_MISC_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_MISC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_MISC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SPDMA0_QCH_ENABLE, + QCH_CON_SPDMA0_QCH_CLOCK_REQ, + QCH_CON_SPDMA0_QCH_EXPIRE_VAL, + QCH_CON_SPDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SPDMA1_QCH_ENABLE, + QCH_CON_SPDMA1_QCH_CLOCK_REQ, + QCH_CON_SPDMA1_QCH_EXPIRE_VAL, + QCH_CON_SPDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_DIT_QCH_ENABLE, + QCH_CON_SSMT_DIT_QCH_CLOCK_REQ, + QCH_CON_SSMT_DIT_QCH_EXPIRE_VAL, + QCH_CON_SSMT_DIT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PDMA0_QCH_ENABLE, + QCH_CON_SSMT_PDMA0_QCH_CLOCK_REQ, + QCH_CON_SSMT_PDMA0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PDMA1_QCH_ENABLE, + QCH_CON_SSMT_PDMA1_QCH_CLOCK_REQ, + QCH_CON_SSMT_PDMA1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_RTIC_QCH_ENABLE, + QCH_CON_SSMT_RTIC_QCH_CLOCK_REQ, + QCH_CON_SSMT_RTIC_QCH_EXPIRE_VAL, + QCH_CON_SSMT_RTIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_SPDMA0_QCH_ENABLE, + QCH_CON_SSMT_SPDMA0_QCH_CLOCK_REQ, + QCH_CON_SSMT_SPDMA0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_SPDMA0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_SPDMA1_QCH_ENABLE, + QCH_CON_SSMT_SPDMA1_QCH_CLOCK_REQ, + QCH_CON_SSMT_SPDMA1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_SPDMA1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_SSS_QCH_ENABLE, + QCH_CON_SSMT_SSS_QCH_CLOCK_REQ, + QCH_CON_SSMT_SSS_QCH_EXPIRE_VAL, + QCH_CON_SSMT_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSS_QCH_ENABLE, + QCH_CON_SSS_QCH_CLOCK_REQ, + QCH_CON_SSS_QCH_EXPIRE_VAL, + QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_MISC_QCH_ENABLE, + QCH_CON_SYSMMU_MISC_QCH_CLOCK_REQ, + QCH_CON_SYSMMU_MISC_QCH_EXPIRE_VAL, + QCH_CON_SYSMMU_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_SSS_QCH_ENABLE, + QCH_CON_SYSMMU_SSS_QCH_CLOCK_REQ, + QCH_CON_SYSMMU_SSS_QCH_EXPIRE_VAL, + QCH_CON_SYSMMU_SSS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_MISC_QCH_ENABLE, + QCH_CON_SYSREG_MISC_QCH_CLOCK_REQ, + QCH_CON_SYSREG_MISC_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TMU_SUB_QCH_ENABLE, + QCH_CON_TMU_SUB_QCH_CLOCK_REQ, + QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, + QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TMU_TOP_QCH_ENABLE, + QCH_CON_TMU_TOP_QCH_CLOCK_REQ, + QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, + QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_WDT_CLUSTER0_QCH_ENABLE, + QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, + QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, + QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_WDT_CLUSTER1_QCH_ENABLE, + QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, + QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, + QCH_CON_WDT_CLUSTER1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_ASYNCSFR_WR_SMC_QCH_ENABLE, + QCH_CON_ASYNCSFR_WR_SMC_QCH_CLOCK_REQ, + QCH_CON_ASYNCSFR_WR_SMC_QCH_EXPIRE_VAL, + QCH_CON_ASYNCSFR_WR_SMC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BDU_QCH_ENABLE, + QCH_CON_BDU_QCH_CLOCK_REQ, + QCH_CON_BDU_QCH_EXPIRE_VAL, + QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CCI_QCH_ENABLE, + QCH_CON_CCI_QCH_CLOCK_REQ, + QCH_CON_CCI_QCH_EXPIRE_VAL, + QCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_NOCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_CPE425_QCH_ENABLE, + QCH_CON_CPE425_QCH_CLOCK_REQ, + QCH_CON_CPE425_QCH_EXPIRE_VAL, + QCH_CON_CPE425_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_NOCL0_QCH_ENABLE, + QCH_CON_D_TZPC_NOCL0_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_NOCL0_QCH_ENABLE, + QCH_CON_GPC_NOCL0_QCH_CLOCK_REQ, + QCH_CON_GPC_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_GPC_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_EH_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_EH_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_EH_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC0_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC0_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC0_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC1_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC1_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC1_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC2_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC2_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC2_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC3_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC3_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC3_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1A_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1B_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL2A_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC2_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_DMC3_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_BDU_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_BDU_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_BDU_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_BDU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_BDU_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_SLC_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_SLC_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_SLC_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_SLC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_T_SLC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_EH_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_EH_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_EH_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_EH_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_EH_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_EH_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_EH_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_GIC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_MISC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_NOCL0_CMU_NOCL0_QCH_ENABLE, + QCH_CON_NOCL0_CMU_NOCL0_QCH_CLOCK_REQ, + QCH_CON_NOCL0_CMU_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_NOCL0_CMU_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CCI_M1_CYCLE_QCH_ENABLE, + QCH_CON_PPC_CCI_M1_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_CCI_M1_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_CCI_M1_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CCI_M1_EVENT_QCH_ENABLE, + QCH_CON_PPC_CCI_M1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CCI_M1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CCI_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CCI_M2_EVENT_QCH_ENABLE, + QCH_CON_PPC_CCI_M2_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CCI_M2_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CCI_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CCI_M3_EVENT_QCH_ENABLE, + QCH_CON_PPC_CCI_M3_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CCI_M3_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CCI_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CCI_M4_EVENT_QCH_ENABLE, + QCH_CON_PPC_CCI_M4_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CCI_M4_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CCI_M4_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_ENABLE, + QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CPUCL0_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_ENABLE, + QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_CPUCL0_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_PPC_DBG_CC_QCH_ENABLE, + DMYQCH_CON_PPC_DBG_CC_QCH_CLOCK_REQ, + DMYQCH_CON_PPC_DBG_CC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_EH_CYCLE_QCH_ENABLE, + QCH_CON_PPC_EH_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_EH_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_EH_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_EH_EVENT_QCH_ENABLE, + QCH_CON_PPC_EH_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_EH_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_EH_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_IO_CYCLE_QCH_ENABLE, + QCH_CON_PPC_IO_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_IO_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_IO_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_IO_EVENT_QCH_ENABLE, + QCH_CON_PPC_IO_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_IO_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_IO_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL1B_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_ENABLE, + QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_CLOCK_REQ, + QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_EXPIRE_VAL, + QCH_CON_PPMU_ACE_CPUCL0_D0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_ENABLE, + QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_CLOCK_REQ, + QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_EXPIRE_VAL, + QCH_CON_PPMU_ACE_CPUCL0_D1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SFR_APBIF_CMU_TOPC_QCH_ENABLE, + QCH_CON_SFR_APBIF_CMU_TOPC_QCH_CLOCK_REQ, + QCH_CON_SFR_APBIF_CMU_TOPC_QCH_EXPIRE_VAL, + QCH_CON_SFR_APBIF_CMU_TOPC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLC_CB_TOP_QCH_ENABLE, + QCH_CON_SLC_CB_TOP_QCH_CLOCK_REQ, + QCH_CON_SLC_CB_TOP_QCH_EXPIRE_VAL, + QCH_CON_SLC_CB_TOP_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_SLC_CH1_QCH_ENABLE, + DMYQCH_CON_SLC_CH1_QCH_CLOCK_REQ, + DMYQCH_CON_SLC_CH1_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_SLC_CH2_QCH_ENABLE, + DMYQCH_CON_SLC_CH2_QCH_CLOCK_REQ, + DMYQCH_CON_SLC_CH2_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_SLC_CH3_QCH_ENABLE, + DMYQCH_CON_SLC_CH3_QCH_CLOCK_REQ, + DMYQCH_CON_SLC_CH3_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_SLC_CH_TOP_QCH_ENABLE, + DMYQCH_CON_SLC_CH_TOP_QCH_CLOCK_REQ, + DMYQCH_CON_SLC_CH_TOP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_G_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_ALIVE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_EH_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_EH_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_EH_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_EH_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_GIC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_GIC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_GIC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_GIC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MIF0_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MIF0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MIF0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MIF0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MIF1_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MIF1_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MIF1_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MIF1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MIF2_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MIF2_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MIF2_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MIF2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MIF3_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MIF3_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MIF3_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MIF3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MISC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MISC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MISC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_NOCL0_QCH_ENABLE, + QCH_CON_SYSREG_NOCL0_QCH_CLOCK_REQ, + QCH_CON_SYSREG_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_D_NOCL0_QCH_ENABLE, + QCH_CON_TREX_D_NOCL0_QCH_CLOCK_REQ, + QCH_CON_TREX_D_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_TREX_D_NOCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_P_NOCL0_QCH_ENABLE, + QCH_CON_TREX_P_NOCL0_QCH_CLOCK_REQ, + QCH_CON_TREX_P_NOCL0_QCH_EXPIRE_VAL, + QCH_CON_TREX_P_NOCL0_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_NOCL1A_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_NOCL1A_QCH_ENABLE, + QCH_CON_D_TZPC_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_NOCL1A_QCH_ENABLE, + QCH_CON_GPC_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_GPC_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_GPC_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D0_G3D_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D0_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D0_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D0_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D1_G3D_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D1_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D1_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D1_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D2_G3D_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D2_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D2_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D2_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D3_G3D_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D3_G3D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D3_G3D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D3_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_TPU_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_TPU_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_TPU_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1A_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_AUR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_AUR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_AUR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_AUR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_AUR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_AUR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_AUR_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_G3D_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_TPU_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_NOCL1A_CMU_NOCL1A_QCH_ENABLE, + QCH_CON_NOCL1A_CMU_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_NOCL1A_CMU_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_NOCL1A_CMU_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPCFW_G3D0_QCH_ENABLE, + QCH_CON_PPCFW_G3D0_QCH_CLOCK_REQ, + QCH_CON_PPCFW_G3D0_QCH_EXPIRE_VAL, + QCH_CON_PPCFW_G3D0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPCFW_G3D1_QCH_ENABLE, + QCH_CON_PPCFW_G3D1_QCH_CLOCK_REQ, + QCH_CON_PPCFW_G3D1_QCH_EXPIRE_VAL, + QCH_CON_PPCFW_G3D1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_AUR_D0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_AUR_D0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_AUR_D0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_AUR_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_AUR_D0_EVENT_QCH_ENABLE, + QCH_CON_PPC_AUR_D0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_AUR_D0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_AUR_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_AUR_D1_EVENT_QCH_ENABLE, + QCH_CON_PPC_AUR_D1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_AUR_D1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_AUR_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_G3D_D0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_G3D_D0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_G3D_D0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_G3D_D0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_G3D_D0_EVENT_QCH_ENABLE, + QCH_CON_PPC_G3D_D0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_G3D_D0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_G3D_D0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_G3D_D1_EVENT_QCH_ENABLE, + QCH_CON_PPC_G3D_D1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_G3D_D1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_G3D_D1_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_G3D_D2_EVENT_QCH_ENABLE, + QCH_CON_PPC_G3D_D2_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_G3D_D2_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_G3D_D2_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_G3D_D3_EVENT_QCH_ENABLE, + QCH_CON_PPC_G3D_D3_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_G3D_D3_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_G3D_D3_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_ENABLE, + QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL2A_M0_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL2A_M1_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL2A_M2_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_ENABLE, + QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_NOCL2A_M3_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_TPU_CYCLE_QCH_ENABLE, + QCH_CON_PPC_TPU_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_TPU_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_TPU_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_TPU_EVENT_QCH_ENABLE, + QCH_CON_PPC_TPU_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_TPU_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_TPU_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_AUR_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_AUR_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_AUR_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_AUR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_G3D_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_G3D_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_G3D_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_G3D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_TPU_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_TPU_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_TPU_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_G3D0_QCH_ENABLE, + QCH_CON_SSMT_G3D0_QCH_CLOCK_REQ, + QCH_CON_SSMT_G3D0_QCH_EXPIRE_VAL, + QCH_CON_SSMT_G3D0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_G3D1_QCH_ENABLE, + QCH_CON_SSMT_G3D1_QCH_CLOCK_REQ, + QCH_CON_SSMT_G3D1_QCH_EXPIRE_VAL, + QCH_CON_SSMT_G3D1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_G3D2_QCH_ENABLE, + QCH_CON_SSMT_G3D2_QCH_CLOCK_REQ, + QCH_CON_SSMT_G3D2_QCH_EXPIRE_VAL, + QCH_CON_SSMT_G3D2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_G3D3_QCH_ENABLE, + QCH_CON_SSMT_G3D3_QCH_CLOCK_REQ, + QCH_CON_SSMT_G3D3_QCH_EXPIRE_VAL, + QCH_CON_SSMT_G3D3_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3D_QCH_D0_ENABLE, + QCH_CON_SYSMMU_G3D_QCH_D0_CLOCK_REQ, + QCH_CON_SYSMMU_G3D_QCH_D0_EXPIRE_VAL, + QCH_CON_SYSMMU_G3D_QCH_D0_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3D_QCH_D1_ENABLE, + QCH_CON_SYSMMU_G3D_QCH_D1_CLOCK_REQ, + QCH_CON_SYSMMU_G3D_QCH_D1_EXPIRE_VAL, + QCH_CON_SYSMMU_G3D_QCH_D1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3D_QCH_D2_ENABLE, + QCH_CON_SYSMMU_G3D_QCH_D2_CLOCK_REQ, + QCH_CON_SYSMMU_G3D_QCH_D2_EXPIRE_VAL, + QCH_CON_SYSMMU_G3D_QCH_D2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3D_QCH_D3_ENABLE, + QCH_CON_SYSMMU_G3D_QCH_D3_CLOCK_REQ, + QCH_CON_SYSMMU_G3D_QCH_D3_EXPIRE_VAL, + QCH_CON_SYSMMU_G3D_QCH_D3_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_G3D_QCH_MPTW_ENABLE, + QCH_CON_SYSMMU_G3D_QCH_MPTW_CLOCK_REQ, + QCH_CON_SYSMMU_G3D_QCH_MPTW_EXPIRE_VAL, + QCH_CON_SYSMMU_G3D_QCH_MPTW_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_NOCL1A_QCH_ENABLE, + QCH_CON_SYSREG_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_SYSREG_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_D_NOCL1A_QCH_ENABLE, + QCH_CON_TREX_D_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_TREX_D_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_TREX_D_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_P_NOCL1A_QCH_ENABLE, + QCH_CON_TREX_P_NOCL1A_QCH_CLOCK_REQ, + QCH_CON_TREX_P_NOCL1A_QCH_EXPIRE_VAL, + QCH_CON_TREX_P_NOCL1A_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_NOCL1B_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_NOCL1B_QCH_ENABLE, + QCH_CON_D_TZPC_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_NOCL1B_QCH_ENABLE, + QCH_CON_GPC_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_GPC_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_GPC_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_HSI0_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_HSI0_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_HSI0_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_HSI1_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_HSI1_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_HSI1_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1B_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_AOC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_AOC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_AOC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_APM_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_APM_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_APM_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_APM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_GSA_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_GSA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_GSA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_AOC_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_GSA_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_NOCL1B_CMU_NOCL1B_QCH_ENABLE, + QCH_CON_NOCL1B_CMU_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_NOCL1B_CMU_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_NOCL1B_CMU_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_AOC_CYCLE_QCH_ENABLE, + QCH_CON_PPC_AOC_CYCLE_QCH_CLOCK_REQ, + QCH_CON_PPC_AOC_CYCLE_QCH_EXPIRE_VAL, + QCH_CON_PPC_AOC_CYCLE_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPC_AOC_EVENT_QCH_ENABLE, + QCH_CON_PPC_AOC_EVENT_QCH_CLOCK_REQ, + QCH_CON_PPC_AOC_EVENT_QCH_EXPIRE_VAL, + QCH_CON_PPC_AOC_EVENT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_AOC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_AOC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_AOC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_AOC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_GSA_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_GSA_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_GSA_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_GSA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_HSI0_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_HSI0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_HSI0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_HSI0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_HSI1_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_HSI1_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_HSI1_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_HSI1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_NOCL1B_QCH_ENABLE, + QCH_CON_SYSREG_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_SYSREG_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_D_NOCL1B_QCH_ENABLE, + QCH_CON_TREX_D_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_TREX_D_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_TREX_D_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_P_NOCL1B_QCH_ENABLE, + QCH_CON_TREX_P_NOCL1B_QCH_CLOCK_REQ, + QCH_CON_TREX_P_NOCL1B_QCH_EXPIRE_VAL, + QCH_CON_TREX_P_NOCL1B_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_ENABLE, + DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_CLOCK_REQ, + DMYQCH_CON_CMU_NOCL2A_CMUREF_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_NOCL2A_QCH_ENABLE, + QCH_CON_D_TZPC_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_NOCL2A_QCH_ENABLE, + QCH_CON_GPC_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_GPC_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_GPC_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D2_G2D_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D2_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D2_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D2_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_HSI2_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_HSI2_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_HSI2_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_MI_D_MISC_QCH_ENABLE, + QCH_CON_LH_ACEL_MI_D_MISC_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_MI_D_MISC_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_MI_D_MISC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_ENABLE, + QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL2A_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_ENABLE, + QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_G2D_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_MFC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_MFC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_MFC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D0_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D0_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D0_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_G2D_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_G2D_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_G2D_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_MFC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_MFC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_MFC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D1_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D1_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D1_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D2_DPU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D2_DPU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D2_DPU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D2_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D2_GDC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D2_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D2_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D2_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D2_MCSC_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D2_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D2_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D2_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D2_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D2_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D2_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D2_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D3_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D3_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D3_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D3_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D4_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D4_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D4_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D4_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_BO_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_BO_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_BO_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_G3AA_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_D_IPP_QCH_ENABLE, + QCH_CON_LH_AXI_MI_D_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_D_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_D_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_NOCL2A_CMU_NOCL2A_QCH_ENABLE, + QCH_CON_NOCL2A_CMU_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_NOCL2A_CMU_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_NOCL2A_CMU_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_BO_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_BO_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_BO_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_BO_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_CSIS_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_CSIS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_CSIS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_DISP_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_DISP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_DISP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_DISP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_DNS_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_DNS_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_DNS_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_DPU_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_DPU_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_DPU_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_DPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_G2D_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_G2D_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_G2D_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_G2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_G3AA_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_G3AA_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_G3AA_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_GDC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_GDC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_GDC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_HSI2_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_HSI2_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_HSI2_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_HSI2_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_IPP_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_IPP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_IPP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_ITP_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_ITP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_ITP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_ITP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MCSC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MCSC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MCSC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_MFC_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_MFC_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_MFC_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_MFC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_PDP_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_PDP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_PDP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_SI_P_TNR_QCH_ENABLE, + QCH_CON_SLH_AXI_SI_P_TNR_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_SI_P_TNR_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_SI_P_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_NOCL2A_QCH_ENABLE, + QCH_CON_SYSREG_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_SYSREG_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_D_NOCL2A_QCH_ENABLE, + QCH_CON_TREX_D_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_TREX_D_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_TREX_D_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TREX_P_NOCL2A_QCH_ENABLE, + QCH_CON_TREX_P_NOCL2A_QCH_CLOCK_REQ, + QCH_CON_TREX_P_NOCL2A_QCH_EXPIRE_VAL, + QCH_CON_TREX_P_NOCL2A_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_PDP_QCH_ENABLE, + QCH_CON_D_TZPC_PDP_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_PDP_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_PDP_QCH_ENABLE, + QCH_CON_GPC_PDP_QCH_CLOCK_REQ, + QCH_CON_GPC_PDP_QCH_EXPIRE_VAL, + QCH_CON_GPC_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PDP_CMU_PDP_QCH_ENABLE, + QCH_CON_PDP_CMU_PDP_QCH_CLOCK_REQ, + QCH_CON_PDP_CMU_PDP_QCH_EXPIRE_VAL, + QCH_CON_PDP_CMU_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PDP_TOP_QCH_C2_PDP_ENABLE, + QCH_CON_PDP_TOP_QCH_C2_PDP_CLOCK_REQ, + QCH_CON_PDP_TOP_QCH_C2_PDP_EXPIRE_VAL, + QCH_CON_PDP_TOP_QCH_C2_PDP_IGNORE_FORCE_PM_EN, + QCH_CON_PDP_TOP_QCH_PDP_TOP_ENABLE, + QCH_CON_PDP_TOP_QCH_PDP_TOP_CLOCK_REQ, + QCH_CON_PDP_TOP_QCH_PDP_TOP_EXPIRE_VAL, + QCH_CON_PDP_TOP_QCH_PDP_TOP_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_VRA_QCH_ENABLE, + QCH_CON_PPMU_VRA_QCH_CLOCK_REQ, + QCH_CON_PPMU_VRA_QCH_EXPIRE_VAL, + QCH_CON_PPMU_VRA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDP_AF0_QCH_ENABLE, + QCH_CON_QE_PDP_AF0_QCH_CLOCK_REQ, + QCH_CON_QE_PDP_AF0_QCH_EXPIRE_VAL, + QCH_CON_QE_PDP_AF0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDP_AF1_QCH_ENABLE, + QCH_CON_QE_PDP_AF1_QCH_CLOCK_REQ, + QCH_CON_QE_PDP_AF1_QCH_EXPIRE_VAL, + QCH_CON_QE_PDP_AF1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDP_STAT0_QCH_ENABLE, + QCH_CON_QE_PDP_STAT0_QCH_CLOCK_REQ, + QCH_CON_QE_PDP_STAT0_QCH_EXPIRE_VAL, + QCH_CON_QE_PDP_STAT0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_PDP_STAT1_QCH_ENABLE, + QCH_CON_QE_PDP_STAT1_QCH_CLOCK_REQ, + QCH_CON_QE_PDP_STAT1_QCH_EXPIRE_VAL, + QCH_CON_QE_PDP_STAT1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_VRA_QCH_ENABLE, + QCH_CON_QE_VRA_QCH_CLOCK_REQ, + QCH_CON_QE_VRA_QCH_EXPIRE_VAL, + QCH_CON_QE_VRA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_PDP_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_PDP_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_PDP_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_PDP_STAT_QCH_ENABLE, + QCH_CON_SSMT_PDP_STAT_QCH_CLOCK_REQ, + QCH_CON_SSMT_PDP_STAT_QCH_EXPIRE_VAL, + QCH_CON_SSMT_PDP_STAT_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_VRA_QCH_ENABLE, + QCH_CON_SSMT_VRA_QCH_CLOCK_REQ, + QCH_CON_SSMT_VRA_QCH_EXPIRE_VAL, + QCH_CON_SSMT_VRA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_PDP_QCH_ENABLE, + QCH_CON_SYSREG_PDP_QCH_CLOCK_REQ, + QCH_CON_SYSREG_PDP_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_PDP_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_VRA_QCH_ENABLE, + QCH_CON_VRA_QCH_CLOCK_REQ, + QCH_CON_VRA_QCH_EXPIRE_VAL, + QCH_CON_VRA_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, + QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_PERIC0_QCH_ENABLE, + QCH_CON_GPC_PERIC0_QCH_CLOCK_REQ, + QCH_CON_GPC_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_GPC_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_PERIC0_QCH_ENABLE, + QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, + QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C1_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C1_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C1_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C1_QCH_PCLK_ENABLE, + QCH_CON_I3C1_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C1_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C1_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C2_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C2_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C2_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C2_QCH_PCLK_ENABLE, + QCH_CON_I3C2_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C2_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C2_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C3_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C3_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C3_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C3_QCH_PCLK_ENABLE, + QCH_CON_I3C3_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C3_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C3_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C4_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C4_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C4_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C4_QCH_PCLK_ENABLE, + QCH_CON_I3C4_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C4_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C4_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C5_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C5_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C5_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C5_QCH_PCLK_ENABLE, + QCH_CON_I3C5_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C5_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C5_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C6_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C6_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C6_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C6_QCH_PCLK_ENABLE, + QCH_CON_I3C6_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C6_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C6_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C7_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C7_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C7_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C7_QCH_PCLK_ENABLE, + QCH_CON_I3C7_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C7_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C7_QCH_PCLK_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C8_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C8_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C8_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C8_QCH_PCLK_ENABLE, + QCH_CON_I3C8_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C8_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C8_QCH_PCLK_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, + QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, + QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_PERIC0_QCH_ENABLE, + QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, + QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI0_UART_QCH_ENABLE, + QCH_CON_USI0_UART_QCH_CLOCK_REQ, + QCH_CON_USI0_UART_QCH_EXPIRE_VAL, + QCH_CON_USI0_UART_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI14_USI_QCH_ENABLE, + QCH_CON_USI14_USI_QCH_CLOCK_REQ, + QCH_CON_USI14_USI_QCH_EXPIRE_VAL, + QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI1_USI_QCH_ENABLE, + QCH_CON_USI1_USI_QCH_CLOCK_REQ, + QCH_CON_USI1_USI_QCH_EXPIRE_VAL, + QCH_CON_USI1_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI2_USI_QCH_ENABLE, + QCH_CON_USI2_USI_QCH_CLOCK_REQ, + QCH_CON_USI2_USI_QCH_EXPIRE_VAL, + QCH_CON_USI2_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI3_USI_QCH_ENABLE, + QCH_CON_USI3_USI_QCH_CLOCK_REQ, + QCH_CON_USI3_USI_QCH_EXPIRE_VAL, + QCH_CON_USI3_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI4_USI_QCH_ENABLE, + QCH_CON_USI4_USI_QCH_CLOCK_REQ, + QCH_CON_USI4_USI_QCH_EXPIRE_VAL, + QCH_CON_USI4_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI5_USI_QCH_ENABLE, + QCH_CON_USI5_USI_QCH_CLOCK_REQ, + QCH_CON_USI5_USI_QCH_EXPIRE_VAL, + QCH_CON_USI5_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI6_USI_QCH_ENABLE, + QCH_CON_USI6_USI_QCH_CLOCK_REQ, + QCH_CON_USI6_USI_QCH_EXPIRE_VAL, + QCH_CON_USI6_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI7_USI_QCH_ENABLE, + QCH_CON_USI7_USI_QCH_CLOCK_REQ, + QCH_CON_USI7_USI_QCH_EXPIRE_VAL, + QCH_CON_USI7_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI8_USI_QCH_ENABLE, + QCH_CON_USI8_USI_QCH_CLOCK_REQ, + QCH_CON_USI8_USI_QCH_EXPIRE_VAL, + QCH_CON_USI8_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, + QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_PERIC1_QCH_ENABLE, + QCH_CON_GPC_PERIC1_QCH_CLOCK_REQ, + QCH_CON_GPC_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_GPC_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPIO_PERIC1_QCH_ENABLE, + QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, + QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_I3C0_QCH_SCLK_ENABLE, + DMYQCH_CON_I3C0_QCH_SCLK_CLOCK_REQ, + DMYQCH_CON_I3C0_QCH_SCLK_IGNORE_FORCE_PM_EN, + QCH_CON_I3C0_QCH_PCLK_ENABLE, + QCH_CON_I3C0_QCH_PCLK_CLOCK_REQ, + QCH_CON_I3C0_QCH_PCLK_EXPIRE_VAL, + QCH_CON_I3C0_QCH_PCLK_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, + QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, + QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PWM_QCH_ENABLE, + QCH_CON_PWM_QCH_CLOCK_REQ, + QCH_CON_PWM_QCH_EXPIRE_VAL, + QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_PERIC1_QCH_ENABLE, + QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, + QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI0_USI_QCH_ENABLE, + QCH_CON_USI0_USI_QCH_CLOCK_REQ, + QCH_CON_USI0_USI_QCH_EXPIRE_VAL, + QCH_CON_USI0_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI10_USI_QCH_ENABLE, + QCH_CON_USI10_USI_QCH_CLOCK_REQ, + QCH_CON_USI10_USI_QCH_EXPIRE_VAL, + QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI11_USI_QCH_ENABLE, + QCH_CON_USI11_USI_QCH_CLOCK_REQ, + QCH_CON_USI11_USI_QCH_EXPIRE_VAL, + QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI12_USI_QCH_ENABLE, + QCH_CON_USI12_USI_QCH_CLOCK_REQ, + QCH_CON_USI12_USI_QCH_EXPIRE_VAL, + QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI13_USI_QCH_ENABLE, + QCH_CON_USI13_USI_QCH_CLOCK_REQ, + QCH_CON_USI13_USI_QCH_EXPIRE_VAL, + QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI15_USI_QCH_ENABLE, + QCH_CON_USI15_USI_QCH_CLOCK_REQ, + QCH_CON_USI15_USI_QCH_EXPIRE_VAL, + QCH_CON_USI15_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI16_USI_QCH_ENABLE, + QCH_CON_USI16_USI_QCH_CLOCK_REQ, + QCH_CON_USI16_USI_QCH_EXPIRE_VAL, + QCH_CON_USI16_USI_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_USI9_USI_QCH_ENABLE, + QCH_CON_USI9_USI_QCH_CLOCK_REQ, + QCH_CON_USI9_USI_QCH_EXPIRE_VAL, + QCH_CON_USI9_USI_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_BIS_S2D_QCH_ENABLE, + DMYQCH_CON_BIS_S2D_QCH_CLOCK_REQ, + DMYQCH_CON_BIS_S2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_S2D_CMU_S2D_QCH_ENABLE, + QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, + QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, + QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_LG_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_TNR_QCH_ENABLE, + QCH_CON_D_TZPC_TNR_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_TNR_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_TNR_QCH_ENABLE, + QCH_CON_GPC_TNR_QCH_CLOCK_REQ, + QCH_CON_GPC_TNR_QCH_EXPIRE_VAL, + QCH_CON_GPC_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_ENABLE, + QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_ENABLE, + QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_CLOCK_REQ, + QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_EXPIRE_VAL, + QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D0_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D0_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D0_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D0_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D1_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D1_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D1_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D1_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D2_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D2_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D2_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D2_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D3_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D3_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D3_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D3_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_D4_TNR_QCH_ENABLE, + QCH_CON_LH_AXI_SI_D4_TNR_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_D4_TNR_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_D4_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D0_TNR_QCH_ENABLE, + QCH_CON_PPMU_D0_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D0_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D0_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D1_TNR_QCH_ENABLE, + QCH_CON_PPMU_D1_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D1_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D1_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D2_TNR_QCH_ENABLE, + QCH_CON_PPMU_D2_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D2_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D2_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D3_TNR_QCH_ENABLE, + QCH_CON_PPMU_D3_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D3_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D3_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D4_TNR_QCH_ENABLE, + QCH_CON_PPMU_D4_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D4_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D4_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D5_TNR_QCH_ENABLE, + QCH_CON_PPMU_D5_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D5_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D5_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D6_TNR_QCH_ENABLE, + QCH_CON_PPMU_D6_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D6_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D6_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D7_TNR_QCH_ENABLE, + QCH_CON_PPMU_D7_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D7_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D7_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_D8_TNR_QCH_ENABLE, + QCH_CON_PPMU_D8_TNR_QCH_CLOCK_REQ, + QCH_CON_PPMU_D8_TNR_QCH_EXPIRE_VAL, + QCH_CON_PPMU_D8_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D0_TNR_QCH_ENABLE, + QCH_CON_QE_D0_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D0_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D0_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D1_TNR_QCH_ENABLE, + QCH_CON_QE_D1_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D1_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D1_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D5_TNR_QCH_ENABLE, + QCH_CON_QE_D5_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D5_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D5_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D6_TNR_QCH_ENABLE, + QCH_CON_QE_D6_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D6_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D6_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D7_TNR_QCH_ENABLE, + QCH_CON_QE_D7_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D7_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D7_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_QE_D8_TNR_QCH_ENABLE, + QCH_CON_QE_D8_TNR_QCH_CLOCK_REQ, + QCH_CON_QE_D8_TNR_QCH_EXPIRE_VAL, + QCH_CON_QE_D8_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_TNR_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_TNR_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_TNR_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D0_TNR_QCH_ENABLE, + QCH_CON_SSMT_D0_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D0_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D0_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D1_TNR_QCH_ENABLE, + QCH_CON_SSMT_D1_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D1_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D1_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D2_TNR_QCH_ENABLE, + QCH_CON_SSMT_D2_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D2_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D2_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D3_TNR_QCH_ENABLE, + QCH_CON_SSMT_D3_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D3_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D3_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D4_TNR_QCH_ENABLE, + QCH_CON_SSMT_D4_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D4_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D4_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D5_TNR_QCH_ENABLE, + QCH_CON_SSMT_D5_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D5_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D5_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D6_TNR_QCH_ENABLE, + QCH_CON_SSMT_D6_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D6_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D6_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D7_TNR_QCH_ENABLE, + QCH_CON_SSMT_D7_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D7_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D7_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_D8_TNR_QCH_ENABLE, + QCH_CON_SSMT_D8_TNR_QCH_CLOCK_REQ, + QCH_CON_SSMT_D8_TNR_QCH_EXPIRE_VAL, + QCH_CON_SSMT_D8_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_TNR_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D0_TNR_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D0_TNR_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_TNR_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D0_TNR_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D0_TNR_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D0_TNR_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D0_TNR_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_TNR_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D1_TNR_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D1_TNR_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_TNR_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D1_TNR_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D1_TNR_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D1_TNR_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D1_TNR_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_TNR_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D2_TNR_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D2_TNR_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_TNR_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D2_TNR_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D2_TNR_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D2_TNR_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D2_TNR_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D3_TNR_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D3_TNR_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D3_TNR_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D3_TNR_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D3_TNR_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D3_TNR_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D3_TNR_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D3_TNR_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D4_TNR_QCH_S1_ENABLE, + QCH_CON_SYSMMU_D4_TNR_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_D4_TNR_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_D4_TNR_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_D4_TNR_QCH_S2_ENABLE, + QCH_CON_SYSMMU_D4_TNR_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_D4_TNR_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_D4_TNR_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_TNR_QCH_ENABLE, + QCH_CON_SYSREG_TNR_QCH_CLOCK_REQ, + QCH_CON_SYSREG_TNR_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TNR_QCH_C2_ENABLE, + QCH_CON_TNR_QCH_C2_CLOCK_REQ, + QCH_CON_TNR_QCH_C2_EXPIRE_VAL, + QCH_CON_TNR_QCH_C2_IGNORE_FORCE_PM_EN, + QCH_CON_TNR_QCH_ACLK_ENABLE, + QCH_CON_TNR_QCH_ACLK_CLOCK_REQ, + QCH_CON_TNR_QCH_ACLK_EXPIRE_VAL, + QCH_CON_TNR_QCH_ACLK_IGNORE_FORCE_PM_EN, + QCH_CON_TNR_CMU_TNR_QCH_ENABLE, + QCH_CON_TNR_CMU_TNR_QCH_CLOCK_REQ, + QCH_CON_TNR_CMU_TNR_QCH_EXPIRE_VAL, + QCH_CON_TNR_CMU_TNR_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_BUSIF_HPMTPU_QCH_ENABLE, + QCH_CON_BUSIF_HPMTPU_QCH_CLOCK_REQ, + QCH_CON_BUSIF_HPMTPU_QCH_EXPIRE_VAL, + QCH_CON_BUSIF_HPMTPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_D_TZPC_TPU_QCH_ENABLE, + QCH_CON_D_TZPC_TPU_QCH_CLOCK_REQ, + QCH_CON_D_TZPC_TPU_QCH_EXPIRE_VAL, + QCH_CON_D_TZPC_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_GPC_TPU_QCH_ENABLE, + QCH_CON_GPC_TPU_QCH_CLOCK_REQ, + QCH_CON_GPC_TPU_QCH_EXPIRE_VAL, + QCH_CON_GPC_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ACEL_SI_D_TPU_QCH_ENABLE, + QCH_CON_LH_ACEL_SI_D_TPU_QCH_CLOCK_REQ, + QCH_CON_LH_ACEL_SI_D_TPU_QCH_EXPIRE_VAL, + QCH_CON_LH_ACEL_SI_D_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_ENABLE, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_CLOCK_REQ, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_EXPIRE_VAL, + QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_ENABLE, + QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_MI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_ENABLE, + QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_CLOCK_REQ, + QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_EXPIRE_VAL, + QCH_CON_LH_AXI_SI_P_TPU_CU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_PPMU_TPU_QCH_ENABLE, + QCH_CON_PPMU_TPU_QCH_CLOCK_REQ, + QCH_CON_PPMU_TPU_QCH_EXPIRE_VAL, + QCH_CON_PPMU_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SLH_AXI_MI_P_TPU_QCH_ENABLE, + QCH_CON_SLH_AXI_MI_P_TPU_QCH_CLOCK_REQ, + QCH_CON_SLH_AXI_MI_P_TPU_QCH_EXPIRE_VAL, + QCH_CON_SLH_AXI_MI_P_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SSMT_TPU_QCH_ENABLE, + QCH_CON_SSMT_TPU_QCH_CLOCK_REQ, + QCH_CON_SSMT_TPU_QCH_EXPIRE_VAL, + QCH_CON_SSMT_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_TPU_QCH_S1_ENABLE, + QCH_CON_SYSMMU_TPU_QCH_S1_CLOCK_REQ, + QCH_CON_SYSMMU_TPU_QCH_S1_EXPIRE_VAL, + QCH_CON_SYSMMU_TPU_QCH_S1_IGNORE_FORCE_PM_EN, + QCH_CON_SYSMMU_TPU_QCH_S2_ENABLE, + QCH_CON_SYSMMU_TPU_QCH_S2_CLOCK_REQ, + QCH_CON_SYSMMU_TPU_QCH_S2_EXPIRE_VAL, + QCH_CON_SYSMMU_TPU_QCH_S2_IGNORE_FORCE_PM_EN, + QCH_CON_SYSREG_TPU_QCH_ENABLE, + QCH_CON_SYSREG_TPU_QCH_CLOCK_REQ, + QCH_CON_SYSREG_TPU_QCH_EXPIRE_VAL, + QCH_CON_SYSREG_TPU_QCH_IGNORE_FORCE_PM_EN, + DMYQCH_CON_TPU_QCH_ENABLE, + DMYQCH_CON_TPU_QCH_CLOCK_REQ, + DMYQCH_CON_TPU_QCH_IGNORE_FORCE_PM_EN, + QCH_CON_TPU_CMU_TPU_QCH_ENABLE, + QCH_CON_TPU_CMU_TPU_QCH_CLOCK_REQ, + QCH_CON_TPU_CMU_TPU_QCH_EXPIRE_VAL, + QCH_CON_TPU_CMU_TPU_QCH_IGNORE_FORCE_PM_EN, + AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + AOC_CMU_AOC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + AUR_CMU_AUR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + BO_CMU_BO_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + BO_CMU_BO_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CMU_CMU_TOP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + CSIS_CMU_CSIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + DISP_CMU_DISP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + DNS_CMU_DNS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + EH_CMU_EH_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + EH_CMU_EH_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + G3AA_CMU_G3AA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + GDC_CMU_GDC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + GSACORE_CMU_GSACORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + GSACTRL_CMU_GSACTRL_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + HSI0_CMU_HSI0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + HSI1_CMU_HSI1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + HSI2_CMU_HSI2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + IPP_CMU_IPP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + ITP_CMU_ITP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + MCSC_CMU_MCSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + MISC_CMU_MISC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL0_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL0_EMBEDDED_CMU_NOCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL0_EMBEDDED_CMU_NOCL01_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL0_EMBEDDED_CMU_NOCL02_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL0_EMBEDDED_CMU_NOCL03_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + PDP_CMU_PDP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + TNR_CMU_TNR_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, + TPU_CMU_TPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING, + end_of_sfr_access, + num_of_sfr_access = end_of_sfr_access - SFR_ACCESS_TYPE, +}; + +#endif diff --git a/drivers/soc/google/cal-if/gs201/cmucal-vclk.c b/drivers/soc/google/cal-if/gs201/cmucal-vclk.c new file mode 100644 index 000000000000..f4485a3f546d --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-vclk.c @@ -0,0 +1,6320 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "../cmucal.h" +#include "cmucal-node.h" +#include "cmucal-vclk.h" +#include "cmucal-vclklut.h" + +/* DVFS VCLK -> Clock Node List */ +enum clk_id cmucal_vclk_vdd_int[] = { + CLKCMU_MFC_MFC, + MUX_CLKCMU_MFC_MFC, + CLKCMU_HSI0_USB31DRD, + CLKCMU_G2D_G2D, + MUX_CLKCMU_G2D_G2D, + CLKCMU_CSIS_NOC, + MUX_CLKCMU_CSIS_NOC, + CLKCMU_ITP_NOC, + MUX_CLKCMU_ITP_NOC, + CLKCMU_G3AA_G3AA, + MUX_CLKCMU_G3AA_G3AA, + CLKCMU_MCSC_ITSC, + MUX_CLKCMU_MCSC_ITSC, + CLKCMU_G2D_MSCL, + MUX_CLKCMU_G2D_MSCL, + CLKCMU_BO_NOC, + MUX_CLKCMU_BO_NOC, + CLKCMU_MISC_NOC, + MUX_CLKCMU_MISC_NOC, + DIV_CLK_CMU_CMUREF, + CLKCMU_MIF_NOCP, + MUX_CLKCMU_MIF_NOCP, + CLKCMU_PDP_VRA, + MUX_CLKCMU_PDP_VRA, + CLKCMU_DPU_NOC, + MUX_CLKCMU_DPU_NOC, + CLKCMU_CPUCL1_SWITCH, + MUX_CLKCMU_CPUCL1_SWITCH, + MUX_CLKCMU_HSI0_NOC, + CLKCMU_IPP_NOC, + MUX_CLKCMU_IPP_NOC, + CLKCMU_TNR_NOC, + MUX_CLKCMU_TNR_NOC, + CLKCMU_NOCL2A_NOC, + MUX_CLKCMU_NOCL2A_NOC, + CLKCMU_NOCL1B_NOC, + MUX_CLKCMU_NOCL1B_NOC, + CLKCMU_DNS_NOC, + MUX_CLKCMU_DNS_NOC, + CLKCMU_GDC_GDC0, + MUX_CLKCMU_GDC_GDC0, + CLKCMU_GDC_GDC1, + MUX_CLKCMU_GDC_GDC1, + CLKCMU_MCSC_MCSC, + MUX_CLKCMU_MCSC_MCSC, + CLKCMU_CPUCL2_SWITCH, + MUX_CLKCMU_CPUCL2_SWITCH, + CLKCMU_GDC_SCSC, + MUX_CLKCMU_GDC_SCSC, + CLKCMU_MISC_SSS, + MUX_CLKCMU_MISC_SSS, + CLKCMU_DISP_NOC, + MUX_CLKCMU_DISP_NOC, + CLKCMU_EH_NOC, + MUX_CLKCMU_EH_NOC, + CLKCMU_PDP_NOC, + MUX_CLKCMU_PDP_NOC, + MUX_CLKCMU_MIF_SWITCH, + PLL_LF_MIF, + CLKCMU_AUR_NOC, + MUX_CLKCMU_AUR_NOC, + CLKCMU_AUR_AURCTL, + MUX_CLKCMU_AUR_AURCTL, + CLKCMU_CPUCL0_SWITCH, + MUX_CLKCMU_CPUCL0_SWITCH, + CLKCMU_CPUCL0_DBG, + MUX_CLKCMU_CPUCL0_DBG, + DIV_CLK_HSI1_NOCP, + CLKCMU_HSI1_NOC, + MUX_CLKCMU_HSI1_NOC, + DIV_CLK_HSI2_NOCP, + CLKCMU_HSI2_NOC, + MUX_CLKCMU_HSI2_NOC, + CLKCMU_NOCL1A_NOC, + MUX_CLKCMU_NOCL1A_NOC, + CLKCMU_CIS_CLK0, + CLKCMU_CIS_CLK1, + CLKCMU_CIS_CLK2, + CLKCMU_CIS_CLK3, + CLKCMU_HSI2_UFS_EMBD, + MUX_CLKCMU_HSI2_UFS_EMBD, + CLKCMU_HSI2_PCIE, + MUX_CLKCMU_HSI2_PCIE, + CLKCMU_PERIC0_IP, + CLKCMU_PERIC1_IP, + CLKCMU_HSI1_PCIE, + MUX_CLKCMU_HSI1_PCIE, + CLKCMU_CIS_CLK4, + MUX_NOCL1A_CMUREF, + DIV_CLKCMU_CMU_BOOST, + CLKCMU_CIS_CLK5, + CLKCMU_CIS_CLK6, + CLKCMU_CIS_CLK7, + CLKCMU_HSI2_MMC_CARD, + MUX_CLKCMU_HSI2_MMC_CARD, +}; +enum clk_id cmucal_vclk_vdd_mif[] = { + PLL_MIF_MAIN, + PLL_MIF_SUB, + DIV_CLK_NOCL0_NOCP, + DIV_CLK_EH_NOCP, + PLL_NOCL0, + MUX_CLK_S2D_CORE, +}; +enum clk_id cmucal_vclk_vdd_g3d[] = { + MUX_CLK_G3D_TOP, + PLL_G3D, + PLL_G3D_L2, +}; +enum clk_id cmucal_vclk_vdd_cam[] = { + PLL_AUR, + DIV_CLK_MFC_NOCP, +}; +enum clk_id cmucal_vclk_vdd_cpucl0[] = { + DIV_CLK_CLUSTER0_ACLK, + PLL_CPUCL0, + MUX_CPUCL0_CMUREF, +}; +enum clk_id cmucal_vclk_vdd_cpucl1[] = { + PLL_CPUCL1, +}; +enum clk_id cmucal_vclk_vdd_tpu[] = { + DIV_CLK_TPU_TPUCTL_DBG, + PLL_TPU, +}; +enum clk_id cmucal_vclk_vdd_cpucl2[] = { + PLL_CPUCL2, +}; +/* SPECIAL VCLK -> Clock Node List */ +enum clk_id cmucal_vclk_mux_cmu_cmuref[] = { + MUX_CMU_CMUREF, + MUX_CLKCMU_TOP_BOOST_OPTION1, + MUX_CLKCMU_TOP_CMUREF, +}; +enum clk_id cmucal_vclk_mux_cpucl1_cmuref[] = { + MUX_CPUCL1_CMUREF, +}; +enum clk_id cmucal_vclk_mux_cpucl2_cmuref[] = { + MUX_CPUCL2_CMUREF, +}; +enum clk_id cmucal_vclk_mux_clk_hsi0_usb20_ref[] = { + MUX_CLK_HSI0_USB20_REF, +}; +enum clk_id cmucal_vclk_mux_clkcmu_hsi0_usbdpdbg[] = { + MUX_CLKCMU_HSI0_USBDPDBG, +}; +enum clk_id cmucal_vclk_mux_mif_cmuref[] = { + MUX_MIF_CMUREF, +}; +enum clk_id cmucal_vclk_mux_nocl0_cmuref[] = { + MUX_NOCL0_CMUREF, +}; +enum clk_id cmucal_vclk_mux_nocl1b_cmuref[] = { + MUX_NOCL1B_CMUREF, +}; +enum clk_id cmucal_vclk_mux_nocl2a_cmuref[] = { + MUX_NOCL2A_CMUREF, +}; +enum clk_id cmucal_vclk_clkcmu_hsi0_dpgtc[] = { + CLKCMU_HSI0_DPGTC, + MUX_CLKCMU_HSI0_DPGTC, +}; +enum clk_id cmucal_vclk_clkcmu_tpu_uart[] = { + CLKCMU_TPU_UART, + MUX_CLKCMU_TPU_UART, +}; +enum clk_id cmucal_vclk_div_clk_apm_usi0_usi[] = { + DIV_CLK_APM_USI0_USI, +}; +enum clk_id cmucal_vclk_div_clk_apm_usi0_uart[] = { + DIV_CLK_APM_USI0_UART, +}; +enum clk_id cmucal_vclk_div_clk_apm_usi1_uart[] = { + DIV_CLK_APM_USI1_UART, +}; +enum clk_id cmucal_vclk_div_clk_apm_i3c_pmic[] = { + DIV_CLK_APM_I3C_PMIC, +}; +enum clk_id cmucal_vclk_clk_aur_add_ch_clk[] = { + CLK_AUR_ADD_CH_CLK, +}; +enum clk_id cmucal_vclk_clkcmu_hpm[] = { + CLKCMU_HPM, + MUX_CLKCMU_HPM, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk0[] = { + MUX_CLKCMU_CIS_CLK0, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk1[] = { + MUX_CLKCMU_CIS_CLK1, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk2[] = { + MUX_CLKCMU_CIS_CLK2, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk3[] = { + MUX_CLKCMU_CIS_CLK3, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk4[] = { + MUX_CLKCMU_CIS_CLK4, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk5[] = { + MUX_CLKCMU_CIS_CLK5, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk6[] = { + MUX_CLKCMU_CIS_CLK6, +}; +enum clk_id cmucal_vclk_mux_clkcmu_cis_clk7[] = { + MUX_CLKCMU_CIS_CLK7, +}; +enum clk_id cmucal_vclk_div_clk_cpucl0_cmuref[] = { + DIV_CLK_CPUCL0_CMUREF, +}; +enum clk_id cmucal_vclk_div_clk_cpucl1_cmuref[] = { + DIV_CLK_CPUCL1_CMUREF, +}; +enum clk_id cmucal_vclk_div_clk_cpucl2_cmuref[] = { + DIV_CLK_CPUCL2_CMUREF, +}; +enum clk_id cmucal_vclk_clk_g3d_add_ch_clk[] = { + CLK_G3D_ADD_CH_CLK, +}; +enum clk_id cmucal_vclk_div_clk_gsacore_spi_fps[] = { + DIV_CLK_GSACORE_SPI_FPS, +}; +enum clk_id cmucal_vclk_div_clk_gsacore_spi_gsc[] = { + DIV_CLK_GSACORE_SPI_GSC, +}; +enum clk_id cmucal_vclk_div_clk_gsacore_uart[] = { + DIV_CLK_GSACORE_UART, +}; +enum clk_id cmucal_vclk_div_clk_slc_dclk[] = { + DIV_CLK_SLC_DCLK, +}; +enum clk_id cmucal_vclk_div_clk_slc1_dclk[] = { + DIV_CLK_SLC1_DCLK, +}; +enum clk_id cmucal_vclk_div_clk_slc2_dclk[] = { + DIV_CLK_SLC2_DCLK, +}; +enum clk_id cmucal_vclk_div_clk_slc3_dclk[] = { + DIV_CLK_SLC3_DCLK, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi6_usi[] = { + DIV_CLK_PERIC0_USI6_USI, + MUX_CLKCMU_PERIC0_USI6_USI_USER, +}; +enum clk_id cmucal_vclk_mux_clkcmu_peric0_ip[] = { + MUX_CLKCMU_PERIC0_IP, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi3_usi[] = { + DIV_CLK_PERIC0_USI3_USI, + MUX_CLKCMU_PERIC0_USI3_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi4_usi[] = { + DIV_CLK_PERIC0_USI4_USI, + MUX_CLKCMU_PERIC0_USI4_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi5_usi[] = { + DIV_CLK_PERIC0_USI5_USI, + MUX_CLKCMU_PERIC0_USI5_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi14_usi[] = { + DIV_CLK_PERIC0_USI14_USI, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi7_usi[] = { + DIV_CLK_PERIC0_USI7_USI, + MUX_CLKCMU_PERIC0_USI7_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi8_usi[] = { + DIV_CLK_PERIC0_USI8_USI, + MUX_CLKCMU_PERIC0_USI8_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi1_usi[] = { + DIV_CLK_PERIC0_USI1_USI, + MUX_CLKCMU_PERIC0_USI1_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi0_uart[] = { + DIV_CLK_PERIC0_USI0_UART, + MUX_CLKCMU_PERIC0_USI0_UART_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric0_usi2_usi[] = { + DIV_CLK_PERIC0_USI2_USI, + MUX_CLKCMU_PERIC0_USI2_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi11_usi[] = { + DIV_CLK_PERIC1_USI11_USI, + MUX_CLKCMU_PERIC1_USI11_USI_USER, +}; +enum clk_id cmucal_vclk_mux_clkcmu_peric1_ip[] = { + MUX_CLKCMU_PERIC1_IP, +}; +enum clk_id cmucal_vclk_div_clk_peric1_i3c[] = { + DIV_CLK_PERIC1_I3C, + MUX_CLKCMU_PERIC1_I3C_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi12_usi[] = { + DIV_CLK_PERIC1_USI12_USI, + MUX_CLKCMU_PERIC1_USI12_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi0_usi[] = { + DIV_CLK_PERIC1_USI0_USI, + MUX_CLKCMU_PERIC1_USI0_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi9_usi[] = { + DIV_CLK_PERIC1_USI9_USI, + MUX_CLKCMU_PERIC1_USI9_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi10_usi[] = { + DIV_CLK_PERIC1_USI10_USI, + MUX_CLKCMU_PERIC1_USI10_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi13_usi[] = { + DIV_CLK_PERIC1_USI13_USI, + MUX_CLKCMU_PERIC1_USI13_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi15_usi[] = { + DIV_CLK_PERIC1_USI15_USI, + MUX_CLKCMU_PERIC1_USI15_USI_USER, +}; +enum clk_id cmucal_vclk_div_clk_peric1_usi16_usi[] = { + DIV_CLK_PERIC1_USI16_USI, + MUX_CLKCMU_PERIC1_USI16_USI_USER, +}; +/* COMMON VCLK -> Clock Node List */ +enum clk_id cmucal_vclk_blk_cmu[] = { + PLL_SHARED0_DIV5, + CLKCMU_TPU_NOC, + MUX_CLKCMU_TPU_NOC, + CLKCMU_G3D_NOCD, + MUX_CLKCMU_G3D_NOCD, + CLKCMU_PERIC0_NOC, + MUX_CLKCMU_PERIC0_NOC, + CLKCMU_HSI0_NOC, + MUX_CLKCMU_CMU_BOOST_OPTION1, + MUX_CLKCMU_CMU_BOOST, + CLKCMU_PERIC1_NOC, + MUX_CLKCMU_PERIC1_NOC, + PLL_SHARED0_DIV4, + PLL_SHARED0_DIV2, + PLL_SHARED0_DIV3, + PLL_SHARED0, + PLL_SHARED1_DIV4, + PLL_SHARED1_DIV2, + PLL_SHARED1_DIV3, + PLL_SHARED1, + MUX_CLKCMU_HSI0_USB31DRD, + PLL_SHARED2_DIV2, + PLL_SHARED2, + PLL_SHARED3_DIV2, + PLL_SHARED3, + PLL_SPARE, +}; +enum clk_id cmucal_vclk_blk_hsi0[] = { + MUX_CLK_HSI0_USB31DRD, + DIV_CLK_HSI0_USB, + PLL_USB, + DIV_CLK_HSI0_NOC_LH, + MUX_CLK_HSI0_NOC, + DIV_CLK_HSI0_USB31DRD, +}; +enum clk_id cmucal_vclk_blk_s2d[] = { + DIV_CLK_S2D_CORE_LH, + PLL_MIF_S2D, +}; +enum clk_id cmucal_vclk_blk_apm[] = { + DIV_CLK_APM_BOOST, + DIV_CLK_APM_NOC_LH, + MUX_CLKCMU_APM_FUNC, + MUX_CLKCMU_APM_FUNCSRC, +}; +enum clk_id cmucal_vclk_blk_cpucl0[] = { + DIV_CLK_CLUSTER0_ATCLK_LH, + DIV_CLK_CLUSTER0_ATCLK, + DIV_CLK_CLUSTER0_PCLKDBG, + DIV_CLK_CLUSTER0_PERIPHCLK, + DIV_CLK_CPUCL0_PCLK_LH, + DIV_CLK_CPUCL0_PCLK, + MUX_CLK_CPUCL0_PLL, + DIV_CLK_CPUCL0_DBG_PCLKDBG, + DIV_CLK_CPUCL0_DBG_NOC_LH, + DIV_CLK_CPUCL0_DBG_NOC, + DIV_CLK_CPUCL0_DBG_ATCLK_LH, +}; +enum clk_id cmucal_vclk_blk_cpucl1[] = { + MUX_CLK_CPUCL1_PLL, +}; +enum clk_id cmucal_vclk_blk_cpucl2[] = { + MUX_CLK_CPUCL2_PLL, +}; +enum clk_id cmucal_vclk_blk_eh[] = { + DIV_CLK_EH_NOCP_LH, + MUX_CLK_EH_NOC, +}; +enum clk_id cmucal_vclk_blk_gsacore[] = { + DIV_CLK_GSACORE_NOCD, + DIV_CLK_GSACORE_NOCP, + DIV_CLK_GSACORE_CPU_LH, + MUX_CLK_GSACORE_CPU_HCH, + DIV_CLK_GSACORE_NOC, +}; +enum clk_id cmucal_vclk_blk_gsactrl[] = { + DIV_CLK_GSACTRL_NOCP_LH, + DIV_CLK_GSACTRL_NOCP, + DIV_CLK_GSACTRL_NOCD, + MUX_CLKCMU_GSA_FUNC, + MUX_CLKCMU_GSA_FUNCSRC, +}; +enum clk_id cmucal_vclk_blk_nocl0[] = { + DIV_CLK_NOCL0_NOCD_LH, + DIV_CLK_NOCL0_NOCP_LH, + MUX_CLK_NOCL0_NOC_OPTION1, +}; +enum clk_id cmucal_vclk_blk_nocl1b[] = { + DIV_CLK_NOCL1B_NOCP_LH, + DIV_CLK_NOCL1B_NOCP, + DIV_CLK_NOCL1B_NOCD_LH, + MUX_CLK_NOCL1B_NOC_OPTION1, +}; +enum clk_id cmucal_vclk_blk_aoc[] = { + DIV_CLK_AOC_NOC_LH, + DIV_CLK_AOC_TRACE_LH, +}; +enum clk_id cmucal_vclk_blk_aur[] = { + DIV_CLK_AUR_NOCP_LH, + DIV_CLK_AUR_NOCP, + DIV_CLK_AUR_AURCTL_LH, +}; +enum clk_id cmucal_vclk_blk_bo[] = { + DIV_CLK_BO_NOCP, +}; +enum clk_id cmucal_vclk_blk_csis[] = { + DIV_CLK_CSIS_NOCP, +}; +enum clk_id cmucal_vclk_blk_disp[] = { + DIV_CLK_DISP_NOCP, +}; +enum clk_id cmucal_vclk_blk_dns[] = { + DIV_CLK_DNS_NOCP, +}; +enum clk_id cmucal_vclk_blk_dpu[] = { + DIV_CLK_DPU_NOCP, +}; +enum clk_id cmucal_vclk_blk_g2d[] = { + DIV_CLK_G2D_NOCP, +}; +enum clk_id cmucal_vclk_blk_g3aa[] = { + DIV_CLK_G3AA_NOCP, +}; +enum clk_id cmucal_vclk_blk_g3d[] = { + DIV_CLK_G3D_NOCP_LH, + DIV_CLK_G3D_NOCP, + DIV_CLK_G3D_TOP, +}; +enum clk_id cmucal_vclk_blk_gdc[] = { + DIV_CLK_GDC_NOCP, +}; +enum clk_id cmucal_vclk_blk_hsi1[] = { + DIV_CLK_HSI1_NOC_LH, +}; +enum clk_id cmucal_vclk_blk_hsi2[] = { + DIV_CLK_HSI2_NOC_LH, +}; +enum clk_id cmucal_vclk_blk_ipp[] = { + DIV_CLK_IPP_NOCP, +}; +enum clk_id cmucal_vclk_blk_itp[] = { + DIV_CLK_ITP_NOCP, +}; +enum clk_id cmucal_vclk_blk_mcsc[] = { + DIV_CLK_MCSC_NOCP, +}; +enum clk_id cmucal_vclk_blk_mif[] = { + DIV_CLK_MIF_NOCP_LH, + DIV_CLK_MIF_NOCD_DBG_LH, +}; +enum clk_id cmucal_vclk_blk_misc[] = { + DIV_CLK_MISC_NOCP_LH, + DIV_CLK_MISC_NOCP, + DIV_CLK_MISC_GIC_LH, + DIV_CLK_MISC_GIC, +}; +enum clk_id cmucal_vclk_blk_nocl1a[] = { + DIV_CLK_NOCL1A_NOCP_LH, + DIV_CLK_NOCL1A_NOCP, + DIV_CLK_NOCL1A_NOCD_LH, +}; +enum clk_id cmucal_vclk_blk_nocl2a[] = { + DIV_CLK_NOCL2A_NOCP_LH, + DIV_CLK_NOCL2A_NOCP, + DIV_CLK_NOCL2A_NOCD_LH, +}; +enum clk_id cmucal_vclk_blk_pdp[] = { + DIV_CLK_PDP_NOCP, +}; +enum clk_id cmucal_vclk_blk_peric0[] = { + DIV_CLK_PERIC0_I3C, + DIV_CLK_PERIC0_NOCP_LH, +}; +enum clk_id cmucal_vclk_blk_peric1[] = { + DIV_CLK_PERIC1_NOCP_LH, +}; +enum clk_id cmucal_vclk_blk_tnr[] = { + DIV_CLK_TNR_NOCP, +}; +enum clk_id cmucal_vclk_blk_tpu[] = { + DIV_CLK_TPU_NOCP_LH, + DIV_CLK_TPU_NOCP, +}; +/* GATE VCLK -> Clock Node List */ +enum clk_id cmucal_vclk_ip_aoc_cmu_aoc[] = { + CLK_BLK_AOC_UID_AOC_CMU_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_baaw_aoc[] = { + GOUT_BLK_AOC_UID_BAAW_AOC_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_aoc[] = { + GOUT_BLK_AOC_UID_D_TZPC_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_aoc[] = { + GOUT_BLK_AOC_UID_GPC_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_hsi0_aoc[] = { + GOUT_BLK_AOC_UID_LH_AXI_MI_LD_HSI0_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_aoc[] = { + GOUT_BLK_AOC_UID_LH_AXI_SI_D_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_aoc[] = { + GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_PPMU_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_usb[] = { + GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_PPMU_USB_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_aoc[] = { + GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_PCLK, + GOUT_BLK_AOC_UID_SSMT_AOC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_aoc[] = { + GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S1, + GOUT_BLK_AOC_UID_SYSMMU_AOC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_aoc[] = { + GOUT_BLK_AOC_UID_SYSREG_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_aoc[] = { + GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_ACLK, + GOUT_BLK_AOC_UID_UASC_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_dp_aoc[] = { + GOUT_BLK_AOC_UID_XIU_DP_AOC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_p_aoc[] = { + GOUT_BLK_AOC_UID_XIU_P_AOC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_aoc_sysctrl_apb[] = { + GOUT_BLK_AOC_UID_AOC_SYSCTRL_APB_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lp0_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_AXI_SI_LP0_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lp0_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_AXI_MI_LP0_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lp1_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_AXI_SI_LP1_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lp1_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_AXI_MI_LP1_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_lp0_aoc[] = { + CLK_BLK_AOC_UID_SLH_AXI_SI_LP0_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_lp1_aoc[] = { + CLK_BLK_AOC_UID_SLH_AXI_SI_LP1_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aoc[] = { + CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_ATB_MI_LT_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_aoc[] = { + CLK_BLK_AOC_UID_SLH_AXI_MI_P_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_aoc_cu[] = { + CLK_BLK_AOC_UID_LH_AXI_SI_P_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_aoc_cu[] = { + CLK_BLK_AOC_UID_LH_AXI_MI_P_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lg_aoc[] = { + CLK_BLK_AOC_UID_SLH_AXI_MI_LG_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aoc_cd[] = { + CLK_BLK_AOC_UID_LH_ATB_SI_LT_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_apm[] = { + GOUT_BLK_APM_UID_LH_AXI_SI_D_APM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_wdt_apm[] = { + GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_apm[] = { + GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_ap[] = { + GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_pmu_alive[] = { + GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_intmem[] = { + GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pmu_intr_gen[] = { + GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_dp_alive[] = { + GOUT_BLK_APM_UID_XIU_DP_ALIVE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_apm_cmu_apm[] = { + CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_grebeintegration[] = { + GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_gpio_alive[] = { + GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_trtc[] = { + GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_apm[] = { + GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_aoc[] = { + GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_dbgcore[] = { + GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_rtc[] = { + GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_gsa[] = { + GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d_apm[] = { + GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_lg_dbgcore[] = { + GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_SSMT_LG_DBGCORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d_apm[] = { + GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_gpc_apm[] = { + GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_apm[] = { + GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_dbgcore[] = { + GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_p_alive[] = { + GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_P_ALIVE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_lp0_aoc[] = { + GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_LP0_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_gpio_far_alive[] = { + GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_rom_crc32_host[] = { + GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ss_dbgcore[] = { + GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_swd[] = { + GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_tpu[] = { + GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ig_swd[] = { + GOUT_BLK_APM_UID_LH_AXI_MI_IG_SWD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_uasc_ig_swd[] = { + GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_ACLK, + GOUT_BLK_APM_UID_UASC_IG_SWD_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apm_usi0_uart[] = { + GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_apm_usi1_uart[] = { + GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_apm_usi0_usi[] = { + GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK, + GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aoca32[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AOCA32_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aocf1[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AOCF1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aocp6[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AOCP6_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aur0[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AUR0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aur1[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AUR1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aur2[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AUR2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_ap_aur3[] = { + CLK_BLK_APM_UID_MAILBOX_AP_AUR3_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apm_i3c_pmic[] = { + CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_PCLK, + CLK_BLK_APM_UID_APM_I3C_PMIC_IPCLKPORT_I_SCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_intcomb_vgpio2pmu[] = { + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2PMU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_intcomb_vgpio2ap[] = { + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2AP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_intcomb_vgpio2apm[] = { + CLK_BLK_APM_UID_APBIF_INTCOMB_VGPIO2APM_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_apm_aur[] = { + CLK_BLK_APM_UID_MAILBOX_APM_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_lg_dbgcore[] = { + CLK_BLK_APM_UID_SLH_AXI_SI_LG_DBGCORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_lg_scan2dram[] = { + CLK_BLK_APM_UID_SLH_AXI_SI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_alive[] = { + CLK_BLK_APM_UID_SLH_AXI_MI_P_ALIVE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lp0_aoc[] = { + CLK_BLK_APM_UID_SLH_AXI_MI_LP0_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_dbgcore_cd[] = { + CLK_BLK_APM_UID_LH_AXI_SI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_dbgcore_cd[] = { + CLK_BLK_APM_UID_LH_AXI_MI_LG_DBGCORE_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_scan2dram_cd[] = { + CLK_BLK_APM_UID_LH_AXI_SI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_scan2dram_cd[] = { + CLK_BLK_APM_UID_LH_AXI_MI_LG_SCAN2DRAM_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lp0_aoc_cu[] = { + CLK_BLK_APM_UID_LH_AXI_SI_LP0_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lp0_aoc_cu[] = { + CLK_BLK_APM_UID_LH_AXI_MI_LP0_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_alive_cu[] = { + CLK_BLK_APM_UID_LH_AXI_SI_P_ALIVE_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_alive_cu[] = { + CLK_BLK_APM_UID_LH_AXI_MI_P_ALIVE_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_aur_cmu_aur[] = { + CLK_BLK_AUR_UID_AUR_CMU_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_aur[] = { + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_CORE_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_PERI_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_TRACE_CLK, + CLK_BLK_AUR_UID_AUR_IPCLKPORT_AURORA_FABRIC_CLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_sysmmu_s1_ns_aur0[] = { + CLK_BLK_AUR_UID_AS_APB_SYSMMU_S1_NS_AUR0_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_aur[] = { + CLK_BLK_AUR_UID_D_TZPC_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_aur[] = { + CLK_BLK_AUR_UID_GPC_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_aur[] = { + CLK_BLK_AUR_UID_LH_AXI_SI_D0_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_aur[] = { + CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_SSMT_D0_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_aur[] = { + CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_SSMT_D1_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_aur[] = { + CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_PPMU_D0_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_aur[] = { + CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_PPMU_D1_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_aur_wp[] = { + CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S1, + CLK_BLK_AUR_UID_SYSMMU_D0_AUR_WP_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_aur_wp[] = { + CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S1, + CLK_BLK_AUR_UID_SYSMMU_D1_AUR_WP_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_aur[] = { + CLK_BLK_AUR_UID_SYSREG_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_aur[] = { + CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_ACLK, + CLK_BLK_AUR_UID_UASC_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_aur[] = { + CLK_BLK_AUR_UID_LH_AXI_SI_D1_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_as_apbm_g_aur[] = { + CLK_BLK_AUR_UID_AS_APBM_G_AUR_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_add_apbif_aur[] = { + CLK_BLK_AUR_UID_ADD_APBIF_AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_baaw_aur[] = { + CLK_BLK_AUR_UID_BAAW_AUR_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0[] = { + CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0_cd[] = { + CLK_BLK_AUR_UID_LH_ATB_SI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0_cd[] = { + CLK_BLK_AUR_UID_LH_ATB_MI_LT_AUR_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_aur_cu[] = { + CLK_BLK_AUR_UID_LH_AXI_SI_P_AUR_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_aur[] = { + CLK_BLK_AUR_UID_SLH_AXI_MI_P_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_aur_cu[] = { + CLK_BLK_AUR_UID_LH_AXI_MI_P_AUR_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_bo_cmu_bo[] = { + CLK_BLK_BO_UID_BO_CMU_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_bo[] = { + GOUT_BLK_BO_UID_LH_AXI_SI_D_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_bo[] = { + GOUT_BLK_BO_UID_SLH_AXI_MI_P_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_bo[] = { + GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_ACLK, + GOUT_BLK_BO_UID_PPMU_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_bo[] = { + GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S1, + GOUT_BLK_BO_UID_SYSMMU_BO_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_as_apb_sysmmu_s1_ns_bo[] = { + GOUT_BLK_BO_UID_AS_APB_SYSMMU_S1_NS_BO_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_sysreg_bo[] = { + GOUT_BLK_BO_UID_SYSREG_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_bo[] = { + GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_PCLK, + GOUT_BLK_BO_UID_SSMT_BO_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_bo[] = { + GOUT_BLK_BO_UID_D_TZPC_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_bo[] = { + GOUT_BLK_BO_UID_GPC_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_bo[] = { + GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_ACLK, + GOUT_BLK_BO_UID_UASC_BO_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_bo[] = { + CLK_BLK_BO_UID_BO_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_bo[] = { + CLK_BLK_BO_UID_LH_AXI_SI_IP_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_bo[] = { + CLK_BLK_BO_UID_LH_AXI_MI_IP_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_hpm_apbif_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_HPM_APBIF_CPUCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_cssys[] = { + GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG, + GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it0_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT0_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it6_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT6_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it1_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT1_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it7_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT7_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it2_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT2_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it3_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT3_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ace_si_d0_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D0_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it0_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT0_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it1_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT1_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it2_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT2_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it3_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT3_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_adm_apb_g_cluster0[] = { + GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_cpucl0_cmu_cpucl0[] = { + CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_cluster0[] = { + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PERIPHCLK, + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_PCLK, + CLK_BLK_CPUCL0_UID_CLUSTER0_IPCLKPORT_ATCLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it4_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT4_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_it5_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_MI_IT5_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ace_si_d1_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_LH_ACE_SI_D1_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it4_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT4_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it5_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT5_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ig_cssys[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_CSSYS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ig_cssys[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_CSSYS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_p_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_hpm_cpucl0_1[] = { + CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C, +}; +enum clk_id cmucal_vclk_ip_hpm_cpucl0_0[] = { + CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C, +}; +enum clk_id cmucal_vclk_ip_apb_async_p_cssys_0[] = { + GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_bps_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it6_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT6_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_GPC_CPUCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ig_dbgcore[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_DBGCORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_dp_cssys[] = { + GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ig_dbgcore[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_DBGCORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_PCLK, + GOUT_BLK_CPUCL0_UID_SSMT_CPUCL0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_s2_cpucl0[] = { + GOUT_BLK_CPUCL0_UID_SYSMMU_S2_CPUCL0_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ig_hsi0[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_apb_async_p_sysmmu[] = { + GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_SYSMMU_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ig_hsi0[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ig_stm[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_SI_IG_STM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_it7_cluster0[] = { + GOUT_BLK_CPUCL0_UID_LH_ATB_SI_IT7_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ig_stm[] = { + GOUT_BLK_CPUCL0_UID_LH_AXI_MI_IG_STM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_g_cssys[] = { + CLK_BLK_CPUCL0_UID_SLH_AXI_SI_G_CSSYS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_g_cssys_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_SI_G_CSSYS_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_g_cssys_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_MI_G_CSSYS_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic[] = { + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_lg_etr_hsi0[] = { + CLK_BLK_CPUCL0_UID_SLH_AXI_SI_LG_ETR_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_etr_hsi0_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_etr_hsi0_cd[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_ETR_HSI0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0[] = { + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lg_dbgcore[] = { + CLK_BLK_CPUCL0_UID_SLH_AXI_MI_LG_DBGCORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_dbgcore_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_SI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_dbgcore_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_MI_LG_DBGCORE_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aoc[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aoc_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aoc_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_AUR_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT_GSA_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_cpucl0[] = { + CLK_BLK_CPUCL0_UID_SLH_AXI_MI_P_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_SI_P_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_AXI_MI_P_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_bdu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_slc[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_bdu_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_BDU_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_bdu_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_BDU_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_slc_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_SI_T_SLC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_slc_cu[] = { + CLK_BLK_CPUCL0_UID_LH_ATB_MI_T_SLC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_cpucl0_con[] = { + CLK_BLK_CPUCL0_UID_CPUCL0_CON_IPCLKPORT_I_PERIPHCLK, +}; +enum clk_id cmucal_vclk_ip_cpucl1[] = { + CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_1, + CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_CK_IN_DD_CTRL_ENYO_0, +}; +enum clk_id cmucal_vclk_ip_cpucl1_cmu_cpucl1[] = { + CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_dd_apbif0_cpucl0[] = { + CLK_BLK_CPUCL1_UID_DD_APBIF0_CPUCL0_IPCLKPORT_CK_IN, +}; +enum clk_id cmucal_vclk_ip_cpucl2_cmu_cpucl2[] = { + CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_cmu_cpucl2_shortstop[] = { + GOUT_BLK_CPUCL2_UID_CMU_CPUCL2_SHORTSTOP_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_cpucl2[] = { + CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_0, + CLK_BLK_CPUCL2_UID_CPUCL2_IPCLKPORT_CK_IN_DD_CTRL_HERA_1, +}; +enum clk_id cmucal_vclk_ip_dd_apbif2_cpucl0[] = { + CLK_BLK_CPUCL2_UID_DD_APBIF2_CPUCL0_IPCLKPORT_CK_IN, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_csis[] = { + GOUT_BLK_CSIS_UID_LH_AXI_SI_D0_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_csis[] = { + GOUT_BLK_CSIS_UID_SLH_AXI_MI_P_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_csis[] = { + GOUT_BLK_CSIS_UID_SYSREG_CSIS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_csis_cmu_csis[] = { + CLK_BLK_CSIS_UID_CSIS_CMU_CSIS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_zotf2_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_mipi_phy_link_wrap[] = { + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS1, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS2, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS3, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS5, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS4, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS6, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS7, + GOUT_BLK_CSIS_UID_MIPI_PHY_LINK_WRAP_IPCLKPORT_ACLK_CSIS0, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_csis[] = { + GOUT_BLK_CSIS_UID_D_TZPC_CSIS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_zotf1_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0[] = { + GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_PCLK, + GOUT_BLK_CSIS_UID_PPMU_D0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_zotf0_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_sotf0_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_sotf1_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_sotf2_ipp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_csis_pdp[] = { + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_csis_pdp[] = { + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf2_csis_pdp[] = { + GOUT_BLK_CSIS_UID_LH_AST_SI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_csis[] = { + GOUT_BLK_CSIS_UID_GPC_CSIS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_csis0[] = { + GOUT_BLK_CSIS_UID_AD_APB_CSIS0_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1[] = { + GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_PPMU_D1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_csis[] = { + GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S2, + GOUT_BLK_CSIS_UID_SYSMMU_D0_CSIS_IPCLKPORT_CLK_S1, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_csis[] = { + GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S1, + GOUT_BLK_CSIS_UID_SYSMMU_D1_CSIS_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1[] = { + GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_SSMT_D1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0[] = { + GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_SSMT_D0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_zsl1[] = { + GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_zsl2[] = { + GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_zsl0[] = { + GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_ZSL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_strp0[] = { + GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d0_csis[] = { + GOUT_BLK_CSIS_UID_XIU_D0_CSIS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d1_csis[] = { + GOUT_BLK_CSIS_UID_XIU_D1_CSIS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_mcsc_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_csis[] = { + GOUT_BLK_CSIS_UID_LH_AXI_SI_D1_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AST_MI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_csis_pdp[] = { + GOUT_BLK_CSIS_UID_LH_AST_SI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_pdp_csis[] = { + GOUT_BLK_CSIS_UID_LH_AXI_MI_LD_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_qe_strp2[] = { + GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_strp1[] = { + GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_STRP1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d2_csis[] = { + GOUT_BLK_CSIS_UID_XIU_D2_CSIS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_csisx8[] = { + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_EBUF, + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_CSIS_DMA, + GOUT_BLK_CSIS_UID_CSISX8_IPCLKPORT_ACLK_C2_CSIS, +}; +enum clk_id cmucal_vclk_ip_qe_csis_dma0[] = { + GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_csis_dma1[] = { + GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_csis_dma2[] = { + GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_csis_dma3[] = { + GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_ACLK, + GOUT_BLK_CSIS_UID_QE_CSIS_DMA3_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_disp_cmu_disp[] = { + CLK_BLK_DISP_UID_DISP_CMU_DISP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_decon_main[] = { + GOUT_BLK_DISP_UID_AD_APB_DECON_MAIN_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_dpub[] = { + GOUT_BLK_DISP_UID_DPUB_IPCLKPORT_ACLK_DECON, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_disp[] = { + CLK_BLK_DISP_UID_SLH_AXI_MI_P_DISP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_disp[] = { + GOUT_BLK_DISP_UID_D_TZPC_DISP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_disp[] = { + GOUT_BLK_DISP_UID_GPC_DISP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_disp[] = { + GOUT_BLK_DISP_UID_SYSREG_DISP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_dns[] = { + GOUT_BLK_DNS_UID_AD_APB_DNS_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_dns[] = { + GOUT_BLK_DNS_UID_D_TZPC_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_dns[] = { + GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK, + GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, + GOUT_BLK_DNS_UID_DNS_IPCLKPORT_I_CLK_C2COM, +}; +enum clk_id cmucal_vclk_ip_gpc_dns[] = { + GOUT_BLK_DNS_UID_GPC_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_dns[] = { + GOUT_BLK_DNS_UID_SLH_AXI_MI_P_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_dns[] = { + GOUT_BLK_DNS_UID_LH_AXI_SI_D_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_dns[] = { + GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_PPMU_D0_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_dns[] = { + GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_SSMT_D0_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_dns[] = { + GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S1, + GOUT_BLK_DNS_UID_SYSMMU_DNS_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_dns[] = { + GOUT_BLK_DNS_UID_SYSREG_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_dns_itp[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_dns_itp[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_dns_mcsc[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_dns_mcsc[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf2_dns_mcsc[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_itp_dns[] = { + GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_dns_gdc[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_ipp_dns[] = { + GOUT_BLK_DNS_UID_LH_AST_MI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_dns_tnr[] = { + GOUT_BLK_DNS_UID_LH_AST_SI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_pdp_dns[] = { + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_PDP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d_dns[] = { + GOUT_BLK_DNS_UID_XIU_D_DNS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_ipp_dns[] = { + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_mcsc_dns[] = { + GOUT_BLK_DNS_UID_LH_AXI_MI_LD_MCSC_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_qe_d0_dns[] = { + GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_ACLK, + GOUT_BLK_DNS_UID_QE_D0_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_ipp_dns[] = { + GOUT_BLK_DNS_UID_LH_AST_MI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_dns_cmu_dns[] = { + CLK_BLK_DNS_UID_DNS_CMU_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_dns[] = { + CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_SSMT_D1_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_dns[] = { + CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_PPMU_D1_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_dns[] = { + CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_ACLK, + CLK_BLK_DNS_UID_QE_D1_DNS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ld_itp_dns[] = { + CLK_BLK_DNS_UID_LH_AXI_MI_LD_ITP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_dpu_cmu_dpu[] = { + CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_dpu[] = { + GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_dpud0[] = { + GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_dpu[] = { + GOUT_BLK_DPU_UID_SLH_AXI_MI_P_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_dpu[] = { + GOUT_BLK_DPU_UID_LH_AXI_SI_D1_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d2_dpu[] = { + GOUT_BLK_DPU_UID_LH_AXI_SI_D2_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_dpud2[] = { + GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_dpud1[] = { + GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1, + GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_dpud0[] = { + GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_dpud1[] = { + GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_dpud2[] = { + GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_dpu[] = { + GOUT_BLK_DPU_UID_LH_AXI_SI_D0_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_dpuf[] = { + GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, + GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_dpu[] = { + GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_dpu_dma[] = { + GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_ssmt_dpu0[] = { + GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_dpu1[] = { + GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_dpu2[] = { + GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, + GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_dpu[] = { + GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_eh_cmu_eh[] = { + CLK_BLK_EH_UID_EH_CMU_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_as_p_sysmmu_s2_eh[] = { + GOUT_BLK_EH_UID_AS_P_SYSMMU_S2_EH_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_eh[] = { + GOUT_BLK_EH_UID_D_TZPC_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_eh[] = { + GOUT_BLK_EH_UID_GPC_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_eh_cu[] = { + GOUT_BLK_EH_UID_LH_AXI_MI_P_EH_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_eh[] = { + GOUT_BLK_EH_UID_LH_ACEL_SI_D_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_eh[] = { + GOUT_BLK_EH_UID_EH_IPCLKPORT_AXI_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_eh[] = { + GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_SSMT_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_eh[] = { + GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_PPMU_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_eh[] = { + GOUT_BLK_EH_UID_SYSMMU_EH_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_eh[] = { + GOUT_BLK_EH_UID_SYSREG_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_eh[] = { + GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_ACLK, + GOUT_BLK_EH_UID_UASC_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_eh[] = { + CLK_BLK_EH_UID_QE_EH_IPCLKPORT_ACLK, + CLK_BLK_EH_UID_QE_EH_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_eh[] = { + CLK_BLK_EH_UID_SLH_AXI_MI_P_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_eh_cu[] = { + CLK_BLK_EH_UID_LH_AXI_SI_P_EH_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_eh[] = { + CLK_BLK_EH_UID_LH_AXI_SI_IP_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_eh[] = { + CLK_BLK_EH_UID_LH_AXI_MI_IP_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_g2d_cmu_g2d[] = { + CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_g2d[] = { + GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D0_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_g2d[] = { + GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D1_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_g2d[] = { + GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_SYSMMU_D0_G2D_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_g2d[] = { + GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_g2d[] = { + GOUT_BLK_G2D_UID_LH_AXI_SI_D0_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_g2d[] = { + GOUT_BLK_G2D_UID_LH_AXI_SI_D1_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d2_g2d[] = { + GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_SYSMMU_D2_G2D_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_d2_g2d[] = { + GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_PPMU_D2_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d2_g2d[] = { + GOUT_BLK_G2D_UID_LH_ACEL_SI_D2_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_g2d[] = { + GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_PCLK, + GOUT_BLK_G2D_UID_SSMT_D0_G2D_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_g2d[] = { + GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_g2d[] = { + GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S1, + GOUT_BLK_G2D_UID_SYSMMU_D1_G2D_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_jpeg[] = { + GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_g2d[] = { + GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_g2d[] = { + GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SSMT_D1_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d2_g2d[] = { + GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_ACLK, + GOUT_BLK_G2D_UID_SSMT_D2_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_g2d[] = { + GOUT_BLK_G2D_UID_GPC_G2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_g2d[] = { + GOUT_BLK_G2D_UID_SLH_AXI_MI_P_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_g2d[] = { + GOUT_BLK_G2D_UID_AS_APB_G2D_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_as_apb_jpeg[] = { + GOUT_BLK_G2D_UID_AS_APB_JPEG_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AXI_SI_D_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_apb_async_top_g3aa[] = { + GOUT_BLK_G3AA_UID_APB_ASYNC_TOP_G3AA_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_sysreg_g3aa[] = { + GOUT_BLK_G3AA_UID_SYSREG_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_g3aa_cmu_g3aa[] = { + CLK_BLK_G3AA_UID_G3AA_CMU_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_g3aa[] = { + GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_ACLK, + GOUT_BLK_G3AA_UID_PPMU_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_g3aa[] = { + GOUT_BLK_G3AA_UID_D_TZPC_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_g3aa[] = { + GOUT_BLK_G3AA_UID_GPC_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_g3aa[] = { + GOUT_BLK_G3AA_UID_G3AA_IPCLKPORT_ACLK_AXIM, +}; +enum clk_id cmucal_vclk_ip_ssmt_g3aa[] = { + GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_ACLK, + GOUT_BLK_G3AA_UID_SSMT_G3AA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_g3aa[] = { + GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S1, + GOUT_BLK_G3AA_UID_SYSMMU_G3AA_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_yotf0_pdp_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AST_MI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_yotf1_pdp_g3aa[] = { + GOUT_BLK_G3AA_UID_LH_AST_MI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_g3aa[] = { + CLK_BLK_G3AA_UID_SLH_AXI_MI_P_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_g3d_cu[] = { + GOUT_BLK_G3D_UID_LH_AXI_MI_P_G3D_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_busif_hpmg3d[] = { + GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_hpm_g3d[] = { + CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, +}; +enum clk_id cmucal_vclk_ip_sysreg_g3d[] = { + GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_g3d_cmu_g3d[] = { + CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_g3d[] = { + GOUT_BLK_G3D_UID_LH_AXI_SI_IP_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpu[] = { + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_STACKS, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK_COREGROUP, + CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_g3d[] = { + GOUT_BLK_G3D_UID_LH_AXI_MI_IP_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gray2bin_g3d[] = { + GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_g3d[] = { + GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_g3d[] = { + GOUT_BLK_G3D_UID_GPC_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_g3d[] = { + GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_ACLK, + GOUT_BLK_G3D_UID_UASC_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_add_apbif_g3d[] = { + GOUT_BLK_G3D_UID_ADD_APBIF_G3D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_add_g3d[] = { + CLK_BLK_G3D_UID_ADD_G3D_IPCLKPORT_CH_CLK, +}; +enum clk_id cmucal_vclk_ip_asb_g3d[] = { + CLK_BLK_G3D_UID_ASB_G3D_IPCLKPORT_CLK_LH, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_g3d[] = { + CLK_BLK_G3D_UID_SLH_AXI_MI_P_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_g3d_cu[] = { + CLK_BLK_G3D_UID_LH_AXI_SI_P_G3D_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_adm_ahb_g_gpu[] = { + CLK_BLK_G3D_UID_ADM_AHB_G_GPU_IPCLKPORT_HCLKM, +}; +enum clk_id cmucal_vclk_ip_gdc_cmu_gdc[] = { + CLK_BLK_GDC_UID_GDC_CMU_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_gdc0[] = { + GOUT_BLK_GDC_UID_AD_APB_GDC0_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_ad_apb_gdc1[] = { + GOUT_BLK_GDC_UID_AD_APB_GDC1_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_ad_apb_scsc[] = { + GOUT_BLK_GDC_UID_AD_APB_SCSC_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_gdc[] = { + GOUT_BLK_GDC_UID_D_TZPC_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gdc0[] = { + GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_GDC0_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_gdc1[] = { + GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_GDC1_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_gdc[] = { + GOUT_BLK_GDC_UID_GPC_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d2_gdc[] = { + GOUT_BLK_GDC_UID_LH_AXI_SI_D2_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_gdc[] = { + GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_PPMU_D0_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_gdc[] = { + GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_PPMU_D1_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_scsc[] = { + GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_CLK, + GOUT_BLK_GDC_UID_SCSC_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_gdc[] = { + GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SSMT_D0_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_gdc[] = { + GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_PCLK, + GOUT_BLK_GDC_UID_SSMT_D1_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_scsc[] = { + GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_SSMT_D0_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d2_gdc[] = { + GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D2_GDC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_gdc[] = { + GOUT_BLK_GDC_UID_SYSREG_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_i_gdc0_gdc1[] = { + GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC0_GDC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_i_gdc1_scsc[] = { + GOUT_BLK_GDC_UID_LH_AST_MI_I_GDC1_SCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_dns_gdc[] = { + GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_DNS_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_tnr_gdc[] = { + GOUT_BLK_GDC_UID_LH_AST_MI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_tnr_gdc[] = { + GOUT_BLK_GDC_UID_LH_AST_MI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_i_gdc0_gdc1[] = { + GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC0_GDC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_i_gdc1_scsc[] = { + GOUT_BLK_GDC_UID_LH_AST_SI_I_GDC1_SCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_gdc_mcsc[] = { + GOUT_BLK_GDC_UID_LH_AST_SI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_gdc[] = { + GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D0_GDC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_gdc[] = { + GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S1, + GOUT_BLK_GDC_UID_SYSMMU_D1_GDC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_gdc[] = { + GOUT_BLK_GDC_UID_LH_AXI_SI_D0_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_scsc[] = { + GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_PPMU_D0_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d2_gdc[] = { + GOUT_BLK_GDC_UID_XIU_D2_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_scsc[] = { + GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_QE_D1_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d0_scsc[] = { + GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_ACLK, + GOUT_BLK_GDC_UID_QE_D0_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_gdc[] = { + GOUT_BLK_GDC_UID_SLH_AXI_MI_P_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_gdc[] = { + GOUT_BLK_GDC_UID_LH_AXI_SI_D1_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d0_gdc[] = { + CLK_BLK_GDC_UID_XIU_D0_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d1_gdc[] = { + CLK_BLK_GDC_UID_XIU_D1_GDC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d2_gdc[] = { + CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D2_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d3_gdc[] = { + CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D3_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_scsc[] = { + CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D1_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d2_scsc[] = { + CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_PPMU_D2_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d2_gdc[] = { + CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D2_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d3_gdc[] = { + CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D3_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_scsc[] = { + CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D1_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d2_scsc[] = { + CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_SSMT_D2_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d0_gdc[] = { + CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D0_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_gdc[] = { + CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D1_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d2_gdc[] = { + CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D2_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d2_scsc[] = { + CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D2_SCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d3_gdc[] = { + CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_ACLK, + CLK_BLK_GDC_UID_QE_D3_GDC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_id_scsc_gdc1[] = { + CLK_BLK_GDC_UID_LH_AXI_MI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_id_scsc_gdc1[] = { + CLK_BLK_GDC_UID_LH_AXI_SI_ID_SCSC_GDC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gsacore_cmu_gsacore[] = { + CLK_BLK_GSACORE_UID_GSACORE_CMU_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ca32_gsacore[] = { + GOUT_BLK_GSACORE_UID_CA32_GSACORE_IPCLKPORT_CLKIN, +}; +enum clk_id cmucal_vclk_ip_gpio_gsacore[] = { + GOUT_BLK_GSACORE_UID_GPIO_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_kdn_gsacore[] = { + GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_KDN_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_otp_con_gsacore[] = { + GOUT_BLK_GSACORE_UID_OTP_CON_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_gsacore[] = { + GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_PPMU_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_ca32_gsacore[] = { + GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_CA32_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_dma_gsacore[] = { + GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_DMA_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_sss_gsacore[] = { + GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_QE_SSS_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_resetmon_gsacore[] = { + GOUT_BLK_GSACORE_UID_RESETMON_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_spi_fps_gsacore[] = { + GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SPI_FPS_GSACORE_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_spi_gsc_gsacore[] = { + GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SPI_GSC_GSACORE_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_gsacore[] = { + GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_SSMT_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sss_gsacore[] = { + GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_PCLK, + GOUT_BLK_GSACORE_UID_SSS_GSACORE_IPCLKPORT_I_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_gsacore[] = { + GOUT_BLK_GSACORE_UID_SYSREG_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uart_gsacore[] = { + GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_PCLK, + GOUT_BLK_GSACORE_UID_UART_GSACORE_IPCLKPORT_IPCLK, +}; +enum clk_id cmucal_vclk_ip_wdt_gsacore[] = { + GOUT_BLK_GSACORE_UID_WDT_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_baaw_gsacore[] = { + GOUT_BLK_GSACORE_UID_BAAW_GSACORE_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_intmem_gsacore[] = { + GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_ACLK, + GOUT_BLK_GSACORE_UID_INTMEM_GSACORE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_gsa[] = { + GOUT_BLK_GSACORE_UID_LH_AXI_SI_D_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_gsa[] = { + GOUT_BLK_GSACORE_UID_LH_AXI_SI_IP_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_dma_gsacore[] = { + GOUT_BLK_GSACORE_UID_DMA_GSACORE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_gsacore[] = { + GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S1, + GOUT_BLK_GSACORE_UID_SYSMMU_GSACORE_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ad_apb_dma_gsacore_ns[] = { + GOUT_BLK_GSACORE_UID_AD_APB_DMA_GSACORE_NS_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_puf_gsacore[] = { + GOUT_BLK_GSACORE_UID_PUF_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_dp0_gsa_wp[] = { + GOUT_BLK_GSACORE_UID_XIU_DP0_GSA_WP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_i_dap_gsa[] = { + GOUT_BLK_GSACORE_UID_LH_AXI_MI_I_DAP_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ugme[] = { + GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_AXI, + GOUT_BLK_GSACORE_UID_UGME_IPCLKPORT_CLK_APB, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_i_ca32_gic[] = { + GOUT_BLK_GSACORE_UID_LH_AST_MI_I_CA32_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_i_gic_ca32[] = { + GOUT_BLK_GSACORE_UID_LH_AST_MI_I_GIC_CA32_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_udap_sss_ahb_async[] = { + GOUT_BLK_GSACORE_UID_UDAP_SSS_AHB_ASYNC_IPCLKPORT_HCLKM, +}; +enum clk_id cmucal_vclk_ip_ad_apb_sysmmu_gsacore_ns[] = { + CLK_BLK_GSACORE_UID_AD_APB_SYSMMU_GSACORE_NS_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_gic_gsacore[] = { + CLK_BLK_GSACORE_UID_GIC_GSACORE_IPCLKPORT_GICCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_i_gic_ca32[] = { + GOUT_BLK_GSACORE_UID_LH_AST_SI_I_GIC_CA32_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_i_ca32_gic[] = { + GOUT_BLK_GSACORE_UID_LH_AST_SI_I_CA32_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0_cd[] = { + CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0[] = { + CLK_BLK_GSACORE_UID_LH_ATB_SI_LT_GSA_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0_cd[] = { + CLK_BLK_GSACORE_UID_LH_ATB_MI_LT_GSA_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_axi2apb1_gsacore[] = { + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_axi2apb1_gsacore[] = { + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB1_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_axi2apb2_gsacore[] = { + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_axi2apb2_gsacore[] = { + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_AXI2APB2_GSACORE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_gme[] = { + CLK_BLK_GSACORE_UID_LH_AXI_SI_IP_GME_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_gme[] = { + CLK_BLK_GSACORE_UID_LH_AXI_MI_IP_GME_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_intmem_gsacore[] = { + CLK_BLK_GSACORE_UID_AD_APB_INTMEM_GSACORE_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_gsactrl_cmu_gsactrl[] = { + CLK_BLK_GSACTRL_UID_GSACTRL_CMU_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_GPC_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_gsa2aoc[] = { + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_gsa2nontz[] = { + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2NONTZ_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_gsa2tpu[] = { + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_gsa2aur[] = { + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2AUR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_tzpc_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_TZPC_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_intmem_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_ACLK, + GOUT_BLK_GSACTRL_UID_INTMEM_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_gsa[] = { + GOUT_BLK_GSACTRL_UID_LH_AXI_MI_IP_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_mailbox_gsa2tz[] = { + GOUT_BLK_GSACTRL_UID_MAILBOX_GSA2TZ_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pmu_gsa[] = { + GOUT_BLK_GSACTRL_UID_PMU_GSA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbif_gpio_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_APBIF_GPIO_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_timer_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_TIMER_GSACTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_dap_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_DAP_GSACTRL_IPCLKPORT_DAPCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_gsa_cu[] = { + GOUT_BLK_GSACTRL_UID_LH_AXI_MI_P_GSA_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_gsactrlext[] = { + GOUT_BLK_GSACTRL_UID_SYSREG_GSACTRLEXT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_secjtag_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_SECJTAG_GSACTRL_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_i_dap_gsa[] = { + GOUT_BLK_GSACTRL_UID_LH_AXI_SI_I_DAP_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_intmem_gsactrl[] = { + GOUT_BLK_GSACTRL_UID_AD_APB_INTMEM_GSACTRL_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_gsa[] = { + CLK_BLK_GSACTRL_UID_SLH_AXI_MI_P_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_gsa_cu[] = { + CLK_BLK_GSACTRL_UID_LH_AXI_SI_P_GSA_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ip_axi2apb0_gsactrl[] = { + CLK_BLK_GSACTRL_UID_LH_AXI_SI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_ip_axi2apb0_gsactrl[] = { + CLK_BLK_GSACTRL_UID_LH_AXI_MI_IP_AXI2APB0_GSACTRL_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_dp1_gsa_wp[] = { + CLK_BLK_GSACTRL_UID_XIU_DP1_GSA_WP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_hsi0_cmu_hsi0[] = { + CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usb31drd[] = { + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK, + GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK, + CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26, +}; +enum clk_id cmucal_vclk_ip_dp_link[] = { + GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK, + GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d0_hsi0[] = { + GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_etr_miu[] = { + GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_hsi0_nocl1b[] = { + GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_hsi0_aoc[] = { + GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_hsi0_aoc[] = { + GOUT_BLK_HSI0_UID_LH_AXI_SI_LD_HSI0_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_hsi0[] = { + GOUT_BLK_HSI0_UID_LH_ACEL_SI_D_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_hsi0[] = { + GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_hsi0[] = { + GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_usb[] = { + GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK, + GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_usb[] = { + GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2, + CLK_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S1, +}; +enum clk_id cmucal_vclk_ip_sysreg_hsi0[] = { + GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_p_hsi0[] = { + GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d1_hsi0[] = { + GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_uasc_hsi0_ctrl[] = { + GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_hsi0_link[] = { + GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK, + GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lg_etr_hsi0[] = { + CLK_BLK_HSI0_UID_SLH_AXI_MI_LG_ETR_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lp1_aoc[] = { + CLK_BLK_HSI0_UID_SLH_AXI_MI_LP1_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_hsi0[] = { + CLK_BLK_HSI0_UID_SLH_AXI_MI_P_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_etr_hsi0_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_SI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_etr_hsi0_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_MI_LG_ETR_HSI0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lp1_aoc_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_SI_LP1_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lp1_aoc_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_MI_LP1_AOC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi0_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_SI_P_HSI0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi0_cu[] = { + CLK_BLK_HSI0_UID_LH_AXI_MI_P_HSI0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_hsi1_cmu_hsi1[] = { + CLK_BLK_HSI1_UID_HSI1_CMU_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_hsi1[] = { + GOUT_BLK_HSI1_UID_LH_ACEL_SI_D_HSI1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi1_cu[] = { + GOUT_BLK_HSI1_UID_LH_AXI_MI_P_HSI1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_hsi1[] = { + GOUT_BLK_HSI1_UID_SYSREG_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d_hsi1[] = { + GOUT_BLK_HSI1_UID_XIU_D_HSI1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_hsi1[] = { + GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_PPMU_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_hsi1[] = { + GOUT_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S2, + CLK_BLK_HSI1_UID_SYSMMU_HSI1_IPCLKPORT_CLK_S1, +}; +enum clk_id cmucal_vclk_ip_xiu_p_hsi1[] = { + GOUT_BLK_HSI1_UID_XIU_P_HSI1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_pcie_gen4_0[] = { + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + GOUT_BLK_HSI1_UID_PCIE_GEN4_0_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, +}; +enum clk_id cmucal_vclk_ip_pcie_ia_gen4a_0[] = { + GOUT_BLK_HSI1_UID_PCIE_IA_GEN4A_0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_pcie_ia_gen4b_0[] = { + GOUT_BLK_HSI1_UID_PCIE_IA_GEN4B_0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_hsi1[] = { + GOUT_BLK_HSI1_UID_D_TZPC_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_hsi1[] = { + GOUT_BLK_HSI1_UID_GPC_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_hsi1[] = { + GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_SSMT_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpio_hsi1[] = { + GOUT_BLK_HSI1_UID_GPIO_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pcie_gen4a_hsi1[] = { + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4A_HSI1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pcie_gen4b_hsi1[] = { + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_PCLK, + GOUT_BLK_HSI1_UID_QE_PCIE_GEN4B_HSI1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4a_dbi_0[] = { + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_DBI_0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4a_slv_0[] = { + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4A_SLV_0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4b_dbi_0[] = { + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_DBI_0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4b_slv_0[] = { + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_ACLK, + GOUT_BLK_HSI1_UID_UASC_PCIE_GEN4B_SLV_0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pcie_ia_gen4a_0[] = { + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_PCLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4A_0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pcie_ia_gen4b_0[] = { + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_ACLK, + CLK_BLK_HSI1_UID_SSMT_PCIE_IA_GEN4B_0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_pciephy_hsi1[] = { + GOUT_BLK_HSI1_UID_AS_APB_PCIEPHY_HSI1_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_hsi1[] = { + CLK_BLK_HSI1_UID_SLH_AXI_MI_P_HSI1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi1_cu[] = { + CLK_BLK_HSI1_UID_LH_AXI_SI_P_HSI1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_hsi2_cmu_hsi2[] = { + GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_hsi2[] = { + GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpio_hsi2[] = { + GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_hsi2[] = { + GOUT_BLK_HSI2_UID_LH_ACEL_SI_D_HSI2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi2_cu[] = { + GOUT_BLK_HSI2_UID_LH_AXI_MI_P_HSI2_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d_hsi2[] = { + GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_p_hsi2[] = { + GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_hsi2[] = { + GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pcie_gen4_1[] = { + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK, + GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_hsi2[] = { + GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2, + CLK_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S1, +}; +enum clk_id cmucal_vclk_ip_ssmt_hsi2[] = { + GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pcie_ia_gen4a_1[] = { + GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_hsi2[] = { + GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ufs_embd[] = { + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, + GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, +}; +enum clk_id cmucal_vclk_ip_pcie_ia_gen4b_1[] = { + GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_hsi2[] = { + GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mmc_card[] = { + GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK, + GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN, +}; +enum clk_id cmucal_vclk_ip_qe_pcie_gen4a_hsi2[] = { + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pcie_gen4b_hsi2[] = { + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_ufs_embd_hsi2[] = { + GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4a_dbi_1[] = { + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4a_slv_1[] = { + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4b_dbi_1[] = { + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_uasc_pcie_gen4b_slv_1[] = { + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_mmc_card_hsi2[] = { + GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK, + GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pcie_ia_gen4a_1[] = { + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pcie_ia_gen4b_1[] = { + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK, + CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_pciephy_hsi2[] = { + GOUT_BLK_HSI2_UID_AS_APB_PCIEPHY_HSI2_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_gpio_hsi2ufs[] = { + CLK_BLK_HSI2_UID_GPIO_HSI2UFS_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_hsi2[] = { + CLK_BLK_HSI2_UID_SLH_AXI_MI_P_HSI2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi2_cu[] = { + CLK_BLK_HSI2_UID_LH_AXI_SI_P_HSI2_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ipp_cmu_ipp[] = { + CLK_BLK_IPP_UID_IPP_CMU_IPP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_ipp[] = { + GOUT_BLK_IPP_UID_D_TZPC_IPP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_ipp[] = { + GOUT_BLK_IPP_UID_SLH_AXI_MI_P_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_ipp[] = { + GOUT_BLK_IPP_UID_SYSREG_IPP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_ipp_dns[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_VO_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_pdp_ipp[] = { + GOUT_BLK_IPP_UID_LH_AST_MI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_ipp[] = { + GOUT_BLK_IPP_UID_AD_APB_IPP_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d_ipp[] = { + GOUT_BLK_IPP_UID_LH_AXI_SI_D_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_sotf0_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF0_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_sotf1_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF1_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_sotf2_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_SOTF2_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_zotf0_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF0_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_zotf1_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF1_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_zotf2_ipp_csis[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_ZOTF2_IPP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_ipp[] = { + GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_PPMU_IPP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sipu_ipp[] = { + GOUT_BLK_IPP_UID_SIPU_IPP_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_ipp[] = { + GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S1, + GOUT_BLK_IPP_UID_SYSMMU_IPP_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_gpc_ipp[] = { + GOUT_BLK_IPP_UID_GPC_IPP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_thstat[] = { + GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_THSTAT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_ipp_dns[] = { + GOUT_BLK_IPP_UID_LH_AXI_SI_LD_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_msa[] = { + GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_PPMU_MSA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_align0[] = { + GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_align1[] = { + GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_align0[] = { + GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_align1[] = { + GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d1_ipp[] = { + GOUT_BLK_IPP_UID_XIU_D1_IPP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_tnr_a[] = { + GOUT_BLK_IPP_UID_TNR_A_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_thstat[] = { + GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_THSTAT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_ipp[] = { + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_ipp[] = { + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_ipp[] = { + GOUT_BLK_IPP_UID_LH_AST_MI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_ipp_dns[] = { + GOUT_BLK_IPP_UID_LH_AST_SI_L_OTF_IPP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d2_ipp[] = { + GOUT_BLK_IPP_UID_XIU_D2_IPP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d0_ipp[] = { + GOUT_BLK_IPP_UID_XIU_D0_IPP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_fdpig[] = { + GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_FDPIG_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_rgbh0[] = { + GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_RGBH0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_rgbh1[] = { + GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_RGBH1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_rgbh2[] = { + GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_RGBH2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_align2[] = { + GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_align3[] = { + GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALIGN3_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_fdpig[] = { + GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_FDPIG_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_rgbh0[] = { + GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_rgbh1[] = { + GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_rgbh2[] = { + GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_RGBH2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_align2[] = { + GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_align3[] = { + GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_ALIGN3_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_tnr_msa0[] = { + GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_aln_stat[] = { + GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_SSMT_ALN_STAT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_tnr_msa0[] = { + GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_aln_stat[] = { + GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_QE_ALN_STAT_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_tnr_msa1[] = { + GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_PCLK, + GOUT_BLK_IPP_UID_SSMT_TNR_MSA1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_tnr_msa1[] = { + GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_ACLK, + GOUT_BLK_IPP_UID_QE_TNR_MSA1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_itp_cmu_itp[] = { + CLK_BLK_ITP_UID_ITP_CMU_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_itp[] = { + GOUT_BLK_ITP_UID_AD_APB_ITP_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_itp[] = { + GOUT_BLK_ITP_UID_D_TZPC_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_itp[] = { + GOUT_BLK_ITP_UID_GPC_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_itp[] = { + GOUT_BLK_ITP_UID_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_itp[] = { + GOUT_BLK_ITP_UID_SLH_AXI_MI_P_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_itp[] = { + GOUT_BLK_ITP_UID_SYSREG_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_dns_itp[] = { + GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF0_DNS_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_dns_itp[] = { + GOUT_BLK_ITP_UID_LH_AST_MI_L_OTF1_DNS_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_itp_dns[] = { + GOUT_BLK_ITP_UID_LH_AST_SI_L_OTF_ITP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_itp[] = { + CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_SSMT_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_itp[] = { + CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_QE_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_itp[] = { + CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_ACLK, + CLK_BLK_ITP_UID_PPMU_ITP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_itp_dns[] = { + CLK_BLK_ITP_UID_LH_AXI_SI_LD_ITP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_mcsc[] = { + GOUT_BLK_MCSC_UID_SLH_AXI_MI_P_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AXI_SI_D0_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_mcsc[] = { + GOUT_BLK_MCSC_UID_SYSREG_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mcsc_cmu_mcsc[] = { + CLK_BLK_MCSC_UID_MCSC_CMU_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_dns_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF0_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_mcsc[] = { + GOUT_BLK_MCSC_UID_D_TZPC_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_mcsc_tnr[] = { + GOUT_BLK_MCSC_UID_LH_AST_SI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_dns_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF1_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_mcsc[] = { + GOUT_BLK_MCSC_UID_GPC_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_itsc[] = { + GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_ITSC_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_mcsc[] = { + GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_SSMT_D0_MCSC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_mcsc[] = { + GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_SYSMMU_D0_MCSC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_mcsc[] = { + GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_PCLK, + GOUT_BLK_MCSC_UID_PPMU_D0_MCSC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_itsc[] = { + GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D0_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_itsc[] = { + GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D1_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_itsc[] = { + GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D0_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_gdc_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_L_VO_GDC_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_mcsc_dns[] = { + GOUT_BLK_MCSC_UID_LH_AXI_SI_LD_MCSC_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_itsc[] = { + GOUT_BLK_MCSC_UID_AD_APB_ITSC_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_ad_apb_mcsc[] = { + GOUT_BLK_MCSC_UID_AD_APB_MCSC_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_mcsc[] = { + GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_CLK, + GOUT_BLK_MCSC_UID_MCSC_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AXI_SI_D1_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_mcsc[] = { + GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_SYSMMU_D1_MCSC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf2_dns_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF2_DNS_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_i_itsc_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_I_ITSC_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_tnr_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_MI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_i_itsc_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AST_SI_I_ITSC_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_mcsc_csis[] = { + GOUT_BLK_MCSC_UID_LH_AST_SI_L_VO_MCSC_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_itsc[] = { + GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D1_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_mcsc[] = { + GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_PPMU_D1_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_mcsc[] = { + GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_SSMT_D1_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_itsc[] = { + GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D1_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d2_itsc[] = { + GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D2_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d0_mcsc[] = { + GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D0_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_mcsc[] = { + GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D1_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d2_mcsc[] = { + GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D2_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d3_mcsc[] = { + GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D3_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d2_mcsc[] = { + GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S1, + GOUT_BLK_MCSC_UID_SYSMMU_D2_MCSC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d2_mcsc[] = { + GOUT_BLK_MCSC_UID_LH_AXI_SI_D2_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_qe_d4_mcsc[] = { + GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_ACLK, + GOUT_BLK_MCSC_UID_QE_D4_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_c2r_mcsc[] = { + GOUT_BLK_MCSC_UID_C2R_MCSC_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_qe_d3_itsc[] = { + CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_ACLK, + CLK_BLK_MCSC_UID_QE_D3_ITSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d5_mcsc[] = { + CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_ACLK, + CLK_BLK_MCSC_UID_QE_D5_MCSC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mfc_cmu_mfc[] = { + CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_mfc[] = { + GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_sysreg_mfc[] = { + GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_mfc[] = { + GOUT_BLK_MFC_UID_LH_AXI_SI_D0_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_mfc[] = { + GOUT_BLK_MFC_UID_LH_AXI_SI_D1_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_mfc[] = { + GOUT_BLK_MFC_UID_SLH_AXI_MI_P_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_mfc[] = { + GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S1, + GOUT_BLK_MFC_UID_SYSMMU_D0_MFC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_mfc[] = { + GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S1, + GOUT_BLK_MFC_UID_SYSMMU_D1_MFC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_mfc[] = { + GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_PPMU_D0_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_mfc[] = { + GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_PPMU_D1_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_mfc[] = { + GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_PCLK, + GOUT_BLK_MFC_UID_SSMT_D0_MFC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_mfc[] = { + GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_mfc[] = { + GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_mfc[] = { + GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_ACLK, + GOUT_BLK_MFC_UID_SSMT_D1_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_mfc[] = { + GOUT_BLK_MFC_UID_GPC_MFC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_mif_cmu_mif[] = { + CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ddrphy[] = { + GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_mif[] = { + GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_mif_cu[] = { + GOUT_BLK_MIF_UID_LH_AXI_MI_P_MIF_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_axi2apb_p_mif[] = { + GOUT_BLK_MIF_UID_AXI2APB_P_MIF_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_apbbr_ddrphy[] = { + GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_apbbr_dmc[] = { + GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_dmc[] = { + GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qch_adapter_ppc_debug[] = { + GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_mif[] = { + GOUT_BLK_MIF_UID_GPC_MIF_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_mif[] = { + GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_debug[] = { + CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_gen_wren_secure[] = { + GOUT_BLK_MIF_UID_GEN_WREN_SECURE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc_cd[] = { + CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_mif[] = { + CLK_BLK_MIF_UID_SLH_AXI_MI_P_MIF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_mif_cu[] = { + CLK_BLK_MIF_UID_LH_AXI_SI_P_MIF_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc[] = { + CLK_BLK_MIF_UID_LH_AST_SI_G_DMC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc_cd[] = { + CLK_BLK_MIF_UID_LH_AST_MI_G_DMC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_misc[] = { + GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_wdt_cluster1[] = { + GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_wdt_cluster0[] = { + GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_otp_con_bira[] = { + GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK, +}; +enum clk_id cmucal_vclk_ip_gic[] = { + GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK, +}; +enum clk_id cmucal_vclk_ip_mct[] = { + GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_otp_con_top[] = { + GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_misc[] = { + GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_tmu_sub[] = { + GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_tmu_top[] = { + GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_otp_con_bisr[] = { + CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK, + GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_dit[] = { + GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_misc_cu[] = { + GOUT_BLK_MISC_UID_LH_AXI_MI_P_MISC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_misc[] = { + GOUT_BLK_MISC_UID_LH_ACEL_SI_D_MISC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_pdma0[] = { + GOUT_BLK_MISC_UID_PDMA0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_misc[] = { + GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_dit[] = { + GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdma0[] = { + GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_PDMA0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_misc_cmu_misc[] = { + CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_rtic[] = { + GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_spdma0[] = { + GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_QE_SPDMA0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_sss[] = { + GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_rtic[] = { + GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK, + GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_spdma0[] = { + GOUT_BLK_MISC_UID_SPDMA0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sss[] = { + GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK, + GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_sss[] = { + GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK, + GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_gpc_misc[] = { + GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_dit[] = { + GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_adm_ahb_g_sss[] = { + GOUT_BLK_MISC_UID_ADM_AHB_G_SSS_IPCLKPORT_HCLKM, +}; +enum clk_id cmucal_vclk_ip_ad_apb_puf[] = { + GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic_cu[] = { + GOUT_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_id_sss[] = { + GOUT_BLK_MISC_UID_LH_AXI_MI_ID_SSS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0_cd[] = { + GOUT_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_id_sss[] = { + GOUT_BLK_MISC_UID_LH_AXI_SI_ID_SSS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_puf[] = { + GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d_misc[] = { + GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_misc[] = { + GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_sss[] = { + GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_gic_cu[] = { + GOUT_BLK_MISC_UID_LH_AXI_MI_P_GIC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_rtic[] = { + GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_spdma0[] = { + GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_SPDMA0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pdma0[] = { + GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_PDMA0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_dit[] = { + GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK, + GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0_cd[] = { + CLK_BLK_MISC_UID_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0[] = { + CLK_BLK_MISC_UID_LH_AST_SI_L_IRI_GIC_CLUSTER0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic[] = { + CLK_BLK_MISC_UID_LH_AST_MI_L_ICC_CLUSTER0_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic_cu[] = { + CLK_BLK_MISC_UID_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_misc[] = { + CLK_BLK_MISC_UID_SLH_AXI_MI_P_MISC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_misc_cu[] = { + CLK_BLK_MISC_UID_LH_AXI_SI_P_MISC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_spdma1[] = { + CLK_BLK_MISC_UID_SPDMA1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdma1[] = { + CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_PCLK, + CLK_BLK_MISC_UID_QE_PDMA1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_spdma1[] = { + CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_QE_SPDMA1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pdma1[] = { + CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_SSMT_PDMA1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_spdma1[] = { + CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_ACLK, + CLK_BLK_MISC_UID_SSMT_SPDMA1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pdma1[] = { + CLK_BLK_MISC_UID_PDMA1_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_gic[] = { + CLK_BLK_MISC_UID_SLH_AXI_MI_P_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_gic_cu[] = { + CLK_BLK_MISC_UID_LH_AXI_SI_P_GIC_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_nocl0_cmu_nocl0[] = { + CLK_BLK_NOCL0_UID_NOCL0_CMU_NOCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_nocl0[] = { + GOUT_BLK_NOCL0_UID_SYSREG_NOCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_trex_p_nocl0[] = { + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_D_NOCL0, + GOUT_BLK_NOCL0_UID_TREX_P_NOCL0_IPCLKPORT_ACLK_P_NOCL0, +}; +enum clk_id cmucal_vclk_ip_lh_ace_mi_d0_cpucl0[] = { + GOUT_BLK_NOCL0_UID_LH_ACE_MI_D0_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ace_mi_d1_cpucl0[] = { + GOUT_BLK_NOCL0_UID_LH_ACE_MI_D1_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_trex_d_nocl0[] = { + GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_TREX_D_NOCL0_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_cci[] = { + GOUT_BLK_NOCL0_UID_AD_APB_CCI_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_nocl0[] = { + GOUT_BLK_NOCL0_UID_D_TZPC_NOCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_bdu[] = { + GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_CLK, + GOUT_BLK_NOCL0_UID_BDU_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_nocl0[] = { + GOUT_BLK_NOCL0_UID_GPC_NOCL0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_ace_cpucl0_d0[] = { + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_ace_cpucl0_d1[] = { + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPMU_ACE_CPUCL0_D1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sfr_apbif_cmu_topc[] = { + GOUT_BLK_NOCL0_UID_SFR_APBIF_CMU_TOPC_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1a_m0_event[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1a_m1_event[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M1_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1a_m2_event[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M2_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1a_m3_event[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M3_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1b_m0_event[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cpucl0_d0_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_CPUCL0_D0_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_slc_cb_top[] = { + GOUT_BLK_NOCL0_UID_SLC_CB_TOP_IPCLKPORT_I_ACLK, +}; +enum clk_id cmucal_vclk_ip_cci[] = { + GOUT_BLK_NOCL0_UID_CCI_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_eh[] = { + GOUT_BLK_NOCL0_UID_LH_ACEL_MI_D_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppc_eh_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_EH_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_io_event[] = { + GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_IO_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_eh_event[] = { + GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_EH_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cpucl0_d0_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D0_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cci_m1_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cci_m2_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M2_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cci_m3_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M3_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cci_m4_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL0_UID_PPC_CCI_M4_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_io_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_IO_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cci_m1_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_CCI_M1_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1a_m0_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_NOCL1A_M0_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl1b_m0_cycle[] = { + GOUT_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL0_UID_PPC_NOCL1B_M0_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_dbg_cc[] = { + GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_DBG_CC_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_mpace_asb_d0_mif[] = { + GOUT_BLK_NOCL0_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_mpace_asb_d1_mif[] = { + GOUT_BLK_NOCL0_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_mpace_asb_d2_mif[] = { + GOUT_BLK_NOCL0_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_mpace_asb_d3_mif[] = { + GOUT_BLK_NOCL0_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppc_cpucl0_d1_event[] = { + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_PCLK, + GOUT_BLK_NOCL0_UID_PPC_CPUCL0_D1_EVENT_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_slc_ch_top[] = { + GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH_TOP_IPCLKPORT_I_DCLK, +}; +enum clk_id cmucal_vclk_ip_slc_ch1[] = { + GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH1_IPCLKPORT_I_DCLK, +}; +enum clk_id cmucal_vclk_ip_slc_ch2[] = { + GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH2_IPCLKPORT_I_DCLK, +}; +enum clk_id cmucal_vclk_ip_slc_ch3[] = { + GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_ACLK, + GOUT_BLK_NOCL0_UID_SLC_CH3_IPCLKPORT_I_DCLK, +}; +enum clk_id cmucal_vclk_ip_cpe425[] = { + GOUT_BLK_NOCL0_UID_CPE425_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_gray2bin_atb_tsvalue[] = { + GOUT_BLK_NOCL0_UID_GRAY2BIN_ATB_TSVALUE_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_g_nocl0[] = { + GOUT_BLK_NOCL0_UID_SLH_AXI_MI_G_NOCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc0_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1a_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc1_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc2_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc3_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1b_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl2a_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_asyncsfr_wr_smc[] = { + CLK_BLK_NOCL0_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_alive[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_ALIVE_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_cpucl0[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_eh[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_EH_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_gic[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_GIC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mif0[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mif1[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mif2[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mif3[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MIF3_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_misc[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_MISC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_peric0[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_peric1[] = { + CLK_BLK_NOCL0_UID_SLH_AXI_SI_P_PERIC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_bdu[] = { + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_slc[] = { + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_alive_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_ALIVE_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_cpucl0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_eh_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_EH_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_gic_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_GIC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_mif0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_mif1_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_mif2_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF2_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_mif3_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MIF3_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_misc_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_MISC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_peric0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_peric1_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_SI_P_PERIC1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_bdu_cd[] = { + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_BDU_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_t_slc_cd[] = { + CLK_BLK_NOCL0_UID_LH_ATB_SI_T_SLC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_alive_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_ALIVE_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_cpucl0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_eh_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_EH_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_gic_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_GIC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_mif0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_mif1_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_mif2_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF2_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_mif3_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MIF3_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_misc_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_MISC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_peric0_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_peric1_cd[] = { + CLK_BLK_NOCL0_UID_LH_AXI_MI_P_PERIC1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_bdu_cd[] = { + CLK_BLK_NOCL0_UID_LH_ATB_MI_T_BDU_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_t_slc_cd[] = { + CLK_BLK_NOCL0_UID_LH_ATB_MI_T_SLC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc0[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc0_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc1[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc1_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc2[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc2_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC2_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_dmc3[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_DMC3_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_dmc3_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_DMC3_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1a[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1A_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1b[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL1B_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl2a[] = { + CLK_BLK_NOCL0_UID_LH_AST_MI_G_NOCL2A_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1a_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1A_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1b_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL1B_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl2a_cu[] = { + CLK_BLK_NOCL0_UID_LH_AST_SI_G_NOCL2A_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_nocl1a_cmu_nocl1a[] = { + CLK_BLK_NOCL1A_UID_NOCL1A_CMU_NOCL1A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_trex_d_nocl1a[] = { + GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_TREX_D_NOCL1A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_nocl1a[] = { + GOUT_BLK_NOCL1A_UID_SYSREG_NOCL1A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d0_g3d[] = { + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D0_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_nocl1a[] = { + GOUT_BLK_NOCL1A_UID_D_TZPC_NOCL1A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d1_g3d[] = { + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D1_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d2_g3d[] = { + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D2_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d3_g3d[] = { + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D3_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_g3d0[] = { + GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_tpu[] = { + GOUT_BLK_NOCL1A_UID_LH_ACEL_MI_D_TPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_g3d[] = { + GOUT_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D0, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D1, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D2, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_S2_D3, + CLK_BLK_NOCL1A_UID_SYSMMU_G3D_IPCLKPORT_CLK_MPTW, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_g3d_cd[] = { + GOUT_BLK_NOCL1A_UID_LH_AXI_SI_P_G3D_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_nocl1a[] = { + GOUT_BLK_NOCL1A_UID_GPC_NOCL1A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_g3d1[] = { + GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_g3d2[] = { + GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D2_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_g3d3[] = { + GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_SSMT_G3D3_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppcfw_g3d0[] = { + GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPCFW_G3D0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_sysmmu_g3d[] = { + GOUT_BLK_NOCL1A_UID_AD_APB_SYSMMU_G3D_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_trex_p_nocl1a[] = { + GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL1A_UID_TREX_P_NOCL1A_IPCLKPORT_ACLK_P_NOCL1A, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1a_cd[] = { + GOUT_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl2a_m0_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl2a_m1_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M1_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl2a_m2_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M2_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl2a_m3_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M3_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_g3d_d0_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_g3d_d1_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D1_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_g3d_d2_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D2_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_g3d_d3_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D3_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_tpu_event[] = { + GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_nocl2a_m0_cycle[] = { + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_NOCL2A_M0_CYCLE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_g3d_d0_cycle[] = { + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_G3D_D0_CYCLE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_tpu_cycle[] = { + GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPC_TPU_CYCLE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppcfw_g3d1[] = { + CLK_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1A_UID_PPCFW_G3D1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_aur[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_MI_D0_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_aur[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_MI_D1_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_aur_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_AUR_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppc_aur_d0_event[] = { + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_EVENT_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_aur_d1_event[] = { + CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D1_EVENT_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppc_aur_d0_cycle[] = { + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_PCLK, + CLK_BLK_NOCL1A_UID_PPC_AUR_D0_CYCLE_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1a_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AST_MI_G_NOCL1A_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1a[] = { + CLK_BLK_NOCL1A_UID_LH_AST_SI_G_NOCL1A_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_aur_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_AUR_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_aur[] = { + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_AUR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_g3d_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_G3D_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_g3d[] = { + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_G3D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_tpu_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_SI_P_TPU_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_tpu_cd[] = { + CLK_BLK_NOCL1A_UID_LH_AXI_MI_P_TPU_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_tpu[] = { + CLK_BLK_NOCL1A_UID_SLH_AXI_SI_P_TPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_nocl1b_cmu_nocl1b[] = { + CLK_BLK_NOCL1B_UID_NOCL1B_CMU_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_trex_d_nocl1b[] = { + GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_TREX_D_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_nocl1b[] = { + GOUT_BLK_NOCL1B_UID_D_TZPC_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_hsi0[] = { + GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_hsi1[] = { + GOUT_BLK_NOCL1B_UID_LH_ACEL_MI_D_HSI1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_aoc[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_apm[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_APM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_gsa[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_D_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_aoc_cd[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_gsa_cd[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_GSA_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi0_cd[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi1_cd[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_SI_P_HSI1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_nocl1b[] = { + GOUT_BLK_NOCL1B_UID_SYSREG_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_trex_p_nocl1b[] = { + GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_ACLK_P_NOCL1B, + GOUT_BLK_NOCL1B_UID_TREX_P_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_nocl1b[] = { + GOUT_BLK_NOCL1B_UID_GPC_NOCL1B_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_g_cssys_cu[] = { + GOUT_BLK_NOCL1B_UID_LH_AXI_MI_G_CSSYS_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1b_cd[] = { + GOUT_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppc_aoc_event[] = { + GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_EVENT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppc_aoc_cycle[] = { + GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_ACLK, + GOUT_BLK_NOCL1B_UID_PPC_AOC_CYCLE_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl1b_cd[] = { + CLK_BLK_NOCL1B_UID_LH_AST_MI_G_NOCL1B_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl1b[] = { + CLK_BLK_NOCL1B_UID_LH_AST_SI_G_NOCL1B_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_aoc_cd[] = { + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_AOC_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_aoc[] = { + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_AOC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_gsa_cd[] = { + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_GSA_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_gsa[] = { + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_GSA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi0_cd[] = { + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_hsi0[] = { + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi1_cd[] = { + CLK_BLK_NOCL1B_UID_LH_AXI_MI_P_HSI1_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_hsi1[] = { + CLK_BLK_NOCL1B_UID_SLH_AXI_SI_P_HSI1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_g_cssys[] = { + CLK_BLK_NOCL1B_UID_SLH_AXI_MI_G_CSSYS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_g_cssys_cu[] = { + CLK_BLK_NOCL1B_UID_LH_AXI_SI_G_CSSYS_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_nocl2a_cmu_nocl2a[] = { + CLK_BLK_NOCL2A_UID_NOCL2A_CMU_NOCL2A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_nocl2a[] = { + GOUT_BLK_NOCL2A_UID_SYSREG_NOCL2A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_g2d[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_g2d[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d2_g2d[] = { + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D2_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_csis[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_misc[] = { + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_MISC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_dpu[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_mfc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_dpu[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_mfc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d2_dpu[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_hsi2_cd[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_SI_P_HSI2_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_csis[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_mi_d_hsi2[] = { + GOUT_BLK_NOCL2A_UID_LH_ACEL_MI_D_HSI2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_bo[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_nocl2a[] = { + GOUT_BLK_NOCL2A_UID_D_TZPC_NOCL2A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_trex_d_nocl2a[] = { + GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_ACLK, + GOUT_BLK_NOCL2A_UID_TREX_D_NOCL2A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_bo[] = { + GOUT_BLK_NOCL2A_UID_SLH_AXI_SI_P_BO_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_nocl2a[] = { + GOUT_BLK_NOCL2A_UID_GPC_NOCL2A_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_g3aa[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_dns[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d_ipp[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_mcsc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_tnr[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_mcsc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_tnr[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_trex_p_nocl2a[] = { + GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_PCLK, + GOUT_BLK_NOCL2A_UID_TREX_P_NOCL2A_IPCLKPORT_ACLK_P_NOCL2A, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d0_gdc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D0_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d1_gdc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D1_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d2_gdc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d2_tnr[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d3_tnr[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D3_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl2a_cd[] = { + GOUT_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d2_mcsc[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D2_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_d4_tnr[] = { + GOUT_BLK_NOCL2A_UID_LH_AXI_MI_D4_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_g_nocl2a_cd[] = { + CLK_BLK_NOCL2A_UID_LH_AST_MI_G_NOCL2A_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_g_nocl2a[] = { + CLK_BLK_NOCL2A_UID_LH_AST_SI_G_NOCL2A_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_hsi2_cd[] = { + CLK_BLK_NOCL2A_UID_LH_AXI_MI_P_HSI2_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_hsi2[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_HSI2_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_dpu[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_csis[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_g3aa[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_ipp[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_dns[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_itp[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_ITP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mcsc[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_tnr[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_mfc[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_MFC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_g2d[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_G2D_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_gdc[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_disp[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_DISP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_si_p_pdp[] = { + CLK_BLK_NOCL2A_UID_SLH_AXI_SI_P_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_pdp_cmu_pdp[] = { + CLK_BLK_PDP_UID_PDP_CMU_PDP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_pdp[] = { + GOUT_BLK_PDP_UID_D_TZPC_PDP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf0_csis_pdp[] = { + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF0_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf1_csis_pdp[] = { + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF1_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf2_csis_pdp[] = { + GOUT_BLK_PDP_UID_LH_AST_MI_L_OTF2_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_pdp[] = { + GOUT_BLK_PDP_UID_SLH_AXI_MI_P_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpc_pdp[] = { + GOUT_BLK_PDP_UID_GPC_PDP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_pdp_top[] = { + GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_C2CLK, + GOUT_BLK_PDP_UID_PDP_TOP_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_pdp_stat[] = { + GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_SSMT_PDP_STAT_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdp_stat0[] = { + GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_c2_pdp[] = { + GOUT_BLK_PDP_UID_AD_APB_C2_PDP_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_ipp[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_ipp[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_ipp[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_csis[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_csis[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_csis[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_g3aa[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF0_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_g3aa[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF1_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_g3aa[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_OTF2_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_yotf0_pdp_g3aa[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF0_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_yotf1_pdp_g3aa[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_YOTF1_PDP_G3AA_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_csis_pdp[] = { + GOUT_BLK_PDP_UID_LH_AST_MI_L_VO_CSIS_PDP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_pdp_ipp[] = { + GOUT_BLK_PDP_UID_LH_AST_SI_L_VO_PDP_IPP_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_pdp_csis[] = { + GOUT_BLK_PDP_UID_LH_AXI_SI_LD_PDP_CSIS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_pdp[] = { + GOUT_BLK_PDP_UID_SYSREG_PDP_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d_pdp[] = { + GOUT_BLK_PDP_UID_XIU_D_PDP_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdp_stat1[] = { + GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_STAT1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdp_af0[] = { + GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_AF0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_pdp_af1[] = { + GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_ACLK, + GOUT_BLK_PDP_UID_QE_PDP_AF1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ad_apb_vra[] = { + GOUT_BLK_PDP_UID_AD_APB_VRA_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_qe_vra[] = { + CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_ACLK, + CLK_BLK_PDP_UID_QE_VRA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_vra[] = { + CLK_BLK_PDP_UID_VRA_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_vra[] = { + CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_PCLK, + CLK_BLK_PDP_UID_SSMT_VRA_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_ld_pdp_dns[] = { + CLK_BLK_PDP_UID_LH_AXI_SI_LD_PDP_DNS_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_vra[] = { + CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_ACLK, + CLK_BLK_PDP_UID_PPMU_VRA_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpio_peric0[] = { + GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_peric0[] = { + GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_peric0_cmu_peric0[] = { + CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_peric0_cu[] = { + GOUT_BLK_PERIC0_UID_LH_AXI_MI_P_PERIC0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_peric0[] = { + GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_peric0[] = { + GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi1_usi[] = { + CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI1_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi2_usi[] = { + CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI2_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi3_usi[] = { + CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI3_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi4_usi[] = { + CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI4_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi5_usi[] = { + CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI5_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi6_usi[] = { + CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI6_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi7_usi[] = { + CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI7_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi8_usi[] = { + CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI8_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c1[] = { + CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C1_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c2[] = { + CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C2_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c3[] = { + CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C3_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c4[] = { + CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C4_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c5[] = { + CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C5_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c6[] = { + CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C6_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c7[] = { + CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C7_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c8[] = { + CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC0_UID_I3C8_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi0_uart[] = { + CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI0_UART_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi14_usi[] = { + CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_peric0[] = { + CLK_BLK_PERIC0_UID_SLH_AXI_MI_P_PERIC0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_peric0_cu[] = { + CLK_BLK_PERIC0_UID_LH_AXI_SI_P_PERIC0_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_gpio_peric1[] = { + GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_peric1[] = { + GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_peric1_cmu_peric1[] = { + CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_peric1_cu[] = { + GOUT_BLK_PERIC1_UID_LH_AXI_MI_P_PERIC1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_peric1[] = { + GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_peric1[] = { + GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi0_usi[] = { + CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI0_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi9_usi[] = { + CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI9_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi10_usi[] = { + CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi11_usi[] = { + CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi12_usi[] = { + CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI12_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi13_usi[] = { + CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI13_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_i3c0[] = { + CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_SCLK, + CLK_BLK_PERIC1_UID_I3C0_IPCLKPORT_I_PCLK, +}; +enum clk_id cmucal_vclk_ip_pwm[] = { + CLK_BLK_PERIC1_UID_PWM_IPCLKPORT_I_PCLK_S0, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_peric1[] = { + CLK_BLK_PERIC1_UID_SLH_AXI_MI_P_PERIC1_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_peric1_cu[] = { + CLK_BLK_PERIC1_UID_LH_AXI_SI_P_PERIC1_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_usi15_usi[] = { + CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI15_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_usi16_usi[] = { + CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK, + CLK_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_s2d_cmu_s2d[] = { + CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_bis_s2d[] = { + GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_SCLK, + GOUT_BLK_S2D_UID_BIS_S2D_IPCLKPORT_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_lg_scan2dram_cu[] = { + GOUT_BLK_S2D_UID_LH_AXI_MI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_lg_scan2dram[] = { + CLK_BLK_S2D_UID_SLH_AXI_MI_LG_SCAN2DRAM_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_lg_scan2dram_cu[] = { + CLK_BLK_S2D_UID_LH_AXI_SI_LG_SCAN2DRAM_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_apb_async_sysmmu_d0_s1_ns_tnr[] = { + GOUT_BLK_TNR_UID_APB_ASYNC_SYSMMU_D0_S1_NS_TNR_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_tnr[] = { + GOUT_BLK_TNR_UID_D_TZPC_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_vo_dns_tnr[] = { + GOUT_BLK_TNR_UID_LH_AST_MI_L_VO_DNS_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_tnr[] = { + GOUT_BLK_TNR_UID_SLH_AXI_MI_P_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_tnr_mcsc[] = { + GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_MCSC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d0_tnr[] = { + GOUT_BLK_TNR_UID_LH_AXI_SI_D0_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d1_tnr[] = { + GOUT_BLK_TNR_UID_LH_AXI_SI_D1_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d0_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D0_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d1_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D1_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d0_tnr[] = { + GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D0_TNR_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d1_tnr[] = { + GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D1_TNR_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysreg_tnr[] = { + GOUT_BLK_TNR_UID_SYSREG_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_tnr_cmu_tnr[] = { + CLK_BLK_TNR_UID_TNR_CMU_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_vo_tnr_gdc[] = { + GOUT_BLK_TNR_UID_LH_AST_SI_L_VO_TNR_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_tnr[] = { + GOUT_BLK_TNR_UID_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_TNR_IPCLKPORT_C2CLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_mi_l_otf_mcsc_tnr[] = { + GOUT_BLK_TNR_UID_LH_AST_MI_L_OTF_MCSC_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d2_tnr[] = { + GOUT_BLK_TNR_UID_LH_AXI_SI_D2_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d3_tnr[] = { + GOUT_BLK_TNR_UID_LH_AXI_SI_D3_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d2_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_PPMU_D2_TNR_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d3_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D3_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d2_tnr[] = { + GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D2_TNR_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d3_tnr[] = { + GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D3_TNR_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_d4_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D4_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d5_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D5_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d6_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D6_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d7_tnr[] = { + GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_PPMU_D7_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d0_tnr[] = { + GOUT_BLK_TNR_UID_XIU_D0_TNR_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_xiu_d1_tnr[] = { + GOUT_BLK_TNR_UID_XIU_D1_TNR_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_d0_tnr[] = { + GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_PCLK, + GOUT_BLK_TNR_UID_QE_D0_TNR_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_qe_d1_tnr[] = { + GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D1_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d5_tnr[] = { + GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D5_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d6_tnr[] = { + GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D6_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d7_tnr[] = { + GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_QE_D7_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d0_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D0_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d1_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D1_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d2_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D2_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d3_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D3_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_d4_tnr[] = { + GOUT_BLK_TNR_UID_LH_AXI_SI_D4_TNR_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_d4_tnr[] = { + GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S1, + GOUT_BLK_TNR_UID_SYSMMU_D4_TNR_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ssmt_d4_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D4_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d5_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D5_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d6_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D6_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d7_tnr[] = { + GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_ACLK, + GOUT_BLK_TNR_UID_SSMT_D7_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_gpc_tnr[] = { + GOUT_BLK_TNR_UID_GPC_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_ast_si_l_otf_tnr_gdc[] = { + GOUT_BLK_TNR_UID_LH_AST_SI_L_OTF_TNR_GDC_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_d8_tnr[] = { + CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_SSMT_D8_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_qe_d8_tnr[] = { + CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_QE_D8_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ppmu_d8_tnr[] = { + CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_ACLK, + CLK_BLK_TNR_UID_PPMU_D8_TNR_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_tpu_cmu_tpu[] = { + CLK_BLK_TPU_UID_TPU_CMU_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_mi_p_tpu_cu[] = { + GOUT_BLK_TPU_UID_LH_AXI_MI_P_TPU_CU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_d_tzpc_tpu[] = { + GOUT_BLK_TPU_UID_D_TZPC_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_acel_si_d_tpu[] = { + GOUT_BLK_TPU_UID_LH_ACEL_SI_D_TPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_sysreg_tpu[] = { + GOUT_BLK_TPU_UID_SYSREG_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_sysmmu_tpu[] = { + GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S1, + GOUT_BLK_TPU_UID_SYSMMU_TPU_IPCLKPORT_CLK_S2, +}; +enum clk_id cmucal_vclk_ip_ppmu_tpu[] = { + GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_ACLK, + GOUT_BLK_TPU_UID_PPMU_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_ssmt_tpu[] = { + GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_PCLK, + GOUT_BLK_TPU_UID_SSMT_TPU_IPCLKPORT_ACLK, +}; +enum clk_id cmucal_vclk_ip_gpc_tpu[] = { + GOUT_BLK_TPU_UID_GPC_TPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_as_apb_sysmmu_ns_tpu[] = { + GOUT_BLK_TPU_UID_AS_APB_SYSMMU_NS_TPU_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_tpu[] = { + CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_APB_PCLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_DBG_UART_SCLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_AXI_CLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_TPU_CTL_CLK, + CLK_BLK_TPU_UID_TPU_IPCLKPORT_DROOPDETECTORIO_CK_IN, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0[] = { + GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0[] = { + GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_async_apbm_tpu[] = { + GOUT_BLK_TPU_UID_ASYNC_APBM_TPU_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_async_apb_int_tpu[] = { + GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKS, + GOUT_BLK_TPU_UID_ASYNC_APB_INT_TPU_IPCLKPORT_PCLKM, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0_cd[] = { + GOUT_BLK_TPU_UID_LH_ATB_MI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0_cd[] = { + GOUT_BLK_TPU_UID_LH_ATB_MI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_hpm_tpu[] = { + CLK_BLK_TPU_UID_HPM_TPU_IPCLKPORT_HPM_TARGETCLK_C, +}; +enum clk_id cmucal_vclk_ip_busif_hpmtpu[] = { + GOUT_BLK_TPU_UID_BUSIF_HPMTPU_IPCLKPORT_PCLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0_cd[] = { + GOUT_BLK_TPU_UID_LH_ATB_SI_LT0_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0_cd[] = { + GOUT_BLK_TPU_UID_LH_ATB_SI_LT1_TPU_CPUCL0_CD_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_busif_dddtpu[] = { + CLK_BLK_TPU_UID_BUSIF_DDDTPU_IPCLKPORT_CK_IN, +}; +enum clk_id cmucal_vclk_ip_slh_axi_mi_p_tpu[] = { + CLK_BLK_TPU_UID_SLH_AXI_MI_P_TPU_IPCLKPORT_I_CLK, +}; +enum clk_id cmucal_vclk_ip_lh_axi_si_p_tpu_cu[] = { + CLK_BLK_TPU_UID_LH_AXI_SI_P_TPU_CU_IPCLKPORT_I_CLK, +}; + +/* DVFS VCLK -> LUT List */ +struct vclk_lut cmucal_vclk_vdd_int_lut[] = { + {2133000, vdd_int_nm_lut_params}, + {2133000, vdd_int_ud_lut_params}, + {1420000, vdd_int_sud_lut_params}, + {711000, vdd_int_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_mif_lut[] = { + {6400000, vdd_mif_od_lut_params}, + {3732000, vdd_mif_nm_lut_params}, + {2688000, vdd_mif_ud_lut_params}, + {1422000, vdd_mif_sud_lut_params}, + {710000, vdd_mif_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_g3d_lut[] = { + {850000, vdd_g3d_nm_lut_params}, + {700000, vdd_g3d_ud_lut_params}, + {470000, vdd_g3d_sud_lut_params}, + {150000, vdd_g3d_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_cam_lut[] = { + {1150000, vdd_cam_nm_lut_params}, + {747000, vdd_cam_ud_lut_params}, + {373000, vdd_cam_sud_lut_params}, + {178000, vdd_cam_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_cpucl0_lut[] = { + {2100000, vdd_cpucl0_sod_lut_params}, + {1800000, vdd_cpucl0_od_lut_params}, + {1400000, vdd_cpucl0_nm_lut_params}, + {930000, vdd_cpucl0_ud_lut_params}, + {580000, vdd_cpucl0_sud_lut_params}, + {300000, vdd_cpucl0_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_cpucl1_lut[] = { + {2350000, vdd_cpucl1_sod_lut_params}, + {2000000, vdd_cpucl1_od_lut_params}, + {1495000, vdd_cpucl1_nm_lut_params}, + {1027000, vdd_cpucl1_ud_lut_params}, + {700000, vdd_cpucl1_sud_lut_params}, + {400000, vdd_cpucl1_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_tpu_lut[] = { + {1067000, vdd_tpu_nm_lut_params}, + {833000, vdd_tpu_ud_lut_params}, + {622000, vdd_tpu_sud_lut_params}, + {350000, vdd_tpu_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_vdd_cpucl2_lut[] = { + {2850000, vdd_cpucl2_sod_lut_params}, + {2250000, vdd_cpucl2_od_lut_params}, + {1825000, vdd_cpucl2_nm_lut_params}, + {1275000, vdd_cpucl2_ud_lut_params}, + {850000, vdd_cpucl2_sud_lut_params}, + {500000, vdd_cpucl2_uud_lut_params}, +}; + +/* SPECIAL VCLK -> LUT List */ +struct vclk_lut cmucal_vclk_mux_cmu_cmuref_lut[] = { + {533250, mux_cmu_cmuref_ud_lut_params}, + {266625, mux_cmu_cmuref_sud_lut_params}, + {133313, mux_cmu_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_cpucl1_cmuref_lut[] = { + {200000, mux_cpucl1_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_cpucl2_cmuref_lut[] = { + {200000, mux_cpucl2_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clk_hsi0_usb20_ref_lut[] = { + {26000, mux_clk_hsi0_usb20_ref_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_hsi0_usbdpdbg_lut[] = { + {400000, mux_clkcmu_hsi0_usbdpdbg_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_mif_cmuref_lut[] = { + {200000, mux_mif_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_nocl0_cmuref_lut[] = { + {200000, mux_nocl0_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_nocl1b_cmuref_lut[] = { + {200000, mux_nocl1b_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_nocl2a_cmuref_lut[] = { + {200000, mux_nocl2a_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_clkcmu_hsi0_dpgtc_lut[] = { + {133313, clkcmu_hsi0_dpgtc_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_clkcmu_tpu_uart_lut[] = { + {100000, clkcmu_tpu_uart_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_apm_usi0_usi_lut[] = { + {394000, div_clk_apm_usi0_usi_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_apm_usi0_uart_lut[] = { + {197000, div_clk_apm_usi0_uart_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_apm_usi1_uart_lut[] = { + {197000, div_clk_apm_usi1_uart_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_apm_i3c_pmic_lut[] = { + {197000, div_clk_apm_i3c_pmic_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_clk_aur_add_ch_clk_lut[] = { + {2167, clk_aur_add_ch_clk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_clkcmu_hpm_lut[] = { + {400000, clkcmu_hpm_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk0_lut[] = { + {400000, mux_clkcmu_cis_clk0_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk1_lut[] = { + {400000, mux_clkcmu_cis_clk1_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk2_lut[] = { + {400000, mux_clkcmu_cis_clk2_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk3_lut[] = { + {400000, mux_clkcmu_cis_clk3_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk4_lut[] = { + {400000, mux_clkcmu_cis_clk4_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk5_lut[] = { + {400000, mux_clkcmu_cis_clk5_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk6_lut[] = { + {400000, mux_clkcmu_cis_clk6_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_cis_clk7_lut[] = { + {400000, mux_clkcmu_cis_clk7_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_cpucl0_cmuref_lut[] = { + {1050000, div_clk_cpucl0_cmuref_sod_lut_params}, + {900000, div_clk_cpucl0_cmuref_od_lut_params}, + {700000, div_clk_cpucl0_cmuref_nm_lut_params}, + {465000, div_clk_cpucl0_cmuref_ud_lut_params}, + {290000, div_clk_cpucl0_cmuref_sud_lut_params}, + {150000, div_clk_cpucl0_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_cpucl1_cmuref_lut[] = { + {1175000, div_clk_cpucl1_cmuref_sod_lut_params}, + {1000000, div_clk_cpucl1_cmuref_od_lut_params}, + {747500, div_clk_cpucl1_cmuref_nm_lut_params}, + {513500, div_clk_cpucl1_cmuref_ud_lut_params}, + {350000, div_clk_cpucl1_cmuref_sud_lut_params}, + {200000, div_clk_cpucl1_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_cpucl2_cmuref_lut[] = { + {1425000, div_clk_cpucl2_cmuref_sod_lut_params}, + {1125000, div_clk_cpucl2_cmuref_od_lut_params}, + {912500, div_clk_cpucl2_cmuref_nm_lut_params}, + {637500, div_clk_cpucl2_cmuref_ud_lut_params}, + {425000, div_clk_cpucl2_cmuref_sud_lut_params}, + {250000, div_clk_cpucl2_cmuref_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_clk_g3d_add_ch_clk_lut[] = { + {2167, clk_g3d_add_ch_clk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_gsacore_spi_fps_lut[] = { + {393500, div_clk_gsacore_spi_fps_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_gsacore_spi_gsc_lut[] = { + {393500, div_clk_gsacore_spi_gsc_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_gsacore_uart_lut[] = { + {196750, div_clk_gsacore_uart_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_slc_dclk_lut[] = { + {490000, div_clk_slc_dclk_nm_lut_params}, + {466500, div_clk_slc_dclk_od_lut_params}, + {320000, div_clk_slc_dclk_ud_lut_params}, + {160000, div_clk_slc_dclk_sud_lut_params}, + {66500, div_clk_slc_dclk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_slc1_dclk_lut[] = { + {490000, div_clk_slc1_dclk_nm_lut_params}, + {466500, div_clk_slc1_dclk_od_lut_params}, + {320000, div_clk_slc1_dclk_ud_lut_params}, + {160000, div_clk_slc1_dclk_sud_lut_params}, + {66500, div_clk_slc1_dclk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_slc2_dclk_lut[] = { + {490000, div_clk_slc2_dclk_nm_lut_params}, + {466500, div_clk_slc2_dclk_od_lut_params}, + {320000, div_clk_slc2_dclk_ud_lut_params}, + {160000, div_clk_slc2_dclk_sud_lut_params}, + {66500, div_clk_slc2_dclk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_slc3_dclk_lut[] = { + {490000, div_clk_slc3_dclk_nm_lut_params}, + {466500, div_clk_slc3_dclk_od_lut_params}, + {320000, div_clk_slc3_dclk_ud_lut_params}, + {160000, div_clk_slc3_dclk_sud_lut_params}, + {66500, div_clk_slc3_dclk_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi6_usi_lut[] = { + {400000, div_clk_peric0_usi6_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_pericx_usixx_usi_lut[] = { + {400000, div_clk_peric_400_lut_params}, + {200000, div_clk_peric_200_lut_params}, + {133000, div_clk_peric_133_lut_params}, + {100000, div_clk_peric_100_lut_params}, + {66000, div_clk_peric_66_lut_params}, + {50000, div_clk_peric_50_lut_params}, + {40000, div_clk_peric_40_lut_params}, + {24576, div_clk_peric_24_lut_params}, + {12288, div_clk_peric_12_lut_params}, + {8192, div_clk_peric_8_lut_params}, + {6144, div_clk_peric_6_lut_params}, + {4000, div_clk_peric_4_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_peric0_ip_lut[] = { + {400000, mux_clkcmu_peric0_ip_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi3_usi_lut[] = { + {400000, div_clk_peric0_usi3_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi4_usi_lut[] = { + {400000, div_clk_peric0_usi4_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi5_usi_lut[] = { + {400000, div_clk_peric0_usi5_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi14_usi_lut[] = { + {400000, div_clk_peric0_usi14_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi7_usi_lut[] = { + {400000, div_clk_peric0_usi7_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi8_usi_lut[] = { + {400000, div_clk_peric0_usi8_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi1_usi_lut[] = { + {400000, div_clk_peric0_usi1_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi0_uart_lut[] = { + {200000, div_clk_peric0_usi0_uart_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric0_usi2_usi_lut[] = { + {400000, div_clk_peric0_usi2_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi11_usi_lut[] = { + {400000, div_clk_peric1_usi11_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_mux_clkcmu_peric1_ip_lut[] = { + {400000, mux_clkcmu_peric1_ip_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_i3c_lut[] = { + {200000, div_clk_peric1_i3c_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi12_usi_lut[] = { + {400000, div_clk_peric1_usi12_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi0_usi_lut[] = { + {400000, div_clk_peric1_usi0_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi9_usi_lut[] = { + {400000, div_clk_peric1_usi9_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi10_usi_lut[] = { + {400000, div_clk_peric1_usi10_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi13_usi_lut[] = { + {400000, div_clk_peric1_usi13_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi15_usi_lut[] = { + {400000, div_clk_peric1_usi15_usi_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_div_clk_peric1_usi16_usi_lut[] = { + {400000, div_clk_peric1_usi16_usi_uud_lut_params}, +}; + +/* COMMON VCLK -> LUT List */ +struct vclk_lut cmucal_vclk_blk_cmu_lut[] = { + {1066500, blk_cmu_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_hsi0_lut[] = { + {266625, blk_hsi0_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_s2d_lut[] = { + {100000, blk_s2d_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_apm_lut[] = { + {394000, blk_apm_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_cpucl0_lut[] = { + {1050000, blk_cpucl0_sod_lut_params}, + {900000, blk_cpucl0_od_lut_params}, + {800000, blk_cpucl0_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_cpucl1_lut[] = { + {2350000, blk_cpucl1_sod_lut_params}, + {2000000, blk_cpucl1_od_lut_params}, + {1495000, blk_cpucl1_nm_lut_params}, + {1027000, blk_cpucl1_ud_lut_params}, + {700000, blk_cpucl1_sud_lut_params}, + {400000, blk_cpucl1_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_cpucl2_lut[] = { + {2850000, blk_cpucl2_sod_lut_params}, + {2250000, blk_cpucl2_od_lut_params}, + {1825000, blk_cpucl2_nm_lut_params}, + {1275000, blk_cpucl2_ud_lut_params}, + {850000, blk_cpucl2_sud_lut_params}, + {500000, blk_cpucl2_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_eh_lut[] = { + {490000, blk_eh_uud_lut_params}, + {326667, blk_eh_ud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_gsacore_lut[] = { + {787000, blk_gsacore_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_gsactrl_lut[] = { + {196750, blk_gsactrl_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_nocl0_lut[] = { + {980000, blk_nocl0_nm_lut_params}, + {933000, blk_nocl0_od_lut_params}, + {640000, blk_nocl0_ud_lut_params}, + {320000, blk_nocl0_sud_lut_params}, + {133000, blk_nocl0_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_nocl1b_lut[] = { + {533250, blk_nocl1b_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_aoc_lut[] = { + {787000, blk_aoc_nm_lut_params}, + {394000, blk_aoc_ud_lut_params}, + {197000, blk_aoc_sud_lut_params}, + {99000, blk_aoc_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_aur_lut[] = { + {800000, blk_aur_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_bo_lut[] = { + {311000, blk_bo_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_csis_lut[] = { + {333000, blk_csis_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_disp_lut[] = { + {333000, blk_disp_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_dns_lut[] = { + {333000, blk_dns_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_dpu_lut[] = { + {333000, blk_dpu_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_g2d_lut[] = { + {266625, blk_g2d_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_g3aa_lut[] = { + {333000, blk_g3aa_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_g3d_lut[] = { + {1000000, blk_g3d_nm_lut_params}, + {933000, blk_g3d_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_gdc_lut[] = { + {333000, blk_gdc_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_hsi1_lut[] = { + {533250, blk_hsi1_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_hsi2_lut[] = { + {533250, blk_hsi2_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_ipp_lut[] = { + {333000, blk_ipp_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_itp_lut[] = { + {333000, blk_itp_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_mcsc_lut[] = { + {333000, blk_mcsc_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_mif_lut[] = { + {533000, blk_mif_uud_lut_params}, + {466000, blk_mif_nm_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_misc_lut[] = { + {266625, blk_misc_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_nocl1a_lut[] = { + {1066500, blk_nocl1a_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_nocl2a_lut[] = { + {622000, blk_nocl2a_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_pdp_lut[] = { + {333000, blk_pdp_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_peric0_lut[] = { + {200000, blk_peric0_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_peric1_lut[] = { + {66656, blk_peric1_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_tnr_lut[] = { + {333000, blk_tnr_uud_lut_params}, +}; +struct vclk_lut cmucal_vclk_blk_tpu_lut[] = { + {266625, blk_tpu_uud_lut_params}, +}; + +/* Switch VCLK -> LUT Parameter List */ +struct switch_lut mux_clk_aur_aur_lut[] = { + {1066500, 0, 0}, + {666000, 3, 0}, + {333000, 3, 1}, + {133313, 0, 7}, +}; +struct switch_lut mux_clk_g3d_stacks_lut[] = { + {800000, 0, 0}, + {622000, 3, 0}, + {400000, 0, 1}, + {133313, 4, 3}, +}; +struct switch_lut mux_clk_g3d_l2_glb_lut[] = { + {933000, 1, 0}, + {711000, 4, 0}, + {400000, 2, 1}, + {133313, 6, 3}, +}; +struct switch_lut mux_clk_nocl0_noc_lut[] = { + {933000, 1, 0}, + {622000, 5, 0}, + {311000, 5, 1}, + {133313, 0, 7}, +}; +struct switch_lut mux_clk_tpu_tpu_lut[] = { + {1066500, 0, 0}, + {800000, 2, 0}, + {533250, 0, 1}, + {311000, 5, 1}, +}; +struct switch_lut mux_clk_tpu_tpuctl_lut[] = { + {1066500, 0, 0}, +}; +/*================================ SWPLL List =================================*/ +struct vclk_switch switch_vdd_mif[] = { + {MUX_CLK_NOCL0_NOC, MUX_CLKCMU_NOCL0_NOC, CLKCMU_NOCL0_NOC, GATE_CLKCMU_NOCL0_NOC, MUX_CLKCMU_NOCL0_NOC_USER, mux_clk_nocl0_noc_lut, 4}, +}; +struct vclk_switch switch_vdd_g3d[] = { + {MUX_CLK_G3D_STACKS, MUX_CLKCMU_G3D_SWITCH, CLKCMU_G3D_SWITCH, GATE_CLKCMU_G3D_SWITCH, MUX_CLKCMU_G3D_SWITCH_USER, mux_clk_g3d_stacks_lut, 4}, + {MUX_CLK_G3D_L2_GLB, MUX_CLKCMU_G3D_GLB, CLKCMU_G3D_GLB, GATE_CLKCMU_G3D_GLB, MUX_CLKCMU_G3D_GLB_USER, mux_clk_g3d_l2_glb_lut, 4}, +}; +struct vclk_switch switch_vdd_cam[] = { + {MUX_CLK_AUR_AUR, MUX_CLKCMU_AUR_AUR, CLKCMU_AUR_AUR, GATE_CLKCMU_AUR_AUR, MUX_CLKCMU_AUR_SWITCH_USER, mux_clk_aur_aur_lut, 4}, +}; +struct vclk_switch switch_vdd_tpu[] = { + {MUX_CLK_TPU_TPU, MUX_CLKCMU_TPU_TPU, CLKCMU_TPU_TPU, GATE_CLKCMU_TPU_TPU, MUX_CLKCMU_TPU_TPU_USER, mux_clk_tpu_tpu_lut, 4}, + {MUX_CLK_TPU_TPUCTL, MUX_CLKCMU_TPU_TPUCTL, CLKCMU_TPU_TPUCTL, GATE_CLKCMU_TPU_TPUCTL, MUX_CLKCMU_TPU_TPUCTL_USER, mux_clk_tpu_tpuctl_lut, 1}, +}; + +/*================================ VCLK List =================================*/ +unsigned int cmucal_vclk_size = 1290; +struct vclk cmucal_vclk_list[] = { + +/* DVFS VCLK*/ + CMUCAL_VCLK(VCLK_VDD_INT, cmucal_vclk_vdd_int_lut, cmucal_vclk_vdd_int, NULL, NULL), + CMUCAL_VCLK(VCLK_VDD_MIF, cmucal_vclk_vdd_mif_lut, cmucal_vclk_vdd_mif, NULL, switch_vdd_mif), + CMUCAL_VCLK(VCLK_VDD_G3D, cmucal_vclk_vdd_g3d_lut, cmucal_vclk_vdd_g3d, NULL, switch_vdd_g3d), + CMUCAL_VCLK(VCLK_VDD_CAM, cmucal_vclk_vdd_cam_lut, cmucal_vclk_vdd_cam, NULL, switch_vdd_cam), + CMUCAL_VCLK(VCLK_VDD_CPUCL0, cmucal_vclk_vdd_cpucl0_lut, cmucal_vclk_vdd_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_VDD_CPUCL1, cmucal_vclk_vdd_cpucl1_lut, cmucal_vclk_vdd_cpucl1, NULL, NULL), + CMUCAL_VCLK(VCLK_VDD_TPU, cmucal_vclk_vdd_tpu_lut, cmucal_vclk_vdd_tpu, NULL, switch_vdd_tpu), + CMUCAL_VCLK(VCLK_VDD_CPUCL2, cmucal_vclk_vdd_cpucl2_lut, cmucal_vclk_vdd_cpucl2, NULL, NULL), + +/* SPECIAL VCLK*/ + CMUCAL_VCLK(VCLK_MUX_CMU_CMUREF, cmucal_vclk_mux_cmu_cmuref_lut, cmucal_vclk_mux_cmu_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CPUCL1_CMUREF, cmucal_vclk_mux_cpucl1_cmuref_lut, cmucal_vclk_mux_cpucl1_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CPUCL2_CMUREF, cmucal_vclk_mux_cpucl2_cmuref_lut, cmucal_vclk_mux_cpucl2_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLK_HSI0_USB20_REF, cmucal_vclk_mux_clk_hsi0_usb20_ref_lut, cmucal_vclk_mux_clk_hsi0_usb20_ref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_HSI0_USBDPDBG, cmucal_vclk_mux_clkcmu_hsi0_usbdpdbg_lut, cmucal_vclk_mux_clkcmu_hsi0_usbdpdbg, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_MIF_CMUREF, cmucal_vclk_mux_mif_cmuref_lut, cmucal_vclk_mux_mif_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_NOCL0_CMUREF, cmucal_vclk_mux_nocl0_cmuref_lut, cmucal_vclk_mux_nocl0_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_NOCL1B_CMUREF, cmucal_vclk_mux_nocl1b_cmuref_lut, cmucal_vclk_mux_nocl1b_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_NOCL2A_CMUREF, cmucal_vclk_mux_nocl2a_cmuref_lut, cmucal_vclk_mux_nocl2a_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_CLKCMU_HSI0_DPGTC, cmucal_vclk_clkcmu_hsi0_dpgtc_lut, cmucal_vclk_clkcmu_hsi0_dpgtc, NULL, NULL), + CMUCAL_VCLK(VCLK_CLKCMU_TPU_UART, cmucal_vclk_clkcmu_tpu_uart_lut, cmucal_vclk_clkcmu_tpu_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_APM_USI0_USI, cmucal_vclk_div_clk_apm_usi0_usi_lut, cmucal_vclk_div_clk_apm_usi0_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_APM_USI0_UART, cmucal_vclk_div_clk_apm_usi0_uart_lut, cmucal_vclk_div_clk_apm_usi0_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_APM_USI1_UART, cmucal_vclk_div_clk_apm_usi1_uart_lut, cmucal_vclk_div_clk_apm_usi1_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_APM_I3C_PMIC, cmucal_vclk_div_clk_apm_i3c_pmic_lut, cmucal_vclk_div_clk_apm_i3c_pmic, NULL, NULL), + CMUCAL_VCLK(VCLK_CLK_AUR_ADD_CH_CLK, cmucal_vclk_clk_aur_add_ch_clk_lut, cmucal_vclk_clk_aur_add_ch_clk, NULL, NULL), + CMUCAL_VCLK(VCLK_CLKCMU_HPM, cmucal_vclk_clkcmu_hpm_lut, cmucal_vclk_clkcmu_hpm, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK0, cmucal_vclk_mux_clkcmu_cis_clk0_lut, cmucal_vclk_mux_clkcmu_cis_clk0, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK1, cmucal_vclk_mux_clkcmu_cis_clk1_lut, cmucal_vclk_mux_clkcmu_cis_clk1, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK2, cmucal_vclk_mux_clkcmu_cis_clk2_lut, cmucal_vclk_mux_clkcmu_cis_clk2, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK3, cmucal_vclk_mux_clkcmu_cis_clk3_lut, cmucal_vclk_mux_clkcmu_cis_clk3, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK4, cmucal_vclk_mux_clkcmu_cis_clk4_lut, cmucal_vclk_mux_clkcmu_cis_clk4, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK5, cmucal_vclk_mux_clkcmu_cis_clk5_lut, cmucal_vclk_mux_clkcmu_cis_clk5, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK6, cmucal_vclk_mux_clkcmu_cis_clk6_lut, cmucal_vclk_mux_clkcmu_cis_clk6, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_CIS_CLK7, cmucal_vclk_mux_clkcmu_cis_clk7_lut, cmucal_vclk_mux_clkcmu_cis_clk7, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_CPUCL0_CMUREF, cmucal_vclk_div_clk_cpucl0_cmuref_lut, cmucal_vclk_div_clk_cpucl0_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_CPUCL1_CMUREF, cmucal_vclk_div_clk_cpucl1_cmuref_lut, cmucal_vclk_div_clk_cpucl1_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_CPUCL2_CMUREF, cmucal_vclk_div_clk_cpucl2_cmuref_lut, cmucal_vclk_div_clk_cpucl2_cmuref, NULL, NULL), + CMUCAL_VCLK(VCLK_CLK_G3D_ADD_CH_CLK, cmucal_vclk_clk_g3d_add_ch_clk_lut, cmucal_vclk_clk_g3d_add_ch_clk, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_GSACORE_SPI_FPS, cmucal_vclk_div_clk_gsacore_spi_fps_lut, cmucal_vclk_div_clk_gsacore_spi_fps, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_GSACORE_SPI_GSC, cmucal_vclk_div_clk_gsacore_spi_gsc_lut, cmucal_vclk_div_clk_gsacore_spi_gsc, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_GSACORE_UART, cmucal_vclk_div_clk_gsacore_uart_lut, cmucal_vclk_div_clk_gsacore_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_SLC_DCLK, cmucal_vclk_div_clk_slc_dclk_lut, cmucal_vclk_div_clk_slc_dclk, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_SLC1_DCLK, cmucal_vclk_div_clk_slc1_dclk_lut, cmucal_vclk_div_clk_slc1_dclk, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_SLC2_DCLK, cmucal_vclk_div_clk_slc2_dclk_lut, cmucal_vclk_div_clk_slc2_dclk, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_SLC3_DCLK, cmucal_vclk_div_clk_slc3_dclk_lut, cmucal_vclk_div_clk_slc3_dclk, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI0_UART, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi0_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI1_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi1_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI2_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi2_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI3_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi3_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI4_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi4_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI5_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi5_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI6_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi6_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI7_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi7_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI8_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi8_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC0_USI14_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric0_usi14_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_PERIC0_IP, + cmucal_vclk_mux_clkcmu_peric0_ip_lut, + cmucal_vclk_mux_clkcmu_peric0_ip, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI0_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi0_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI9_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi9_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI10_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi10_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI11_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi11_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI12_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi12_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI13_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi13_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_I3C, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_i3c, NULL, NULL), + CMUCAL_VCLK(VCLK_MUX_CLKCMU_PERIC1_IP, cmucal_vclk_mux_clkcmu_peric1_ip_lut, cmucal_vclk_mux_clkcmu_peric1_ip, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI15_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi15_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_DIV_CLK_PERIC1_USI16_USI, + cmucal_vclk_div_clk_pericx_usixx_usi_lut, + cmucal_vclk_div_clk_peric1_usi16_usi, NULL, NULL), + +/* COMMON VCLK*/ + CMUCAL_VCLK(VCLK_BLK_CMU, cmucal_vclk_blk_cmu_lut, cmucal_vclk_blk_cmu, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_HSI0, cmucal_vclk_blk_hsi0_lut, cmucal_vclk_blk_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_S2D, cmucal_vclk_blk_s2d_lut, cmucal_vclk_blk_s2d, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_APM, cmucal_vclk_blk_apm_lut, cmucal_vclk_blk_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_CPUCL0, cmucal_vclk_blk_cpucl0_lut, cmucal_vclk_blk_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_CPUCL1, cmucal_vclk_blk_cpucl1_lut, cmucal_vclk_blk_cpucl1, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_CPUCL2, cmucal_vclk_blk_cpucl2_lut, cmucal_vclk_blk_cpucl2, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_EH, cmucal_vclk_blk_eh_lut, cmucal_vclk_blk_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_GSACORE, cmucal_vclk_blk_gsacore_lut, cmucal_vclk_blk_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_GSACTRL, cmucal_vclk_blk_gsactrl_lut, cmucal_vclk_blk_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_NOCL0, cmucal_vclk_blk_nocl0_lut, cmucal_vclk_blk_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_NOCL1B, cmucal_vclk_blk_nocl1b_lut, cmucal_vclk_blk_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_AOC, cmucal_vclk_blk_aoc_lut, cmucal_vclk_blk_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_AUR, cmucal_vclk_blk_aur_lut, cmucal_vclk_blk_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_BO, cmucal_vclk_blk_bo_lut, cmucal_vclk_blk_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_CSIS, cmucal_vclk_blk_csis_lut, cmucal_vclk_blk_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_DISP, cmucal_vclk_blk_disp_lut, cmucal_vclk_blk_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_DNS, cmucal_vclk_blk_dns_lut, cmucal_vclk_blk_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_DPU, cmucal_vclk_blk_dpu_lut, cmucal_vclk_blk_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_G2D, cmucal_vclk_blk_g2d_lut, cmucal_vclk_blk_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_G3AA, cmucal_vclk_blk_g3aa_lut, cmucal_vclk_blk_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_G3D, cmucal_vclk_blk_g3d_lut, cmucal_vclk_blk_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_GDC, cmucal_vclk_blk_gdc_lut, cmucal_vclk_blk_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_HSI1, cmucal_vclk_blk_hsi1_lut, cmucal_vclk_blk_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_HSI2, cmucal_vclk_blk_hsi2_lut, cmucal_vclk_blk_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_IPP, cmucal_vclk_blk_ipp_lut, cmucal_vclk_blk_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_ITP, cmucal_vclk_blk_itp_lut, cmucal_vclk_blk_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_MCSC, cmucal_vclk_blk_mcsc_lut, cmucal_vclk_blk_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_MIF, cmucal_vclk_blk_mif_lut, cmucal_vclk_blk_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_MISC, cmucal_vclk_blk_misc_lut, cmucal_vclk_blk_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_NOCL1A, cmucal_vclk_blk_nocl1a_lut, cmucal_vclk_blk_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_NOCL2A, cmucal_vclk_blk_nocl2a_lut, cmucal_vclk_blk_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_PDP, cmucal_vclk_blk_pdp_lut, cmucal_vclk_blk_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_PERIC0, cmucal_vclk_blk_peric0_lut, cmucal_vclk_blk_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_PERIC1, cmucal_vclk_blk_peric1_lut, cmucal_vclk_blk_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_TNR, cmucal_vclk_blk_tnr_lut, cmucal_vclk_blk_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_BLK_TPU, cmucal_vclk_blk_tpu_lut, cmucal_vclk_blk_tpu, NULL, NULL), + +/* GATE VCLK*/ + CMUCAL_VCLK(VCLK_IP_AOC_CMU_AOC, NULL, cmucal_vclk_ip_aoc_cmu_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BAAW_AOC, NULL, cmucal_vclk_ip_baaw_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_AOC, NULL, cmucal_vclk_ip_d_tzpc_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_AOC, NULL, cmucal_vclk_ip_gpc_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_HSI0_AOC, NULL, cmucal_vclk_ip_lh_axi_mi_ld_hsi0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_AOC, NULL, cmucal_vclk_ip_lh_axi_si_d_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_AOC, NULL, cmucal_vclk_ip_ppmu_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_USB, NULL, cmucal_vclk_ip_ppmu_usb, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_AOC, NULL, cmucal_vclk_ip_ssmt_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_AOC, NULL, cmucal_vclk_ip_sysmmu_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_AOC, NULL, cmucal_vclk_ip_sysreg_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_AOC, NULL, cmucal_vclk_ip_uasc_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_DP_AOC, NULL, cmucal_vclk_ip_xiu_dp_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_P_AOC, NULL, cmucal_vclk_ip_xiu_p_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AOC_SYSCTRL_APB, NULL, cmucal_vclk_ip_aoc_sysctrl_apb, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LP0_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_si_lp0_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LP0_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_mi_lp0_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LP1_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_si_lp1_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LP1_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_mi_lp1_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_LP0_AOC, NULL, cmucal_vclk_ip_slh_axi_si_lp0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_LP1_AOC, NULL, cmucal_vclk_ip_slh_axi_si_lp1_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AOC, NULL, cmucal_vclk_ip_lh_atb_si_lt_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AOC_CD, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_AOC, NULL, cmucal_vclk_ip_slh_axi_mi_p_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LG_AOC, NULL, cmucal_vclk_ip_slh_axi_mi_lg_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AOC_CD, NULL, cmucal_vclk_ip_lh_atb_si_lt_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_APM, NULL, cmucal_vclk_ip_lh_axi_si_d_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_WDT_APM, NULL, cmucal_vclk_ip_wdt_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_APM, NULL, cmucal_vclk_ip_sysreg_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_AP, NULL, cmucal_vclk_ip_mailbox_apm_ap, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_PMU_ALIVE, NULL, cmucal_vclk_ip_apbif_pmu_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_INTMEM, NULL, cmucal_vclk_ip_intmem, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PMU_INTR_GEN, NULL, cmucal_vclk_ip_pmu_intr_gen, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_DP_ALIVE, NULL, cmucal_vclk_ip_xiu_dp_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APM_CMU_APM, NULL, cmucal_vclk_ip_apm_cmu_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GREBEINTEGRATION, NULL, cmucal_vclk_ip_grebeintegration, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_GPIO_ALIVE, NULL, cmucal_vclk_ip_apbif_gpio_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_TRTC, NULL, cmucal_vclk_ip_apbif_trtc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_APM, NULL, cmucal_vclk_ip_d_tzpc_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_AOC, NULL, cmucal_vclk_ip_mailbox_apm_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_DBGCORE, NULL, cmucal_vclk_ip_mailbox_ap_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_RTC, NULL, cmucal_vclk_ip_apbif_rtc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_GSA, NULL, cmucal_vclk_ip_mailbox_apm_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D_APM, NULL, cmucal_vclk_ip_ssmt_d_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_LG_DBGCORE, NULL, cmucal_vclk_ip_ssmt_lg_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D_APM, NULL, cmucal_vclk_ip_sysmmu_d_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_APM, NULL, cmucal_vclk_ip_gpc_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_APM, NULL, cmucal_vclk_ip_uasc_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_DBGCORE, NULL, cmucal_vclk_ip_uasc_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_P_ALIVE, NULL, cmucal_vclk_ip_uasc_p_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_LP0_AOC, NULL, cmucal_vclk_ip_uasc_lp0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_GPIO_FAR_ALIVE, NULL, cmucal_vclk_ip_apbif_gpio_far_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ROM_CRC32_HOST, NULL, cmucal_vclk_ip_rom_crc32_host, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SS_DBGCORE, NULL, cmucal_vclk_ip_ss_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_SWD, NULL, cmucal_vclk_ip_mailbox_apm_swd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_TPU, NULL, cmucal_vclk_ip_mailbox_apm_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IG_SWD, NULL, cmucal_vclk_ip_lh_axi_mi_ig_swd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_IG_SWD, NULL, cmucal_vclk_ip_uasc_ig_swd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APM_USI0_UART, NULL, cmucal_vclk_ip_apm_usi0_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APM_USI1_UART, NULL, cmucal_vclk_ip_apm_usi1_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APM_USI0_USI, NULL, cmucal_vclk_ip_apm_usi0_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AOCA32, NULL, cmucal_vclk_ip_mailbox_ap_aoca32, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AOCF1, NULL, cmucal_vclk_ip_mailbox_ap_aocf1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AOCP6, NULL, cmucal_vclk_ip_mailbox_ap_aocp6, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AUR0, NULL, cmucal_vclk_ip_mailbox_ap_aur0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AUR1, NULL, cmucal_vclk_ip_mailbox_ap_aur1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AUR2, NULL, cmucal_vclk_ip_mailbox_ap_aur2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_AP_AUR3, NULL, cmucal_vclk_ip_mailbox_ap_aur3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APM_I3C_PMIC, NULL, cmucal_vclk_ip_apm_i3c_pmic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_INTCOMB_VGPIO2PMU, NULL, cmucal_vclk_ip_apbif_intcomb_vgpio2pmu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_INTCOMB_VGPIO2AP, NULL, cmucal_vclk_ip_apbif_intcomb_vgpio2ap, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_INTCOMB_VGPIO2APM, NULL, cmucal_vclk_ip_apbif_intcomb_vgpio2apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_APM_AUR, NULL, cmucal_vclk_ip_mailbox_apm_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_LG_DBGCORE, NULL, cmucal_vclk_ip_slh_axi_si_lg_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_LG_SCAN2DRAM, NULL, cmucal_vclk_ip_slh_axi_si_lg_scan2dram, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_ALIVE, NULL, cmucal_vclk_ip_slh_axi_mi_p_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LP0_AOC, NULL, cmucal_vclk_ip_slh_axi_mi_lp0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_DBGCORE_CD, NULL, cmucal_vclk_ip_lh_axi_si_lg_dbgcore_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_DBGCORE_CD, NULL, cmucal_vclk_ip_lh_axi_mi_lg_dbgcore_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CD, NULL, cmucal_vclk_ip_lh_axi_si_lg_scan2dram_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_SCAN2DRAM_CD, NULL, cmucal_vclk_ip_lh_axi_mi_lg_scan2dram_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LP0_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_si_lp0_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LP0_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_mi_lp0_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_ALIVE_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_alive_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_ALIVE_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_alive_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AUR_CMU_AUR, NULL, cmucal_vclk_ip_aur_cmu_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AUR, NULL, cmucal_vclk_ip_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_SYSMMU_S1_NS_AUR0, NULL, cmucal_vclk_ip_as_apb_sysmmu_s1_ns_aur0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_AUR, NULL, cmucal_vclk_ip_d_tzpc_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_AUR, NULL, cmucal_vclk_ip_gpc_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_AUR, NULL, cmucal_vclk_ip_lh_axi_si_d0_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_AUR, NULL, cmucal_vclk_ip_ssmt_d0_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_AUR, NULL, cmucal_vclk_ip_ssmt_d1_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_AUR, NULL, cmucal_vclk_ip_ppmu_d0_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_AUR, NULL, cmucal_vclk_ip_ppmu_d1_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_AUR_WP, NULL, cmucal_vclk_ip_sysmmu_d0_aur_wp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_AUR_WP, NULL, cmucal_vclk_ip_sysmmu_d1_aur_wp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_AUR, NULL, cmucal_vclk_ip_sysreg_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_AUR, NULL, cmucal_vclk_ip_uasc_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_AUR, NULL, cmucal_vclk_ip_lh_axi_si_d1_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APBM_G_AUR, NULL, cmucal_vclk_ip_as_apbm_g_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADD_APBIF_AUR, NULL, cmucal_vclk_ip_add_apbif_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BAAW_AUR, NULL, cmucal_vclk_ip_baaw_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_AUR_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_aur_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_AUR, NULL, cmucal_vclk_ip_slh_axi_mi_p_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_AUR_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_aur_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BO_CMU_BO, NULL, cmucal_vclk_ip_bo_cmu_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_BO, NULL, cmucal_vclk_ip_lh_axi_si_d_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_BO, NULL, cmucal_vclk_ip_slh_axi_mi_p_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_BO, NULL, cmucal_vclk_ip_ppmu_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_BO, NULL, cmucal_vclk_ip_sysmmu_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_SYSMMU_S1_NS_BO, NULL, cmucal_vclk_ip_as_apb_sysmmu_s1_ns_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_BO, NULL, cmucal_vclk_ip_sysreg_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_BO, NULL, cmucal_vclk_ip_ssmt_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_BO, NULL, cmucal_vclk_ip_d_tzpc_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_BO, NULL, cmucal_vclk_ip_gpc_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_BO, NULL, cmucal_vclk_ip_uasc_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BO, NULL, cmucal_vclk_ip_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_BO, NULL, cmucal_vclk_ip_lh_axi_si_ip_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_BO, NULL, cmucal_vclk_ip_lh_axi_mi_ip_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_CPUCL0, NULL, cmucal_vclk_ip_sysreg_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HPM_APBIF_CPUCL0, NULL, cmucal_vclk_ip_hpm_apbif_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CSSYS, NULL, cmucal_vclk_ip_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT0_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it0_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT6_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it6_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT1_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it1_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT7_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it7_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT2_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it2_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT3_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it3_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACE_SI_D0_CPUCL0, NULL, cmucal_vclk_ip_lh_ace_si_d0_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT0_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it0_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT1_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it1_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT2_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it2_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT3_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it3_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADM_APB_G_CLUSTER0, NULL, cmucal_vclk_ip_adm_apb_g_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL0_CMU_CPUCL0, NULL, cmucal_vclk_ip_cpucl0_cmu_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CLUSTER0, NULL, cmucal_vclk_ip_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT4_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it4_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_IT5_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_mi_it5_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACE_SI_D1_CPUCL0, NULL, cmucal_vclk_ip_lh_ace_si_d1_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT4_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it4_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT5_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it5_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_CPUCL0, NULL, cmucal_vclk_ip_d_tzpc_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IG_CSSYS, NULL, cmucal_vclk_ip_lh_axi_si_ig_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IG_CSSYS, NULL, cmucal_vclk_ip_lh_axi_mi_ig_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_P_CPUCL0, NULL, cmucal_vclk_ip_xiu_p_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HPM_CPUCL0_1, NULL, cmucal_vclk_ip_hpm_cpucl0_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HPM_CPUCL0_0, NULL, cmucal_vclk_ip_hpm_cpucl0_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APB_ASYNC_P_CSSYS_0, NULL, cmucal_vclk_ip_apb_async_p_cssys_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BPS_CPUCL0, NULL, cmucal_vclk_ip_bps_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT6_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it6_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_CPUCL0, NULL, cmucal_vclk_ip_gpc_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IG_DBGCORE, NULL, cmucal_vclk_ip_lh_axi_si_ig_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_DP_CSSYS, NULL, cmucal_vclk_ip_xiu_dp_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IG_DBGCORE, NULL, cmucal_vclk_ip_lh_axi_mi_ig_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_CPUCL0, NULL, cmucal_vclk_ip_ssmt_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_S2_CPUCL0, NULL, cmucal_vclk_ip_sysmmu_s2_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IG_HSI0, NULL, cmucal_vclk_ip_lh_axi_mi_ig_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APB_ASYNC_P_SYSMMU, NULL, cmucal_vclk_ip_apb_async_p_sysmmu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IG_HSI0, NULL, cmucal_vclk_ip_lh_axi_si_ig_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IG_STM, NULL, cmucal_vclk_ip_lh_axi_si_ig_stm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_IT7_CLUSTER0, NULL, cmucal_vclk_ip_lh_atb_si_it7_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IG_STM, NULL, cmucal_vclk_ip_lh_axi_mi_ig_stm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_G_CSSYS, NULL, cmucal_vclk_ip_slh_axi_si_g_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_G_CSSYS_CD, NULL, cmucal_vclk_ip_lh_axi_si_g_cssys_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_G_CSSYS_CD, NULL, cmucal_vclk_ip_lh_axi_mi_g_cssys_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC, NULL, cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD, NULL, cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD, NULL, cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_LG_ETR_HSI0, NULL, cmucal_vclk_ip_slh_axi_si_lg_etr_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_ETR_HSI0_CD, NULL, cmucal_vclk_ip_lh_axi_si_lg_etr_hsi0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_ETR_HSI0_CD, NULL, cmucal_vclk_ip_lh_axi_mi_lg_etr_hsi0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0, NULL, cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU, NULL, cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU, NULL, cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LG_DBGCORE, NULL, cmucal_vclk_ip_slh_axi_mi_lg_dbgcore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_DBGCORE_CU, NULL, cmucal_vclk_ip_lh_axi_si_lg_dbgcore_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_DBGCORE_CU, NULL, cmucal_vclk_ip_lh_axi_mi_lg_dbgcore_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AOC, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AOC_CU, NULL, cmucal_vclk_ip_lh_atb_si_lt_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AOC_CU, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_si_lt_aur_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_mi_lt_aur_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_CPUCL0, NULL, cmucal_vclk_ip_slh_axi_mi_p_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CU, NULL, cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_BDU, NULL, cmucal_vclk_ip_lh_atb_mi_t_bdu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_SLC, NULL, cmucal_vclk_ip_lh_atb_mi_t_slc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_BDU_CU, NULL, cmucal_vclk_ip_lh_atb_si_t_bdu_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_BDU_CU, NULL, cmucal_vclk_ip_lh_atb_mi_t_bdu_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_SLC_CU, NULL, cmucal_vclk_ip_lh_atb_si_t_slc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_SLC_CU, NULL, cmucal_vclk_ip_lh_atb_mi_t_slc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL0_CON, NULL, cmucal_vclk_ip_cpucl0_con, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL1, NULL, cmucal_vclk_ip_cpucl1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL1_CMU_CPUCL1, NULL, cmucal_vclk_ip_cpucl1_cmu_cpucl1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DD_APBIF0_CPUCL0, NULL, cmucal_vclk_ip_dd_apbif0_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL2_CMU_CPUCL2, NULL, cmucal_vclk_ip_cpucl2_cmu_cpucl2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CMU_CPUCL2_SHORTSTOP, NULL, cmucal_vclk_ip_cmu_cpucl2_shortstop, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPUCL2, NULL, cmucal_vclk_ip_cpucl2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DD_APBIF2_CPUCL0, NULL, cmucal_vclk_ip_dd_apbif2_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_CSIS, NULL, cmucal_vclk_ip_lh_axi_si_d0_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_CSIS, NULL, cmucal_vclk_ip_slh_axi_mi_p_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_CSIS, NULL, cmucal_vclk_ip_sysreg_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CSIS_CMU_CSIS, NULL, cmucal_vclk_ip_csis_cmu_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ZOTF2_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_zotf2_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MIPI_PHY_LINK_WRAP, NULL, cmucal_vclk_ip_mipi_phy_link_wrap, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_CSIS, NULL, cmucal_vclk_ip_d_tzpc_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ZOTF1_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_zotf1_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0, NULL, cmucal_vclk_ip_ppmu_d0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ZOTF0_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_zotf0_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_SOTF0_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_sotf0_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_SOTF1_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_sotf1_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_SOTF2_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_sotf2_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF2_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf2_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_CSIS, NULL, cmucal_vclk_ip_gpc_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_CSIS0, NULL, cmucal_vclk_ip_ad_apb_csis0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1, NULL, cmucal_vclk_ip_ppmu_d1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_CSIS, NULL, cmucal_vclk_ip_sysmmu_d0_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_CSIS, NULL, cmucal_vclk_ip_sysmmu_d1_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1, NULL, cmucal_vclk_ip_ssmt_d1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0, NULL, cmucal_vclk_ip_ssmt_d0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ZSL1, NULL, cmucal_vclk_ip_qe_zsl1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ZSL2, NULL, cmucal_vclk_ip_qe_zsl2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ZSL0, NULL, cmucal_vclk_ip_qe_zsl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_STRP0, NULL, cmucal_vclk_ip_qe_strp0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D0_CSIS, NULL, cmucal_vclk_ip_xiu_d0_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D1_CSIS, NULL, cmucal_vclk_ip_xiu_d1_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_MCSC_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_mcsc_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_CSIS, NULL, cmucal_vclk_ip_lh_axi_si_d1_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF2_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_PDP_CSIS, NULL, cmucal_vclk_ip_lh_axi_mi_ld_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_STRP2, NULL, cmucal_vclk_ip_qe_strp2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_STRP1, NULL, cmucal_vclk_ip_qe_strp1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D2_CSIS, NULL, cmucal_vclk_ip_xiu_d2_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CSISX8, NULL, cmucal_vclk_ip_csisx8, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_CSIS_DMA0, NULL, cmucal_vclk_ip_qe_csis_dma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_CSIS_DMA1, NULL, cmucal_vclk_ip_qe_csis_dma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_CSIS_DMA2, NULL, cmucal_vclk_ip_qe_csis_dma2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_CSIS_DMA3, NULL, cmucal_vclk_ip_qe_csis_dma3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DISP_CMU_DISP, NULL, cmucal_vclk_ip_disp_cmu_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_DECON_MAIN, NULL, cmucal_vclk_ip_ad_apb_decon_main, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DPUB, NULL, cmucal_vclk_ip_dpub, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_DISP, NULL, cmucal_vclk_ip_slh_axi_mi_p_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_DISP, NULL, cmucal_vclk_ip_d_tzpc_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_DISP, NULL, cmucal_vclk_ip_gpc_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_DISP, NULL, cmucal_vclk_ip_sysreg_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_DNS, NULL, cmucal_vclk_ip_ad_apb_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_DNS, NULL, cmucal_vclk_ip_d_tzpc_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DNS, NULL, cmucal_vclk_ip_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_DNS, NULL, cmucal_vclk_ip_gpc_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_DNS, NULL, cmucal_vclk_ip_slh_axi_mi_p_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_DNS, NULL, cmucal_vclk_ip_lh_axi_si_d_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_DNS, NULL, cmucal_vclk_ip_ppmu_d0_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_DNS, NULL, cmucal_vclk_ip_ssmt_d0_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_DNS, NULL, cmucal_vclk_ip_sysmmu_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_DNS, NULL, cmucal_vclk_ip_sysreg_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_DNS_ITP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_dns_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_DNS_ITP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_dns_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF2_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf2_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_ITP_DNS, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_itp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_DNS_GDC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_dns_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_IPP_DNS, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_DNS_TNR, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_dns_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_PDP_DNS, NULL, cmucal_vclk_ip_lh_axi_mi_ld_pdp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D_DNS, NULL, cmucal_vclk_ip_xiu_d_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_IPP_DNS, NULL, cmucal_vclk_ip_lh_axi_mi_ld_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_MCSC_DNS, NULL, cmucal_vclk_ip_lh_axi_mi_ld_mcsc_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D0_DNS, NULL, cmucal_vclk_ip_qe_d0_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_IPP_DNS, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DNS_CMU_DNS, NULL, cmucal_vclk_ip_dns_cmu_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_DNS, NULL, cmucal_vclk_ip_ssmt_d1_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_DNS, NULL, cmucal_vclk_ip_ppmu_d1_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_DNS, NULL, cmucal_vclk_ip_qe_d1_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LD_ITP_DNS, NULL, cmucal_vclk_ip_lh_axi_mi_ld_itp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DPU_CMU_DPU, NULL, cmucal_vclk_ip_dpu_cmu_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_DPU, NULL, cmucal_vclk_ip_sysreg_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_DPUD0, NULL, cmucal_vclk_ip_sysmmu_dpud0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_DPU, NULL, cmucal_vclk_ip_slh_axi_mi_p_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_DPU, NULL, cmucal_vclk_ip_lh_axi_si_d1_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D2_DPU, NULL, cmucal_vclk_ip_lh_axi_si_d2_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_DPUD2, NULL, cmucal_vclk_ip_sysmmu_dpud2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_DPUD1, NULL, cmucal_vclk_ip_sysmmu_dpud1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_DPUD0, NULL, cmucal_vclk_ip_ppmu_dpud0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_DPUD1, NULL, cmucal_vclk_ip_ppmu_dpud1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_DPUD2, NULL, cmucal_vclk_ip_ppmu_dpud2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_DPU, NULL, cmucal_vclk_ip_lh_axi_si_d0_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DPUF, NULL, cmucal_vclk_ip_dpuf, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_DPU, NULL, cmucal_vclk_ip_d_tzpc_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_DPU_DMA, NULL, cmucal_vclk_ip_ad_apb_dpu_dma, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_DPU0, NULL, cmucal_vclk_ip_ssmt_dpu0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_DPU1, NULL, cmucal_vclk_ip_ssmt_dpu1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_DPU2, NULL, cmucal_vclk_ip_ssmt_dpu2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_DPU, NULL, cmucal_vclk_ip_gpc_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_EH_CMU_EH, NULL, cmucal_vclk_ip_eh_cmu_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_P_SYSMMU_S2_EH, NULL, cmucal_vclk_ip_as_p_sysmmu_s2_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_EH, NULL, cmucal_vclk_ip_d_tzpc_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_EH, NULL, cmucal_vclk_ip_gpc_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_EH_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_eh_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_EH, NULL, cmucal_vclk_ip_lh_acel_si_d_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_EH, NULL, cmucal_vclk_ip_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_EH, NULL, cmucal_vclk_ip_ssmt_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_EH, NULL, cmucal_vclk_ip_ppmu_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_EH, NULL, cmucal_vclk_ip_sysmmu_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_EH, NULL, cmucal_vclk_ip_sysreg_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_EH, NULL, cmucal_vclk_ip_uasc_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_EH, NULL, cmucal_vclk_ip_qe_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_EH, NULL, cmucal_vclk_ip_slh_axi_mi_p_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_EH_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_eh_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_EH, NULL, cmucal_vclk_ip_lh_axi_si_ip_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_EH, NULL, cmucal_vclk_ip_lh_axi_mi_ip_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_G2D_CMU_G2D, NULL, cmucal_vclk_ip_g2d_cmu_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_G2D, NULL, cmucal_vclk_ip_ppmu_d0_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_G2D, NULL, cmucal_vclk_ip_ppmu_d1_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_G2D, NULL, cmucal_vclk_ip_sysmmu_d0_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_G2D, NULL, cmucal_vclk_ip_sysreg_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_G2D, NULL, cmucal_vclk_ip_lh_axi_si_d0_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_G2D, NULL, cmucal_vclk_ip_lh_axi_si_d1_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D2_G2D, NULL, cmucal_vclk_ip_sysmmu_d2_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D2_G2D, NULL, cmucal_vclk_ip_ppmu_d2_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D2_G2D, NULL, cmucal_vclk_ip_lh_acel_si_d2_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_G2D, NULL, cmucal_vclk_ip_ssmt_d0_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_G2D, NULL, cmucal_vclk_ip_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_G2D, NULL, cmucal_vclk_ip_sysmmu_d1_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_JPEG, NULL, cmucal_vclk_ip_jpeg, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_G2D, NULL, cmucal_vclk_ip_d_tzpc_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_G2D, NULL, cmucal_vclk_ip_ssmt_d1_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D2_G2D, NULL, cmucal_vclk_ip_ssmt_d2_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_G2D, NULL, cmucal_vclk_ip_gpc_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_G2D, NULL, cmucal_vclk_ip_slh_axi_mi_p_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_G2D, NULL, cmucal_vclk_ip_as_apb_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_JPEG, NULL, cmucal_vclk_ip_as_apb_jpeg, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_G3AA, NULL, cmucal_vclk_ip_lh_axi_si_d_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APB_ASYNC_TOP_G3AA, NULL, cmucal_vclk_ip_apb_async_top_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_G3AA, NULL, cmucal_vclk_ip_sysreg_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_G3AA_CMU_G3AA, NULL, cmucal_vclk_ip_g3aa_cmu_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_G3AA, NULL, cmucal_vclk_ip_ppmu_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_G3AA, NULL, cmucal_vclk_ip_d_tzpc_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_G3AA, NULL, cmucal_vclk_ip_gpc_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_G3AA, NULL, cmucal_vclk_ip_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_G3AA, NULL, cmucal_vclk_ip_ssmt_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_G3AA, NULL, cmucal_vclk_ip_sysmmu_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_YOTF0_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_mi_l_yotf0_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF2_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_YOTF1_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_mi_l_yotf1_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_G3AA, NULL, cmucal_vclk_ip_slh_axi_mi_p_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_G3D_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_g3d_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BUSIF_HPMG3D, NULL, cmucal_vclk_ip_busif_hpmg3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HPM_G3D, NULL, cmucal_vclk_ip_hpm_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_G3D, NULL, cmucal_vclk_ip_sysreg_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_G3D_CMU_G3D, NULL, cmucal_vclk_ip_g3d_cmu_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_G3D, NULL, cmucal_vclk_ip_lh_axi_si_ip_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPU, NULL, cmucal_vclk_ip_gpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_G3D, NULL, cmucal_vclk_ip_lh_axi_mi_ip_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GRAY2BIN_G3D, NULL, cmucal_vclk_ip_gray2bin_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_G3D, NULL, cmucal_vclk_ip_d_tzpc_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_G3D, NULL, cmucal_vclk_ip_gpc_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_G3D, NULL, cmucal_vclk_ip_uasc_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADD_APBIF_G3D, NULL, cmucal_vclk_ip_add_apbif_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADD_G3D, NULL, cmucal_vclk_ip_add_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ASB_G3D, NULL, cmucal_vclk_ip_asb_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_G3D, NULL, cmucal_vclk_ip_slh_axi_mi_p_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_G3D_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_g3d_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADM_AHB_G_GPU, NULL, cmucal_vclk_ip_adm_ahb_g_gpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GDC_CMU_GDC, NULL, cmucal_vclk_ip_gdc_cmu_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_GDC0, NULL, cmucal_vclk_ip_ad_apb_gdc0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_GDC1, NULL, cmucal_vclk_ip_ad_apb_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_SCSC, NULL, cmucal_vclk_ip_ad_apb_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_GDC, NULL, cmucal_vclk_ip_d_tzpc_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GDC0, NULL, cmucal_vclk_ip_gdc0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GDC1, NULL, cmucal_vclk_ip_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_GDC, NULL, cmucal_vclk_ip_gpc_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D2_GDC, NULL, cmucal_vclk_ip_lh_axi_si_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_GDC, NULL, cmucal_vclk_ip_ppmu_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_GDC, NULL, cmucal_vclk_ip_ppmu_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SCSC, NULL, cmucal_vclk_ip_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_GDC, NULL, cmucal_vclk_ip_ssmt_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_GDC, NULL, cmucal_vclk_ip_ssmt_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_SCSC, NULL, cmucal_vclk_ip_ssmt_d0_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D2_GDC, NULL, cmucal_vclk_ip_sysmmu_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_GDC, NULL, cmucal_vclk_ip_sysreg_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_I_GDC0_GDC1, NULL, cmucal_vclk_ip_lh_ast_mi_i_gdc0_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_I_GDC1_SCSC, NULL, cmucal_vclk_ip_lh_ast_mi_i_gdc1_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_DNS_GDC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_dns_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_TNR_GDC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_tnr_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_TNR_GDC, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_tnr_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_I_GDC0_GDC1, NULL, cmucal_vclk_ip_lh_ast_si_i_gdc0_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_I_GDC1_SCSC, NULL, cmucal_vclk_ip_lh_ast_si_i_gdc1_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_GDC_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_gdc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_GDC, NULL, cmucal_vclk_ip_sysmmu_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_GDC, NULL, cmucal_vclk_ip_sysmmu_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_GDC, NULL, cmucal_vclk_ip_lh_axi_si_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_SCSC, NULL, cmucal_vclk_ip_ppmu_d0_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D2_GDC, NULL, cmucal_vclk_ip_xiu_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_SCSC, NULL, cmucal_vclk_ip_qe_d1_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D0_SCSC, NULL, cmucal_vclk_ip_qe_d0_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_GDC, NULL, cmucal_vclk_ip_slh_axi_mi_p_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_GDC, NULL, cmucal_vclk_ip_lh_axi_si_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D0_GDC, NULL, cmucal_vclk_ip_xiu_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D1_GDC, NULL, cmucal_vclk_ip_xiu_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D2_GDC, NULL, cmucal_vclk_ip_ppmu_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D3_GDC, NULL, cmucal_vclk_ip_ppmu_d3_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_SCSC, NULL, cmucal_vclk_ip_ppmu_d1_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D2_SCSC, NULL, cmucal_vclk_ip_ppmu_d2_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D2_GDC, NULL, cmucal_vclk_ip_ssmt_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D3_GDC, NULL, cmucal_vclk_ip_ssmt_d3_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_SCSC, NULL, cmucal_vclk_ip_ssmt_d1_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D2_SCSC, NULL, cmucal_vclk_ip_ssmt_d2_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D0_GDC, NULL, cmucal_vclk_ip_qe_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_GDC, NULL, cmucal_vclk_ip_qe_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D2_GDC, NULL, cmucal_vclk_ip_qe_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D2_SCSC, NULL, cmucal_vclk_ip_qe_d2_scsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D3_GDC, NULL, cmucal_vclk_ip_qe_d3_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_ID_SCSC_GDC1, NULL, cmucal_vclk_ip_lh_axi_mi_id_scsc_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_ID_SCSC_GDC1, NULL, cmucal_vclk_ip_lh_axi_si_id_scsc_gdc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GSACORE_CMU_GSACORE, NULL, cmucal_vclk_ip_gsacore_cmu_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CA32_GSACORE, NULL, cmucal_vclk_ip_ca32_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_GSACORE, NULL, cmucal_vclk_ip_gpio_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_KDN_GSACORE, NULL, cmucal_vclk_ip_kdn_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_OTP_CON_GSACORE, NULL, cmucal_vclk_ip_otp_con_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_GSACORE, NULL, cmucal_vclk_ip_ppmu_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_CA32_GSACORE, NULL, cmucal_vclk_ip_qe_ca32_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_DMA_GSACORE, NULL, cmucal_vclk_ip_qe_dma_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_SSS_GSACORE, NULL, cmucal_vclk_ip_qe_sss_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_RESETMON_GSACORE, NULL, cmucal_vclk_ip_resetmon_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SPI_FPS_GSACORE, NULL, cmucal_vclk_ip_spi_fps_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SPI_GSC_GSACORE, NULL, cmucal_vclk_ip_spi_gsc_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_GSACORE, NULL, cmucal_vclk_ip_ssmt_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSS_GSACORE, NULL, cmucal_vclk_ip_sss_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_GSACORE, NULL, cmucal_vclk_ip_sysreg_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UART_GSACORE, NULL, cmucal_vclk_ip_uart_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_WDT_GSACORE, NULL, cmucal_vclk_ip_wdt_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BAAW_GSACORE, NULL, cmucal_vclk_ip_baaw_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_INTMEM_GSACORE, NULL, cmucal_vclk_ip_intmem_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_GSA, NULL, cmucal_vclk_ip_lh_axi_si_d_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_GSA, NULL, cmucal_vclk_ip_lh_axi_si_ip_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DMA_GSACORE, NULL, cmucal_vclk_ip_dma_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_GSACORE, NULL, cmucal_vclk_ip_sysmmu_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_DMA_GSACORE_NS, NULL, cmucal_vclk_ip_ad_apb_dma_gsacore_ns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PUF_GSACORE, NULL, cmucal_vclk_ip_puf_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_DP0_GSA_WP, NULL, cmucal_vclk_ip_xiu_dp0_gsa_wp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_I_DAP_GSA, NULL, cmucal_vclk_ip_lh_axi_mi_i_dap_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UGME, NULL, cmucal_vclk_ip_ugme, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_I_CA32_GIC, NULL, cmucal_vclk_ip_lh_ast_mi_i_ca32_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_I_GIC_CA32, NULL, cmucal_vclk_ip_lh_ast_mi_i_gic_ca32, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UDAP_SSS_AHB_ASYNC, NULL, cmucal_vclk_ip_udap_sss_ahb_async, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_SYSMMU_GSACORE_NS, NULL, cmucal_vclk_ip_ad_apb_sysmmu_gsacore_ns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GIC_GSACORE, NULL, cmucal_vclk_ip_gic_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_I_GIC_CA32, NULL, cmucal_vclk_ip_lh_ast_si_i_gic_ca32, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_I_CA32_GIC, NULL, cmucal_vclk_ip_lh_ast_si_i_ca32_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_si_lt_gsa_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_mi_lt_gsa_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_AXI2APB1_GSACORE, NULL, cmucal_vclk_ip_lh_axi_si_ip_axi2apb1_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_AXI2APB1_GSACORE, NULL, cmucal_vclk_ip_lh_axi_mi_ip_axi2apb1_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_AXI2APB2_GSACORE, NULL, cmucal_vclk_ip_lh_axi_si_ip_axi2apb2_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_AXI2APB2_GSACORE, NULL, cmucal_vclk_ip_lh_axi_mi_ip_axi2apb2_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_GME, NULL, cmucal_vclk_ip_lh_axi_si_ip_gme, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_GME, NULL, cmucal_vclk_ip_lh_axi_mi_ip_gme, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_INTMEM_GSACORE, NULL, cmucal_vclk_ip_ad_apb_intmem_gsacore, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GSACTRL_CMU_GSACTRL, NULL, cmucal_vclk_ip_gsactrl_cmu_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_GSACTRL, NULL, cmucal_vclk_ip_gpc_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_GSA2AOC, NULL, cmucal_vclk_ip_mailbox_gsa2aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_GSA2NONTZ, NULL, cmucal_vclk_ip_mailbox_gsa2nontz, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_GSA2TPU, NULL, cmucal_vclk_ip_mailbox_gsa2tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_GSA2AUR, NULL, cmucal_vclk_ip_mailbox_gsa2aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_GSACTRL, NULL, cmucal_vclk_ip_sysreg_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TZPC_GSACTRL, NULL, cmucal_vclk_ip_tzpc_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_INTMEM_GSACTRL, NULL, cmucal_vclk_ip_intmem_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_GSA, NULL, cmucal_vclk_ip_lh_axi_mi_ip_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MAILBOX_GSA2TZ, NULL, cmucal_vclk_ip_mailbox_gsa2tz, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PMU_GSA, NULL, cmucal_vclk_ip_pmu_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBIF_GPIO_GSACTRL, NULL, cmucal_vclk_ip_apbif_gpio_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TIMER_GSACTRL, NULL, cmucal_vclk_ip_timer_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DAP_GSACTRL, NULL, cmucal_vclk_ip_dap_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_GSA_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_gsa_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_GSACTRLEXT, NULL, cmucal_vclk_ip_sysreg_gsactrlext, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SECJTAG_GSACTRL, NULL, cmucal_vclk_ip_secjtag_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_I_DAP_GSA, NULL, cmucal_vclk_ip_lh_axi_si_i_dap_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_INTMEM_GSACTRL, NULL, cmucal_vclk_ip_ad_apb_intmem_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_GSA, NULL, cmucal_vclk_ip_slh_axi_mi_p_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_GSA_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_gsa_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_IP_AXI2APB0_GSACTRL, NULL, cmucal_vclk_ip_lh_axi_si_ip_axi2apb0_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_IP_AXI2APB0_GSACTRL, NULL, cmucal_vclk_ip_lh_axi_mi_ip_axi2apb0_gsactrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_DP1_GSA_WP, NULL, cmucal_vclk_ip_xiu_dp1_gsa_wp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HSI0_CMU_HSI0, NULL, cmucal_vclk_ip_hsi0_cmu_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USB31DRD, NULL, cmucal_vclk_ip_usb31drd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DP_LINK, NULL, cmucal_vclk_ip_dp_link, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D0_HSI0, NULL, cmucal_vclk_ip_xiu_d0_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ETR_MIU, NULL, cmucal_vclk_ip_etr_miu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_HSI0_NOCL1B, NULL, cmucal_vclk_ip_ppmu_hsi0_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_HSI0_AOC, NULL, cmucal_vclk_ip_ppmu_hsi0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_HSI0_AOC, NULL, cmucal_vclk_ip_lh_axi_si_ld_hsi0_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_HSI0, NULL, cmucal_vclk_ip_lh_acel_si_d_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_HSI0, NULL, cmucal_vclk_ip_gpc_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_HSI0, NULL, cmucal_vclk_ip_d_tzpc_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_USB, NULL, cmucal_vclk_ip_ssmt_usb, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_USB, NULL, cmucal_vclk_ip_sysmmu_usb, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_HSI0, NULL, cmucal_vclk_ip_sysreg_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_P_HSI0, NULL, cmucal_vclk_ip_xiu_p_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D1_HSI0, NULL, cmucal_vclk_ip_xiu_d1_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_HSI0_CTRL, NULL, cmucal_vclk_ip_uasc_hsi0_ctrl, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_HSI0_LINK, NULL, cmucal_vclk_ip_uasc_hsi0_link, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LG_ETR_HSI0, NULL, cmucal_vclk_ip_slh_axi_mi_lg_etr_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LP1_AOC, NULL, cmucal_vclk_ip_slh_axi_mi_lp1_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_HSI0, NULL, cmucal_vclk_ip_slh_axi_mi_p_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_ETR_HSI0_CU, NULL, cmucal_vclk_ip_lh_axi_si_lg_etr_hsi0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_ETR_HSI0_CU, NULL, cmucal_vclk_ip_lh_axi_mi_lg_etr_hsi0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LP1_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_si_lp1_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LP1_AOC_CU, NULL, cmucal_vclk_ip_lh_axi_mi_lp1_aoc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI0_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI0_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HSI1_CMU_HSI1, NULL, cmucal_vclk_ip_hsi1_cmu_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_HSI1, NULL, cmucal_vclk_ip_lh_acel_si_d_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI1_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_HSI1, NULL, cmucal_vclk_ip_sysreg_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D_HSI1, NULL, cmucal_vclk_ip_xiu_d_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_HSI1, NULL, cmucal_vclk_ip_ppmu_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_HSI1, NULL, cmucal_vclk_ip_sysmmu_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_P_HSI1, NULL, cmucal_vclk_ip_xiu_p_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_GEN4_0, NULL, cmucal_vclk_ip_pcie_gen4_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_IA_GEN4A_0, NULL, cmucal_vclk_ip_pcie_ia_gen4a_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_IA_GEN4B_0, NULL, cmucal_vclk_ip_pcie_ia_gen4b_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_HSI1, NULL, cmucal_vclk_ip_d_tzpc_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_HSI1, NULL, cmucal_vclk_ip_gpc_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_HSI1, NULL, cmucal_vclk_ip_ssmt_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_HSI1, NULL, cmucal_vclk_ip_gpio_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PCIE_GEN4A_HSI1, NULL, cmucal_vclk_ip_qe_pcie_gen4a_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PCIE_GEN4B_HSI1, NULL, cmucal_vclk_ip_qe_pcie_gen4b_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4A_DBI_0, NULL, cmucal_vclk_ip_uasc_pcie_gen4a_dbi_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4A_SLV_0, NULL, cmucal_vclk_ip_uasc_pcie_gen4a_slv_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4B_DBI_0, NULL, cmucal_vclk_ip_uasc_pcie_gen4b_dbi_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4B_SLV_0, NULL, cmucal_vclk_ip_uasc_pcie_gen4b_slv_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PCIE_IA_GEN4A_0, NULL, cmucal_vclk_ip_ssmt_pcie_ia_gen4a_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PCIE_IA_GEN4B_0, NULL, cmucal_vclk_ip_ssmt_pcie_ia_gen4b_0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_PCIEPHY_HSI1, NULL, cmucal_vclk_ip_as_apb_pciephy_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_HSI1, NULL, cmucal_vclk_ip_slh_axi_mi_p_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI1_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HSI2_CMU_HSI2, NULL, cmucal_vclk_ip_hsi2_cmu_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_HSI2, NULL, cmucal_vclk_ip_sysreg_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_HSI2, NULL, cmucal_vclk_ip_gpio_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_HSI2, NULL, cmucal_vclk_ip_lh_acel_si_d_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI2_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi2_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D_HSI2, NULL, cmucal_vclk_ip_xiu_d_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_P_HSI2, NULL, cmucal_vclk_ip_xiu_p_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_HSI2, NULL, cmucal_vclk_ip_ppmu_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_GEN4_1, NULL, cmucal_vclk_ip_pcie_gen4_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_HSI2, NULL, cmucal_vclk_ip_sysmmu_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_HSI2, NULL, cmucal_vclk_ip_ssmt_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_IA_GEN4A_1, NULL, cmucal_vclk_ip_pcie_ia_gen4a_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_HSI2, NULL, cmucal_vclk_ip_d_tzpc_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UFS_EMBD, NULL, cmucal_vclk_ip_ufs_embd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PCIE_IA_GEN4B_1, NULL, cmucal_vclk_ip_pcie_ia_gen4b_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_HSI2, NULL, cmucal_vclk_ip_gpc_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MMC_CARD, NULL, cmucal_vclk_ip_mmc_card, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PCIE_GEN4A_HSI2, NULL, cmucal_vclk_ip_qe_pcie_gen4a_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PCIE_GEN4B_HSI2, NULL, cmucal_vclk_ip_qe_pcie_gen4b_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_UFS_EMBD_HSI2, NULL, cmucal_vclk_ip_qe_ufs_embd_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4A_DBI_1, NULL, cmucal_vclk_ip_uasc_pcie_gen4a_dbi_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4A_SLV_1, NULL, cmucal_vclk_ip_uasc_pcie_gen4a_slv_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4B_DBI_1, NULL, cmucal_vclk_ip_uasc_pcie_gen4b_dbi_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_UASC_PCIE_GEN4B_SLV_1, NULL, cmucal_vclk_ip_uasc_pcie_gen4b_slv_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_MMC_CARD_HSI2, NULL, cmucal_vclk_ip_qe_mmc_card_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PCIE_IA_GEN4A_1, NULL, cmucal_vclk_ip_ssmt_pcie_ia_gen4a_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PCIE_IA_GEN4B_1, NULL, cmucal_vclk_ip_ssmt_pcie_ia_gen4b_1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_PCIEPHY_HSI2, NULL, cmucal_vclk_ip_as_apb_pciephy_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_HSI2UFS, NULL, cmucal_vclk_ip_gpio_hsi2ufs, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_HSI2, NULL, cmucal_vclk_ip_slh_axi_mi_p_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI2_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi2_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_IPP_CMU_IPP, NULL, cmucal_vclk_ip_ipp_cmu_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_IPP, NULL, cmucal_vclk_ip_d_tzpc_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_IPP, NULL, cmucal_vclk_ip_slh_axi_mi_p_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_IPP, NULL, cmucal_vclk_ip_sysreg_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_IPP_DNS, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_IPP, NULL, cmucal_vclk_ip_ad_apb_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D_IPP, NULL, cmucal_vclk_ip_lh_axi_si_d_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_SOTF0_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_sotf0_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_SOTF1_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_sotf1_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_SOTF2_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_sotf2_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ZOTF0_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_zotf0_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ZOTF1_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_zotf1_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ZOTF2_IPP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_zotf2_ipp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_IPP, NULL, cmucal_vclk_ip_ppmu_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SIPU_IPP, NULL, cmucal_vclk_ip_sipu_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_IPP, NULL, cmucal_vclk_ip_sysmmu_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_IPP, NULL, cmucal_vclk_ip_gpc_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_THSTAT, NULL, cmucal_vclk_ip_ssmt_thstat, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_IPP_DNS, NULL, cmucal_vclk_ip_lh_axi_si_ld_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_MSA, NULL, cmucal_vclk_ip_ppmu_msa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ALIGN0, NULL, cmucal_vclk_ip_qe_align0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ALIGN1, NULL, cmucal_vclk_ip_qe_align1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ALIGN0, NULL, cmucal_vclk_ip_ssmt_align0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ALIGN1, NULL, cmucal_vclk_ip_ssmt_align1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D1_IPP, NULL, cmucal_vclk_ip_xiu_d1_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TNR_A, NULL, cmucal_vclk_ip_tnr_a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_THSTAT, NULL, cmucal_vclk_ip_qe_thstat, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF2_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf2_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_IPP_DNS, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_ipp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D2_IPP, NULL, cmucal_vclk_ip_xiu_d2_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D0_IPP, NULL, cmucal_vclk_ip_xiu_d0_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_FDPIG, NULL, cmucal_vclk_ip_ssmt_fdpig, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_RGBH0, NULL, cmucal_vclk_ip_ssmt_rgbh0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_RGBH1, NULL, cmucal_vclk_ip_ssmt_rgbh1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_RGBH2, NULL, cmucal_vclk_ip_ssmt_rgbh2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ALIGN2, NULL, cmucal_vclk_ip_ssmt_align2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ALIGN3, NULL, cmucal_vclk_ip_ssmt_align3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_FDPIG, NULL, cmucal_vclk_ip_qe_fdpig, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_RGBH0, NULL, cmucal_vclk_ip_qe_rgbh0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_RGBH1, NULL, cmucal_vclk_ip_qe_rgbh1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_RGBH2, NULL, cmucal_vclk_ip_qe_rgbh2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ALIGN2, NULL, cmucal_vclk_ip_qe_align2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ALIGN3, NULL, cmucal_vclk_ip_qe_align3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_TNR_MSA0, NULL, cmucal_vclk_ip_ssmt_tnr_msa0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ALN_STAT, NULL, cmucal_vclk_ip_ssmt_aln_stat, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_TNR_MSA0, NULL, cmucal_vclk_ip_qe_tnr_msa0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ALN_STAT, NULL, cmucal_vclk_ip_qe_aln_stat, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_TNR_MSA1, NULL, cmucal_vclk_ip_ssmt_tnr_msa1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_TNR_MSA1, NULL, cmucal_vclk_ip_qe_tnr_msa1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ITP_CMU_ITP, NULL, cmucal_vclk_ip_itp_cmu_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_ITP, NULL, cmucal_vclk_ip_ad_apb_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_ITP, NULL, cmucal_vclk_ip_d_tzpc_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_ITP, NULL, cmucal_vclk_ip_gpc_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ITP, NULL, cmucal_vclk_ip_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_ITP, NULL, cmucal_vclk_ip_slh_axi_mi_p_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_ITP, NULL, cmucal_vclk_ip_sysreg_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_DNS_ITP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_dns_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_DNS_ITP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_dns_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_ITP_DNS, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_itp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_ITP, NULL, cmucal_vclk_ip_ssmt_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_ITP, NULL, cmucal_vclk_ip_qe_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_ITP, NULL, cmucal_vclk_ip_ppmu_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_ITP_DNS, NULL, cmucal_vclk_ip_lh_axi_si_ld_itp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_MCSC, NULL, cmucal_vclk_ip_slh_axi_mi_p_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_MCSC, NULL, cmucal_vclk_ip_lh_axi_si_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_MCSC, NULL, cmucal_vclk_ip_sysreg_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MCSC_CMU_MCSC, NULL, cmucal_vclk_ip_mcsc_cmu_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_MCSC, NULL, cmucal_vclk_ip_d_tzpc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_MCSC_TNR, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_mcsc_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_MCSC, NULL, cmucal_vclk_ip_gpc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ITSC, NULL, cmucal_vclk_ip_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_MCSC, NULL, cmucal_vclk_ip_ssmt_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_MCSC, NULL, cmucal_vclk_ip_sysmmu_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_MCSC, NULL, cmucal_vclk_ip_ppmu_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_ITSC, NULL, cmucal_vclk_ip_ssmt_d0_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_ITSC, NULL, cmucal_vclk_ip_ppmu_d1_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_ITSC, NULL, cmucal_vclk_ip_ppmu_d0_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_GDC_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_gdc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_MCSC_DNS, NULL, cmucal_vclk_ip_lh_axi_si_ld_mcsc_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_ITSC, NULL, cmucal_vclk_ip_ad_apb_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_MCSC, NULL, cmucal_vclk_ip_ad_apb_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MCSC, NULL, cmucal_vclk_ip_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_MCSC, NULL, cmucal_vclk_ip_lh_axi_si_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_MCSC, NULL, cmucal_vclk_ip_sysmmu_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF2_DNS_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf2_dns_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_I_ITSC_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_i_itsc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_TNR_MCSC, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_tnr_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_I_ITSC_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_i_itsc_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_MCSC_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_mcsc_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_ITSC, NULL, cmucal_vclk_ip_ssmt_d1_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_MCSC, NULL, cmucal_vclk_ip_ppmu_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_MCSC, NULL, cmucal_vclk_ip_ssmt_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_ITSC, NULL, cmucal_vclk_ip_qe_d1_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D2_ITSC, NULL, cmucal_vclk_ip_qe_d2_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D0_MCSC, NULL, cmucal_vclk_ip_qe_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_MCSC, NULL, cmucal_vclk_ip_qe_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D2_MCSC, NULL, cmucal_vclk_ip_qe_d2_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D3_MCSC, NULL, cmucal_vclk_ip_qe_d3_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D2_MCSC, NULL, cmucal_vclk_ip_sysmmu_d2_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D2_MCSC, NULL, cmucal_vclk_ip_lh_axi_si_d2_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D4_MCSC, NULL, cmucal_vclk_ip_qe_d4_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_C2R_MCSC, NULL, cmucal_vclk_ip_c2r_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D3_ITSC, NULL, cmucal_vclk_ip_qe_d3_itsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D5_MCSC, NULL, cmucal_vclk_ip_qe_d5_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MFC_CMU_MFC, NULL, cmucal_vclk_ip_mfc_cmu_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_MFC, NULL, cmucal_vclk_ip_as_apb_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_MFC, NULL, cmucal_vclk_ip_sysreg_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_MFC, NULL, cmucal_vclk_ip_lh_axi_si_d0_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_MFC, NULL, cmucal_vclk_ip_lh_axi_si_d1_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_MFC, NULL, cmucal_vclk_ip_slh_axi_mi_p_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_MFC, NULL, cmucal_vclk_ip_sysmmu_d0_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_MFC, NULL, cmucal_vclk_ip_sysmmu_d1_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_MFC, NULL, cmucal_vclk_ip_ppmu_d0_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_MFC, NULL, cmucal_vclk_ip_ppmu_d1_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_MFC, NULL, cmucal_vclk_ip_ssmt_d0_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MFC, NULL, cmucal_vclk_ip_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_MFC, NULL, cmucal_vclk_ip_d_tzpc_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_MFC, NULL, cmucal_vclk_ip_ssmt_d1_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_MFC, NULL, cmucal_vclk_ip_gpc_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MIF_CMU_MIF, NULL, cmucal_vclk_ip_mif_cmu_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DDRPHY, NULL, cmucal_vclk_ip_ddrphy, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_MIF, NULL, cmucal_vclk_ip_sysreg_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MIF_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_mif_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AXI2APB_P_MIF, NULL, cmucal_vclk_ip_axi2apb_p_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBBR_DDRPHY, NULL, cmucal_vclk_ip_apbbr_ddrphy, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APBBR_DMC, NULL, cmucal_vclk_ip_apbbr_dmc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DMC, NULL, cmucal_vclk_ip_dmc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QCH_ADAPTER_PPC_DEBUG, NULL, cmucal_vclk_ip_qch_adapter_ppc_debug, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_MIF, NULL, cmucal_vclk_ip_gpc_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_MIF, NULL, cmucal_vclk_ip_d_tzpc_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_DEBUG, NULL, cmucal_vclk_ip_ppc_debug, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GEN_WREN_SECURE, NULL, cmucal_vclk_ip_gen_wren_secure, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC_CD, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_MIF, NULL, cmucal_vclk_ip_slh_axi_mi_p_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MIF_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_mif_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC_CD, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_MISC, NULL, cmucal_vclk_ip_sysreg_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_WDT_CLUSTER1, NULL, cmucal_vclk_ip_wdt_cluster1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_WDT_CLUSTER0, NULL, cmucal_vclk_ip_wdt_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_OTP_CON_BIRA, NULL, cmucal_vclk_ip_otp_con_bira, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GIC, NULL, cmucal_vclk_ip_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MCT, NULL, cmucal_vclk_ip_mct, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_OTP_CON_TOP, NULL, cmucal_vclk_ip_otp_con_top, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_MISC, NULL, cmucal_vclk_ip_d_tzpc_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TMU_SUB, NULL, cmucal_vclk_ip_tmu_sub, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TMU_TOP, NULL, cmucal_vclk_ip_tmu_top, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_OTP_CON_BISR, NULL, cmucal_vclk_ip_otp_con_bisr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_DIT, NULL, cmucal_vclk_ip_dit, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MISC_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_misc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_MISC, NULL, cmucal_vclk_ip_lh_acel_si_d_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PDMA0, NULL, cmucal_vclk_ip_pdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_MISC, NULL, cmucal_vclk_ip_ppmu_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_DIT, NULL, cmucal_vclk_ip_qe_dit, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDMA0, NULL, cmucal_vclk_ip_qe_pdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MISC_CMU_MISC, NULL, cmucal_vclk_ip_misc_cmu_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_RTIC, NULL, cmucal_vclk_ip_qe_rtic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_SPDMA0, NULL, cmucal_vclk_ip_qe_spdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_SSS, NULL, cmucal_vclk_ip_qe_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_RTIC, NULL, cmucal_vclk_ip_rtic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SPDMA0, NULL, cmucal_vclk_ip_spdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSS, NULL, cmucal_vclk_ip_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_SSS, NULL, cmucal_vclk_ip_ssmt_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_MISC, NULL, cmucal_vclk_ip_gpc_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_DIT, NULL, cmucal_vclk_ip_ad_apb_dit, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ADM_AHB_G_SSS, NULL, cmucal_vclk_ip_adm_ahb_g_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_PUF, NULL, cmucal_vclk_ip_ad_apb_puf, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU, NULL, cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_ID_SSS, NULL, cmucal_vclk_ip_lh_axi_mi_id_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD, NULL, cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_ID_SSS, NULL, cmucal_vclk_ip_lh_axi_si_id_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PUF, NULL, cmucal_vclk_ip_puf, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D_MISC, NULL, cmucal_vclk_ip_xiu_d_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_MISC, NULL, cmucal_vclk_ip_sysmmu_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_SSS, NULL, cmucal_vclk_ip_sysmmu_sss, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_GIC_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_gic_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_RTIC, NULL, cmucal_vclk_ip_ssmt_rtic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_SPDMA0, NULL, cmucal_vclk_ip_ssmt_spdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PDMA0, NULL, cmucal_vclk_ip_ssmt_pdma0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_DIT, NULL, cmucal_vclk_ip_ssmt_dit, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD, NULL, cmucal_vclk_ip_lh_ast_mi_l_iri_gic_cluster0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0, NULL, cmucal_vclk_ip_lh_ast_si_l_iri_gic_cluster0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC, NULL, cmucal_vclk_ip_lh_ast_mi_l_icc_cluster0_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU, NULL, cmucal_vclk_ip_lh_ast_si_l_icc_cluster0_gic_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_MISC, NULL, cmucal_vclk_ip_slh_axi_mi_p_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MISC_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_misc_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SPDMA1, NULL, cmucal_vclk_ip_spdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDMA1, NULL, cmucal_vclk_ip_qe_pdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_SPDMA1, NULL, cmucal_vclk_ip_qe_spdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PDMA1, NULL, cmucal_vclk_ip_ssmt_pdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_SPDMA1, NULL, cmucal_vclk_ip_ssmt_spdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PDMA1, NULL, cmucal_vclk_ip_pdma1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_GIC, NULL, cmucal_vclk_ip_slh_axi_mi_p_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_GIC_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_gic_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_NOCL0_CMU_NOCL0, NULL, cmucal_vclk_ip_nocl0_cmu_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_NOCL0, NULL, cmucal_vclk_ip_sysreg_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_P_NOCL0, NULL, cmucal_vclk_ip_trex_p_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACE_MI_D0_CPUCL0, NULL, cmucal_vclk_ip_lh_ace_mi_d0_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACE_MI_D1_CPUCL0, NULL, cmucal_vclk_ip_lh_ace_mi_d1_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_D_NOCL0, NULL, cmucal_vclk_ip_trex_d_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_CCI, NULL, cmucal_vclk_ip_ad_apb_cci, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_NOCL0, NULL, cmucal_vclk_ip_d_tzpc_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BDU, NULL, cmucal_vclk_ip_bdu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_NOCL0, NULL, cmucal_vclk_ip_gpc_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_ACE_CPUCL0_D0, NULL, cmucal_vclk_ip_ppmu_ace_cpucl0_d0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_ACE_CPUCL0_D1, NULL, cmucal_vclk_ip_ppmu_ace_cpucl0_d1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SFR_APBIF_CMU_TOPC, NULL, cmucal_vclk_ip_sfr_apbif_cmu_topc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1A_M0_EVENT, NULL, cmucal_vclk_ip_ppc_nocl1a_m0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1A_M1_EVENT, NULL, cmucal_vclk_ip_ppc_nocl1a_m1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1A_M2_EVENT, NULL, cmucal_vclk_ip_ppc_nocl1a_m2_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1A_M3_EVENT, NULL, cmucal_vclk_ip_ppc_nocl1a_m3_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1B_M0_EVENT, NULL, cmucal_vclk_ip_ppc_nocl1b_m0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CPUCL0_D0_CYCLE, NULL, cmucal_vclk_ip_ppc_cpucl0_d0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLC_CB_TOP, NULL, cmucal_vclk_ip_slc_cb_top, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CCI, NULL, cmucal_vclk_ip_cci, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_EH, NULL, cmucal_vclk_ip_lh_acel_mi_d_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_EH_CYCLE, NULL, cmucal_vclk_ip_ppc_eh_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_IO_EVENT, NULL, cmucal_vclk_ip_ppc_io_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_EH_EVENT, NULL, cmucal_vclk_ip_ppc_eh_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CPUCL0_D0_EVENT, NULL, cmucal_vclk_ip_ppc_cpucl0_d0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CCI_M1_EVENT, NULL, cmucal_vclk_ip_ppc_cci_m1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CCI_M2_EVENT, NULL, cmucal_vclk_ip_ppc_cci_m2_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CCI_M3_EVENT, NULL, cmucal_vclk_ip_ppc_cci_m3_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CCI_M4_EVENT, NULL, cmucal_vclk_ip_ppc_cci_m4_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_IO_CYCLE, NULL, cmucal_vclk_ip_ppc_io_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CCI_M1_CYCLE, NULL, cmucal_vclk_ip_ppc_cci_m1_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1A_M0_CYCLE, NULL, cmucal_vclk_ip_ppc_nocl1a_m0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL1B_M0_CYCLE, NULL, cmucal_vclk_ip_ppc_nocl1b_m0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_DBG_CC, NULL, cmucal_vclk_ip_ppc_dbg_cc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MPACE_ASB_D0_MIF, NULL, cmucal_vclk_ip_mpace_asb_d0_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MPACE_ASB_D1_MIF, NULL, cmucal_vclk_ip_mpace_asb_d1_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MPACE_ASB_D2_MIF, NULL, cmucal_vclk_ip_mpace_asb_d2_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_MPACE_ASB_D3_MIF, NULL, cmucal_vclk_ip_mpace_asb_d3_mif, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_CPUCL0_D1_EVENT, NULL, cmucal_vclk_ip_ppc_cpucl0_d1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLC_CH_TOP, NULL, cmucal_vclk_ip_slc_ch_top, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLC_CH1, NULL, cmucal_vclk_ip_slc_ch1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLC_CH2, NULL, cmucal_vclk_ip_slc_ch2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLC_CH3, NULL, cmucal_vclk_ip_slc_ch3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_CPE425, NULL, cmucal_vclk_ip_cpe425, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GRAY2BIN_ATB_TSVALUE, NULL, cmucal_vclk_ip_gray2bin_atb_tsvalue, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_G_NOCL0, NULL, cmucal_vclk_ip_slh_axi_mi_g_nocl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC0_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1A_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1a_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC1_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC2_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc2_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC3_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc3_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1B_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1b_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL2A_CU, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl2a_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ASYNCSFR_WR_SMC, NULL, cmucal_vclk_ip_asyncsfr_wr_smc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_ALIVE, NULL, cmucal_vclk_ip_slh_axi_si_p_alive, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_CPUCL0, NULL, cmucal_vclk_ip_slh_axi_si_p_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_EH, NULL, cmucal_vclk_ip_slh_axi_si_p_eh, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_GIC, NULL, cmucal_vclk_ip_slh_axi_si_p_gic, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MIF0, NULL, cmucal_vclk_ip_slh_axi_si_p_mif0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MIF1, NULL, cmucal_vclk_ip_slh_axi_si_p_mif1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MIF2, NULL, cmucal_vclk_ip_slh_axi_si_p_mif2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MIF3, NULL, cmucal_vclk_ip_slh_axi_si_p_mif3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MISC, NULL, cmucal_vclk_ip_slh_axi_si_p_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_PERIC0, NULL, cmucal_vclk_ip_slh_axi_si_p_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_PERIC1, NULL, cmucal_vclk_ip_slh_axi_si_p_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_BDU, NULL, cmucal_vclk_ip_lh_atb_si_t_bdu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_SLC, NULL, cmucal_vclk_ip_lh_atb_si_t_slc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_ALIVE_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_alive_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_EH_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_eh_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_GIC_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_gic_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MIF0_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_mif0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MIF1_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_mif1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MIF2_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_mif2_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MIF3_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_mif3_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_MISC_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_misc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_PERIC0_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_peric0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_PERIC1_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_peric1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_BDU_CD, NULL, cmucal_vclk_ip_lh_atb_si_t_bdu_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_T_SLC_CD, NULL, cmucal_vclk_ip_lh_atb_si_t_slc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_ALIVE_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_alive_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_EH_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_eh_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_GIC_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_gic_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MIF0_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_mif0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MIF1_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_mif1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MIF2_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_mif2_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MIF3_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_mif3_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_MISC_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_misc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_PERIC0_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_peric0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_PERIC1_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_peric1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_BDU_CD, NULL, cmucal_vclk_ip_lh_atb_mi_t_bdu_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_T_SLC_CD, NULL, cmucal_vclk_ip_lh_atb_mi_t_slc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC0, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC0_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC1, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC1_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC2, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC2_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc2_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_DMC3, NULL, cmucal_vclk_ip_lh_ast_mi_g_dmc3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_DMC3_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_dmc3_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1A, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1B, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL2A, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1A_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1a_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1B_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1b_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL2A_CU, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl2a_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_NOCL1A_CMU_NOCL1A, NULL, cmucal_vclk_ip_nocl1a_cmu_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_D_NOCL1A, NULL, cmucal_vclk_ip_trex_d_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_NOCL1A, NULL, cmucal_vclk_ip_sysreg_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D0_G3D, NULL, cmucal_vclk_ip_lh_acel_mi_d0_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_NOCL1A, NULL, cmucal_vclk_ip_d_tzpc_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D1_G3D, NULL, cmucal_vclk_ip_lh_acel_mi_d1_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D2_G3D, NULL, cmucal_vclk_ip_lh_acel_mi_d2_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D3_G3D, NULL, cmucal_vclk_ip_lh_acel_mi_d3_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_G3D0, NULL, cmucal_vclk_ip_ssmt_g3d0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_TPU, NULL, cmucal_vclk_ip_lh_acel_mi_d_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_G3D, NULL, cmucal_vclk_ip_sysmmu_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_G3D_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_g3d_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_NOCL1A, NULL, cmucal_vclk_ip_gpc_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_G3D1, NULL, cmucal_vclk_ip_ssmt_g3d1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_G3D2, NULL, cmucal_vclk_ip_ssmt_g3d2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_G3D3, NULL, cmucal_vclk_ip_ssmt_g3d3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPCFW_G3D0, NULL, cmucal_vclk_ip_ppcfw_g3d0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_SYSMMU_G3D, NULL, cmucal_vclk_ip_ad_apb_sysmmu_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_P_NOCL1A, NULL, cmucal_vclk_ip_trex_p_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1A_CD, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1a_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL2A_M0_EVENT, NULL, cmucal_vclk_ip_ppc_nocl2a_m0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL2A_M1_EVENT, NULL, cmucal_vclk_ip_ppc_nocl2a_m1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL2A_M2_EVENT, NULL, cmucal_vclk_ip_ppc_nocl2a_m2_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL2A_M3_EVENT, NULL, cmucal_vclk_ip_ppc_nocl2a_m3_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_G3D_D0_EVENT, NULL, cmucal_vclk_ip_ppc_g3d_d0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_G3D_D1_EVENT, NULL, cmucal_vclk_ip_ppc_g3d_d1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_G3D_D2_EVENT, NULL, cmucal_vclk_ip_ppc_g3d_d2_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_G3D_D3_EVENT, NULL, cmucal_vclk_ip_ppc_g3d_d3_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_TPU_EVENT, NULL, cmucal_vclk_ip_ppc_tpu_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_NOCL2A_M0_CYCLE, NULL, cmucal_vclk_ip_ppc_nocl2a_m0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_G3D_D0_CYCLE, NULL, cmucal_vclk_ip_ppc_g3d_d0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_TPU_CYCLE, NULL, cmucal_vclk_ip_ppc_tpu_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPCFW_G3D1, NULL, cmucal_vclk_ip_ppcfw_g3d1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_AUR, NULL, cmucal_vclk_ip_lh_axi_mi_d0_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_AUR, NULL, cmucal_vclk_ip_lh_axi_mi_d1_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_AUR_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_aur_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_AUR_D0_EVENT, NULL, cmucal_vclk_ip_ppc_aur_d0_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_AUR_D1_EVENT, NULL, cmucal_vclk_ip_ppc_aur_d1_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_AUR_D0_CYCLE, NULL, cmucal_vclk_ip_ppc_aur_d0_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1A_CD, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1a_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1A, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_AUR_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_aur_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_AUR, NULL, cmucal_vclk_ip_slh_axi_si_p_aur, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_G3D_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_g3d_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_G3D, NULL, cmucal_vclk_ip_slh_axi_si_p_g3d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_TPU_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_tpu_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_TPU_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_tpu_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_TPU, NULL, cmucal_vclk_ip_slh_axi_si_p_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_NOCL1B_CMU_NOCL1B, NULL, cmucal_vclk_ip_nocl1b_cmu_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_D_NOCL1B, NULL, cmucal_vclk_ip_trex_d_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_NOCL1B, NULL, cmucal_vclk_ip_d_tzpc_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_HSI0, NULL, cmucal_vclk_ip_lh_acel_mi_d_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_HSI1, NULL, cmucal_vclk_ip_lh_acel_mi_d_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_AOC, NULL, cmucal_vclk_ip_lh_axi_mi_d_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_APM, NULL, cmucal_vclk_ip_lh_axi_mi_d_apm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_GSA, NULL, cmucal_vclk_ip_lh_axi_mi_d_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_GSA_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_gsa_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI0_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI1_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_NOCL1B, NULL, cmucal_vclk_ip_sysreg_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_P_NOCL1B, NULL, cmucal_vclk_ip_trex_p_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_NOCL1B, NULL, cmucal_vclk_ip_gpc_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_G_CSSYS_CU, NULL, cmucal_vclk_ip_lh_axi_mi_g_cssys_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1B_CD, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1b_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_AOC_EVENT, NULL, cmucal_vclk_ip_ppc_aoc_event, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPC_AOC_CYCLE, NULL, cmucal_vclk_ip_ppc_aoc_cycle, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL1B_CD, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl1b_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL1B, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl1b, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_AOC_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_aoc_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_AOC, NULL, cmucal_vclk_ip_slh_axi_si_p_aoc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_GSA_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_gsa_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_GSA, NULL, cmucal_vclk_ip_slh_axi_si_p_gsa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI0_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_HSI0, NULL, cmucal_vclk_ip_slh_axi_si_p_hsi0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI1_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi1_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_HSI1, NULL, cmucal_vclk_ip_slh_axi_si_p_hsi1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_G_CSSYS, NULL, cmucal_vclk_ip_slh_axi_mi_g_cssys, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_G_CSSYS_CU, NULL, cmucal_vclk_ip_lh_axi_si_g_cssys_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_NOCL2A_CMU_NOCL2A, NULL, cmucal_vclk_ip_nocl2a_cmu_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_NOCL2A, NULL, cmucal_vclk_ip_sysreg_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_G2D, NULL, cmucal_vclk_ip_lh_axi_mi_d0_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_G2D, NULL, cmucal_vclk_ip_lh_axi_mi_d1_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D2_G2D, NULL, cmucal_vclk_ip_lh_acel_mi_d2_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_CSIS, NULL, cmucal_vclk_ip_lh_axi_mi_d0_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_MISC, NULL, cmucal_vclk_ip_lh_acel_mi_d_misc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_DPU, NULL, cmucal_vclk_ip_lh_axi_mi_d0_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_MFC, NULL, cmucal_vclk_ip_lh_axi_mi_d0_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_DPU, NULL, cmucal_vclk_ip_lh_axi_mi_d1_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_MFC, NULL, cmucal_vclk_ip_lh_axi_mi_d1_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D2_DPU, NULL, cmucal_vclk_ip_lh_axi_mi_d2_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_HSI2_CD, NULL, cmucal_vclk_ip_lh_axi_si_p_hsi2_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_CSIS, NULL, cmucal_vclk_ip_lh_axi_mi_d1_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_MI_D_HSI2, NULL, cmucal_vclk_ip_lh_acel_mi_d_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_BO, NULL, cmucal_vclk_ip_lh_axi_mi_d_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_NOCL2A, NULL, cmucal_vclk_ip_d_tzpc_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_D_NOCL2A, NULL, cmucal_vclk_ip_trex_d_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_BO, NULL, cmucal_vclk_ip_slh_axi_si_p_bo, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_NOCL2A, NULL, cmucal_vclk_ip_gpc_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_G3AA, NULL, cmucal_vclk_ip_lh_axi_mi_d_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_DNS, NULL, cmucal_vclk_ip_lh_axi_mi_d_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D_IPP, NULL, cmucal_vclk_ip_lh_axi_mi_d_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_MCSC, NULL, cmucal_vclk_ip_lh_axi_mi_d0_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_TNR, NULL, cmucal_vclk_ip_lh_axi_mi_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_MCSC, NULL, cmucal_vclk_ip_lh_axi_mi_d1_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_TNR, NULL, cmucal_vclk_ip_lh_axi_mi_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TREX_P_NOCL2A, NULL, cmucal_vclk_ip_trex_p_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D0_GDC, NULL, cmucal_vclk_ip_lh_axi_mi_d0_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D1_GDC, NULL, cmucal_vclk_ip_lh_axi_mi_d1_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D2_GDC, NULL, cmucal_vclk_ip_lh_axi_mi_d2_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D2_TNR, NULL, cmucal_vclk_ip_lh_axi_mi_d2_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D3_TNR, NULL, cmucal_vclk_ip_lh_axi_mi_d3_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL2A_CD, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl2a_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D2_MCSC, NULL, cmucal_vclk_ip_lh_axi_mi_d2_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_D4_TNR, NULL, cmucal_vclk_ip_lh_axi_mi_d4_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_G_NOCL2A_CD, NULL, cmucal_vclk_ip_lh_ast_mi_g_nocl2a_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_G_NOCL2A, NULL, cmucal_vclk_ip_lh_ast_si_g_nocl2a, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_HSI2_CD, NULL, cmucal_vclk_ip_lh_axi_mi_p_hsi2_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_HSI2, NULL, cmucal_vclk_ip_slh_axi_si_p_hsi2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_DPU, NULL, cmucal_vclk_ip_slh_axi_si_p_dpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_CSIS, NULL, cmucal_vclk_ip_slh_axi_si_p_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_G3AA, NULL, cmucal_vclk_ip_slh_axi_si_p_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_IPP, NULL, cmucal_vclk_ip_slh_axi_si_p_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_DNS, NULL, cmucal_vclk_ip_slh_axi_si_p_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_ITP, NULL, cmucal_vclk_ip_slh_axi_si_p_itp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MCSC, NULL, cmucal_vclk_ip_slh_axi_si_p_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_TNR, NULL, cmucal_vclk_ip_slh_axi_si_p_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_MFC, NULL, cmucal_vclk_ip_slh_axi_si_p_mfc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_G2D, NULL, cmucal_vclk_ip_slh_axi_si_p_g2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_GDC, NULL, cmucal_vclk_ip_slh_axi_si_p_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_DISP, NULL, cmucal_vclk_ip_slh_axi_si_p_disp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_SI_P_PDP, NULL, cmucal_vclk_ip_slh_axi_si_p_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PDP_CMU_PDP, NULL, cmucal_vclk_ip_pdp_cmu_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_PDP, NULL, cmucal_vclk_ip_d_tzpc_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF0_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf0_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF1_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf1_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF2_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf2_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_PDP, NULL, cmucal_vclk_ip_slh_axi_mi_p_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_PDP, NULL, cmucal_vclk_ip_gpc_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PDP_TOP, NULL, cmucal_vclk_ip_pdp_top, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_PDP_STAT, NULL, cmucal_vclk_ip_ssmt_pdp_stat, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDP_STAT0, NULL, cmucal_vclk_ip_qe_pdp_stat0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_C2_PDP, NULL, cmucal_vclk_ip_ad_apb_c2_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF2_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF2_PDP_CSIS, NULL, cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF0_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_si_l_otf0_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF1_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_si_l_otf1_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF2_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_si_l_otf2_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_YOTF0_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_si_l_yotf0_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_YOTF1_PDP_G3AA, NULL, cmucal_vclk_ip_lh_ast_si_l_yotf1_pdp_g3aa, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_CSIS_PDP, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_csis_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_PDP_IPP, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_pdp_ipp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_PDP_CSIS, NULL, cmucal_vclk_ip_lh_axi_si_ld_pdp_csis, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_PDP, NULL, cmucal_vclk_ip_sysreg_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D_PDP, NULL, cmucal_vclk_ip_xiu_d_pdp, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDP_STAT1, NULL, cmucal_vclk_ip_qe_pdp_stat1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDP_AF0, NULL, cmucal_vclk_ip_qe_pdp_af0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_PDP_AF1, NULL, cmucal_vclk_ip_qe_pdp_af1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AD_APB_VRA, NULL, cmucal_vclk_ip_ad_apb_vra, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_VRA, NULL, cmucal_vclk_ip_qe_vra, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_VRA, NULL, cmucal_vclk_ip_vra, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_VRA, NULL, cmucal_vclk_ip_ssmt_vra, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LD_PDP_DNS, NULL, cmucal_vclk_ip_lh_axi_si_ld_pdp_dns, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_VRA, NULL, cmucal_vclk_ip_ppmu_vra, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_PERIC0, NULL, cmucal_vclk_ip_gpio_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_PERIC0, NULL, cmucal_vclk_ip_sysreg_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PERIC0_CMU_PERIC0, NULL, cmucal_vclk_ip_peric0_cmu_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_PERIC0_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_peric0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_PERIC0, NULL, cmucal_vclk_ip_d_tzpc_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_PERIC0, NULL, cmucal_vclk_ip_gpc_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI1_USI, NULL, cmucal_vclk_ip_usi1_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI2_USI, NULL, cmucal_vclk_ip_usi2_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI3_USI, NULL, cmucal_vclk_ip_usi3_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI4_USI, NULL, cmucal_vclk_ip_usi4_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI5_USI, NULL, cmucal_vclk_ip_usi5_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI6_USI, NULL, cmucal_vclk_ip_usi6_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI7_USI, NULL, cmucal_vclk_ip_usi7_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI8_USI, NULL, cmucal_vclk_ip_usi8_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C1, NULL, cmucal_vclk_ip_i3c1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C2, NULL, cmucal_vclk_ip_i3c2, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C3, NULL, cmucal_vclk_ip_i3c3, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C4, NULL, cmucal_vclk_ip_i3c4, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C5, NULL, cmucal_vclk_ip_i3c5, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C6, NULL, cmucal_vclk_ip_i3c6, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C7, NULL, cmucal_vclk_ip_i3c7, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C8, NULL, cmucal_vclk_ip_i3c8, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI0_UART, NULL, cmucal_vclk_ip_usi0_uart, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI14_USI, NULL, cmucal_vclk_ip_usi14_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_PERIC0, NULL, cmucal_vclk_ip_slh_axi_mi_p_peric0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_PERIC0_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_peric0_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPIO_PERIC1, NULL, cmucal_vclk_ip_gpio_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_PERIC1, NULL, cmucal_vclk_ip_sysreg_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PERIC1_CMU_PERIC1, NULL, cmucal_vclk_ip_peric1_cmu_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_PERIC1_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_peric1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_PERIC1, NULL, cmucal_vclk_ip_d_tzpc_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_PERIC1, NULL, cmucal_vclk_ip_gpc_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI0_USI, NULL, cmucal_vclk_ip_usi0_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI9_USI, NULL, cmucal_vclk_ip_usi9_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI10_USI, NULL, cmucal_vclk_ip_usi10_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI11_USI, NULL, cmucal_vclk_ip_usi11_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI12_USI, NULL, cmucal_vclk_ip_usi12_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI13_USI, NULL, cmucal_vclk_ip_usi13_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_I3C0, NULL, cmucal_vclk_ip_i3c0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PWM, NULL, cmucal_vclk_ip_pwm, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_PERIC1, NULL, cmucal_vclk_ip_slh_axi_mi_p_peric1, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_PERIC1_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_peric1_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI15_USI, NULL, cmucal_vclk_ip_usi15_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_USI16_USI, NULL, cmucal_vclk_ip_usi16_usi, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_S2D_CMU_S2D, NULL, cmucal_vclk_ip_s2d_cmu_s2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BIS_S2D, NULL, cmucal_vclk_ip_bis_s2d, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_LG_SCAN2DRAM_CU, NULL, cmucal_vclk_ip_lh_axi_mi_lg_scan2dram_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_LG_SCAN2DRAM, NULL, cmucal_vclk_ip_slh_axi_mi_lg_scan2dram, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CU, NULL, cmucal_vclk_ip_lh_axi_si_lg_scan2dram_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_APB_ASYNC_SYSMMU_D0_S1_NS_TNR, NULL, cmucal_vclk_ip_apb_async_sysmmu_d0_s1_ns_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_TNR, NULL, cmucal_vclk_ip_d_tzpc_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_VO_DNS_TNR, NULL, cmucal_vclk_ip_lh_ast_mi_l_vo_dns_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_TNR, NULL, cmucal_vclk_ip_slh_axi_mi_p_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_TNR_MCSC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_tnr_mcsc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D0_TNR, NULL, cmucal_vclk_ip_lh_axi_si_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D1_TNR, NULL, cmucal_vclk_ip_lh_axi_si_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D0_TNR, NULL, cmucal_vclk_ip_ppmu_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D1_TNR, NULL, cmucal_vclk_ip_ppmu_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D0_TNR, NULL, cmucal_vclk_ip_sysmmu_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D1_TNR, NULL, cmucal_vclk_ip_sysmmu_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_TNR, NULL, cmucal_vclk_ip_sysreg_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TNR_CMU_TNR, NULL, cmucal_vclk_ip_tnr_cmu_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_VO_TNR_GDC, NULL, cmucal_vclk_ip_lh_ast_si_l_vo_tnr_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TNR, NULL, cmucal_vclk_ip_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_MI_L_OTF_MCSC_TNR, NULL, cmucal_vclk_ip_lh_ast_mi_l_otf_mcsc_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D2_TNR, NULL, cmucal_vclk_ip_lh_axi_si_d2_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D3_TNR, NULL, cmucal_vclk_ip_lh_axi_si_d3_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D2_TNR, NULL, cmucal_vclk_ip_ppmu_d2_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D3_TNR, NULL, cmucal_vclk_ip_ppmu_d3_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D2_TNR, NULL, cmucal_vclk_ip_sysmmu_d2_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D3_TNR, NULL, cmucal_vclk_ip_sysmmu_d3_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D4_TNR, NULL, cmucal_vclk_ip_ppmu_d4_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D5_TNR, NULL, cmucal_vclk_ip_ppmu_d5_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D6_TNR, NULL, cmucal_vclk_ip_ppmu_d6_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D7_TNR, NULL, cmucal_vclk_ip_ppmu_d7_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D0_TNR, NULL, cmucal_vclk_ip_xiu_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_XIU_D1_TNR, NULL, cmucal_vclk_ip_xiu_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D0_TNR, NULL, cmucal_vclk_ip_qe_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D1_TNR, NULL, cmucal_vclk_ip_qe_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D5_TNR, NULL, cmucal_vclk_ip_qe_d5_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D6_TNR, NULL, cmucal_vclk_ip_qe_d6_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D7_TNR, NULL, cmucal_vclk_ip_qe_d7_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D0_TNR, NULL, cmucal_vclk_ip_ssmt_d0_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D1_TNR, NULL, cmucal_vclk_ip_ssmt_d1_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D2_TNR, NULL, cmucal_vclk_ip_ssmt_d2_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D3_TNR, NULL, cmucal_vclk_ip_ssmt_d3_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_D4_TNR, NULL, cmucal_vclk_ip_lh_axi_si_d4_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_D4_TNR, NULL, cmucal_vclk_ip_sysmmu_d4_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D4_TNR, NULL, cmucal_vclk_ip_ssmt_d4_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D5_TNR, NULL, cmucal_vclk_ip_ssmt_d5_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D6_TNR, NULL, cmucal_vclk_ip_ssmt_d6_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D7_TNR, NULL, cmucal_vclk_ip_ssmt_d7_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_TNR, NULL, cmucal_vclk_ip_gpc_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AST_SI_L_OTF_TNR_GDC, NULL, cmucal_vclk_ip_lh_ast_si_l_otf_tnr_gdc, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_D8_TNR, NULL, cmucal_vclk_ip_ssmt_d8_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_QE_D8_TNR, NULL, cmucal_vclk_ip_qe_d8_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_D8_TNR, NULL, cmucal_vclk_ip_ppmu_d8_tnr, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TPU_CMU_TPU, NULL, cmucal_vclk_ip_tpu_cmu_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_MI_P_TPU_CU, NULL, cmucal_vclk_ip_lh_axi_mi_p_tpu_cu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_D_TZPC_TPU, NULL, cmucal_vclk_ip_d_tzpc_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ACEL_SI_D_TPU, NULL, cmucal_vclk_ip_lh_acel_si_d_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSREG_TPU, NULL, cmucal_vclk_ip_sysreg_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SYSMMU_TPU, NULL, cmucal_vclk_ip_sysmmu_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_PPMU_TPU, NULL, cmucal_vclk_ip_ppmu_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SSMT_TPU, NULL, cmucal_vclk_ip_ssmt_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_GPC_TPU, NULL, cmucal_vclk_ip_gpc_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_AS_APB_SYSMMU_NS_TPU, NULL, cmucal_vclk_ip_as_apb_sysmmu_ns_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_TPU, NULL, cmucal_vclk_ip_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0, NULL, cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ASYNC_APBM_TPU, NULL, cmucal_vclk_ip_async_apbm_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_ASYNC_APB_INT_TPU, NULL, cmucal_vclk_ip_async_apb_int_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_mi_lt0_tpu_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_mi_lt1_tpu_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_HPM_TPU, NULL, cmucal_vclk_ip_hpm_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BUSIF_HPMTPU, NULL, cmucal_vclk_ip_busif_hpmtpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_si_lt0_tpu_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CD, NULL, cmucal_vclk_ip_lh_atb_si_lt1_tpu_cpucl0_cd, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_BUSIF_DDDTPU, NULL, cmucal_vclk_ip_busif_dddtpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_SLH_AXI_MI_P_TPU, NULL, cmucal_vclk_ip_slh_axi_mi_p_tpu, NULL, NULL), + CMUCAL_VCLK(VCLK_IP_LH_AXI_SI_P_TPU_CU, NULL, cmucal_vclk_ip_lh_axi_si_p_tpu_cu, NULL, NULL), +}; + diff --git a/drivers/soc/google/cal-if/gs201/cmucal-vclk.h b/drivers/soc/google/cal-if/gs201/cmucal-vclk.h new file mode 100644 index 000000000000..486a256ceadd --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-vclk.h @@ -0,0 +1,1323 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMUCAL_VCLK_H__ +#define __CMUCAL_VCLK_H__ + +#include "../cmucal.h" + +enum vclk_id { + +/* DVFS VCLK*/ + VCLK_VDD_INT = DFS_VCLK_TYPE, + VCLK_VDD_MIF, + VCLK_VDD_G3D, + VCLK_VDD_CAM, + VCLK_VDD_CPUCL0, + VCLK_VDD_CPUCL1, + VCLK_VDD_TPU, + VCLK_VDD_CPUCL2, + end_of_dfs_vclk, + num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE, + + +/* SPECIAL VCLK*/ + VCLK_MUX_CMU_CMUREF = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE, + VCLK_MUX_CPUCL1_CMUREF, + VCLK_MUX_CPUCL2_CMUREF, + VCLK_MUX_CLK_HSI0_USB20_REF, + VCLK_MUX_CLKCMU_HSI0_USBDPDBG, + VCLK_MUX_MIF_CMUREF, + VCLK_MUX_NOCL0_CMUREF, + VCLK_MUX_NOCL1B_CMUREF, + VCLK_MUX_NOCL2A_CMUREF, + VCLK_CLKCMU_HSI0_DPGTC, + VCLK_CLKCMU_TPU_UART, + VCLK_DIV_CLK_APM_USI0_USI, + VCLK_DIV_CLK_APM_USI0_UART, + VCLK_DIV_CLK_APM_USI1_UART, + VCLK_DIV_CLK_APM_I3C_PMIC, + VCLK_CLK_AUR_ADD_CH_CLK, + VCLK_CLKCMU_HPM, + VCLK_MUX_CLKCMU_CIS_CLK0, + VCLK_MUX_CLKCMU_CIS_CLK1, + VCLK_MUX_CLKCMU_CIS_CLK2, + VCLK_MUX_CLKCMU_CIS_CLK3, + VCLK_MUX_CLKCMU_CIS_CLK4, + VCLK_MUX_CLKCMU_CIS_CLK5, + VCLK_MUX_CLKCMU_CIS_CLK6, + VCLK_MUX_CLKCMU_CIS_CLK7, + VCLK_DIV_CLK_CPUCL0_CMUREF, + VCLK_DIV_CLK_CPUCL1_CMUREF, + VCLK_DIV_CLK_CPUCL2_CMUREF, + VCLK_CLK_G3D_ADD_CH_CLK, + VCLK_DIV_CLK_GSACORE_SPI_FPS, + VCLK_DIV_CLK_GSACORE_SPI_GSC, + VCLK_DIV_CLK_GSACORE_UART, + VCLK_DIV_CLK_SLC_DCLK, + VCLK_DIV_CLK_SLC1_DCLK, + VCLK_DIV_CLK_SLC2_DCLK, + VCLK_DIV_CLK_SLC3_DCLK, + VCLK_DIV_CLK_PERIC0_USI6_USI, + VCLK_MUX_CLKCMU_PERIC0_IP, + VCLK_DIV_CLK_PERIC0_USI3_USI, + VCLK_DIV_CLK_PERIC0_USI4_USI, + VCLK_DIV_CLK_PERIC0_USI5_USI, + VCLK_DIV_CLK_PERIC0_USI14_USI, + VCLK_DIV_CLK_PERIC0_USI7_USI, + VCLK_DIV_CLK_PERIC0_USI8_USI, + VCLK_DIV_CLK_PERIC0_USI1_USI, + VCLK_DIV_CLK_PERIC0_USI0_UART, + VCLK_DIV_CLK_PERIC0_USI2_USI, + VCLK_DIV_CLK_PERIC1_USI11_USI, + VCLK_MUX_CLKCMU_PERIC1_IP, + VCLK_DIV_CLK_PERIC1_I3C, + VCLK_DIV_CLK_PERIC1_USI12_USI, + VCLK_DIV_CLK_PERIC1_USI0_USI, + VCLK_DIV_CLK_PERIC1_USI9_USI, + VCLK_DIV_CLK_PERIC1_USI10_USI, + VCLK_DIV_CLK_PERIC1_USI13_USI, + VCLK_DIV_CLK_PERIC1_USI15_USI, + VCLK_DIV_CLK_PERIC1_USI16_USI, + end_of_vclk, + num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE), + + +/* COMMON VCLK*/ + VCLK_BLK_CMU = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE, + VCLK_BLK_HSI0, + VCLK_BLK_S2D, + VCLK_BLK_APM, + VCLK_BLK_CPUCL0, + VCLK_BLK_CPUCL1, + VCLK_BLK_CPUCL2, + VCLK_BLK_EH, + VCLK_BLK_GSACORE, + VCLK_BLK_GSACTRL, + VCLK_BLK_NOCL0, + VCLK_BLK_NOCL1B, + VCLK_BLK_AOC, + VCLK_BLK_AUR, + VCLK_BLK_BO, + VCLK_BLK_CSIS, + VCLK_BLK_DISP, + VCLK_BLK_DNS, + VCLK_BLK_DPU, + VCLK_BLK_G2D, + VCLK_BLK_G3AA, + VCLK_BLK_G3D, + VCLK_BLK_GDC, + VCLK_BLK_HSI1, + VCLK_BLK_HSI2, + VCLK_BLK_IPP, + VCLK_BLK_ITP, + VCLK_BLK_MCSC, + VCLK_BLK_MIF, + VCLK_BLK_MISC, + VCLK_BLK_NOCL1A, + VCLK_BLK_NOCL2A, + VCLK_BLK_PDP, + VCLK_BLK_PERIC0, + VCLK_BLK_PERIC1, + VCLK_BLK_TNR, + VCLK_BLK_TPU, + end_of_common_vclk, + num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE), + + +/* GATE VCLK*/ + VCLK_IP_AOC_CMU_AOC = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE, + VCLK_IP_BAAW_AOC, + VCLK_IP_D_TZPC_AOC, + VCLK_IP_GPC_AOC, + VCLK_IP_LH_AXI_MI_LD_HSI0_AOC, + VCLK_IP_LH_AXI_SI_D_AOC, + VCLK_IP_PPMU_AOC, + VCLK_IP_PPMU_USB, + VCLK_IP_SSMT_AOC, + VCLK_IP_SYSMMU_AOC, + VCLK_IP_SYSREG_AOC, + VCLK_IP_UASC_AOC, + VCLK_IP_XIU_DP_AOC, + VCLK_IP_XIU_P_AOC, + VCLK_IP_AOC_SYSCTRL_APB, + VCLK_IP_LH_AXI_SI_LP0_AOC_CD, + VCLK_IP_LH_AXI_MI_LP0_AOC_CD, + VCLK_IP_LH_AXI_SI_LP1_AOC_CD, + VCLK_IP_LH_AXI_MI_LP1_AOC_CD, + VCLK_IP_SLH_AXI_SI_LP0_AOC, + VCLK_IP_SLH_AXI_SI_LP1_AOC, + VCLK_IP_LH_ATB_SI_LT_AOC, + VCLK_IP_LH_ATB_MI_LT_AOC_CD, + VCLK_IP_SLH_AXI_MI_P_AOC, + VCLK_IP_LH_AXI_SI_P_AOC_CU, + VCLK_IP_LH_AXI_MI_P_AOC_CU, + VCLK_IP_SLH_AXI_MI_LG_AOC, + VCLK_IP_LH_ATB_SI_LT_AOC_CD, + VCLK_IP_LH_AXI_SI_D_APM, + VCLK_IP_WDT_APM, + VCLK_IP_SYSREG_APM, + VCLK_IP_MAILBOX_APM_AP, + VCLK_IP_APBIF_PMU_ALIVE, + VCLK_IP_INTMEM, + VCLK_IP_PMU_INTR_GEN, + VCLK_IP_XIU_DP_ALIVE, + VCLK_IP_APM_CMU_APM, + VCLK_IP_GREBEINTEGRATION, + VCLK_IP_APBIF_GPIO_ALIVE, + VCLK_IP_APBIF_TRTC, + VCLK_IP_D_TZPC_APM, + VCLK_IP_MAILBOX_APM_AOC, + VCLK_IP_MAILBOX_AP_DBGCORE, + VCLK_IP_APBIF_RTC, + VCLK_IP_MAILBOX_APM_GSA, + VCLK_IP_SSMT_D_APM, + VCLK_IP_SSMT_LG_DBGCORE, + VCLK_IP_SYSMMU_D_APM, + VCLK_IP_GPC_APM, + VCLK_IP_UASC_APM, + VCLK_IP_UASC_DBGCORE, + VCLK_IP_UASC_P_ALIVE, + VCLK_IP_UASC_LP0_AOC, + VCLK_IP_APBIF_GPIO_FAR_ALIVE, + VCLK_IP_ROM_CRC32_HOST, + VCLK_IP_SS_DBGCORE, + VCLK_IP_MAILBOX_APM_SWD, + VCLK_IP_MAILBOX_APM_TPU, + VCLK_IP_LH_AXI_MI_IG_SWD, + VCLK_IP_UASC_IG_SWD, + VCLK_IP_APM_USI0_UART, + VCLK_IP_APM_USI1_UART, + VCLK_IP_APM_USI0_USI, + VCLK_IP_MAILBOX_AP_AOCA32, + VCLK_IP_MAILBOX_AP_AOCF1, + VCLK_IP_MAILBOX_AP_AOCP6, + VCLK_IP_MAILBOX_AP_AUR0, + VCLK_IP_MAILBOX_AP_AUR1, + VCLK_IP_MAILBOX_AP_AUR2, + VCLK_IP_MAILBOX_AP_AUR3, + VCLK_IP_APM_I3C_PMIC, + VCLK_IP_APBIF_INTCOMB_VGPIO2PMU, + VCLK_IP_APBIF_INTCOMB_VGPIO2AP, + VCLK_IP_APBIF_INTCOMB_VGPIO2APM, + VCLK_IP_MAILBOX_APM_AUR, + VCLK_IP_SLH_AXI_SI_LG_DBGCORE, + VCLK_IP_SLH_AXI_SI_LG_SCAN2DRAM, + VCLK_IP_SLH_AXI_MI_P_ALIVE, + VCLK_IP_SLH_AXI_MI_LP0_AOC, + VCLK_IP_LH_AXI_SI_LG_DBGCORE_CD, + VCLK_IP_LH_AXI_MI_LG_DBGCORE_CD, + VCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CD, + VCLK_IP_LH_AXI_MI_LG_SCAN2DRAM_CD, + VCLK_IP_LH_AXI_SI_LP0_AOC_CU, + VCLK_IP_LH_AXI_MI_LP0_AOC_CU, + VCLK_IP_LH_AXI_SI_P_ALIVE_CU, + VCLK_IP_LH_AXI_MI_P_ALIVE_CU, + VCLK_IP_AUR_CMU_AUR, + VCLK_IP_AUR, + VCLK_IP_AS_APB_SYSMMU_S1_NS_AUR0, + VCLK_IP_D_TZPC_AUR, + VCLK_IP_GPC_AUR, + VCLK_IP_LH_AXI_SI_D0_AUR, + VCLK_IP_SSMT_D0_AUR, + VCLK_IP_SSMT_D1_AUR, + VCLK_IP_PPMU_D0_AUR, + VCLK_IP_PPMU_D1_AUR, + VCLK_IP_SYSMMU_D0_AUR_WP, + VCLK_IP_SYSMMU_D1_AUR_WP, + VCLK_IP_SYSREG_AUR, + VCLK_IP_UASC_AUR, + VCLK_IP_LH_AXI_SI_D1_AUR, + VCLK_IP_AS_APBM_G_AUR, + VCLK_IP_ADD_APBIF_AUR, + VCLK_IP_BAAW_AUR, + VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0, + VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0_CD, + VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CD, + VCLK_IP_LH_AXI_SI_P_AUR_CU, + VCLK_IP_SLH_AXI_MI_P_AUR, + VCLK_IP_LH_AXI_MI_P_AUR_CU, + VCLK_IP_BO_CMU_BO, + VCLK_IP_LH_AXI_SI_D_BO, + VCLK_IP_SLH_AXI_MI_P_BO, + VCLK_IP_PPMU_BO, + VCLK_IP_SYSMMU_BO, + VCLK_IP_AS_APB_SYSMMU_S1_NS_BO, + VCLK_IP_SYSREG_BO, + VCLK_IP_SSMT_BO, + VCLK_IP_D_TZPC_BO, + VCLK_IP_GPC_BO, + VCLK_IP_UASC_BO, + VCLK_IP_BO, + VCLK_IP_LH_AXI_SI_IP_BO, + VCLK_IP_LH_AXI_MI_IP_BO, + VCLK_IP_SYSREG_CPUCL0, + VCLK_IP_HPM_APBIF_CPUCL0, + VCLK_IP_CSSYS, + VCLK_IP_LH_ATB_MI_IT0_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT6_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT1_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT7_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT2_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT3_CLUSTER0, + VCLK_IP_LH_ACE_SI_D0_CPUCL0, + VCLK_IP_LH_ATB_SI_IT0_CLUSTER0, + VCLK_IP_LH_ATB_SI_IT1_CLUSTER0, + VCLK_IP_LH_ATB_SI_IT2_CLUSTER0, + VCLK_IP_LH_ATB_SI_IT3_CLUSTER0, + VCLK_IP_ADM_APB_G_CLUSTER0, + VCLK_IP_CPUCL0_CMU_CPUCL0, + VCLK_IP_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT4_CLUSTER0, + VCLK_IP_LH_ATB_MI_IT5_CLUSTER0, + VCLK_IP_LH_ACE_SI_D1_CPUCL0, + VCLK_IP_LH_ATB_SI_IT4_CLUSTER0, + VCLK_IP_LH_ATB_SI_IT5_CLUSTER0, + VCLK_IP_D_TZPC_CPUCL0, + VCLK_IP_LH_AXI_SI_IG_CSSYS, + VCLK_IP_LH_AXI_MI_IG_CSSYS, + VCLK_IP_XIU_P_CPUCL0, + VCLK_IP_HPM_CPUCL0_1, + VCLK_IP_HPM_CPUCL0_0, + VCLK_IP_APB_ASYNC_P_CSSYS_0, + VCLK_IP_BPS_CPUCL0, + VCLK_IP_LH_ATB_SI_IT6_CLUSTER0, + VCLK_IP_GPC_CPUCL0, + VCLK_IP_LH_AXI_SI_IG_DBGCORE, + VCLK_IP_XIU_DP_CSSYS, + VCLK_IP_LH_AXI_MI_IG_DBGCORE, + VCLK_IP_SSMT_CPUCL0, + VCLK_IP_SYSMMU_S2_CPUCL0, + VCLK_IP_LH_AXI_MI_IG_HSI0, + VCLK_IP_APB_ASYNC_P_SYSMMU, + VCLK_IP_LH_AXI_SI_IG_HSI0, + VCLK_IP_LH_AXI_SI_IG_STM, + VCLK_IP_LH_ATB_SI_IT7_CLUSTER0, + VCLK_IP_LH_AXI_MI_IG_STM, + VCLK_IP_SLH_AXI_SI_G_CSSYS, + VCLK_IP_LH_AXI_SI_G_CSSYS_CD, + VCLK_IP_LH_AXI_MI_G_CSSYS_CD, + VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC, + VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CD, + VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC_CD, + VCLK_IP_SLH_AXI_SI_LG_ETR_HSI0, + VCLK_IP_LH_AXI_SI_LG_ETR_HSI0_CD, + VCLK_IP_LH_AXI_MI_LG_ETR_HSI0_CD, + VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0, + VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CU, + VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0_CU, + VCLK_IP_SLH_AXI_MI_LG_DBGCORE, + VCLK_IP_LH_AXI_SI_LG_DBGCORE_CU, + VCLK_IP_LH_AXI_MI_LG_DBGCORE_CU, + VCLK_IP_LH_ATB_MI_LT_AOC, + VCLK_IP_LH_ATB_SI_LT_AOC_CU, + VCLK_IP_LH_ATB_MI_LT_AOC_CU, + VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0, + VCLK_IP_LH_ATB_SI_LT_AUR_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT_AUR_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0, + VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0_CU, + VCLK_IP_SLH_AXI_MI_P_CPUCL0, + VCLK_IP_LH_AXI_SI_P_CPUCL0_CU, + VCLK_IP_LH_AXI_MI_P_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0, + VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0, + VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CU, + VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CU, + VCLK_IP_LH_ATB_MI_T_BDU, + VCLK_IP_LH_ATB_MI_T_SLC, + VCLK_IP_LH_ATB_SI_T_BDU_CU, + VCLK_IP_LH_ATB_MI_T_BDU_CU, + VCLK_IP_LH_ATB_SI_T_SLC_CU, + VCLK_IP_LH_ATB_MI_T_SLC_CU, + VCLK_IP_CPUCL0_CON, + VCLK_IP_CPUCL1, + VCLK_IP_CPUCL1_CMU_CPUCL1, + VCLK_IP_DD_APBIF0_CPUCL0, + VCLK_IP_CPUCL2_CMU_CPUCL2, + VCLK_IP_CMU_CPUCL2_SHORTSTOP, + VCLK_IP_CPUCL2, + VCLK_IP_DD_APBIF2_CPUCL0, + VCLK_IP_LH_AXI_SI_D0_CSIS, + VCLK_IP_SLH_AXI_MI_P_CSIS, + VCLK_IP_SYSREG_CSIS, + VCLK_IP_CSIS_CMU_CSIS, + VCLK_IP_LH_AST_MI_L_ZOTF2_IPP_CSIS, + VCLK_IP_MIPI_PHY_LINK_WRAP, + VCLK_IP_D_TZPC_CSIS, + VCLK_IP_LH_AST_MI_L_ZOTF1_IPP_CSIS, + VCLK_IP_PPMU_D0, + VCLK_IP_LH_AST_MI_L_ZOTF0_IPP_CSIS, + VCLK_IP_LH_AST_MI_L_SOTF0_IPP_CSIS, + VCLK_IP_LH_AST_MI_L_SOTF1_IPP_CSIS, + VCLK_IP_LH_AST_MI_L_SOTF2_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_OTF0_CSIS_PDP, + VCLK_IP_LH_AST_SI_L_OTF1_CSIS_PDP, + VCLK_IP_LH_AST_SI_L_OTF2_CSIS_PDP, + VCLK_IP_GPC_CSIS, + VCLK_IP_AD_APB_CSIS0, + VCLK_IP_PPMU_D1, + VCLK_IP_SYSMMU_D0_CSIS, + VCLK_IP_SYSMMU_D1_CSIS, + VCLK_IP_SSMT_D1, + VCLK_IP_SSMT_D0, + VCLK_IP_QE_ZSL1, + VCLK_IP_QE_ZSL2, + VCLK_IP_QE_ZSL0, + VCLK_IP_QE_STRP0, + VCLK_IP_XIU_D0_CSIS, + VCLK_IP_XIU_D1_CSIS, + VCLK_IP_LH_AST_MI_L_VO_MCSC_CSIS, + VCLK_IP_LH_AXI_SI_D1_CSIS, + VCLK_IP_LH_AST_MI_L_OTF0_PDP_CSIS, + VCLK_IP_LH_AST_MI_L_OTF1_PDP_CSIS, + VCLK_IP_LH_AST_MI_L_OTF2_PDP_CSIS, + VCLK_IP_LH_AST_SI_L_VO_CSIS_PDP, + VCLK_IP_LH_AXI_MI_LD_PDP_CSIS, + VCLK_IP_QE_STRP2, + VCLK_IP_QE_STRP1, + VCLK_IP_XIU_D2_CSIS, + VCLK_IP_CSISX8, + VCLK_IP_QE_CSIS_DMA0, + VCLK_IP_QE_CSIS_DMA1, + VCLK_IP_QE_CSIS_DMA2, + VCLK_IP_QE_CSIS_DMA3, + VCLK_IP_DISP_CMU_DISP, + VCLK_IP_AD_APB_DECON_MAIN, + VCLK_IP_DPUB, + VCLK_IP_SLH_AXI_MI_P_DISP, + VCLK_IP_D_TZPC_DISP, + VCLK_IP_GPC_DISP, + VCLK_IP_SYSREG_DISP, + VCLK_IP_AD_APB_DNS, + VCLK_IP_D_TZPC_DNS, + VCLK_IP_DNS, + VCLK_IP_GPC_DNS, + VCLK_IP_SLH_AXI_MI_P_DNS, + VCLK_IP_LH_AXI_SI_D_DNS, + VCLK_IP_PPMU_D0_DNS, + VCLK_IP_SSMT_D0_DNS, + VCLK_IP_SYSMMU_DNS, + VCLK_IP_SYSREG_DNS, + VCLK_IP_LH_AST_SI_L_OTF0_DNS_ITP, + VCLK_IP_LH_AST_SI_L_OTF1_DNS_ITP, + VCLK_IP_LH_AST_SI_L_OTF0_DNS_MCSC, + VCLK_IP_LH_AST_SI_L_OTF1_DNS_MCSC, + VCLK_IP_LH_AST_SI_L_OTF2_DNS_MCSC, + VCLK_IP_LH_AST_MI_L_OTF_ITP_DNS, + VCLK_IP_LH_AST_SI_L_OTF_DNS_GDC, + VCLK_IP_LH_AST_MI_L_VO_IPP_DNS, + VCLK_IP_LH_AST_SI_L_VO_DNS_TNR, + VCLK_IP_LH_AXI_MI_LD_PDP_DNS, + VCLK_IP_XIU_D_DNS, + VCLK_IP_LH_AXI_MI_LD_IPP_DNS, + VCLK_IP_LH_AXI_MI_LD_MCSC_DNS, + VCLK_IP_QE_D0_DNS, + VCLK_IP_LH_AST_MI_L_OTF_IPP_DNS, + VCLK_IP_DNS_CMU_DNS, + VCLK_IP_SSMT_D1_DNS, + VCLK_IP_PPMU_D1_DNS, + VCLK_IP_QE_D1_DNS, + VCLK_IP_LH_AXI_MI_LD_ITP_DNS, + VCLK_IP_DPU_CMU_DPU, + VCLK_IP_SYSREG_DPU, + VCLK_IP_SYSMMU_DPUD0, + VCLK_IP_SLH_AXI_MI_P_DPU, + VCLK_IP_LH_AXI_SI_D1_DPU, + VCLK_IP_LH_AXI_SI_D2_DPU, + VCLK_IP_SYSMMU_DPUD2, + VCLK_IP_SYSMMU_DPUD1, + VCLK_IP_PPMU_DPUD0, + VCLK_IP_PPMU_DPUD1, + VCLK_IP_PPMU_DPUD2, + VCLK_IP_LH_AXI_SI_D0_DPU, + VCLK_IP_DPUF, + VCLK_IP_D_TZPC_DPU, + VCLK_IP_AD_APB_DPU_DMA, + VCLK_IP_SSMT_DPU0, + VCLK_IP_SSMT_DPU1, + VCLK_IP_SSMT_DPU2, + VCLK_IP_GPC_DPU, + VCLK_IP_EH_CMU_EH, + VCLK_IP_AS_P_SYSMMU_S2_EH, + VCLK_IP_D_TZPC_EH, + VCLK_IP_GPC_EH, + VCLK_IP_LH_AXI_MI_P_EH_CU, + VCLK_IP_LH_ACEL_SI_D_EH, + VCLK_IP_EH, + VCLK_IP_SSMT_EH, + VCLK_IP_PPMU_EH, + VCLK_IP_SYSMMU_EH, + VCLK_IP_SYSREG_EH, + VCLK_IP_UASC_EH, + VCLK_IP_QE_EH, + VCLK_IP_SLH_AXI_MI_P_EH, + VCLK_IP_LH_AXI_SI_P_EH_CU, + VCLK_IP_LH_AXI_SI_IP_EH, + VCLK_IP_LH_AXI_MI_IP_EH, + VCLK_IP_G2D_CMU_G2D, + VCLK_IP_PPMU_D0_G2D, + VCLK_IP_PPMU_D1_G2D, + VCLK_IP_SYSMMU_D0_G2D, + VCLK_IP_SYSREG_G2D, + VCLK_IP_LH_AXI_SI_D0_G2D, + VCLK_IP_LH_AXI_SI_D1_G2D, + VCLK_IP_SYSMMU_D2_G2D, + VCLK_IP_PPMU_D2_G2D, + VCLK_IP_LH_ACEL_SI_D2_G2D, + VCLK_IP_SSMT_D0_G2D, + VCLK_IP_G2D, + VCLK_IP_SYSMMU_D1_G2D, + VCLK_IP_JPEG, + VCLK_IP_D_TZPC_G2D, + VCLK_IP_SSMT_D1_G2D, + VCLK_IP_SSMT_D2_G2D, + VCLK_IP_GPC_G2D, + VCLK_IP_SLH_AXI_MI_P_G2D, + VCLK_IP_AS_APB_G2D, + VCLK_IP_AS_APB_JPEG, + VCLK_IP_LH_AXI_SI_D_G3AA, + VCLK_IP_APB_ASYNC_TOP_G3AA, + VCLK_IP_SYSREG_G3AA, + VCLK_IP_G3AA_CMU_G3AA, + VCLK_IP_PPMU_G3AA, + VCLK_IP_D_TZPC_G3AA, + VCLK_IP_GPC_G3AA, + VCLK_IP_G3AA, + VCLK_IP_SSMT_G3AA, + VCLK_IP_SYSMMU_G3AA, + VCLK_IP_LH_AST_MI_L_OTF0_PDP_G3AA, + VCLK_IP_LH_AST_MI_L_YOTF0_PDP_G3AA, + VCLK_IP_LH_AST_MI_L_OTF1_PDP_G3AA, + VCLK_IP_LH_AST_MI_L_OTF2_PDP_G3AA, + VCLK_IP_LH_AST_MI_L_YOTF1_PDP_G3AA, + VCLK_IP_SLH_AXI_MI_P_G3AA, + VCLK_IP_LH_AXI_MI_P_G3D_CU, + VCLK_IP_BUSIF_HPMG3D, + VCLK_IP_HPM_G3D, + VCLK_IP_SYSREG_G3D, + VCLK_IP_G3D_CMU_G3D, + VCLK_IP_LH_AXI_SI_IP_G3D, + VCLK_IP_GPU, + VCLK_IP_LH_AXI_MI_IP_G3D, + VCLK_IP_GRAY2BIN_G3D, + VCLK_IP_D_TZPC_G3D, + VCLK_IP_GPC_G3D, + VCLK_IP_UASC_G3D, + VCLK_IP_ADD_APBIF_G3D, + VCLK_IP_ADD_G3D, + VCLK_IP_ASB_G3D, + VCLK_IP_SLH_AXI_MI_P_G3D, + VCLK_IP_LH_AXI_SI_P_G3D_CU, + VCLK_IP_ADM_AHB_G_GPU, + VCLK_IP_GDC_CMU_GDC, + VCLK_IP_AD_APB_GDC0, + VCLK_IP_AD_APB_GDC1, + VCLK_IP_AD_APB_SCSC, + VCLK_IP_D_TZPC_GDC, + VCLK_IP_GDC0, + VCLK_IP_GDC1, + VCLK_IP_GPC_GDC, + VCLK_IP_LH_AXI_SI_D2_GDC, + VCLK_IP_PPMU_D0_GDC, + VCLK_IP_PPMU_D1_GDC, + VCLK_IP_SCSC, + VCLK_IP_SSMT_D0_GDC, + VCLK_IP_SSMT_D1_GDC, + VCLK_IP_SSMT_D0_SCSC, + VCLK_IP_SYSMMU_D2_GDC, + VCLK_IP_SYSREG_GDC, + VCLK_IP_LH_AST_MI_I_GDC0_GDC1, + VCLK_IP_LH_AST_MI_I_GDC1_SCSC, + VCLK_IP_LH_AST_MI_L_OTF_DNS_GDC, + VCLK_IP_LH_AST_MI_L_OTF_TNR_GDC, + VCLK_IP_LH_AST_MI_L_VO_TNR_GDC, + VCLK_IP_LH_AST_SI_I_GDC0_GDC1, + VCLK_IP_LH_AST_SI_I_GDC1_SCSC, + VCLK_IP_LH_AST_SI_L_VO_GDC_MCSC, + VCLK_IP_SYSMMU_D0_GDC, + VCLK_IP_SYSMMU_D1_GDC, + VCLK_IP_LH_AXI_SI_D0_GDC, + VCLK_IP_PPMU_D0_SCSC, + VCLK_IP_XIU_D2_GDC, + VCLK_IP_QE_D1_SCSC, + VCLK_IP_QE_D0_SCSC, + VCLK_IP_SLH_AXI_MI_P_GDC, + VCLK_IP_LH_AXI_SI_D1_GDC, + VCLK_IP_XIU_D0_GDC, + VCLK_IP_XIU_D1_GDC, + VCLK_IP_PPMU_D2_GDC, + VCLK_IP_PPMU_D3_GDC, + VCLK_IP_PPMU_D1_SCSC, + VCLK_IP_PPMU_D2_SCSC, + VCLK_IP_SSMT_D2_GDC, + VCLK_IP_SSMT_D3_GDC, + VCLK_IP_SSMT_D1_SCSC, + VCLK_IP_SSMT_D2_SCSC, + VCLK_IP_QE_D0_GDC, + VCLK_IP_QE_D1_GDC, + VCLK_IP_QE_D2_GDC, + VCLK_IP_QE_D2_SCSC, + VCLK_IP_QE_D3_GDC, + VCLK_IP_LH_AXI_MI_ID_SCSC_GDC1, + VCLK_IP_LH_AXI_SI_ID_SCSC_GDC1, + VCLK_IP_GSACORE_CMU_GSACORE, + VCLK_IP_CA32_GSACORE, + VCLK_IP_GPIO_GSACORE, + VCLK_IP_KDN_GSACORE, + VCLK_IP_OTP_CON_GSACORE, + VCLK_IP_PPMU_GSACORE, + VCLK_IP_QE_CA32_GSACORE, + VCLK_IP_QE_DMA_GSACORE, + VCLK_IP_QE_SSS_GSACORE, + VCLK_IP_RESETMON_GSACORE, + VCLK_IP_SPI_FPS_GSACORE, + VCLK_IP_SPI_GSC_GSACORE, + VCLK_IP_SSMT_GSACORE, + VCLK_IP_SSS_GSACORE, + VCLK_IP_SYSREG_GSACORE, + VCLK_IP_UART_GSACORE, + VCLK_IP_WDT_GSACORE, + VCLK_IP_BAAW_GSACORE, + VCLK_IP_INTMEM_GSACORE, + VCLK_IP_LH_AXI_SI_D_GSA, + VCLK_IP_LH_AXI_SI_IP_GSA, + VCLK_IP_DMA_GSACORE, + VCLK_IP_SYSMMU_GSACORE, + VCLK_IP_AD_APB_DMA_GSACORE_NS, + VCLK_IP_PUF_GSACORE, + VCLK_IP_XIU_DP0_GSA_WP, + VCLK_IP_LH_AXI_MI_I_DAP_GSA, + VCLK_IP_UGME, + VCLK_IP_LH_AST_MI_I_CA32_GIC, + VCLK_IP_LH_AST_MI_I_GIC_CA32, + VCLK_IP_UDAP_SSS_AHB_ASYNC, + VCLK_IP_AD_APB_SYSMMU_GSACORE_NS, + VCLK_IP_GIC_GSACORE, + VCLK_IP_LH_AST_SI_I_GIC_CA32, + VCLK_IP_LH_AST_SI_I_CA32_GIC, + VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0_CD, + VCLK_IP_LH_ATB_SI_LT_GSA_CPUCL0, + VCLK_IP_LH_ATB_MI_LT_GSA_CPUCL0_CD, + VCLK_IP_LH_AXI_SI_IP_AXI2APB1_GSACORE, + VCLK_IP_LH_AXI_MI_IP_AXI2APB1_GSACORE, + VCLK_IP_LH_AXI_SI_IP_AXI2APB2_GSACORE, + VCLK_IP_LH_AXI_MI_IP_AXI2APB2_GSACORE, + VCLK_IP_LH_AXI_SI_IP_GME, + VCLK_IP_LH_AXI_MI_IP_GME, + VCLK_IP_AD_APB_INTMEM_GSACORE, + VCLK_IP_GSACTRL_CMU_GSACTRL, + VCLK_IP_GPC_GSACTRL, + VCLK_IP_MAILBOX_GSA2AOC, + VCLK_IP_MAILBOX_GSA2NONTZ, + VCLK_IP_MAILBOX_GSA2TPU, + VCLK_IP_MAILBOX_GSA2AUR, + VCLK_IP_SYSREG_GSACTRL, + VCLK_IP_TZPC_GSACTRL, + VCLK_IP_INTMEM_GSACTRL, + VCLK_IP_LH_AXI_MI_IP_GSA, + VCLK_IP_MAILBOX_GSA2TZ, + VCLK_IP_PMU_GSA, + VCLK_IP_APBIF_GPIO_GSACTRL, + VCLK_IP_TIMER_GSACTRL, + VCLK_IP_DAP_GSACTRL, + VCLK_IP_LH_AXI_MI_P_GSA_CU, + VCLK_IP_SYSREG_GSACTRLEXT, + VCLK_IP_SECJTAG_GSACTRL, + VCLK_IP_LH_AXI_SI_I_DAP_GSA, + VCLK_IP_AD_APB_INTMEM_GSACTRL, + VCLK_IP_SLH_AXI_MI_P_GSA, + VCLK_IP_LH_AXI_SI_P_GSA_CU, + VCLK_IP_LH_AXI_SI_IP_AXI2APB0_GSACTRL, + VCLK_IP_LH_AXI_MI_IP_AXI2APB0_GSACTRL, + VCLK_IP_XIU_DP1_GSA_WP, + VCLK_IP_HSI0_CMU_HSI0, + VCLK_IP_USB31DRD, + VCLK_IP_DP_LINK, + VCLK_IP_XIU_D0_HSI0, + VCLK_IP_ETR_MIU, + VCLK_IP_PPMU_HSI0_NOCL1B, + VCLK_IP_PPMU_HSI0_AOC, + VCLK_IP_LH_AXI_SI_LD_HSI0_AOC, + VCLK_IP_LH_ACEL_SI_D_HSI0, + VCLK_IP_GPC_HSI0, + VCLK_IP_D_TZPC_HSI0, + VCLK_IP_SSMT_USB, + VCLK_IP_SYSMMU_USB, + VCLK_IP_SYSREG_HSI0, + VCLK_IP_XIU_P_HSI0, + VCLK_IP_XIU_D1_HSI0, + VCLK_IP_UASC_HSI0_CTRL, + VCLK_IP_UASC_HSI0_LINK, + VCLK_IP_SLH_AXI_MI_LG_ETR_HSI0, + VCLK_IP_SLH_AXI_MI_LP1_AOC, + VCLK_IP_SLH_AXI_MI_P_HSI0, + VCLK_IP_LH_AXI_SI_LG_ETR_HSI0_CU, + VCLK_IP_LH_AXI_MI_LG_ETR_HSI0_CU, + VCLK_IP_LH_AXI_SI_LP1_AOC_CU, + VCLK_IP_LH_AXI_MI_LP1_AOC_CU, + VCLK_IP_LH_AXI_SI_P_HSI0_CU, + VCLK_IP_LH_AXI_MI_P_HSI0_CU, + VCLK_IP_HSI1_CMU_HSI1, + VCLK_IP_LH_ACEL_SI_D_HSI1, + VCLK_IP_LH_AXI_MI_P_HSI1_CU, + VCLK_IP_SYSREG_HSI1, + VCLK_IP_XIU_D_HSI1, + VCLK_IP_PPMU_HSI1, + VCLK_IP_SYSMMU_HSI1, + VCLK_IP_XIU_P_HSI1, + VCLK_IP_PCIE_GEN4_0, + VCLK_IP_PCIE_IA_GEN4A_0, + VCLK_IP_PCIE_IA_GEN4B_0, + VCLK_IP_D_TZPC_HSI1, + VCLK_IP_GPC_HSI1, + VCLK_IP_SSMT_HSI1, + VCLK_IP_GPIO_HSI1, + VCLK_IP_QE_PCIE_GEN4A_HSI1, + VCLK_IP_QE_PCIE_GEN4B_HSI1, + VCLK_IP_UASC_PCIE_GEN4A_DBI_0, + VCLK_IP_UASC_PCIE_GEN4A_SLV_0, + VCLK_IP_UASC_PCIE_GEN4B_DBI_0, + VCLK_IP_UASC_PCIE_GEN4B_SLV_0, + VCLK_IP_SSMT_PCIE_IA_GEN4A_0, + VCLK_IP_SSMT_PCIE_IA_GEN4B_0, + VCLK_IP_AS_APB_PCIEPHY_HSI1, + VCLK_IP_SLH_AXI_MI_P_HSI1, + VCLK_IP_LH_AXI_SI_P_HSI1_CU, + VCLK_IP_HSI2_CMU_HSI2, + VCLK_IP_SYSREG_HSI2, + VCLK_IP_GPIO_HSI2, + VCLK_IP_LH_ACEL_SI_D_HSI2, + VCLK_IP_LH_AXI_MI_P_HSI2_CU, + VCLK_IP_XIU_D_HSI2, + VCLK_IP_XIU_P_HSI2, + VCLK_IP_PPMU_HSI2, + VCLK_IP_PCIE_GEN4_1, + VCLK_IP_SYSMMU_HSI2, + VCLK_IP_SSMT_HSI2, + VCLK_IP_PCIE_IA_GEN4A_1, + VCLK_IP_D_TZPC_HSI2, + VCLK_IP_UFS_EMBD, + VCLK_IP_PCIE_IA_GEN4B_1, + VCLK_IP_GPC_HSI2, + VCLK_IP_MMC_CARD, + VCLK_IP_QE_PCIE_GEN4A_HSI2, + VCLK_IP_QE_PCIE_GEN4B_HSI2, + VCLK_IP_QE_UFS_EMBD_HSI2, + VCLK_IP_UASC_PCIE_GEN4A_DBI_1, + VCLK_IP_UASC_PCIE_GEN4A_SLV_1, + VCLK_IP_UASC_PCIE_GEN4B_DBI_1, + VCLK_IP_UASC_PCIE_GEN4B_SLV_1, + VCLK_IP_QE_MMC_CARD_HSI2, + VCLK_IP_SSMT_PCIE_IA_GEN4A_1, + VCLK_IP_SSMT_PCIE_IA_GEN4B_1, + VCLK_IP_AS_APB_PCIEPHY_HSI2, + VCLK_IP_GPIO_HSI2UFS, + VCLK_IP_SLH_AXI_MI_P_HSI2, + VCLK_IP_LH_AXI_SI_P_HSI2_CU, + VCLK_IP_IPP_CMU_IPP, + VCLK_IP_D_TZPC_IPP, + VCLK_IP_SLH_AXI_MI_P_IPP, + VCLK_IP_SYSREG_IPP, + VCLK_IP_LH_AST_SI_L_VO_IPP_DNS, + VCLK_IP_LH_AST_MI_L_VO_PDP_IPP, + VCLK_IP_AD_APB_IPP, + VCLK_IP_LH_AXI_SI_D_IPP, + VCLK_IP_LH_AST_SI_L_SOTF0_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_SOTF1_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_SOTF2_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_ZOTF0_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_ZOTF1_IPP_CSIS, + VCLK_IP_LH_AST_SI_L_ZOTF2_IPP_CSIS, + VCLK_IP_PPMU_IPP, + VCLK_IP_SIPU_IPP, + VCLK_IP_SYSMMU_IPP, + VCLK_IP_GPC_IPP, + VCLK_IP_SSMT_THSTAT, + VCLK_IP_LH_AXI_SI_LD_IPP_DNS, + VCLK_IP_PPMU_MSA, + VCLK_IP_QE_ALIGN0, + VCLK_IP_QE_ALIGN1, + VCLK_IP_SSMT_ALIGN0, + VCLK_IP_SSMT_ALIGN1, + VCLK_IP_XIU_D1_IPP, + VCLK_IP_TNR_A, + VCLK_IP_QE_THSTAT, + VCLK_IP_LH_AST_MI_L_OTF0_PDP_IPP, + VCLK_IP_LH_AST_MI_L_OTF1_PDP_IPP, + VCLK_IP_LH_AST_MI_L_OTF2_PDP_IPP, + VCLK_IP_LH_AST_SI_L_OTF_IPP_DNS, + VCLK_IP_XIU_D2_IPP, + VCLK_IP_XIU_D0_IPP, + VCLK_IP_SSMT_FDPIG, + VCLK_IP_SSMT_RGBH0, + VCLK_IP_SSMT_RGBH1, + VCLK_IP_SSMT_RGBH2, + VCLK_IP_SSMT_ALIGN2, + VCLK_IP_SSMT_ALIGN3, + VCLK_IP_QE_FDPIG, + VCLK_IP_QE_RGBH0, + VCLK_IP_QE_RGBH1, + VCLK_IP_QE_RGBH2, + VCLK_IP_QE_ALIGN2, + VCLK_IP_QE_ALIGN3, + VCLK_IP_SSMT_TNR_MSA0, + VCLK_IP_SSMT_ALN_STAT, + VCLK_IP_QE_TNR_MSA0, + VCLK_IP_QE_ALN_STAT, + VCLK_IP_SSMT_TNR_MSA1, + VCLK_IP_QE_TNR_MSA1, + VCLK_IP_ITP_CMU_ITP, + VCLK_IP_AD_APB_ITP, + VCLK_IP_D_TZPC_ITP, + VCLK_IP_GPC_ITP, + VCLK_IP_ITP, + VCLK_IP_SLH_AXI_MI_P_ITP, + VCLK_IP_SYSREG_ITP, + VCLK_IP_LH_AST_MI_L_OTF0_DNS_ITP, + VCLK_IP_LH_AST_MI_L_OTF1_DNS_ITP, + VCLK_IP_LH_AST_SI_L_OTF_ITP_DNS, + VCLK_IP_SSMT_ITP, + VCLK_IP_QE_ITP, + VCLK_IP_PPMU_ITP, + VCLK_IP_LH_AXI_SI_LD_ITP_DNS, + VCLK_IP_SLH_AXI_MI_P_MCSC, + VCLK_IP_LH_AXI_SI_D0_MCSC, + VCLK_IP_SYSREG_MCSC, + VCLK_IP_MCSC_CMU_MCSC, + VCLK_IP_LH_AST_MI_L_OTF0_DNS_MCSC, + VCLK_IP_D_TZPC_MCSC, + VCLK_IP_LH_AST_SI_L_OTF_MCSC_TNR, + VCLK_IP_LH_AST_MI_L_OTF1_DNS_MCSC, + VCLK_IP_GPC_MCSC, + VCLK_IP_ITSC, + VCLK_IP_SSMT_D0_MCSC, + VCLK_IP_SYSMMU_D0_MCSC, + VCLK_IP_PPMU_D0_MCSC, + VCLK_IP_SSMT_D0_ITSC, + VCLK_IP_PPMU_D1_ITSC, + VCLK_IP_PPMU_D0_ITSC, + VCLK_IP_LH_AST_MI_L_VO_GDC_MCSC, + VCLK_IP_LH_AXI_SI_LD_MCSC_DNS, + VCLK_IP_AD_APB_ITSC, + VCLK_IP_AD_APB_MCSC, + VCLK_IP_MCSC, + VCLK_IP_LH_AXI_SI_D1_MCSC, + VCLK_IP_SYSMMU_D1_MCSC, + VCLK_IP_LH_AST_MI_L_OTF2_DNS_MCSC, + VCLK_IP_LH_AST_MI_I_ITSC_MCSC, + VCLK_IP_LH_AST_MI_L_OTF_TNR_MCSC, + VCLK_IP_LH_AST_SI_I_ITSC_MCSC, + VCLK_IP_LH_AST_SI_L_VO_MCSC_CSIS, + VCLK_IP_SSMT_D1_ITSC, + VCLK_IP_PPMU_D1_MCSC, + VCLK_IP_SSMT_D1_MCSC, + VCLK_IP_QE_D1_ITSC, + VCLK_IP_QE_D2_ITSC, + VCLK_IP_QE_D0_MCSC, + VCLK_IP_QE_D1_MCSC, + VCLK_IP_QE_D2_MCSC, + VCLK_IP_QE_D3_MCSC, + VCLK_IP_SYSMMU_D2_MCSC, + VCLK_IP_LH_AXI_SI_D2_MCSC, + VCLK_IP_QE_D4_MCSC, + VCLK_IP_C2R_MCSC, + VCLK_IP_QE_D3_ITSC, + VCLK_IP_QE_D5_MCSC, + VCLK_IP_MFC_CMU_MFC, + VCLK_IP_AS_APB_MFC, + VCLK_IP_SYSREG_MFC, + VCLK_IP_LH_AXI_SI_D0_MFC, + VCLK_IP_LH_AXI_SI_D1_MFC, + VCLK_IP_SLH_AXI_MI_P_MFC, + VCLK_IP_SYSMMU_D0_MFC, + VCLK_IP_SYSMMU_D1_MFC, + VCLK_IP_PPMU_D0_MFC, + VCLK_IP_PPMU_D1_MFC, + VCLK_IP_SSMT_D0_MFC, + VCLK_IP_MFC, + VCLK_IP_D_TZPC_MFC, + VCLK_IP_SSMT_D1_MFC, + VCLK_IP_GPC_MFC, + VCLK_IP_MIF_CMU_MIF, + VCLK_IP_DDRPHY, + VCLK_IP_SYSREG_MIF, + VCLK_IP_LH_AXI_MI_P_MIF_CU, + VCLK_IP_AXI2APB_P_MIF, + VCLK_IP_APBBR_DDRPHY, + VCLK_IP_APBBR_DMC, + VCLK_IP_DMC, + VCLK_IP_QCH_ADAPTER_PPC_DEBUG, + VCLK_IP_GPC_MIF, + VCLK_IP_D_TZPC_MIF, + VCLK_IP_PPC_DEBUG, + VCLK_IP_GEN_WREN_SECURE, + VCLK_IP_LH_AST_SI_G_DMC_CD, + VCLK_IP_SLH_AXI_MI_P_MIF, + VCLK_IP_LH_AXI_SI_P_MIF_CU, + VCLK_IP_LH_AST_SI_G_DMC, + VCLK_IP_LH_AST_MI_G_DMC_CD, + VCLK_IP_SYSREG_MISC, + VCLK_IP_WDT_CLUSTER1, + VCLK_IP_WDT_CLUSTER0, + VCLK_IP_OTP_CON_BIRA, + VCLK_IP_GIC, + VCLK_IP_MCT, + VCLK_IP_OTP_CON_TOP, + VCLK_IP_D_TZPC_MISC, + VCLK_IP_TMU_SUB, + VCLK_IP_TMU_TOP, + VCLK_IP_OTP_CON_BISR, + VCLK_IP_DIT, + VCLK_IP_LH_AXI_MI_P_MISC_CU, + VCLK_IP_LH_ACEL_SI_D_MISC, + VCLK_IP_PDMA0, + VCLK_IP_PPMU_MISC, + VCLK_IP_QE_DIT, + VCLK_IP_QE_PDMA0, + VCLK_IP_MISC_CMU_MISC, + VCLK_IP_QE_RTIC, + VCLK_IP_QE_SPDMA0, + VCLK_IP_QE_SSS, + VCLK_IP_RTIC, + VCLK_IP_SPDMA0, + VCLK_IP_SSS, + VCLK_IP_SSMT_SSS, + VCLK_IP_GPC_MISC, + VCLK_IP_AD_APB_DIT, + VCLK_IP_ADM_AHB_G_SSS, + VCLK_IP_AD_APB_PUF, + VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU, + VCLK_IP_LH_AXI_MI_ID_SSS, + VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD, + VCLK_IP_LH_AXI_SI_ID_SSS, + VCLK_IP_PUF, + VCLK_IP_XIU_D_MISC, + VCLK_IP_SYSMMU_MISC, + VCLK_IP_SYSMMU_SSS, + VCLK_IP_LH_AXI_MI_P_GIC_CU, + VCLK_IP_SSMT_RTIC, + VCLK_IP_SSMT_SPDMA0, + VCLK_IP_SSMT_PDMA0, + VCLK_IP_SSMT_DIT, + VCLK_IP_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD, + VCLK_IP_LH_AST_SI_L_IRI_GIC_CLUSTER0, + VCLK_IP_LH_AST_MI_L_ICC_CLUSTER0_GIC, + VCLK_IP_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU, + VCLK_IP_SLH_AXI_MI_P_MISC, + VCLK_IP_LH_AXI_SI_P_MISC_CU, + VCLK_IP_SPDMA1, + VCLK_IP_QE_PDMA1, + VCLK_IP_QE_SPDMA1, + VCLK_IP_SSMT_PDMA1, + VCLK_IP_SSMT_SPDMA1, + VCLK_IP_PDMA1, + VCLK_IP_SLH_AXI_MI_P_GIC, + VCLK_IP_LH_AXI_SI_P_GIC_CU, + VCLK_IP_NOCL0_CMU_NOCL0, + VCLK_IP_SYSREG_NOCL0, + VCLK_IP_TREX_P_NOCL0, + VCLK_IP_LH_ACE_MI_D0_CPUCL0, + VCLK_IP_LH_ACE_MI_D1_CPUCL0, + VCLK_IP_TREX_D_NOCL0, + VCLK_IP_AD_APB_CCI, + VCLK_IP_D_TZPC_NOCL0, + VCLK_IP_BDU, + VCLK_IP_GPC_NOCL0, + VCLK_IP_PPMU_ACE_CPUCL0_D0, + VCLK_IP_PPMU_ACE_CPUCL0_D1, + VCLK_IP_SFR_APBIF_CMU_TOPC, + VCLK_IP_PPC_NOCL1A_M0_EVENT, + VCLK_IP_PPC_NOCL1A_M1_EVENT, + VCLK_IP_PPC_NOCL1A_M2_EVENT, + VCLK_IP_PPC_NOCL1A_M3_EVENT, + VCLK_IP_PPC_NOCL1B_M0_EVENT, + VCLK_IP_PPC_CPUCL0_D0_CYCLE, + VCLK_IP_SLC_CB_TOP, + VCLK_IP_CCI, + VCLK_IP_LH_ACEL_MI_D_EH, + VCLK_IP_PPC_EH_CYCLE, + VCLK_IP_PPC_IO_EVENT, + VCLK_IP_PPC_EH_EVENT, + VCLK_IP_PPC_CPUCL0_D0_EVENT, + VCLK_IP_PPC_CCI_M1_EVENT, + VCLK_IP_PPC_CCI_M2_EVENT, + VCLK_IP_PPC_CCI_M3_EVENT, + VCLK_IP_PPC_CCI_M4_EVENT, + VCLK_IP_PPC_IO_CYCLE, + VCLK_IP_PPC_CCI_M1_CYCLE, + VCLK_IP_PPC_NOCL1A_M0_CYCLE, + VCLK_IP_PPC_NOCL1B_M0_CYCLE, + VCLK_IP_PPC_DBG_CC, + VCLK_IP_MPACE_ASB_D0_MIF, + VCLK_IP_MPACE_ASB_D1_MIF, + VCLK_IP_MPACE_ASB_D2_MIF, + VCLK_IP_MPACE_ASB_D3_MIF, + VCLK_IP_PPC_CPUCL0_D1_EVENT, + VCLK_IP_SLC_CH_TOP, + VCLK_IP_SLC_CH1, + VCLK_IP_SLC_CH2, + VCLK_IP_SLC_CH3, + VCLK_IP_CPE425, + VCLK_IP_GRAY2BIN_ATB_TSVALUE, + VCLK_IP_SLH_AXI_MI_G_NOCL0, + VCLK_IP_LH_AST_MI_G_DMC0_CU, + VCLK_IP_LH_AST_MI_G_NOCL1A_CU, + VCLK_IP_LH_AST_MI_G_DMC1_CU, + VCLK_IP_LH_AST_MI_G_DMC2_CU, + VCLK_IP_LH_AST_MI_G_DMC3_CU, + VCLK_IP_LH_AST_MI_G_NOCL1B_CU, + VCLK_IP_LH_AST_MI_G_NOCL2A_CU, + VCLK_IP_ASYNCSFR_WR_SMC, + VCLK_IP_SLH_AXI_SI_P_ALIVE, + VCLK_IP_SLH_AXI_SI_P_CPUCL0, + VCLK_IP_SLH_AXI_SI_P_EH, + VCLK_IP_SLH_AXI_SI_P_GIC, + VCLK_IP_SLH_AXI_SI_P_MIF0, + VCLK_IP_SLH_AXI_SI_P_MIF1, + VCLK_IP_SLH_AXI_SI_P_MIF2, + VCLK_IP_SLH_AXI_SI_P_MIF3, + VCLK_IP_SLH_AXI_SI_P_MISC, + VCLK_IP_SLH_AXI_SI_P_PERIC0, + VCLK_IP_SLH_AXI_SI_P_PERIC1, + VCLK_IP_LH_ATB_SI_T_BDU, + VCLK_IP_LH_ATB_SI_T_SLC, + VCLK_IP_LH_AXI_SI_P_ALIVE_CD, + VCLK_IP_LH_AXI_SI_P_CPUCL0_CD, + VCLK_IP_LH_AXI_SI_P_EH_CD, + VCLK_IP_LH_AXI_SI_P_GIC_CD, + VCLK_IP_LH_AXI_SI_P_MIF0_CD, + VCLK_IP_LH_AXI_SI_P_MIF1_CD, + VCLK_IP_LH_AXI_SI_P_MIF2_CD, + VCLK_IP_LH_AXI_SI_P_MIF3_CD, + VCLK_IP_LH_AXI_SI_P_MISC_CD, + VCLK_IP_LH_AXI_SI_P_PERIC0_CD, + VCLK_IP_LH_AXI_SI_P_PERIC1_CD, + VCLK_IP_LH_ATB_SI_T_BDU_CD, + VCLK_IP_LH_ATB_SI_T_SLC_CD, + VCLK_IP_LH_AXI_MI_P_ALIVE_CD, + VCLK_IP_LH_AXI_MI_P_CPUCL0_CD, + VCLK_IP_LH_AXI_MI_P_EH_CD, + VCLK_IP_LH_AXI_MI_P_GIC_CD, + VCLK_IP_LH_AXI_MI_P_MIF0_CD, + VCLK_IP_LH_AXI_MI_P_MIF1_CD, + VCLK_IP_LH_AXI_MI_P_MIF2_CD, + VCLK_IP_LH_AXI_MI_P_MIF3_CD, + VCLK_IP_LH_AXI_MI_P_MISC_CD, + VCLK_IP_LH_AXI_MI_P_PERIC0_CD, + VCLK_IP_LH_AXI_MI_P_PERIC1_CD, + VCLK_IP_LH_ATB_MI_T_BDU_CD, + VCLK_IP_LH_ATB_MI_T_SLC_CD, + VCLK_IP_LH_AST_MI_G_DMC0, + VCLK_IP_LH_AST_SI_G_DMC0_CU, + VCLK_IP_LH_AST_MI_G_DMC1, + VCLK_IP_LH_AST_SI_G_DMC1_CU, + VCLK_IP_LH_AST_MI_G_DMC2, + VCLK_IP_LH_AST_SI_G_DMC2_CU, + VCLK_IP_LH_AST_MI_G_DMC3, + VCLK_IP_LH_AST_SI_G_DMC3_CU, + VCLK_IP_LH_AST_MI_G_NOCL1A, + VCLK_IP_LH_AST_MI_G_NOCL1B, + VCLK_IP_LH_AST_MI_G_NOCL2A, + VCLK_IP_LH_AST_SI_G_NOCL1A_CU, + VCLK_IP_LH_AST_SI_G_NOCL1B_CU, + VCLK_IP_LH_AST_SI_G_NOCL2A_CU, + VCLK_IP_NOCL1A_CMU_NOCL1A, + VCLK_IP_TREX_D_NOCL1A, + VCLK_IP_SYSREG_NOCL1A, + VCLK_IP_LH_ACEL_MI_D0_G3D, + VCLK_IP_D_TZPC_NOCL1A, + VCLK_IP_LH_ACEL_MI_D1_G3D, + VCLK_IP_LH_ACEL_MI_D2_G3D, + VCLK_IP_LH_ACEL_MI_D3_G3D, + VCLK_IP_SSMT_G3D0, + VCLK_IP_LH_ACEL_MI_D_TPU, + VCLK_IP_SYSMMU_G3D, + VCLK_IP_LH_AXI_SI_P_G3D_CD, + VCLK_IP_GPC_NOCL1A, + VCLK_IP_SSMT_G3D1, + VCLK_IP_SSMT_G3D2, + VCLK_IP_SSMT_G3D3, + VCLK_IP_PPCFW_G3D0, + VCLK_IP_AD_APB_SYSMMU_G3D, + VCLK_IP_TREX_P_NOCL1A, + VCLK_IP_LH_AST_SI_G_NOCL1A_CD, + VCLK_IP_PPC_NOCL2A_M0_EVENT, + VCLK_IP_PPC_NOCL2A_M1_EVENT, + VCLK_IP_PPC_NOCL2A_M2_EVENT, + VCLK_IP_PPC_NOCL2A_M3_EVENT, + VCLK_IP_PPC_G3D_D0_EVENT, + VCLK_IP_PPC_G3D_D1_EVENT, + VCLK_IP_PPC_G3D_D2_EVENT, + VCLK_IP_PPC_G3D_D3_EVENT, + VCLK_IP_PPC_TPU_EVENT, + VCLK_IP_PPC_NOCL2A_M0_CYCLE, + VCLK_IP_PPC_G3D_D0_CYCLE, + VCLK_IP_PPC_TPU_CYCLE, + VCLK_IP_PPCFW_G3D1, + VCLK_IP_LH_AXI_MI_D0_AUR, + VCLK_IP_LH_AXI_MI_D1_AUR, + VCLK_IP_LH_AXI_SI_P_AUR_CD, + VCLK_IP_PPC_AUR_D0_EVENT, + VCLK_IP_PPC_AUR_D1_EVENT, + VCLK_IP_PPC_AUR_D0_CYCLE, + VCLK_IP_LH_AST_MI_G_NOCL1A_CD, + VCLK_IP_LH_AST_SI_G_NOCL1A, + VCLK_IP_LH_AXI_MI_P_AUR_CD, + VCLK_IP_SLH_AXI_SI_P_AUR, + VCLK_IP_LH_AXI_MI_P_G3D_CD, + VCLK_IP_SLH_AXI_SI_P_G3D, + VCLK_IP_LH_AXI_SI_P_TPU_CD, + VCLK_IP_LH_AXI_MI_P_TPU_CD, + VCLK_IP_SLH_AXI_SI_P_TPU, + VCLK_IP_NOCL1B_CMU_NOCL1B, + VCLK_IP_TREX_D_NOCL1B, + VCLK_IP_D_TZPC_NOCL1B, + VCLK_IP_LH_ACEL_MI_D_HSI0, + VCLK_IP_LH_ACEL_MI_D_HSI1, + VCLK_IP_LH_AXI_MI_D_AOC, + VCLK_IP_LH_AXI_MI_D_APM, + VCLK_IP_LH_AXI_MI_D_GSA, + VCLK_IP_LH_AXI_SI_P_AOC_CD, + VCLK_IP_LH_AXI_SI_P_GSA_CD, + VCLK_IP_LH_AXI_SI_P_HSI0_CD, + VCLK_IP_LH_AXI_SI_P_HSI1_CD, + VCLK_IP_SYSREG_NOCL1B, + VCLK_IP_TREX_P_NOCL1B, + VCLK_IP_GPC_NOCL1B, + VCLK_IP_LH_AXI_MI_G_CSSYS_CU, + VCLK_IP_LH_AST_SI_G_NOCL1B_CD, + VCLK_IP_PPC_AOC_EVENT, + VCLK_IP_PPC_AOC_CYCLE, + VCLK_IP_LH_AST_MI_G_NOCL1B_CD, + VCLK_IP_LH_AST_SI_G_NOCL1B, + VCLK_IP_LH_AXI_MI_P_AOC_CD, + VCLK_IP_SLH_AXI_SI_P_AOC, + VCLK_IP_LH_AXI_MI_P_GSA_CD, + VCLK_IP_SLH_AXI_SI_P_GSA, + VCLK_IP_LH_AXI_MI_P_HSI0_CD, + VCLK_IP_SLH_AXI_SI_P_HSI0, + VCLK_IP_LH_AXI_MI_P_HSI1_CD, + VCLK_IP_SLH_AXI_SI_P_HSI1, + VCLK_IP_SLH_AXI_MI_G_CSSYS, + VCLK_IP_LH_AXI_SI_G_CSSYS_CU, + VCLK_IP_NOCL2A_CMU_NOCL2A, + VCLK_IP_SYSREG_NOCL2A, + VCLK_IP_LH_AXI_MI_D0_G2D, + VCLK_IP_LH_AXI_MI_D1_G2D, + VCLK_IP_LH_ACEL_MI_D2_G2D, + VCLK_IP_LH_AXI_MI_D0_CSIS, + VCLK_IP_LH_ACEL_MI_D_MISC, + VCLK_IP_LH_AXI_MI_D0_DPU, + VCLK_IP_LH_AXI_MI_D0_MFC, + VCLK_IP_LH_AXI_MI_D1_DPU, + VCLK_IP_LH_AXI_MI_D1_MFC, + VCLK_IP_LH_AXI_MI_D2_DPU, + VCLK_IP_LH_AXI_SI_P_HSI2_CD, + VCLK_IP_LH_AXI_MI_D1_CSIS, + VCLK_IP_LH_ACEL_MI_D_HSI2, + VCLK_IP_LH_AXI_MI_D_BO, + VCLK_IP_D_TZPC_NOCL2A, + VCLK_IP_TREX_D_NOCL2A, + VCLK_IP_SLH_AXI_SI_P_BO, + VCLK_IP_GPC_NOCL2A, + VCLK_IP_LH_AXI_MI_D_G3AA, + VCLK_IP_LH_AXI_MI_D_DNS, + VCLK_IP_LH_AXI_MI_D_IPP, + VCLK_IP_LH_AXI_MI_D0_MCSC, + VCLK_IP_LH_AXI_MI_D0_TNR, + VCLK_IP_LH_AXI_MI_D1_MCSC, + VCLK_IP_LH_AXI_MI_D1_TNR, + VCLK_IP_TREX_P_NOCL2A, + VCLK_IP_LH_AXI_MI_D0_GDC, + VCLK_IP_LH_AXI_MI_D1_GDC, + VCLK_IP_LH_AXI_MI_D2_GDC, + VCLK_IP_LH_AXI_MI_D2_TNR, + VCLK_IP_LH_AXI_MI_D3_TNR, + VCLK_IP_LH_AST_SI_G_NOCL2A_CD, + VCLK_IP_LH_AXI_MI_D2_MCSC, + VCLK_IP_LH_AXI_MI_D4_TNR, + VCLK_IP_LH_AST_MI_G_NOCL2A_CD, + VCLK_IP_LH_AST_SI_G_NOCL2A, + VCLK_IP_LH_AXI_MI_P_HSI2_CD, + VCLK_IP_SLH_AXI_SI_P_HSI2, + VCLK_IP_SLH_AXI_SI_P_DPU, + VCLK_IP_SLH_AXI_SI_P_CSIS, + VCLK_IP_SLH_AXI_SI_P_G3AA, + VCLK_IP_SLH_AXI_SI_P_IPP, + VCLK_IP_SLH_AXI_SI_P_DNS, + VCLK_IP_SLH_AXI_SI_P_ITP, + VCLK_IP_SLH_AXI_SI_P_MCSC, + VCLK_IP_SLH_AXI_SI_P_TNR, + VCLK_IP_SLH_AXI_SI_P_MFC, + VCLK_IP_SLH_AXI_SI_P_G2D, + VCLK_IP_SLH_AXI_SI_P_GDC, + VCLK_IP_SLH_AXI_SI_P_DISP, + VCLK_IP_SLH_AXI_SI_P_PDP, + VCLK_IP_PDP_CMU_PDP, + VCLK_IP_D_TZPC_PDP, + VCLK_IP_LH_AST_MI_L_OTF0_CSIS_PDP, + VCLK_IP_LH_AST_MI_L_OTF1_CSIS_PDP, + VCLK_IP_LH_AST_MI_L_OTF2_CSIS_PDP, + VCLK_IP_SLH_AXI_MI_P_PDP, + VCLK_IP_GPC_PDP, + VCLK_IP_PDP_TOP, + VCLK_IP_SSMT_PDP_STAT, + VCLK_IP_QE_PDP_STAT0, + VCLK_IP_AD_APB_C2_PDP, + VCLK_IP_LH_AST_SI_L_OTF0_PDP_IPP, + VCLK_IP_LH_AST_SI_L_OTF1_PDP_IPP, + VCLK_IP_LH_AST_SI_L_OTF2_PDP_IPP, + VCLK_IP_LH_AST_SI_L_OTF0_PDP_CSIS, + VCLK_IP_LH_AST_SI_L_OTF1_PDP_CSIS, + VCLK_IP_LH_AST_SI_L_OTF2_PDP_CSIS, + VCLK_IP_LH_AST_SI_L_OTF0_PDP_G3AA, + VCLK_IP_LH_AST_SI_L_OTF1_PDP_G3AA, + VCLK_IP_LH_AST_SI_L_OTF2_PDP_G3AA, + VCLK_IP_LH_AST_SI_L_YOTF0_PDP_G3AA, + VCLK_IP_LH_AST_SI_L_YOTF1_PDP_G3AA, + VCLK_IP_LH_AST_MI_L_VO_CSIS_PDP, + VCLK_IP_LH_AST_SI_L_VO_PDP_IPP, + VCLK_IP_LH_AXI_SI_LD_PDP_CSIS, + VCLK_IP_SYSREG_PDP, + VCLK_IP_XIU_D_PDP, + VCLK_IP_QE_PDP_STAT1, + VCLK_IP_QE_PDP_AF0, + VCLK_IP_QE_PDP_AF1, + VCLK_IP_AD_APB_VRA, + VCLK_IP_QE_VRA, + VCLK_IP_VRA, + VCLK_IP_SSMT_VRA, + VCLK_IP_LH_AXI_SI_LD_PDP_DNS, + VCLK_IP_PPMU_VRA, + VCLK_IP_GPIO_PERIC0, + VCLK_IP_SYSREG_PERIC0, + VCLK_IP_PERIC0_CMU_PERIC0, + VCLK_IP_LH_AXI_MI_P_PERIC0_CU, + VCLK_IP_D_TZPC_PERIC0, + VCLK_IP_GPC_PERIC0, + VCLK_IP_USI1_USI, + VCLK_IP_USI2_USI, + VCLK_IP_USI3_USI, + VCLK_IP_USI4_USI, + VCLK_IP_USI5_USI, + VCLK_IP_USI6_USI, + VCLK_IP_USI7_USI, + VCLK_IP_USI8_USI, + VCLK_IP_I3C1, + VCLK_IP_I3C2, + VCLK_IP_I3C3, + VCLK_IP_I3C4, + VCLK_IP_I3C5, + VCLK_IP_I3C6, + VCLK_IP_I3C7, + VCLK_IP_I3C8, + VCLK_IP_USI0_UART, + VCLK_IP_USI14_USI, + VCLK_IP_SLH_AXI_MI_P_PERIC0, + VCLK_IP_LH_AXI_SI_P_PERIC0_CU, + VCLK_IP_GPIO_PERIC1, + VCLK_IP_SYSREG_PERIC1, + VCLK_IP_PERIC1_CMU_PERIC1, + VCLK_IP_LH_AXI_MI_P_PERIC1_CU, + VCLK_IP_D_TZPC_PERIC1, + VCLK_IP_GPC_PERIC1, + VCLK_IP_USI0_USI, + VCLK_IP_USI9_USI, + VCLK_IP_USI10_USI, + VCLK_IP_USI11_USI, + VCLK_IP_USI12_USI, + VCLK_IP_USI13_USI, + VCLK_IP_I3C0, + VCLK_IP_PWM, + VCLK_IP_SLH_AXI_MI_P_PERIC1, + VCLK_IP_LH_AXI_SI_P_PERIC1_CU, + VCLK_IP_USI15_USI, + VCLK_IP_USI16_USI, + VCLK_IP_S2D_CMU_S2D, + VCLK_IP_BIS_S2D, + VCLK_IP_LH_AXI_MI_LG_SCAN2DRAM_CU, + VCLK_IP_SLH_AXI_MI_LG_SCAN2DRAM, + VCLK_IP_LH_AXI_SI_LG_SCAN2DRAM_CU, + VCLK_IP_APB_ASYNC_SYSMMU_D0_S1_NS_TNR, + VCLK_IP_D_TZPC_TNR, + VCLK_IP_LH_AST_MI_L_VO_DNS_TNR, + VCLK_IP_SLH_AXI_MI_P_TNR, + VCLK_IP_LH_AST_SI_L_OTF_TNR_MCSC, + VCLK_IP_LH_AXI_SI_D0_TNR, + VCLK_IP_LH_AXI_SI_D1_TNR, + VCLK_IP_PPMU_D0_TNR, + VCLK_IP_PPMU_D1_TNR, + VCLK_IP_SYSMMU_D0_TNR, + VCLK_IP_SYSMMU_D1_TNR, + VCLK_IP_SYSREG_TNR, + VCLK_IP_TNR_CMU_TNR, + VCLK_IP_LH_AST_SI_L_VO_TNR_GDC, + VCLK_IP_TNR, + VCLK_IP_LH_AST_MI_L_OTF_MCSC_TNR, + VCLK_IP_LH_AXI_SI_D2_TNR, + VCLK_IP_LH_AXI_SI_D3_TNR, + VCLK_IP_PPMU_D2_TNR, + VCLK_IP_PPMU_D3_TNR, + VCLK_IP_SYSMMU_D2_TNR, + VCLK_IP_SYSMMU_D3_TNR, + VCLK_IP_PPMU_D4_TNR, + VCLK_IP_PPMU_D5_TNR, + VCLK_IP_PPMU_D6_TNR, + VCLK_IP_PPMU_D7_TNR, + VCLK_IP_XIU_D0_TNR, + VCLK_IP_XIU_D1_TNR, + VCLK_IP_QE_D0_TNR, + VCLK_IP_QE_D1_TNR, + VCLK_IP_QE_D5_TNR, + VCLK_IP_QE_D6_TNR, + VCLK_IP_QE_D7_TNR, + VCLK_IP_SSMT_D0_TNR, + VCLK_IP_SSMT_D1_TNR, + VCLK_IP_SSMT_D2_TNR, + VCLK_IP_SSMT_D3_TNR, + VCLK_IP_LH_AXI_SI_D4_TNR, + VCLK_IP_SYSMMU_D4_TNR, + VCLK_IP_SSMT_D4_TNR, + VCLK_IP_SSMT_D5_TNR, + VCLK_IP_SSMT_D6_TNR, + VCLK_IP_SSMT_D7_TNR, + VCLK_IP_GPC_TNR, + VCLK_IP_LH_AST_SI_L_OTF_TNR_GDC, + VCLK_IP_SSMT_D8_TNR, + VCLK_IP_QE_D8_TNR, + VCLK_IP_PPMU_D8_TNR, + VCLK_IP_TPU_CMU_TPU, + VCLK_IP_LH_AXI_MI_P_TPU_CU, + VCLK_IP_D_TZPC_TPU, + VCLK_IP_LH_ACEL_SI_D_TPU, + VCLK_IP_SYSREG_TPU, + VCLK_IP_SYSMMU_TPU, + VCLK_IP_PPMU_TPU, + VCLK_IP_SSMT_TPU, + VCLK_IP_GPC_TPU, + VCLK_IP_AS_APB_SYSMMU_NS_TPU, + VCLK_IP_TPU, + VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0, + VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0, + VCLK_IP_ASYNC_APBM_TPU, + VCLK_IP_ASYNC_APB_INT_TPU, + VCLK_IP_LH_ATB_MI_LT0_TPU_CPUCL0_CD, + VCLK_IP_LH_ATB_MI_LT1_TPU_CPUCL0_CD, + VCLK_IP_HPM_TPU, + VCLK_IP_BUSIF_HPMTPU, + VCLK_IP_LH_ATB_SI_LT0_TPU_CPUCL0_CD, + VCLK_IP_LH_ATB_SI_LT1_TPU_CPUCL0_CD, + VCLK_IP_BUSIF_DDDTPU, + VCLK_IP_SLH_AXI_MI_P_TPU, + VCLK_IP_LH_AXI_SI_P_TPU_CU, + end_of_gate_vclk, + num_of_gate_vclk = end_of_gate_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE), + +}; +#endif diff --git a/drivers/soc/google/cal-if/gs201/cmucal-vclklut.c b/drivers/soc/google/cal-if/gs201/cmucal-vclklut.c new file mode 100644 index 000000000000..ede758ea4515 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-vclklut.c @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#include "../cmucal.h" +#include "cmucal-vclklut.h" + + +/* DVFS VCLK -> LUT Parameter List */ +unsigned int vdd_int_nm_lut_params[] = { + 0, 0, 0, 0, 0, 0, 5, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 2, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 2133000, 0, 0, 0, 1, 0, 0, 0, 0, 3, 3, 3, 3, 3, 1, 2, 1, 0, 0, 0, 1, 3, 3, 1, 3, 3, 3, 0, 0, 0, 1, 1, 1, +}; +unsigned int vdd_int_ud_lut_params[] = { + 0, 0, 0, 3, 0, 0, 7, 0, 5, 4, 0, 6, 4, 0, 4, 0, 0, 4, 0, 2, 0, 0, 1, 1, 0, 1, 3, 0, 4, 4, 2, 2, 4, 0, 4, 0, 3, 1, 0, 0, 0, 4, 0, 4, 0, 4, 0, 4, 0, 0, 0, 1, 4, 0, 1, 1, 4, 0, 5, 0, 4, 0, 2133000, 4, 0, 4, 3, 2, 3, 3, 4, 3, 3, 3, 3, 3, 1, 2, 1, 0, 0, 0, 1, 3, 3, 1, 3, 3, 3, 0, 0, 0, 1, 1, 1, +}; +unsigned int vdd_int_sud_lut_params[] = { + 1, 1, 1, 2, 1, 1, 7, 1, 5, 4, 1, 6, 4, 1, 4, 1, 1, 4, 1, 2, 1, 2, 2, 1, 1, 1, 3, 1, 2, 2, 4, 2, 4, 1, 4, 1, 3, 2, 1, 2, 1, 4, 1, 4, 1, 4, 1, 4, 1, 1, 1, 3, 4, 1, 0, 3, 2, 1, 5, 1, 4, 1, 1420000, 4, 1, 6, 1, 0, 0, 0, 0, 3, 3, 3, 3, 3, 1, 2, 1, 0, 0, 0, 1, 3, 3, 1, 3, 3, 3, 0, 0, 0, 1, 1, 1, +}; +unsigned int vdd_int_uud_lut_params[] = { + 3, 11, 4, 4, 3, 3, 9, 5, 5, 5, 3, 5, 5, 5, 5, 5, 5, 5, 3, 2, 3, 2, 6, 0, 3, 2, 5, 9, 2, 1, 4, 0, 5, 5, 5, 5, 3, 2, 3, 5, 3, 5, 5, 5, 5, 5, 5, 5, 5, 11, 19, 2, 5, 5, 0, 7, 1, 4, 0, 7, 5, 5, 711000, 0, 5, 4, 1, 0, 3, 3, 0, 0, 7, 7, 7, 7, 0, 0, 0, 1, 1, 1, 0, 0, 7, 3, 7, 7, 7, 2, 1, 2, 0, 0, 0, +}; +unsigned int vdd_mif_od_lut_params[] = { + 6400000, 6400000, 1067000, 2, 2, 1, +}; +unsigned int vdd_mif_nm_lut_params[] = { + 3732000, 3732000, 980000, 2, 2, 1, +}; +unsigned int vdd_mif_ud_lut_params[] = { + 2688000, 2688000, 640000, 2, 2, 1, +}; +unsigned int vdd_mif_sud_lut_params[] = { + 1422000, 1422000, 320000, 2, 2, 1, +}; +unsigned int vdd_mif_uud_lut_params[] = { + 710000, 842000, 133000, 1, 1, 0, +}; +unsigned int vdd_g3d_nm_lut_params[] = { + 850000, 1000000, 2, +}; +unsigned int vdd_g3d_ud_lut_params[] = { + 700000, 750000, 1, +}; +unsigned int vdd_g3d_sud_lut_params[] = { + 470000, 470000, 1, +}; +unsigned int vdd_g3d_uud_lut_params[] = { + 150000, 150000, 1, +}; +unsigned int vdd_cam_nm_lut_params[] = { + 1150000, 3, +}; +unsigned int vdd_cam_ud_lut_params[] = { + 747000, 3, +}; +unsigned int vdd_cam_sud_lut_params[] = { + 373000, 3, +}; +unsigned int vdd_cam_uud_lut_params[] = { + 178000, 1, +}; +unsigned int vdd_cpucl0_sod_lut_params[] = { + 2100000, 1, 0, +}; +unsigned int vdd_cpucl0_od_lut_params[] = { + 1800000, 1, 0, +}; +unsigned int vdd_cpucl0_nm_lut_params[] = { + 1400000, 0, 1, +}; +unsigned int vdd_cpucl0_ud_lut_params[] = { + 930000, 0, 0, +}; +unsigned int vdd_cpucl0_sud_lut_params[] = { + 580000, 0, 0, +}; +unsigned int vdd_cpucl0_uud_lut_params[] = { + 300000, 0, 0, +}; +unsigned int vdd_cpucl1_sod_lut_params[] = { + 2350000, +}; +unsigned int vdd_cpucl1_od_lut_params[] = { + 2000000, +}; +unsigned int vdd_cpucl1_nm_lut_params[] = { + 1495000, +}; +unsigned int vdd_cpucl1_ud_lut_params[] = { + 1027000, +}; +unsigned int vdd_cpucl1_sud_lut_params[] = { + 700000, +}; +unsigned int vdd_cpucl1_uud_lut_params[] = { + 400000, +}; +unsigned int vdd_tpu_nm_lut_params[] = { + 1067000, 2, +}; +unsigned int vdd_tpu_ud_lut_params[] = { + 833000, 3, +}; +unsigned int vdd_tpu_sud_lut_params[] = { + 622000, 2, +}; +unsigned int vdd_tpu_uud_lut_params[] = { + 350000, 2, +}; +unsigned int vdd_cpucl2_sod_lut_params[] = { + 2850000, +}; +unsigned int vdd_cpucl2_od_lut_params[] = { + 2250000, +}; +unsigned int vdd_cpucl2_nm_lut_params[] = { + 1825000, +}; +unsigned int vdd_cpucl2_ud_lut_params[] = { + 1275000, +}; +unsigned int vdd_cpucl2_sud_lut_params[] = { + 850000, +}; +unsigned int vdd_cpucl2_uud_lut_params[] = { + 500000, +}; + +/* SPECIAL VCLK -> LUT Parameter List */ +unsigned int mux_cmu_cmuref_ud_lut_params[] = { + 1, 0, 0, +}; +unsigned int mux_cmu_cmuref_sud_lut_params[] = { + 1, 0, 0, +}; +unsigned int mux_cmu_cmuref_uud_lut_params[] = { + 1, 0, 0, +}; +unsigned int mux_cpucl1_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int mux_cpucl2_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int mux_clk_hsi0_usb20_ref_nm_lut_params[] = { + 1, +}; +unsigned int mux_clkcmu_hsi0_usbdpdbg_uud_lut_params[] = { + 1, +}; +unsigned int mux_mif_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int mux_nocl0_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int mux_nocl1b_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int mux_nocl2a_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int clkcmu_hsi0_dpgtc_uud_lut_params[] = { + 3, 1, +}; +unsigned int clkcmu_tpu_uart_uud_lut_params[] = { + 3, 1, +}; +unsigned int div_clk_apm_usi0_usi_nm_lut_params[] = { + 0, +}; +unsigned int div_clk_apm_usi0_uart_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_apm_usi1_uart_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_apm_i3c_pmic_nm_lut_params[] = { + 1, +}; +unsigned int clk_aur_add_ch_clk_uud_lut_params[] = { + 11, +}; +unsigned int clkcmu_hpm_uud_lut_params[] = { + 0, 3, +}; +unsigned int mux_clkcmu_cis_clk0_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk1_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk2_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk3_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk4_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk5_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk6_uud_lut_params[] = { + 3, +}; +unsigned int mux_clkcmu_cis_clk7_uud_lut_params[] = { + 3, +}; +unsigned int div_clk_cpucl0_cmuref_sod_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl0_cmuref_od_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl0_cmuref_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl0_cmuref_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl0_cmuref_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl0_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_sod_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_od_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl1_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_sod_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_od_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_cpucl2_cmuref_uud_lut_params[] = { + 1, +}; +unsigned int clk_g3d_add_ch_clk_uud_lut_params[] = { + 11, +}; +unsigned int div_clk_gsacore_spi_fps_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_gsacore_spi_gsc_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_gsacore_uart_nm_lut_params[] = { + 3, +}; +unsigned int div_clk_slc_dclk_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_slc_dclk_od_lut_params[] = { + 1, +}; +unsigned int div_clk_slc_dclk_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc_dclk_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc_dclk_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc1_dclk_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_slc1_dclk_od_lut_params[] = { + 1, +}; +unsigned int div_clk_slc1_dclk_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc1_dclk_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc1_dclk_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc2_dclk_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_slc2_dclk_od_lut_params[] = { + 1, +}; +unsigned int div_clk_slc2_dclk_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc2_dclk_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc2_dclk_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc3_dclk_nm_lut_params[] = { + 1, +}; +unsigned int div_clk_slc3_dclk_od_lut_params[] = { + 1, +}; +unsigned int div_clk_slc3_dclk_ud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc3_dclk_sud_lut_params[] = { + 1, +}; +unsigned int div_clk_slc3_dclk_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_peric0_usi6_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric_400_lut_params[] = { + 0, 1, +}; +unsigned int div_clk_peric_200_lut_params[] = { + 1, 1, +}; +unsigned int div_clk_peric_133_lut_params[] = { + 2, 1, +}; +unsigned int div_clk_peric_100_lut_params[] = { + 3, 1, +}; +unsigned int div_clk_peric_66_lut_params[] = { + 5, 1, +}; +unsigned int div_clk_peric_50_lut_params[] = { + 7, 1, +}; +unsigned int div_clk_peric_40_lut_params[] = { + 9, 1, +}; +unsigned int div_clk_peric_24_lut_params[] = { + 0, 0, +}; +unsigned int div_clk_peric_12_lut_params[] = { + 1, 0, +}; +unsigned int div_clk_peric_8_lut_params[] = { + 2, 0, +}; +unsigned int div_clk_peric_6_lut_params[] = { + 3, 0, +}; +unsigned int div_clk_peric_4_lut_params[] = { + 5, 0, +}; +unsigned int mux_clkcmu_peric0_ip_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_peric0_usi3_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi4_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi5_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi14_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi7_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi8_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi1_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric0_usi0_uart_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_peric0_usi2_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi11_usi_uud_lut_params[] = { + 0, +}; +unsigned int mux_clkcmu_peric1_ip_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_peric1_i3c_uud_lut_params[] = { + 1, +}; +unsigned int div_clk_peric1_usi12_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi0_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi9_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi10_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi13_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi15_usi_uud_lut_params[] = { + 0, +}; +unsigned int div_clk_peric1_usi16_usi_uud_lut_params[] = { + 0, +}; + +/* COMMON VCLK -> LUT Parameter List */ +unsigned int blk_cmu_uud_lut_params[] = { + 2133000, 1866000, 800000, 666000, 2400000, 1, 0, 0, 0, 2, 0, 1, 7, 7, 0, 1, 4, 0, 1, 1, 2, 1, 1, 2, 1, 1, +}; +unsigned int blk_hsi0_nm_lut_params[] = { + 614400, 1, 0, 2, 31, 0, +}; +unsigned int blk_s2d_nm_lut_params[] = { + 400000, 0, +}; +unsigned int blk_apm_nm_lut_params[] = { + 1, 0, 1, 0, +}; +unsigned int blk_cpucl0_sod_lut_params[] = { + 0, 1, 1, 1, 3, 7, 1, 0, 0, 0, 0, +}; +unsigned int blk_cpucl0_od_lut_params[] = { + 0, 1, 1, 1, 3, 7, 1, 0, 0, 0, 0, +}; +unsigned int blk_cpucl0_uud_lut_params[] = { + 0, 1, 1, 1, 3, 7, 1, 0, 0, 0, 0, +}; +unsigned int blk_cpucl1_sod_lut_params[] = { + 0, +}; +unsigned int blk_cpucl1_od_lut_params[] = { + 0, +}; +unsigned int blk_cpucl1_nm_lut_params[] = { + 0, +}; +unsigned int blk_cpucl1_ud_lut_params[] = { + 0, +}; +unsigned int blk_cpucl1_sud_lut_params[] = { + 0, +}; +unsigned int blk_cpucl1_uud_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_sod_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_od_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_nm_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_ud_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_sud_lut_params[] = { + 0, +}; +unsigned int blk_cpucl2_uud_lut_params[] = { + 0, +}; +unsigned int blk_eh_uud_lut_params[] = { + 1, 0, +}; +unsigned int blk_eh_ud_lut_params[] = { + 1, 0, +}; +unsigned int blk_gsacore_nm_lut_params[] = { + 0, 3, 1, 0, 0, +}; +unsigned int blk_gsactrl_nm_lut_params[] = { + 1, 1, 1, 1, 0, +}; +unsigned int blk_nocl0_nm_lut_params[] = { + 0, 0, 0, +}; +unsigned int blk_nocl0_od_lut_params[] = { + 0, 0, 0, +}; +unsigned int blk_nocl0_ud_lut_params[] = { + 0, 0, 0, +}; +unsigned int blk_nocl0_sud_lut_params[] = { + 0, 0, 0, +}; +unsigned int blk_nocl0_uud_lut_params[] = { + 0, 0, 0, +}; +unsigned int blk_nocl1b_uud_lut_params[] = { + 0, 1, 0, 0, +}; +unsigned int blk_aoc_nm_lut_params[] = { + 0, 0, +}; +unsigned int blk_aoc_ud_lut_params[] = { + 0, 0, +}; +unsigned int blk_aoc_sud_lut_params[] = { + 0, 0, +}; +unsigned int blk_aoc_uud_lut_params[] = { + 0, 0, +}; +unsigned int blk_aur_uud_lut_params[] = { + 3, 0, 0, +}; +unsigned int blk_bo_uud_lut_params[] = { + 1, +}; +unsigned int blk_csis_uud_lut_params[] = { + 1, +}; +unsigned int blk_disp_uud_lut_params[] = { + 1, +}; +unsigned int blk_dns_uud_lut_params[] = { + 1, +}; +unsigned int blk_dpu_uud_lut_params[] = { + 1, +}; +unsigned int blk_g2d_uud_lut_params[] = { + 1, +}; +unsigned int blk_g3aa_uud_lut_params[] = { + 1, +}; +unsigned int blk_g3d_nm_lut_params[] = { + 2, 0, 0, +}; +unsigned int blk_g3d_uud_lut_params[] = { + 2, 0, 0, +}; +unsigned int blk_gdc_uud_lut_params[] = { + 1, +}; +unsigned int blk_hsi1_uud_lut_params[] = { + 0, +}; +unsigned int blk_hsi2_uud_lut_params[] = { + 0, +}; +unsigned int blk_ipp_uud_lut_params[] = { + 1, +}; +unsigned int blk_itp_uud_lut_params[] = { + 1, +}; +unsigned int blk_mcsc_uud_lut_params[] = { + 1, +}; +unsigned int blk_mif_uud_lut_params[] = { + 0, 0, +}; +unsigned int blk_mif_nm_lut_params[] = { + 0, 0, +}; +unsigned int blk_misc_uud_lut_params[] = { + 1, 1, 0, 0, +}; +unsigned int blk_nocl1a_uud_lut_params[] = { + 2, 0, 0, +}; +unsigned int blk_nocl2a_uud_lut_params[] = { + 1, 0, 0, +}; +unsigned int blk_pdp_uud_lut_params[] = { + 1, +}; +unsigned int blk_peric0_uud_lut_params[] = { + 1, 0, +}; +unsigned int blk_peric1_uud_lut_params[] = { + 0, +}; +unsigned int blk_tnr_uud_lut_params[] = { + 1, +}; +unsigned int blk_tpu_uud_lut_params[] = { + 3, 0, +}; diff --git a/drivers/soc/google/cal-if/gs201/cmucal-vclklut.h b/drivers/soc/google/cal-if/gs201/cmucal-vclklut.h new file mode 100644 index 000000000000..f6799329df9d --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/cmucal-vclklut.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef __CMUCAL_VCLKLUT_H__ +#define __CMUCAL_VCLKLUT_H__ + +#include "../cmucal.h" + +extern unsigned int vdd_int_nm_lut_params[]; +extern unsigned int vdd_int_ud_lut_params[]; +extern unsigned int vdd_int_sud_lut_params[]; +extern unsigned int vdd_int_uud_lut_params[]; +extern unsigned int vdd_mif_od_lut_params[]; +extern unsigned int vdd_mif_nm_lut_params[]; +extern unsigned int vdd_mif_ud_lut_params[]; +extern unsigned int vdd_mif_sud_lut_params[]; +extern unsigned int vdd_mif_uud_lut_params[]; +extern unsigned int vdd_g3d_nm_lut_params[]; +extern unsigned int vdd_g3d_ud_lut_params[]; +extern unsigned int vdd_g3d_sud_lut_params[]; +extern unsigned int vdd_g3d_uud_lut_params[]; +extern unsigned int vdd_cam_nm_lut_params[]; +extern unsigned int vdd_cam_ud_lut_params[]; +extern unsigned int vdd_cam_sud_lut_params[]; +extern unsigned int vdd_cam_uud_lut_params[]; +extern unsigned int vdd_cpucl0_sod_lut_params[]; +extern unsigned int vdd_cpucl0_od_lut_params[]; +extern unsigned int vdd_cpucl0_nm_lut_params[]; +extern unsigned int vdd_cpucl0_ud_lut_params[]; +extern unsigned int vdd_cpucl0_sud_lut_params[]; +extern unsigned int vdd_cpucl0_uud_lut_params[]; +extern unsigned int vdd_cpucl1_sod_lut_params[]; +extern unsigned int vdd_cpucl1_od_lut_params[]; +extern unsigned int vdd_cpucl1_nm_lut_params[]; +extern unsigned int vdd_cpucl1_ud_lut_params[]; +extern unsigned int vdd_cpucl1_sud_lut_params[]; +extern unsigned int vdd_cpucl1_uud_lut_params[]; +extern unsigned int vdd_tpu_nm_lut_params[]; +extern unsigned int vdd_tpu_ud_lut_params[]; +extern unsigned int vdd_tpu_sud_lut_params[]; +extern unsigned int vdd_tpu_uud_lut_params[]; +extern unsigned int vdd_cpucl2_sod_lut_params[]; +extern unsigned int vdd_cpucl2_od_lut_params[]; +extern unsigned int vdd_cpucl2_nm_lut_params[]; +extern unsigned int vdd_cpucl2_ud_lut_params[]; +extern unsigned int vdd_cpucl2_sud_lut_params[]; +extern unsigned int vdd_cpucl2_uud_lut_params[]; +extern unsigned int mux_cmu_cmuref_ud_lut_params[]; +extern unsigned int mux_cmu_cmuref_sud_lut_params[]; +extern unsigned int mux_cmu_cmuref_uud_lut_params[]; +extern unsigned int mux_cpucl1_cmuref_uud_lut_params[]; +extern unsigned int mux_cpucl2_cmuref_uud_lut_params[]; +extern unsigned int mux_clk_hsi0_usb20_ref_nm_lut_params[]; +extern unsigned int mux_clkcmu_hsi0_usbdpdbg_uud_lut_params[]; +extern unsigned int mux_mif_cmuref_uud_lut_params[]; +extern unsigned int mux_nocl0_cmuref_uud_lut_params[]; +extern unsigned int mux_nocl1b_cmuref_uud_lut_params[]; +extern unsigned int mux_nocl2a_cmuref_uud_lut_params[]; +extern unsigned int clkcmu_hsi0_dpgtc_uud_lut_params[]; +extern unsigned int clkcmu_tpu_uart_uud_lut_params[]; +extern unsigned int div_clk_apm_usi0_usi_nm_lut_params[]; +extern unsigned int div_clk_apm_usi0_uart_nm_lut_params[]; +extern unsigned int div_clk_apm_usi1_uart_nm_lut_params[]; +extern unsigned int div_clk_apm_i3c_pmic_nm_lut_params[]; +extern unsigned int clk_aur_add_ch_clk_uud_lut_params[]; +extern unsigned int clkcmu_hpm_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk0_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk1_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk2_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk3_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk4_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk5_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk6_uud_lut_params[]; +extern unsigned int mux_clkcmu_cis_clk7_uud_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_sod_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_od_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_nm_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_ud_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_sud_lut_params[]; +extern unsigned int div_clk_cpucl0_cmuref_uud_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_sod_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_od_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_nm_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_ud_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_sud_lut_params[]; +extern unsigned int div_clk_cpucl1_cmuref_uud_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_sod_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_od_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_nm_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_ud_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_sud_lut_params[]; +extern unsigned int div_clk_cpucl2_cmuref_uud_lut_params[]; +extern unsigned int clk_g3d_add_ch_clk_uud_lut_params[]; +extern unsigned int div_clk_gsacore_spi_fps_nm_lut_params[]; +extern unsigned int div_clk_gsacore_spi_gsc_nm_lut_params[]; +extern unsigned int div_clk_gsacore_uart_nm_lut_params[]; +extern unsigned int div_clk_slc_dclk_nm_lut_params[]; +extern unsigned int div_clk_slc_dclk_od_lut_params[]; +extern unsigned int div_clk_slc_dclk_ud_lut_params[]; +extern unsigned int div_clk_slc_dclk_sud_lut_params[]; +extern unsigned int div_clk_slc_dclk_uud_lut_params[]; +extern unsigned int div_clk_slc1_dclk_nm_lut_params[]; +extern unsigned int div_clk_slc1_dclk_od_lut_params[]; +extern unsigned int div_clk_slc1_dclk_ud_lut_params[]; +extern unsigned int div_clk_slc1_dclk_sud_lut_params[]; +extern unsigned int div_clk_slc1_dclk_uud_lut_params[]; +extern unsigned int div_clk_slc2_dclk_nm_lut_params[]; +extern unsigned int div_clk_slc2_dclk_od_lut_params[]; +extern unsigned int div_clk_slc2_dclk_ud_lut_params[]; +extern unsigned int div_clk_slc2_dclk_sud_lut_params[]; +extern unsigned int div_clk_slc2_dclk_uud_lut_params[]; +extern unsigned int div_clk_slc3_dclk_nm_lut_params[]; +extern unsigned int div_clk_slc3_dclk_od_lut_params[]; +extern unsigned int div_clk_slc3_dclk_ud_lut_params[]; +extern unsigned int div_clk_slc3_dclk_sud_lut_params[]; +extern unsigned int div_clk_slc3_dclk_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi6_usi_uud_lut_params[]; +extern unsigned int div_clk_peric_400_lut_params[]; +extern unsigned int div_clk_peric_200_lut_params[]; +extern unsigned int div_clk_peric_133_lut_params[]; +extern unsigned int div_clk_peric_100_lut_params[]; +extern unsigned int div_clk_peric_66_lut_params[]; +extern unsigned int div_clk_peric_50_lut_params[]; +extern unsigned int div_clk_peric_40_lut_params[]; +extern unsigned int div_clk_peric_24_lut_params[]; +extern unsigned int div_clk_peric_12_lut_params[]; +extern unsigned int div_clk_peric_8_lut_params[]; +extern unsigned int div_clk_peric_6_lut_params[]; +extern unsigned int div_clk_peric_4_lut_params[]; +extern unsigned int mux_clkcmu_peric0_ip_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi3_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi4_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi5_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi14_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi7_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi8_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi1_usi_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi0_uart_uud_lut_params[]; +extern unsigned int div_clk_peric0_usi2_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi11_usi_uud_lut_params[]; +extern unsigned int mux_clkcmu_peric1_ip_uud_lut_params[]; +extern unsigned int div_clk_peric1_i3c_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi12_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi0_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi9_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi10_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi13_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi15_usi_uud_lut_params[]; +extern unsigned int div_clk_peric1_usi16_usi_uud_lut_params[]; +extern unsigned int blk_cmu_uud_lut_params[]; +extern unsigned int blk_hsi0_nm_lut_params[]; +extern unsigned int blk_s2d_nm_lut_params[]; +extern unsigned int blk_apm_nm_lut_params[]; +extern unsigned int blk_cpucl0_sod_lut_params[]; +extern unsigned int blk_cpucl0_od_lut_params[]; +extern unsigned int blk_cpucl0_uud_lut_params[]; +extern unsigned int blk_cpucl1_sod_lut_params[]; +extern unsigned int blk_cpucl1_od_lut_params[]; +extern unsigned int blk_cpucl1_nm_lut_params[]; +extern unsigned int blk_cpucl1_ud_lut_params[]; +extern unsigned int blk_cpucl1_sud_lut_params[]; +extern unsigned int blk_cpucl1_uud_lut_params[]; +extern unsigned int blk_cpucl2_sod_lut_params[]; +extern unsigned int blk_cpucl2_od_lut_params[]; +extern unsigned int blk_cpucl2_nm_lut_params[]; +extern unsigned int blk_cpucl2_ud_lut_params[]; +extern unsigned int blk_cpucl2_sud_lut_params[]; +extern unsigned int blk_cpucl2_uud_lut_params[]; +extern unsigned int blk_eh_uud_lut_params[]; +extern unsigned int blk_eh_ud_lut_params[]; +extern unsigned int blk_gsacore_nm_lut_params[]; +extern unsigned int blk_gsactrl_nm_lut_params[]; +extern unsigned int blk_nocl0_nm_lut_params[]; +extern unsigned int blk_nocl0_od_lut_params[]; +extern unsigned int blk_nocl0_ud_lut_params[]; +extern unsigned int blk_nocl0_sud_lut_params[]; +extern unsigned int blk_nocl0_uud_lut_params[]; +extern unsigned int blk_nocl1b_uud_lut_params[]; +extern unsigned int blk_aoc_nm_lut_params[]; +extern unsigned int blk_aoc_ud_lut_params[]; +extern unsigned int blk_aoc_sud_lut_params[]; +extern unsigned int blk_aoc_uud_lut_params[]; +extern unsigned int blk_aur_uud_lut_params[]; +extern unsigned int blk_bo_uud_lut_params[]; +extern unsigned int blk_csis_uud_lut_params[]; +extern unsigned int blk_disp_uud_lut_params[]; +extern unsigned int blk_dns_uud_lut_params[]; +extern unsigned int blk_dpu_uud_lut_params[]; +extern unsigned int blk_g2d_uud_lut_params[]; +extern unsigned int blk_g3aa_uud_lut_params[]; +extern unsigned int blk_g3d_nm_lut_params[]; +extern unsigned int blk_g3d_uud_lut_params[]; +extern unsigned int blk_gdc_uud_lut_params[]; +extern unsigned int blk_hsi1_uud_lut_params[]; +extern unsigned int blk_hsi2_uud_lut_params[]; +extern unsigned int blk_ipp_uud_lut_params[]; +extern unsigned int blk_itp_uud_lut_params[]; +extern unsigned int blk_mcsc_uud_lut_params[]; +extern unsigned int blk_mif_uud_lut_params[]; +extern unsigned int blk_mif_nm_lut_params[]; +extern unsigned int blk_misc_uud_lut_params[]; +extern unsigned int blk_nocl1a_uud_lut_params[]; +extern unsigned int blk_nocl2a_uud_lut_params[]; +extern unsigned int blk_pdp_uud_lut_params[]; +extern unsigned int blk_peric0_uud_lut_params[]; +extern unsigned int blk_peric1_uud_lut_params[]; +extern unsigned int blk_tnr_uud_lut_params[]; +extern unsigned int blk_tpu_uud_lut_params[]; +#endif diff --git a/drivers/soc/google/cal-if/gs201/flexpmu_cal_cpu_gs201.h b/drivers/soc/google/cal-if/gs201/flexpmu_cal_cpu_gs201.h new file mode 100644 index 000000000000..627b3ac6ce35 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/flexpmu_cal_cpu_gs201.h @@ -0,0 +1,702 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +struct cpu_inform pmucal_cpuinform_list[] = { + PMUCAL_CPU_INFORM(0, 0x18060000, 0x860), + PMUCAL_CPU_INFORM(1, 0x18060000, 0x864), + PMUCAL_CPU_INFORM(2, 0x18060000, 0x868), + PMUCAL_CPU_INFORM(3, 0x18060000, 0x86C), + PMUCAL_CPU_INFORM(4, 0x18060000, 0x870), + PMUCAL_CPU_INFORM(5, 0x18060000, 0x874), + PMUCAL_CPU_INFORM(6, 0x18060000, 0x878), + PMUCAL_CPU_INFORM(7, 0x18060000, 0x87C), +}; +unsigned int cpu_inform_list_size = ARRAY_SIZE(pmucal_cpuinform_list); +#ifndef ACPM_FRAMEWORK +/* individual sequence descriptor for each core - on, off, status */ +struct pmucal_seq core00_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0208, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), +}; + +struct pmucal_seq core00_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 8), (0x1 << 8), 0x18070000, 0x0108, (0x1 << 8), (0x1 << 8) | (0x1 << 8)), +}; + +struct pmucal_seq core00_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU0_STATUS", 0x18060000, 0x1004, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core01_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 1), (0x0 << 1), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 1), (0x1 << 1), 0x18070000, 0x0208, (0x1 << 1), (0x1 << 1) | (0x1 << 1)), +}; + +struct pmucal_seq core01_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 1), (0x1 << 1), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 1), (0x1 << 1), 0x18070000, 0x0108, (0x1 << 1), (0x1 << 1) | (0x1 << 1)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 9), (0x1 << 9), 0x18070000, 0x0108, (0x1 << 9), (0x1 << 9) | (0x1 << 9)), +}; + +struct pmucal_seq core01_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU1_STATUS", 0x18060000, 0x1084, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core02_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 2), (0x0 << 2), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 2), (0x1 << 2), 0x18070000, 0x0208, (0x1 << 2), (0x1 << 2) | (0x1 << 2)), +}; + +struct pmucal_seq core02_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 2), (0x1 << 2), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 2), (0x1 << 2), 0x18070000, 0x0108, (0x1 << 2), (0x1 << 2) | (0x1 << 2)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 10), (0x1 << 10), 0x18070000, 0x0108, (0x1 << 10), (0x1 << 10) | (0x1 << 10)), +}; + +struct pmucal_seq core02_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU2_STATUS", 0x18060000, 0x1104, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core03_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 3), (0x1 << 3), 0x18070000, 0x0208, (0x1 << 3), (0x1 << 3) | (0x1 << 3)), +}; + +struct pmucal_seq core03_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 3), (0x1 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 3), (0x1 << 3), 0x18070000, 0x0108, (0x1 << 3), (0x1 << 3) | (0x1 << 3)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 11), (0x1 << 11), 0x18070000, 0x0108, (0x1 << 11), (0x1 << 11) | (0x1 << 11)), +}; + +struct pmucal_seq core03_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU3_STATUS", 0x18060000, 0x1184, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core10_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 4), (0x1 << 4), 0x18070000, 0x0208, (0x1 << 4), (0x1 << 4) | (0x1 << 4)), +}; + +struct pmucal_seq core10_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 4), (0x1 << 4), 0x18070000, 0x0108, (0x1 << 4), (0x1 << 4) | (0x1 << 4)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 12), (0x1 << 12), 0x18070000, 0x0108, (0x1 << 12), (0x1 << 12) | (0x1 << 12)), +}; + +struct pmucal_seq core10_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_CPU0_STATUS", 0x18060000, 0x1304, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core11_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 5), (0x0 << 5), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 5), (0x1 << 5), 0x18070000, 0x0208, (0x1 << 5), (0x1 << 5) | (0x1 << 5)), +}; + +struct pmucal_seq core11_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 5), (0x1 << 5), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 5), (0x1 << 5), 0x18070000, 0x0108, (0x1 << 5), (0x1 << 5) | (0x1 << 5)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 13), (0x1 << 13), 0x18070000, 0x0108, (0x1 << 13), (0x1 << 13) | (0x1 << 13)), +}; + +struct pmucal_seq core11_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_CPU1_STATUS", 0x18060000, 0x1384, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core20_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 6), (0x0 << 6), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 6), (0x1 << 6), 0x18070000, 0x0208, (0x1 << 6), (0x1 << 6) | (0x1 << 6)), +}; + +struct pmucal_seq core20_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 6), (0x1 << 6), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 6), (0x1 << 6), 0x18070000, 0x0108, (0x1 << 6), (0x1 << 6) | (0x1 << 6)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 14), (0x1 << 14), 0x18070000, 0x0108, (0x1 << 14), (0x1 << 14) | (0x1 << 14)), +}; + +struct pmucal_seq core20_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_CPU0_STATUS", 0x18060000, 0x1504, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core21_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 7), (0x0 << 7), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 7), (0x1 << 7), 0x18070000, 0x0208, (0x1 << 7), (0x1 << 7) | (0x1 << 7)), +}; + +struct pmucal_seq core21_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 7), (0x1 << 7), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 7), (0x1 << 7), 0x18070000, 0x0108, (0x1 << 7), (0x1 << 7) | (0x1 << 7)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 15), (0x1 << 15), 0x18070000, 0x0108, (0x1 << 15), (0x1 << 15) | (0x1 << 15)), +}; + +struct pmucal_seq core21_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_CPU1_STATUS", 0x18060000, 0x1584, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster0_on[] = { +}; + +struct pmucal_seq cluster0_off[] = { +}; + +struct pmucal_seq cluster0_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_NONCPU_STATUS", 0x18060000, 0x1204, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster1_on[] = { +}; + +struct pmucal_seq cluster1_off[] = { +}; + +struct pmucal_seq cluster1_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_NONCPU_STATUS", 0x18060000, 0x1404, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster2_on[] = { +}; + +struct pmucal_seq cluster2_off[] = { +}; + +struct pmucal_seq cluster2_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_NONCPU_STATUS", 0x18060000, 0x1604, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +enum pmucal_cpu_corenum { + CPU_CORE00, + CPU_CORE01, + CPU_CORE02, + CPU_CORE03, + CPU_CORE10, + CPU_CORE11, + CPU_CORE20, + CPU_CORE21, + PMUCAL_NUM_CORES, +}; + +struct pmucal_cpu pmucal_cpu_list[PMUCAL_NUM_CORES] = { + [CPU_CORE00] = { + .id = CPU_CORE00, + .release = 0, + .on = core00_on, + .off = core00_off, + .status = core00_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core00_on), + .num_off = ARRAY_SIZE(core00_off), + .num_status = ARRAY_SIZE(core00_status), + }, + [CPU_CORE01] = { + .id = CPU_CORE01, + .release = 0, + .on = core01_on, + .off = core01_off, + .status = core01_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core01_on), + .num_off = ARRAY_SIZE(core01_off), + .num_status = ARRAY_SIZE(core01_status), + }, + [CPU_CORE02] = { + .id = CPU_CORE02, + .release = 0, + .on = core02_on, + .off = core02_off, + .status = core02_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core02_on), + .num_off = ARRAY_SIZE(core02_off), + .num_status = ARRAY_SIZE(core02_status), + }, + [CPU_CORE03] = { + .id = CPU_CORE03, + .release = 0, + .on = core03_on, + .off = core03_off, + .status = core03_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core03_on), + .num_off = ARRAY_SIZE(core03_off), + .num_status = ARRAY_SIZE(core03_status), + }, + [CPU_CORE10] = { + .id = CPU_CORE10, + .release = 0, + .on = core10_on, + .off = core10_off, + .status = core10_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core10_on), + .num_off = ARRAY_SIZE(core10_off), + .num_status = ARRAY_SIZE(core10_status), + }, + [CPU_CORE11] = { + .id = CPU_CORE11, + .release = 0, + .on = core11_on, + .off = core11_off, + .status = core11_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core11_on), + .num_off = ARRAY_SIZE(core11_off), + .num_status = ARRAY_SIZE(core11_status), + }, + [CPU_CORE20] = { + .id = CPU_CORE20, + .release = 0, + .on = core20_on, + .off = core20_off, + .status = core20_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core20_on), + .num_off = ARRAY_SIZE(core20_off), + .num_status = ARRAY_SIZE(core20_status), + }, + [CPU_CORE21] = { + .id = CPU_CORE21, + .release = 0, + .on = core21_on, + .off = core21_off, + .status = core21_status, + .num_release = 0, + .num_on = ARRAY_SIZE(core21_on), + .num_off = ARRAY_SIZE(core21_off), + .num_status = ARRAY_SIZE(core21_status), + }, +}; + +unsigned int pmucal_cpu_list_size = ARRAY_SIZE(pmucal_cpu_list); + +enum pmucal_cpu_clusternum { + CPU_CLUSTER0, + CPU_CLUSTER1, + CPU_CLUSTER2, + PMUCAL_NUM_CLUSTERS, +}; + +struct pmucal_cpu pmucal_cluster_list[PMUCAL_NUM_CLUSTERS] = { + [CPU_CLUSTER0] = { + .id = CPU_CLUSTER0, + .on = cluster0_on, + .off = cluster0_off, + .status = cluster0_status, + .num_on = ARRAY_SIZE(cluster0_on), + .num_off = ARRAY_SIZE(cluster0_off), + .num_status = ARRAY_SIZE(cluster0_status), + }, + [CPU_CLUSTER1] = { + .id = CPU_CLUSTER1, + .on = cluster1_on, + .off = cluster1_off, + .status = cluster1_status, + .num_on = ARRAY_SIZE(cluster1_on), + .num_off = ARRAY_SIZE(cluster1_off), + .num_status = ARRAY_SIZE(cluster1_status), + }, + [CPU_CLUSTER2] = { + .id = CPU_CLUSTER2, + .on = cluster2_on, + .off = cluster2_off, + .status = cluster2_status, + .num_on = ARRAY_SIZE(cluster2_on), + .num_off = ARRAY_SIZE(cluster2_off), + .num_status = ARRAY_SIZE(cluster2_status), + }, +}; + +unsigned int pmucal_cluster_list_size = ARRAY_SIZE(pmucal_cluster_list); + +enum pmucal_opsnum { + NUM_PMUCAL_OPTIONS, +}; + +struct pmucal_cpu pmucal_pmu_ops_list[] = {}; + +unsigned int pmucal_option_list_size = ARRAY_SIZE(pmucal_pmu_ops_list); + +#else + +struct pmucal_seq core00_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_reset_release", 0, 0, 0x20, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq core00_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_up", 0, 0, 0x21, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core00_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_down", 0, 0, 0x22, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core00_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU0_STATUS", 0x18060000, 0x1004, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core01_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_reset_release", 0, 0, 0x20, 0x1, 0, 0, 0, 0), +}; + +struct pmucal_seq core01_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_up", 0, 0, 0x21, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core01_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_down", 0, 0, 0x22, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core01_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU1_STATUS", 0x18060000, 0x1084, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core02_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_reset_release", 0, 0, 0x20, 0x2, 0, 0, 0, 0), +}; + +struct pmucal_seq core02_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_up", 0, 0, 0x21, 0x2, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core02_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_down", 0, 0, 0x22, 0x2, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core02_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU2_STATUS", 0x18060000, 0x1104, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core03_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_reset_release", 0, 0, 0x20, 0x3, 0, 0, 0, 0), +}; + +struct pmucal_seq core03_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_up", 0, 0, 0x21, 0x3, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core03_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_cpu_down", 0, 0, 0x22, 0x3, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core03_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_CPU3_STATUS", 0x18060000, 0x1184, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core10_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_reset_release", 0, 0, 0x30, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq core10_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_up", 0, 0, 0x31, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core10_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_down", 0, 0, 0x32, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core10_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_CPU0_STATUS", 0x18060000, 0x1304, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core11_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_reset_release", 0, 0, 0x30, 0x1, 0, 0, 0, 0), +}; + +struct pmucal_seq core11_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_up", 0, 0, 0x31, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core11_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_cpu_down", 0, 0, 0x32, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core11_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_CPU1_STATUS", 0x18060000, 0x1384, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core20_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_reset_release", 0, 0, 0x40, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq core20_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_up", 0, 0, 0x41, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core20_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_down", 0, 0, 0x42, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core20_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_CPU0_STATUS", 0x18060000, 0x1504, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core21_release[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_reset_release", 0, 0, 0x40, 0x1, 0, 0, 0, 0), +}; + +struct pmucal_seq core21_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_up", 0, 0, 0x41, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core21_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_cpu_down", 0, 0, 0x42, 0x1, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq core21_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_CPU1_STATUS", 0x18060000, 0x1584, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster0_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_noncpu_up", 0, 0, 0x28, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "QCH_CON_CLUSTER0_QCH_SCLK", 0x20c00000, 0x3144, (0x7 << 0), (0x6 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster0_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "QCH_CON_CLUSTER0_QCH_SCLK", 0x20c00000, 0x3144, (0x7 << 0), (0x2 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster0_noncpu_down", 0, 0, 0x29, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster0_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER0_NONCPU_STATUS", 0x18060000, 0x1204, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster1_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_noncpu_up", 0, 0, 0x38, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster1_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster1_noncpu_down", 0, 0, 0x39, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster1_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER1_NONCPU_STATUS", 0x18060000, 0x1404, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster2_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_noncpu_up", 0, 0, 0x48, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster2_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x1 << 4), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "cluster2_noncpu_down", 0, 0, 0x49, 0x0, 0, 0, 0, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x1 << 4), (0x0 << 4), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq cluster2_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CLUSTER2_NONCPU_STATUS", 0x18060000, 0x1604, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +enum pmucal_cpu_corenum { + CPU_CORE00, + CPU_CORE01, + CPU_CORE02, + CPU_CORE03, + CPU_CORE10, + CPU_CORE11, + CPU_CORE20, + CPU_CORE21, + PMUCAL_NUM_CORES, +}; + +struct pmucal_cpu pmucal_cpu_list[PMUCAL_NUM_CORES] = { + [CPU_CORE00] = { + .id = CPU_CORE00, + .release = core00_release, + .on = core00_on, + .off = core00_off, + .status = core00_status, + .num_release = ARRAY_SIZE(core00_release), + .num_on = ARRAY_SIZE(core00_on), + .num_off = ARRAY_SIZE(core00_off), + .num_status = ARRAY_SIZE(core00_status), + }, + [CPU_CORE01] = { + .id = CPU_CORE01, + .release = core01_release, + .on = core01_on, + .off = core01_off, + .status = core01_status, + .num_release = ARRAY_SIZE(core01_release), + .num_on = ARRAY_SIZE(core01_on), + .num_off = ARRAY_SIZE(core01_off), + .num_status = ARRAY_SIZE(core01_status), + }, + [CPU_CORE02] = { + .id = CPU_CORE02, + .release = core02_release, + .on = core02_on, + .off = core02_off, + .status = core02_status, + .num_release = ARRAY_SIZE(core02_release), + .num_on = ARRAY_SIZE(core02_on), + .num_off = ARRAY_SIZE(core02_off), + .num_status = ARRAY_SIZE(core02_status), + }, + [CPU_CORE03] = { + .id = CPU_CORE03, + .release = core03_release, + .on = core03_on, + .off = core03_off, + .status = core03_status, + .num_release = ARRAY_SIZE(core03_release), + .num_on = ARRAY_SIZE(core03_on), + .num_off = ARRAY_SIZE(core03_off), + .num_status = ARRAY_SIZE(core03_status), + }, + [CPU_CORE10] = { + .id = CPU_CORE10, + .release = core10_release, + .on = core10_on, + .off = core10_off, + .status = core10_status, + .num_release = ARRAY_SIZE(core10_release), + .num_on = ARRAY_SIZE(core10_on), + .num_off = ARRAY_SIZE(core10_off), + .num_status = ARRAY_SIZE(core10_status), + }, + [CPU_CORE11] = { + .id = CPU_CORE11, + .release = core11_release, + .on = core11_on, + .off = core11_off, + .status = core11_status, + .num_release = ARRAY_SIZE(core11_release), + .num_on = ARRAY_SIZE(core11_on), + .num_off = ARRAY_SIZE(core11_off), + .num_status = ARRAY_SIZE(core11_status), + }, + [CPU_CORE20] = { + .id = CPU_CORE20, + .release = core20_release, + .on = core20_on, + .off = core20_off, + .status = core20_status, + .num_release = ARRAY_SIZE(core20_release), + .num_on = ARRAY_SIZE(core20_on), + .num_off = ARRAY_SIZE(core20_off), + .num_status = ARRAY_SIZE(core20_status), + }, + [CPU_CORE21] = { + .id = CPU_CORE21, + .release = core21_release, + .on = core21_on, + .off = core21_off, + .status = core21_status, + .num_release = ARRAY_SIZE(core21_release), + .num_on = ARRAY_SIZE(core21_on), + .num_off = ARRAY_SIZE(core21_off), + .num_status = ARRAY_SIZE(core21_status), + }, +}; + +unsigned int pmucal_cpu_list_size = ARRAY_SIZE(pmucal_cpu_list); + +enum pmucal_cpu_clusternum { + CPU_CLUSTER0, + CPU_CLUSTER1, + CPU_CLUSTER2, + PMUCAL_NUM_CLUSTERS, +}; + +struct pmucal_cpu pmucal_cluster_list[PMUCAL_NUM_CLUSTERS] = { + [CPU_CLUSTER0] = { + .id = CPU_CLUSTER0, + .on = cluster0_on, + .off = cluster0_off, + .status = cluster0_status, + .num_on = ARRAY_SIZE(cluster0_on), + .num_off = ARRAY_SIZE(cluster0_off), + .num_status = ARRAY_SIZE(cluster0_status), + }, + [CPU_CLUSTER1] = { + .id = CPU_CLUSTER1, + .on = cluster1_on, + .off = cluster1_off, + .status = cluster1_status, + .num_on = ARRAY_SIZE(cluster1_on), + .num_off = ARRAY_SIZE(cluster1_off), + .num_status = ARRAY_SIZE(cluster1_status), + }, + [CPU_CLUSTER2] = { + .id = CPU_CLUSTER2, + .on = cluster2_on, + .off = cluster2_off, + .status = cluster2_status, + .num_on = ARRAY_SIZE(cluster2_on), + .num_off = ARRAY_SIZE(cluster2_off), + .num_status = ARRAY_SIZE(cluster2_status), + }, +}; + +unsigned int pmucal_cluster_list_size = ARRAY_SIZE(pmucal_cluster_list); + +enum pmucal_opsnum { + NUM_PMUCAL_OPTIONS, +}; + +struct pmucal_cpu pmucal_pmu_ops_list[NUM_PMUCAL_OPTIONS] = { +}; +unsigned int pmucal_option_list_size = ARRAY_SIZE(pmucal_pmu_ops_list); + +struct cpu_info cpuinfo[] = { + [0] = { + .min = 0, + .max = 3, + .total = 4, + }, + [1] = { + .min = 4, + .max = 5, + .total = 2, + }, + [2] = { + .min = 6, + .max = 7, + .total = 2, + }, +}; +#endif diff --git a/drivers/soc/google/cal-if/gs201/flexpmu_cal_define_gs201.h b/drivers/soc/google/cal-if/gs201/flexpmu_cal_define_gs201.h new file mode 100644 index 000000000000..6320f6ad0a01 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/flexpmu_cal_define_gs201.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#define CPU_INFORM_C1 (0) +#define CPU_INFORM_C2 (1) +#define CPU_INFORM_CPD (2) +#define CPU_INFORM_SICD (3) +#define CPU_INFORM_SLEEP (4) +#define CPU_INFORM_SLEEP_SLCMON (5) +#define CPU_INFORM_SLEEP_HSI1ON (6) +#define CPU_INFORM_STOP (7) +#define CPU_INFORM_POWERMODE_NUM (8) diff --git a/drivers/soc/google/cal-if/gs201/flexpmu_cal_local_gs201.h b/drivers/soc/google/cal-if/gs201/flexpmu_cal_local_gs201.h new file mode 100644 index 000000000000..62f477ea7642 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/flexpmu_cal_local_gs201.h @@ -0,0 +1,2080 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef ACPM_FRAMEWORK + +struct pmucal_seq aoc_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AOC_CONFIGURATION", 0x18060000, 0x1880, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "AOC_STATUS", 0x18060000, 0x1884, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aoc_save[] = { +}; + +struct pmucal_seq aoc_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "AOC_STATUS", 0x18060000, 0x1884, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aoc_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AOC_CMU_AOC_CONTROLLER_OPTION", 0x1a000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AOC_CONFIGURATION", 0x18060000, 0x1880, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "AOC_STATUS", 0x18060000, 0x1884, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1b_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1B_CONFIGURATION", 0x18060000, 0x1a00, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL1B_STATUS", 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1b_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1B_NOCD_LH", 0x1e800000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP", 0x1e800000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1B_NOCP_LH", 0x1e800000, 0x1808, 0xffffffff, 0, 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_NOCL1B_NOC_USER", 0x1e800000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_NOCL1B_QCH", 0x1e800000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_NOCL1B_QCH", 0x1e800000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_HSI0_QCH", 0x1e800000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_HSI1_QCH", 0x1e800000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1B_CD_QCH", 0x1e800000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1B_CD_QCH", 0x1e800000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1B_QCH", 0x1e800000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_AOC_QCH", 0x1e800000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_APM_QCH", 0x1e800000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_GSA_QCH", 0x1e800000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_G_CSSYS_CU_QCH", 0x1e800000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_AOC_CD_QCH", 0x1e800000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_GSA_CD_QCH", 0x1e800000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI0_CD_QCH", 0x1e800000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI1_CD_QCH", 0x1e800000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_G_CSSYS_CU_QCH", 0x1e800000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_AOC_CD_QCH", 0x1e800000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_GSA_CD_QCH", 0x1e800000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI0_CD_QCH", 0x1e800000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI1_CD_QCH", 0x1e800000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_NOCL1B_CMU_NOCL1B_QCH", 0x1e800000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_AOC_CYCLE_QCH", 0x1e800000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_AOC_EVENT_QCH", 0x1e800000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_G_CSSYS_QCH", 0x1e800000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_AOC_QCH", 0x1e800000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_GSA_QCH", 0x1e800000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_HSI0_QCH", 0x1e800000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_HSI1_QCH", 0x1e800000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_NOCL1B_QCH", 0x1e800000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_D_NOCL1B_QCH", 0x1e800000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_P_NOCL1B_QCH", 0x1e800000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION", 0x1e800000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1e820000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1e820000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1b_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "NOCL1B_STATUS", 0x18060000, 0x1a04, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1b_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1B_CMU_NOCL1B_CONTROLLER_OPTION", 0x1e800000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1B_CONFIGURATION", 0x18060000, 0x1a00, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL1B_STATUS", 0x18060000, 0x1a04, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl2a_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL2A_CONFIGURATION", 0x18060000, 0x1a80, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL2A_STATUS", 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl2a_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL2A_NOCD_LH", 0x1f000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP", 0x1f000000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL2A_NOCP_LH", 0x1f000000, 0x1808, 0xffffffff, 0, 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_NOCL2A_NOC_USER", 0x1f000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_NOCL2A_QCH", 0x1f000000, 0x3130, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_NOCL2A_QCH", 0x1f000000, 0x3134, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D2_G2D_QCH", 0x1f000000, 0x3138, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_HSI2_QCH", 0x1f000000, 0x313c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_MISC_QCH", 0x1f000000, 0x3140, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL2A_CD_QCH", 0x1f000000, 0x3144, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL2A_CD_QCH", 0x1f000000, 0x3148, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL2A_QCH", 0x1f000000, 0x314c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_CSIS_QCH", 0x1f000000, 0x3150, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_DPU_QCH", 0x1f000000, 0x3154, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_G2D_QCH", 0x1f000000, 0x3158, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_GDC_QCH", 0x1f000000, 0x315c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_MCSC_QCH", 0x1f000000, 0x3160, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_MFC_QCH", 0x1f000000, 0x3164, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_TNR_QCH", 0x1f000000, 0x3168, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_CSIS_QCH", 0x1f000000, 0x316c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_DPU_QCH", 0x1f000000, 0x3170, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_G2D_QCH", 0x1f000000, 0x3174, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_GDC_QCH", 0x1f000000, 0x3178, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_MCSC_QCH", 0x1f000000, 0x317c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_MFC_QCH", 0x1f000000, 0x3180, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_TNR_QCH", 0x1f000000, 0x3184, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D2_DPU_QCH", 0x1f000000, 0x3188, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D2_GDC_QCH", 0x1f000000, 0x318c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D2_MCSC_QCH", 0x1f000000, 0x3190, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D2_TNR_QCH", 0x1f000000, 0x3194, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D3_TNR_QCH", 0x1f000000, 0x3198, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D4_TNR_QCH", 0x1f000000, 0x319c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_BO_QCH", 0x1f000000, 0x31a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_DNS_QCH", 0x1f000000, 0x31a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_G3AA_QCH", 0x1f000000, 0x31a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D_IPP_QCH", 0x1f000000, 0x31ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI2_CD_QCH", 0x1f000000, 0x31cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI2_CD_QCH", 0x1f000000, 0x3204, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_NOCL2A_CMU_NOCL2A_QCH", 0x1f000000, 0x3220, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_BO_QCH", 0x1f000000, 0x3224, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_CSIS_QCH", 0x1f000000, 0x3228, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_DISP_QCH", 0x1f000000, 0x322c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_DNS_QCH", 0x1f000000, 0x3230, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_DPU_QCH", 0x1f000000, 0x3234, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_G2D_QCH", 0x1f000000, 0x3238, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_G3AA_QCH", 0x1f000000, 0x323c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_GDC_QCH", 0x1f000000, 0x3240, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_HSI2_QCH", 0x1f000000, 0x3244, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_IPP_QCH", 0x1f000000, 0x3248, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_ITP_QCH", 0x1f000000, 0x324c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MCSC_QCH", 0x1f000000, 0x3250, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MFC_QCH", 0x1f000000, 0x3254, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_PDP_QCH", 0x1f000000, 0x3258, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_TNR_QCH", 0x1f000000, 0x325c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_NOCL2A_QCH", 0x1f000000, 0x3260, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_D_NOCL2A_QCH", 0x1f000000, 0x3264, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_P_NOCL2A_QCH", 0x1f000000, 0x3268, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION", 0x1f000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1f020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1f020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl2a_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "NOCL2A_STATUS", 0x18060000, 0x1a84, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl2a_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL2A_CMU_NOCL2A_CONTROLLER_OPTION", 0x1f000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL2A_CONFIGURATION", 0x18060000, 0x1a80, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL2A_STATUS", 0x18060000, 0x1a84, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1a_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1A_CONFIGURATION", 0x18060000, 0x1b00, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL1A_STATUS", 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1a_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1A_NOCD_LH", 0x20000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP", 0x20000000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL1A_NOCP_LH", 0x20000000, 0x1808, 0xffffffff, 0, 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_NOCL1A_NOC_USER", 0x20000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_NOCL1A_QCH", 0x20000000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_NOCL1A_QCH", 0x20000000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D0_G3D_QCH", 0x20000000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D1_G3D_QCH", 0x20000000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D2_G3D_QCH", 0x20000000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D3_G3D_QCH", 0x20000000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_TPU_QCH", 0x20000000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1A_CD_QCH", 0x20000000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1A_CD_QCH", 0x20000000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1A_QCH", 0x20000000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D0_AUR_QCH", 0x20000000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_D1_AUR_QCH", 0x20000000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_AUR_CD_QCH", 0x20000000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_G3D_CD_QCH", 0x20000000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_TPU_CD_QCH", 0x20000000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_AUR_CD_QCH", 0x20000000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_G3D_CD_QCH", 0x20000000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_TPU_CD_QCH", 0x20000000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_NOCL1A_CMU_NOCL1A_QCH", 0x20000000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPCFW_G3D0_QCH", 0x20000000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPCFW_G3D1_QCH", 0x20000000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_AUR_D0_CYCLE_QCH", 0x20000000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_AUR_D0_EVENT_QCH", 0x20000000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_AUR_D1_EVENT_QCH", 0x20000000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_G3D_D0_CYCLE_QCH", 0x20000000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_G3D_D0_EVENT_QCH", 0x20000000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_G3D_D1_EVENT_QCH", 0x20000000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_G3D_D2_EVENT_QCH", 0x20000000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_G3D_D3_EVENT_QCH", 0x20000000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL2A_M0_CYCLE_QCH", 0x20000000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL2A_M0_EVENT_QCH", 0x20000000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL2A_M1_EVENT_QCH", 0x20000000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL2A_M2_EVENT_QCH", 0x20000000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL2A_M3_EVENT_QCH", 0x20000000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_TPU_CYCLE_QCH", 0x20000000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_TPU_EVENT_QCH", 0x20000000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_AUR_QCH", 0x20000000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_G3D_QCH", 0x20000000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_TPU_QCH", 0x20000000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_G3D0_QCH", 0x20000000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_G3D1_QCH", 0x20000000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_G3D2_QCH", 0x20000000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_G3D3_QCH", 0x20000000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3D_QCH_D0", 0x20000000, 0x3104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3D_QCH_D1", 0x20000000, 0x3108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3D_QCH_D2", 0x20000000, 0x310c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3D_QCH_D3", 0x20000000, 0x3110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3D_QCH_MPTW", 0x20000000, 0x3114, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_NOCL1A_QCH", 0x20000000, 0x3118, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_D_NOCL1A_QCH", 0x20000000, 0x311c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_P_NOCL1A_QCH", 0x20000000, 0x3120, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION", 0x20000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x20020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x20020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1a_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "NOCL1A_STATUS", 0x18060000, 0x1b04, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl1a_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1A_CMU_NOCL1A_CONTROLLER_OPTION", 0x20000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1A_CONFIGURATION", 0x18060000, 0x1b00, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL1A_STATUS", 0x18060000, 0x1b04, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl0_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL0_CONFIGURATION", 0x18060000, 0x1b80, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL0_STATUS", 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl0_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL0_NOCD_LH", 0x1e000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL0_NOCP", 0x1e000000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_NOCL0_NOCP_LH", 0x1e000000, 0x1808, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_SLC1_DCLK", 0x1e000000, 0x180c, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_SLC2_DCLK", 0x1e000000, 0x1810, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_SLC3_DCLK", 0x1e000000, 0x1814, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_SLC_DCLK", 0x1e000000, 0x1818, 0xffffffff, 0, 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_NOCL0_NOC_USER", 0x1e000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ASYNCSFR_WR_SMC_QCH", 0x1e000000, 0x3124, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_BDU_QCH", 0x1e000000, 0x3128, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CCI_QCH", 0x1e000000, 0x312c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CPE425_QCH", 0x1e000000, 0x3130, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_NOCL0_QCH", 0x1e000000, 0x3134, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_NOCL0_QCH", 0x1e000000, 0x3138, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_MI_D_EH_QCH", 0x1e000000, 0x313c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACE_MI_D0_CPUCL0_QCH", 0x1e000000, 0x3140, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACE_MI_D1_CPUCL0_QCH", 0x1e000000, 0x3144, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC0_CU_QCH", 0x1e000000, 0x3148, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC0_QCH", 0x1e000000, 0x314c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC1_CU_QCH", 0x1e000000, 0x3150, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC1_QCH", 0x1e000000, 0x3154, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC2_CU_QCH", 0x1e000000, 0x3158, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC2_QCH", 0x1e000000, 0x315c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC3_CU_QCH", 0x1e000000, 0x3160, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_DMC3_QCH", 0x1e000000, 0x3164, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1A_CU_QCH", 0x1e000000, 0x3168, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1A_QCH", 0x1e000000, 0x316c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1B_CU_QCH", 0x1e000000, 0x3170, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL1B_QCH", 0x1e000000, 0x3174, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL2A_CU_QCH", 0x1e000000, 0x3178, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_G_NOCL2A_QCH", 0x1e000000, 0x317c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_DMC0_CU_QCH", 0x1e000000, 0x3180, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_DMC1_CU_QCH", 0x1e000000, 0x3184, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_DMC2_CU_QCH", 0x1e000000, 0x3188, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_DMC3_CU_QCH", 0x1e000000, 0x318c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1A_CU_QCH", 0x1e000000, 0x3190, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL1B_CU_QCH", 0x1e000000, 0x3194, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_G_NOCL2A_CU_QCH", 0x1e000000, 0x3198, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_MI_T_BDU_CD_QCH", 0x1e000000, 0x319c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_MI_T_SLC_CD_QCH", 0x1e000000, 0x31a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_T_BDU_CD_QCH", 0x1e000000, 0x31a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_T_BDU_QCH", 0x1e000000, 0x31a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_T_SLC_CD_QCH", 0x1e000000, 0x31ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_T_SLC_QCH", 0x1e000000, 0x31b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_ALIVE_CD_QCH", 0x1e000000, 0x31b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_CPUCL0_CD_QCH", 0x1e000000, 0x31b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_EH_CD_QCH", 0x1e000000, 0x31bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_GIC_CD_QCH", 0x1e000000, 0x31c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MIF0_CD_QCH", 0x1e000000, 0x31c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MIF1_CD_QCH", 0x1e000000, 0x31c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MIF2_CD_QCH", 0x1e000000, 0x31cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MIF3_CD_QCH", 0x1e000000, 0x31d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MISC_CD_QCH", 0x1e000000, 0x31d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC0_CD_QCH", 0x1e000000, 0x31d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC1_CD_QCH", 0x1e000000, 0x31dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_ALIVE_CD_QCH", 0x1e000000, 0x31e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_CPUCL0_CD_QCH", 0x1e000000, 0x31e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_EH_CD_QCH", 0x1e000000, 0x31e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_GIC_CD_QCH", 0x1e000000, 0x31ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MIF0_CD_QCH", 0x1e000000, 0x31f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MIF1_CD_QCH", 0x1e000000, 0x31f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MIF2_CD_QCH", 0x1e000000, 0x31f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MIF3_CD_QCH", 0x1e000000, 0x31fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MISC_CD_QCH", 0x1e000000, 0x3200, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC0_CD_QCH", 0x1e000000, 0x3204, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC1_CD_QCH", 0x1e000000, 0x3208, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_NOCL0_CMU_NOCL0_QCH", 0x1e000000, 0x320c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CCI_M1_CYCLE_QCH", 0x1e000000, 0x3210, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CCI_M1_EVENT_QCH", 0x1e000000, 0x3214, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CCI_M2_EVENT_QCH", 0x1e000000, 0x3218, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CCI_M3_EVENT_QCH", 0x1e000000, 0x321c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CCI_M4_EVENT_QCH", 0x1e000000, 0x3220, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CPUCL0_D0_CYCLE_QCH", 0x1e000000, 0x3224, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CPUCL0_D0_EVENT_QCH", 0x1e000000, 0x3228, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_CPUCL0_D1_EVENT_QCH", 0x1e000000, 0x322c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_EH_CYCLE_QCH", 0x1e000000, 0x3230, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_EH_EVENT_QCH", 0x1e000000, 0x3234, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_IO_CYCLE_QCH", 0x1e000000, 0x3238, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_IO_EVENT_QCH", 0x1e000000, 0x323c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1A_M0_CYCLE_QCH", 0x1e000000, 0x3240, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1A_M0_EVENT_QCH", 0x1e000000, 0x3244, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1A_M1_EVENT_QCH", 0x1e000000, 0x3248, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1A_M2_EVENT_QCH", 0x1e000000, 0x324c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1A_M3_EVENT_QCH", 0x1e000000, 0x3250, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1B_M0_CYCLE_QCH", 0x1e000000, 0x3254, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPC_NOCL1B_M0_EVENT_QCH", 0x1e000000, 0x3258, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_ACE_CPUCL0_D0_QCH", 0x1e000000, 0x325c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_ACE_CPUCL0_D1_QCH", 0x1e000000, 0x3260, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SFR_APBIF_CMU_TOPC_QCH", 0x1e000000, 0x3264, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLC_CB_TOP_QCH", 0x1e000000, 0x3268, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_G_NOCL0_QCH", 0x1e000000, 0x326c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_ALIVE_QCH", 0x1e000000, 0x3270, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_CPUCL0_QCH", 0x1e000000, 0x3274, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_EH_QCH", 0x1e000000, 0x3278, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_GIC_QCH", 0x1e000000, 0x327c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MIF0_QCH", 0x1e000000, 0x3280, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MIF1_QCH", 0x1e000000, 0x3284, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MIF2_QCH", 0x1e000000, 0x3288, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MIF3_QCH", 0x1e000000, 0x328c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_MISC_QCH", 0x1e000000, 0x3290, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_PERIC0_QCH", 0x1e000000, 0x3294, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_P_PERIC1_QCH", 0x1e000000, 0x3298, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_NOCL0_QCH", 0x1e000000, 0x329c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_D_NOCL0_QCH", 0x1e000000, 0x32a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TREX_P_NOCL0_QCH", 0x1e000000, 0x32a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1b84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL0_CMU_NOCL0_CONTROLLER_OPTION", 0x1e000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT0_DRCG_EN", 0x1e020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT1_DRCG_EN", 0x1e020000, 0x010c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1e020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl0_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "NOCL0_STATUS", 0x18060000, 0x1b84, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq nocl0_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL0_CMU_NOCL0_CONTROLLER_OPTION", 0x1e000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL0_CONFIGURATION", 0x18060000, 0x1b80, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "NOCL0_STATUS", 0x18060000, 0x1b84, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq eh_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EH_CONFIGURATION", 0x18060000, 0x1c00, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "EH_STATUS", 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq eh_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_EH_NOCP", 0x17000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_EH_NOCP_LH", 0x17000000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_EH_NOC", 0x17000000, 0x1004, 0xffffffff, 0, 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_EH_NOC_USER", 0x17000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_EH_PLL_NOCL0_USER", 0x17000000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_EH_QCH", 0x17000000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_EH_CMU_EH_QCH", 0x17000000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_EH_QCH", 0x17000000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_EH_QCH", 0x17000000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_EH_QCH", 0x17000000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_IP_EH_QCH", 0x17000000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_EH_CU_QCH", 0x17000000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_IP_EH_QCH", 0x17000000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_EH_CU_QCH", 0x17000000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_EH_QCH", 0x17000000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_EH_QCH", 0x17000000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_EH_QCH", 0x17000000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_EH_QCH", 0x17000000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_EH_QCH", 0x17000000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_EH_QCH", 0x17000000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_EH_QCH", 0x17000000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1c04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "EH_CMU_EH_CONTROLLER_OPTION", 0x17000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x17020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x17020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_EH_QCH", 0x17000000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_EH_CMU_EH_QCH", 0x17000000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_EH_QCH", 0x17000000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_EH_QCH", 0x17000000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_EH_QCH", 0x17000000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_IP_EH_QCH", 0x17000000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_EH_CU_QCH", 0x17000000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_IP_EH_QCH", 0x17000000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_EH_CU_QCH", 0x17000000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_EH_QCH", 0x17000000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_EH_QCH", 0x17000000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_EH_QCH", 0x17000000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_EH_QCH", 0x17000000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_EH_QCH", 0x17000000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_EH_QCH", 0x17000000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_EH_QCH", 0x17000000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq eh_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "EH_STATUS", 0x18060000, 0x1c04, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq eh_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EH_CMU_EH_CONTROLLER_OPTION", 0x17000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EH_CONFIGURATION", 0x18060000, 0x1c00, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "EH_STATUS", 0x18060000, 0x1c04, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq embedded_g3d_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EMBEDDED_G3D_CONFIGURATION", 0x18060000, 0x2000, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "EMBEDDED_G3D_STATUS", 0x18060000, 0x2004, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq embedded_g3d_save[] = { +}; + +struct pmucal_seq embedded_g3d_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "EMBEDDED_G3D_STATUS", 0x18060000, 0x2004, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq embedded_g3d_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EMBEDDED_G3D_CONFIGURATION", 0x18060000, 0x2000, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "EMBEDDED_G3D_STATUS", 0x18060000, 0x2004, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3d_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_CONFIGURATION", 0x18060000, 0x1e00, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3D_STATUS", 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3d_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_G3D_ADD_CH_CLK", 0x27f00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3D_L2_GLB", 0x27f00000, 0x1804, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3D_NOCP", 0x27f00000, 0x1808, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3D_NOCP_LH", 0x27f00000, 0x180c, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3D_STACKS", 0x27f00000, 0x1810, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3D_TOP", 0x27f00000, 0x1814, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_G3D_L2_GLB", 0x27f00000, 0x1000, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_G3D_STACKS", 0x27f00000, 0x1004, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_G3D_TOP", 0x27f00000, 0x1008, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_LOCKTIME_PLL_G3D", 0x27f00000, 0x4, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_LOCKTIME_PLL_G3D_L2", 0x27f00000, 0x8, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON1_PLL_G3D", 0x27f00000, 0x104, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON1_PLL_G3D_L2", 0x27f00000, 0x144, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON2_PLL_G3D", 0x27f00000, 0x108, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON2_PLL_G3D_L2", 0x27f00000, 0x148, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON3_PLL_G3D", 0x27f00000, 0x10c, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON3_PLL_G3D_L2", 0x27f00000, 0x14c, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_PLL_G3D", 0x27f00000, 0x0100, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_PLL_G3D_L2", 0x27f00000, 0x0140, 0xffffffff, 0, 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_COREGROUP_USER", 0x27f00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_STACKS_USER", 0x27f00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_EMBEDDED_G3D_TOP_USER", 0x27f00000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G3D_NOCD_USER", 0x27f00000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G3D_GLB_USER", 0x27f00000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER", 0x27f00000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ADD_APBIF_G3D_QCH", 0x27f00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ADM_AHB_G_GPU_QCH", 0x27f00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ASB_G3D_QCH_LH_D0_G3D", 0x27f00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ASB_G3D_QCH_LH_D1_G3D", 0x27f00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ASB_G3D_QCH_LH_D2_G3D", 0x27f00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ASB_G3D_QCH_LH_D3_G3D", 0x27f00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_BUSIF_HPMG3D_QCH", 0x27f00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_G3D_QCH", 0x27f00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_G3D_CMU_G3D_QCH", 0x27f00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_G3D_QCH", 0x27f00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPU_QCH", 0x27f00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_IP_G3D_QCH", 0x27f00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_G3D_CU_QCH", 0x27f00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_IP_G3D_QCH", 0x27f00000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_G3D_CU_QCH", 0x27f00000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH", 0x27f00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_G3D_QCH", 0x27f00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_G3D_QCH", 0x27f00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_G3D_QCH", 0x27f00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "G3D_CMU_G3D_CONTROLLER_OPTION", 0x27f00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION", 0x27f00000, 0x0804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x27f20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x27f20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_ADD_G3D_QCH", 0x27f00000, 0x7000, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ADD_APBIF_G3D_QCH", 0x27f00000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ADM_AHB_G_GPU_QCH", 0x27f00000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ASB_G3D_QCH_LH_D0_G3D", 0x27f00000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ASB_G3D_QCH_LH_D1_G3D", 0x27f00000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ASB_G3D_QCH_LH_D2_G3D", 0x27f00000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ASB_G3D_QCH_LH_D3_G3D", 0x27f00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_BUSIF_HPMG3D_QCH", 0x27f00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_G3D_QCH", 0x27f00000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_G3D_CMU_G3D_QCH", 0x27f00000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_G3D_QCH", 0x27f00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPU_QCH", 0x27f00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_IP_G3D_QCH", 0x27f00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_G3D_CU_QCH", 0x27f00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_IP_G3D_QCH", 0x27f00000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_G3D_CU_QCH", 0x27f00000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_G3D_DD_QCH", 0x27f00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_G3D_QCH", 0x27f00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_G3D_QCH", 0x27f00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_G3D_QCH", 0x27f00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3d_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "G3D_STATUS", 0x18060000, 0x1e04, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3d_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_CMU_G3D_CONTROLLER_OPTION", 0x27f00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_CONFIGURATION", 0x18060000, 0x1e00, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3D_STATUS", 0x18060000, 0x1e04, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi0_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI0_CONFIGURATION", 0x18060000, 0x2080, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "HSI0_STATUS", 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi0_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_LOCKTIME_PLL_USB", 0x11000000, 0x0004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON2_PLL_USB", 0x11000000, 0x0148, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON4_PLL_USB", 0x11000000, 0x0150, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_HSI0_NOC_LH", 0x11000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_HSI0_USB", 0x11000000, 0x1804, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD", 0x11000000, 0x1808, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_HSI0_NOC", 0x11000000, 0x1000, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF", 0x11000000, 0x1004, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD", 0x11000000, 0x1008, 0xffffffff, 0, 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER", 0x11000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER", 0x11000000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER", 0x11000000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER", 0x11000000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER", 0x11000000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER", 0x11000000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER", 0x11000000, 0x0660, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON3_PLL_USB", 0x11000000, 0x014c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CHECK_SKIP, "PLL_CON3_PLL_USB", 0x11000000, 0x014c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "PLL_CON3_PLL_USB", 0x11000000, 0x014c, (0x1 << 29), (0x1 << 29), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_PLL_USB", 0x11000000, 0x0140, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON1_PLL_USB", 0x11000000, 0x0144, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DP_LINK_QCH_GTC_CLK", 0x11000000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DP_LINK_QCH_PCLK", 0x11000000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_HSI0_QCH", 0x11000000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ETR_MIU_QCH_ACLK", 0x11000000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ETR_MIU_QCH_PCLK", 0x11000000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_HSI0_QCH", 0x11000000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_HSI0_CMU_HSI0_QCH", 0x11000000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_HSI0_QCH", 0x11000000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LG_ETR_HSI0_CU_QCH", 0x11000000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LP1_AOC_CU_QCH", 0x11000000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI0_CU_QCH", 0x11000000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_HSI0_AOC_QCH", 0x11000000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LG_ETR_HSI0_CU_QCH", 0x11000000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LP1_AOC_CU_QCH", 0x11000000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI0_CU_QCH", 0x11000000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_HSI0_AOC_QCH", 0x11000000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_HSI0_NOCL1B_QCH", 0x11000000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_LG_ETR_HSI0_QCH", 0x11000000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_LP1_AOC_QCH", 0x11000000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_HSI0_QCH", 0x11000000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_USB_QCH", 0x11000000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_USB_QCH_S1", 0x11000000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_USB_QCH_S2", 0x11000000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_HSI0_QCH", 0x11000000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_HSI0_CTRL_QCH", 0x11000000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_HSI0_LINK_QCH", 0x11000000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USB31DRD_QCH_APB", 0x11000000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USB31DRD_QCH_DBG", 0x11000000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USB31DRD_QCH_PCS", 0x11000000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USB31DRD_QCH_SLV_CTRL", 0x11000000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USB31DRD_QCH_SLV_LINK", 0x11000000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2084, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "HSI0_CMU_HSI0_CONTROLLER_OPTION", 0x11000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x11020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x11020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi0_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "HSI0_STATUS", 0x18060000, 0x2084, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi0_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI0_CMU_HSI0_CONTROLLER_OPTION", 0x11000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PLL_CON0_PLL_USB", + 0x11000000, 0x0140, (0x1 << 4), (0x0 << 4), + 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI0_CONFIGURATION", 0x18060000, 0x2080, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "HSI0_STATUS", 0x18060000, 0x2084, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi2_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI2_CONFIGURATION", 0x18060000, 0x2180, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "HSI2_STATUS", 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi2_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_HSI2_NOCP", 0x14400000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_HSI2_NOC_LH", 0x14400000, 0x1804, 0xffffffff, 0, 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI2_NOC_USER", 0x14400000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER", 0x14400000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER", 0x14400000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER", 0x14400000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_HSI2_QCH", 0x14400000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_HSI2_QCH", 0x14400000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_HSI2UFS_QCH", 0x14400000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_HSI2_QCH", 0x14400000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_HSI2_CMU_HSI2_QCH", 0x14400000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_HSI2_QCH", 0x14400000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI2_CU_QCH", 0x14400000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI2_CU_QCH", 0x14400000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MMC_CARD_QCH", 0x14400000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_APB_1", 0x14400000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_APB_2", 0x14400000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_AXI_1", 0x14400000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_AXI_2", 0x14400000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_DBG_1", 0x14400000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_DBG_2", 0x14400000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_PCS_APB", 0x14400000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_PMA_APB", 0x14400000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_1_QCH_UDBG", 0x14400000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4A_1_QCH", 0x14400000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4B_1_QCH", 0x14400000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_HSI2_QCH", 0x14400000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_MMC_CARD_HSI2_QCH", 0x14400000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4A_HSI2_QCH", 0x14400000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4B_HSI2_QCH", 0x14400000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_UFS_EMBD_HSI2_QCH", 0x14400000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_HSI2_QCH", 0x14400000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_HSI2_QCH", 0x14400000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH", 0x14400000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH", 0x14400000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI2_QCH_S1", 0x14400000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI2_QCH_S2", 0x14400000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_HSI2_QCH", 0x14400000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH", 0x14400000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH", 0x14400000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH", 0x14400000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH", 0x14400000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UFS_EMBD_QCH", 0x14400000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UFS_EMBD_QCH_FMP", 0x14400000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2184, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "HSI2_CMU_HSI2_CONTROLLER_OPTION", 0x14400000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x14420000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x14420000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi2_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "HSI2_STATUS", 0x18060000, 0x2184, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq hsi2_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI2_CMU_HSI2_CONTROLLER_OPTION", 0x14400000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "HSI2_CONFIGURATION", 0x18060000, 0x2180, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "HSI2_STATUS", 0x18060000, 0x2184, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dpu_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DPU_CONFIGURATION", 0x18060000, 0x2200, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DPU_STATUS", 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dpu_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_DPU_NOCP", 0x1c000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_DPU_NOC_USER", 0x1c000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DPUF_QCH_DPU_DMA", 0x1c000000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DPUF_QCH_DPU_DPP", 0x1c000000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DPU_CMU_DPU_QCH", 0x1c000000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_DPU_QCH", 0x1c000000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_DPU_QCH", 0x1c000000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_DPU_QCH", 0x1c000000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_DPU_QCH", 0x1c000000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D2_DPU_QCH", 0x1c000000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_DPUD0_QCH", 0x1c000000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_DPUD1_QCH", 0x1c000000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_DPUD2_QCH", 0x1c000000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_DPU_QCH", 0x1c000000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_DPU0_QCH", 0x1c000000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_DPU1_QCH", 0x1c000000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_DPU2_QCH", 0x1c000000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD0_QCH_S1", 0x1c000000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD0_QCH_S2", 0x1c000000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD1_QCH_S1", 0x1c000000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD1_QCH_S2", 0x1c000000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD2_QCH_S1", 0x1c000000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DPUD2_QCH_S2", 0x1c000000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_DPU_QCH", 0x1c000000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2204, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DPU_CMU_DPU_CONTROLLER_OPTION", 0x1c000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1c020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L0_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x0140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L1_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x1140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L2_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x2140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L3_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x3140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L4_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x4140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L5_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x5140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L12_WDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0xc140, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L0_GLB_GLB_CGEN", 0x1c0b0000, 0x0f14, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L2_GLB_GLB_CGEN", 0x1c0b0000, 0x2f14, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "L4_GLB_GLB_CGEN", 0x1c0b0000, 0x4f14, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1c020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DPUF_QCH_DPU_DMA", 0x1c000000, 0x7014, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DPUF_QCH_DPU_DPP", 0x1c000000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DPU_CMU_DPU_QCH", 0x1c000000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_DPU_QCH", 0x1c000000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_DPU_QCH", 0x1c000000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_DPU_QCH", 0x1c000000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_DPU_QCH", 0x1c000000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D2_DPU_QCH", 0x1c000000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_DPUD0_QCH", 0x1c000000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_DPUD1_QCH", 0x1c000000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_DPUD2_QCH", 0x1c000000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_DPU_QCH", 0x1c000000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_DPU0_QCH", 0x1c000000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_DPU1_QCH", 0x1c000000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_DPU2_QCH", 0x1c000000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD0_QCH_S1", 0x1c000000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD0_QCH_S2", 0x1c000000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD1_QCH_S1", 0x1c000000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD1_QCH_S2", 0x1c000000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD2_QCH_S1", 0x1c000000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DPUD2_QCH_S2", 0x1c000000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_DPU_QCH", 0x1c000000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dpu_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "DPU_STATUS", 0x18060000, 0x2204, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dpu_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DPU_CMU_DPU_CONTROLLER_OPTION", 0x1c000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DPU_CONFIGURATION", 0x18060000, 0x2200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DPU_STATUS", 0x18060000, 0x2204, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq disp_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISP_CONFIGURATION", 0x18060000, 0x2280, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DISP_STATUS", 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq disp_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_DISP_NOCP", 0x1c200000, 0x1804, 0xffffffff, 0, 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_DISP_NOC_USER", 0x1c200000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DISP_CMU_DISP_QCH", 0x1c200000, 0x3008, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DPUB_QCH", 0x1c200000, 0x300c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_DISP_QCH", 0x1c200000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_DISP_QCH", 0x1c200000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_DISP_QCH", 0x1c200000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_DISP_QCH", 0x1c200000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2284, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DISP_CMU_DISP_CONTROLLER_OPTION", 0x1c200000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1c220000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1c220000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DISP_CMU_DISP_QCH", 0x1c200000, 0x7008, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DPUB_QCH", 0x1c200000, 0x700c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_DISP_QCH", 0x1c200000, 0x7010, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_DISP_QCH", 0x1c200000, 0x7014, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_DISP_QCH", 0x1c200000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_DISP_QCH", 0x1c200000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq disp_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "DISP_STATUS", 0x18060000, 0x2284, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq disp_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISP_CMU_DISP_CONTROLLER_OPTION", 0x1c200000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DISP_CONFIGURATION", 0x18060000, 0x2280, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DISP_STATUS", 0x18060000, 0x2284, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g2d_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_CONFIGURATION", 0x18060000, 0x2300, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G2D_STATUS", 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g2d_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G2D_NOCP", 0x1c600000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G2D_G2D_USER", 0x1c600000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER", 0x1c600000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_G2D_QCH", 0x1c600000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_G2D_CMU_G2D_QCH", 0x1c600000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_G2D_QCH", 0x1c600000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_G2D_QCH", 0x1c600000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_JPEG_QCH", 0x1c600000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D2_G2D_QCH", 0x1c600000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_G2D_QCH", 0x1c600000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_G2D_QCH", 0x1c600000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_G2D_QCH", 0x1c600000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_G2D_QCH", 0x1c600000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D2_G2D_QCH", 0x1c600000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_G2D_QCH", 0x1c600000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_G2D_QCH", 0x1c600000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_G2D_QCH", 0x1c600000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D2_G2D_QCH", 0x1c600000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_G2D_QCH_0", 0x1c600000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_G2D_QCH_1", 0x1c600000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_G2D_QCH_0", 0x1c600000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_G2D_QCH_1", 0x1c600000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_G2D_QCH_0", 0x1c600000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_G2D_QCH_1", 0x1c600000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_G2D_QCH", 0x1c600000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2304, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "G2D_CMU_G2D_CONTROLLER_OPTION", 0x1c600000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1c620000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1c620000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_G2D_QCH", 0x1c600000, 0x7014, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_G2D_CMU_G2D_QCH", 0x1c600000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_G2D_QCH", 0x1c600000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_G2D_QCH", 0x1c600000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_JPEG_QCH", 0x1c600000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D2_G2D_QCH", 0x1c600000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_G2D_QCH", 0x1c600000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_G2D_QCH", 0x1c600000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_G2D_QCH", 0x1c600000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_G2D_QCH", 0x1c600000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D2_G2D_QCH", 0x1c600000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_G2D_QCH", 0x1c600000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_G2D_QCH", 0x1c600000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_G2D_QCH", 0x1c600000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D2_G2D_QCH", 0x1c600000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_G2D_QCH_0", 0x1c600000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_G2D_QCH_1", 0x1c600000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_G2D_QCH_0", 0x1c600000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_G2D_QCH_1", 0x1c600000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_G2D_QCH_0", 0x1c600000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_G2D_QCH_1", 0x1c600000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_G2D_QCH", 0x1c600000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g2d_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "G2D_STATUS", 0x18060000, 0x2304, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g2d_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_CMU_G2D_CONTROLLER_OPTION", 0x1c600000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G2D_CONFIGURATION", 0x18060000, 0x2300, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G2D_STATUS", 0x18060000, 0x2304, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mfc_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFC_CONFIGURATION", 0x18060000, 0x2380, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MFC_STATUS", 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mfc_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_MFC_NOCP", 0x1c800000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MFC_MFC_USER", 0x1c800000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_MFC_QCH", 0x1c800000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_MFC_QCH", 0x1c800000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_MFC_QCH", 0x1c800000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_MFC_QCH", 0x1c800000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MFC_CMU_MFC_QCH", 0x1c800000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MFC_QCH", 0x1c800000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_MFC_QCH", 0x1c800000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_MFC_QCH", 0x1c800000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH", 0x1c800000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_MFC_QCH", 0x1c800000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_MFC_QCH", 0x1c800000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_MFC_QCH", 0x1c800000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_MFC_QCH_0", 0x1c800000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_MFC_QCH_1", 0x1c800000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_MFC_QCH_0", 0x1c800000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_MFC_QCH_1", 0x1c800000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_MFC_QCH", 0x1c800000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2384, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MFC_CMU_MFC_CONTROLLER_OPTION", 0x1c800000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1c820000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1c820000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_MFC_QCH", 0x1c800000, 0x7010, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_MFC_QCH", 0x1c800000, 0x7014, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_MFC_QCH", 0x1c800000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_MFC_QCH", 0x1c800000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MFC_CMU_MFC_QCH", 0x1c800000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MFC_QCH", 0x1c800000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_MFC_QCH", 0x1c800000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_MFC_QCH", 0x1c800000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_MFC_NOCD_SW_RESET_QCH", 0x1c800000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_MFC_QCH", 0x1c800000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_MFC_QCH", 0x1c800000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_MFC_QCH", 0x1c800000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_MFC_QCH_0", 0x1c800000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_MFC_QCH_1", 0x1c800000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_MFC_QCH_0", 0x1c800000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_MFC_QCH_1", 0x1c800000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_MFC_QCH", 0x1c800000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mfc_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "MFC_STATUS", 0x18060000, 0x2384, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mfc_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFC_CMU_MFC_CONTROLLER_OPTION", 0x1c800000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MFC_CONFIGURATION", 0x18060000, 0x2380, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MFC_STATUS", 0x18060000, 0x2384, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq csis_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CSIS_CONFIGURATION", 0x18060000, 0x2400, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "CSIS_STATUS", 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq csis_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_CSIS_NOCP", 0x1a400000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_CSIS_NOC_USER", 0x1a400000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CSISX8_QCH_C2_CSIS", 0x1a400000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CSISX8_QCH_CSIS_DMA", 0x1a400000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CSISX8_QCH_EBUF", 0x1a400000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_CSIS_CMU_CSIS_QCH", 0x1a400000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_CSIS_QCH", 0x1a400000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_CSIS_QCH", 0x1a400000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH", 0x1a400000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH", 0x1a400000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH", 0x1a400000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH", 0x1a400000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH", 0x1a400000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH", 0x1a400000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH", 0x1a400000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH", 0x1a400000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH", 0x1a400000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH", 0x1a400000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH", 0x1a400000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH", 0x1a400000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH", 0x1a400000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH", 0x1a400000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH", 0x1a400000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_CSIS_QCH", 0x1a400000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_CSIS_QCH", 0x1a400000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0", 0x1a400000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1", 0x1a400000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2", 0x1a400000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3", 0x1a400000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4", 0x1a400000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5", 0x1a400000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6", 0x1a400000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7", 0x1a400000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_QCH", 0x1a400000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_QCH", 0x1a400000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_CSIS_DMA0_QCH", 0x1a400000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_CSIS_DMA1_QCH", 0x1a400000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_CSIS_DMA2_QCH", 0x1a400000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_CSIS_DMA3_QCH", 0x1a400000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_STRP0_QCH", 0x1a400000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_STRP1_QCH", 0x1a400000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_STRP2_QCH", 0x1a400000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ZSL0_QCH", 0x1a400000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ZSL1_QCH", 0x1a400000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ZSL2_QCH", 0x1a400000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_CSIS_QCH", 0x1a400000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_QCH", 0x1a400000, 0x3108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_QCH", 0x1a400000, 0x310c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_CSIS_QCH_S1", 0x1a400000, 0x3110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_CSIS_QCH_S2", 0x1a400000, 0x3114, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_CSIS_QCH_S1", 0x1a400000, 0x3118, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_CSIS_QCH_S2", 0x1a400000, 0x311c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_CSIS_QCH", 0x1a400000, 0x3120, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2404, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CSIS_CMU_CSIS_CONTROLLER_OPTION", 0x1a400000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1a420000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1a420000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_CSISX8_QCH_C2_CSIS", 0x1a400000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_CSISX8_QCH_CSIS_DMA", 0x1a400000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_CSISX8_QCH_EBUF", 0x1a400000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_CSIS_CMU_CSIS_QCH", 0x1a400000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_CSIS_QCH", 0x1a400000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_CSIS_QCH", 0x1a400000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_PDP_CSIS_QCH", 0x1a400000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_PDP_CSIS_QCH", 0x1a400000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF2_PDP_CSIS_QCH", 0x1a400000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_SOTF0_IPP_CSIS_QCH", 0x1a400000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_SOTF1_IPP_CSIS_QCH", 0x1a400000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_SOTF2_IPP_CSIS_QCH", 0x1a400000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_MCSC_CSIS_QCH", 0x1a400000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ZOTF0_IPP_CSIS_QCH", 0x1a400000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ZOTF1_IPP_CSIS_QCH", 0x1a400000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ZOTF2_IPP_CSIS_QCH", 0x1a400000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_CSIS_PDP_QCH", 0x1a400000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_CSIS_PDP_QCH", 0x1a400000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF2_CSIS_PDP_QCH", 0x1a400000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_CSIS_PDP_QCH", 0x1a400000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LD_PDP_CSIS_QCH", 0x1a400000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_CSIS_QCH", 0x1a400000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_CSIS_QCH", 0x1a400000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS0", 0x1a400000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS1", 0x1a400000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS2", 0x1a400000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS3", 0x1a400000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS4", 0x1a400000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS5", 0x1a400000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS6", 0x1a400000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MIPI_PHY_LINK_WRAP_QCH_CSIS7", 0x1a400000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_QCH", 0x1a400000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_QCH", 0x1a400000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_CSIS_DMA0_QCH", 0x1a400000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_CSIS_DMA1_QCH", 0x1a400000, 0x70dc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_CSIS_DMA2_QCH", 0x1a400000, 0x70e0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_CSIS_DMA3_QCH", 0x1a400000, 0x70e4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_STRP0_QCH", 0x1a400000, 0x70e8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_STRP1_QCH", 0x1a400000, 0x70ec, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_STRP2_QCH", 0x1a400000, 0x70f0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ZSL0_QCH", 0x1a400000, 0x70f4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ZSL1_QCH", 0x1a400000, 0x70f8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ZSL2_QCH", 0x1a400000, 0x70fc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_CSIS_QCH", 0x1a400000, 0x7100, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_QCH", 0x1a400000, 0x7108, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_QCH", 0x1a400000, 0x710c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_CSIS_QCH_S1", 0x1a400000, 0x7110, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_CSIS_QCH_S2", 0x1a400000, 0x7114, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_CSIS_QCH_S1", 0x1a400000, 0x7118, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_CSIS_QCH_S2", 0x1a400000, 0x711c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_CSIS_QCH", 0x1a400000, 0x7120, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq csis_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "CSIS_STATUS", 0x18060000, 0x2404, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq csis_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CSIS_CMU_CSIS_CONTROLLER_OPTION", 0x1a400000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CSIS_CONFIGURATION", 0x18060000, 0x2400, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "CSIS_STATUS", 0x18060000, 0x2404, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq pdp_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PDP_CONFIGURATION", 0x18060000, 0x2480, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "PDP_STATUS", 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq pdp_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PDP_NOCP", 0x1aa00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PDP_NOC_USER", 0x1aa00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PDP_VRA_USER", 0x1aa00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_PDP_QCH", 0x1aa00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_PDP_QCH", 0x1aa00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH", 0x1aa00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH", 0x1aa00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH", 0x1aa00000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH", 0x1aa00000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH", 0x1aa00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH", 0x1aa00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH", 0x1aa00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH", 0x1aa00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH", 0x1aa00000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH", 0x1aa00000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH", 0x1aa00000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH", 0x1aa00000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH", 0x1aa00000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH", 0x1aa00000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH", 0x1aa00000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH", 0x1aa00000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH", 0x1aa00000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH", 0x1aa00000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDP_CMU_PDP_QCH", 0x1aa00000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDP_TOP_QCH_C2_PDP", 0x1aa00000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDP_TOP_QCH_PDP_TOP", 0x1aa00000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_VRA_QCH", 0x1aa00000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDP_AF0_QCH", 0x1aa00000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDP_AF1_QCH", 0x1aa00000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDP_STAT0_QCH", 0x1aa00000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDP_STAT1_QCH", 0x1aa00000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_VRA_QCH", 0x1aa00000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_PDP_QCH", 0x1aa00000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PDP_STAT_QCH", 0x1aa00000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_VRA_QCH", 0x1aa00000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_PDP_QCH", 0x1aa00000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_VRA_QCH", 0x1aa00000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2484, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PDP_CMU_PDP_CONTROLLER_OPTION", 0x1aa00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1aa20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1aa20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_PDP_QCH", 0x1aa00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_PDP_QCH", 0x1aa00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_CSIS_PDP_QCH", 0x1aa00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_CSIS_PDP_QCH", 0x1aa00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF2_CSIS_PDP_QCH", 0x1aa00000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_CSIS_PDP_QCH", 0x1aa00000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_PDP_CSIS_QCH", 0x1aa00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_PDP_G3AA_QCH", 0x1aa00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_PDP_IPP_QCH", 0x1aa00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_PDP_CSIS_QCH", 0x1aa00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_PDP_G3AA_QCH", 0x1aa00000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_PDP_IPP_QCH", 0x1aa00000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF2_PDP_CSIS_QCH", 0x1aa00000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF2_PDP_G3AA_QCH", 0x1aa00000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF2_PDP_IPP_QCH", 0x1aa00000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_PDP_IPP_QCH", 0x1aa00000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_YOTF0_PDP_G3AA_QCH", 0x1aa00000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_YOTF1_PDP_G3AA_QCH", 0x1aa00000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LD_PDP_CSIS_QCH", 0x1aa00000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LD_PDP_DNS_QCH", 0x1aa00000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDP_CMU_PDP_QCH", 0x1aa00000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDP_TOP_QCH_C2_PDP", 0x1aa00000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDP_TOP_QCH_PDP_TOP", 0x1aa00000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_VRA_QCH", 0x1aa00000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDP_AF0_QCH", 0x1aa00000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDP_AF1_QCH", 0x1aa00000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDP_STAT0_QCH", 0x1aa00000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDP_STAT1_QCH", 0x1aa00000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_VRA_QCH", 0x1aa00000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_PDP_QCH", 0x1aa00000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_PDP_STAT_QCH", 0x1aa00000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_VRA_QCH", 0x1aa00000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_PDP_QCH", 0x1aa00000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_VRA_QCH", 0x1aa00000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq pdp_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "PDP_STATUS", 0x18060000, 0x2484, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq pdp_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PDP_CMU_PDP_CONTROLLER_OPTION", 0x1aa00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PDP_CONFIGURATION", 0x18060000, 0x2480, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "PDP_STATUS", 0x18060000, 0x2484, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dns_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DNS_CONFIGURATION", 0x18060000, 0x2500, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DNS_STATUS", 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dns_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_DNS_NOCP", 0x1b000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_DNS_NOC_USER", 0x1b000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DNS_CMU_DNS_QCH", 0x1b000000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DNS_QCH_00", 0x1b000000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DNS_QCH_01", 0x1b000000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_DNS_QCH", 0x1b000000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_DNS_QCH", 0x1b000000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH", 0x1b000000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH", 0x1b000000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH", 0x1b000000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH", 0x1b000000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH", 0x1b000000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH", 0x1b000000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH", 0x1b000000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH", 0x1b000000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH", 0x1b000000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH", 0x1b000000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH", 0x1b000000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH", 0x1b000000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH", 0x1b000000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH", 0x1b000000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_DNS_QCH", 0x1b000000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_DNS_QCH", 0x1b000000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_DNS_QCH", 0x1b000000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D0_DNS_QCH", 0x1b000000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_DNS_QCH", 0x1b000000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_DNS_QCH", 0x1b000000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_DNS_QCH", 0x1b000000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_DNS_QCH", 0x1b000000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DNS_QCH_S1", 0x1b000000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_DNS_QCH_S2", 0x1b000000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_DNS_QCH", 0x1b000000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2504, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DNS_CMU_DNS_CONTROLLER_OPTION", 0x1b000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1b020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1b020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DNS_CMU_DNS_QCH", 0x1b000000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DNS_QCH_00", 0x1b000000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DNS_QCH_01", 0x1b000000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_DNS_QCH", 0x1b000000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_DNS_QCH", 0x1b000000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_IPP_DNS_QCH", 0x1b000000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_ITP_DNS_QCH", 0x1b000000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_IPP_DNS_QCH", 0x1b000000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_DNS_ITP_QCH", 0x1b000000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF0_DNS_MCSC_QCH", 0x1b000000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_DNS_ITP_QCH", 0x1b000000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF1_DNS_MCSC_QCH", 0x1b000000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF2_DNS_MCSC_QCH", 0x1b000000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_DNS_GDC_QCH", 0x1b000000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_DNS_TNR_QCH", 0x1b000000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LD_IPP_DNS_QCH", 0x1b000000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LD_ITP_DNS_QCH", 0x1b000000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LD_MCSC_DNS_QCH", 0x1b000000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LD_PDP_DNS_QCH", 0x1b000000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_DNS_QCH", 0x1b000000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_DNS_QCH", 0x1b000000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_DNS_QCH", 0x1b000000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D0_DNS_QCH", 0x1b000000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_DNS_QCH", 0x1b000000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_DNS_QCH", 0x1b000000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_DNS_QCH", 0x1b000000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_DNS_QCH", 0x1b000000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DNS_QCH_S1", 0x1b000000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_DNS_QCH_S2", 0x1b000000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_DNS_QCH", 0x1b000000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dns_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "DNS_STATUS", 0x18060000, 0x2504, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq dns_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DNS_CMU_DNS_CONTROLLER_OPTION", 0x1b000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "DNS_CONFIGURATION", 0x18060000, 0x2500, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "DNS_STATUS", 0x18060000, 0x2504, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3aa_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3AA_CONFIGURATION", 0x18060000, 0x2580, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3AA_STATUS", 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3aa_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_G3AA_NOCP", 0x1a800000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_G3AA_G3AA_USER", 0x1a800000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_G3AA_QCH", 0x1a800000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_G3AA_CMU_G3AA_QCH", 0x1a800000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_G3AA_QCH", 0x1a800000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH", 0x1a800000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH", 0x1a800000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH", 0x1a800000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH", 0x1a800000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH", 0x1a800000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_G3AA_QCH", 0x1a800000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_G3AA_QCH", 0x1a800000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_G3AA_QCH", 0x1a800000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_G3AA_QCH", 0x1a800000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3AA_QCH_S1", 0x1a800000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_G3AA_QCH_S2", 0x1a800000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_G3AA_QCH", 0x1a800000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2584, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "G3AA_CMU_G3AA_CONTROLLER_OPTION", 0x1a800000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1a820000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1a820000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_G3AA_QCH", 0x1a800000, 0x7000, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_G3AA_QCH", 0x1a800000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_G3AA_CMU_G3AA_QCH", 0x1a800000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_G3AA_QCH", 0x1a800000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_PDP_G3AA_QCH", 0x1a800000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_PDP_G3AA_QCH", 0x1a800000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF2_PDP_G3AA_QCH", 0x1a800000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_YOTF0_PDP_G3AA_QCH", 0x1a800000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_YOTF1_PDP_G3AA_QCH", 0x1a800000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_G3AA_QCH", 0x1a800000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_G3AA_QCH", 0x1a800000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_G3AA_QCH", 0x1a800000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_G3AA_QCH", 0x1a800000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_G3AA_QCH_S1", 0x1a800000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_G3AA_QCH_S2", 0x1a800000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_G3AA_QCH", 0x1a800000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3aa_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "G3AA_STATUS", 0x18060000, 0x2584, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq g3aa_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3AA_CMU_G3AA_CONTROLLER_OPTION", 0x1a800000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3AA_CONFIGURATION", 0x18060000, 0x2580, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "G3AA_STATUS", 0x18060000, 0x2584, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq ipp_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "IPP_CONFIGURATION", 0x18060000, 0x2600, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "IPP_STATUS", 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq ipp_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_IPP_NOCP", 0x1ac00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_IPP_NOC_USER", 0x1ac00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_IPP_QCH", 0x1ac00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_IPP_QCH", 0x1ac00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_IPP_CMU_IPP_QCH", 0x1ac00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH", 0x1ac00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH", 0x1ac00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH", 0x1ac00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH", 0x1ac00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH", 0x1ac00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH", 0x1ac00000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH", 0x1ac00000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH", 0x1ac00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH", 0x1ac00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH", 0x1ac00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH", 0x1ac00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH", 0x1ac00000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_IPP_QCH", 0x1ac00000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH", 0x1ac00000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_IPP_QCH", 0x1ac00000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_MSA_QCH", 0x1ac00000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ALIGN0_QCH", 0x1ac00000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ALIGN1_QCH", 0x1ac00000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ALIGN2_QCH", 0x1ac00000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ALIGN3_QCH", 0x1ac00000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ALN_STAT_QCH", 0x1ac00000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_FDPIG_QCH", 0x1ac00000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_RGBH0_QCH", 0x1ac00000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_RGBH1_QCH", 0x1ac00000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_RGBH2_QCH", 0x1ac00000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_THSTAT_QCH", 0x1ac00000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_TNR_MSA0_QCH", 0x1ac00000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_TNR_MSA1_QCH", 0x1ac00000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SIPU_IPP_QCH", 0x1ac00000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_IPP_QCH", 0x1ac00000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ALIGN0_QCH", 0x1ac00000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ALIGN1_QCH", 0x1ac00000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ALIGN2_QCH", 0x1ac00000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ALIGN3_QCH", 0x1ac00000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ALN_STAT_QCH", 0x1ac00000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_FDPIG_QCH", 0x1ac00000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_RGBH0_QCH", 0x1ac00000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_RGBH1_QCH", 0x1ac00000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_RGBH2_QCH", 0x1ac00000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_THSTAT_QCH", 0x1ac00000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_TNR_MSA0_QCH", 0x1ac00000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_TNR_MSA1_QCH", 0x1ac00000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_IPP_QCH_S1", 0x1ac00000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_IPP_QCH_S2", 0x1ac00000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_IPP_QCH", 0x1ac00000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TNR_A_QCH", 0x1ac00000, 0x3104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2604, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "IPP_CMU_IPP_CONTROLLER_OPTION", 0x1ac00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1ac20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1ac20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_IPP_QCH", 0x1ac00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_IPP_QCH", 0x1ac00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_IPP_CMU_IPP_QCH", 0x1ac00000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_PDP_IPP_QCH", 0x1ac00000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_PDP_IPP_QCH", 0x1ac00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF2_PDP_IPP_QCH", 0x1ac00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_PDP_IPP_QCH", 0x1ac00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_IPP_DNS_QCH", 0x1ac00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_SOTF0_IPP_CSIS_QCH", 0x1ac00000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_SOTF1_IPP_CSIS_QCH", 0x1ac00000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_SOTF2_IPP_CSIS_QCH", 0x1ac00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_IPP_DNS_QCH", 0x1ac00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_ZOTF0_IPP_CSIS_QCH", 0x1ac00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_ZOTF1_IPP_CSIS_QCH", 0x1ac00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_ZOTF2_IPP_CSIS_QCH", 0x1ac00000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_IPP_QCH", 0x1ac00000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LD_IPP_DNS_QCH", 0x1ac00000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_IPP_QCH", 0x1ac00000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_MSA_QCH", 0x1ac00000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ALIGN0_QCH", 0x1ac00000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ALIGN1_QCH", 0x1ac00000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ALIGN2_QCH", 0x1ac00000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ALIGN3_QCH", 0x1ac00000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ALN_STAT_QCH", 0x1ac00000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_FDPIG_QCH", 0x1ac00000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_RGBH0_QCH", 0x1ac00000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_RGBH1_QCH", 0x1ac00000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_RGBH2_QCH", 0x1ac00000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_THSTAT_QCH", 0x1ac00000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_TNR_MSA0_QCH", 0x1ac00000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_TNR_MSA1_QCH", 0x1ac00000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SIPU_IPP_QCH", 0x1ac00000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_IPP_QCH", 0x1ac00000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ALIGN0_QCH", 0x1ac00000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ALIGN1_QCH", 0x1ac00000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ALIGN2_QCH", 0x1ac00000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ALIGN3_QCH", 0x1ac00000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ALN_STAT_QCH", 0x1ac00000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_FDPIG_QCH", 0x1ac00000, 0x70dc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_RGBH0_QCH", 0x1ac00000, 0x70e0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_RGBH1_QCH", 0x1ac00000, 0x70e4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_RGBH2_QCH", 0x1ac00000, 0x70e8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_THSTAT_QCH", 0x1ac00000, 0x70ec, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_TNR_MSA0_QCH", 0x1ac00000, 0x70f0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_TNR_MSA1_QCH", 0x1ac00000, 0x70f4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_IPP_QCH_S1", 0x1ac00000, 0x70f8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_IPP_QCH_S2", 0x1ac00000, 0x70fc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_IPP_QCH", 0x1ac00000, 0x7100, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TNR_A_QCH", 0x1ac00000, 0x7104, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq ipp_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "IPP_STATUS", 0x18060000, 0x2604, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq ipp_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "IPP_CMU_IPP_CONTROLLER_OPTION", 0x1ac00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "IPP_CONFIGURATION", 0x18060000, 0x2600, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "IPP_STATUS", 0x18060000, 0x2604, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq itp_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ITP_CONFIGURATION", 0x18060000, 0x2680, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "ITP_STATUS", 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq itp_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_ITP_NOCP", 0x1b400000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_ITP_NOC_USER", 0x1b400000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_ITP_QCH", 0x1b400000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_ITP_QCH", 0x1b400000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ITP_CMU_ITP_QCH", 0x1b400000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ITP_QCH", 0x1b400000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH", 0x1b400000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH", 0x1b400000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH", 0x1b400000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH", 0x1b400000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_ITP_QCH", 0x1b400000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_ITP_QCH", 0x1b400000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_ITP_QCH", 0x1b400000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_ITP_QCH", 0x1b400000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_ITP_QCH", 0x1b400000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2684, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "ITP_CMU_ITP_CONTROLLER_OPTION", 0x1b400000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1b420000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1b420000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_ITP_QCH", 0x1b400000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_ITP_QCH", 0x1b400000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ITP_CMU_ITP_QCH", 0x1b400000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ITP_QCH", 0x1b400000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_DNS_ITP_QCH", 0x1b400000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_DNS_ITP_QCH", 0x1b400000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_ITP_DNS_QCH", 0x1b400000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LD_ITP_DNS_QCH", 0x1b400000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_ITP_QCH", 0x1b400000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_ITP_QCH", 0x1b400000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_ITP_QCH", 0x1b400000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_ITP_QCH", 0x1b400000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_ITP_QCH", 0x1b400000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq itp_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "ITP_STATUS", 0x18060000, 0x2684, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq itp_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ITP_CMU_ITP_CONTROLLER_OPTION", 0x1b400000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "ITP_CONFIGURATION", 0x18060000, 0x2680, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "ITP_STATUS", 0x18060000, 0x2684, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mcsc_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MCSC_CONFIGURATION", 0x18060000, 0x2700, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MCSC_STATUS", 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mcsc_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_MCSC_NOCP", 0x1b700000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MCSC_ITSC_USER", 0x1b700000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MCSC_MCSC_USER", 0x1b700000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_C2R_MCSC_QCH", 0x1b700000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_MCSC_QCH", 0x1b700000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_MCSC_QCH", 0x1b700000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ITSC_QCH_C2", 0x1b700000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ITSC_QCH_CLK", 0x1b700000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH", 0x1b700000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH", 0x1b700000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH", 0x1b700000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH", 0x1b700000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH", 0x1b700000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH", 0x1b700000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH", 0x1b700000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH", 0x1b700000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH", 0x1b700000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_MCSC_QCH", 0x1b700000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_MCSC_QCH", 0x1b700000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D2_MCSC_QCH", 0x1b700000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH", 0x1b700000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MCSC_CMU_MCSC_QCH", 0x1b700000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MCSC_QCH_C2CLK", 0x1b700000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MCSC_QCH_CLK", 0x1b700000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_ITSC_QCH", 0x1b700000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_MCSC_QCH", 0x1b700000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_ITSC_QCH", 0x1b700000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_MCSC_QCH", 0x1b700000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D0_MCSC_QCH", 0x1b700000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_ITSC_QCH", 0x1b700000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_MCSC_QCH", 0x1b700000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D2_ITSC_QCH", 0x1b700000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D2_MCSC_QCH", 0x1b700000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D3_ITSC_QCH", 0x1b700000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D3_MCSC_QCH", 0x1b700000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D4_MCSC_QCH", 0x1b700000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D5_MCSC_QCH", 0x1b700000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_MCSC_QCH", 0x1b700000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_ITSC_QCH", 0x1b700000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_MCSC_QCH", 0x1b700000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_ITSC_QCH", 0x1b700000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_MCSC_QCH", 0x1b700000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_MCSC_QCH_S1", 0x1b700000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_MCSC_QCH_S2", 0x1b700000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_MCSC_QCH_S1", 0x1b700000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_MCSC_QCH_S2", 0x1b700000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_MCSC_QCH_S1", 0x1b700000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_MCSC_QCH_S2", 0x1b700000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_MCSC_QCH", 0x1b700000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2704, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MCSC_CMU_MCSC_CONTROLLER_OPTION", 0x1b700000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1b720000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1b720000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_C2R_MCSC_QCH", 0x1b700000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_MCSC_QCH", 0x1b700000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_MCSC_QCH", 0x1b700000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ITSC_QCH_C2", 0x1b700000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ITSC_QCH_CLK", 0x1b700000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_I_ITSC_MCSC_QCH", 0x1b700000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF0_DNS_MCSC_QCH", 0x1b700000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF1_DNS_MCSC_QCH", 0x1b700000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF2_DNS_MCSC_QCH", 0x1b700000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_TNR_MCSC_QCH", 0x1b700000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_GDC_MCSC_QCH", 0x1b700000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_I_ITSC_MCSC_QCH", 0x1b700000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_MCSC_TNR_QCH", 0x1b700000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_MCSC_CSIS_QCH", 0x1b700000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_MCSC_QCH", 0x1b700000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_MCSC_QCH", 0x1b700000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D2_MCSC_QCH", 0x1b700000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LD_MCSC_DNS_QCH", 0x1b700000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MCSC_CMU_MCSC_QCH", 0x1b700000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MCSC_QCH_C2CLK", 0x1b700000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MCSC_QCH_CLK", 0x1b700000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_ITSC_QCH", 0x1b700000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_MCSC_QCH", 0x1b700000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_ITSC_QCH", 0x1b700000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_MCSC_QCH", 0x1b700000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D0_MCSC_QCH", 0x1b700000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_ITSC_QCH", 0x1b700000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_MCSC_QCH", 0x1b700000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D2_ITSC_QCH", 0x1b700000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D2_MCSC_QCH", 0x1b700000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D3_ITSC_QCH", 0x1b700000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D3_MCSC_QCH", 0x1b700000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D4_MCSC_QCH", 0x1b700000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D5_MCSC_QCH", 0x1b700000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_MCSC_QCH", 0x1b700000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_ITSC_QCH", 0x1b700000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_MCSC_QCH", 0x1b700000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_ITSC_QCH", 0x1b700000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_MCSC_QCH", 0x1b700000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_MCSC_QCH_S1", 0x1b700000, 0x70dc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_MCSC_QCH_S2", 0x1b700000, 0x70e0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_MCSC_QCH_S1", 0x1b700000, 0x70e4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_MCSC_QCH_S2", 0x1b700000, 0x70e8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_MCSC_QCH_S1", 0x1b700000, 0x70ec, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_MCSC_QCH_S2", 0x1b700000, 0x70f0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_MCSC_QCH", 0x1b700000, 0x70f4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mcsc_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "MCSC_STATUS", 0x18060000, 0x2704, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq mcsc_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MCSC_CMU_MCSC_CONTROLLER_OPTION", 0x1b700000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MCSC_CONFIGURATION", 0x18060000, 0x2700, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "MCSC_STATUS", 0x18060000, 0x2704, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq gdc_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GDC_CONFIGURATION", 0x18060000, 0x2780, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "GDC_STATUS", 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq gdc_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_GDC_NOCP", 0x1d000000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_GDC_GDC0_USER", 0x1d000000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_GDC_GDC1_USER", 0x1d000000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_GDC_SCSC_USER", 0x1d000000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_GDC_QCH", 0x1d000000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GDC0_QCH_C2CLK", 0x1d000000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GDC0_QCH_CLK", 0x1d000000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GDC1_QCH_C2CLK", 0x1d000000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GDC1_QCH_CLK", 0x1d000000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GDC_CMU_GDC_QCH", 0x1d000000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_GDC_QCH", 0x1d000000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH", 0x1d000000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH", 0x1d000000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH", 0x1d000000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH", 0x1d000000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH", 0x1d000000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH", 0x1d000000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH", 0x1d000000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH", 0x1d000000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH", 0x1d000000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_GDC_QCH", 0x1d000000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_GDC_QCH", 0x1d000000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D2_GDC_QCH", 0x1d000000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH", 0x1d000000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_GDC_QCH", 0x1d000000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_SCSC_QCH", 0x1d000000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_GDC_QCH", 0x1d000000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_SCSC_QCH", 0x1d000000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D2_GDC_QCH", 0x1d000000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D2_SCSC_QCH", 0x1d000000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D3_GDC_QCH", 0x1d000000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D0_GDC_QCH", 0x1d000000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D0_SCSC_QCH", 0x1d000000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_GDC_QCH", 0x1d000000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_SCSC_QCH", 0x1d000000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D2_GDC_QCH", 0x1d000000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D2_SCSC_QCH", 0x1d000000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D3_GDC_QCH", 0x1d000000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SCSC_QCH_C2CLK", 0x1d000000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SCSC_QCH_CLK", 0x1d000000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_GDC_QCH", 0x1d000000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_GDC_QCH", 0x1d000000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_SCSC_QCH", 0x1d000000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_GDC_QCH", 0x1d000000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_SCSC_QCH", 0x1d000000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D2_GDC_QCH", 0x1d000000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D2_SCSC_QCH", 0x1d000000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D3_GDC_QCH", 0x1d000000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_GDC_QCH_S1", 0x1d000000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_GDC_QCH_S2", 0x1d000000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_GDC_QCH_S1", 0x1d000000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_GDC_QCH_S2", 0x1d000000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_GDC_QCH_S1", 0x1d000000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_GDC_QCH_S2", 0x1d000000, 0x3104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_GDC_QCH", 0x1d000000, 0x3108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2784, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "GDC_CMU_GDC_CONTROLLER_OPTION", 0x1d000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1d020000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1d020000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_GDC_QCH", 0x1d000000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GDC0_QCH_C2CLK", 0x1d000000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GDC0_QCH_CLK", 0x1d000000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GDC1_QCH_C2CLK", 0x1d000000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GDC1_QCH_CLK", 0x1d000000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GDC_CMU_GDC_QCH", 0x1d000000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_GDC_QCH", 0x1d000000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_I_GDC0_GDC1_QCH", 0x1d000000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_I_GDC1_SCSC_QCH", 0x1d000000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_DNS_GDC_QCH", 0x1d000000, 0x7060, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_TNR_GDC_QCH", 0x1d000000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_TNR_GDC_QCH", 0x1d000000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_I_GDC0_GDC1_QCH", 0x1d000000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_I_GDC1_SCSC_QCH", 0x1d000000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_GDC_MCSC_QCH", 0x1d000000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_ID_SCSC_GDC1_QCH", 0x1d000000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_GDC_QCH", 0x1d000000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_GDC_QCH", 0x1d000000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D2_GDC_QCH", 0x1d000000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_ID_SCSC_GDC1_QCH", 0x1d000000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_GDC_QCH", 0x1d000000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_SCSC_QCH", 0x1d000000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_GDC_QCH", 0x1d000000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_SCSC_QCH", 0x1d000000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D2_GDC_QCH", 0x1d000000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D2_SCSC_QCH", 0x1d000000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D3_GDC_QCH", 0x1d000000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D0_GDC_QCH", 0x1d000000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D0_SCSC_QCH", 0x1d000000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_GDC_QCH", 0x1d000000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_SCSC_QCH", 0x1d000000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D2_GDC_QCH", 0x1d000000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D2_SCSC_QCH", 0x1d000000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D3_GDC_QCH", 0x1d000000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SCSC_QCH_C2CLK", 0x1d000000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SCSC_QCH_CLK", 0x1d000000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_GDC_QCH", 0x1d000000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_GDC_QCH", 0x1d000000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_SCSC_QCH", 0x1d000000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_GDC_QCH", 0x1d000000, 0x70dc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_SCSC_QCH", 0x1d000000, 0x70e0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D2_GDC_QCH", 0x1d000000, 0x70e4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D2_SCSC_QCH", 0x1d000000, 0x70e8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D3_GDC_QCH", 0x1d000000, 0x70ec, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_GDC_QCH_S1", 0x1d000000, 0x70f0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_GDC_QCH_S2", 0x1d000000, 0x70f4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_GDC_QCH_S1", 0x1d000000, 0x70f8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_GDC_QCH_S2", 0x1d000000, 0x70fc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_GDC_QCH_S1", 0x1d000000, 0x7100, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_GDC_QCH_S2", 0x1d000000, 0x7104, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_GDC_QCH", 0x1d000000, 0x7108, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq gdc_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "GDC_STATUS", 0x18060000, 0x2784, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq gdc_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GDC_CMU_GDC_CONTROLLER_OPTION", 0x1d000000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GDC_CONFIGURATION", 0x18060000, 0x2780, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "GDC_STATUS", 0x18060000, 0x2784, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tnr_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TNR_CONFIGURATION", 0x18060000, 0x2800, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "TNR_STATUS", 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tnr_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TNR_NOCP", 0x1bc00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_TNR_NOC_USER", 0x1bc00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_TNR_QCH", 0x1bc00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_TNR_QCH", 0x1bc00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH", 0x1bc00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH", 0x1bc00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH", 0x1bc00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH", 0x1bc00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH", 0x1bc00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_TNR_QCH", 0x1bc00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_TNR_QCH", 0x1bc00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D2_TNR_QCH", 0x1bc00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D3_TNR_QCH", 0x1bc00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D4_TNR_QCH", 0x1bc00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_TNR_QCH", 0x1bc00000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_TNR_QCH", 0x1bc00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D2_TNR_QCH", 0x1bc00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D3_TNR_QCH", 0x1bc00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D4_TNR_QCH", 0x1bc00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D5_TNR_QCH", 0x1bc00000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D6_TNR_QCH", 0x1bc00000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D7_TNR_QCH", 0x1bc00000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D8_TNR_QCH", 0x1bc00000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D0_TNR_QCH", 0x1bc00000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D1_TNR_QCH", 0x1bc00000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D5_TNR_QCH", 0x1bc00000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D6_TNR_QCH", 0x1bc00000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D7_TNR_QCH", 0x1bc00000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_D8_TNR_QCH", 0x1bc00000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_TNR_QCH", 0x1bc00000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_TNR_QCH", 0x1bc00000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_TNR_QCH", 0x1bc00000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D2_TNR_QCH", 0x1bc00000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D3_TNR_QCH", 0x1bc00000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D4_TNR_QCH", 0x1bc00000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D5_TNR_QCH", 0x1bc00000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D6_TNR_QCH", 0x1bc00000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D7_TNR_QCH", 0x1bc00000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D8_TNR_QCH", 0x1bc00000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_TNR_QCH_S1", 0x1bc00000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_TNR_QCH_S2", 0x1bc00000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_TNR_QCH_S1", 0x1bc00000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_TNR_QCH_S2", 0x1bc00000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_TNR_QCH_S1", 0x1bc00000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D2_TNR_QCH_S2", 0x1bc00000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D3_TNR_QCH_S1", 0x1bc00000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D3_TNR_QCH_S2", 0x1bc00000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D4_TNR_QCH_S1", 0x1bc00000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D4_TNR_QCH_S2", 0x1bc00000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_TNR_QCH", 0x1bc00000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TNR_CMU_TNR_QCH", 0x1bc00000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TNR_QCH_ACLK", 0x1bc00000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TNR_QCH_C2", 0x1bc00000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2804, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "TNR_CMU_TNR_CONTROLLER_OPTION", 0x1bc00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN0", 0x1bc20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN1", 0x1bc20000, 0x010c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1bc20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_TNR_QCH", 0x1bc00000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_TNR_QCH", 0x1bc00000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_OTF_MCSC_TNR_QCH", 0x1bc00000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_VO_DNS_TNR_QCH", 0x1bc00000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_TNR_GDC_QCH", 0x1bc00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_OTF_TNR_MCSC_QCH", 0x1bc00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_VO_TNR_GDC_QCH", 0x1bc00000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_TNR_QCH", 0x1bc00000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_TNR_QCH", 0x1bc00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D2_TNR_QCH", 0x1bc00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D3_TNR_QCH", 0x1bc00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D4_TNR_QCH", 0x1bc00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_TNR_QCH", 0x1bc00000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_TNR_QCH", 0x1bc00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D2_TNR_QCH", 0x1bc00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D3_TNR_QCH", 0x1bc00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D4_TNR_QCH", 0x1bc00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D5_TNR_QCH", 0x1bc00000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D6_TNR_QCH", 0x1bc00000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D7_TNR_QCH", 0x1bc00000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D8_TNR_QCH", 0x1bc00000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D0_TNR_QCH", 0x1bc00000, 0x7088, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D1_TNR_QCH", 0x1bc00000, 0x708c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D5_TNR_QCH", 0x1bc00000, 0x7090, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D6_TNR_QCH", 0x1bc00000, 0x7094, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D7_TNR_QCH", 0x1bc00000, 0x7098, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_D8_TNR_QCH", 0x1bc00000, 0x709c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_TNR_QCH", 0x1bc00000, 0x70a0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_TNR_QCH", 0x1bc00000, 0x70a4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_TNR_QCH", 0x1bc00000, 0x70a8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D2_TNR_QCH", 0x1bc00000, 0x70ac, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D3_TNR_QCH", 0x1bc00000, 0x70b0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D4_TNR_QCH", 0x1bc00000, 0x70b4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D5_TNR_QCH", 0x1bc00000, 0x70b8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D6_TNR_QCH", 0x1bc00000, 0x70bc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D7_TNR_QCH", 0x1bc00000, 0x70c0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D8_TNR_QCH", 0x1bc00000, 0x70c4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_TNR_QCH_S1", 0x1bc00000, 0x70c8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_TNR_QCH_S2", 0x1bc00000, 0x70cc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_TNR_QCH_S1", 0x1bc00000, 0x70d0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_TNR_QCH_S2", 0x1bc00000, 0x70d4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_TNR_QCH_S1", 0x1bc00000, 0x70d8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D2_TNR_QCH_S2", 0x1bc00000, 0x70dc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D3_TNR_QCH_S1", 0x1bc00000, 0x70e0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D3_TNR_QCH_S2", 0x1bc00000, 0x70e4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D4_TNR_QCH_S1", 0x1bc00000, 0x70e8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D4_TNR_QCH_S2", 0x1bc00000, 0x70ec, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_TNR_QCH", 0x1bc00000, 0x70f0, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TNR_CMU_TNR_QCH", 0x1bc00000, 0x70f4, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TNR_QCH_ACLK", 0x1bc00000, 0x70f8, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TNR_QCH_C2", 0x1bc00000, 0x70fc, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tnr_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "TNR_STATUS", 0x18060000, 0x2804, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tnr_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TNR_CMU_TNR_CONTROLLER_OPTION", 0x1bc00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TNR_CONFIGURATION", 0x18060000, 0x2800, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "TNR_STATUS", 0x18060000, 0x2804, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq bo_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BO_CONFIGURATION", 0x18060000, 0x2880, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "BO_STATUS", 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq bo_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_BO_NOCP", 0x1ca00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_BO_NOC_USER", 0x1ca00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_BO_CMU_BO_QCH", 0x1ca00000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_BO_QCH", 0x1ca00000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_BO_QCH", 0x1ca00000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_IP_BO_QCH", 0x1ca00000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_BO_QCH", 0x1ca00000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_IP_BO_QCH", 0x1ca00000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_BO_QCH", 0x1ca00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_BO_QCH", 0x1ca00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_BO_QCH", 0x1ca00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_BO_QCH_S1", 0x1ca00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_BO_QCH_S2", 0x1ca00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_BO_QCH", 0x1ca00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_BO_QCH", 0x1ca00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2884, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BO_CMU_BO_CONTROLLER_OPTION", 0x1ca00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1ca20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1ca20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_BO_QCH", 0x1ca00000, 0x7000, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_BO_CMU_BO_QCH", 0x1ca00000, 0x7014, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_BO_QCH", 0x1ca00000, 0x7018, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_BO_QCH", 0x1ca00000, 0x701c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_IP_BO_QCH", 0x1ca00000, 0x7020, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_BO_QCH", 0x1ca00000, 0x7024, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_IP_BO_QCH", 0x1ca00000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_BO_QCH", 0x1ca00000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_BO_QCH", 0x1ca00000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_BO_QCH", 0x1ca00000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_BO_QCH_S1", 0x1ca00000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_BO_QCH_S2", 0x1ca00000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_BO_QCH", 0x1ca00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_BO_QCH", 0x1ca00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq bo_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "BO_STATUS", 0x18060000, 0x2884, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq bo_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BO_CMU_BO_CONTROLLER_OPTION", 0x1ca00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BO_CONFIGURATION", 0x18060000, 0x2880, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "BO_STATUS", 0x18060000, 0x2884, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tpu_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TPU_CONFIGURATION", 0x18060000, 0x2900, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "TPU_STATUS", 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tpu_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_LOCKTIME_PLL_TPU", 0x1cc00000, 0x0000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON2_PLL_TPU", 0x1cc00000, 0x0108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON4_PLL_TPU", 0x1cc00000, 0x0110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TPU_NOCP", 0x1cc00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TPU_NOCP_LH", 0x1cc00000, 0x1804, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TPU_TPU", 0x1cc00000, 0x1808, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TPU_TPUCTL", 0x1cc00000, 0x180c, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_TPU_TPUCTL_DBG", 0x1cc00000, 0x1810, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_TPU_TPU", 0x1cc00000, 0x1000, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_TPU_TPUCTL", 0x1cc00000, 0x1004, 0xffffffff, 0, 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_TPU_NOC_USER", 0x1cc00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_TPU_TPUCTL_USER", 0x1cc00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_TPU_TPU_USER", 0x1cc00000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_TPU_UART_USER", 0x1cc00000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON3_PLL_TPU", 0x1cc00000, 0x010c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CHECK_SKIP, "PLL_CON3_PLL_TPU", 0x1cc00000, 0x010c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "PLL_CON3_PLL_TPU", 0x1cc00000, 0x010c, (0x1 << 29), (0x1 << 29), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_PLL_TPU", 0x1cc00000, 0x0100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON1_PLL_TPU", 0x1cc00000, 0x0104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_BUSIF_HPMTPU_QCH", 0x1cc00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_TPU_QCH", 0x1cc00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_TPU_QCH", 0x1cc00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_TPU_QCH", 0x1cc00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH", 0x1cc00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH", 0x1cc00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_TPU_CU_QCH", 0x1cc00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_TPU_CU_QCH", 0x1cc00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_TPU_QCH", 0x1cc00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_TPU_QCH", 0x1cc00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_TPU_QCH", 0x1cc00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_TPU_QCH_S1", 0x1cc00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_TPU_QCH_S2", 0x1cc00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_TPU_QCH", 0x1cc00000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TPU_CMU_TPU_QCH", 0x1cc00000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "TPU_CMU_TPU_CONTROLLER_OPTION", 0x1cc00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x1cc20000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x1cc20000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_TPU_QCH", 0x1cc00000, 0x7000, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_BUSIF_HPMTPU_QCH", 0x1cc00000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_TPU_QCH", 0x1cc00000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_TPU_QCH", 0x1cc00000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_TPU_QCH", 0x1cc00000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_MI_LT0_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_MI_LT1_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT0_TPU_CPUCL0_QCH", 0x1cc00000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_CD_QCH", 0x1cc00000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT1_TPU_CPUCL0_QCH", 0x1cc00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_TPU_CU_QCH", 0x1cc00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_TPU_CU_QCH", 0x1cc00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_TPU_QCH", 0x1cc00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_TPU_QCH", 0x1cc00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_TPU_QCH", 0x1cc00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_TPU_QCH_S1", 0x1cc00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_TPU_QCH_S2", 0x1cc00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_TPU_QCH", 0x1cc00000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TPU_CMU_TPU_QCH", 0x1cc00000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tpu_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "TPU_STATUS", 0x18060000, 0x2904, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq tpu_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TPU_CMU_TPU_CONTROLLER_OPTION", 0x1cc00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TPU_CONFIGURATION", 0x18060000, 0x2900, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "TPU_STATUS", 0x18060000, 0x2904, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aur_on[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AUR_CONFIGURATION", 0x18060000, 0x2980, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "AUR_STATUS", 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aur_save[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_LOCKTIME_PLL_AUR", 0x25a00000, 0x0000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON2_PLL_AUR", 0x25a00000, 0x0108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON4_PLL_AUR", 0x25a00000, 0x0110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLK_AUR_ADD_CH_CLK", 0x25a00000, 0x1800, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_AUR_AUR", 0x25a00000, 0x1804, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_AUR_AURCTL_LH", 0x25a00000, 0x1808, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_AUR_NOCP", 0x25a00000, 0x180c, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_AUR_NOCP_LH", 0x25a00000, 0x1810, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLK_AUR_AUR", 0x25a00000, 0x1000, 0xffffffff, 0, 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_AUR_AURCTL_USER", 0x25a00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_AUR_NOC_USER", 0x25a00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_AUR_SWITCH_USER", 0x25a00000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON3_PLL_AUR", 0x25a00000, 0x010c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CHECK_SKIP, "PLL_CON3_PLL_AUR", 0x25a00000, 0x010c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "PLL_CON3_PLL_AUR", 0x25a00000, 0x010c, (0x1 << 29), (0x1 << 29), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_PLL_AUR", 0x25a00000, 0x0100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON1_PLL_AUR", 0x25a00000, 0x0104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ADD_APBIF_AUR_QCH", 0x25a00000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_AUR_CMU_AUR_QCH", 0x25a00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_BAAW_AUR_QCH", 0x25a00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_AUR_QCH", 0x25a00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_AUR_QCH", 0x25a00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH", 0x25a00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH", 0x25a00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH", 0x25a00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_AUR_CU_QCH", 0x25a00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D0_AUR_QCH", 0x25a00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D1_AUR_QCH", 0x25a00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_AUR_CU_QCH", 0x25a00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D0_AUR_QCH", 0x25a00000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_D1_AUR_QCH", 0x25a00000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_AUR_QCH", 0x25a00000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D0_AUR_QCH", 0x25a00000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D1_AUR_QCH", 0x25a00000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1", 0x25a00000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2", 0x25a00000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1", 0x25a00000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2", 0x25a00000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_AUR_QCH", 0x25a00000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_AUR_QCH", 0x25a00000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "AUR_CMU_AUR_CONTROLLER_OPTION", 0x25a00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "BUS_COMPONENT_DRCG_EN", 0x25a40000, 0x0104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MEMCLK", 0x25a40000, 0x0108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_ADD_AUR_QCH", 0x25a00000, 0x7000, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_AUR_QCH", 0x25a00000, 0x7004, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ADD_APBIF_AUR_QCH", 0x25a00000, 0x7028, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_AUR_CMU_AUR_QCH", 0x25a00000, 0x702c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_BAAW_AUR_QCH", 0x25a00000, 0x7030, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_AUR_QCH", 0x25a00000, 0x7034, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_AUR_QCH", 0x25a00000, 0x7038, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_MI_LT_AUR_CPUCL0_CD_QCH", 0x25a00000, 0x703c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_CD_QCH", 0x25a00000, 0x7040, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ATB_SI_LT_AUR_CPUCL0_QCH", 0x25a00000, 0x7044, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_AUR_CU_QCH", 0x25a00000, 0x7048, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D0_AUR_QCH", 0x25a00000, 0x704c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D1_AUR_QCH", 0x25a00000, 0x7050, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_AUR_CU_QCH", 0x25a00000, 0x7054, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D0_AUR_QCH", 0x25a00000, 0x7058, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_D1_AUR_QCH", 0x25a00000, 0x705c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_AUR_QCH", 0x25a00000, 0x7064, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D0_AUR_QCH", 0x25a00000, 0x7068, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D1_AUR_QCH", 0x25a00000, 0x706c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_AUR_WP_QCH_S1", 0x25a00000, 0x7070, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D0_AUR_WP_QCH_S2", 0x25a00000, 0x7074, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_AUR_WP_QCH_S1", 0x25a00000, 0x7078, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D1_AUR_WP_QCH_S2", 0x25a00000, 0x707c, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_AUR_QCH", 0x25a00000, 0x7080, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_AUR_QCH", 0x25a00000, 0x7084, (0xffffffff << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aur_status[] = { + PMUCAL_SEQ_DESC(PMUCAL_READ, "AUR_STATUS", 0x18060000, 0x2984, (0x1 << 0), 0, 0, 0, 0xffffffff, 0), +}; + +struct pmucal_seq aur_off[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AUR_CMU_AUR_CONTROLLER_OPTION", 0x25a00000, 0x0800, (0x1 << 24), (0x0 << 24), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AUR_CONFIGURATION", 0x18060000, 0x2980, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WAIT, "AUR_STATUS", 0x18060000, 0x2984, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), +}; + + +enum pmucal_local_pdnum { + PD_AOC, + PD_NOCL1B, + PD_NOCL2A, + PD_NOCL1A, + PD_NOCL0, + PD_EH, + PD_EMBEDDED_G3D, + PD_G3D, + PD_HSI0, + PD_HSI2, + PD_DPU, + PD_DISP, + PD_G2D, + PD_MFC, + PD_CSIS, + PD_PDP, + PD_DNS, + PD_G3AA, + PD_IPP, + PD_ITP, + PD_MCSC, + PD_GDC, + PD_TNR, + PD_BO, + PD_TPU, + PD_AUR, + PD_MAX, +}; + +struct pmucal_pd pmucal_pd_list[PMUCAL_NUM_PDS] = { + PMUCAL_PD_DESC(PD_AOC, "blkpwr_aoc", aoc_on, aoc_save, aoc_off, aoc_status), + PMUCAL_PD_DESC(PD_NOCL1B, "blkpwr_nocl1b", nocl1b_on, nocl1b_save, nocl1b_off, nocl1b_status), + PMUCAL_PD_DESC(PD_NOCL2A, "blkpwr_nocl2a", nocl2a_on, nocl2a_save, nocl2a_off, nocl2a_status), + PMUCAL_PD_DESC(PD_NOCL1A, "blkpwr_nocl1a", nocl1a_on, nocl1a_save, nocl1a_off, nocl1a_status), + PMUCAL_PD_DESC(PD_NOCL0, "blkpwr_nocl0", nocl0_on, nocl0_save, nocl0_off, nocl0_status), + PMUCAL_PD_DESC(PD_EH, "blkpwr_eh", eh_on, eh_save, eh_off, eh_status), + PMUCAL_PD_DESC(PD_EMBEDDED_G3D, "blkpwr_embedded_g3d", embedded_g3d_on, embedded_g3d_save, embedded_g3d_off, embedded_g3d_status), + PMUCAL_PD_DESC(PD_G3D, "blkpwr_g3d", g3d_on, g3d_save, g3d_off, g3d_status), + PMUCAL_PD_DESC(PD_HSI0, "blkpwr_hsi0", hsi0_on, hsi0_save, hsi0_off, hsi0_status), + PMUCAL_PD_DESC(PD_HSI2, "blkpwr_hsi2", hsi2_on, hsi2_save, hsi2_off, hsi2_status), + PMUCAL_PD_DESC(PD_DPU, "blkpwr_dpu", dpu_on, dpu_save, dpu_off, dpu_status), + PMUCAL_PD_DESC(PD_DISP, "blkpwr_disp", disp_on, disp_save, disp_off, disp_status), + PMUCAL_PD_DESC(PD_G2D, "blkpwr_g2d", g2d_on, g2d_save, g2d_off, g2d_status), + PMUCAL_PD_DESC(PD_MFC, "blkpwr_mfc", mfc_on, mfc_save, mfc_off, mfc_status), + PMUCAL_PD_DESC(PD_CSIS, "blkpwr_csis", csis_on, csis_save, csis_off, csis_status), + PMUCAL_PD_DESC(PD_PDP, "blkpwr_pdp", pdp_on, pdp_save, pdp_off, pdp_status), + PMUCAL_PD_DESC(PD_DNS, "blkpwr_dns", dns_on, dns_save, dns_off, dns_status), + PMUCAL_PD_DESC(PD_G3AA, "blkpwr_g3aa", g3aa_on, g3aa_save, g3aa_off, g3aa_status), + PMUCAL_PD_DESC(PD_IPP, "blkpwr_ipp", ipp_on, ipp_save, ipp_off, ipp_status), + PMUCAL_PD_DESC(PD_ITP, "blkpwr_itp", itp_on, itp_save, itp_off, itp_status), + PMUCAL_PD_DESC(PD_MCSC, "blkpwr_mcsc", mcsc_on, mcsc_save, mcsc_off, mcsc_status), + PMUCAL_PD_DESC(PD_GDC, "blkpwr_gdc", gdc_on, gdc_save, gdc_off, gdc_status), + PMUCAL_PD_DESC(PD_TNR, "blkpwr_tnr", tnr_on, tnr_save, tnr_off, tnr_status), + PMUCAL_PD_DESC(PD_BO, "blkpwr_bo", bo_on, bo_save, bo_off, bo_status), + PMUCAL_PD_DESC(PD_TPU, "blkpwr_tpu", tpu_on, tpu_save, tpu_off, tpu_status), + PMUCAL_PD_DESC(PD_AUR, "blkpwr_aur", aur_on, aur_save, aur_off, aur_status), +}; +unsigned int pmucal_pd_list_size = ARRAY_SIZE(pmucal_pd_list); +#else + + +enum pmucal_local_pdnum { + PD_MAX, +}; + +struct pmucal_pd pmucal_pd_list[PMUCAL_NUM_PDS] = { +}; +unsigned int pmucal_pd_list_size = ARRAY_SIZE(pmucal_pd_list); +#endif diff --git a/drivers/soc/google/cal-if/gs201/flexpmu_cal_p2vmap_gs201.h b/drivers/soc/google/cal-if/gs201/flexpmu_cal_p2vmap_gs201.h new file mode 100644 index 000000000000..35df2080a9c3 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/flexpmu_cal_p2vmap_gs201.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +struct p2v_map pmucal_p2v_list[] = { + DEFINE_PHY(0x1C800000), + DEFINE_PHY(0x1CA20000), + DEFINE_PHY(0x20020000), + DEFINE_PHY(0x11820000), + DEFINE_PHY(0x1E000000), + DEFINE_PHY(0x18020000), + DEFINE_PHY(0x11020000), + DEFINE_PHY(0x27F20000), + DEFINE_PHY(0x11800000), + DEFINE_PHY(0x1D000000), + DEFINE_PHY(0x10820000), + DEFINE_PHY(0x20920000), + DEFINE_PHY(0x1A020000), + DEFINE_PHY(0x1C600000), + DEFINE_PHY(0x1A400000), + DEFINE_PHY(0x1CC00000), + DEFINE_PHY(0x20000000), + DEFINE_PHY(0x20B40000), + DEFINE_PHY(0x1E020000), + DEFINE_PHY(0x1B000000), + DEFINE_PHY(0x14400000), + DEFINE_PHY(0x1BC00000), + DEFINE_PHY(0x17020000), + DEFINE_PHY(0x14700000), + DEFINE_PHY(0x1E080000), + DEFINE_PHY(0x1AA20000), + DEFINE_PHY(0x1CC20000), + DEFINE_PHY(0x20B20000), + DEFINE_PHY(0x10800000), + DEFINE_PHY(0x1E820000), + DEFINE_PHY(0x1B020000), + DEFINE_PHY(0x10030000), + DEFINE_PHY(0x20A00000), + DEFINE_PHY(0x1A420000), + DEFINE_PHY(0x20820000), + DEFINE_PHY(0x20800000), + DEFINE_PHY(0x20C00000), + DEFINE_PHY(0x17000000), + DEFINE_PHY(0x10010000), + DEFINE_PHY(0x20900000), + DEFINE_PHY(0x25A40000), + DEFINE_PHY(0x27F00000), + DEFINE_PHY(0x1C020000), + DEFINE_PHY(0x20C10000), + DEFINE_PHY(0x1C200000), + DEFINE_PHY(0x1C620000), + DEFINE_PHY(0x1CA00000), + DEFINE_PHY(0x10C00000), + DEFINE_PHY(0x1B720000), + DEFINE_PHY(0x10C20000), + DEFINE_PHY(0x11000000), + DEFINE_PHY(0x1F020000), + DEFINE_PHY(0x20840000), + DEFINE_PHY(0x1C820000), + DEFINE_PHY(0x18060000), + DEFINE_PHY(0x1AC20000), + DEFINE_PHY(0x1B400000), + DEFINE_PHY(0x1F000000), + DEFINE_PHY(0x1AC00000), + DEFINE_PHY(0x20A40000), + DEFINE_PHY(0x1C220000), + DEFINE_PHY(0x1BC20000), + DEFINE_PHY(0x1C0B0000), + DEFINE_PHY(0x1D020000), + DEFINE_PHY(0x1A820000), + DEFINE_PHY(0x14420000), + DEFINE_PHY(0x18070000), + DEFINE_PHY(0x18000000), + DEFINE_PHY(0x1C000000), + DEFINE_PHY(0x25A00000), + DEFINE_PHY(0x20A20000), + DEFINE_PHY(0x20B00000), + DEFINE_PHY(0x20940000), + DEFINE_PHY(0x1A800000), + DEFINE_PHY(0x1AA00000), + DEFINE_PHY(0x1B420000), + DEFINE_PHY(0x20C40000), + DEFINE_PHY(0x20C20000), + DEFINE_PHY(0x1E800000), + DEFINE_PHY(0x1B700000), + DEFINE_PHY(0x1A000000), + DEFINE_PHY(0x20510000), +}; +unsigned int pmucal_p2v_list_size = ARRAY_SIZE(pmucal_p2v_list); diff --git a/drivers/soc/google/cal-if/gs201/flexpmu_cal_system_gs201.h b/drivers/soc/google/cal-if/gs201/flexpmu_cal_system_gs201.h new file mode 100644 index 000000000000..2f76476c36f2 --- /dev/null +++ b/drivers/soc/google/cal-if/gs201/flexpmu_cal_system_gs201.h @@ -0,0 +1,1666 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef ACPM_FRAMEWORK +/* common sequence descriptor for lpm init. - exposed to common logic */ +struct pmucal_seq pmucal_lpm_init[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, (0x7f << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, (0x7f << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, (0x7f << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MASK_IRQ0", 0x18020000, 0x0420, (0xf << 28), (0xf << 28), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CLKDIVSTEP_SMPL_FLT", 0x20c00000, 0x0834, (0xffffffff << 0), (0x8000ffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CLKDIVSTEP_CON", 0x20c00000, 0x0838, (0xffffffff << 0), (0xf041c3 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_CLKDIVSTEP", 0x20c00000, 0x0830, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_CLKDIVSTEP_SMPL_FLT", 0x20c10000, 0x083c, (0xffffffff << 0), (0x8000ffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_CLKDIVSTEP_CON_HEAVY", 0x20c10000, 0x0840, (0xffffffff << 0), (0xfff041c1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_CLKDIVSTEP_CON_LIGHT", 0x20c10000, 0x0844, (0xffffffff << 0), (0xf041c3 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_CLKDIVSTEP", 0x20c10000, 0x0830, (0xffffffff << 0), (0x3 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_CLKDIVSTEP_SMPL_FLT", 0x20c20000, 0x083c, (0xffffffff << 0), (0x8000ffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_CLKDIVSTEP_CON_HEAVY", 0x20c20000, 0x0840, (0xffffffff << 0), (0xfff041c1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_CLKDIVSTEP_CON_LIGHT", 0x20c20000, 0x0844, (0xffffffff << 0), (0xf041c3 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_CLKDIVSTEP", 0x20c20000, 0x0830, (0xffffffff << 0), (0x3 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CMU_HCHGEN_CLKMUX", 0x1e080000, 0x0850, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20800000, 0x0850, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20900000, 0x0850, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20a00000, 0x0850, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20b00000, 0x0850, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1A_HCHGEN_CLKMUX_CMUREF", 0x20000000, 0x0840, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL1B_HCHGEN_CLKMUX_CMUREF", 0x1e800000, 0x0840, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL2A_HCHGEN_CLKMUX_CMUREF", 0x1f000000, 0x0840, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL0_HCHGEN_CLKMUX_CMUREF", 0x1e000000, 0x0840, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_HCHGEN_CLKMUX_CMUREF", 0x20c00000, 0x0840, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_HCHGEN_CLKMUX_CMUREF", 0x20c10000, 0x0850, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_HCHGEN_CLKMUX_CMUREF", 0x20c20000, 0x0850, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_SHORTSTOP_DBG", 0x20c00000, 0x0824, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL0_SHORTSTOP", 0x20c00000, 0x0820, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL1_SHORTSTOP", 0x20c10000, 0x0820, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CPUCL2_SHORTSTOP", 0x20c20000, 0x0820, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "G3D_SHORTSTOP", 0x27f00000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_SHORTSTOP", 0x20800000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_SHORTSTOP", 0x20900000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_SHORTSTOP", 0x20a00000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MIF_SHORTSTOP", 0x20b00000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "NOCL0_SHORTSTOP", 0x1e000000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "AUR_SHORTSTOP", 0x25a00000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TPU_SHORTSTOP", 0x1cc00000, 0x0820, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20840000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20940000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20a40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20b40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1a020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x18020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1ca20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1e820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1f020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT0_DRCG_EN", 0x1e020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT1_DRCG_EN", 0x1e020000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20c40000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN_INT", 0x20c40000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1a420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1c220000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1b020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1c020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x17020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1c620000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1a820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x27f20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1d020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x11020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x11820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x14420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1ac20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1b420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1b720000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1c820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20920000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20a20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20b20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10030000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1aa20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10c20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN0", 0x1bc20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN1", 0x1bc20000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1cc20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x25a40000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MISC", 0x14700000, 0x11b4, (0x1 << 8), (0x1 << 8), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L0_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x0140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L1_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x1140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L2_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x2140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L3_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x3140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L4_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x4140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L5_RDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0x5140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L12_WDMA_DYNAMIC_GATING_EN", 0x1c0b0000, 0xc140, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L0_GLB_GLB_CGEN", 0x1c0b0000, 0x0f14, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L2_GLB_GLB_CGEN", 0x1c0b0000, 0x2f14, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "L4_GLB_GLB_CGEN", 0x1c0b0000, 0x4f14, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_MIF_DURATION", 0x18060000, 0x3cb0, (0xffffffff << 0), (0x29e << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_TOP_DURATION", 0x18060000, 0x3cb4, (0xffffffff << 0), (0xa0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_CPUCL2_DURATION", 0x18060000, 0x3cb8, (0xffffffff << 0), (0xa0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_CPUCL1_DURATION", 0x18060000, 0x3cbc, (0xffffffff << 0), (0xa0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_G3D_DURATION", 0x18060000, 0x3cc0, (0xffffffff << 0), (0xbe << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EXT_REGULATOR_TPU_DURATION", 0x18060000, 0x3cc4, (0xffffffff << 0), (0xa0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TCXO_DURATION", 0x18060000, 0x3cc8, (0xfffff << 0), (0x66c << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EARLY_WAKEUP_DPU_CTRL", 0x1e080000, 0x0880, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "EARLY_WAKEUP_DPU_DEST", 0x1e080000, 0x0898, (0xffffffff << 0), (0xfe << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TREX_D_NOCL1A", 0x20510000, 0x2000, (0xffffffff << 0), (0xf000 << 0), 0, 0, 0xffffffff, 0), +}; +unsigned int pmucal_lpm_init_size = ARRAY_SIZE(pmucal_lpm_init); +/* individual sequence descriptor for each power mode - enter, exit, early_wakeup */ +struct pmucal_seq enter_sicd[] = { +}; +struct pmucal_seq save_sicd[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_NOC", 0x1e080000, 0x1008, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_NOC", 0x1e080000, 0x180c, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL", 0x1e080000, + 0x1004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_AURCTL", 0x1e080000, 0x1808, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), +}; +struct pmucal_seq exit_sicd[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), +}; +struct pmucal_seq early_sicd[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SYSTEM_CTRL", 0x18060000, 0x3a10, (0x1 << 14), (0x0 << 14), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP4_INTR_BID_CLEAR", 0x18070000, 0x040c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0408, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), +}; +struct pmucal_seq enter_sleep[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x1 << 3), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq save_sleep[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_BOOST", 0x18000000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC", 0x18000000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_NOC_LH", 0x18000000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI0_UART", 0x18000000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI0_USI", 0x18000000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI1_UART", 0x18000000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_I3C", 0x10800000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH", 0x10800000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART", 0x10800000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI", 0x10800000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI", 0x10800000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI", 0x10800000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI", 0x10800000, 0x1818, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI", 0x10800000, 0x181c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI", 0x10800000, 0x1820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI", 0x10800000, 0x1824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI", 0x10800000, 0x1828, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI", 0x10800000, 0x182c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_I3C", 0x10c00000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH", 0x10c00000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI", 0x10c00000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI", 0x10c00000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI", 0x10c00000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI", 0x10c00000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI", 0x10c00000, 0x1818, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI", 0x10c00000, 0x181c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI", 0x10c00000, 0x1820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI", 0x10c00000, 0x1824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_APM_FUNC", 0x18000000, 0x1000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC", 0x18000000, 0x1004, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER", 0x11800000, 0x0600, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER", 0x11800000, 0x0610, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MISC_NOC_USER", 0x10010000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MISC_SSS_USER", 0x10010000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER", 0x10800000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER", 0x10800000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER", 0x10800000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER", 0x10800000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER", 0x10800000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER", 0x10800000, 0x0660, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER", 0x10800000, 0x0670, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER", 0x10800000, 0x0680, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER", 0x10800000, 0x0690, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER", 0x10800000, 0x06a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER", 0x10800000, 0x06b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER", 0x10800000, 0x06c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER", 0x10c00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER", 0x10c00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER", 0x10c00000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER", 0x10c00000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER", 0x10c00000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER", 0x10c00000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER", 0x10c00000, 0x0660, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER", 0x10c00000, 0x0670, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER", 0x10c00000, 0x0680, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER", 0x10c00000, 0x0690, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_APM_I3C_PMIC_QCH_S", 0x18000000, 0x3000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_GPIO_ALIVE_QCH", 0x18000000, 0x303c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH", 0x18000000, 0x3040, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH", 0x18000000, 0x3044, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH", 0x18000000, 0x3048, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH", 0x18000000, 0x304c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_PMU_ALIVE_QCH", 0x18000000, 0x3050, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_RTC_QCH", 0x18000000, 0x3054, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_TRTC_QCH", 0x18000000, 0x3058, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_CMU_APM_QCH", 0x18000000, 0x305c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_I3C_PMIC_QCH_P", 0x18000000, 0x3060, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI0_UART_QCH", 0x18000000, 0x3064, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI0_USI_QCH", 0x18000000, 0x3068, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI1_UART_QCH", 0x18000000, 0x306c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_APM_QCH", 0x18000000, 0x3070, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_APM_QCH", 0x18000000, 0x3074, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GREBEINTEGRATION_QCH_DBG", 0x18000000, 0x3078, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GREBEINTEGRATION_QCH_GREBE", 0x18000000, 0x307c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_INTMEM_QCH", 0x18000000, 0x3080, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_IG_SWD_QCH", 0x18000000, 0x3084, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH", 0x18000000, 0x3088, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x308c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH", 0x18000000, 0x3090, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH", 0x18000000, 0x3094, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_APM_QCH", 0x18000000, 0x3098, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH", 0x18000000, 0x309c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x30a0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH", 0x18000000, 0x30a4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH", 0x18000000, 0x30a8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AOC_QCH", 0x18000000, 0x30ac, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AP_QCH", 0x18000000, 0x30b0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AUR_QCH", 0x18000000, 0x30b4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_GSA_QCH", 0x18000000, 0x30b8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_SWD_QCH", 0x18000000, 0x30bc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_TPU_QCH", 0x18000000, 0x30c0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCA32_QCH", 0x18000000, 0x30c4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCF1_QCH", 0x18000000, 0x30c8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCP6_QCH", 0x18000000, 0x30cc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR0_QCH", 0x18000000, 0x30d0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR1_QCH", 0x18000000, 0x30d4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR2_QCH", 0x18000000, 0x30d8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR3_QCH", 0x18000000, 0x30dc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_DBGCORE_QCH", 0x18000000, 0x30e0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PMU_INTR_GEN_QCH", 0x18000000, 0x30e4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ROM_CRC32_HOST_QCH", 0x18000000, 0x30e8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH", 0x18000000, 0x30ec, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH", 0x18000000, 0x30f0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_LP0_AOC_QCH", 0x18000000, 0x30f4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_ALIVE_QCH", 0x18000000, 0x30f8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH", 0x18000000, 0x30fc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH", 0x18000000, 0x3100, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D_APM_QCH", 0x18000000, 0x3104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_LG_DBGCORE_QCH", 0x18000000, 0x3108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SS_DBGCORE_QCH_DBG", 0x18000000, 0x310c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SS_DBGCORE_QCH_GREBE", 0x18000000, 0x3110, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D_APM_QCH", 0x18000000, 0x3114, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_APM_QCH", 0x18000000, 0x3118, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_APM_QCH", 0x18000000, 0x311c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_DBGCORE_QCH", 0x18000000, 0x3120, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_IG_SWD_QCH", 0x18000000, 0x3124, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_LP0_AOC_QCH", 0x18000000, 0x3128, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_P_ALIVE_QCH", 0x18000000, 0x312c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_APM_QCH", 0x18000000, 0x3130, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_APM_I3C_PMIC_QCH_S", 0x18000000, 0x7000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_GPIO_ALIVE_QCH", 0x18000000, 0x703c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH", 0x18000000, 0x7040, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH", 0x18000000, 0x7044, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH", 0x18000000, 0x7048, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH", 0x18000000, 0x704c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_PMU_ALIVE_QCH", 0x18000000, 0x7050, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_RTC_QCH", 0x18000000, 0x7054, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_TRTC_QCH", 0x18000000, 0x7058, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_CMU_APM_QCH", 0x18000000, 0x705c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_I3C_PMIC_QCH_P", 0x18000000, 0x7060, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI0_UART_QCH", 0x18000000, 0x7064, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI0_USI_QCH", 0x18000000, 0x7068, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI1_UART_QCH", 0x18000000, 0x706c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_APM_QCH", 0x18000000, 0x7070, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_APM_QCH", 0x18000000, 0x7074, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_DBG", 0x18000000, 0x7078, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_GREBE", 0x18000000, 0x707c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_INTMEM_QCH", 0x18000000, 0x7080, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_IG_SWD_QCH", 0x18000000, 0x7084, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH", 0x18000000, 0x7088, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x708c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH", 0x18000000, 0x7090, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH", 0x18000000, 0x7094, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_APM_QCH", 0x18000000, 0x7098, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH", 0x18000000, 0x709c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x70a0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH", 0x18000000, 0x70a4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH", 0x18000000, 0x70a8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AOC_QCH", 0x18000000, 0x70ac, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AP_QCH", 0x18000000, 0x70b0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AUR_QCH", 0x18000000, 0x70b4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_GSA_QCH", 0x18000000, 0x70b8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_SWD_QCH", 0x18000000, 0x70bc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_TPU_QCH", 0x18000000, 0x70c0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCA32_QCH", 0x18000000, 0x70c4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCF1_QCH", 0x18000000, 0x70c8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCP6_QCH", 0x18000000, 0x70cc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR0_QCH", 0x18000000, 0x70d0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR1_QCH", 0x18000000, 0x70d4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR2_QCH", 0x18000000, 0x70d8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR3_QCH", 0x18000000, 0x70dc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_DBGCORE_QCH", 0x18000000, 0x70e0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PMU_INTR_GEN_QCH", 0x18000000, 0x70e4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ROM_CRC32_HOST_QCH", 0x18000000, 0x70e8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH", 0x18000000, 0x70ec, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH", 0x18000000, 0x70f0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_LP0_AOC_QCH", 0x18000000, 0x70f4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_ALIVE_QCH", 0x18000000, 0x70f8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH", 0x18000000, 0x70fc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH", 0x18000000, 0x7100, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D_APM_QCH", 0x18000000, 0x7104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_LG_DBGCORE_QCH", 0x18000000, 0x7108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SS_DBGCORE_QCH_DBG", 0x18000000, 0x710c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SS_DBGCORE_QCH_GREBE", 0x18000000, 0x7110, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D_APM_QCH", 0x18000000, 0x7114, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_APM_QCH", 0x18000000, 0x7118, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_APM_QCH", 0x18000000, 0x711c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_DBGCORE_QCH", 0x18000000, 0x7120, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_IG_SWD_QCH", 0x18000000, 0x7124, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_LP0_AOC_QCH", 0x18000000, 0x7128, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_P_ALIVE_QCH", 0x18000000, 0x712c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_APM_QCH", 0x18000000, 0x7130, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0", 0x1e080000, 0x3004, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1", 0x1e080000, 0x3008, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2", 0x1e080000, 0x300c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3", 0x1e080000, 0x3010, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4", 0x1e080000, 0x3014, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5", 0x1e080000, 0x3018, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6", 0x1e080000, 0x301c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7", 0x1e080000, 0x3020, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "DMYQCH_CON_PCIE_GEN4_0_QCH", 0x11800000, 0x3000, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1", 0x11800000, 0x3004, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_D_TZPC_HSI1_QCH", 0x11800000, 0x3018, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_GPC_HSI1_QCH", 0x11800000, 0x301c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_GPIO_HSI1_QCH", 0x11800000, 0x3020, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_HSI1_CMU_HSI1_QCH", 0x11800000, 0x3024, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_HSI1_QCH", 0x11800000, 0x3028, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH", 0x11800000, 0x302c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH", 0x11800000, 0x3030, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_APB_1", 0x11800000, 0x3034, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_APB_2", 0x11800000, 0x3038, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_AXI_1", 0x11800000, 0x303c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_AXI_2", 0x11800000, 0x3040, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_DBG_1", 0x11800000, 0x3044, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_DBG_2", 0x11800000, 0x3048, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_PCS_APB", 0x11800000, 0x304c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_PMA_APB", 0x11800000, 0x3050, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_UDBG", 0x11800000, 0x3054, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x3058, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x305c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PPMU_HSI1_QCH", 0x11800000, 0x3060, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4A_HSI1_QCH", 0x11800000, 0x3064, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4B_HSI1_QCH", 0x11800000, 0x3068, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_HSI1_QCH", 0x11800000, 0x306c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_HSI1_QCH", 0x11800000, 0x3070, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x3074, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x3078, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI1_QCH_S1", 0x11800000, 0x307c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI1_QCH_S2", 0x11800000, 0x3080, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSREG_HSI1_QCH", 0x11800000, 0x3084, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH", 0x11800000, 0x3088, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH", 0x11800000, 0x308c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH", 0x11800000, 0x3090, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH", 0x11800000, 0x3094, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_DMYQCH_CON_PCIE_GEN4_0_QCH", 0x11800000, 0x7000, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1", 0x11800000, 0x7004, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_D_TZPC_HSI1_QCH", 0x11800000, 0x7018, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_GPC_HSI1_QCH", 0x11800000, 0x701c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_GPIO_HSI1_QCH", 0x11800000, 0x7020, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_HSI1_CMU_HSI1_QCH", 0x11800000, 0x7024, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_HSI1_QCH", 0x11800000, 0x7028, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH", 0x11800000, 0x702c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH", 0x11800000, 0x7030, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_APB_1", 0x11800000, 0x7034, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_APB_2", 0x11800000, 0x7038, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_AXI_1", 0x11800000, 0x703c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_AXI_2", 0x11800000, 0x7040, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_DBG_1", 0x11800000, 0x7044, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_DBG_2", 0x11800000, 0x7048, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_PCS_APB", 0x11800000, 0x704c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_PMA_APB", 0x11800000, 0x7050, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_UDBG", 0x11800000, 0x7054, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x7058, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x705c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PPMU_HSI1_QCH", 0x11800000, 0x7060, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_QE_PCIE_GEN4A_HSI1_QCH", 0x11800000, 0x7064, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_QE_PCIE_GEN4B_HSI1_QCH", 0x11800000, 0x7068, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_HSI1_QCH", 0x11800000, 0x706c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_HSI1_QCH", 0x11800000, 0x7070, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x7074, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x7078, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSMMU_HSI1_QCH_S1", 0x11800000, 0x707c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSMMU_HSI1_QCH_S2", 0x11800000, 0x7080, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSREG_HSI1_QCH", 0x11800000, 0x7084, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH", 0x11800000, 0x7088, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH", 0x11800000, 0x708c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH", 0x11800000, 0x7090, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH", 0x11800000, 0x7094, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_PUF_QCH", 0x10010000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ADM_AHB_G_SSS_QCH", 0x10010000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DIT_QCH", 0x10010000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_MISC_QCH", 0x10010000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GIC_QCH", 0x10010000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_MISC_QCH", 0x10010000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_MISC_QCH", 0x10010000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH", 0x10010000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH", 0x10010000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_ID_SSS_QCH", 0x10010000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_GIC_CU_QCH", 0x10010000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MISC_CU_QCH", 0x10010000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_ID_SSS_QCH", 0x10010000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_GIC_CU_QCH", 0x10010000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MISC_CU_QCH", 0x10010000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MCT_QCH", 0x10010000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MISC_CMU_MISC_QCH", 0x10010000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_BIRA_QCH", 0x10010000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_BISR_QCH", 0x10010000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_TOP_QCH", 0x10010000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDMA0_QCH", 0x10010000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDMA1_QCH", 0x10010000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_MISC_QCH", 0x10010000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_DIT_QCH", 0x10010000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDMA0_QCH", 0x10010000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDMA1_QCH", 0x10010000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_RTIC_QCH", 0x10010000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SPDMA0_QCH", 0x10010000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SPDMA1_QCH", 0x10010000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SSS_QCH", 0x10010000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RTIC_QCH", 0x10010000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_GIC_QCH", 0x10010000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_MISC_QCH", 0x10010000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SPDMA0_QCH", 0x10010000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SPDMA1_QCH", 0x10010000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_DIT_QCH", 0x10010000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PDMA0_QCH", 0x10010000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PDMA1_QCH", 0x10010000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_RTIC_QCH", 0x10010000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SPDMA0_QCH", 0x10010000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SPDMA1_QCH", 0x10010000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SSS_QCH", 0x10010000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSS_QCH", 0x10010000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_MISC_QCH", 0x10010000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_SSS_QCH", 0x10010000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_MISC_QCH", 0x10010000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TMU_SUB_QCH", 0x10010000, 0x3104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TMU_TOP_QCH", 0x10010000, 0x3108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_CLUSTER0_QCH", 0x10010000, 0x310c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_CLUSTER1_QCH", 0x10010000, 0x3110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_PUF_QCH", 0x10010000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ADM_AHB_G_SSS_QCH", 0x10010000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DIT_QCH", 0x10010000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_MISC_QCH", 0x10010000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GIC_QCH", 0x10010000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_MISC_QCH", 0x10010000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_MISC_QCH", 0x10010000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x7058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH", 0x10010000, 0x705c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x7060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x7064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x7068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH", 0x10010000, 0x706c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_ID_SSS_QCH", 0x10010000, 0x7070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_GIC_CU_QCH", 0x10010000, 0x7074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_CU_QCH", 0x10010000, 0x7078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_ID_SSS_QCH", 0x10010000, 0x707c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_GIC_CU_QCH", 0x10010000, 0x7080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_CU_QCH", 0x10010000, 0x7084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MCT_QCH", 0x10010000, 0x7088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MISC_CMU_MISC_QCH", 0x10010000, 0x708c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_BIRA_QCH", 0x10010000, 0x7090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_BISR_QCH", 0x10010000, 0x7094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_TOP_QCH", 0x10010000, 0x7098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDMA0_QCH", 0x10010000, 0x709c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDMA1_QCH", 0x10010000, 0x70a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_MISC_QCH", 0x10010000, 0x70a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_DIT_QCH", 0x10010000, 0x70a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDMA0_QCH", 0x10010000, 0x70ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDMA1_QCH", 0x10010000, 0x70b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_RTIC_QCH", 0x10010000, 0x70b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SPDMA0_QCH", 0x10010000, 0x70b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SPDMA1_QCH", 0x10010000, 0x70bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SSS_QCH", 0x10010000, 0x70c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RTIC_QCH", 0x10010000, 0x70c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_GIC_QCH", 0x10010000, 0x70c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_MISC_QCH", 0x10010000, 0x70cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SPDMA0_QCH", 0x10010000, 0x70d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SPDMA1_QCH", 0x10010000, 0x70d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_DIT_QCH", 0x10010000, 0x70d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_PDMA0_QCH", 0x10010000, 0x70dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_PDMA1_QCH", 0x10010000, 0x70e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_RTIC_QCH", 0x10010000, 0x70e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SPDMA0_QCH", 0x10010000, 0x70e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SPDMA1_QCH", 0x10010000, 0x70ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SSS_QCH", 0x10010000, 0x70f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSS_QCH", 0x10010000, 0x70f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_MISC_QCH", 0x10010000, 0x70f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_SSS_QCH", 0x10010000, 0x70fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_MISC_QCH", 0x10010000, 0x7100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TMU_SUB_QCH", 0x10010000, 0x7104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TMU_TOP_QCH", 0x10010000, 0x7108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_CLUSTER0_QCH", 0x10010000, 0x710c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_CLUSTER1_QCH", 0x10010000, 0x7110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C1_QCH_SCLK", 0x10800000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C2_QCH_SCLK", 0x10800000, 0x3004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C3_QCH_SCLK", 0x10800000, 0x3008, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C4_QCH_SCLK", 0x10800000, 0x300c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C5_QCH_SCLK", 0x10800000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C6_QCH_SCLK", 0x10800000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C7_QCH_SCLK", 0x10800000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C8_QCH_SCLK", 0x10800000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_PERIC0_QCH", 0x10800000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_PERIC0_QCH", 0x10800000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_PERIC0_QCH", 0x10800000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C1_QCH_PCLK", 0x10800000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C2_QCH_PCLK", 0x10800000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C3_QCH_PCLK", 0x10800000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C4_QCH_PCLK", 0x10800000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C5_QCH_PCLK", 0x10800000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C6_QCH_PCLK", 0x10800000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C7_QCH_PCLK", 0x10800000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C8_QCH_PCLK", 0x10800000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH", 0x10800000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH", 0x10800000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PERIC0_CMU_PERIC0_QCH", 0x10800000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_PERIC0_QCH", 0x10800000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_PERIC0_QCH", 0x10800000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI0_UART_QCH", 0x10800000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI14_USI_QCH", 0x10800000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI1_USI_QCH", 0x10800000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI2_USI_QCH", 0x10800000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI3_USI_QCH", 0x10800000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI4_USI_QCH", 0x10800000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI5_USI_QCH", 0x10800000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI6_USI_QCH", 0x10800000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI7_USI_QCH", 0x10800000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI8_USI_QCH", 0x10800000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C1_QCH_SCLK", 0x10800000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C2_QCH_SCLK", 0x10800000, 0x7004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C3_QCH_SCLK", 0x10800000, 0x7008, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C4_QCH_SCLK", 0x10800000, 0x700c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C5_QCH_SCLK", 0x10800000, 0x7010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C6_QCH_SCLK", 0x10800000, 0x7014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C7_QCH_SCLK", 0x10800000, 0x7018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C8_QCH_SCLK", 0x10800000, 0x701c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_PERIC0_QCH", 0x10800000, 0x702c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_PERIC0_QCH", 0x10800000, 0x7030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPIO_PERIC0_QCH", 0x10800000, 0x7034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C1_QCH_PCLK", 0x10800000, 0x7038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C2_QCH_PCLK", 0x10800000, 0x703c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C3_QCH_PCLK", 0x10800000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C4_QCH_PCLK", 0x10800000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C5_QCH_PCLK", 0x10800000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C6_QCH_PCLK", 0x10800000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C7_QCH_PCLK", 0x10800000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C8_QCH_PCLK", 0x10800000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH", 0x10800000, 0x7058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH", 0x10800000, 0x705c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PERIC0_CMU_PERIC0_QCH", 0x10800000, 0x7060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC0_QCH", 0x10800000, 0x7064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_PERIC0_QCH", 0x10800000, 0x7068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI0_UART_QCH", 0x10800000, 0x706c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI14_USI_QCH", 0x10800000, 0x7070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI1_USI_QCH", 0x10800000, 0x7074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI2_USI_QCH", 0x10800000, 0x7078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI3_USI_QCH", 0x10800000, 0x707c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI4_USI_QCH", 0x10800000, 0x7080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI5_USI_QCH", 0x10800000, 0x7084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI6_USI_QCH", 0x10800000, 0x7088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI7_USI_QCH", 0x10800000, 0x708c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI8_USI_QCH", 0x10800000, 0x7090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C0_QCH_SCLK", 0x10c00000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_PERIC1_QCH", 0x10c00000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_PERIC1_QCH", 0x10c00000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_PERIC1_QCH", 0x10c00000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C0_QCH_PCLK", 0x10c00000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH", 0x10c00000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH", 0x10c00000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PERIC1_CMU_PERIC1_QCH", 0x10c00000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PWM_QCH", 0x10c00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_PERIC1_QCH", 0x10c00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_PERIC1_QCH", 0x10c00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI0_USI_QCH", 0x10c00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI10_USI_QCH", 0x10c00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI11_USI_QCH", 0x10c00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI12_USI_QCH", 0x10c00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI13_USI_QCH", 0x10c00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI15_USI_QCH", 0x10c00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI16_USI_QCH", 0x10c00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI9_USI_QCH", 0x10c00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C0_QCH_SCLK", 0x10c00000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_PERIC1_QCH", 0x10c00000, 0x7010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_PERIC1_QCH", 0x10c00000, 0x7014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPIO_PERIC1_QCH", 0x10c00000, 0x7018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C0_QCH_PCLK", 0x10c00000, 0x701c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH", 0x10c00000, 0x7020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH", 0x10c00000, 0x7024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PERIC1_CMU_PERIC1_QCH", 0x10c00000, 0x7028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PWM_QCH", 0x10c00000, 0x702c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC1_QCH", 0x10c00000, 0x7030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_PERIC1_QCH", 0x10c00000, 0x7034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI0_USI_QCH", 0x10c00000, 0x7038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI10_USI_QCH", 0x10c00000, 0x703c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI11_USI_QCH", 0x10c00000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI12_USI_QCH", 0x10c00000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI13_USI_QCH", 0x10c00000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI15_USI_QCH", 0x10c00000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI16_USI_QCH", 0x10c00000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI9_USI_QCH", 0x10c00000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0", 0x18000000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0", 0x1e080000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0", 0x20c00000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0", 0x20c00000, 0x0814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0", 0x20c10000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL2_CMU_CPUCL2_CLKOUT0", 0x20c20000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "CLKOUT_CON_BLK_HSI1_CMU_HSI1_CLKOUT0", 0x11800000, 0x0810, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20800000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20900000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20a00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20b00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0", 0x10010000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0", 0x10800000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0", 0x10c00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "APM_CMU_APM_CONTROLLER_OPTION", 0x18000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_CMU_TOP_CONTROLLER_OPTION", 0x1e080000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION", 0x20c00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION", 0x20c00000, 0x0804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION", 0x20c10000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION", 0x20c20000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "HSI1_CMU_HSI1_CONTROLLER_OPTION", 0x11800000, 0x0800, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20800000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20900000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20a00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20b00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MISC_CMU_MISC_CONTROLLER_OPTION", 0x10010000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PERIC0_CMU_PERIC0_CONTROLLER_OPTION", 0x10800000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PERIC1_CMU_PERIC1_CONTROLLER_OPTION", 0x10c00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_HCHGEN_CLKMUX", 0x1e080000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CPU_SW", 0x20c00000, 0x0848, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CMUREF", 0x20c00000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CPU_SW", 0x20c10000, 0x0858, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CMUREF", 0x20c10000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CPU_SW", 0x20c20000, 0x085c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CMUREF", 0x20c20000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20800000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20900000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20a00000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20b00000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP_SMPL_FLT", 0x20c00000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_SMPL_FLT", 0x20c10000, 0x083c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_SMPL_FLT", 0x20c20000, 0x083c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_OCP_FLT", 0x20c10000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_OCP_FLT", 0x20c20000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_VDROOP_FLT", 0x20c10000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_VDROOP_FLT", 0x20c20000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_CON_HEAVY", 0x20c10000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_CON_HEAVY", 0x20c20000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_CON_LIGHT", 0x20c10000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_CON_LIGHT", 0x20c20000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP_CON", 0x20c00000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP", 0x20c00000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP", 0x20c10000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP", 0x20c20000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_SHORTSTOP_DBG", 0x20c00000, 0x0824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_SHORTSTOP", 0x20c00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_SHORTSTOP", 0x20c10000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_SHORTSTOP", 0x20c20000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "G3D_SHORTSTOP", 0x27f00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20800000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20900000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20a00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20b00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "TPU_SHORTSTOP", 0x1cc00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "AUR_SHORTSTOP", 0x25a00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL0_SHORTSTOP", 0x1e000000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_NOC", 0x1e080000, 0x1008, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_NOC", 0x1e080000, 0x180c, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL", 0x1e080000, + 0x1004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_AURCTL", 0x1e080000, 0x1808, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), +}; +struct pmucal_seq exit_sleep[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0208, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20840000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20940000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20a40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20b40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x18020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1e820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1f020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT0_DRCG_EN", 0x1e020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT1_DRCG_EN", 0x1e020000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20c40000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN_INT", 0x20c40000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x27f20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x11820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x14420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20920000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20a20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20b20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10c20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10030000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MISC", 0x14700000, 0x11b4, (0x1 << 8), (0x1 << 8), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0x7 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0x9 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xb << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xc << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xd << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xe << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TREX_D_NOCL1A", 0x20510000, 0x2000, (0xffffffff << 0), (0xf000 << 0), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq early_sleep[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SYSTEM_CTRL", 0x18060000, 0x3a10, (0x1 << 14), (0x0 << 14), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP4_INTR_BID_CLEAR", 0x18070000, 0x040c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0408, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), +}; +struct pmucal_seq enter_sleep_slcmon[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x1 << 3), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq save_sleep_slcmon[] = { + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_BOOST", 0x18000000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_I3C_PMIC", 0x18000000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_NOC_LH", 0x18000000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI0_UART", 0x18000000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI0_USI", 0x18000000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_APM_USI1_UART", 0x18000000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_I3C", 0x10800000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_NOCP_LH", 0x10800000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART", 0x10800000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI", 0x10800000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI", 0x10800000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI", 0x10800000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI", 0x10800000, 0x1818, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI", 0x10800000, 0x181c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI", 0x10800000, 0x1820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI", 0x10800000, 0x1824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI", 0x10800000, 0x1828, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI", 0x10800000, 0x182c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_I3C", 0x10c00000, 0x1800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_NOCP_LH", 0x10c00000, 0x1804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI", 0x10c00000, 0x1808, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI", 0x10c00000, 0x180c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI", 0x10c00000, 0x1810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI", 0x10c00000, 0x1814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI", 0x10c00000, 0x1818, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI", 0x10c00000, 0x181c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI", 0x10c00000, 0x1820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI", 0x10c00000, 0x1824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_APM_FUNC", 0x18000000, 0x1000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC", 0x18000000, 0x1004, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER", 0x11800000, 0x0600, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_HSI1_PCIE_USER", 0x11800000, 0x0610, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MISC_NOC_USER", 0x10010000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_MISC_SSS_USER", 0x10010000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_NOC_USER", 0x10800000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER", 0x10800000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER", 0x10800000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER", 0x10800000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER", 0x10800000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER", 0x10800000, 0x0660, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER", 0x10800000, 0x0670, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER", 0x10800000, 0x0680, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER", 0x10800000, 0x0690, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER", 0x10800000, 0x06a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER", 0x10800000, 0x06b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER", 0x10800000, 0x06c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER", 0x10c00000, 0x0600, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER", 0x10c00000, 0x0610, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER", 0x10c00000, 0x0620, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER", 0x10c00000, 0x0630, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER", 0x10c00000, 0x0640, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER", 0x10c00000, 0x0650, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER", 0x10c00000, 0x0660, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI15_USI_USER", 0x10c00000, 0x0670, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI16_USI_USER", 0x10c00000, 0x0680, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER", 0x10c00000, 0x0690, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_APM_I3C_PMIC_QCH_S", 0x18000000, 0x3000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_GPIO_ALIVE_QCH", 0x18000000, 0x303c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH", 0x18000000, 0x3040, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH", 0x18000000, 0x3044, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH", 0x18000000, 0x3048, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH", 0x18000000, 0x304c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_PMU_ALIVE_QCH", 0x18000000, 0x3050, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_RTC_QCH", 0x18000000, 0x3054, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APBIF_TRTC_QCH", 0x18000000, 0x3058, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_CMU_APM_QCH", 0x18000000, 0x305c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_I3C_PMIC_QCH_P", 0x18000000, 0x3060, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI0_UART_QCH", 0x18000000, 0x3064, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI0_USI_QCH", 0x18000000, 0x3068, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_APM_USI1_UART_QCH", 0x18000000, 0x306c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_APM_QCH", 0x18000000, 0x3070, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_APM_QCH", 0x18000000, 0x3074, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GREBEINTEGRATION_QCH_DBG", 0x18000000, 0x3078, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GREBEINTEGRATION_QCH_GREBE", 0x18000000, 0x307c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_INTMEM_QCH", 0x18000000, 0x3080, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_IG_SWD_QCH", 0x18000000, 0x3084, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH", 0x18000000, 0x3088, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x308c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH", 0x18000000, 0x3090, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH", 0x18000000, 0x3094, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_D_APM_QCH", 0x18000000, 0x3098, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH", 0x18000000, 0x309c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x30a0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH", 0x18000000, 0x30a4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH", 0x18000000, 0x30a8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AOC_QCH", 0x18000000, 0x30ac, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AP_QCH", 0x18000000, 0x30b0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_AUR_QCH", 0x18000000, 0x30b4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_GSA_QCH", 0x18000000, 0x30b8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_SWD_QCH", 0x18000000, 0x30bc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_APM_TPU_QCH", 0x18000000, 0x30c0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCA32_QCH", 0x18000000, 0x30c4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCF1_QCH", 0x18000000, 0x30c8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AOCP6_QCH", 0x18000000, 0x30cc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR0_QCH", 0x18000000, 0x30d0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR1_QCH", 0x18000000, 0x30d4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR2_QCH", 0x18000000, 0x30d8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_AUR3_QCH", 0x18000000, 0x30dc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MAILBOX_AP_DBGCORE_QCH", 0x18000000, 0x30e0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PMU_INTR_GEN_QCH", 0x18000000, 0x30e4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ROM_CRC32_HOST_QCH", 0x18000000, 0x30e8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH", 0x18000000, 0x30ec, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH", 0x18000000, 0x30f0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_LP0_AOC_QCH", 0x18000000, 0x30f4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_ALIVE_QCH", 0x18000000, 0x30f8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH", 0x18000000, 0x30fc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH", 0x18000000, 0x3100, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_D_APM_QCH", 0x18000000, 0x3104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_LG_DBGCORE_QCH", 0x18000000, 0x3108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SS_DBGCORE_QCH_DBG", 0x18000000, 0x310c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SS_DBGCORE_QCH_GREBE", 0x18000000, 0x3110, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_D_APM_QCH", 0x18000000, 0x3114, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_APM_QCH", 0x18000000, 0x3118, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_APM_QCH", 0x18000000, 0x311c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_DBGCORE_QCH", 0x18000000, 0x3120, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_IG_SWD_QCH", 0x18000000, 0x3124, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_LP0_AOC_QCH", 0x18000000, 0x3128, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_UASC_P_ALIVE_QCH", 0x18000000, 0x312c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_APM_QCH", 0x18000000, 0x3130, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_APM_I3C_PMIC_QCH_S", 0x18000000, 0x7000, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_GPIO_ALIVE_QCH", 0x18000000, 0x703c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH", 0x18000000, 0x7040, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2APM_QCH", 0x18000000, 0x7044, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2AP_QCH", 0x18000000, 0x7048, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_INTCOMB_VGPIO2PMU_QCH", 0x18000000, 0x704c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_PMU_ALIVE_QCH", 0x18000000, 0x7050, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_RTC_QCH", 0x18000000, 0x7054, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APBIF_TRTC_QCH", 0x18000000, 0x7058, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_CMU_APM_QCH", 0x18000000, 0x705c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_I3C_PMIC_QCH_P", 0x18000000, 0x7060, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI0_UART_QCH", 0x18000000, 0x7064, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI0_USI_QCH", 0x18000000, 0x7068, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_APM_USI1_UART_QCH", 0x18000000, 0x706c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_APM_QCH", 0x18000000, 0x7070, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_APM_QCH", 0x18000000, 0x7074, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_DBG", 0x18000000, 0x7078, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GREBEINTEGRATION_QCH_GREBE", 0x18000000, 0x707c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_INTMEM_QCH", 0x18000000, 0x7080, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_IG_SWD_QCH", 0x18000000, 0x7084, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LG_DBGCORE_CD_QCH", 0x18000000, 0x7088, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x708c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_LP0_AOC_CU_QCH", 0x18000000, 0x7090, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_ALIVE_CU_QCH", 0x18000000, 0x7094, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_D_APM_QCH", 0x18000000, 0x7098, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LG_DBGCORE_CD_QCH", 0x18000000, 0x709c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LG_SCAN2DRAM_CD_QCH", 0x18000000, 0x70a0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_LP0_AOC_CU_QCH", 0x18000000, 0x70a4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_ALIVE_CU_QCH", 0x18000000, 0x70a8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AOC_QCH", 0x18000000, 0x70ac, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AP_QCH", 0x18000000, 0x70b0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_AUR_QCH", 0x18000000, 0x70b4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_GSA_QCH", 0x18000000, 0x70b8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_SWD_QCH", 0x18000000, 0x70bc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_APM_TPU_QCH", 0x18000000, 0x70c0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCA32_QCH", 0x18000000, 0x70c4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCF1_QCH", 0x18000000, 0x70c8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AOCP6_QCH", 0x18000000, 0x70cc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR0_QCH", 0x18000000, 0x70d0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR1_QCH", 0x18000000, 0x70d4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR2_QCH", 0x18000000, 0x70d8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_AUR3_QCH", 0x18000000, 0x70dc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MAILBOX_AP_DBGCORE_QCH", 0x18000000, 0x70e0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PMU_INTR_GEN_QCH", 0x18000000, 0x70e4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ROM_CRC32_HOST_QCH", 0x18000000, 0x70e8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_DBGCORE_QCH", 0x18000000, 0x70ec, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RSTNSYNC_CLK_APM_GREBE_QCH", 0x18000000, 0x70f0, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_LP0_AOC_QCH", 0x18000000, 0x70f4, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_ALIVE_QCH", 0x18000000, 0x70f8, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_SI_LG_DBGCORE_QCH", 0x18000000, 0x70fc, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_SI_LG_SCAN2DRAM_QCH", 0x18000000, 0x7100, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_D_APM_QCH", 0x18000000, 0x7104, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_LG_DBGCORE_QCH", 0x18000000, 0x7108, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SS_DBGCORE_QCH_DBG", 0x18000000, 0x710c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SS_DBGCORE_QCH_GREBE", 0x18000000, 0x7110, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_D_APM_QCH", 0x18000000, 0x7114, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_APM_QCH", 0x18000000, 0x7118, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_APM_QCH", 0x18000000, 0x711c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_DBGCORE_QCH", 0x18000000, 0x7120, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_IG_SWD_QCH", 0x18000000, 0x7124, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_LP0_AOC_QCH", 0x18000000, 0x7128, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_UASC_P_ALIVE_QCH", 0x18000000, 0x712c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_APM_QCH", 0x18000000, 0x7130, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0", 0x1e080000, 0x3004, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1", 0x1e080000, 0x3008, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2", 0x1e080000, 0x300c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3", 0x1e080000, 0x3010, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4", 0x1e080000, 0x3014, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5", 0x1e080000, 0x3018, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6", 0x1e080000, 0x301c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7", 0x1e080000, 0x3020, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "DMYQCH_CON_PCIE_GEN4_0_QCH", 0x11800000, 0x3000, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1", 0x11800000, 0x3004, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_D_TZPC_HSI1_QCH", 0x11800000, 0x3018, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_GPC_HSI1_QCH", 0x11800000, 0x301c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_GPIO_HSI1_QCH", 0x11800000, 0x3020, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_HSI1_CMU_HSI1_QCH", 0x11800000, 0x3024, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_HSI1_QCH", 0x11800000, 0x3028, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH", 0x11800000, 0x302c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH", 0x11800000, 0x3030, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_APB_1", 0x11800000, 0x3034, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_APB_2", 0x11800000, 0x3038, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_AXI_1", 0x11800000, 0x303c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_AXI_2", 0x11800000, 0x3040, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_DBG_1", 0x11800000, 0x3044, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_DBG_2", 0x11800000, 0x3048, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_PCS_APB", 0x11800000, 0x304c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_PMA_APB", 0x11800000, 0x3050, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_GEN4_0_QCH_UDBG", 0x11800000, 0x3054, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x3058, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x305c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_PPMU_HSI1_QCH", 0x11800000, 0x3060, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4A_HSI1_QCH", 0x11800000, 0x3064, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_QE_PCIE_GEN4B_HSI1_QCH", 0x11800000, 0x3068, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_HSI1_QCH", 0x11800000, 0x306c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_HSI1_QCH", 0x11800000, 0x3070, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x3074, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x3078, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI1_QCH_S1", 0x11800000, 0x307c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSMMU_HSI1_QCH_S2", 0x11800000, 0x3080, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_SYSREG_HSI1_QCH", 0x11800000, 0x3084, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH", 0x11800000, 0x3088, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH", 0x11800000, 0x308c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH", 0x11800000, 0x3090, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH", 0x11800000, 0x3094, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_DMYQCH_CON_PCIE_GEN4_0_QCH", 0x11800000, 0x7000, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_DMYQCH_CON_PCIE_GEN4_0_QCH_SCLK_1", 0x11800000, 0x7004, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_D_TZPC_HSI1_QCH", 0x11800000, 0x7018, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_GPC_HSI1_QCH", 0x11800000, 0x701c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_GPIO_HSI1_QCH", 0x11800000, 0x7020, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_HSI1_CMU_HSI1_QCH", 0x11800000, 0x7024, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_HSI1_QCH", 0x11800000, 0x7028, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_HSI1_CU_QCH", 0x11800000, 0x702c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_HSI1_CU_QCH", 0x11800000, 0x7030, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_APB_1", 0x11800000, 0x7034, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_APB_2", 0x11800000, 0x7038, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_AXI_1", 0x11800000, 0x703c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_AXI_2", 0x11800000, 0x7040, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_DBG_1", 0x11800000, 0x7044, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_DBG_2", 0x11800000, 0x7048, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_PCS_APB", 0x11800000, 0x704c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_PMA_APB", 0x11800000, 0x7050, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_GEN4_0_QCH_UDBG", 0x11800000, 0x7054, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x7058, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x705c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_PPMU_HSI1_QCH", 0x11800000, 0x7060, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_QE_PCIE_GEN4A_HSI1_QCH", 0x11800000, 0x7064, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_QE_PCIE_GEN4B_HSI1_QCH", 0x11800000, 0x7068, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_HSI1_QCH", 0x11800000, 0x706c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_HSI1_QCH", 0x11800000, 0x7070, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN4A_0_QCH", 0x11800000, 0x7074, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SSMT_PCIE_IA_GEN4B_0_QCH", 0x11800000, 0x7078, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSMMU_HSI1_QCH_S1", 0x11800000, 0x707c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSMMU_HSI1_QCH_S2", 0x11800000, 0x7080, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_SYSREG_HSI1_QCH", 0x11800000, 0x7084, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4A_DBI_0_QCH", 0x11800000, 0x7088, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4A_SLV_0_QCH", 0x11800000, 0x708c, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4B_DBI_0_QCH", 0x11800000, 0x7090, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_READ, "DBG_NFO_QCH_CON_UASC_PCIE_GEN4B_SLV_0_QCH", 0x11800000, 0x7094, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_PUF_QCH", 0x10010000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_ADM_AHB_G_SSS_QCH", 0x10010000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_DIT_QCH", 0x10010000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_MISC_QCH", 0x10010000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GIC_QCH", 0x10010000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_MISC_QCH", 0x10010000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_ACEL_SI_D_MISC_QCH", 0x10010000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH", 0x10010000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH", 0x10010000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_ID_SSS_QCH", 0x10010000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_GIC_CU_QCH", 0x10010000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_MISC_CU_QCH", 0x10010000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_ID_SSS_QCH", 0x10010000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_GIC_CU_QCH", 0x10010000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_MISC_CU_QCH", 0x10010000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MCT_QCH", 0x10010000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_MISC_CMU_MISC_QCH", 0x10010000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_BIRA_QCH", 0x10010000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_BISR_QCH", 0x10010000, 0x3094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_OTP_CON_TOP_QCH", 0x10010000, 0x3098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDMA0_QCH", 0x10010000, 0x309c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PDMA1_QCH", 0x10010000, 0x30a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PPMU_MISC_QCH", 0x10010000, 0x30a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_DIT_QCH", 0x10010000, 0x30a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDMA0_QCH", 0x10010000, 0x30ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_PDMA1_QCH", 0x10010000, 0x30b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_RTIC_QCH", 0x10010000, 0x30b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SPDMA0_QCH", 0x10010000, 0x30b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SPDMA1_QCH", 0x10010000, 0x30bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_QE_SSS_QCH", 0x10010000, 0x30c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_RTIC_QCH", 0x10010000, 0x30c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_GIC_QCH", 0x10010000, 0x30c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_MISC_QCH", 0x10010000, 0x30cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SPDMA0_QCH", 0x10010000, 0x30d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SPDMA1_QCH", 0x10010000, 0x30d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_DIT_QCH", 0x10010000, 0x30d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PDMA0_QCH", 0x10010000, 0x30dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_PDMA1_QCH", 0x10010000, 0x30e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_RTIC_QCH", 0x10010000, 0x30e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SPDMA0_QCH", 0x10010000, 0x30e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SPDMA1_QCH", 0x10010000, 0x30ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSMT_SSS_QCH", 0x10010000, 0x30f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SSS_QCH", 0x10010000, 0x30f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_MISC_QCH", 0x10010000, 0x30f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSMMU_SSS_QCH", 0x10010000, 0x30fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_MISC_QCH", 0x10010000, 0x3100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TMU_SUB_QCH", 0x10010000, 0x3104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_TMU_TOP_QCH", 0x10010000, 0x3108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_CLUSTER0_QCH", 0x10010000, 0x310c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_WDT_CLUSTER1_QCH", 0x10010000, 0x3110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_PUF_QCH", 0x10010000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_ADM_AHB_G_SSS_QCH", 0x10010000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_DIT_QCH", 0x10010000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_MISC_QCH", 0x10010000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GIC_QCH", 0x10010000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_MISC_QCH", 0x10010000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_ACEL_SI_D_MISC_QCH", 0x10010000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x7058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_ICC_CLUSTER0_GIC_QCH", 0x10010000, 0x705c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_MI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x7060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_ICC_CLUSTER0_GIC_CU_QCH", 0x10010000, 0x7064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_CD_QCH", 0x10010000, 0x7068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AST_SI_L_IRI_GIC_CLUSTER0_QCH", 0x10010000, 0x706c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_ID_SSS_QCH", 0x10010000, 0x7070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_GIC_CU_QCH", 0x10010000, 0x7074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_MISC_CU_QCH", 0x10010000, 0x7078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_ID_SSS_QCH", 0x10010000, 0x707c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_GIC_CU_QCH", 0x10010000, 0x7080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_MISC_CU_QCH", 0x10010000, 0x7084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MCT_QCH", 0x10010000, 0x7088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_MISC_CMU_MISC_QCH", 0x10010000, 0x708c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_BIRA_QCH", 0x10010000, 0x7090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_BISR_QCH", 0x10010000, 0x7094, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_OTP_CON_TOP_QCH", 0x10010000, 0x7098, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDMA0_QCH", 0x10010000, 0x709c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PDMA1_QCH", 0x10010000, 0x70a0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PPMU_MISC_QCH", 0x10010000, 0x70a4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_DIT_QCH", 0x10010000, 0x70a8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDMA0_QCH", 0x10010000, 0x70ac, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_PDMA1_QCH", 0x10010000, 0x70b0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_RTIC_QCH", 0x10010000, 0x70b4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SPDMA0_QCH", 0x10010000, 0x70b8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SPDMA1_QCH", 0x10010000, 0x70bc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_QE_SSS_QCH", 0x10010000, 0x70c0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_RTIC_QCH", 0x10010000, 0x70c4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_GIC_QCH", 0x10010000, 0x70c8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_MISC_QCH", 0x10010000, 0x70cc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SPDMA0_QCH", 0x10010000, 0x70d0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SPDMA1_QCH", 0x10010000, 0x70d4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_DIT_QCH", 0x10010000, 0x70d8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_PDMA0_QCH", 0x10010000, 0x70dc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_PDMA1_QCH", 0x10010000, 0x70e0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_RTIC_QCH", 0x10010000, 0x70e4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SPDMA0_QCH", 0x10010000, 0x70e8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SPDMA1_QCH", 0x10010000, 0x70ec, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSMT_SSS_QCH", 0x10010000, 0x70f0, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SSS_QCH", 0x10010000, 0x70f4, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_MISC_QCH", 0x10010000, 0x70f8, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSMMU_SSS_QCH", 0x10010000, 0x70fc, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_MISC_QCH", 0x10010000, 0x7100, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TMU_SUB_QCH", 0x10010000, 0x7104, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_TMU_TOP_QCH", 0x10010000, 0x7108, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_CLUSTER0_QCH", 0x10010000, 0x710c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_WDT_CLUSTER1_QCH", 0x10010000, 0x7110, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C1_QCH_SCLK", 0x10800000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C2_QCH_SCLK", 0x10800000, 0x3004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C3_QCH_SCLK", 0x10800000, 0x3008, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C4_QCH_SCLK", 0x10800000, 0x300c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C5_QCH_SCLK", 0x10800000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C6_QCH_SCLK", 0x10800000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C7_QCH_SCLK", 0x10800000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C8_QCH_SCLK", 0x10800000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_PERIC0_QCH", 0x10800000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_PERIC0_QCH", 0x10800000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_PERIC0_QCH", 0x10800000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C1_QCH_PCLK", 0x10800000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C2_QCH_PCLK", 0x10800000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C3_QCH_PCLK", 0x10800000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C4_QCH_PCLK", 0x10800000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C5_QCH_PCLK", 0x10800000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C6_QCH_PCLK", 0x10800000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C7_QCH_PCLK", 0x10800000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C8_QCH_PCLK", 0x10800000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH", 0x10800000, 0x3058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH", 0x10800000, 0x305c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PERIC0_CMU_PERIC0_QCH", 0x10800000, 0x3060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_PERIC0_QCH", 0x10800000, 0x3064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_PERIC0_QCH", 0x10800000, 0x3068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI0_UART_QCH", 0x10800000, 0x306c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI14_USI_QCH", 0x10800000, 0x3070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI1_USI_QCH", 0x10800000, 0x3074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI2_USI_QCH", 0x10800000, 0x3078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI3_USI_QCH", 0x10800000, 0x307c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI4_USI_QCH", 0x10800000, 0x3080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI5_USI_QCH", 0x10800000, 0x3084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI6_USI_QCH", 0x10800000, 0x3088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI7_USI_QCH", 0x10800000, 0x308c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI8_USI_QCH", 0x10800000, 0x3090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C1_QCH_SCLK", 0x10800000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C2_QCH_SCLK", 0x10800000, 0x7004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C3_QCH_SCLK", 0x10800000, 0x7008, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C4_QCH_SCLK", 0x10800000, 0x700c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C5_QCH_SCLK", 0x10800000, 0x7010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C6_QCH_SCLK", 0x10800000, 0x7014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C7_QCH_SCLK", 0x10800000, 0x7018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C8_QCH_SCLK", 0x10800000, 0x701c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_PERIC0_QCH", 0x10800000, 0x702c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_PERIC0_QCH", 0x10800000, 0x7030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPIO_PERIC0_QCH", 0x10800000, 0x7034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C1_QCH_PCLK", 0x10800000, 0x7038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C2_QCH_PCLK", 0x10800000, 0x703c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C3_QCH_PCLK", 0x10800000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C4_QCH_PCLK", 0x10800000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C5_QCH_PCLK", 0x10800000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C6_QCH_PCLK", 0x10800000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C7_QCH_PCLK", 0x10800000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C8_QCH_PCLK", 0x10800000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC0_CU_QCH", 0x10800000, 0x7058, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC0_CU_QCH", 0x10800000, 0x705c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PERIC0_CMU_PERIC0_QCH", 0x10800000, 0x7060, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC0_QCH", 0x10800000, 0x7064, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_PERIC0_QCH", 0x10800000, 0x7068, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI0_UART_QCH", 0x10800000, 0x706c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI14_USI_QCH", 0x10800000, 0x7070, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI1_USI_QCH", 0x10800000, 0x7074, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI2_USI_QCH", 0x10800000, 0x7078, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI3_USI_QCH", 0x10800000, 0x707c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI4_USI_QCH", 0x10800000, 0x7080, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI5_USI_QCH", 0x10800000, 0x7084, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI6_USI_QCH", 0x10800000, 0x7088, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI7_USI_QCH", 0x10800000, 0x708c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI8_USI_QCH", 0x10800000, 0x7090, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "DMYQCH_CON_I3C0_QCH_SCLK", 0x10c00000, 0x3000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_D_TZPC_PERIC1_QCH", 0x10c00000, 0x3010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPC_PERIC1_QCH", 0x10c00000, 0x3014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_GPIO_PERIC1_QCH", 0x10c00000, 0x3018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_I3C0_QCH_PCLK", 0x10c00000, 0x301c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH", 0x10c00000, 0x3020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH", 0x10c00000, 0x3024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PERIC1_CMU_PERIC1_QCH", 0x10c00000, 0x3028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_PWM_QCH", 0x10c00000, 0x302c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SLH_AXI_MI_P_PERIC1_QCH", 0x10c00000, 0x3030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_SYSREG_PERIC1_QCH", 0x10c00000, 0x3034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI0_USI_QCH", 0x10c00000, 0x3038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI10_USI_QCH", 0x10c00000, 0x303c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI11_USI_QCH", 0x10c00000, 0x3040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI12_USI_QCH", 0x10c00000, 0x3044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI13_USI_QCH", 0x10c00000, 0x3048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI15_USI_QCH", 0x10c00000, 0x304c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI16_USI_QCH", 0x10c00000, 0x3050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "QCH_CON_USI9_USI_QCH", 0x10c00000, 0x3054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_DMYQCH_CON_I3C0_QCH_SCLK", 0x10c00000, 0x7000, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_D_TZPC_PERIC1_QCH", 0x10c00000, 0x7010, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPC_PERIC1_QCH", 0x10c00000, 0x7014, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_GPIO_PERIC1_QCH", 0x10c00000, 0x7018, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_I3C0_QCH_PCLK", 0x10c00000, 0x701c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_MI_P_PERIC1_CU_QCH", 0x10c00000, 0x7020, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_LH_AXI_SI_P_PERIC1_CU_QCH", 0x10c00000, 0x7024, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PERIC1_CMU_PERIC1_QCH", 0x10c00000, 0x7028, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_PWM_QCH", 0x10c00000, 0x702c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SLH_AXI_MI_P_PERIC1_QCH", 0x10c00000, 0x7030, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_SYSREG_PERIC1_QCH", 0x10c00000, 0x7034, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI0_USI_QCH", 0x10c00000, 0x7038, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI10_USI_QCH", 0x10c00000, 0x703c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI11_USI_QCH", 0x10c00000, 0x7040, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI12_USI_QCH", 0x10c00000, 0x7044, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI13_USI_QCH", 0x10c00000, 0x7048, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI15_USI_QCH", 0x10c00000, 0x704c, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI16_USI_QCH", 0x10c00000, 0x7050, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_READ, "DBG_NFO_QCH_CON_USI9_USI_QCH", 0x10c00000, 0x7054, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0", 0x18000000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0", 0x1e080000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL0_CMU_CPUCL0_CLKOUT0", 0x20c00000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0", 0x20c00000, 0x0814, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL1_CMU_CPUCL1_CLKOUT0", 0x20c10000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_CPUCL2_CMU_CPUCL2_CLKOUT0", 0x20c20000, 0x0810, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "CLKOUT_CON_BLK_HSI1_CMU_HSI1_CLKOUT0", 0x11800000, 0x0810, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20800000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20900000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20a00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MIF_CMU_MIF_CLKOUT0", 0x20b00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0", 0x10010000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0", 0x10800000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0", 0x10c00000, 0x0810, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "APM_CMU_APM_CONTROLLER_OPTION", 0x18000000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_CMU_TOP_CONTROLLER_OPTION", 0x1e080000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION", 0x20c00000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION", 0x20c00000, 0x0804, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION", 0x20c10000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION", 0x20c20000, 0x0800, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "HSI1_CMU_HSI1_CONTROLLER_OPTION", 0x11800000, 0x0800, 0xffffffff, 0, 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20800000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20900000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20a00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_CMU_MIF_CONTROLLER_OPTION", 0x20b00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MISC_CMU_MISC_CONTROLLER_OPTION", 0x10010000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PERIC0_CMU_PERIC0_CONTROLLER_OPTION", 0x10800000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "PERIC1_CMU_PERIC1_CONTROLLER_OPTION", 0x10c00000, 0x0800, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2104, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CMU_HCHGEN_CLKMUX", 0x1e080000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CPU", 0x20c00000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CPU_SW", 0x20c00000, 0x0848, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_HCHGEN_CLKMUX_CMUREF", 0x20c00000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CPU", 0x20c10000, 0x0854, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CPU_SW", 0x20c10000, 0x0858, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_HCHGEN_CLKMUX_CMUREF", 0x20c10000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CPU", 0x20c20000, 0x0854, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CPU_SW", 0x20c20000, 0x085c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_HCHGEN_CLKMUX_CMUREF", 0x20c20000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20800000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20900000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20a00000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_HCHGEN_CLKMUX_CMUREF", 0x20b00000, 0x0850, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP_SMPL_FLT", 0x20c00000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_SMPL_FLT", 0x20c10000, 0x083c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_SMPL_FLT", 0x20c20000, 0x083c, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_OCP_FLT", 0x20c10000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_OCP_FLT", 0x20c20000, 0x0834, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_VDROOP_FLT", 0x20c10000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_VDROOP_FLT", 0x20c20000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_CON_HEAVY", 0x20c10000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_CON_HEAVY", 0x20c20000, 0x0840, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP_CON_LIGHT", 0x20c10000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP_CON_LIGHT", 0x20c20000, 0x0844, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP_CON", 0x20c00000, 0x0838, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_CLKDIVSTEP", 0x20c00000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_CLKDIVSTEP", 0x20c10000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_CLKDIVSTEP", 0x20c20000, 0x0830, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_SHORTSTOP_DBG", 0x20c00000, 0x0824, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL0_SHORTSTOP", 0x20c00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL1_SHORTSTOP", 0x20c10000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CPUCL2_SHORTSTOP", 0x20c20000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "G3D_SHORTSTOP", 0x27f00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20800000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20900000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20a00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "MIF_SHORTSTOP", 0x20b00000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "TPU_SHORTSTOP", 0x1cc00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x2904, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_SAVE_RESTORE, "AUR_SHORTSTOP", 0x25a00000, 0x0820, (0x1 << 0), (0x1 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "NOCL0_SHORTSTOP", 0x1e000000, 0x0820, 0xffffffff, 0, 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_NOC", 0x1e080000, 0x1008, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_NOC", 0x1e080000, 0x180c, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_MUX_MUX_CLKCMU_AUR_AURCTL", 0x1e080000, + 0x1004, (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_SAVE_RESTORE, "CLK_CON_DIV_CLKCMU_AUR_AURCTL", 0x1e080000, 0x1808, + (0xffffffff << 0), (0x0 << 0), 0x18060000, 0x2984, (0x1 << 0), (0x1 << 0)), +}; +struct pmucal_seq exit_sleep_slcmon[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0208, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20840000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20940000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20a40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20b40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x18020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1e820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1f020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT0_DRCG_EN", 0x1e020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT1_DRCG_EN", 0x1e020000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20c40000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN_INT", 0x20c40000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x27f20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x11820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x14420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20920000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20a20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20b20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10c20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10030000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MISC", 0x14700000, 0x11b4, (0x1 << 8), (0x1 << 8), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0x7 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0x9 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xb << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xc << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xd << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_SET_BIT_ATOMIC, "TOP_OUT", 0x18060000, 0x3920, (0xffffffff << 0), (0xe << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TREX_D_NOCL1A", 0x20510000, 0x2000, (0xffffffff << 0), (0xf000 << 0), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq early_sleep_slcmon[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SYSTEM_CTRL", 0x18060000, 0x3a10, (0x1 << 14), (0x0 << 14), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP4_INTR_BID_CLEAR", 0x18070000, 0x040c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0408, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), +}; + +struct pmucal_seq enter_stop[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x1 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x1 << 3), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq save_stop[] = { +}; +struct pmucal_seq exit_stop[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP2_INTR_BID_CLEAR", 0x18070000, 0x020c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0208, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20840000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20940000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20a40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "PWRMGMT_BUNDLE_PwrMgmtMode", 0x20b40000, 0xf23c, (0x1 << 31), (0x0 << 31), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x18020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1b04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1e820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x1f020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1a84, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT0_DRCG_EN", 0x1e020000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT1_DRCG_EN", 0x1e020000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20c40000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN_INT", 0x20c40000, 0x010c, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_COND_WRITE, "BUS_COMPONENT_DRCG_EN", 0x27f20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0x18060000, 0x1e04, (0x1 << 0), (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x11820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x14420000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20920000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20a20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x20b20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10820000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10c20000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "BUS_COMPONENT_DRCG_EN", 0x10030000, 0x0104, (0xffffffff << 0), (0xffffffff << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "MISC", 0x14700000, 0x11b4, (0x1 << 8), (0x1 << 8), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "TREX_D_NOCL1A", 0x20510000, 0x2000, (0xffffffff << 0), (0xf000 << 0), 0, 0, 0xffffffff, 0), +}; +struct pmucal_seq early_stop[] = { + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP_INT_EN", 0x18060000, 0x3944, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "WAKEUP2_INT_EN", 0x18060000, 0x3964, (0xffffffff << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP27_INTR_BID_CLEAR", 0x18070000, 0x1b0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1b08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP31_INTR_BID_CLEAR", 0x18070000, 0x1f0c, (0xffffffff << 0), (0xffffffff << 0), 0x18070000, 0x1f08, (0xffffffff << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "GRP2_INTR_BID_ENABLE", 0x18070000, 0x0200, (0x1 << 0), (0x0 << 0), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP1_INTR_BID_CLEAR", 0x18070000, 0x010c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0108, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "CLUSTER0_CPU0_INT_EN", 0x18060000, 0x1044, (0x1 << 3), (0x0 << 3), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_WRITE, "SYSTEM_CTRL", 0x18060000, 0x3a10, (0x1 << 14), (0x0 << 14), 0, 0, 0xffffffff, 0), + PMUCAL_SEQ_DESC(PMUCAL_CLEAR_PEND, "GRP4_INTR_BID_CLEAR", 0x18070000, 0x040c, (0x1 << 0), (0x1 << 0), 0x18070000, 0x0408, (0x1 << 0), (0x1 << 0) | (0x1 << 0)), +}; +/* global array for supported low power modes - exposed to common logic */ +struct pmucal_lpm pmucal_lpm_list[NUM_SYS_POWERDOWN] = { + [SYS_SICD] = { + .id = SYS_SICD, + .enter = enter_sicd, + .save = save_sicd, + .exit = exit_sicd, + .early_wakeup = early_sicd, + .num_enter = ARRAY_SIZE(enter_sicd), + .num_save = ARRAY_SIZE(save_sicd), + .num_exit = ARRAY_SIZE(exit_sicd), + .num_early_wakeup = ARRAY_SIZE(early_sicd), + }, + [SYS_SLEEP] = { + .id = SYS_SLEEP, + .enter = enter_sleep, + .save = save_sleep, + .exit = exit_sleep, + .early_wakeup = early_sleep, + .num_enter = ARRAY_SIZE(enter_sleep), + .num_save = ARRAY_SIZE(save_sleep), + .num_exit = ARRAY_SIZE(exit_sleep), + .num_early_wakeup = ARRAY_SIZE(early_sleep), + }, + [SYS_SLEEP_SLCMON] = { + .id = SYS_SLEEP_SLCMON, + .enter = enter_sleep_slcmon, + .save = save_sleep_slcmon, + .exit = exit_sleep_slcmon, + .early_wakeup = early_sleep_slcmon, + .num_enter = ARRAY_SIZE(enter_sleep_slcmon), + .num_save = ARRAY_SIZE(save_sleep_slcmon), + .num_exit = ARRAY_SIZE(exit_sleep_slcmon), + .num_early_wakeup = ARRAY_SIZE(early_sleep_slcmon), + }, + [SYS_SLEEP_HSI1ON] = { + /* + * Same sequence as SLCMON + */ + .id = SYS_SLEEP_SLCMON, + .enter = enter_sleep_slcmon, + .save = save_sleep_slcmon, + .exit = exit_sleep_slcmon, + .early_wakeup = early_sleep_slcmon, + .num_enter = ARRAY_SIZE(enter_sleep_slcmon), + .num_save = ARRAY_SIZE(save_sleep_slcmon), + .num_exit = ARRAY_SIZE(exit_sleep_slcmon), + .num_early_wakeup = ARRAY_SIZE(early_sleep_slcmon), + }, + [SYS_STOP] = { + .id = SYS_STOP, + .enter = enter_stop, + .save = save_stop, + .exit = exit_stop, + .early_wakeup = early_stop, + .num_enter = ARRAY_SIZE(enter_stop), + .num_save = ARRAY_SIZE(save_stop), + .num_exit = ARRAY_SIZE(exit_stop), + .num_early_wakeup = ARRAY_SIZE(early_stop), + }, +}; +unsigned int pmucal_lpm_list_size = ARRAY_SIZE(pmucal_lpm_list); +#else +/* common sequence descriptor for apm pmu init. - exposed to common logic */ +struct pmucal_seq pmucal_apm_pmu_init[] = { +}; +unsigned int pmucal_apm_pmu_init_size = ARRAY_SIZE(pmucal_apm_pmu_init); +struct pmucal_seq soc_sequencer_sicd_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sicd_down", 0, 0, 0x0, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_sicd_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sicd_up", 0, 0, 0x1, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_sleep_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sleep_down", 0, 0, 0x2, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_sleep_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sleep_up", 0, 0, 0x3, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_sleep_slcmon_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sleep_down", 0, 0, 0x4, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_sleep_slcmon_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_sleep_up", 0, 0, 0x5, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_stop_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "soc_stop_down", 0, 0, 0x6, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq soc_sequencer_stop_up[] = { +}; + +struct pmucal_seq mif_sequencer_sicd_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sicd_down", 0, 0, 0x10, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_sicd_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sicd_up", 0, 0, 0x11, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_sleep_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sleep_down", 0, 0, 0x12, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_sleep_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sleep_up", 0, 0, 0x13, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_sleep_slcmon_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sleep_down", 0, 0, 0x14, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_sleep_slcmon_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_sleep_up", 0, 0, 0x15, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_stop_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "smc_stop_down", 0, 0, 0x16, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq mif_sequencer_stop_up[] = { +}; + +struct pmucal_seq slc_sequencer_sicd_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sicd_down", 0, 0, 0x17, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_sicd_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sicd_up", 0, 0, 0x18, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_sleep_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sleep_down", 0, 0, 0x19, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_sleep_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sleep_up", 0, 0, 0x1A, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_sleep_slcmon_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sleep_slcmon_down", 0, 0, 0x1B, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_sleep_slcmon_up[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_sleep_slcmon_up", 0, 0, 0x1C, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_stop_down[] = { + PMUCAL_SEQ_DESC(PMUCAL_EXT_FUNC, "mif_stop_down", 0, 0, 0x1D, 0x0, 0, 0, 0, 0), +}; + +struct pmucal_seq slc_sequencer_stop_up[] = { +}; + +enum sys_powermode { + SYS_SICD, + SYS_SLEEP, + SYS_SLEEP_SLCMON, + SYS_STOP, + NUM_SYS_POWERMODE, +}; + +struct pmucal_system_sequencer pmucal_system_apsoc_list[NUM_SYS_POWERMODE] = { + [SYS_SICD] = { + .id = SYS_SICD, + .up = soc_sequencer_sicd_up, + .down = soc_sequencer_sicd_down, + .num_up = ARRAY_SIZE(soc_sequencer_sicd_up), + .num_down = ARRAY_SIZE(soc_sequencer_sicd_down), + }, + [SYS_SLEEP] = { + .id = SYS_SLEEP, + .up = soc_sequencer_sleep_up, + .down = soc_sequencer_sleep_down, + .num_up = ARRAY_SIZE(soc_sequencer_sleep_up), + .num_down = ARRAY_SIZE(soc_sequencer_sleep_down), + }, + [SYS_SLEEP_SLCMON] = { + .id = SYS_SLEEP_SLCMON, + .up = soc_sequencer_sleep_slcmon_up, + .down = soc_sequencer_sleep_slcmon_down, + .num_up = ARRAY_SIZE(soc_sequencer_sleep_slcmon_up), + .num_down = ARRAY_SIZE(soc_sequencer_sleep_slcmon_down), + }, + [SYS_STOP] = { + .id = SYS_STOP, + .up = soc_sequencer_stop_up, + .down = soc_sequencer_stop_down, + .num_up = ARRAY_SIZE(soc_sequencer_stop_up), + .num_down = ARRAY_SIZE(soc_sequencer_stop_down), + }, +}; + +struct pmucal_system_sequencer pmucal_system_mif_list[NUM_SYS_POWERMODE] = { + [SYS_SICD] = { + .id = SYS_SICD, + .up = mif_sequencer_sicd_up, + .down = mif_sequencer_sicd_down, + .num_up = ARRAY_SIZE(mif_sequencer_sicd_up), + .num_down = ARRAY_SIZE(mif_sequencer_sicd_down), + }, + [SYS_SLEEP] = { + .id = SYS_SLEEP, + .up = mif_sequencer_sleep_up, + .down = mif_sequencer_sleep_down, + .num_up = ARRAY_SIZE(mif_sequencer_sleep_up), + .num_down = ARRAY_SIZE(mif_sequencer_sleep_down), + }, + [SYS_SLEEP_SLCMON] = { + .id = SYS_SLEEP_SLCMON, + .up = mif_sequencer_sleep_slcmon_up, + .down = mif_sequencer_sleep_slcmon_down, + .num_up = ARRAY_SIZE(mif_sequencer_sleep_slcmon_up), + .num_down = ARRAY_SIZE(mif_sequencer_sleep_slcmon_down), + }, + [SYS_STOP] = { + .id = SYS_STOP, + .up = mif_sequencer_stop_up, + .down = mif_sequencer_stop_down, + .num_up = ARRAY_SIZE(mif_sequencer_stop_up), + .num_down = ARRAY_SIZE(mif_sequencer_stop_down), + }, +}; + +struct pmucal_system_sequencer pmucal_system_slc_list[NUM_SYS_POWERMODE] = { + [SYS_SICD] = { + .id = SYS_SICD, + .up = slc_sequencer_sicd_up, + .down = slc_sequencer_sicd_down, + .num_up = ARRAY_SIZE(slc_sequencer_sicd_up), + .num_down = ARRAY_SIZE(slc_sequencer_sicd_down), + }, + [SYS_SLEEP] = { + .id = SYS_SLEEP, + .up = slc_sequencer_sleep_up, + .down = slc_sequencer_sleep_down, + .num_up = ARRAY_SIZE(slc_sequencer_sleep_up), + .num_down = ARRAY_SIZE(slc_sequencer_sleep_down), + }, + [SYS_SLEEP_SLCMON] = { + .id = SYS_SLEEP_SLCMON, + .up = slc_sequencer_sleep_slcmon_up, + .down = slc_sequencer_sleep_slcmon_down, + .num_up = ARRAY_SIZE(slc_sequencer_sleep_slcmon_up), + .num_down = ARRAY_SIZE(slc_sequencer_sleep_slcmon_down), + }, + [SYS_STOP] = { + .id = SYS_STOP, + .up = slc_sequencer_stop_up, + .down = slc_sequencer_stop_down, + .num_up = ARRAY_SIZE(slc_sequencer_stop_up), + .num_down = ARRAY_SIZE(slc_sequencer_stop_down), + }, +}; + +unsigned int pmucal_system_sequencer_list_size = NUM_SYS_POWERMODE; +#endif diff --git a/drivers/soc/google/cal-if/pmucal_local.h b/drivers/soc/google/cal-if/pmucal_local.h index c49ef9d608aa..f9f16e71f3ea 100644 --- a/drivers/soc/google/cal-if/pmucal_local.h +++ b/drivers/soc/google/cal-if/pmucal_local.h @@ -6,7 +6,7 @@ /* Number of MAX_POWER_DOMAIN */ #if defined(CONFIG_SOC_EXYNOS9820) #define PMUCAL_NUM_PDS 20 -#elif defined(CONFIG_SOC_GS101) +#elif defined(CONFIG_SOC_GS101) || defined(CONFIG_SOC_GS201) #define PMUCAL_NUM_PDS 30 #else #error "Unknown CONFIG_SOC" diff --git a/drivers/soc/google/cal-if/pmucal_rae.c b/drivers/soc/google/cal-if/pmucal_rae.c index 75d7d3fca3cb..69e6d5959378 100644 --- a/drivers/soc/google/cal-if/pmucal_rae.c +++ b/drivers/soc/google/cal-if/pmucal_rae.c @@ -116,7 +116,7 @@ static int pmucal_rae_wait(struct pmucal_seq *seq, unsigned int idx) break; timeout++; udelay(1); - if (timeout > 2000) { + if (timeout > 5000) { u32 reg; reg = readl(seq->base_va + seq->offset); @@ -139,7 +139,9 @@ static inline void pmucal_rae_read(struct pmucal_seq *seq) static void pmucal_write_reg(phys_addr_t base_pa, void __iomem *base_va, u32 offset, u32 val) { - if ((base_pa >> 16) == 0x1746) + /* TODO: we should get the base address prefix from device tree instead + of hardcoding here. */ + if (((base_pa >> 16) == 0x1746) || ((base_pa >> 16) == 0x1806)) set_priv_reg(base_pa + offset, val); else writel(val, base_va + offset); diff --git a/drivers/soc/google/cal-if/pmucal_system.h b/drivers/soc/google/cal-if/pmucal_system.h index 7eccbf65243b..5f0469b02255 100644 --- a/drivers/soc/google/cal-if/pmucal_system.h +++ b/drivers/soc/google/cal-if/pmucal_system.h @@ -34,7 +34,7 @@ enum sys_powerdown { SYS_FAPO, SYS_SLEEP_USBL2, SYS_SLEEP_HSI1ON, -#if defined(CONFIG_SOC_GS101) +#if defined(CONFIG_SOC_GS101) || defined(CONFIG_SOC_GS201) SYS_SLEEP_SLCMON, #endif NUM_SYS_POWERDOWN, diff --git a/drivers/soc/google/cpif/Kconfig b/drivers/soc/google/cpif/Kconfig index 893e1d2d231e..1206bd81dded 100644 --- a/drivers/soc/google/cpif/Kconfig +++ b/drivers/soc/google/cpif/Kconfig @@ -14,12 +14,14 @@ config SEC_MODEM_S5000AP select MCU_IPC select SHM_IPC select CP_PMUCAL + select CPIF_PAGE_RECYCLING default n config SEC_MODEM_S5100 tristate "Exynos S51xx" select BOOT_DEVICE_SPI select LINK_DEVICE_PCIE + select CPIF_PAGE_RECYCLING default n menu "Configuration Description" @@ -47,10 +49,6 @@ config LINK_DEVICE_WITH_SBD_ARCH tristate "Link device with the SBD architecture from MIPI-LLI" default n -config CP_ZEROCOPY - tristate "Support zero memory copy" - default n - config CP_PKTPROC tristate "Support packet processor" default n @@ -71,10 +69,6 @@ config LINK_DEVICE_PCIE tristate "modem driver link device PCIe" default n -config LINK_CONTROL_MSG_IOSM - tristate "Control Message Type: IPC Over Shared Memory (IOSM)" - default n - config CP_SECURE_BOOT tristate "Support CP Secure Boot" default n @@ -101,40 +95,44 @@ config HW_REV_DETECT default n config MODEM_IF_QOS - tristate "Implement QoS for sbd" + tristate "Implement QoS" default n help - This enables QoS for SBD model + This enables QoS config MODEM_IF_LEGACY_QOS tristate "Implement QoS for legacy buffer" + select MODEM_IF_QOS default n help This enables QoS for legacy buffer model config SUSPEND_DURING_VOICE_CALL - tristate "control wake_lock by voice call start/end notification" + bool "control wake_lock by voice call start/end notification" depends on LINK_DEVICE_PCIE default n help This enables AP suspend during PCM over PCIE -config CACHED_LEGACY_RAW_RX_BUFFER - tristate "Set cached RX RAW buffer for high data performance" - default n - config CPIF_TP_MONITOR tristate "Support CP network throughput monitor" default n help This enables CP network throughput monitor -config LINK_DEVICE_PCIE_S2MPU - tristate "Use PCIE S2MPU" +config LINK_DEVICE_PCIE_IOCC + bool "Use PCIE IOCC" depends on LINK_DEVICE_PCIE default n help - Gate some addresses AP and CP shared + This enables PCIe IOCC + +config LINK_DEVICE_PCIE_IOMMU + bool "Use PCIE IOMMU" + depends on LINK_DEVICE_PCIE && EXYNOS_PCIE_IOMMU + default n + help + This enables PCIe IOMMU config CPIF_CHECK_SJTAG_STATUS tristate "Check secure JTAG status to disable CP memory dump" @@ -149,31 +147,37 @@ config CP_LCD_NOTIFIER This enables LCD notifier for CP config LINK_DEVICE_PCIE_GPIO_WA - tristate "Workaround for discarded GPIOs" + bool "Workaround for discarded GPIOs" depends on LINK_DEVICE_PCIE default n help Use a GPIO for the other purpose instead +config CP_WRESET_WA + bool "CP warm reset WA due to WRSTBI disabled" + depends on LINK_DEVICE_PCIE + default n + help + CP warm reset WA + config EXYNOS_DIT tristate "Enable DIT" default n help Enable DIT (Direct Internet Packet Transfer) -config CP_WRESET_WA - tristate "CP warm reset WA due to WRSTBI disabled" - depends on LINK_DEVICE_PCIE - default n - help - CP warm reset WA +config EXYNOS_DIT_VERSION + hex "DIT version" + depends on EXYNOS_DIT + default 0x02010000 + help + DIT version -config CP_THERMAL - tristate "Enable CP thermal zones" - depends on THERMAL - help - Enables support for reporting CP temperature sensor data to kernel thermal - framework. +config CPIF_DIRECT_DM + tristate "Enable direct dm path" + default n + help + This enables direct dm path config CH_EXTENSION tristate "Enable Channel Extension" @@ -181,5 +185,36 @@ config CH_EXTENSION help Enable Channel Extension +config CPIF_VENDOR_HOOK + tristate "Enable Android vendor hook" + default n + help + This enables Android vendor hook + +config CPIF_PAGE_RECYCLING + tristate "Enable page recycling" + default n + help + This enables page recycling to improve alloc overhead + +config CP_PKTPROC_CLAT + tristate "Enable HW PKTPROC CLAT" + default n + help + Enable HW pktproc clat + +config CP_PKTPROC_LRO + tristate "Enable HW PKTPROC LRO" + default n + help + Enable HW pktproc LRO + +config CP_THERMAL + tristate "Enable CP thermal zones" + depends on THERMAL + help + Enables support for reporting CP temperature sensor data to kernel thermal + framework. + endmenu endif diff --git a/drivers/soc/google/cpif/Makefile b/drivers/soc/google/cpif/Makefile index f9a473fff9c3..5375221dd3e9 100644 --- a/drivers/soc/google/cpif/Makefile +++ b/drivers/soc/google/cpif/Makefile @@ -1,44 +1,48 @@ # SPDX-License-Identifier: GPL-2.0 # Makefile of cpif -EXTRA_CFLAGS += -Idrivers/soc/samsung/cpif \ - -DCONFIG_OPTION_REGION=\"$(PROJECT_REGION)\" +ccflags-y += -Wformat +ccflags-y += -Wformat-zero-length +ccflags-y += -DCONFIG_OPTION_REGION=\"$(PROJECT_REGION)\" +subdir-ccflags-y += -I$(srctree)/$(src) obj-$(CONFIG_MCU_IPC) += mcu_ipc.o obj-$(CONFIG_SHM_IPC) += shm_ipc.o obj-$(CONFIG_BOOT_DEVICE_SPI) += boot_device_spi.o -obj-$(CONFIG_EXYNOS_DIT) += exynos_dit.o -exynos_dit-y += dit.o dit_net.o dit_hal.o +obj-$(CONFIG_EXYNOS_DIT) += dit/ + +obj-$(CONFIG_CPIF_PAGE_RECYCLING) += cpif_page.o + +obj-$(CONFIG_CPIF_DIRECT_DM) += direct_dm.o + +obj-$(CONFIG_CPIF_VENDOR_HOOK) += hook.o obj-$(CONFIG_EXYNOS_MODEM_IF) += cpif.o cpif-y += modem_main.o modem_variation.o -cpif-y += modem_io_device.o net_io_device.o bootdump_io_device.o ipc_io_device.o +cpif-y += modem_io_device.o net_io_device.o bootdump_io_device.o ipc_io_device.o modem_toe_device.o cpif-y += modem_utils.o modem_dump.o - cpif-y += link_device.o link_device_memory_flow_control.o cpif-y += link_device_memory_debug.o modem_notifier.o -cpif-y += link_device_memory_snapshot.o link_device_memory_sbd.o link_device_memory_legacy.o +cpif-y += link_device_memory_snapshot.o link_device_memory_legacy.o + +cpif-$(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) += link_device_memory_sbd.o + +cpif-$(CONFIG_EXYNOS_CPIF_IOMMU) += cpif_netrx_mng.o cpif_vmapper.o cpif-$(CONFIG_LINK_DEVICE_PCIE) += s51xx_pcie.o +cpif-$(CONFIG_LINK_DEVICE_PCIE_IOMMU) += link_device_pcie_iommu.o cpif-$(CONFIG_SEC_MODEM_S5000AP) += modem_ctrl_s5000ap.o modem_ctrl.o cpif-$(CONFIG_SEC_MODEM_S5100) += modem_ctrl_s5100.o modem_ctrl.o -cpif-$(CONFIG_CP_ZEROCOPY) += link_rx_zerocopy.o cpif-$(CONFIG_CP_PKTPROC) += link_rx_pktproc.o cpif-$(CONFIG_CP_PKTPROC_UL) += link_tx_pktproc.o -cpif-$(CONFIG_LINK_CONTROL_MSG_IOSM) += link_ctrlmsg_iosm.o - cpif-$(CONFIG_CP_BTL) += cp_btl.o cpif-$(CONFIG_CPIF_TP_MONITOR) += cpif_tp_monitor.o cpif-$(CONFIG_MODEM_IF_LEGACY_QOS) += cpif_qos_info.o -ifeq ($(CONFIG_RPS), y) -cpif-$(CONFIG_ARGOS) += modem_argos_notifier.o -endif - obj-$(CONFIG_CP_THERMAL) += cp_thermal_zone.o diff --git a/drivers/soc/google/cpif/boot_device_spi.c b/drivers/soc/google/cpif/boot_device_spi.c index 27473e67bd35..34ea1693896d 100644 --- a/drivers/soc/google/cpif/boot_device_spi.c +++ b/drivers/soc/google/cpif/boot_device_spi.c @@ -26,13 +26,13 @@ int cpboot_spi_load_cp_image(struct link_device *ld, struct io_device *iod, unsi { int ret = 0; struct mem_link_device *mld = ld_to_mem_link_device(ld); - struct cpboot_spi *cpboot = mld->boot_spi; + struct cpboot_spi *cpboot = cpboot_spi_get_device(mld->spi_bus_num); struct cp_image img; char *buff = NULL; struct spi_message msg; struct spi_transfer xfer; - if (!cpboot->spi) { + if (!cpboot || !cpboot->spi) { mif_err("spi is null\n"); return -EPERM; } @@ -118,7 +118,8 @@ static int cpboot_spi_probe(struct spi_device *spi) if (_count >= MAX_SPI_DEVICE) { mif_err("_count is over %d\n", MAX_SPI_DEVICE); - return -EINVAL; + ret = -EINVAL; + goto err; } mutex_init(&_cpboot[_count].lock); @@ -138,6 +139,8 @@ static int cpboot_spi_probe(struct spi_device *spi) err_setup: mutex_destroy(&_cpboot[_count].lock); +err: + panic("CP SPI driver probe failed\n"); return ret; } diff --git a/drivers/soc/google/cpif/bootdump_io_device.c b/drivers/soc/google/cpif/bootdump_io_device.c index 09a8ea153e24..4d77d3f8b38c 100644 --- a/drivers/soc/google/cpif/bootdump_io_device.c +++ b/drivers/soc/google/cpif/bootdump_io_device.c @@ -101,52 +101,30 @@ static unsigned int bootdump_poll(struct file *filp, struct poll_table_struct *w switch (mc->phone_state) { case STATE_BOOTING: case STATE_ONLINE: - if (!mc->sim_state.changed) { - if (!skb_queue_empty(rxq)) - return POLLIN | POLLRDNORM; - else /* wq is waken up without rx, return for wait */ - return 0; - } - /* fall through, if sim_state has been changed */ + if (!skb_queue_empty(rxq)) + return POLLIN | POLLRDNORM; + break; case STATE_CRASH_EXIT: case STATE_CRASH_RESET: case STATE_NV_REBUILDING: case STATE_CRASH_WATCHDOG: - /* report crash only if iod is fmt/boot device */ - if (iod->format == IPC_FMT) { - mif_err_limited("FMT %s: %s.state == %s\n", - iod->name, mc->name, mc_state(mc)); - return POLLHUP; - } else if (iod->format == IPC_BOOT || ld->is_boot_ch(iod->ch)) { + if (iod->format == IPC_BOOT || ld->is_boot_ch(iod->ch) || + iod->format == IPC_DUMP || ld->is_dump_ch(iod->ch)) { if (!skb_queue_empty(rxq)) return POLLIN | POLLRDNORM; + } - mif_err_limited("BOOT %s: %s.state == %s\n", - iod->name, mc->name, mc_state(mc)); - return POLLHUP; - } else if (iod->format == IPC_DUMP || ld->is_dump_ch(iod->ch)) { - if (!skb_queue_empty(rxq)) - return POLLIN | POLLRDNORM; + mif_err_limited("%s: %s.state == %s\n", iod->name, mc->name, mc_state(mc)); - mif_err_limited("DUMP %s: %s.state == %s\n", - iod->name, mc->name, mc_state(mc)); - } else { - mif_err_limited("%s: %s.state == %s\n", - iod->name, mc->name, mc_state(mc)); - - /* give delay to prevent infinite sys_poll call from - * select() in APP layer without 'sleep' user call takes - * almost 100% cpu usage when it is looked up by 'top' - * command. - */ - msleep(20); - } + if (iod->format == IPC_BOOT || ld->is_boot_ch(iod->ch)) + return POLLHUP; break; + case STATE_RESET: + mif_err_limited("%s: %s.state == %s\n", iod->name, mc->name, mc_state(mc)); - case STATE_OFFLINE: - if (ld->protocol == PROTOCOL_SIT) + if (iod->attrs & IO_ATTR_STATE_RESET_NOTI) return POLLHUP; - /* fall through */ + break; default: break; } @@ -162,6 +140,7 @@ static long bootdump_ioctl(struct file *filp, unsigned int cmd, unsigned long ar enum modem_state p_state; struct cpif_version version; int ret = 0; + struct mem_link_device *mld; switch (cmd) { case IOCTL_POWER_ON: @@ -220,9 +199,6 @@ static long bootdump_ioctl(struct file *filp, unsigned int cmd, unsigned long ar return -EINVAL; } - if (ld->reset_zerocopy) - ld->reset_zerocopy(ld); - return ret; } @@ -305,15 +281,17 @@ static long bootdump_ioctl(struct file *filp, unsigned int cmd, unsigned long ar iod->name, cp_state_str(p_state)); } - if (mc->sim_state.changed) { - enum modem_state s_state = mc->sim_state.online ? - STATE_SIM_ATTACH : STATE_SIM_DETACH; - mc->sim_state.changed = false; - return s_state; - } - - if (p_state == STATE_NV_REBUILDING) + switch (p_state) { + case STATE_NV_REBUILDING: mc->phone_state = STATE_ONLINE; + break; + /* Do not return an internal state */ + case STATE_RESET: + p_state = STATE_OFFLINE; + break; + default: + break; + } return p_state; @@ -408,6 +386,24 @@ static long bootdump_ioctl(struct file *filp, unsigned int cmd, unsigned long ar mif_info("%s: IOCTL_HANDOVER_BLOCK_INFO\n", iod->name); return ld->handover_block_info(ld, arg); + case IOCTL_SET_SPI_BOOT_MODE: + mld = to_mem_link_device(ld); + if (!mld) { + mif_err("%s: mld is null\n", iod->name); + return -EINVAL; + } + if (mld->spi_bus_num < 0) { + mif_err("invalid cpboot_spi_bus_num\n"); + return -ENODEV; + } + mld->attrs |= LINK_ATTR_XMIT_BTDLR_SPI; + mld->attrs &= (~LINK_ATTR_XMIT_BTDLR_PCIE); + + ld->load_cp_image = cpboot_spi_load_cp_image; + + mif_info("%s: IOCTL_SET_SPI_BOOT_MODE\n", iod->name); + return 0; + default: /* If you need to handle the ioctl for specific link device, * then assign the link ioctl handler to ld->ioctl @@ -442,14 +438,10 @@ static ssize_t bootdump_write(struct file *filp, const char __user *data, unsigned int alloc_size; /* 64bit prevent */ unsigned int cnt = (unsigned int)count; -#ifdef DEBUG_MODEM_IF struct timespec64 ts; -#endif -#ifdef DEBUG_MODEM_IF /* Record the timestamp */ ktime_get_ts64(&ts); -#endif if (iod->format <= IPC_RFS && iod->ch == 0) return -EINVAL; @@ -482,8 +474,13 @@ static ssize_t bootdump_write(struct file *filp, const char __user *data, while (copied < cnt) { remains = cnt - copied; - alloc_size = min_t(unsigned int, remains + headroom, - iod->max_tx_size ?: remains + headroom); + + if (check_add_overflow(remains, headroom, &alloc_size)) + alloc_size = SZ_2K; + + if (iod->max_tx_size) + alloc_size = min_t(unsigned int, alloc_size, + iod->max_tx_size); /* Calculate tailroom for padding size */ if (iod->link_header && ld->aligned) @@ -526,10 +523,8 @@ static ssize_t bootdump_write(struct file *filp, const char __user *data, skbpriv(skb)->lnk_hdr = iod->link_header; skbpriv(skb)->sipc_ch = iod->ch; -#ifdef DEBUG_MODEM_IF /* Copy the timestamp to the skb */ skbpriv(skb)->ts = ts; -#endif #ifdef DEBUG_MODEM_IF_IODEV_TX mif_pkt(iod->ch, "IOD-TX", skb); #endif diff --git a/drivers/soc/google/cpif/cp_btl.c b/drivers/soc/google/cpif/cp_btl.c index f642d282d158..da91ec6f1f31 100644 --- a/drivers/soc/google/cpif/cp_btl.c +++ b/drivers/soc/google/cpif/cp_btl.c @@ -21,6 +21,7 @@ #include #include "modem_utils.h" +#include "modem_ctrl.h" #include "cp_btl.h" #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) #include "s51xx_pcie.h" @@ -31,6 +32,8 @@ #define BTL_MAP_SIZE SZ_1M /* per PCI BAR2 limit */ #endif +#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10)) + /* fops */ static int btl_open(struct inode *inode, struct file *filep) { @@ -281,6 +284,7 @@ int cp_btl_create(struct cp_btl *btl, struct device *dev) { struct modem_data *pdata = NULL; int ret = 0; + struct sysinfo s; if (!dev) { mif_err("dev is null\n"); @@ -300,6 +304,11 @@ int cp_btl_create(struct cp_btl *btl, struct device *dev) atomic_set(&btl->active, 0); mif_dt_read_string(dev->of_node, "cp_btl_node_name", btl->name); + mif_dt_read_u32_noerr(dev->of_node, "cp_btl_support_extension", btl->support_extension); + mif_dt_read_u32_noerr(dev->of_node, "cp_btl_extension_dram_size", btl->extension_dram_size); + + if (btl->support_extension) + btl->extension_enabled = true; btl->id = pdata->cp_num; if (btl->id >= MAX_BTL_ID) { @@ -318,16 +327,33 @@ int cp_btl_create(struct cp_btl *btl, struct device *dev) mif_info("name:%s id:%d link:%d\n", btl->name, btl->id, btl->link_type); switch (btl->link_type) { case LINKDEV_SHMEM: - btl->mem.v_base = cp_shmem_get_region(btl->id, SHMEM_BTL); + btl->mem.size = cp_shmem_get_size(btl->id, SHMEM_BTL); + + if (btl->support_extension) { + si_meminfo(&s); + mif_info("total mem (%ld kb)\n", convert_to_kb(s.totalram)); + /* DRAM size: over 8GB -> BTL size: 64MB */ + /* DRAM size: under 8GB -> BTL size: 32MB */ + if (convert_to_kb(s.totalram) > btl->extension_dram_size) { + btl->mem.size += cp_shmem_get_size(btl->id, SHMEM_BTL_EXT); + } else { + cp_shmem_release_rmem(btl->id, SHMEM_BTL_EXT, 0); + btl->extension_enabled = false; + } + } + + /* TODO: cached */ + btl->mem.v_base = cp_shmem_get_nc_region(cp_shmem_get_base(btl->id, SHMEM_BTL), + btl->mem.size); if (!btl->mem.v_base) { mif_err("cp_shmem_get_region() error:v_base\n"); ret = -ENOMEM; goto create_exit; } - btl->mem.size = cp_shmem_get_size(btl->id, SHMEM_BTL); /* BAAW */ exynos_smc(SMC_ID_CLK, SSS_CLK_ENABLE, 0, 0); + ret = (int)exynos_smc(SMC_ID, CP_BOOT_REQ_CP_RAM_LOGGING, 0, 0); if (ret) { mif_err("exynos_smc() error:%d\n", ret); @@ -371,9 +397,9 @@ int cp_btl_create(struct cp_btl *btl, struct device *dev) if (btl->mem.v_base) vunmap(btl->mem.v_base); -#if !IS_ENABLED(CONFIG_SOC_EXYNOS9820) - cp_shmem_release_rmem(btl->id, SHMEM_BTL); -#endif + cp_shmem_release_rmem(btl->id, SHMEM_BTL, 0); + if (btl->extension_enabled) + cp_shmem_release_rmem(btl->id, SHMEM_BTL_EXT, 0); return ret; } diff --git a/drivers/soc/google/cpif/cp_btl.h b/drivers/soc/google/cpif/cp_btl.h index 3fdf1731518b..09593d694514 100644 --- a/drivers/soc/google/cpif/cp_btl.h +++ b/drivers/soc/google/cpif/cp_btl.h @@ -35,6 +35,10 @@ struct cp_btl { struct mem_link_device *mld; struct miscdevice miscdev; + + bool support_extension; + u32 extension_dram_size; + bool extension_enabled; }; #if IS_ENABLED(CONFIG_CP_BTL) diff --git a/drivers/soc/google/cpif/cpif_netrx_mng.c b/drivers/soc/google/cpif/cpif_netrx_mng.c new file mode 100644 index 000000000000..2657345090ac --- /dev/null +++ b/drivers/soc/google/cpif/cpif_netrx_mng.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#include +#include +#include +#include + +#include "cpif_netrx_mng.h" + +#define NETRX_POOL_PAGE_SIZE 32768 +struct cpif_netrx_mng *cpif_create_netrx_mng(struct cpif_addr_pair *desc_addr_pair, + u64 desc_size, u64 databuf_cp_pbase, + u64 frag_size, u64 num_packet) +{ + struct cpif_netrx_mng *cm; + u64 temp; + u64 num_packet_per_page; + u64 total_page_count; + + if (!desc_addr_pair) { + mif_err("desc addr pair not given\n"); + return NULL; + } + + cm = kvzalloc(sizeof(struct cpif_netrx_mng), GFP_KERNEL); + if (cm == NULL) + goto fail_cm; + + cm->frag_size = frag_size; + cm->num_packet = num_packet; + + /* finding the least number of pages required for data map */ + num_packet_per_page = NETRX_POOL_PAGE_SIZE / frag_size; + total_page_count = num_packet / num_packet_per_page + 1; + /** + * total buffer size is calculated based on worst case. buffer + * composed of 4KB pages only + */ + cm->total_buf_size = (num_packet + 100) * PAGE_SIZE; + + cm->desc_map = cpif_vmap_create(desc_addr_pair->cp_addr, desc_size, desc_size); + if (!cm->desc_map) + goto fail_vmap; + cm->data_map = cpif_vmap_create(databuf_cp_pbase, cm->total_buf_size, frag_size); + if (!cm->data_map) { + cpif_vmap_free(cm->desc_map); + goto fail_vmap; + } + + /* map descriptor region in advance */ + temp = cpif_vmap_map_area(cm->desc_map, 0, 0, virt_to_phys(desc_addr_pair->ap_addr)); + if (temp != desc_addr_pair->cp_addr) + goto fail; + + /* create recycling page array */ + cm->data_pool = cpif_page_pool_create(total_page_count, NETRX_POOL_PAGE_SIZE); + if (unlikely(!cm->data_pool)) + goto fail; + + spin_lock_init(&cm->lock); + + /* initialize data address list */ + INIT_LIST_HEAD(&cm->data_addr_list); + + mif_info("netrx mng: num_packet: %llu frag_size: %llu total_buf_size: %llu\n", + cm->num_packet, cm->frag_size, cm->total_buf_size); + mif_info("desc vmap: va_start: 0x%llX va_end: 0x%llX va_size: %llu\n", + cm->desc_map->va_start, cm->desc_map->va_end, cm->desc_map->va_size); + mif_info("data vmap: va_start: 0x%llX va_end: 0x%llX va_size: %llu\n", + cm->data_map->va_start, cm->data_map->va_end, cm->data_map->va_size); + mif_info("data_pool: num_pages: %d\n", cm->data_pool->rpage_arr_len); + + return cm; + +fail: + cpif_vmap_free(cm->desc_map); + cpif_vmap_free(cm->data_map); + +fail_vmap: + kvfree(cm); + +fail_cm: + return NULL; +} +EXPORT_SYMBOL(cpif_create_netrx_mng); + +void cpif_exit_netrx_mng(struct cpif_netrx_mng *cm) +{ + if (cm) { + struct cpif_addr_pair *temp, *temp2; + + if (cm->data_pool) + cpif_page_pool_delete(cm->data_pool); + + cpif_vmap_free(cm->desc_map); + cpif_vmap_free(cm->data_map); + list_for_each_entry_safe(temp, temp2, &cm->data_addr_list, addr_item) { + list_del(&temp->addr_item); + kfree(temp); + } + kvfree(cm); + } +} +EXPORT_SYMBOL(cpif_exit_netrx_mng); + +void cpif_init_netrx_mng(struct cpif_netrx_mng *cm) +{ + if (cm && cm->data_map && cm->data_pool) { + struct cpif_addr_pair *temp, *temp2; + + list_for_each_entry_safe(temp, temp2, &cm->data_addr_list, addr_item) + cpif_unmap_rx_buf(cm, temp->cp_addr, true); + + cpif_page_init_tmp_page(cm->data_pool); + } +} +EXPORT_SYMBOL(cpif_init_netrx_mng); + +struct cpif_addr_pair *cpif_map_rx_buf(struct cpif_netrx_mng *cm) +{ + struct page *page; + void *data; + u64 page_size, cp_addr; + unsigned long flags; + struct cpif_addr_pair *ret = NULL; + bool used_tmp_alloc = false; + + spin_lock_irqsave(&cm->lock, flags); + + if (unlikely(!cm->data_map)) { + mif_err_limited("data map is not created yet\n"); + goto done; + } + + data = cpif_page_alloc(cm->data_pool, cm->frag_size, &used_tmp_alloc); + if (!data) { + mif_err_limited("failed to page alloc: return\n"); + goto done; + } + + page = cpif_get_cur_page(cm->data_pool, used_tmp_alloc); + page_size = cpif_cur_page_size(cm->data_pool, used_tmp_alloc); + + ret = kzalloc(sizeof(struct cpif_addr_pair), GFP_ATOMIC); + if (!ret) { + mif_err_limited("failed to kzalloc for addr_pair\n"); + goto done; + } + + cp_addr = cpif_vmap_map_area(cm->data_map, page_to_phys(page), + page_size, virt_to_phys(data)); + if (!cp_addr) { /* cp_addr cannot be allocated */ + mif_err_limited("failed to vmap and get cp_addr\n"); + kfree(ret); + ret = NULL; + goto done; + } + + /* returns addr that cp is allowed to write */ + ret->cp_addr = cp_addr; + ret->ap_addr = data; + ret->page = page; + ret->page_order = get_order(page_size); + list_add_tail(&ret->addr_item, &cm->data_addr_list); + +done: + spin_unlock_irqrestore(&cm->lock, flags); + + return ret; +} +EXPORT_SYMBOL(cpif_map_rx_buf); + +void *cpif_unmap_rx_buf(struct cpif_netrx_mng *cm, u64 cp_addr, bool free) +{ + unsigned long flags; + u64 ap_paddr = 0; + void *ap_addr = NULL; + struct cpif_addr_pair *apair; + + spin_lock_irqsave(&cm->lock, flags); + + if (unlikely(!cm->data_map)) { + mif_err_limited("data map does not exist\n"); + goto done; + } + + if (cm->already_retrieved) { + ap_addr = cm->already_retrieved; + cm->already_retrieved = NULL; + goto done; + } + + ap_paddr = cpif_vmap_unmap_area(cm->data_map, cp_addr); + if (unlikely(ap_paddr == 0)) { + mif_err_limited("failed to receive ap_addr\n"); + goto done; + } + ap_addr = phys_to_virt(ap_paddr); + + apair = list_first_entry_or_null(&cm->data_addr_list, struct cpif_addr_pair, addr_item); + if (unlikely(!apair) || ap_addr != apair->ap_addr) { + mif_err_limited("ERR! ap_addr: %pK apair->ap_addr:%pK\n", ap_addr, + apair ? apair->ap_addr : 0); + ap_addr = NULL; + goto done; + } + + if (ap_addr && free) { + __free_pages(apair->page, apair->page_order); + ap_addr = NULL; + } + list_del(&apair->addr_item); + kfree(apair); + +done: + spin_unlock_irqrestore(&cm->lock, flags); + + return ap_addr; /* returns NULL or unmapped AP virtual address */ +} +EXPORT_SYMBOL(cpif_unmap_rx_buf); diff --git a/drivers/soc/google/cpif/cpif_netrx_mng.h b/drivers/soc/google/cpif/cpif_netrx_mng.h new file mode 100644 index 000000000000..2dda9738bb9d --- /dev/null +++ b/drivers/soc/google/cpif/cpif_netrx_mng.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __CPIF_NETRX_MNG_H__ +#define __CPIF_NETRX_MNG_H__ + +#include "modem_prj.h" +#include "link_device_memory.h" +#include "cpif_page.h" +#include "cpif_vmapper.h" + +struct cpif_addr_pair { + u64 cp_addr; /* cp address */ + void *ap_addr; /* ap virtual address */ + + struct page *page; /* page holding the ap address */ + u64 page_order; + + struct list_head addr_item; +}; + +struct cpif_netrx_mng { + u64 num_packet; + u64 frag_size; + u64 total_buf_size; + + struct cpif_va_mapper *desc_map; + struct cpif_va_mapper *data_map; + + struct cpif_page_pool *data_pool; + struct list_head data_addr_list; + spinlock_t lock; + + /* contains pre-unmapped AP addr which couldn't be delivered to kernel yet */ + void *already_retrieved; +}; + +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) +struct cpif_netrx_mng *cpif_create_netrx_mng(struct cpif_addr_pair *desc_addr_pair, + u64 desc_size, u64 databuf_cp_pbase, + u64 max_packet_size, u64 num_packet); +void cpif_exit_netrx_mng(struct cpif_netrx_mng *cm); +void cpif_init_netrx_mng(struct cpif_netrx_mng *cm); +struct cpif_addr_pair *cpif_map_rx_buf(struct cpif_netrx_mng *cm); +void *cpif_unmap_rx_buf(struct cpif_netrx_mng *cm, + u64 cp_data_paddr, bool free); +#else +static inline struct cpif_netrx_mng *cpif_create_netrx_mng( + struct cpif_addr_pair *desc_addr_pair, + u64 desc_size, u64 databuf_cp_pbase, + u64 max_packet_size, u64 num_packet) { return NULL; } +static inline void cpif_exit_netrx_mng(struct cpif_netrx_mng *cm) { return; } +static inline void cpif_init_netrx_mng(struct cpif_netrx_mng *cm) { return; } +static inline struct cpif_addr_pair *cpif_map_rx_buf(struct cpif_netrx_mng *cm) +{ return NULL; } +static inline void *cpif_unmap_rx_buf(struct cpif_netrx_mng *cm, + u64 cp_data_paddr, bool free) {return NULL; } +#endif +#endif /* __CPIF_NETRX_MNG_H__ */ diff --git a/drivers/soc/google/cpif/cpif_page.c b/drivers/soc/google/cpif/cpif_page.c new file mode 100644 index 000000000000..3176c19029e5 --- /dev/null +++ b/drivers/soc/google/cpif/cpif_page.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#include +#include "cpif_page.h" + +void cpif_page_pool_delete(struct cpif_page_pool *pool) +{ + int i; + struct cpif_page **rpage_arr = pool->recycling_page_arr; + struct cpif_page *tmp_page = pool->tmp_page; + + if (rpage_arr) { + for (i = 0; i < pool->rpage_arr_len; i++) { + struct cpif_page *cur = rpage_arr[i]; + + if (!cur) + continue; + if (cur->page) { + init_page_count(cur->page); + __free_pages(cur->page, pool->page_order); + } + kvfree(cur); + } + kvfree(rpage_arr); + } + + if (tmp_page) { + if (tmp_page->page) { + init_page_count(tmp_page->page); + __free_pages(tmp_page->page, get_order(pool->tmp_page_size)); + } + kvfree(tmp_page); + } + + kvfree(pool); + pool = NULL; +} +EXPORT_SYMBOL(cpif_page_pool_delete); + +void cpif_page_init_tmp_page(struct cpif_page_pool *pool) +{ + if (pool->tmp_page) { + pool->tmp_page->usable = false; + pool->tmp_page->offset = 0; + if (pool->tmp_page->page) { + __free_pages(pool->tmp_page->page, get_order(pool->tmp_page_size)); + pool->tmp_page->page = NULL; + } + } +} +EXPORT_SYMBOL(cpif_page_init_tmp_page); + +struct cpif_page_pool *cpif_page_pool_create(u64 num_page, u64 page_size) +{ + int i; + struct cpif_page_pool *pool; + struct cpif_page **rpage_arr; + struct cpif_page *tmp_page; + + pool = kvzalloc(sizeof(struct cpif_page_pool), GFP_KERNEL); + if (unlikely(!pool)) { + mif_err("failed to create page pool\n"); + return NULL; + } + + num_page *= 2; /* reserve twice as large of the least required */ + rpage_arr = kvzalloc(sizeof(struct cpif_page *) * num_page, GFP_KERNEL); + if (unlikely(!rpage_arr)) { + mif_err("failed to alloc recycling_page_arr\n"); + goto fail; + } + + pool->page_size = page_size; + pool->page_order = get_order(page_size); + + mif_info("num_page: %llu page_size: %llu page_order: %llu\n", + num_page, page_size, pool->page_order); + + for (i = 0; i < num_page; i++) { + struct cpif_page *cur = kvzalloc(sizeof(struct cpif_page), GFP_KERNEL); + + if (unlikely(!cur)) { + mif_err("failed to alloc cpif_page\n"); + goto fail; + } + cur->page = __dev_alloc_pages(GFP_KERNEL | CPIF_GFP_MASK, pool->page_order); + if (unlikely(!cur->page)) { + mif_err("failed to get page\n"); + cur->usable = false; + goto fail; + } + cur->usable = true; + cur->offset = 0; + rpage_arr[i] = cur; + } + + tmp_page = kvzalloc(sizeof(struct cpif_page), GFP_KERNEL); + if (unlikely(!tmp_page)) { + mif_err("failed to allocate temporary page\n"); + goto fail; + } + tmp_page->offset = 0; + tmp_page->usable = false; + + pool->recycling_page_arr = rpage_arr; + pool->tmp_page = tmp_page; + pool->rpage_arr_idx = 0; + pool->rpage_arr_len = num_page; + + return pool; + +fail: + cpif_page_pool_delete(pool); + return NULL; +} +EXPORT_SYMBOL(cpif_page_pool_create); + +struct page *cpif_get_cur_page(struct cpif_page_pool *pool, bool used_tmp_alloc) +{ + if (!used_tmp_alloc) + return pool->recycling_page_arr[pool->rpage_arr_idx]->page; + else + return pool->tmp_page->page; +} +EXPORT_SYMBOL(cpif_get_cur_page); + +u64 cpif_cur_page_size(struct cpif_page_pool *pool, bool used_tmp_alloc) +{ + if (!used_tmp_alloc) + return pool->page_size; + else + return pool->tmp_page_size; +} +EXPORT_SYMBOL(cpif_cur_page_size); + +#define RECYCLING_MAX_TRIAL 100 +static void *cpif_alloc_recycling_page(struct cpif_page_pool *pool, u64 alloc_size) +{ + u32 ret; + u32 idx = pool->rpage_arr_idx; + struct cpif_page *cur = pool->recycling_page_arr[idx]; + int retry_count = RECYCLING_MAX_TRIAL / (pool->page_order + 1); + + if (cur->offset < 0) { /* this page cannot handle next packet */ + cur->usable = false; + cur->offset = 0; +try_next_rpage: + if (++idx == pool->rpage_arr_len) + pool->rpage_arr_idx = 0; + else + pool->rpage_arr_idx++; + + idx = pool->rpage_arr_idx; + cur = pool->recycling_page_arr[idx]; + } + + if (page_ref_count(cur->page) == 1) { /* no one uses this page */ + cur->offset = pool->page_size - alloc_size; + cur->usable = true; + goto assign_page; + } + + if (cur->usable == true) /* page is in use, but still has some space left */ + goto assign_page; + + /* else, the page is not ready to be used, need to see next one */ + if (retry_count > 0) { + retry_count--; + goto try_next_rpage; + } + + return NULL; + +assign_page: + ret = cur->offset; + cur->offset -= alloc_size; + page_ref_inc(cur->page); + + return page_to_virt(cur->page) + ret; +} + +static void *cpif_alloc_tmp_page(struct cpif_page_pool *pool, u64 alloc_size) +{ + struct cpif_page *tmp = pool->tmp_page; + int ret; + + /* new page is required */ + if (!tmp->usable) { + u64 page_order = pool->page_order; + struct page *new_pg = __dev_alloc_pages(GFP_ATOMIC | CPIF_GFP_MASK, page_order); + + if (unlikely(!new_pg)) { + if (alloc_size > PAGE_SIZE) { + mif_err_limited("cannot alloc page for size: %llu\n", + alloc_size); + return NULL; + } + new_pg = __dev_alloc_pages(GFP_ATOMIC | CPIF_GFP_MASK, 0); /* try 4KB */ + if (unlikely(!new_pg)) { + mif_err_limited("cannot alloc new page\n"); + return NULL; + } + page_order = 0; + } + + if (tmp->page) /* unref, or possibly free the page */ + __free_pages(tmp->page, get_order(pool->tmp_page_size)); + tmp->page = new_pg; + pool->tmp_page_size = 4096 * (1 << page_order); + pool->using_tmp_alloc = true; + tmp->usable = true; + tmp->offset = pool->tmp_page_size - alloc_size; + } + + ret = tmp->offset; + tmp->offset -= alloc_size; + page_ref_inc(tmp->page); + if (tmp->offset < 0) { /* drained page, let pool try recycle page next time */ + pool->using_tmp_alloc = false; + tmp->usable = false; + } + + return page_to_virt(tmp->page) + ret; +} + +void *cpif_page_alloc(struct cpif_page_pool *pool, u64 alloc_size, bool *used_tmp_alloc) +{ + void *ret; + + if (alloc_size > pool->page_size) { + mif_err_limited("requested size exceeds page size. r_size: %llu p_size: %llu\n", + alloc_size, pool->page_size); + return NULL; + } + + if (!pool->using_tmp_alloc) { + ret = cpif_alloc_recycling_page(pool, alloc_size); + if (ret) { + *used_tmp_alloc = false; + goto done; + } + } + + mif_err_limited("cannot recycle page, alloc new one\n"); + ret = cpif_alloc_tmp_page(pool, alloc_size); + if (!ret) { + mif_err_limited("failed to tmp page alloc: return\n"); + goto done; + } + *used_tmp_alloc = true; + +done: + return ret; +} +EXPORT_SYMBOL(cpif_page_alloc); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Samsung Page Recycling driver"); diff --git a/drivers/soc/google/cpif/cpif_page.h b/drivers/soc/google/cpif/cpif_page.h new file mode 100644 index 000000000000..996f61662c97 --- /dev/null +++ b/drivers/soc/google/cpif/cpif_page.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __CPIF_RX_PAGE_H__ +#define __CPIF_RX_PAGE_H__ + +#include "modem_prj.h" + +#define CPIF_GFP_MASK (__GFP_NOWARN | __GFP_NORETRY | __GFP_NOMEMALLOC) + +struct cpif_page { + struct page *page; + bool usable; + int offset; +}; + +struct cpif_page_pool { + u64 page_order; + u64 page_size; + u64 tmp_page_size; + struct cpif_page **recycling_page_arr; + struct cpif_page *tmp_page; + u32 rpage_arr_idx; + u32 rpage_arr_len; + bool using_tmp_alloc; +}; + +#if IS_ENABLED(CONFIG_CPIF_PAGE_RECYCLING) +void cpif_page_pool_delete(struct cpif_page_pool *pool); +void cpif_page_init_tmp_page(struct cpif_page_pool *pool); +struct cpif_page_pool *cpif_page_pool_create(u64 num_page, u64 page_size); +struct page *cpif_get_cur_page(struct cpif_page_pool *pool, bool used_tmp_alloc); +u64 cpif_cur_page_size(struct cpif_page_pool *pool, bool used_tmp_alloc); +void *cpif_page_alloc(struct cpif_page_pool *pool, u64 alloc_size, bool *used_tmp_alloc); +#else +static inline void cpif_page_pool_delete(struct cpif_page_pool *pool) { return; } +static inline void cpif_page_init_tmp_page(struct cpif_page_pool *pool) { return; } +static inline struct cpif_page_pool *cpif_page_pool_create(u64 num_page, + u64 page_size) { return NULL; } +static inline struct page *cpif_get_cur_page(struct cpif_page_pool *pool, + bool used_tmp_alloc) { return NULL; } +static inline u64 cpif_cur_page_size(struct cpif_page_pool *pool, bool used_tmp_alloc) + { return 0; } +static inline void *cpif_page_alloc(struct cpif_page_pool *pool, u64 alloc_size, + bool *used_tmp_alloc) { return NULL; } +#endif + +#endif /* __CPIF_RX_PAGE_H__ */ diff --git a/drivers/soc/google/cpif/cpif_qos_info.h b/drivers/soc/google/cpif/cpif_qos_info.h index 9fa331a76771..7469f1848e8f 100644 --- a/drivers/soc/google/cpif/cpif_qos_info.h +++ b/drivers/soc/google/cpif/cpif_qos_info.h @@ -20,10 +20,6 @@ struct hiprio_uid { }; int cpif_qos_init_list(void); -struct hiprio_uid_list *cpif_qos_get_list(void); struct hiprio_uid *cpif_qos_get_node(u32 uid); -bool cpif_qos_add_uid(u32 uid); -bool cpif_qos_remove_uid(u32 uid); - #endif /* __CPIF_QOS_INFO_H__ */ diff --git a/drivers/soc/google/cpif/cpif_tp_monitor.c b/drivers/soc/google/cpif/cpif_tp_monitor.c index 23895a788b77..01028ac148df 100644 --- a/drivers/soc/google/cpif/cpif_tp_monitor.c +++ b/drivers/soc/google/cpif/cpif_tp_monitor.c @@ -8,6 +8,7 @@ #include #include "modem_prj.h" #include "modem_utils.h" +#include "modem_ctrl.h" #include "link_device_memory.h" #include "cpif_tp_monitor.h" #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) @@ -23,212 +24,201 @@ static struct cpif_tpmon _tpmon; -/* Queue status */ -static int tpmon_calc_pktproc_queue_status(struct cpif_tpmon *tpmon) +/* + * Get data + */ +/* RX speed */ +static u32 tpmon_get_rx_speed_mbps(struct tpmon_data *data) { - struct mem_link_device *mld = ld_to_mem_link_device(tpmon->ld); - struct pktproc_adaptor *ppa = &mld->pktproc; - u32 usage = 0; - int i; + unsigned long speed = 0; - if (!pktproc_check_support(ppa)) + if (!data->enable) return 0; - for (i = 0; i < mld->pktproc.num_queue; i++) { - if (!pktproc_check_active(ppa, i)) - continue; - - if (pktproc_get_usage_fore_rear(ppa->q[i]) > 0) - usage += pktproc_get_usage_fore_rear(ppa->q[i]); + switch (data->proto) { + case TPMON_PROTO_TCP: + speed = data->tpmon->rx_tcp.rx_mbps; + break; + case TPMON_PROTO_UDP: + speed = data->tpmon->rx_udp.rx_mbps; + break; + case TPMON_PROTO_OTHERS: + speed = data->tpmon->rx_others.rx_mbps; + break; + case TPMON_PROTO_ALL: + default: + speed = data->tpmon->rx_total.rx_mbps; + break; } - tpmon->pktproc_queue_status = usage; - - return 0; + return (u32)speed; } -static int tpmon_calc_netdev_backlog_queue_status(struct cpif_tpmon *tpmon) +static int tpmon_calc_rx_speed_internal( + struct cpif_tpmon *tpmon, struct cpif_rx_data *rx_data, bool check_stat) { - struct softnet_data *sd = NULL; - u32 usage = 0; - int i; - int num_cpu; + u64 rx_bytes; + u64 delta_msec; + ktime_t curr_time; + unsigned long flags; -#if defined(CONFIG_VENDOR_NR_CPUS) - num_cpu = CONFIG_VENDOR_NR_CPUS; -#else - num_cpu = 8; -#endif - for (i = 0; i < num_cpu; i++) { - sd = &per_cpu(softnet_data, i); - if (sd->input_queue_tail > sd->input_queue_head) - usage += sd->input_queue_tail - sd->input_queue_head; - } + curr_time = ktime_get(); - tpmon->netdev_backlog_queue_status = usage; + delta_msec = ktime_ms_delta(curr_time, rx_data->prev_time); + if (delta_msec < tpmon->trigger_msec_min) + return -EIO; - return 0; -} + rx_data->prev_time = curr_time; -static int tpmon_calc_dit_src_queue_status(struct cpif_tpmon *tpmon) -{ - u32 usage = 0; + spin_lock_irqsave(&tpmon->lock, flags); + rx_bytes = rx_data->rx_bytes; + rx_data->rx_bytes = 0; + spin_unlock_irqrestore(&tpmon->lock, flags); -#if IS_ENABLED(CONFIG_EXYNOS_DIT) - int ret = dit_get_src_usage(DIT_DIR_RX, &usage); - if (ret && (ret != -EPERM)) { - mif_err_limited("dit_get_src_usage() error:%d\n", ret); - return ret; + if (!check_stat && (delta_msec > tpmon->trigger_msec_max)) { + rx_data->rx_mbps = 0; + return -EIO; } -#endif - tpmon->dit_src_queue_status = usage; + rx_data->rx_mbps = rx_bytes * 8 / delta_msec / 1000; return 0; } -/* - * Get data - */ -static u32 tpmon_get_pktproc_queue_status(struct tpmon_data *data) +static void tpmon_stat_rx_speed(struct cpif_tpmon *tpmon) { - if (!data->enable) - return 0; - - tpmon_calc_pktproc_queue_status(data->tpmon); - - return data->tpmon->pktproc_queue_status; + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_total_stat, true); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_tcp_stat, true); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_udp_stat, true); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_others_stat, true); } -static u32 tpmon_get_netdev_backlog_queue_status(struct tpmon_data *data) +static void tpmon_calc_rx_speed(struct cpif_tpmon *tpmon) { - if (!data->enable) - return 0; + int ret = 0; + + ret = tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_total, false); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_tcp, false); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_udp, false); + tpmon_calc_rx_speed_internal(tpmon, &tpmon->rx_others, false); - tpmon_calc_netdev_backlog_queue_status(data->tpmon); + if (tpmon->debug_print && tpmon->rx_total.rx_mbps && !ret) + mif_info("%ldMbps(%ld/%ld/%ld)\n", + tpmon->rx_total.rx_mbps, tpmon->rx_tcp.rx_mbps, + tpmon->rx_udp.rx_mbps, tpmon->rx_others.rx_mbps); - return data->tpmon->netdev_backlog_queue_status; + if (!tpmon_check_active()) + tpmon_stat_rx_speed(tpmon); } -static u32 tpmon_get_dit_src_queue_status(struct tpmon_data *data) +/* Queue status */ +static u32 tpmon_get_q_status(struct tpmon_data *data) { + u32 usage = 0; + if (!data->enable) return 0; - tpmon_calc_dit_src_queue_status(data->tpmon); + switch (data->measure) { + case TPMON_MEASURE_NETDEV_Q: + usage = data->tpmon->q_status_netdev_backlog; + break; + case TPMON_MEASURE_PKTPROC_DL_Q: + usage = data->tpmon->q_status_pktproc_dl; + break; + case TPMON_MEASURE_DIT_SRC_Q: + usage = data->tpmon->q_status_dit_src; + break; + default: + mif_err_limited("measure %d is not valid\n", data->measure); + break; + } - return data->tpmon->dit_src_queue_status; + return usage; } -static u32 tpmon_get_rx_total_speed_mbps(struct tpmon_data *data) +static int tpmon_calc_q_status_pktproc_dl(struct cpif_tpmon *tpmon) { - if (!data->enable) - return 0; - - return (u32)data->tpmon->rx_total.rx_mbps; -} + struct mem_link_device *mld = ld_to_mem_link_device(tpmon->ld); + struct pktproc_adaptor *ppa = &mld->pktproc; + u32 usage = 0; + int i; -static u32 tpmon_get_rx_tcp_speed_mbps(struct tpmon_data *data) -{ - if (!data->enable) + if (!pktproc_check_support(ppa)) return 0; - return (u32)data->tpmon->rx_tcp.rx_mbps; -} - -static u32 tpmon_get_rx_udp_speed_mbps(struct tpmon_data *data) -{ - if (!data->enable) - return 0; + for (i = 0; i < mld->pktproc.num_queue; i++) { + if (!pktproc_check_active(ppa, i)) + continue; - return (u32)data->tpmon->rx_udp.rx_mbps; -} + if (pktproc_get_usage_fore_rear(ppa->q[i]) > 0) + usage += pktproc_get_usage_fore_rear(ppa->q[i]); + } -static u32 tpmon_get_rx_others_speed_mbps(struct tpmon_data *data) -{ - if (!data->enable) - return 0; + tpmon->q_status_pktproc_dl = usage; - return (u32)data->tpmon->rx_others.rx_mbps; + return 0; } -/* RX speed */ -static void calc_rx_speed_internal(struct cpif_tpmon *tpmon, - struct cpif_rx_data *rx_data) +static int tpmon_calc_q_status_dit_src(struct cpif_tpmon *tpmon) { - unsigned long divider_mbps, divider_kbps; - unsigned long rx_bytes; - unsigned long flags; - - /* mbps 131072 = 1024 * 1024 / 8 */ - /* kbps 128 = 1024 / 8 */ - divider_mbps = 131072 * tpmon->monitor_interval_msec / 1000; - divider_mbps *= tpmon->rx_bytes_valid_cnt; - divider_kbps = 128 * tpmon->monitor_interval_msec / 1000; - divider_kbps *= tpmon->rx_bytes_valid_cnt; - - spin_lock_irqsave(&tpmon->lock, flags); - rx_bytes = rx_data->rx_bytes; - rx_data->rx_bytes = 0; - spin_unlock_irqrestore(&tpmon->lock, flags); + u32 usage = 0; - rx_data->rx_sum -= rx_data->rx_bytes_data[rx_data->rx_bytes_idx]; - rx_data->rx_sum += rx_bytes; - rx_data->rx_bytes_data[rx_data->rx_bytes_idx] = rx_bytes; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + int ret = dit_get_src_usage(DIT_DIR_RX, &usage); - rx_data->rx_bytes_idx++; - rx_data->rx_bytes_idx %= tpmon->rx_bytes_len; + if (ret && (ret != -EPERM)) { + mif_err_limited("dit_get_src_usage() error:%d\n", ret); + return ret; + } +#endif - if (!divider_mbps || rx_data->rx_sum < divider_mbps) - rx_data->rx_mbps = 0; - else - rx_data->rx_mbps = rx_data->rx_sum / divider_mbps; + tpmon->q_status_dit_src = usage; - if (!divider_kbps || rx_data->rx_sum < divider_kbps) - rx_data->rx_kbps = 0; - else - rx_data->rx_kbps = rx_data->rx_sum / divider_kbps; + return 0; } -static void tpmon_calc_rx_speed(struct cpif_tpmon *tpmon) +static int tpmon_calc_q_status_netdev_backlog(struct cpif_tpmon *tpmon) { - unsigned long flags; + struct softnet_data *sd = NULL; + u32 usage = 0; + int i; + int num_cpu; + +#if defined(CONFIG_VENDOR_NR_CPUS) + num_cpu = CONFIG_VENDOR_NR_CPUS; +#else + num_cpu = 8; +#endif + for (i = 0; i < num_cpu; i++) { + sd = &per_cpu(softnet_data, i); + if (sd->input_queue_tail > sd->input_queue_head) + usage += sd->input_queue_tail - sd->input_queue_head; + } - if (tpmon->rx_bytes_valid_cnt < tpmon->rx_bytes_len) - tpmon->rx_bytes_valid_cnt++; + tpmon->q_status_netdev_backlog = usage; - calc_rx_speed_internal(tpmon, &tpmon->rx_total); - calc_rx_speed_internal(tpmon, &tpmon->rx_tcp); - calc_rx_speed_internal(tpmon, &tpmon->rx_udp); - calc_rx_speed_internal(tpmon, &tpmon->rx_others); + return 0; +} - spin_lock_irqsave(&tpmon->lock, flags); - tpmon->rx_bytes_skip_add = false; - spin_unlock_irqrestore(&tpmon->lock, flags); +static void tpmon_calc_q_status(struct cpif_tpmon *tpmon) +{ + tpmon_calc_q_status_pktproc_dl(tpmon); + tpmon_calc_q_status_dit_src(tpmon); + tpmon_calc_q_status_netdev_backlog(tpmon); } /* Inforamtion */ -static void tpmon_print_info(struct cpif_tpmon *tpmon) +static void tpmon_print_stat(struct cpif_tpmon *tpmon) { - if (tpmon->rx_total.rx_bytes_idx != 0) - return; - - tpmon_calc_pktproc_queue_status(tpmon); - tpmon_calc_dit_src_queue_status(tpmon); - tpmon_calc_netdev_backlog_queue_status(tpmon); - - mif_info("DL:%ld%s(%ld%s/%ld%s/%ld%s) pktproc:%d/dit:%d/netdev:%d legacy:%d tcp_rmem:%d %d %d\n", - tpmon->rx_total.rx_mbps ? tpmon->rx_total.rx_mbps : tpmon->rx_total.rx_kbps, - tpmon->rx_total.rx_mbps ? "Mbps" : "Kbps", - tpmon->rx_tcp.rx_mbps ? tpmon->rx_tcp.rx_mbps : tpmon->rx_tcp.rx_kbps, - tpmon->rx_tcp.rx_mbps ? "Mbps" : "Kbps", - tpmon->rx_udp.rx_mbps ? tpmon->rx_udp.rx_mbps : tpmon->rx_udp.rx_kbps, - tpmon->rx_udp.rx_mbps ? "Mbps" : "Kbps", - tpmon->rx_others.rx_mbps ? tpmon->rx_others.rx_mbps : tpmon->rx_others.rx_kbps, - tpmon->rx_others.rx_mbps ? "Mbps" : "Kbps", - tpmon->pktproc_queue_status, - tpmon->dit_src_queue_status, - tpmon->netdev_backlog_queue_status, + mif_info_limited("DL:%ldMbps(%ld/%ld/%ld) Q:%d/%d/%d/%d tcp_rmem:%d/%d/%d\n", + tpmon->rx_total_stat.rx_mbps, + tpmon->rx_tcp_stat.rx_mbps, + tpmon->rx_udp_stat.rx_mbps, + tpmon->rx_others_stat.rx_mbps, + tpmon->q_status_pktproc_dl, + tpmon->q_status_dit_src, + tpmon->q_status_netdev_backlog, tpmon->legacy_packet_count, init_net.ipv4.sysctl_tcp_rmem[0], init_net.ipv4.sysctl_tcp_rmem[1], init_net.ipv4.sysctl_tcp_rmem[2]); @@ -236,12 +226,13 @@ static void tpmon_print_info(struct cpif_tpmon *tpmon) tpmon->legacy_packet_count = 0; } -/* Check speed changing */ +/* Check boost/unboost */ static bool tpmon_check_to_boost(struct tpmon_data *data) { - struct tpmon_data *data_list; int usage = 0; int i; + struct cpif_tpmon *tpmon = data->tpmon; + struct tpmon_data *all_data = NULL; if (!data->enable) return false; @@ -251,29 +242,14 @@ static bool tpmon_check_to_boost(struct tpmon_data *data) return false; } - list_for_each_entry(data_list, &data->tpmon->data_list, data_node) { - if (strcmp(data_list->name, data->name) == 0) - continue; - - if (data_list->target == data->target) { - if (data_list->curr_value_pos) { - mif_info("disable %s. %s is boosted\n", - data->name, data_list->name); - data->enable = 0; - continue; - } + list_for_each_entry(all_data, &tpmon->all_data_list, data_node) { + if ((data->target == all_data->target) && + (data->measure != all_data->measure) && + (data->curr_level_pos < all_data->curr_level_pos)) { + return false; } } - if (data->check_udp && - (data->tpmon->rx_udp.rx_mbps > data->tpmon->trigger_mbps) && - (data->tpmon->rx_udp.rx_mbps > - (data->tpmon->rx_tcp.rx_mbps + data->tpmon->rx_others.rx_mbps))) { - data->forced_unboost = true; - return false; - } - data->forced_unboost = false; - usage = data->get_data(data); if (usage < 0) { mif_err_limited("get_data(%s) error:%d\n", data->name, usage); @@ -284,102 +260,121 @@ static bool tpmon_check_to_boost(struct tpmon_data *data) if (usage < data->threshold[i]) break; - if (i <= data->curr_value_pos) + if (i <= data->curr_level_pos) return false; - if (i >= data->num_values) { - mif_err_limited("Invalid value:%s %d %d\n", - data->name, i, data->num_values); + if (i >= data->num_level) { + mif_err_limited("Invalid level:%s %d %d\n", + data->name, i, data->num_level); return false; } - data->prev_value_pos = data->curr_value_pos; - data->curr_value_pos = i; + data->prev_level_pos = data->curr_level_pos; + data->curr_level_pos = i; data->prev_threshold_pos = data->curr_threshold_pos; - if (data->curr_value_pos) - data->curr_threshold_pos = data->curr_value_pos - 1; + if (data->curr_level_pos) + data->curr_threshold_pos = data->curr_level_pos - 1; else data->curr_threshold_pos = 0; - for (i = data->curr_threshold_pos; i >= 0; i--) { - if (data->unboost_tp_mbps[i]) - continue; - switch (data->measure) { - case TPMON_MEASURE_TP: - data->unboost_tp_mbps[i] = data->threshold[i] * - data->tpmon->unboost_tp_percent / 100; - break; - default: - data->unboost_tp_mbps[i] = data->tpmon->rx_total.rx_mbps * - data->tpmon->unboost_tp_percent / 100; - break; - } - } + data->need_boost = true; mif_info("%s %d->%d (usage:%d unboost@%dMbps)\n", - data->name, data->prev_value_pos, data->curr_value_pos, - usage, data->unboost_tp_mbps[data->curr_threshold_pos]); + data->name, data->prev_level_pos, data->curr_level_pos, + usage, data->unboost_threshold_mbps[data->curr_threshold_pos]); return true; } static bool tpmon_check_to_unboost(struct tpmon_data *data) { - u64 jiffies_curr; + ktime_t curr_time; u64 delta_msec; if (!data->enable) return false; - if (!data->curr_value_pos) + if (!data->curr_level_pos) return false; - jiffies_curr = get_jiffies_64(); - if (!data->jiffies_to_unboost) { - data->jiffies_to_unboost = jiffies_curr; + curr_time = ktime_get(); + if (!data->prev_unboost_time) { + data->prev_unboost_time = curr_time; return false; } - if ((data->tpmon->rx_total.rx_mbps >= - data->unboost_tp_mbps[data->curr_threshold_pos])) { - if (!data->forced_unboost) { - data->jiffies_to_unboost = jiffies_curr; - return false; - } + if ((tpmon_get_rx_speed_mbps(data) >= + data->unboost_threshold_mbps[data->curr_threshold_pos])) { + data->prev_unboost_time = curr_time; + return false; } - if (jiffies_curr > data->jiffies_to_unboost) - delta_msec = jiffies64_to_msecs(jiffies_curr - data->jiffies_to_unboost); - else - delta_msec = jiffies64_to_msecs(data->jiffies_to_unboost - jiffies_curr); - + delta_msec = ktime_ms_delta(curr_time, data->prev_unboost_time); if (delta_msec < data->tpmon->boost_hold_msec) return false; - data->prev_value_pos = data->curr_value_pos; - if (data->curr_value_pos > 0) - data->curr_value_pos--; + data->prev_level_pos = data->curr_level_pos; + if (data->curr_level_pos > 0) + data->curr_level_pos--; data->prev_threshold_pos = data->curr_threshold_pos; if (data->curr_threshold_pos > 0) data->curr_threshold_pos--; - mif_info("%s %d->%d (%ldMbps < %dMbps) forced_unboost:%d\n", - data->name, data->prev_value_pos, data->curr_value_pos, + mif_info("%s %d->%d (%ldMbps < %dMbps)\n", + data->name, data->prev_level_pos, data->curr_level_pos, data->tpmon->rx_total.rx_mbps, - data->unboost_tp_mbps[data->prev_threshold_pos], - data->forced_unboost); + data->unboost_threshold_mbps[data->prev_threshold_pos]); - data->jiffies_to_unboost = 0; - data->unboost_tp_mbps[data->prev_threshold_pos] = 0; + data->prev_unboost_time = 0; return true; } +static void tpmon_get_cpu_per_queue(u32 mask, u32 *q, unsigned int q_num, + bool get_mask) +{ + u32 cur_mask = mask, bit_pos = 0; + bool masks_lt_qnum = false; + unsigned int idx = 0; + + if (!mask) + return; + + while (cur_mask || idx < q_num) { + u32 bit_mask; + + if (!cur_mask) { + cur_mask = mask; + bit_pos = 0; + + if (idx < q_num) + masks_lt_qnum = true; + } + + bit_mask = (u32)BIT(bit_pos); + + if (bit_mask & cur_mask) { + cur_mask &= ~bit_mask; + if (get_mask) + q[idx % q_num] |= bit_mask; + else + q[idx % q_num] = bit_pos; + idx++; + } + + if (masks_lt_qnum && idx == q_num) + cur_mask = 0; + + bit_pos++; + } +} + /* - * Set data + * Target */ +/* RPS */ #if IS_ENABLED(CONFIG_RPS) /* From net/core/net-sysfs.c */ static ssize_t tpmon_store_rps_map(struct netdev_rx_queue *queue, @@ -423,17 +418,10 @@ static ssize_t tpmon_store_rps_map(struct netdev_rx_queue *queue, mutex_is_locked(&rps_map_mutex)); rcu_assign_pointer(queue->rps_map, map); -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) if (map) static_branch_inc(&rps_needed); if (old_map) static_branch_dec(&rps_needed); -#else - if (map) - static_key_slow_inc(&rps_needed); - if (old_map) - static_key_slow_dec(&rps_needed); -#endif mutex_unlock(&rps_map_mutex); @@ -446,55 +434,50 @@ static ssize_t tpmon_store_rps_map(struct netdev_rx_queue *queue, static void tpmon_set_rps(struct tpmon_data *data) { +#if IS_ENABLED(CONFIG_CP_PKTPROC) + struct mem_link_device *mld = container_of(data->tpmon->ld, + struct mem_link_device, link_dev); + struct pktproc_adaptor *ppa = &mld->pktproc; +#endif struct io_device *iod; - struct mem_link_device *mld; - struct pktproc_adaptor *ppa; - unsigned long flags; - int ret = 0; - char mask[MAX_RPS_STRING]; - u32 rps_value; - int q_stat; - int i; + unsigned int num_queue = 1; + unsigned int i; + u32 val, *rxq_mask; if (!data->enable) return; - rps_value = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; - snprintf(mask, MAX_RPS_STRING, "%x", rps_value); - - mld = to_mem_link_device(data->tpmon->ld); - ppa = &mld->pktproc; - if (ppa->use_exclusive_irq) { - for (i = 0; i < ppa->num_queue; i++) { - ppa->q[i]->disable_irq(ppa->q[i]); - if (ppa->use_napi) - napi_disable(&ppa->q[i]->napi); - } - } +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (ppa->use_exclusive_irq) + num_queue = ppa->num_queue; +#endif - for (i = 0; i < 1000; i++) { - tpmon_calc_netdev_backlog_queue_status(data->tpmon); - q_stat = data->tpmon->netdev_backlog_queue_status; - if (q_stat == 0) - break; + rxq_mask = kzalloc(sizeof(u32) * num_queue, GFP_KERNEL); + if (!rxq_mask) + return; - udelay(100); - } - if (q_stat) - mif_info("can not clear q_stat:%d\n", q_stat); + val = tpmon_get_curr_level(data); + tpmon_get_cpu_per_queue(val, rxq_mask, num_queue, true); list_for_each_entry(iod, &data->tpmon->net_node_list, node_all_ndev) { + char mask[MAX_RPS_STRING] = {}; + unsigned long flags; + int ret; + if (!iod->name) continue; if (!iod->ndev) continue; - ret = (int)tpmon_store_rps_map(&(iod->ndev->_rx[0]), mask, strlen(mask)); - if (ret < 0) { - mif_err("tpmon_store_rps_map() error:%d\n", ret); - break; + for (i = 0; i < num_queue; i++) { + snprintf(mask, MAX_RPS_STRING, "%x", rxq_mask[i]); + + ret = (int)tpmon_store_rps_map(&iod->ndev->_rx[i], mask, strlen(mask)); + if (ret < 0) { + mif_err("tpmon_store_rps_map() error:%d\n", ret); + goto out; + } } spin_lock_irqsave(&iod->clat_lock, flags); @@ -506,7 +489,9 @@ static void tpmon_set_rps(struct tpmon_data *data) dev_hold(iod->clat_ndev); spin_unlock_irqrestore(&iod->clat_lock, flags); - ret = (int)tpmon_store_rps_map(&(iod->clat_ndev->_rx[0]), mask, strlen(mask)); + snprintf(mask, MAX_RPS_STRING, "%x", val); + ret = (int)tpmon_store_rps_map(&(iod->clat_ndev->_rx[0]), + mask, strlen(mask)); dev_put(iod->clat_ndev); if (ret < 0) { @@ -515,44 +500,34 @@ static void tpmon_set_rps(struct tpmon_data *data) } } - if (ppa->use_exclusive_irq) { - for (i = 0; i < ppa->num_queue; i++) { - if (ppa->use_napi) - napi_enable(&ppa->q[i]->napi); - ppa->q[i]->enable_irq(ppa->q[i]); - } - } + for (i = 0; i < num_queue; i++) + mif_info("%s (rxq[%u] mask:0x%02x)\n", data->name, i, rxq_mask[i]); - mif_info("%s (mask:0x%s)\n", data->name, mask); +out: + kfree(rxq_mask); } #endif +/* GRO flush timeout */ static void tpmon_set_gro(struct tpmon_data *data) { struct mem_link_device *mld = container_of(data->tpmon->ld, struct mem_link_device, link_dev); long timeout; + #if IS_ENABLED(CONFIG_CP_PKTPROC) struct pktproc_adaptor *ppa = &mld->pktproc; int i; #endif -#if IS_ENABLED(CONFIG_EXYNOS_DIT) - struct net_device *netdev = NULL; -#endif if (!data->enable) return; - timeout = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; - -#if !IS_ENABLED(CONFIG_CP_PKTPROC) && !IS_ENABLED(CONFIG_EXYNOS_DIT) - mld->dummy_net.gro_flush_timeout = timeout; -#endif + timeout = tpmon_get_curr_level(data); #if IS_ENABLED(CONFIG_CP_PKTPROC) - if (ppa->use_napi && ppa->use_exclusive_irq) { - for (i = 0; i > ppa->num_queue; i++) { + if (ppa->use_exclusive_irq) { + for (i = 0; i < ppa->num_queue; i++) { struct pktproc_queue *q = ppa->q[i]; q->netdev.gro_flush_timeout = timeout; @@ -560,12 +535,13 @@ static void tpmon_set_gro(struct tpmon_data *data) } else { mld->dummy_net.gro_flush_timeout = timeout; } +#else + mld->dummy_net.gro_flush_timeout = timeout; #endif #if IS_ENABLED(CONFIG_EXYNOS_DIT) - netdev = dit_get_netdev(); - if (netdev) { - netdev->gro_flush_timeout = timeout; + if (dit_get_netdev()) { + dit_get_netdev()->gro_flush_timeout = timeout; mld->dummy_net.gro_flush_timeout = 0; } #endif @@ -577,79 +553,119 @@ static void tpmon_set_gro(struct tpmon_data *data) #if IS_ENABLED(CONFIG_MCU_IPC) static void tpmon_set_irq_affinity_mbox(struct tpmon_data *data) { - u32 cpu_num; +#if IS_ENABLED(CONFIG_CP_PKTPROC) + struct mem_link_device *mld = ld_to_mem_link_device(data->tpmon->ld); + struct pktproc_adaptor *ppa = &mld->pktproc; +#endif + unsigned int num_queue = 1; + unsigned int i; + u32 val, *q_cpu; if (!data->enable) return; - cpu_num = data->tpmon->use_user_value ? data->user_value : - data->values[data->curr_value_pos]; +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (ppa->use_exclusive_irq) + num_queue = ppa->num_queue; +#endif - if (cp_mbox_get_affinity(data->extra_idx) == cpu_num) { - mif_info("skip to set same cpu_num for %s (CPU:%d)\n", - data->name, cpu_num); + q_cpu = kzalloc(sizeof(u32) * num_queue, GFP_KERNEL); + if (!q_cpu) return; } - mif_info("%s (CPU:%d)\n", data->name, cpu_num); + val = tpmon_get_curr_level(data); + tpmon_get_cpu_per_queue(val, q_cpu, num_queue, false); + + for (i = 0; i < num_queue; i++) { + int irq_idx = data->extra_idx; + +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (ppa->use_exclusive_irq) + irq_idx = ppa->q[i]->irq_idx; +#endif + + if (cp_mbox_get_affinity(irq_idx) == q_cpu[i]) { + mif_info("skip to set same cpu_num for %s (CPU:%u)\n", + data->name, q_cpu[i]); + continue; + } + + mif_info("%s (CPU:%u)\n", data->name, val); + cp_mbox_set_affinity(irq_idx, q_cpu[i]); + } - cp_mbox_set_affinity(data->extra_idx, cpu_num); + kfree(q_cpu); } #endif #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) static void tpmon_set_irq_affinity_pcie(struct tpmon_data *data) { + struct mem_link_device *mld = ld_to_mem_link_device(data->tpmon->ld); struct modem_ctl *mc = data->tpmon->ld->mc; - u32 cpu_num; +#if IS_ENABLED(CONFIG_CP_PKTPROC) + struct pktproc_adaptor *ppa = &mld->pktproc; + unsigned int num_queue = 1; + unsigned int i; + u32 val, *q_cpu; +#endif - if (!mc) + if (!data->enable) return; - if (!data->enable) +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (ppa->use_exclusive_irq) + num_queue = ppa->num_queue; + + q_cpu = kzalloc(sizeof(u32) * num_queue, GFP_KERNEL); + if (!q_cpu) return; - cpu_num = data->tpmon->use_user_value ? data->user_value : - data->values[data->curr_value_pos]; + val = tpmon_get_curr_level(data); + tpmon_get_cpu_per_queue(val, q_cpu, num_queue, false); - mif_info("%s (CPU:%d)\n", data->name, cpu_num); + for (i = 0; i < num_queue; i++) { + if (!ppa->q[i]->irq) + break; + + if (!ppa->use_exclusive_irq) + q_cpu[i] = data->extra_idx; + + mif_info("%s (q[%u] cpu:%u)\n", data->name, i, q_cpu[i]); + mld->msi_irq_q_cpu[i] = q_cpu[i]; + } - exynos_pcie_rc_set_affinity(mc->pcie_ch_num, cpu_num); + kfree(q_cpu); +#endif + + /* The affinity of msi_irq_base is fixed, use the extra_idx */ + mld->msi_irq_base_cpu = data->extra_idx; + s5100_set_pcie_irq_affinity(mc); } #endif #if IS_ENABLED(CONFIG_EXYNOS_DIT) static void tpmon_set_irq_affinity_dit(struct tpmon_data *data) { - u32 cpu_num; + u32 val, cpu[1]; if (!data->enable) return; - cpu_num = data->tpmon->use_user_value ? data->user_value : - data->values[data->curr_value_pos]; + val = tpmon_get_curr_level(data); + tpmon_get_cpu_per_queue(val, cpu, 1, false); - if (dit_get_irq_affinity() == cpu_num) { - mif_info("skip to set same cpu_num for %s (CPU:%d)\n", - data->name, cpu_num); + if (dit_get_irq_affinity() == cpu[0]) { + mif_info("skip to set same cpu_num for %s (CPU:%u)\n", + data->name, cpu[0]); return; } - mif_info("%s (CPU:%d)\n", data->name, cpu_num); - -#if IS_ENABLED(CONFIG_MCPS) - if (mcps_enable) { - char mask[MAX_IRQ_AFFINITY_STRING]; - - snprintf(mask, MAX_IRQ_AFFINITY_STRING, "%x", 1 << cpu_num); - mif_info("set %s to mcps\n", mask); - set_mcps_cp_irq_mask(mask); - } -#endif - - dit_set_irq_affinity(cpu_num); -} -#endif + mif_info("%s (CPU:%u)\n", data->name, cpu[0]); + dit_set_irq_affinity(cpu[0]); +} +#endif /* Frequency */ #if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) @@ -663,8 +679,7 @@ static void tpmon_set_exynos_pm_qos(struct tpmon_data *data) if (!data->extra_data) return; - val = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; + val = tpmon_get_curr_level(data); mif_info("%s (freq:%d)\n", data->name, val); @@ -683,8 +698,7 @@ static void tpmon_set_cpu_freq(struct tpmon_data *data) if (!data->extra_data) return; - val = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; + val = tpmon_get_curr_level(data); mif_info("%s (freq:%d)\n", data->name, val); @@ -701,7 +715,7 @@ static int tpmon_cpufreq_nb(struct notifier_block *nb, if (event != CPUFREQ_CREATE_POLICY) return NOTIFY_OK; - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { switch (data->target) { case TPMON_TARGET_CPU_CL0: case TPMON_TARGET_CPU_CL1: @@ -740,27 +754,30 @@ static int tpmon_cpufreq_nb(struct notifier_block *nb, } #endif +/* PCIe power */ #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) static void tpmon_set_pci_low_power(struct tpmon_data *data) { struct modem_ctl *mc = data->tpmon->ld->mc; - u32 pci_low_power_value; + u32 val; if (!data->enable) return; - if (!mc || !mc->pcie_powered_on) - return; - - pci_low_power_value = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; + mutex_lock(&mc->pcie_check_lock); + if (!mc->pcie_powered_on || s51xx_check_pcie_link_status(mc->pcie_ch_num) == 0) + goto out; - s51xx_pcie_l1ss_ctrl((int)pci_low_power_value, mc->pcie_ch_num); + val = tpmon_get_curr_level(data); + mif_info("%s (enable:%u)\n", data->name, val); + s51xx_pcie_l1ss_ctrl((int)val, mc->pcie_ch_num); - mif_info("%s (enable:%u)\n", data->name, pci_low_power_value); +out: + mutex_unlock(&mc->pcie_check_lock); } #endif +/* Bus */ #if IS_ENABLED(CONFIG_EXYNOS_BTS) static void tpmon_set_bts(struct tpmon_data *data) { @@ -769,8 +786,7 @@ static void tpmon_set_bts(struct tpmon_data *data) if (!data->enable) return; - val = data->tpmon->use_user_value ? - data->user_value : data->values[data->curr_value_pos]; + val = tpmon_get_curr_level(data); mif_info("%s (val:%d)\n", data->name, val); @@ -781,93 +797,60 @@ static void tpmon_set_bts(struct tpmon_data *data) } #endif +/* + * Work + */ /* Monitor work */ static void tpmon_monitor_work(struct work_struct *ws) { - struct cpif_tpmon *tpmon = container_of(ws, struct cpif_tpmon, monitor_dwork.work); + struct cpif_tpmon *tpmon = container_of(ws, + struct cpif_tpmon, monitor_dwork.work); struct tpmon_data *data; - u64 jiffies_curr; + ktime_t curr_time; u64 delta_msec; if (tpmon_check_active()) { - tpmon_calc_rx_speed(tpmon); - tpmon_print_info(tpmon); + tpmon_stat_rx_speed(tpmon); + tpmon_calc_q_status(tpmon); + tpmon_print_stat(tpmon); } - if (atomic_read(&tpmon->need_urgent)) { - list_for_each_entry(data, &tpmon->urgent_data_list, urgent_data_node) { - if (!data->set_data) { - mif_err_limited("set_data is null:%s\n", data->name); - continue; - } - - if (tpmon_check_to_boost(data)) { - data->set_data(data); - continue; - } - } - } - - list_for_each_entry(data, &tpmon->data_list, data_node) { -#if IS_ENABLED(CONFIG_MCPS) - if (mcps_enable) { - switch (data->target) { - case TPMON_TARGET_RPS: - case TPMON_TARGET_GRO: - continue; - default: - break; - } - } -#endif - - if (!data->set_data) { - mif_err_limited("set_data is null:%s\n", data->name); - continue; - } + if (tpmon->use_user_level) + goto run_again; + list_for_each_entry(data, &tpmon->all_data_list, data_node) { if (atomic_read(&tpmon->need_init)) { data->set_data(data); continue; } - if (tpmon_check_to_boost(data)) { - data->set_data(data); - continue; - } - if (tpmon_check_to_unboost(data)) data->set_data(data); } - if (atomic_read(&tpmon->need_urgent)) - atomic_set(&tpmon->need_urgent, 0); - if (atomic_read(&tpmon->need_init)) { atomic_set(&tpmon->need_init, 0); return; } - jiffies_curr = get_jiffies_64(); - if (!tpmon->jiffies_to_trigger) - tpmon->jiffies_to_trigger = jiffies_curr; + curr_time = ktime_get(); + if (!tpmon->prev_monitor_time) + tpmon->prev_monitor_time = curr_time; - if (tpmon->rx_total.rx_mbps >= tpmon->monitor_stop_mbps) { - tpmon->jiffies_to_trigger = 0; + if (tpmon->rx_total_stat.rx_mbps >= tpmon->monitor_stop_mbps) { + tpmon->prev_monitor_time = 0; goto run_again; } - if (jiffies_curr > tpmon->jiffies_to_trigger) - delta_msec = jiffies64_to_msecs(jiffies_curr - tpmon->jiffies_to_trigger); - else - delta_msec = jiffies64_to_msecs(tpmon->jiffies_to_trigger - jiffies_curr); - + delta_msec = ktime_ms_delta(curr_time, tpmon->prev_monitor_time); if (delta_msec < tpmon->monitor_hold_msec) goto run_again; if (tpmon_check_active()) tpmon_stop(); + mif_info("monitor is stopped\n"); + return; run_again: @@ -875,6 +858,33 @@ static void tpmon_monitor_work(struct work_struct *ws) msecs_to_jiffies(tpmon->monitor_interval_msec)); } +/* Boost work */ +static void tpmon_boost_work(struct work_struct *ws) +{ + struct cpif_tpmon *tpmon = container_of(ws, + struct cpif_tpmon, boost_dwork.work); + struct tpmon_data *data; + + list_for_each_entry(data, &tpmon->all_data_list, data_node) { + if (!data->set_data) { + mif_err_limited("set_data is null:%s\n", data->name); + continue; + } + + if (data->need_boost) { + mif_info("set data name:%s\n", data->name); + data->set_data(data); + data->need_boost = false; + } + } + + if (!tpmon_check_active()) { + mif_info("start monitor\n"); + atomic_set(&tpmon->active, 1); + queue_delayed_work(tpmon->monitor_wq, &tpmon->monitor_dwork, 0); + } +} + /* * Control */ @@ -890,32 +900,32 @@ void tpmon_add_rx_bytes(struct sk_buff *skb) break; case 6: proto = ipv6_hdr(skb)->nexthdr; + if (proto == IPPROTO_FRAGMENT) + proto = skb->data[sizeof(struct ipv6hdr)]; break; default: mif_err_limited("Non IPv4/IPv6 packet:0x%x\n", ip_hdr(skb)->version); - return; + break; } spin_lock_irqsave(&tpmon->lock, flags); - if (tpmon->rx_bytes_skip_add) - goto skip_add; - tpmon->rx_total.rx_bytes += skb->len; - + tpmon->rx_total_stat.rx_bytes += skb->len; switch (proto) { case IPPROTO_TCP: tpmon->rx_tcp.rx_bytes += skb->len; + tpmon->rx_tcp_stat.rx_bytes += skb->len; break; case IPPROTO_UDP: tpmon->rx_udp.rx_bytes += skb->len; + tpmon->rx_udp_stat.rx_bytes += skb->len; break; default: tpmon->rx_others.rx_bytes += skb->len; + tpmon->rx_others_stat.rx_bytes += skb->len; break; } - -skip_add: spin_unlock_irqrestore(&tpmon->lock, flags); } EXPORT_SYMBOL(tpmon_add_rx_bytes); @@ -946,7 +956,7 @@ void tpmon_reset_data(char *name) struct cpif_tpmon *tpmon = &_tpmon; struct tpmon_data *data; - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { if (strncmp(data->name, name, strlen(name)) == 0) { data->set_data(data); break; @@ -955,6 +965,7 @@ void tpmon_reset_data(char *name) } EXPORT_SYMBOL(tpmon_reset_data); +/* Init */ static int tpmon_init_params(struct cpif_tpmon *tpmon) { struct tpmon_data *data; @@ -964,170 +975,82 @@ static int tpmon_init_params(struct cpif_tpmon *tpmon) memset(&tpmon->rx_udp, 0, sizeof(struct cpif_rx_data)); memset(&tpmon->rx_others, 0, sizeof(struct cpif_rx_data)); - tpmon->pktproc_queue_status = 0; - tpmon->netdev_backlog_queue_status = 0; - tpmon->dit_src_queue_status = 0; - tpmon->legacy_packet_count = 0; + memset(&tpmon->rx_total_stat, 0, sizeof(struct cpif_rx_data)); + memset(&tpmon->rx_tcp_stat, 0, sizeof(struct cpif_rx_data)); + memset(&tpmon->rx_udp_stat, 0, sizeof(struct cpif_rx_data)); + memset(&tpmon->rx_others_stat, 0, sizeof(struct cpif_rx_data)); - tpmon->jiffies_to_trigger = 0; - tpmon->rx_bytes_len = (MAX_RX_BYTES_COUNT / tpmon->monitor_interval_msec) ?: 1; - tpmon->rx_bytes_valid_cnt = tpmon->rx_bytes_len; + tpmon->q_status_pktproc_dl = 0; + tpmon->q_status_netdev_backlog = 0; + tpmon->q_status_dit_src = 0; + tpmon->legacy_packet_count = 0; - atomic_set(&tpmon->need_urgent, 0); - tpmon->urgent_active = false; + tpmon->prev_monitor_time = 0; - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { data->curr_threshold_pos = 0; data->prev_threshold_pos = 0; - data->curr_value_pos = 0; - data->prev_value_pos = 0; - data->jiffies_to_unboost = 0; - memset(data->unboost_tp_mbps, 0, sizeof(data->unboost_tp_mbps)); - data->forced_unboost = false; - data->enable = 1; + data->curr_level_pos = 0; + data->prev_level_pos = 0; + data->prev_unboost_time = 0; + data->need_boost = false; } return 0; } -static bool tpmon_check_urgent(struct cpif_tpmon *tpmon) +static void tpmon_check_q_status(struct cpif_tpmon *tpmon) { struct tpmon_data *data; - int usage; - int i; - - if (tpmon->urgent_active && atomic_read(&tpmon->need_urgent)) - return false; + bool run_work = false; - list_for_each_entry(data, &tpmon->urgent_data_list, urgent_data_node) { - usage = data->get_data(data); - if (usage < 0) { - mif_err_limited("get_data(%s) error:%d\n", data->name, usage); - return false; - } - - for (i = 0; i < data->num_threshold; i++) - if (usage < data->threshold[i]) - break; - - if (i <= data->curr_value_pos) + list_for_each_entry(data, &tpmon->q_status_list, q_status_node) { + if (data->need_boost) continue; - if (i >= data->num_values) { - mif_err_limited("Invalid value:%s %d %d\n", - data->name, i, data->num_values); + if (!tpmon_check_to_boost(data)) continue; - } - mif_info("urgent:%s\n", data->name); - atomic_set(&tpmon->need_urgent, 1); - tpmon->urgent_active = true; - return true; + mif_debug("need to run work for %s\n", data->name); + run_work = true; } - return false; + if (run_work) + queue_delayed_work(tpmon->boost_wq, &tpmon->boost_dwork, 0); } -static bool tpmon_check_to_start(struct cpif_tpmon *tpmon) +static void tpmon_check_tp_status(struct cpif_tpmon *tpmon) { - u64 jiffies_curr; - u64 delta_msec; - unsigned long flags; - - jiffies_curr = get_jiffies_64(); - if (!tpmon->jiffies_to_trigger) { - tpmon->jiffies_to_trigger = jiffies_curr; - return false; - } - - if (jiffies_curr > tpmon->jiffies_to_trigger) - delta_msec = jiffies64_to_msecs(jiffies_curr - tpmon->jiffies_to_trigger); - else - delta_msec = jiffies64_to_msecs(tpmon->jiffies_to_trigger - jiffies_curr); - - if (delta_msec > tpmon->trigger_msec_max) { - tpmon->jiffies_to_trigger = jiffies_curr; - tpmon->rx_total.rx_bytes = 0; - tpmon->rx_tcp.rx_bytes = 0; - tpmon->rx_udp.rx_bytes = 0; - tpmon->rx_others.rx_bytes = 0; - tpmon->legacy_packet_count = 0; - return false; - } - - if (!delta_msec || delta_msec < tpmon->trigger_msec_min) - return false; - - if (delta_msec >= 1000) { - tpmon->rx_total.rx_mbps = tpmon->rx_total.rx_bytes / (131072 * delta_msec / 1000); - tpmon->rx_total.rx_kbps = tpmon->rx_total.rx_bytes / (128 * delta_msec / 1000); - } else { - tpmon->rx_total.rx_mbps = (tpmon->rx_total.rx_bytes * 1000 / delta_msec) / 131072; - tpmon->rx_total.rx_kbps = (tpmon->rx_total.rx_bytes * 1000 / delta_msec) / 128; - } + struct tpmon_data *data; + bool run_work = false; - if (tpmon->debug_print) - mif_info_limited("%ldMbps(%ldKbps) %llumsec rx_bytes:%ld(%ld/%ld/%ld) legacy:%d\n", - tpmon->rx_total.rx_mbps, tpmon->rx_total.rx_kbps, delta_msec, - tpmon->rx_total.rx_bytes, tpmon->rx_tcp.rx_bytes, - tpmon->rx_udp.rx_bytes, tpmon->rx_others.rx_bytes, - tpmon->legacy_packet_count); + list_for_each_entry(data, &tpmon->tp_node_list, tp_node) { + if (data->need_boost) + continue; - tpmon->jiffies_to_trigger = jiffies_curr; + if (!tpmon_check_to_boost(data)) + continue; - if ((tpmon->rx_total.rx_mbps < tpmon->trigger_mbps) || tpmon->use_user_value) { - tpmon->rx_total.rx_bytes = 0; - tpmon->rx_tcp.rx_bytes = 0; - tpmon->rx_udp.rx_bytes = 0; - tpmon->rx_others.rx_bytes = 0; - tpmon->legacy_packet_count = 0; - return false; + mif_debug("need to run work for %s\n", data->name); + run_work = true; } - mif_info("trigger@%ldMbps\n", tpmon->rx_total.rx_mbps); - - spin_lock_irqsave(&tpmon->lock, flags); - tpmon->rx_bytes_skip_add = true; - - /* Normalize rx_bytes by interval */ - tpmon->rx_total.rx_bytes *= tpmon->monitor_interval_msec; - tpmon->rx_total.rx_bytes /= delta_msec; - tpmon->rx_tcp.rx_bytes *= tpmon->monitor_interval_msec; - tpmon->rx_tcp.rx_bytes /= delta_msec; - tpmon->rx_udp.rx_bytes *= tpmon->monitor_interval_msec; - tpmon->rx_udp.rx_bytes /= delta_msec; - tpmon->rx_others.rx_bytes *= tpmon->monitor_interval_msec; - tpmon->rx_others.rx_bytes /= delta_msec; - spin_unlock_irqrestore(&tpmon->lock, flags); - - tpmon->rx_bytes_valid_cnt = 0; - - return true; + if (run_work) + queue_delayed_work(tpmon->boost_wq, &tpmon->boost_dwork, 0); } int tpmon_start(void) { struct cpif_tpmon *tpmon = &_tpmon; - if (tpmon_check_urgent(tpmon)) { - mif_info("need urgent\n"); - goto run_monitor; - } - - if (tpmon_check_active()) + if (tpmon->use_user_level) return 0; - if (!tpmon_check_to_start(tpmon)) - return 0; + tpmon_calc_q_status(tpmon); + tpmon_check_q_status(tpmon); -run_monitor: - atomic_set(&tpmon->active, 1); - - cancel_delayed_work(&tpmon->monitor_dwork); - queue_delayed_work(tpmon->monitor_wq, &tpmon->monitor_dwork, 0); - - if (tpmon->debug_print) - mif_info("started\n"); + tpmon_calc_rx_speed(tpmon); + tpmon_check_tp_status(tpmon); return 0; } @@ -1141,12 +1064,13 @@ int tpmon_stop(void) if (!tpmon_check_active()) return 0; + cancel_delayed_work(&tpmon->boost_dwork); cancel_delayed_work(&tpmon->monitor_dwork); atomic_set(&tpmon->active, 0); - list_for_each_entry(data, &tpmon->data_list, data_node) { - if (data->curr_value_pos != 0) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { + if (data->curr_level_pos != 0) { atomic_set(&tpmon->need_init, 1); break; } @@ -1157,9 +1081,6 @@ int tpmon_stop(void) if (atomic_read(&tpmon->need_init)) queue_delayed_work(tpmon->monitor_wq, &tpmon->monitor_dwork, 0); - if (tpmon->debug_print) - mif_info("stopped\n"); - return 0; } EXPORT_SYMBOL(tpmon_stop); @@ -1168,9 +1089,9 @@ int tpmon_init(void) { struct cpif_tpmon *tpmon = &_tpmon; - if (tpmon->use_user_value) { - mif_info("enable use_user_value again if you want to set user value\n"); - tpmon->use_user_value = 0; + if (tpmon->use_user_level) { + mif_info("enable use_user_level again if you want to set user level\n"); + tpmon->use_user_level = 0; } if (tpmon_check_active()) @@ -1178,7 +1099,7 @@ int tpmon_init(void) tpmon_init_params(tpmon); - mif_info("set initial values\n"); + mif_info("set initial level\n"); atomic_set(&tpmon->need_init, 1); queue_delayed_work(tpmon->monitor_wq, &tpmon->monitor_dwork, 0); @@ -1197,69 +1118,39 @@ EXPORT_SYMBOL(tpmon_check_active); /* * sysfs */ -static ssize_t dt_value_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t dt_level_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cpif_tpmon *tpmon = &_tpmon; struct tpmon_data *data; ssize_t len = 0; int i = 0; - list_for_each_entry(data, &tpmon->data_list, data_node) { - len += scnprintf(buf + len, PAGE_SIZE - len, "%s threshold: ", data->name); + list_for_each_entry(data, &tpmon->all_data_list, data_node) { + len += scnprintf(buf + len, PAGE_SIZE - len, + "%s threshold: ", data->name); for (i = 0; i < data->num_threshold; i++) - len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", data->threshold[i]); + len += scnprintf(buf + len, PAGE_SIZE - len, + "%d ", data->threshold[i]); len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); - len += scnprintf(buf + len, PAGE_SIZE - len, "%s values: ", data->name); + len += scnprintf(buf + len, PAGE_SIZE - len, + "%s level: ", data->name); - for (i = 0; i < data->num_values; i++) + for (i = 0; i < data->num_level; i++) len += scnprintf(buf + len, PAGE_SIZE - len, "0x%x(%d) ", - data->values[i], data->values[i]); + data->level[i], data->level[i]); len += scnprintf(buf + len, PAGE_SIZE - len, "\n\n"); } return len; } -static DEVICE_ATTR_RO(dt_value); - -static ssize_t curr_value_show(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct cpif_tpmon *tpmon = &_tpmon; - struct tpmon_data *data; - ssize_t len = 0; - int ret = 0; - - list_for_each_entry(data, &tpmon->data_list, data_node) { - ret = tpmon->use_user_value ? data->user_value : data->values[data->curr_value_pos]; - - len += scnprintf(buf + len, PAGE_SIZE - len, "%s: enable:%d", - data->name, data->enable); - - if (!data->enable) { - len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); - continue; - } - - len += scnprintf(buf + len, PAGE_SIZE - len, " val:%d(0x%x)", - ret, ret); - - if (tpmon->use_user_value) - len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); - else - len += scnprintf(buf + len, PAGE_SIZE - len, - " pos:%d unboost@%dMbps forced_unboost:%d urgent:%d\n", - data->curr_value_pos, - data->unboost_tp_mbps[data->curr_threshold_pos], - data->forced_unboost, data->urgent); - } - - return len; -} -static DEVICE_ATTR_RO(curr_value); +static DEVICE_ATTR_RO(dt_level); -static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t curr_level_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cpif_tpmon *tpmon = &_tpmon; struct tpmon_data *data; @@ -1267,46 +1158,17 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch int i; len += scnprintf(buf + len, PAGE_SIZE - len, - "start at %dMbps min:%dmsec max:%dmsec\n", - tpmon->trigger_mbps, tpmon->trigger_msec_min, - tpmon->trigger_msec_max); + "trigger min:%dmsec max:%dmsec\n", + tpmon->trigger_msec_min, tpmon->trigger_msec_max); len += scnprintf(buf + len, PAGE_SIZE - len, "monitor interval:%dmsec hold:%dmsec stop:%dMbps\n", tpmon->monitor_interval_msec, tpmon->monitor_hold_msec, tpmon->monitor_stop_mbps); len += scnprintf(buf + len, PAGE_SIZE - len, - "boost hold:%dmsec unboost_percent:%d\n", - tpmon->boost_hold_msec, - tpmon->unboost_tp_percent); - len += scnprintf(buf + len, PAGE_SIZE - len, - "rx_total %ldbytes %ldMbps %ldKbps sum:%lu\n", - tpmon->rx_total.rx_bytes, tpmon->rx_total.rx_mbps, - tpmon->rx_total.rx_kbps, tpmon->rx_total.rx_sum); - len += scnprintf(buf + len, PAGE_SIZE - len, - "rx_tcp %ldbytes %ldMbps %ldKbps sum:%lu\n", - tpmon->rx_tcp.rx_bytes, tpmon->rx_tcp.rx_mbps, - tpmon->rx_tcp.rx_kbps, tpmon->rx_tcp.rx_sum); - len += scnprintf(buf + len, PAGE_SIZE - len, - "rx_udp %ldbytes %ldMbps %ldKbps sum:%lu\n", - tpmon->rx_udp.rx_bytes, tpmon->rx_udp.rx_mbps, - tpmon->rx_udp.rx_kbps, tpmon->rx_udp.rx_sum); - len += scnprintf(buf + len, PAGE_SIZE - len, - "rx_others %ldbytes %ldMbps %ldKbps sum:%lu\n", - tpmon->rx_others.rx_bytes, tpmon->rx_others.rx_mbps, - tpmon->rx_others.rx_kbps, tpmon->rx_others.rx_sum); - len += scnprintf(buf + len, PAGE_SIZE - len, - "queue status pktproc:%d dit:%d netdev:%d legacy:%d\n", - tpmon->pktproc_queue_status, - tpmon->dit_src_queue_status, - tpmon->netdev_backlog_queue_status, - tpmon->legacy_packet_count); - len += scnprintf(buf + len, PAGE_SIZE - len, - "use_user_value:%d debug_print:%d\n", - tpmon->use_user_value, - tpmon->debug_print); + "boost hold:%dmsec\n", tpmon->boost_hold_msec); - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); len += scnprintf(buf + len, PAGE_SIZE - len, "name:%s measure:%d target:%d enable:%d extra_idx:%d proto:%d\n", @@ -1318,86 +1180,143 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch for (i = 0; i < data->num_threshold; i++) len += scnprintf(buf + len, PAGE_SIZE - len, "%d(unboost@%dMbps) ", - data->threshold[i], data->unboost_tp_mbps[i]); + data->threshold[i], data->unboost_threshold_mbps[i]); len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); len += scnprintf(buf + len, PAGE_SIZE - len, - "num_values:%d\n", data->num_values); - for (i = 0; i < data->num_values; i++) + "num_level:%d\n", data->num_level); + for (i = 0; i < data->num_level; i++) len += scnprintf(buf + len, PAGE_SIZE - len, - "%d ", data->values[i]); + "%d ", data->level[i]); len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); len += scnprintf(buf + len, PAGE_SIZE - len, - "curr_value_pos:%d user_value:%d\n", - data->curr_value_pos, data->user_value); + "curr_level_pos:%d user_level:%d\n", + data->curr_level_pos, data->user_level); + } - len += scnprintf(buf + len, PAGE_SIZE - len, - "check_udp:%d forced_unboost:%d urgent:%d\n", - data->check_udp, data->forced_unboost, data->urgent); + return len; +} +static DEVICE_ATTR_RO(curr_level); + +static ssize_t status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cpif_tpmon *tpmon = &_tpmon; + struct tpmon_data *data; + ssize_t len = 0; + u32 val = 0; + + len += scnprintf(buf + len, PAGE_SIZE - len, + "rx_total %ldbytes %ldMbps\n", + tpmon->rx_total.rx_bytes, tpmon->rx_total.rx_mbps); + len += scnprintf(buf + len, PAGE_SIZE - len, + "rx_tcp %ldbytes %ldMbps\n", + tpmon->rx_tcp.rx_bytes, tpmon->rx_tcp.rx_mbps); + len += scnprintf(buf + len, PAGE_SIZE - len, + "rx_udp %ldbytes %ldMbps\n", + tpmon->rx_udp.rx_bytes, tpmon->rx_udp.rx_mbps); + len += scnprintf(buf + len, PAGE_SIZE - len, + "rx_others %ldbytes %ldMbps\n", + tpmon->rx_others.rx_bytes, tpmon->rx_others.rx_mbps); + + len += scnprintf(buf + len, PAGE_SIZE - len, + "queue status pktproc:%d dit:%d netdev:%d legacy:%d\n", + tpmon->q_status_pktproc_dl, + tpmon->q_status_dit_src, + tpmon->q_status_netdev_backlog, + tpmon->legacy_packet_count); + len += scnprintf(buf + len, PAGE_SIZE - len, + "use_user_level:%d debug_print:%d\n", + tpmon->use_user_level, + tpmon->debug_print); + + list_for_each_entry(data, &tpmon->all_data_list, data_node) { + len += scnprintf(buf + len, PAGE_SIZE - len, "%s: enable:%d", + data->name, data->enable); + + if (!data->enable) { + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); + continue; + } + + val = tpmon_get_curr_level(data); + len += scnprintf(buf + len, PAGE_SIZE - len, " val:%d(0x%x)", + val, val); + + if (tpmon->use_user_level) + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); + else + len += scnprintf(buf + len, PAGE_SIZE - len, + " pos:%d unboost@%dMbps\n", + data->curr_level_pos, + data->curr_level_pos ? + data->unboost_threshold_mbps[data->curr_threshold_pos] : 0); } return len; } static DEVICE_ATTR_RO(status); -static ssize_t use_user_value_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t use_user_level_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cpif_tpmon *tpmon = &_tpmon; - return scnprintf(buf, PAGE_SIZE, "use_user_value:%d\n", tpmon->use_user_value); + return scnprintf(buf, PAGE_SIZE, "use_user_level:%d\n", + tpmon->use_user_level); } -static ssize_t use_user_value_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t use_user_level_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) { struct cpif_tpmon *tpmon = &_tpmon; struct tpmon_data *data; int ret; - int value; + int level; - ret = kstrtoint(buf, 0, &value); + ret = kstrtoint(buf, 0, &level); if (ret != 0) { - mif_err("invalid value:%d with %d\n", value, ret); + mif_err("invalid level:%d with %d\n", level, ret); return -EINVAL; } - tpmon->use_user_value = value; - mif_info("use_user_value:%d\n", tpmon->use_user_value); + tpmon->use_user_level = level; + mif_info("use_user_level:%d\n", tpmon->use_user_level); - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { if (data->set_data) { - data->user_value = data->values[0]; - data->set_data(data); + data->user_level = data->level[data->curr_level_pos]; } } - tpmon_stop(); return count; } -static DEVICE_ATTR_RW(use_user_value); +static DEVICE_ATTR_RW(use_user_level); -static ssize_t debug_print_show(struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t debug_print_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct cpif_tpmon *tpmon = &_tpmon; - return scnprintf(buf, PAGE_SIZE, "debug pring enable:%d\n", tpmon->debug_print); + return scnprintf(buf, PAGE_SIZE, + "debug pring enable:%d\n", tpmon->debug_print); } -static ssize_t debug_print_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t debug_print_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) { struct cpif_tpmon *tpmon = &_tpmon; int ret; - int value; + int level; - ret = kstrtoint(buf, 0, &value); + ret = kstrtoint(buf, 0, &level); if (ret != 0) { - mif_err("invalid value:%d with %d\n", value, ret); + mif_err("invalid level:%d with %d\n", level, ret); return -EINVAL; } - tpmon->debug_print = value; + tpmon->debug_print = level; mif_info("debug pring enable:%d\n", tpmon->debug_print); @@ -1405,44 +1324,44 @@ static ssize_t debug_print_store(struct device *dev, struct device_attribute *at } static DEVICE_ATTR_RW(debug_print); -static ssize_t set_user_value_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) +static ssize_t set_user_level_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) { struct cpif_tpmon *tpmon = &_tpmon; struct tpmon_data *data; char name[20]; - int value; + int level; int ret; - if (!tpmon->use_user_value) { - mif_info("use_user_value is not set\n"); + if (!tpmon->use_user_level) { + mif_info("use_user_level is not set\n"); return count; } - ret = sscanf(buf, "%19s %i", name, &value); + ret = sscanf(buf, "%19s %i", name, &level); if (ret < 1) return -EINVAL; - mif_info("Change %s to %d(0x%x)\n", name, value, value); + mif_info("Change %s to %d(0x%x)\n", name, level, level); - list_for_each_entry(data, &tpmon->data_list, data_node) { + list_for_each_entry(data, &tpmon->all_data_list, data_node) { if (strcmp(data->name, name) == 0) { - data->user_value = value; + data->user_level = level; data->set_data(data); } } return count; } -static DEVICE_ATTR_WO(set_user_value); +static DEVICE_ATTR_WO(set_user_level); static struct attribute *tpmon_attrs[] = { - &dev_attr_dt_value.attr, - &dev_attr_curr_value.attr, + &dev_attr_dt_level.attr, + &dev_attr_curr_level.attr, &dev_attr_status.attr, - &dev_attr_use_user_value.attr, + &dev_attr_use_user_level.attr, &dev_attr_debug_print.attr, - &dev_attr_set_user_value.attr, + &dev_attr_set_user_level.attr, NULL, }; @@ -1454,294 +1373,266 @@ static const struct attribute_group tpmon_group = { /* * Init */ -static void tpmon_parse_protocol(struct tpmon_data *data) +static int tpmon_set_cpufreq(struct tpmon_data *data) { - switch (data->proto) { - case TPMON_PROTO_TCP: - data->get_data = tpmon_get_rx_tcp_speed_mbps; +#if IS_ENABLED(CONFIG_CPU_FREQ) + struct cpif_tpmon *tpmon = data->tpmon; + struct cpufreq_policy *policy; + int qos_type; + + switch (data->target) { + case TPMON_TARGET_CPU_CL0: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl0; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MIN; break; - case TPMON_PROTO_UDP: - data->get_data = tpmon_get_rx_udp_speed_mbps; + case TPMON_TARGET_CPU_CL0_MAX: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl0_max; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MAX; break; - case TPMON_PROTO_OTHERS: - data->get_data = tpmon_get_rx_others_speed_mbps; + case TPMON_TARGET_CPU_CL1: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl1; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MIN; break; - case TPMON_PROTO_ALL: - default: - data->get_data = tpmon_get_rx_total_speed_mbps; + case TPMON_TARGET_CPU_CL1_MAX: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl1_max; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MAX; break; + case TPMON_TARGET_CPU_CL2: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl2; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MIN; + break; + case TPMON_TARGET_CPU_CL2_MAX: + data->extra_data = (void *)&tpmon->qos_req_cpu_cl2_max; + data->set_data = tpmon_set_cpu_freq; + qos_type = FREQ_QOS_MAX; + break; + default: + mif_err_limited("no target\n"); + return -EINVAL; } -} -static int tpmon_parse_dt(struct device_node *np, struct cpif_tpmon *tpmon) -{ - struct device_node *tpmon_np = NULL; - struct device_node *child_np = NULL; - struct tpmon_data *data = NULL; - int ret = 0; - u32 count = 0; - unsigned long flags; - - tpmon_np = of_get_child_by_name(np, "cpif_tpmon"); - if (!tpmon_np) { - mif_err("tpmon_np is null\n"); - return -ENODEV; + if (tpmon->cpufreq_nb.notifier_call) { + mif_info("notifier_call is registered\n"); + return 0; } - mif_dt_read_u32(tpmon_np, "tpmon_trigger_mbps", - tpmon->trigger_mbps); - mif_dt_read_u32(tpmon_np, "tpmon_trigger_msec_min", - tpmon->trigger_msec_min); - mif_dt_read_u32(tpmon_np, "tpmon_trigger_msec_max", - tpmon->trigger_msec_max); - mif_info("trigger:%dMbps min:%dmsec max:%dmsec\n", - tpmon->trigger_mbps, tpmon->trigger_msec_min, - tpmon->trigger_msec_max); - - mif_dt_read_u32(tpmon_np, "tpmon_monitor_interval_msec", - tpmon->monitor_interval_msec); - mif_dt_read_u32(tpmon_np, "tpmon_monitor_hold_msec", - tpmon->monitor_hold_msec); - mif_dt_read_u32(tpmon_np, "tpmon_monitor_stop_mbps", - tpmon->monitor_stop_mbps); - mif_info("monitor interval:%dmsec hold:%dmsec stop:%dmbps\n", - tpmon->monitor_interval_msec, tpmon->monitor_hold_msec, - tpmon->monitor_stop_mbps); - - mif_dt_read_u32(tpmon_np, "tpmon_boost_hold_msec", - tpmon->boost_hold_msec); - mif_dt_read_u32(tpmon_np, "tpmon_unboost_tp_percent", - tpmon->unboost_tp_percent); - mif_info("boost hold:%dmsec unboost percent:%d\n", - tpmon->boost_hold_msec, - tpmon->unboost_tp_percent); - - for_each_child_of_node(tpmon_np, child_np) { - if (count >= MAX_TPMON_DATA) { - mif_err("count is full:%d\n", count); - return -EINVAL; - } - - data = &tpmon->data[count]; - memset(data, 0, sizeof(struct tpmon_data)); - - /* name */ - ret = of_property_read_string(child_np, "tpmon,name", - (const char **)&data->name); - if (ret < 0) { - mif_info("can not get %u tpmon,name:%d\n", count, ret); - return ret; - } - - /* enable */ - ret = of_property_read_u32(child_np, "tpmon,enable", &data->enable); - if (ret || !data->enable) { - mif_info("%s is not enabled:%d %d\n", - data->name, ret, data->enable); - continue; - } + policy = cpufreq_cpu_get(data->extra_idx); + if (!policy) { + mif_err_limited("cpufreq_cpu_get() error\n"); + return -EINVAL; + } - /* measure */ - ret = of_property_read_u32(child_np, "tpmon,measure", &data->measure); - if (ret) { - mif_info("can not get tpmon,measure:%s %d %d %d\n", - data->name, count, ret, data->measure); - return ret; - } + if (policy->cpu == data->extra_idx) { + mif_info("freq_qos_add_request for cpu%d %d\n", + policy->cpu, qos_type); +#if IS_ENABLED(CONFIG_ARM_FREQ_QOS_TRACER) + freq_qos_tracer_add_request(&policy->constraints, + data->extra_data, qos_type, PM_QOS_DEFAULT_VALUE); +#else + freq_qos_add_request(&policy->constraints, + data->extra_data, qos_type, PM_QOS_DEFAULT_VALUE); +#endif + } +#endif /* CONFIG_CPU_FREQ */ - switch (data->measure) { - case TPMON_MEASURE_TP: - /* protocol */ - ret = of_property_read_u32(child_np, "tpmon,proto", &data->proto); - if (ret) { - mif_info("can not get tpmon,proto. set to all\n"); - data->proto = TPMON_PROTO_ALL; - } - tpmon_parse_protocol(data); - break; - case TPMON_MEASURE_NETDEV_Q: - data->get_data = tpmon_get_netdev_backlog_queue_status; - break; - case TPMON_MEASURE_PKTPROC_DL_Q: - data->get_data = tpmon_get_pktproc_queue_status; - break; - case TPMON_MEASURE_DIT_SRC_Q: - data->get_data = tpmon_get_dit_src_queue_status; - break; - default: - mif_err("%s measure error:%d %d\n", data->name, count, data->measure); - return -EINVAL; - } + return 0; +} - /* target */ - ret = of_property_read_u32(child_np, "tpmon,target", &data->target); - if (ret) { - mif_info("can not get tpmon,target:%s %d %d %d\n", - data->name, count, ret, data->target); - return ret; - } +static int tpmon_set_target(struct tpmon_data *data) +{ + struct cpif_tpmon *tpmon = data->tpmon; + int ret = 0; - switch (data->target) { + switch (data->target) { #if IS_ENABLED(CONFIG_RPS) - case TPMON_TARGET_RPS: - data->set_data = tpmon_set_rps; - break; + case TPMON_TARGET_RPS: + data->set_data = tpmon_set_rps; + break; #endif - case TPMON_TARGET_GRO: - data->set_data = tpmon_set_gro; - break; + case TPMON_TARGET_GRO: + data->set_data = tpmon_set_gro; + break; #if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) - case TPMON_TARGET_MIF: - data->extra_data = (void *)&tpmon->qos_req_mif; - data->set_data = tpmon_set_exynos_pm_qos; - break; - case TPMON_TARGET_MIF_MAX: - data->extra_data = (void *)&tpmon->qos_req_mif_max; - data->set_data = tpmon_set_exynos_pm_qos; - break; - case TPMON_TARGET_INT_FREQ: - data->extra_data = (void *)&tpmon->qos_req_int; - data->set_data = tpmon_set_exynos_pm_qos; - break; - case TPMON_TARGET_INT_FREQ_MAX: - data->extra_data = (void *)&tpmon->qos_req_int_max; - data->set_data = tpmon_set_exynos_pm_qos; - break; + case TPMON_TARGET_MIF: + data->extra_data = (void *)&tpmon->qos_req_mif; + data->set_data = tpmon_set_exynos_pm_qos; + break; + case TPMON_TARGET_MIF_MAX: + data->extra_data = (void *)&tpmon->qos_req_mif_max; + data->set_data = tpmon_set_exynos_pm_qos; + break; + case TPMON_TARGET_INT_FREQ: + data->extra_data = (void *)&tpmon->qos_req_int; + data->set_data = tpmon_set_exynos_pm_qos; + break; + case TPMON_TARGET_INT_FREQ_MAX: + data->extra_data = (void *)&tpmon->qos_req_int_max; + data->set_data = tpmon_set_exynos_pm_qos; + break; #endif #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) - case TPMON_TARGET_PCIE_LOW_POWER: - data->set_data = tpmon_set_pci_low_power; - break; - case TPMON_TARGET_IRQ_PCIE: - data->set_data = tpmon_set_irq_affinity_pcie; - break; + case TPMON_TARGET_PCIE_LOW_POWER: + data->set_data = tpmon_set_pci_low_power; + break; + case TPMON_TARGET_IRQ_PCIE: + data->set_data = tpmon_set_irq_affinity_pcie; + break; #endif #if IS_ENABLED(CONFIG_MCU_IPC) - case TPMON_TARGET_IRQ_MBOX: - data->set_data = tpmon_set_irq_affinity_mbox; - break; + case TPMON_TARGET_IRQ_MBOX: + data->set_data = tpmon_set_irq_affinity_mbox; + break; #endif #if IS_ENABLED(CONFIG_EXYNOS_DIT) - case TPMON_TARGET_IRQ_DIT: - data->set_data = tpmon_set_irq_affinity_dit; - break; + case TPMON_TARGET_IRQ_DIT: + data->set_data = tpmon_set_irq_affinity_dit; + break; #endif #if IS_ENABLED(CONFIG_EXYNOS_BTS) - case TPMON_TARGET_BTS: - data->set_data = tpmon_set_bts; - break; + case TPMON_TARGET_BTS: + data->set_data = tpmon_set_bts; + break; #endif #if IS_ENABLED(CONFIG_CPU_FREQ) - case TPMON_TARGET_CPU_CL0: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl0; - data->set_data = tpmon_set_cpu_freq; - break; - case TPMON_TARGET_CPU_CL0_MAX: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl0_max; - data->set_data = tpmon_set_cpu_freq; - break; - case TPMON_TARGET_CPU_CL1: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl1; - data->set_data = tpmon_set_cpu_freq; - break; - case TPMON_TARGET_CPU_CL1_MAX: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl1_max; - data->set_data = tpmon_set_cpu_freq; - break; - case TPMON_TARGET_CPU_CL2: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl2; - data->set_data = tpmon_set_cpu_freq; - break; - case TPMON_TARGET_CPU_CL2_MAX: - data->extra_data = (void *)&tpmon->qos_req_cpu_cl2_max; - data->set_data = tpmon_set_cpu_freq; - break; -#endif - default: - mif_err("%s target error:%d %d\n", data->name, count, data->target); - continue; - } - - /* extra_idx */ - ret = of_property_read_u32(child_np, "tpmon,idx", - &data->extra_idx); + case TPMON_TARGET_CPU_CL0: + case TPMON_TARGET_CPU_CL0_MAX: + case TPMON_TARGET_CPU_CL1: + case TPMON_TARGET_CPU_CL1_MAX: + case TPMON_TARGET_CPU_CL2: + case TPMON_TARGET_CPU_CL2_MAX: + ret = tpmon_set_cpufreq(data); if (ret) { - mif_info("can not get tpmon,extra_idx:%s, %d %d %d %d\n", - data->name, data->measure, data->target, - ret, data->extra_idx); + mif_err("tpmon_set_cpufreq() error:%d\n", ret); return ret; } + break; +#endif - /* threshold */ - ret = of_property_count_u32_elems(child_np, "tpmon,threshold"); - if (ret < 0) { - mif_err("can not get num_threshold:%s %d %d %d\n", - data->name, data->measure, data->target, ret); - return ret; - } - data->num_threshold = ret; - if (data->num_threshold > MAX_TPMON_THRESHOLD) { - mif_err("num_threshold is over max:%s %d %d %d\n", - data->name, data->measure, data->target, - data->num_threshold); - return -EINVAL; - } - ret = of_property_read_u32_array(child_np, "tpmon,threshold", - data->threshold, data->num_threshold); - if (ret) { - mif_err("can not get threshold:%s %d %d %d\n", - data->name, data->measure, data->target, ret); - return ret; - } + default: + mif_err("%s target error:%d\n", data->name, data->target); + return -EINVAL; + } - /* values */ - ret = of_property_count_u32_elems(child_np, "tpmon,values"); - if (ret < 0) { - mif_err("can not get num_values:%s %d %d %d\n", - data->name, data->measure, data->target, ret); - return -EINVAL; - } - data->num_values = ret; - if (data->num_values > MAX_TPMON_VALUES) { - mif_err("num_values is over max:%s %d %d %d\n", - data->name, data->measure, data->target, data->num_values); - return -EINVAL; - } - ret = of_property_read_u32_array(child_np, "tpmon,values", - data->values, data->num_values); - if (ret) { - mif_err("can not get values:%s %d %d %d\n", - data->name, data->measure, data->target, ret); - return ret; - } + return 0; +} + +static int tpmon_parse_dt(struct device_node *np, struct cpif_tpmon *tpmon) +{ + struct device_node *tpmon_np = NULL; + struct device_node *child_np = NULL; + struct device_node *boost_np = NULL; + struct tpmon_data *data = NULL; + int ret = 0; + u32 count = 0; + unsigned long flags; + + tpmon_np = of_get_child_by_name(np, "cpif_tpmon"); + if (!tpmon_np) { + mif_err("tpmon_np is null\n"); + return -ENODEV; + } + + mif_dt_read_u32(tpmon_np, "trigger_msec_min", tpmon->trigger_msec_min); + mif_dt_read_u32(tpmon_np, "trigger_msec_max", tpmon->trigger_msec_max); + mif_info("trigger min:%dmsec max:%dmsec\n", + tpmon->trigger_msec_min, tpmon->trigger_msec_max); + + mif_dt_read_u32(tpmon_np, "monitor_interval_msec", + tpmon->monitor_interval_msec); + mif_dt_read_u32(tpmon_np, "monitor_hold_msec", + tpmon->monitor_hold_msec); + mif_dt_read_u32(tpmon_np, "monitor_stop_mbps", + tpmon->monitor_stop_mbps); + mif_info("monitor interval:%dmsec hold:%dmsec stop:%dmbps\n", + tpmon->monitor_interval_msec, tpmon->monitor_hold_msec, + tpmon->monitor_stop_mbps); - /* check_udp */ - of_property_read_u32(child_np, "tpmon,check_udp", &data->check_udp); + mif_dt_read_u32(tpmon_np, "boost_hold_msec", tpmon->boost_hold_msec); + mif_info("boost hold:%dmsec\n", tpmon->boost_hold_msec); - /* urgent */ - of_property_read_u32(child_np, "tpmon,urgent", &data->urgent); + for_each_child_of_node(tpmon_np, child_np) { + struct tpmon_data child_data = {}; + + mif_dt_read_string(child_np, "boost_name", child_data.name); + mif_dt_read_u32(child_np, "target", child_data.target); + mif_dt_read_u32(child_np, "extra_idx", child_data.extra_idx); + mif_dt_count_u32_elems(child_np, "level", child_data.num_level); + mif_dt_count_u32_array(child_np, "level", + child_data.level, child_data.num_level); + + /* boost */ + for_each_child_of_node(child_np, boost_np) { + if (count >= MAX_TPMON_DATA) { + mif_err("count is full:%d\n", count); + return -EINVAL; + } - data->tpmon = tpmon; + data = &tpmon->data[count]; + memcpy(data, &child_data, sizeof(child_data)); + data->tpmon = tpmon; - spin_lock_irqsave(&tpmon->lock, flags); - list_add_tail(&data->data_node, &tpmon->data_list); - if (data->urgent) - list_add_tail(&data->urgent_data_node, &tpmon->urgent_data_list); - spin_unlock_irqrestore(&tpmon->lock, flags); + /* check enabled */ + mif_dt_read_u32(boost_np, "enable", data->enable); + if (!data->enable) + continue; - mif_info("name:%s measure:%d target:%d enable:%d idx:%d num:%d/%d proto:%d check_udp:%d urgent:%d\n", - data->name, data->measure, data->target, data->enable, - data->extra_idx, data->num_threshold, data->num_values, - data->proto, data->check_udp, data->urgent); + /* threshold */ + mif_dt_count_u32_elems(boost_np, "boost_threshold", + data->num_threshold); + mif_dt_count_u32_array(boost_np, "boost_threshold", + data->threshold, data->num_threshold); + mif_dt_count_u32_array(boost_np, "unboost_threshold_mbps", + data->unboost_threshold_mbps, data->num_threshold); - count++; + /* target */ + ret = tpmon_set_target(data); + if (ret) { + mif_err("tpmon_set_target() error:%d\n", ret); + continue; + } + + /* measure */ + mif_dt_read_u32(boost_np, "proto", data->proto); + mif_dt_read_u32(boost_np, "measure", data->measure); + spin_lock_irqsave(&tpmon->lock, flags); + switch (data->measure) { + case TPMON_MEASURE_TP: + data->get_data = tpmon_get_rx_speed_mbps; + list_add_tail(&data->tp_node, &tpmon->tp_node_list); + break; + case TPMON_MEASURE_NETDEV_Q: + case TPMON_MEASURE_PKTPROC_DL_Q: + case TPMON_MEASURE_DIT_SRC_Q: + data->get_data = tpmon_get_q_status; + list_add_tail(&data->q_status_node, &tpmon->q_status_list); + break; + default: + mif_err("%s measure error:%d %d\n", + data->name, count, data->measure); + spin_unlock_irqrestore(&tpmon->lock, flags); + return -EINVAL; + } + list_add_tail(&data->data_node, &tpmon->all_data_list); + spin_unlock_irqrestore(&tpmon->lock, flags); + + mif_info("name:%s measure:%d target:%d extra_idx:%d level:%d/%d proto:%d\n", + data->name, data->measure, data->target, data->extra_idx, + data->num_threshold, data->num_level, data->proto); + + count++; + } } return 0; @@ -1753,6 +1644,9 @@ int tpmon_create(struct platform_device *pdev, struct link_device *ld) struct cpif_tpmon *tpmon = &_tpmon; struct mem_link_device *mld = ld_to_mem_link_device(ld); int ret = 0; +#if IS_ENABLED(CONFIG_CPU_FREQ) + struct cpufreq_policy pol; +#endif if (!np) { mif_err("np is null\n"); @@ -1766,51 +1660,67 @@ int tpmon_create(struct platform_device *pdev, struct link_device *ld) } tpmon->ld = ld; - tpmon->use_user_value = 0; + tpmon->use_user_level = 0; tpmon->debug_print = 0; mld->tpmon = &_tpmon; spin_lock_init(&tpmon->lock); atomic_set(&tpmon->active, 0); - INIT_LIST_HEAD(&tpmon->data_list); - INIT_LIST_HEAD(&tpmon->urgent_data_list); - - ret = tpmon_parse_dt(np, tpmon); - if (ret) { - mif_err("tpmon_parse_dt() error:%d\n", ret); - goto create_error; - } - + INIT_LIST_HEAD(&tpmon->all_data_list); + INIT_LIST_HEAD(&tpmon->tp_node_list); + INIT_LIST_HEAD(&tpmon->q_status_list); INIT_LIST_HEAD(&tpmon->net_node_list); -#if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) - exynos_pm_qos_add_request(&tpmon->qos_req_mif, PM_QOS_BUS_THROUGHPUT, 0); - exynos_pm_qos_add_request(&tpmon->qos_req_mif_max, PM_QOS_BUS_THROUGHPUT_MAX, - PM_QOS_BUS_THROUGHPUT_MAX_DEFAULT_VALUE); - exynos_pm_qos_add_request(&tpmon->qos_req_int, PM_QOS_DEVICE_THROUGHPUT, 0); - exynos_pm_qos_add_request(&tpmon->qos_req_int_max, PM_QOS_DEVICE_THROUGHPUT_MAX, - PM_QOS_DEVICE_THROUGHPUT_MAX_DEFAULT_VALUE); +#if IS_ENABLED(CONFIG_CPU_FREQ) + if (cpufreq_get_policy(&pol, 0) != 0) { + mif_info("register cpufreq notifier\n"); + tpmon->cpufreq_nb.notifier_call = tpmon_cpufreq_nb; + cpufreq_register_notifier(&tpmon->cpufreq_nb, CPUFREQ_POLICY_NOTIFIER); + } #endif -#if IS_ENABLED(CONFIG_CPU_FREQ) - tpmon->cpufreq_nb.notifier_call = tpmon_cpufreq_nb; - cpufreq_register_notifier(&tpmon->cpufreq_nb, CPUFREQ_POLICY_NOTIFIER); +#if IS_ENABLED(CONFIG_EXYNOS_PM_QOS) + exynos_pm_qos_add_request(&tpmon->qos_req_mif, + PM_QOS_BUS_THROUGHPUT, 0); + exynos_pm_qos_add_request(&tpmon->qos_req_mif_max, + PM_QOS_BUS_THROUGHPUT_MAX, + PM_QOS_BUS_THROUGHPUT_MAX_DEFAULT_VALUE); + exynos_pm_qos_add_request(&tpmon->qos_req_int, + PM_QOS_DEVICE_THROUGHPUT, 0); + exynos_pm_qos_add_request(&tpmon->qos_req_int_max, + PM_QOS_DEVICE_THROUGHPUT_MAX, + PM_QOS_DEVICE_THROUGHPUT_MAX_DEFAULT_VALUE); #endif #if IS_ENABLED(CONFIG_EXYNOS_BTS) tpmon->bts_scen_index = bts_get_scenindex("cp_throughput"); #endif + ret = tpmon_parse_dt(np, tpmon); + if (ret) { + mif_err("tpmon_parse_dt() error:%d\n", ret); + goto create_error; + } + tpmon->monitor_wq = alloc_workqueue("cpif_tpmon_monitor_wq", __WQ_LEGACY | WQ_MEM_RECLAIM | WQ_UNBOUND, 1); if (!tpmon->monitor_wq) { - mif_err("create_workqueue() error\n"); + mif_err("create_workqueue() monitor_wq error\n"); ret = -EINVAL; goto create_error; } INIT_DELAYED_WORK(&tpmon->monitor_dwork, tpmon_monitor_work); + tpmon->boost_wq = alloc_workqueue("cpif_tpmon_boost_wq", + __WQ_LEGACY | WQ_MEM_RECLAIM | WQ_UNBOUND, 1); + if (!tpmon->boost_wq) { + mif_err("create_workqueue() boost_wq error\n"); + ret = -EINVAL; + goto create_error; + } + INIT_DELAYED_WORK(&tpmon->boost_dwork, tpmon_boost_work); + tpmon->start = tpmon_start; tpmon->stop = tpmon_stop; tpmon->add_rx_bytes = tpmon_add_rx_bytes; diff --git a/drivers/soc/google/cpif/cpif_tp_monitor.h b/drivers/soc/google/cpif/cpif_tp_monitor.h index f5307d361fd5..ab4929e77e1e 100644 --- a/drivers/soc/google/cpif/cpif_tp_monitor.h +++ b/drivers/soc/google/cpif/cpif_tp_monitor.h @@ -21,7 +21,7 @@ #define MAX_TPMON_DATA 16 #define MAX_TPMON_THRESHOLD 10 -#define MAX_TPMON_VALUES (MAX_TPMON_THRESHOLD+1) +#define MAX_TPMON_LEVEL (MAX_TPMON_THRESHOLD+1) #define MAX_RPS_STRING 8 #define MAX_IRQ_AFFINITY_DATA 5 #define MAX_IRQ_AFFINITY_STRING 8 @@ -31,46 +31,44 @@ struct tpmon_data { struct cpif_tpmon *tpmon; struct list_head data_node; + struct list_head tp_node; + struct list_head q_status_node; char *name; - u32 measure; u32 target; + + u32 num_level; + u32 level[MAX_TPMON_LEVEL]; + u32 curr_level_pos; + u32 prev_level_pos; + u32 user_level; + u32 enable; - u32 extra_idx; + u32 measure; u32 proto; - u32 check_udp; - - struct list_head urgent_data_node; - u32 urgent; + u32 extra_idx; u32 num_threshold; u32 threshold[MAX_TPMON_THRESHOLD]; u32 curr_threshold_pos; u32 prev_threshold_pos; - u32 num_values; - u32 values[MAX_TPMON_VALUES]; - u32 curr_value_pos; - u32 prev_value_pos; - u32 user_value; + u32 unboost_threshold_mbps[MAX_TPMON_THRESHOLD]; + ktime_t prev_unboost_time; - u32 unboost_tp_mbps[MAX_TPMON_THRESHOLD]; - u64 jiffies_to_unboost; - bool forced_unboost; + bool need_boost; void *extra_data; - void (*set_data)(struct tpmon_data *data); u32 (*get_data)(struct tpmon_data *data); + void (*set_data)(struct tpmon_data *data); }; struct cpif_rx_data { unsigned long rx_bytes; unsigned long rx_mbps; - unsigned long rx_kbps; - unsigned long rx_sum; - unsigned long rx_bytes_data[MAX_RX_BYTES_COUNT]; - u32 rx_bytes_idx; + + ktime_t prev_time; }; struct cpif_tpmon { @@ -80,10 +78,6 @@ struct cpif_tpmon { atomic_t active; spinlock_t lock; - struct list_head data_list; - struct list_head net_node_list; - - u32 trigger_mbps; u32 trigger_msec_min; u32 trigger_msec_max; @@ -92,31 +86,36 @@ struct cpif_tpmon { u32 monitor_stop_mbps; u32 boost_hold_msec; - u32 unboost_tp_percent; - - u64 jiffies_to_trigger; - atomic_t need_urgent; - struct list_head urgent_data_list; - bool urgent_active; + struct list_head all_data_list; + struct list_head tp_node_list; + struct list_head q_status_list; + struct list_head net_node_list; + ktime_t prev_monitor_time; struct workqueue_struct *monitor_wq; struct delayed_work monitor_dwork; + atomic_t boost_active; + struct workqueue_struct *boost_wq; + struct delayed_work boost_dwork; + struct cpif_rx_data rx_total; struct cpif_rx_data rx_tcp; struct cpif_rx_data rx_udp; struct cpif_rx_data rx_others; - unsigned int rx_bytes_len; - u32 rx_bytes_valid_cnt; - bool rx_bytes_skip_add; - u32 pktproc_queue_status; - u32 netdev_backlog_queue_status; - u32 dit_src_queue_status; + struct cpif_rx_data rx_total_stat; + struct cpif_rx_data rx_tcp_stat; + struct cpif_rx_data rx_udp_stat; + struct cpif_rx_data rx_others_stat; + + u32 q_status_pktproc_dl; + u32 q_status_netdev_backlog; + u32 q_status_dit_src; u32 legacy_packet_count; - u32 use_user_value; + u32 use_user_level; u32 debug_print; struct tpmon_data data[MAX_TPMON_DATA]; @@ -150,6 +149,15 @@ struct cpif_tpmon { void (*reset_data)(char *name); }; +static inline u32 tpmon_get_curr_level(struct tpmon_data *data) +{ + if (!data->enable) + return 0; + + return data->tpmon->use_user_level ? + data->user_level : data->level[data->curr_level_pos]; +} + #if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) extern int tpmon_create(struct platform_device *pdev, struct link_device *ld); extern int tpmon_start(void); @@ -170,9 +178,4 @@ static inline void tpmon_add_net_node(struct list_head *node) { return; } static inline int tpmon_check_active(void) { return 0; } #endif -#if IS_ENABLED(CONFIG_MCPS) -extern int mcps_enable; -extern int set_mcps_cp_irq_mask(const char *buf); -#endif - #endif /* __CPIF_TP_MONITOR_H__ */ diff --git a/drivers/soc/google/cpif/cpif_version.h b/drivers/soc/google/cpif/cpif_version.h index 666c55dd9c46..40cd02b28f0d 100644 --- a/drivers/soc/google/cpif/cpif_version.h +++ b/drivers/soc/google/cpif/cpif_version.h @@ -7,5 +7,6 @@ #ifndef __CPIF_VERSION_H__ #define __CPIF_VERSION_H__ -static const char cpif_driver_version[] = "CPIF-20210812R1"; +/* Should not exceed CPIF_VERSION_SIZE */ +static const char cpif_driver_version[] = "CPIF-20220408R1"; #endif /* __CPIF_VERSION_H__ */ diff --git a/drivers/soc/google/cpif/cpif_vmapper.c b/drivers/soc/google/cpif/cpif_vmapper.c new file mode 100644 index 000000000000..786288a38856 --- /dev/null +++ b/drivers/soc/google/cpif/cpif_vmapper.c @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#include "cpif_vmapper.h" +#include +#include +#include "modem_v1.h" + +struct cpif_va_mapper *cpif_vmap_create(u64 va_start, u64 va_size, u64 instance_size) +{ + struct cpif_va_mapper *vmap; + + vmap = kzalloc(sizeof(struct cpif_va_mapper), GFP_ATOMIC); + if (vmap == NULL) + return NULL; + + vmap->va_start = va_start; + vmap->va_size = va_size; + vmap->va_end = va_start + va_size; + vmap->instance_size = instance_size; + + if (va_size == instance_size) /* no need to use item list */ + goto skip_item_list; + INIT_LIST_HEAD(&vmap->item_list); + +skip_item_list: + cpif_sysmmu_set_use_iocc(); + cpif_sysmmu_enable(); + + return vmap; +} +EXPORT_SYMBOL(cpif_vmap_create); + +void cpif_vmap_free(struct cpif_va_mapper *vmap) +{ + struct cpif_vmap_item *temp, *temp2; + int err; + + if (unlikely(!vmap)) { + mif_err("no vmap to free\n"); + return; + } + + if (vmap->va_size == vmap->instance_size && vmap->out) { + /* when va and pa is mapped at once */ + err = cpif_iommu_unmap(vmap->va_start, vmap->va_size); + if (unlikely(err == 0)) + mif_err("failed to perform iommu unmapping\n"); + kfree(vmap->out); + vmap->out = NULL; + kfree(vmap); + vmap = NULL; + return; + } + + if (vmap->in) { + err = cpif_iommu_unmap(vmap->in->vaddr_base, vmap->in->item_size); + if (err == 0) + mif_err("failed to unmap\n"); + kfree(vmap->in); + vmap->in = NULL; + } + + if (vmap->out) { + err = cpif_iommu_unmap(vmap->out->vaddr_base, vmap->out->item_size); + if (err == 0) + mif_err("failed to unmap\n"); + kfree(vmap->out); + vmap->out = NULL; + } + + list_for_each_entry_safe(temp, temp2, &vmap->item_list, item) { + err = cpif_iommu_unmap(temp->vaddr_base, temp->item_size); + if (err == 0) + mif_err("failed to unmap\n"); + list_del(&temp->item); + kfree(temp); + } + + kfree(vmap); + vmap = NULL; +} +EXPORT_SYMBOL(cpif_vmap_free); + +u64 cpif_vmap_map_area(struct cpif_va_mapper *vmap, u64 item_paddr, u64 item_size, + u64 instance_paddr) +{ + int err; + struct cpif_vmap_item *temp; + + if (vmap->va_size == vmap->instance_size) { /* when va and pa is mapped at once */ + if (vmap->out) { + mif_err("whole range mapping is done already\n"); + return 0; + } + + err = cpif_iommu_map(vmap->va_start, instance_paddr, vmap->va_size, + DMA_BIDIRECTIONAL); + if (unlikely(err)) { + mif_err("failed to perform iommu mapping\n"); + return 0; + } + temp = kzalloc(sizeof(struct cpif_vmap_item), GFP_ATOMIC); + if (!temp) + return 0; + temp->vaddr_base = vmap->va_start; + temp->paddr_base = instance_paddr; + atomic_set(&temp->ref, 1); + vmap->out = temp; /* need to be positioned at out for easy unmap */ + + return vmap->out->vaddr_base; + } + + if (!vmap->in) {/* first time to map */ + err = cpif_iommu_map(vmap->va_start, item_paddr, item_size, + DMA_BIDIRECTIONAL); + if (unlikely(err)) { + mif_err_limited("failed to perform iommu mapping\n"); + return 0; + } + temp = kzalloc(sizeof(struct cpif_vmap_item), GFP_ATOMIC); + if (!temp) + return 0; + temp->vaddr_base = vmap->va_start; + temp->paddr_base = item_paddr; + temp->item_size = item_size; + atomic_set(&temp->ref, 1); + vmap->in = temp; + } else if (vmap->in->paddr_base != item_paddr) { + /* normal case + * if in's vmap item is fully mapped, enqueue that item to + * item_list and create new item + */ + u64 next_vaddr_base = vmap->in->vaddr_base + vmap->in->item_size; + + if ((next_vaddr_base + item_size) >= vmap->va_end) /* back to va start */ + next_vaddr_base = vmap->va_start; + + err = cpif_iommu_map(next_vaddr_base, item_paddr, item_size, + DMA_BIDIRECTIONAL); + + if (unlikely(err)) { + mif_err_limited("failed to perform iommu mapping\n"); + return 0; + } + temp = kzalloc(sizeof(struct cpif_vmap_item), GFP_ATOMIC); + if (!temp) + return 0; + temp->vaddr_base = next_vaddr_base; + temp->paddr_base = item_paddr; + temp->item_size = item_size; + atomic_set(&temp->ref, 1); + + list_add_tail(&vmap->in->item, &vmap->item_list); + vmap->in = temp; + } else /* item "in" still has room to use, no need to iommu this time */ + atomic_inc(&vmap->in->ref); + + return vmap->in->vaddr_base + (instance_paddr - item_paddr); +} +EXPORT_SYMBOL(cpif_vmap_map_area); + +u64 cpif_vmap_unmap_area(struct cpif_va_mapper *vmap, u64 vaddr) +{ + int err = 0; + u64 ret = 0; + struct cpif_vmap_item *temp; + struct cpif_vmap_item *target; + + if (vmap->va_size == vmap->instance_size) { /* when va and pa is mapped at once */ + + err = cpif_iommu_unmap(vmap->va_start, vmap->va_size); + if (unlikely(err == 0)) { + mif_err_limited("failed to perform iommu unmapping\n"); + return 0; + } + kfree(vmap->out); + vmap->out = NULL; + + return vmap->va_start; + } + + if (unlikely(!vmap->out)) { /* first time to unmap */ + temp = list_first_entry_or_null(&vmap->item_list, + struct cpif_vmap_item, item); + if (unlikely(!temp)) { + mif_err_limited("failed to get item from list\n"); + return 0; + } + vmap->out = temp; + list_del(&temp->item); + } + + target = vmap->out; + + if (unlikely(vaddr < target->vaddr_base || vaddr > target->vaddr_base + + target->item_size)) { + mif_err("invalid vaddr 0x%llX vbase: 0x%llX vend: 0x%llX\n", + vaddr, target->vaddr_base, + target->vaddr_base + target->item_size); + return 0; + } + + atomic_dec(&target->ref); + + ret = target->paddr_base + (vaddr - target->vaddr_base); + + /* unmap this item when ref count goes to 0 */ + if (atomic_read(&target->ref) == 0) { + err = cpif_iommu_unmap(target->vaddr_base, target->item_size); + if (err == 0) { + mif_err_limited("failed to unmap\n"); + return 0; + } + kfree(vmap->out); + /* update vmap->out to the next item to be unmapped */ + temp = list_first_entry_or_null(&vmap->item_list, + struct cpif_vmap_item, item); + if (unlikely(!temp)) { + mif_err_limited("item list is empty\n"); + if (vmap->in) { + /* drain out rest, next map will start from beginning */ + mif_info("drain out vmap->in\n"); + vmap->out = vmap->in; + vmap->in = NULL; + } else /* last of last, initialize vmap->out */ + vmap->out = NULL; + return ret; + } + vmap->out = temp; + list_del(&temp->item); + } + + return ret; +} +EXPORT_SYMBOL(cpif_vmap_unmap_area); diff --git a/drivers/soc/google/cpif/cpif_vmapper.h b/drivers/soc/google/cpif/cpif_vmapper.h new file mode 100644 index 000000000000..cbe096123f86 --- /dev/null +++ b/drivers/soc/google/cpif/cpif_vmapper.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __CPIF_VMAPPER_H__ +#define __CPIF_VMAPPER_H__ + +#include +#include + +struct cpif_vmap_item { + u64 vaddr_base; /* cp address */ + u64 paddr_base; /* ap physical address */ + u64 item_size; + struct list_head item; + atomic_t ref; /* if zero, this item will be unmapped */ +}; + +/* vmapper contains vaddr that is linear, but paddr sparsed with certain size + * vmapper contains several items, and each item contains several + * instances have fixed size, whereas each item size may defer due to + * page allocation + */ +struct cpif_va_mapper { + u64 va_start; /* va = cp address */ + u64 va_size; + u64 va_end; + u64 instance_size; /* size of instance in the item */ + + /* vmap table guaranteed to be mapped/unmapped sequentially */ + struct list_head item_list; + struct cpif_vmap_item *out; /* item to be unmapped, after list out */ + struct cpif_vmap_item *in; /* item mapped recently, before list in */ +}; + +struct cpif_va_mapper *cpif_vmap_create(u64 va_start, u64 va_size, u64 instance_size); +void cpif_vmap_free(struct cpif_va_mapper *vmap); +u64 cpif_vmap_map_area(struct cpif_va_mapper *vmap, u64 item_paddr, u64 item_size, + u64 instance_paddr); +u64 cpif_vmap_unmap_area(struct cpif_va_mapper *vmap, u64 vaddr); +#endif /* __CPIF_VMAPPER_H__ */ diff --git a/drivers/soc/google/cpif/direct_dm.c b/drivers/soc/google/cpif/direct_dm.c new file mode 100644 index 000000000000..46953712edc0 --- /dev/null +++ b/drivers/soc/google/cpif/direct_dm.c @@ -0,0 +1,1139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#include +#include +#include +#include +#include + +#include "direct_dm.h" +#include "modem_utils.h" + +static struct direct_dm_ctrl *_dc; + +static void direct_dm_rx_func(unsigned long arg); + +/* RX timer */ +static inline void direct_dm_start_rx_timer(struct direct_dm_ctrl *dc, + struct hrtimer *timer) +{ + unsigned long flags; + + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + if (!dc->use_rx_timer) { + mif_err_limited("use_rx_timer is not set\n"); + return; + } + + spin_lock_irqsave(&dc->rx_timer_lock, flags); + if (!hrtimer_is_queued(timer)) { + ktime_t ktime = ktime_set(0, dc->rx_timer_period_msec * NSEC_PER_MSEC); + + dc->stat.rx_timer_req++; + hrtimer_start(timer, ktime, HRTIMER_MODE_REL); + } + spin_unlock_irqrestore(&dc->rx_timer_lock, flags); +} + +static enum hrtimer_restart direct_dm_rx_timer(struct hrtimer *timer) +{ + mif_info("run rx func by timer\n"); + + _dc->stat.rx_timer_expire++; + + if (_dc->use_rx_task) + tasklet_hi_schedule(&_dc->rx_task); + else + direct_dm_rx_func((unsigned long)_dc); + + return HRTIMER_NORESTART; +} + +/* RX func */ +static int direct_dm_send_to_upper_layer(struct direct_dm_ctrl *dc, + struct direct_dm_desc *curr_desc, void *addr) +{ + struct sk_buff *skb = NULL; + struct mem_link_device *mld; + int ch_id = 0; + + if (!dc || !curr_desc || !addr) { + mif_err_limited("null addr\n"); + return -ENOMEM; + } + + dc->stat.upper_layer_req_cnt++; + skb = dev_alloc_skb(curr_desc->length); + if (unlikely(!skb)) { + mif_err_limited("mem_alloc_skb() error pos:%d\n", + dc->curr_desc_pos); + dc->stat.err_upper_layer_req++; + return -ENOMEM; + } + skb_put(skb, curr_desc->length); + skb_copy_to_linear_data(skb, addr, curr_desc->length); + + switch (dc->ld->protocol) { + case PROTOCOL_SIPC: + ch_id = SIPC_CH_ID_CPLOG1; + break; + case PROTOCOL_SIT: + ch_id = EXYNOS_CH_ID_CPLOG; + break; + default: + mif_err_limited("protocol error:%d\n", dc->ld->protocol); + return -EINVAL; + } + + skbpriv(skb)->lnk_hdr = 0; + skbpriv(skb)->sipc_ch = ch_id; + skbpriv(skb)->iod = link_get_iod_with_channel(dc->ld, ch_id); + skbpriv(skb)->ld = dc->ld; + skbpriv(skb)->napi = NULL; + + mld = to_mem_link_device(dc->ld); + mld->pass_skb_to_demux(mld, skb); + + dc->desc_rgn[dc->curr_desc_pos].status &= ~BIT(DDM_DESC_S_DONE); + + dc->curr_desc_pos = circ_new_ptr(dc->num_desc, + dc->curr_desc_pos, 1); + dc->curr_done_pos = circ_new_ptr(dc->num_desc, + dc->curr_done_pos, 1); + + return 0; +} + +static int direct_dm_send_to_usb(struct direct_dm_ctrl *dc, + struct direct_dm_desc *curr_desc, void *addr) +{ + int ret = 0; + + if (!dc || !curr_desc || !addr) { + mif_err_limited("null addr\n"); + return -ENOMEM; + } + + dc->stat.usb_req_cnt++; + ret = usb_dm_request(addr, curr_desc->length); + if (ret) { + mif_info_limited("usb_dm_request() ret:%d pos:%d\n", + ret, dc->curr_desc_pos); + + dc->usb_req_failed = true; + dc->stat.err_usb_req++; + if (dc->use_rx_timer) { + if (unlikely(dc->enable_debug)) + mif_info("start timer\n"); + + direct_dm_start_rx_timer(dc, &dc->rx_timer); + } + + return ret; + } + dc->usb_req_failed = false; + + dc->curr_desc_pos = circ_new_ptr(dc->num_desc, + dc->curr_desc_pos, 1); + + return 0; +} + +static void direct_dm_rx_func(unsigned long arg) +{ + struct direct_dm_ctrl *dc = (struct direct_dm_ctrl *)arg; + unsigned long paddr; + void *addr; + int ret; + int i; + bool upper_layer_req = false; + int rcvd = 0; + unsigned long flags; + + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + spin_lock_irqsave(&dc->rx_lock, flags); + + upper_layer_req = dc->info_rgn->silent_log; + if (!upper_layer_req && !dc->usb_active) { + mif_info_limited("usb is not activated\n"); + spin_unlock_irqrestore(&dc->rx_lock, flags); + return; + } + + for (i = 0; i < dc->num_desc; i++) { + struct direct_dm_desc curr_desc = dc->desc_rgn[dc->curr_desc_pos]; + + if (!(curr_desc.status & BIT(DDM_DESC_S_DONE))) { + if (unlikely(dc->enable_debug)) + mif_info("DDM_DESC_S_DONE is not set %d 0x%llx\n", + dc->curr_desc_pos, curr_desc.cp_buff_paddr); + + break; + } + + if (curr_desc.status & BIT(DDM_DESC_S_TOUT)) { + mif_err_limited("DDM_DESC_S_TOUT is set %d 0x%llx\n", + dc->curr_desc_pos, curr_desc.cp_buff_paddr); + dc->stat.err_desc_tout++; + } + + /* TODO: support compressed log of DM log mover H/W */ + if (curr_desc.status & BIT(DDM_DESC_S_COMPRESSED)) + mif_err_limited("DDM_DESC_S_COMPRESSED is set %d 0x%llx\n", + dc->curr_desc_pos, curr_desc.cp_buff_paddr); + + if (!curr_desc.length || (curr_desc.length > dc->max_packet_size)) { + mif_err_limited("length error:%d\n", curr_desc.length); + dc->stat.err_length++; + break; + } + + paddr = curr_desc.cp_buff_paddr - + dc->buff_rgn_offset - dc->cp_ddm_pbase + dc->buff_pbase; + addr = phys_to_virt(paddr); + + if (dc->buff_rgn_cached && !dc->hw_iocc) + dma_sync_single_for_cpu(dc->dev, paddr, + dc->max_packet_size, DMA_FROM_DEVICE); + + if (unlikely(dc->enable_debug)) + mif_info("pos:%d len:%d a:%pK/0x%lx/0x%llx upper:%d done:%d\n", + dc->curr_desc_pos, curr_desc.length, + addr, paddr, curr_desc.cp_buff_paddr, + upper_layer_req, dc->desc_rgn[dc->curr_desc_pos].status); + + if (unlikely(upper_layer_req)) { + ret = direct_dm_send_to_upper_layer(dc, &curr_desc, addr); + if (ret) + break; + + rcvd++; + } else { + ret = direct_dm_send_to_usb(dc, &curr_desc, addr); + if (ret) + break; + + rcvd++; + + if (dc->curr_desc_pos == dc->curr_done_pos) { + if (unlikely(dc->enable_debug)) + mif_info("prev desc is enqueued:%d\n", + dc->curr_done_pos); + break; + } + } + } + + if (unlikely(dc->enable_debug)) + mif_info("rcvd:%d\n", rcvd); + + spin_unlock_irqrestore(&dc->rx_lock, flags); +} + +static void direct_dm_run_rx_func(struct direct_dm_ctrl *dc) +{ + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + if (dc->use_rx_timer && hrtimer_active(&dc->rx_timer)) + hrtimer_cancel(&dc->rx_timer); + + if (dc->use_rx_task) + tasklet_hi_schedule(&dc->rx_task); + else + direct_dm_rx_func((unsigned long)dc); +} + +/* IRQ handler */ +static irqreturn_t direct_dm_irq_handler(int irq, void *arg) +{ + struct direct_dm_ctrl *dc = (struct direct_dm_ctrl *)arg; + + if (!dc) { + mif_err_limited("dc is null\n"); + return IRQ_HANDLED; + } + + direct_dm_run_rx_func(dc); + + return IRQ_HANDLED; +} + +/* Callback from USB driver */ +static void direct_dm_usb_active_noti(void *arg) +{ + struct direct_dm_ctrl *dc = (struct direct_dm_ctrl *)arg; + unsigned long flags; + + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + spin_lock_irqsave(&dc->rx_lock, flags); + + mif_info("usb is activated\n"); + dc->usb_active = true; + + spin_unlock_irqrestore(&dc->rx_lock, flags); + + if (dc->usb_req_failed) { + mif_info("run rx func\n"); + direct_dm_run_rx_func(dc); + } +} + +static void direct_dm_usb_disable_noti(void *arg) +{ + struct direct_dm_ctrl *dc = (struct direct_dm_ctrl *)arg; + unsigned long flags; + + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + spin_lock_irqsave(&dc->rx_lock, flags); + + mif_info("usb is deactivated\n"); + dc->usb_active = false; + dc->usb_req_failed = true; + + spin_unlock_irqrestore(&dc->rx_lock, flags); + + if (dc->use_rx_timer && hrtimer_active(&dc->rx_timer)) { + mif_info("cancel rx timer\n"); + hrtimer_cancel(&dc->rx_timer); + } +} + +static void direct_dm_usb_completion_noti(void *addr, int length, void *arg) +{ + struct direct_dm_ctrl *dc = (struct direct_dm_ctrl *)arg; + unsigned long paddr; + u32 pos; + unsigned long flags; + + if (!dc) { + mif_err_limited("dc is null\n"); + return; + } + + dc->stat.usb_complete_cnt++; + + paddr = virt_to_phys(addr); + if ((paddr < dc->buff_pbase) || + (paddr >= (dc->buff_pbase + dc->buff_rgn_size))) { + mif_err("addr error:%pK 0x%lx 0x%lx 0x%x\n", + addr, paddr, dc->buff_pbase, dc->buff_rgn_offset); + dc->stat.err_usb_complete++; + return; + } + + if (dc->buff_rgn_cached && !dc->hw_iocc) + dma_sync_single_for_device(dc->dev, paddr, + dc->max_packet_size, DMA_FROM_DEVICE); + + spin_lock_irqsave(&dc->rx_lock, flags); + pos = (paddr - dc->buff_pbase) / dc->max_packet_size; + dc->desc_rgn[pos].status &= ~BIT(DDM_DESC_S_DONE); + + if (dc->curr_done_pos != pos) + mif_err("pos error! pos:%d done:%d len:%d a:%pK/0x%lx\n", + pos, dc->curr_done_pos, length, addr, paddr); + + if ((length <= 0) || (length > dc->max_packet_size)) { + mif_err_limited("length error:%d\n", length); + dc->usb_req_failed = true; + } + + if (unlikely(dc->enable_debug)) + mif_info("pos:%d done:%d len:%d a:%pK/0x%lx\n", + pos, dc->curr_done_pos, length, addr, paddr); + + dc->curr_done_pos = circ_new_ptr(dc->num_desc, + dc->curr_done_pos, 1); + + spin_unlock_irqrestore(&dc->rx_lock, flags); +} + +/* sysfs */ +static ssize_t ctrl_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "version:%d shm_rgn_index:%d\n", + dc->version, dc->shm_rgn_index); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "hw_iocc:%d info_desc_rgn_cached:%d buff_rgn_cached:%d\n", + dc->hw_iocc, dc->info_desc_rgn_cached, dc->buff_rgn_cached); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "info_rgn_offset:0x%08x info_rgn_size:0x%08x\n", + dc->info_rgn_offset, dc->info_rgn_size); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "desc_rgn_offset:0x%08x desc_rgn_size:0x%08x num_desc:%d\n", + dc->desc_rgn_offset, dc->desc_rgn_size, dc->num_desc); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "buff_rgn_offset:0x%08x buff_rgn_size:0x%08x\n", + dc->buff_rgn_offset, dc->buff_rgn_size); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "max_packet_size:%d usb_req_num:%d irq_index:%d\n", + dc->max_packet_size, dc->usb_req_num, dc->irq_index); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "cp_ddm_pbase:0x%08x\n", dc->cp_ddm_pbase); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "curr_desc_pos:%d\n", dc->curr_desc_pos); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "curr_done_pos:%d\n", dc->curr_done_pos); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "use_rx_task:%d\n", dc->use_rx_task); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "use_rx_timer:%d\n", dc->use_rx_timer); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "rx_timer_period_msec:%d\n", dc->rx_timer_period_msec); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "enable_debug:%d\n", dc->enable_debug); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "usb_req_failed:%d\n", dc->usb_req_failed); + + return count; +} + +static ssize_t stat_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "err_desc_tout:%lld\n", dc->stat.err_desc_tout); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "err_length:%lld\n", dc->stat.err_length); + + count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "usb_req_cnt:%lld\n", dc->stat.usb_req_cnt); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "err_usb_req:%lld\n", dc->stat.err_usb_req); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "usb_complete_cnt:%lld\n", dc->stat.usb_complete_cnt); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "err_usb_complete:%lld\n", dc->stat.err_usb_complete); + + count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "upper_layer_req_cnt:%lld\n", dc->stat.upper_layer_req_cnt); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "err_upper_layer_req:%lld\n", dc->stat.err_upper_layer_req); + + count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "rx_timer_req:%lld\n", dc->stat.rx_timer_req); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "rx_timer_expire:%lld\n", dc->stat.rx_timer_expire); + + return count; +} + +static ssize_t info_rgn_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "version:%d max_packet_size:%d\n", + dc->info_rgn->version, dc->info_rgn->max_packet_size); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "silent_log:%d\n", + dc->info_rgn->silent_log); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "cp_desc_pbase:0x%llx cp_buff_pbase:0x%llx\n", + dc->info_rgn->cp_desc_pbase, dc->info_rgn->cp_buff_pbase); + + return count; +} + +static ssize_t desc_rgn_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + int i; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "curr_desc_pos:%d\n", dc->curr_desc_pos); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "curr_done_pos:%d\n", dc->curr_done_pos); + + for (i = 0; i < dc->num_desc; i++) { + count += scnprintf(&buf[count], PAGE_SIZE - count, + "%d 0x%llx 0x%x 0x%x %d\n", + i, dc->desc_rgn[i].cp_buff_paddr, dc->desc_rgn[i].control, + dc->desc_rgn[i].status, dc->desc_rgn[i].length); + } + + return count; +} + +static ssize_t enable_debug_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + int val; + int ret; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + val ? (dc->enable_debug = true) : (dc->enable_debug = false); + mif_info("enable_debug:%d\n", dc->enable_debug); + + return count; +} + +static ssize_t enable_debug_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "enable_debug:%d\n", + dc->enable_debug); + + return count; +} + +static ssize_t use_rx_task_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + int val; + int ret; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + val ? (dc->use_rx_task = true) : (dc->use_rx_task = false); + mif_info("use_rx_task:%d\n", dc->use_rx_task); + + return count; +} + +static ssize_t use_rx_task_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "use_rx_task:%d\n", + dc->use_rx_task); + + return count; +} + +static ssize_t use_rx_timer_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + int val; + int ret; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + val ? (dc->use_rx_timer = true) : (dc->use_rx_timer = false); + mif_info("use_rx_timer:%d\n", dc->use_rx_timer); + + return count; +} + +static ssize_t use_rx_timer_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "use_rx_timer:%d\n", + dc->use_rx_timer); + + return count; +} + +static ssize_t rx_timer_period_msec_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + int val; + int ret; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + if (!dc->use_rx_timer) { + mif_err("use_rx_timer is not set\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + dc->rx_timer_period_msec = val; + mif_info("rx_timer_period_msec:%d\n", dc->rx_timer_period_msec); + + return count; +} + +static ssize_t rx_timer_period_msec_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct direct_dm_ctrl *dc = _dc; + ssize_t count = 0; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + if (!dc->use_rx_timer) { + mif_err("use_rx_timer is not set\n"); + return count; + } + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "rx_timer_period_msec:%d\n", + dc->rx_timer_period_msec); + + return count; +} + +static u32 _test_dm_desc_pos; +static ssize_t test_dm_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + void *addr; + int val; + int ret; + int i; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + if (!val || (val > dc->num_desc)) { + mif_err("val error:%d\n", val); + return count; + } + + for (i = 0; i < val; i++) { + addr = dc->desc_rgn[_test_dm_desc_pos].cp_buff_paddr - + dc->buff_rgn_offset - dc->cp_ddm_pbase + dc->buff_vbase; + + mif_info("pos:%d a:%pK/0x%llx\n", + _test_dm_desc_pos, addr, + dc->desc_rgn[_test_dm_desc_pos].cp_buff_paddr); + + if (dc->desc_rgn[_test_dm_desc_pos].status & BIT(DDM_DESC_S_DONE)) { + mif_err("DDM_DESC_S_DONE is already set. pos:%d\n", + _test_dm_desc_pos); + break; + } + + memset(addr, _test_dm_desc_pos, dc->max_packet_size); + dc->desc_rgn[_test_dm_desc_pos].length = dc->max_packet_size; + dc->desc_rgn[_test_dm_desc_pos].status |= BIT(DDM_DESC_S_DONE); + + if (dc->desc_rgn[_test_dm_desc_pos].control & BIT(DDM_DESC_C_END)) + _test_dm_desc_pos = 0; + else + _test_dm_desc_pos++; + } + + direct_dm_irq_handler(dc->irq_index, dc); + + return count; +} + +static ssize_t test_silent_log_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct direct_dm_ctrl *dc = _dc; + int val; + int ret; + + if (!dc) { + mif_err("dc is null\n"); + return count; + } + + ret = kstrtoint(buf, 0, &val); + if (ret) { + mif_err("kstrtoint() error:%d\n", ret); + return ret; + } + + val ? (dc->info_rgn->silent_log = 1) : + (dc->info_rgn->silent_log = 0); + mif_info("silent_log:%d\n", dc->info_rgn->silent_log); + + return count; +} + +static DEVICE_ATTR_RO(ctrl_status); +static DEVICE_ATTR_RO(stat); +static DEVICE_ATTR_RO(info_rgn); +static DEVICE_ATTR_RO(desc_rgn); +static DEVICE_ATTR_RW(enable_debug); +static DEVICE_ATTR_RW(use_rx_task); +static DEVICE_ATTR_RW(use_rx_timer); +static DEVICE_ATTR_RW(rx_timer_period_msec); +static DEVICE_ATTR_WO(test_dm); +static DEVICE_ATTR_WO(test_silent_log); + +static struct attribute *direct_dm_attrs[] = { + &dev_attr_ctrl_status.attr, + &dev_attr_stat.attr, + &dev_attr_info_rgn.attr, + &dev_attr_desc_rgn.attr, + &dev_attr_enable_debug.attr, + &dev_attr_use_rx_task.attr, + &dev_attr_use_rx_timer.attr, + &dev_attr_rx_timer_period_msec.attr, + &dev_attr_test_dm.attr, + &dev_attr_test_silent_log.attr, + NULL, +}; +ATTRIBUTE_GROUPS(direct_dm); + +/* Initialize */ +int direct_dm_init(struct link_device *ld) +{ + struct direct_dm_ctrl *dc = _dc; + int i; + + if (!dc) { + mif_err("dc is null\n"); + return -EPERM; + } + + dc->ld = ld; + + dc->info_rgn->version = dc->version; + dc->info_rgn->max_packet_size = dc->max_packet_size; + dc->info_rgn->cp_desc_pbase = dc->cp_ddm_pbase + dc->desc_rgn_offset; + dc->info_rgn->cp_buff_pbase = dc->cp_ddm_pbase + dc->buff_rgn_offset; + mif_info("version:%d max_packet_size:%d\n", + dc->info_rgn->version, dc->info_rgn->max_packet_size); + mif_info("cp_desc_pbase:0x%llx cp_buff_pbase:0x%llx\n", + dc->info_rgn->cp_desc_pbase, dc->info_rgn->cp_buff_pbase); + + memset(dc->desc_vbase, 0, dc->desc_rgn_size); + for (i = 0; i < dc->num_desc; i++) { + dc->desc_rgn[i].cp_buff_paddr = dc->cp_ddm_pbase + + dc->buff_rgn_offset + (dc->max_packet_size * i); + + dc->desc_rgn[i].control |= BIT(DDM_DESC_C_INT); + + if (i == (dc->num_desc - 1)) + dc->desc_rgn[i].control |= BIT(DDM_DESC_C_END); + } + + if (unlikely(dc->enable_debug)) { + for (i = 0; i < dc->num_desc; i++) { + mif_info("%d a:0x%llx c:0x%x s:0x%x l:%d\n", + i, dc->desc_rgn[i].cp_buff_paddr, dc->desc_rgn[i].control, + dc->desc_rgn[i].status, dc->desc_rgn[i].length); + } + } + + memset(dc->buff_vbase, 0, dc->buff_rgn_size); + + dc->curr_desc_pos = 0; + dc->curr_done_pos = 0; + _test_dm_desc_pos = 0; + + dc->usb_req_failed = false; + + memset(&dc->stat, 0, sizeof(dc->stat)); + + return 0; +} +EXPORT_SYMBOL(direct_dm_init); + +int direct_dm_deinit(void) +{ + return 0; +} +EXPORT_SYMBOL(direct_dm_deinit); + +/* Create */ +static int direct_dm_setup_region(struct direct_dm_ctrl *dc) +{ + unsigned long cp_pbase; + unsigned long ddm_pbase; + u32 ddm_rgn_size; + + if (!dc) { + mif_err("dc is null\n"); + return -EPERM; + } + + cp_pbase = cp_shmem_get_base(0, SHMEM_CP); + if (!cp_pbase) { + mif_err("cp_pbase is null\n"); + return -ENOMEM; + } + ddm_pbase = cp_shmem_get_base(0, dc->shm_rgn_index); + if (!ddm_pbase) { + mif_err("ddm_pbase is null\n"); + return -ENOMEM; + } + ddm_rgn_size = cp_shmem_get_size(0, dc->shm_rgn_index); + if (!ddm_rgn_size) { + mif_err("ddm_rgn_size is null\n"); + return -ENOMEM; + } + mif_info("cp_pbase:0x%lx ddm_pbase:0x%lx ddm_rgn_size:0x%08x\n", + cp_pbase, ddm_pbase, ddm_rgn_size); + + /* TODO: support slim modem */ + dc->cp_ddm_pbase = ddm_pbase - cp_pbase + CP_CPU_BASE_ADDRESS; + mif_info("cp_ddm_pbase:0x%08x\n", dc->cp_ddm_pbase); + + if (dc->info_desc_rgn_cached) { + dc->info_vbase = phys_to_virt(ddm_pbase + dc->info_rgn_offset); + dc->desc_vbase = phys_to_virt(ddm_pbase + dc->desc_rgn_offset); + if (!dc->hw_iocc) { + mif_err("cached region is not supported yet without hw_iocc\n"); + return -EINVAL; + } + } else { + dc->info_vbase = cp_shmem_get_nc_region( + ddm_pbase + dc->info_rgn_offset, + dc->info_rgn_size + dc->desc_rgn_size); + if (!dc->info_vbase) { + mif_err("dc->info_base error\n"); + return -ENOMEM; + } + dc->desc_vbase = dc->info_vbase + dc->info_rgn_size; + } + memset(dc->info_vbase, 0, dc->info_rgn_size + dc->desc_rgn_size); + mif_info("info_rgn_size:0x%08x desc_rgn_size:0x%08x\n", + dc->info_rgn_size, dc->desc_rgn_size); + + dc->buff_rgn_size = ddm_rgn_size - + (dc->info_rgn_size + dc->desc_rgn_size); + dc->buff_pbase = ddm_pbase + dc->buff_rgn_offset; + if (dc->buff_rgn_cached) { + dc->buff_vbase = phys_to_virt(dc->buff_pbase); + } else { + dc->buff_vbase = cp_shmem_get_nc_region( + dc->buff_pbase, dc->buff_rgn_size); + if (!dc->buff_vbase) { + mif_err("dc->buff_vbase error\n"); + return -ENOMEM; + } + } + memset(dc->buff_vbase, 0, dc->buff_rgn_size); + dc->num_desc = dc->buff_rgn_size / dc->max_packet_size; + if (dc->buff_rgn_cached && !dc->hw_iocc) + dma_sync_single_for_device(dc->dev, dc->buff_pbase, + dc->buff_rgn_size, DMA_FROM_DEVICE); + mif_info("buff_rgn_size:0x%08x num_desc:%d\n", + dc->buff_rgn_size, dc->num_desc); + + dc->info_rgn = (struct direct_dm_info_rgn *)dc->info_vbase; + dc->desc_rgn = (struct direct_dm_desc *)dc->desc_vbase; + + return 0; +} + +static int direct_dm_register_irq(struct direct_dm_ctrl *dc) +{ + int ret; + + ret = cp_mbox_register_handler(dc->irq_index, 0, + direct_dm_irq_handler, dc); + if (ret) { + mif_err("cp_mbox_register_handler() error:%d\n", ret); + goto error; + } + +error: + return ret; +} + +static int direct_dm_read_dt(struct device_node *np, + struct direct_dm_ctrl *dc) +{ + mif_dt_read_u32(np, "version", dc->version); + mif_dt_read_u32(np, "shm_rgn_index", dc->shm_rgn_index); + mif_dt_read_u32(np, "hw_iocc", dc->hw_iocc); + mif_dt_read_u32(np, "info_desc_rgn_cached", dc->info_desc_rgn_cached); + mif_dt_read_u32(np, "buff_rgn_cached", dc->buff_rgn_cached); + + mif_dt_read_u32(np, "info_rgn_offset", dc->info_rgn_offset); + mif_dt_read_u32(np, "info_rgn_size", dc->info_rgn_size); + mif_dt_read_u32(np, "desc_rgn_offset", dc->desc_rgn_offset); + mif_dt_read_u32(np, "desc_rgn_size", dc->desc_rgn_size); + mif_dt_read_u32(np, "buff_rgn_offset", dc->buff_rgn_offset); + + mif_dt_read_u32(np, "max_packet_size", dc->max_packet_size); + mif_dt_read_u32(np, "usb_req_num", dc->usb_req_num); + mif_dt_read_u32(np, "irq_index", dc->irq_index); + + mif_dt_read_bool(np, "use_rx_task", dc->use_rx_task); + mif_dt_read_bool(np, "use_rx_timer", dc->use_rx_timer); + mif_dt_read_u32(np, "rx_timer_period_msec", dc->rx_timer_period_msec); + + mif_info("version:%d shm_rgn_index:%d\n", + dc->version, dc->shm_rgn_index); + mif_info("hw_iocc:%d info_desc_rgn_cached:%d buff_rgn_cached:%d\n", + dc->hw_iocc, dc->info_desc_rgn_cached, dc->buff_rgn_cached); + + mif_info("info_rgn_offset:0x%08x info_rgn_size:0x%08x\n", + dc->info_rgn_offset, dc->info_rgn_size); + mif_info("desc_rgn_offset:0x%08x desc_rgn_size:0x%08x\n", + dc->desc_rgn_offset, dc->desc_rgn_size); + mif_info("buff_rgn_offset:0x%08x\n", dc->buff_rgn_offset); + + mif_info("max_packet_size:%d usb_req_num:%d irq_index:%d\n", + dc->max_packet_size, dc->usb_req_num, dc->irq_index); + mif_info("use_rx_timer:%d rx_timer_period_msec:%d\n", + dc->use_rx_timer, dc->rx_timer_period_msec); + + + return 0; +} + +int direct_dm_create(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct direct_dm_ctrl *dc = NULL; + int ret; + + mif_info("+++\n"); + + if (!np) { + mif_err("of_node is null\n"); + ret = -EINVAL; + goto err; + } + + _dc = devm_kzalloc(dev, sizeof(struct direct_dm_ctrl), GFP_KERNEL); + if (!_dc) { + mif_err_limited("devm_kzalloc() error\n"); + ret = -ENOMEM; + goto err; + } + dc = _dc; + + dc->dev = dev; + + ret = direct_dm_read_dt(np, dc); + if (ret) { + mif_err("direct_dm_read_dt() error:%d\n", ret); + goto err_setup; + } + + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); + + ret = direct_dm_register_irq(dc); + if (ret) { + mif_err("direct_dm_register_irq() error:%d\n", ret); + goto err_setup; + } + + ret = direct_dm_setup_region(dc); + if (ret) { + mif_err("direct_dm_setup_region() error:%d\n", ret); + goto err_setup; + } + + ret = init_dm_direct_path(dc->usb_req_num, + direct_dm_usb_completion_noti, + direct_dm_usb_active_noti, + direct_dm_usb_disable_noti, + (void *)dc); + if (ret) { + mif_err("init_dm_direct_path() error:%d\n", ret); + goto err_setup; + } + + spin_lock_init(&dc->rx_lock); + + tasklet_init(&dc->rx_task, direct_dm_rx_func, (unsigned long)dc); + + spin_lock_init(&dc->rx_timer_lock); + hrtimer_init(&dc->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + dc->rx_timer.function = direct_dm_rx_timer; + + dev_set_drvdata(dev, dc); + + ret = sysfs_create_groups(&dev->kobj, direct_dm_groups); + if (ret != 0) { + mif_err("sysfs_create_group() error:%d\n", ret); + goto err_setup; + } + + mif_info("---\n"); + + return 0; + +err_setup: + devm_kfree(dev, dc); + dc = NULL; + +err: + panic("Direct DM driver probe failed\n"); + mif_err("xxx\n"); + + return ret; +} +EXPORT_SYMBOL(direct_dm_create); + +/* Platform driver */ +static int direct_dm_probe(struct platform_device *pdev) +{ + return direct_dm_create(pdev); +} + +static int direct_dm_remove(struct platform_device *pdev) +{ + return 0; +} + +static int direct_dm_suspend(struct device *dev) +{ + return 0; +} + +static int direct_dm_resume(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops direct_dm_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(direct_dm_suspend, direct_dm_resume) +}; + +static const struct of_device_id direct_dm_dt_match[] = { + { .compatible = "samsung,cpif-direct-dm", }, + {}, +}; +MODULE_DEVICE_TABLE(of, direct_dm_dt_match); + +static struct platform_driver direct_dm_driver = { + .probe = direct_dm_probe, + .remove = direct_dm_remove, + .driver = { + .name = "direct_dm", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(direct_dm_dt_match), + .pm = &direct_dm_pm_ops, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(direct_dm_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Samsung direct DM driver"); diff --git a/drivers/soc/google/cpif/direct_dm.h b/drivers/soc/google/cpif/direct_dm.h new file mode 100644 index 000000000000..534b0b03fdf2 --- /dev/null +++ b/drivers/soc/google/cpif/direct_dm.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __DIRECT_DM_H__ +#define __DIRECT_DM_H__ + +#include + +enum direct_dm_desc_control_bits { + DDM_DESC_C_END = 3, /* End of buffer descriptor */ + DDM_DESC_C_INT /* Interrupt enabled */ +}; + +enum direct_dm_desc_status_bits { + DDM_DESC_S_DONE, /* DMA done */ + DDM_DESC_S_TOUT, /* Transferred on timeout */ + DDM_DESC_S_COMPRESSED = 5 /* "1":compressed log is on, "0":comp is off */ +}; + +struct direct_dm_desc { + u64 cp_buff_paddr:40, + _reserved_0:24; + u64 length:16, + status:8, + control:8, + _reserved_1:32; +} __packed; + +struct direct_dm_info_rgn { + u64 version:4, + _reserved_0:4, + max_packet_size:16, + silent_log:1, + _reserved_1:39; + u64 cp_desc_pbase:40, + _reserved_2:24; + u64 cp_buff_pbase:40, + _reserved_3:24; +} __packed; + +/* Statistics */ +struct direct_dm_statistics { + u64 err_desc_done; + u64 err_desc_tout; + u64 err_length; + + u64 usb_req_cnt; + u64 err_usb_req; + u64 usb_complete_cnt; + u64 err_usb_complete; + + u64 upper_layer_req_cnt; + u64 err_upper_layer_req; + + u64 rx_timer_req; + u64 rx_timer_expire; +}; + +struct direct_dm_ctrl { + struct link_device *ld; + + u32 version; + u32 shm_rgn_index; + + u32 hw_iocc; + u32 info_desc_rgn_cached; + u32 buff_rgn_cached; + + u32 info_rgn_offset; + u32 info_rgn_size; + u32 desc_rgn_offset; + u32 desc_rgn_size; + u32 num_desc; + u32 buff_rgn_offset; + u32 buff_rgn_size; + + u32 max_packet_size; + u32 usb_req_num; + u32 irq_index; + + u32 cp_ddm_pbase; + + struct device *dev; + + u32 curr_desc_pos; + u32 curr_done_pos; + + bool usb_req_failed; + + spinlock_t rx_lock; + struct tasklet_struct rx_task; + bool use_rx_task; + + bool use_rx_timer; + spinlock_t rx_timer_lock; + struct hrtimer rx_timer; + u32 rx_timer_period_msec; + + bool usb_active; + + struct direct_dm_statistics stat; + + bool enable_debug; + + void __iomem *info_vbase; + void __iomem *desc_vbase; + void __iomem *buff_vbase; + unsigned long buff_pbase; + + struct direct_dm_info_rgn *info_rgn; + struct direct_dm_desc *desc_rgn; +}; + +#if IS_ENABLED(CONFIG_CPIF_DIRECT_DM) +extern int direct_dm_create(struct platform_device *pdev); +extern int direct_dm_init(struct link_device *ld); +extern int direct_dm_deinit(void); +#else +static inline int direct_dm_create(struct platform_device *pdev) { return 0; } +static inline int direct_dm_init(struct link_device *ld) { return 0; } +static inline int direct_dm_deinit(void) { return 0; } +#endif + +#endif /* __DIRECT_DM_H__ */ diff --git a/drivers/soc/google/cpif/dit.h b/drivers/soc/google/cpif/dit.h index b2cb050ff3cb..1abd158bcdc8 100644 --- a/drivers/soc/google/cpif/dit.h +++ b/drivers/soc/google/cpif/dit.h @@ -10,145 +10,8 @@ #ifndef __DIT_H__ #define __DIT_H__ -#ifndef DIT_DEBUG -#define DIT_DEBUG -#endif - -#ifdef DIT_DEBUG -#define DIT_DEBUG_LOW -#endif - -#define DIT_REG_SW_COMMAND 0x0000 -#define DIT_REG_CLK_GT_OFF 0x0004 /* 20 bit */ -#define DIT_REG_DMA_INIT_DATA 0x0008 /* 28 bit */ - -/* 0:16beat, 1:8beat, 2:4beat, 3:2beat, 4:1beat */ -#define DIT_REG_TX_DESC_CTRL_SRC 0x000C /* 3 bit */ -#define DIT_REG_TX_DESC_CTRL_DST 0x0010 /* 3 bit */ -#define DIT_REG_TX_HEAD_CTRL 0x0014 /* 3 bit */ -#define DIT_REG_TX_MOD_HD_CTRL 0x0018 /* 3 bit */ -#define DIT_REG_TX_PKT_CTRL 0x001C /* 3 bit */ -#define DIT_REG_TX_CHKSUM_CTRL 0x0020 /* 3 bit */ - -#define DIT_REG_RX_DESC_CTRL_SRC 0x0024 /* 3 bit */ -#define DIT_REG_RX_DESC_CTRL_DST 0x0028 /* 3 bit */ -#define DIT_REG_RX_HEAD_CTRL 0x002C /* 3 bit */ -#define DIT_REG_RX_MOD_HD_CTRL 0x0030 /* 3 bit */ -#define DIT_REG_RX_PKT_CTRL 0x0034 /* 3 bit */ -#define DIT_REG_RX_CHKSUM_CTRL 0x0038 /* 3 bit */ - -#define DIT_REG_DMA_CHKSUM_OFF 0x003C /* 2 bit */ - -/* start address for Tx desc */ -#define DIT_REG_TX_RING_START_ADDR_0_SRC 0x0044 -#define DIT_REG_TX_RING_START_ADDR_1_SRC 0x0048 -#define DIT_REG_TX_RING_START_ADDR_0_DST0 0x004C -#define DIT_REG_TX_RING_START_ADDR_1_DST0 0x0050 -#define DIT_REG_TX_RING_START_ADDR_0_DST1 0x0054 -#define DIT_REG_TX_RING_START_ADDR_1_DST1 0x0058 -#define DIT_REG_TX_RING_START_ADDR_0_DST2 0x005C -#define DIT_REG_TX_RING_START_ADDR_1_DST2 0x0060 - -/* start address for Rx desc */ -#define DIT_REG_RX_RING_START_ADDR_0_SRC 0x0064 -#define DIT_REG_RX_RING_START_ADDR_1_SRC 0x0068 -#define DIT_REG_RX_RING_START_ADDR_0_DST0 0x006C -#define DIT_REG_RX_RING_START_ADDR_1_DST0 0x0070 -#define DIT_REG_RX_RING_START_ADDR_0_DST1 0x0074 -#define DIT_REG_RX_RING_START_ADDR_1_DST1 0x0078 -#define DIT_REG_RX_RING_START_ADDR_0_DST2 0x007C -#define DIT_REG_RX_RING_START_ADDR_1_DST2 0x0080 - -#define DIT_REG_INT_ENABLE 0x0084 -#define DIT_REG_INT_MASK 0x0088 -#define DIT_REG_INT_PENDING 0x008C -#define DIT_REG_STATUS 0x0090 - -/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_FILTER_INTERVAL */ -#define DIT_REG_CLAT_TX_FILTER 0x2000 -/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL */ -#define DIT_REG_CLAT_TX_PLAT_PREFIX_0 0x2020 -#define DIT_REG_CLAT_TX_PLAT_PREFIX_1 0x2024 -#define DIT_REG_CLAT_TX_PLAT_PREFIX_2 0x2028 -/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL */ -#define DIT_REG_CLAT_TX_CLAT_SRC_0 0x2080 -#define DIT_REG_CLAT_TX_CLAT_SRC_1 0x2084 -#define DIT_REG_CLAT_TX_CLAT_SRC_2 0x2088 -#define DIT_REG_CLAT_TX_CLAT_SRC_3 0x208C - -/* address for Tx desc */ -#define DIT_REG_NAT_TX_DESC_ADDR_0_SRC 0x4000 /* 32 bit */ -#define DIT_REG_NAT_TX_DESC_ADDR_1_SRC 0x4004 /* 4 bit */ -#define DIT_REG_NAT_TX_DESC_ADDR_EN_SRC 0x4008 /* 1 bit */ -#define DIT_REG_NAT_TX_DESC_ADDR_0_DST0 0x4018 -#define DIT_REG_NAT_TX_DESC_ADDR_1_DST0 0x401C -#define DIT_REG_NAT_TX_DESC_ADDR_0_DST1 0x4020 -#define DIT_REG_NAT_TX_DESC_ADDR_1_DST1 0x4024 -#define DIT_REG_NAT_TX_DESC_ADDR_0_DST2 0x4028 -#define DIT_REG_NAT_TX_DESC_ADDR_1_DST2 0x402C - -/* address for Rx desc */ -#define DIT_REG_NAT_RX_DESC_ADDR_0_SRC 0x4030 /* 32 bit */ -#define DIT_REG_NAT_RX_DESC_ADDR_1_SRC 0x4034 /* 4 bit */ -#define DIT_REG_NAT_RX_DESC_ADDR_EN_SRC 0x4038 /* 1 bit */ -#define DIT_REG_NAT_RX_DESC_ADDR_0_DST0 0x4048 -#define DIT_REG_NAT_RX_DESC_ADDR_1_DST0 0x404C -#define DIT_REG_NAT_RX_DESC_ADDR_0_DST1 0x4050 -#define DIT_REG_NAT_RX_DESC_ADDR_1_DST1 0x4054 -#define DIT_REG_NAT_RX_DESC_ADDR_0_DST2 0x4058 -#define DIT_REG_NAT_RX_DESC_ADDR_1_DST2 0x405C - -/* total: DIT_REG_NAT_LOCAL_ADDR_MAX, interval: DIT_REG_NAT_LOCAL_INTERVAL */ -#define DIT_REG_NAT_LOCAL_ADDR 0x4100 - -#define DIT_REG_NAT_ZERO_CHK_OFF 0x4144 -#define DIT_REG_NAT_ETHERNET_EN 0x414C - -/* total: DIT_REG_NAT_LOCAL_ADDR_MAX, interval: DIT_REG_ETHERNET_MAC_INTERVAL */ -#define DIT_REG_NAT_ETHERNET_DST_MAC_ADDR_0 0x6000 /* 32 bit */ -#define DIT_REG_NAT_ETHERNET_DST_MAC_ADDR_1 0x6004 /* 16 bit */ -#define DIT_REG_NAT_ETHERNET_SRC_MAC_ADDR_0 0x6008 /* 32 bit */ -#define DIT_REG_NAT_ETHERNET_SRC_MAC_ADDR_1 0x600C /* 16 bit */ -#define DIT_REG_NAT_ETHERNET_TYPE 0x6010 /* 16 bit */ - -#define DIT_REG_NAT_TX_PORT_INIT_START 0x6210 -#define DIT_REG_NAT_TX_PORT_INIT_DONE 0x6214 -#define DIT_REG_NAT_RX_PORT_INIT_START 0x6228 -#define DIT_REG_NAT_RX_PORT_INIT_DONE 0x622C - -/* total: DIT_REG_NAT_LOCAL_PORT_MAX, interval: DIT_REG_NAT_LOCAL_INTERVAL */ -#define DIT_REG_NAT_RX_PORT_TABLE_SLOT 0xC000 - -/* total numbers and intervals */ -#define DIT_REG_NAT_LOCAL_ADDR_MAX (16) -#define DIT_REG_NAT_LOCAL_PORT_MAX (2048) -#define DIT_REG_NAT_LOCAL_INTERVAL (4) -#define DIT_REG_ETHERNET_MAC_INTERVAL (0x20) -#define DIT_REG_CLAT_ADDR_MAX (8) -#define DIT_REG_CLAT_TX_FILTER_INTERVAL (4) -#define DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL (12) -#define DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL (16) - -/* macro for DIT register operation */ -#define PADDR_LO(paddr) (paddr & 0xFFFFFFFF) -#define PADDR_HI(paddr) ((paddr >> 32) & 0xF) - -#define WRITE_REG_PADDR_LO(dc, paddr, offset) \ - writel(PADDR_LO(paddr), dc->register_base + offset) -#define WRITE_REG_PADDR_HI(dc, paddr, offset) \ - writel(PADDR_HI(paddr), dc->register_base + offset) -#define WRITE_REG_VALUE(dc, value, offset) \ - writel(value, dc->register_base + offset) -#define READ_REG_VALUE(dc, offset) \ - readl(dc->register_base + offset) -#define WRITE_SHR_VALUE(dc, value) \ - writel(value, dc->sharability_base + dc->sharability_offset) -#define BACKUP_REG_VALUE(dc, dst, offset, size) \ - memcpy_fromio(dst, dc->register_base + offset, size) -#define RESTORE_REG_VALUE(dc, src, offset, size) \ - memcpy_toio(dc->register_base + offset, src, size) - -#define DIT_RX_BURST_16BEAT (0) +#include "modem_utils.h" +#include "modem_toe_device.h" enum dit_direction { DIT_DIR_TX, @@ -168,285 +31,41 @@ enum dit_store_type { DIT_STORE_RESTORE, }; -enum dit_int_enable_bits { - TX_DST0_INT_ENABLE_BIT = 0, - TX_DST1_INT_ENABLE_BIT, - TX_DST2_INT_ENABLE_BIT, - RX_DST0_INT_ENABLE_BIT = 3, - RX_DST1_INT_ENABLE_BIT, - RX_DST2_INT_ENABLE_BIT, - ERR_INT_ENABLE_BIT = 14, -}; - -#define DIT_INT_ENABLE_MASK \ - (BIT(TX_DST0_INT_ENABLE_BIT) | BIT(TX_DST1_INT_ENABLE_BIT) | \ - BIT(TX_DST2_INT_ENABLE_BIT) | \ - BIT(RX_DST0_INT_ENABLE_BIT) | BIT(RX_DST1_INT_ENABLE_BIT) | \ - BIT(RX_DST2_INT_ENABLE_BIT) | \ - BIT(ERR_INT_ENABLE_BIT)) - -enum dit_desc_ring { - DIT_DST_DESC_RING_0, - DIT_DST_DESC_RING_1, - DIT_DST_DESC_RING_2, - DIT_DST_DESC_RING_MAX, - DIT_SRC_DESC_RING = DIT_DST_DESC_RING_MAX, - DIT_DESC_RING_MAX -}; - -enum dit_desc_control_bits { - DIT_DESC_C_RESERVED, /* Reserved */ - DIT_DESC_C_END, /* end packet of LRO */ - DIT_DESC_C_START, /* first packet of LRO */ - DIT_DESC_C_RINGEND, /* End of descriptor */ - DIT_DESC_C_INT, /* Interrupt enabled */ - DIT_DESC_C_CSUM, /* csum enabled */ - DIT_DESC_C_TAIL, /* last buffer */ - DIT_DESC_C_HEAD /* first buffer */ -}; - -#define DIT_SRC_KICK_CONTROL_MASK \ - (BIT(DIT_DESC_C_HEAD) | BIT(DIT_DESC_C_TAIL) | \ - BIT(DIT_DESC_C_INT) | BIT(DIT_DESC_C_RINGEND)) - -enum dit_desc_status_bits { - DIT_DESC_S_DONE, /* DMA done */ - DIT_DESC_S_RESERVED, /* Reserved */ - DIT_DESC_S_TCPCF, /* Failed TCP csum */ - DIT_DESC_S_IPCSF, /* Failed IP csum */ - DIT_DESC_S_IGNR, /* Ignore csum */ - DIT_DESC_S_TCPC, /* TCP/UDP csum done: IGNR shold be 0 */ - DIT_DESC_S_IPCS, /* IP header csum done: IGNR shold be 0 */ - DIT_DESC_S_PFD /* passed packet filter */ -}; - -#define DIT_CHECKSUM_FAILED_STATUS_MASK \ - (BIT(DIT_DESC_S_TCPCF) | BIT(DIT_DESC_S_IPCSF) | BIT(DIT_DESC_S_IGNR)) - -enum dit_sw_command_bits { - DMA_INIT_COMMAND_BIT, - TX_COMMAND_BIT, - RX_COMMAND_BIT, -}; - -enum dit_nat_ethernet_en_bits { - TX_ETHERNET_EN_BIT, - RX_ETHERNET_EN_BIT, -}; - -/* DIT_INT_PENDING */ -enum dit_int_pending_bits { - TX_DST0_INT_PENDING_BIT = 0, - TX_DST1_INT_PENDING_BIT, - TX_DST2_INT_PENDING_BIT, - RX_DST0_INT_PENDING_BIT = 3, - RX_DST1_INT_PENDING_BIT, - RX_DST2_INT_PENDING_BIT, - ERR_INT_PENDING_BIT = 14, -}; - -#define DIT_TX_INT_PENDING_MASK \ - (BIT(TX_DST0_INT_PENDING_BIT) | BIT(TX_DST1_INT_PENDING_BIT) | \ - BIT(TX_DST2_INT_PENDING_BIT) | BIT(ERR_INT_PENDING_BIT)) - -#define DIT_RX_INT_PENDING_MASK \ - (BIT(RX_DST0_INT_PENDING_BIT) | BIT(RX_DST1_INT_PENDING_BIT) | \ - BIT(RX_DST2_INT_PENDING_BIT) | BIT(ERR_INT_PENDING_BIT)) - -#define DIT_ALL_INT_PENDING_MASK \ - (DIT_TX_INT_PENDING_MASK | DIT_RX_INT_PENDING_MASK) - -/* DIT_STATUS - * zero means idle - */ -enum dit_status_mask { - TX_STATUS_MASK = 0x0F, - RX_STATUS_MASK = 0xF0, -}; - -enum dit_packet_info_bits { - DIT_PACKET_INFO_IPV6_BIT = 10, - DIT_PACKET_INFO_IPV4_BIT, -}; - -struct dit_src_desc { - u64 src_addr:36, - _reserved_0:12, - /* the below 16 bits are "private info" on the document */ - ch_id:8, /* max ch value for rmnet is 17 */ - pre_csum:1, /* checksum successful from pktproc */ - udp_csum_zero:1, /* reset udp checksum 0 after NAT */ - _reserved_2:6; - u64 length:16, - _reserved_1:32, - control:8, - status:8; -} __packed; - -struct dit_dst_desc { - u64 dst_addr:36, - packet_info:12, - /* the below 16 bits are "private info" on the document */ - ch_id:8, - pre_csum:1, - udp_csum_zero:1, - _reserved_2:6; - u64 length:16, - org_port:16, - trans_port:16, - control:8, /* misspelled as "reserved" on the document */ - status:8; -} __packed; - -struct dit_desc_info { - unsigned int src_wp; - unsigned int src_rp; - unsigned int dst_wp[DIT_DST_DESC_RING_MAX]; - unsigned int dst_rp[DIT_DST_DESC_RING_MAX]; - - unsigned int src_desc_ring_len; - struct dit_src_desc *src_desc_ring; - struct sk_buff **src_skb_buf; - u32 buf_size; - - phys_addr_t pktproc_pbase; - u32 pktproc_desc_len; - u32 *pktproc_fore_ptr; - - unsigned int dst_desc_ring_len; - struct dit_dst_desc *dst_desc_ring[DIT_DST_DESC_RING_MAX]; - struct sk_buff **dst_skb_buf[DIT_DST_DESC_RING_MAX]; - bool dst_skb_buf_filled[DIT_DST_DESC_RING_MAX]; -}; - -struct dit_ctrl_t { - struct device *dev; - struct link_device *ld; - struct net_device *netdev; - struct napi_struct napi; - int *irq_buf; - int irq_len; - int irq_affinity; - int idle_ip_index; - - void __iomem *register_base; - void __iomem *sharability_base; - u32 sharability_offset; - u32 sharability_value; - - u32 hw_version; - u32 hw_capabilities; - bool use_tx; - bool use_rx; - bool use_clat; - bool hal_linked; - u32 rx_extra_desc_ring_len; - - struct dit_desc_info desc_info[DIT_DIR_MAX]; - - /* for kicked flag, reg_value_q and init_done */ - spinlock_t src_lock; - bool kicked[DIT_DIR_MAX]; - bool kick_reserved[DIT_DIR_MAX]; - struct list_head reg_value_q; - bool init_done; - bool init_reserved; - - atomic_t init_running; - atomic_t stop_napi_poll; - -#if defined(DIT_DEBUG_LOW) - int pktgen_ch; - int force_bypass; -#endif -}; - -struct dit_snapshot_t { - char *name; - int head; - int tail; - - u64 packets; - /* cumulative amount */ - u64 total_packets; - u64 clat_packets; - - u32 max_usage; - u32 alloc_skbs; -}; - -struct dit_reg_value_item { - struct list_head list; - u32 value; - u32 offset; -}; - -struct dit_iface { - u8 upstream_ch; -}; - -enum dit_dump_bits { - DIT_DUMP_SNAPSHOT_BIT, - DIT_DUMP_DESC_BIT, - DIT_DUMP_PORT_TABLE_BIT, - DIT_DUMP_MAX, -}; - -#define DIT_DUMP_ALL \ - (BIT(DIT_DUMP_SNAPSHOT_BIT) | BIT(DIT_DUMP_DESC_BIT) | \ - BIT(DIT_DUMP_PORT_TABLE_BIT)) - -/* DIT works with pktproc for the specific queue */ -#define DIT_PKTPROC_TX_QUEUE_NUM (1) -#define DIT_PKTPROC_RX_QUEUE_NUM (0) - -enum dit_idle_ip { - DIT_IDLE_IP_ACTIVE = 0, - DIT_IDLE_IP_IDLE, -}; - -/* - * if there is 1 src desc and it is at the ring_end, - * DIT will reads 3 descs from the ring_end. - * for the safety, add additional 2 descs. - */ -#define DIT_SRC_DESC_RING_LEN_PADDING (2) - -int dit_create(struct platform_device *pdev); int dit_init(struct link_device *ld, enum dit_init_type type, enum dit_store_type store); -int dit_enqueue_reg_value_with_ext_lock(u32 value, u32 offset); -int dit_enqueue_reg_value(u32 value, u32 offset); -int dit_read_rx_dst_poll(struct napi_struct *napi, int budget); -int dit_manage_rx_dst_data_buffers(bool fill); int dit_get_irq_affinity(void); int dit_set_irq_affinity(int affinity); +int dit_set_pktproc_queue_num(enum dit_direction dir, u32 queue_num); int dit_set_buf_size(enum dit_direction dir, u32 size); int dit_set_pktproc_base(enum dit_direction dir, phys_addr_t base); int dit_set_desc_ring_len(enum dit_direction dir, u32 len); int dit_get_src_usage(enum dit_direction dir, u32 *usage); -struct net_device *dit_get_netdev(void); extern u32 gs_chipid_get_type(void); #if IS_ENABLED(CONFIG_EXYNOS_DIT) int dit_enqueue_src_desc_ring( enum dit_direction dir, u8 *src, unsigned long src_paddr, - u16 len, u16 ch_id, bool csum); + u16 len, u8 ch_id, bool csum); int dit_enqueue_src_desc_ring_skb(enum dit_direction dir, struct sk_buff *skb); int dit_kick(enum dit_direction dir, bool retry); bool dit_check_dir_use_queue(enum dit_direction dir, unsigned int queue_num); int dit_reset_dst_wp_rp(enum dit_direction dir); -int dit_stop_napi_poll(void); +struct net_device *dit_get_netdev(void); +bool dit_support_clat(void); +bool dit_hal_set_clat_info(struct mem_link_device *mld, struct clat_info *clat); #else static inline int dit_enqueue_src_desc_ring( enum dit_direction dir, u8 *src, unsigned long src_paddr, - u16 len, u16 ch_id, bool csum) { return -1; } + u16 len, u8 ch_id, bool csum) { return -1; } static inline int dit_enqueue_src_desc_ring_skb( enum dit_direction dir, struct sk_buff *skb) { return -1; } static inline int dit_kick(enum dit_direction dir, bool retry) { return -1; } static inline bool dit_check_dir_use_queue( enum dit_direction dir, unsigned int queue_num) { return false; } static inline int dit_reset_dst_wp_rp(enum dit_direction dir) { return -1; } -static inline int dit_stop_napi_poll(void) { return 0; } +static inline struct net_device *dit_get_netdev(void) { return NULL; } +static inline bool dit_support_clat(void) { return false; } +static inline bool dit_hal_set_clat_info(struct mem_link_device *mld, struct clat_info *clat) +{ return false; } #endif #endif /* __DIT_H__ */ diff --git a/drivers/soc/google/cpif/dit/Makefile b/drivers/soc/google/cpif/dit/Makefile new file mode 100644 index 000000000000..711cedc184b4 --- /dev/null +++ b/drivers/soc/google/cpif/dit/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile of dit + +ccflags-y += -Wformat +ccflags-y += -Wformat-zero-length + +obj-$(CONFIG_EXYNOS_DIT) += exynos_dit.o +exynos_dit-y += dit.o dit_net.o dit_hal.o + +ifeq ($(CONFIG_EXYNOS_DIT_VERSION),0x02020000) + exynos_dit-y += dit_2_2_0.o +else + exynos_dit-y += dit_2_1_0.o +endif diff --git a/drivers/soc/google/cpif/dit.c b/drivers/soc/google/cpif/dit/dit.c similarity index 76% rename from drivers/soc/google/cpif/dit.c rename to drivers/soc/google/cpif/dit/dit.c index 1cd8a6ad385b..1fc1f446eac9 100644 --- a/drivers/soc/google/cpif/dit.c +++ b/drivers/soc/google/cpif/dit/dit.c @@ -19,8 +19,8 @@ #include #endif -#include "modem_utils.h" -#include "dit.h" +#include "link_device.h" +#include "dit_common.h" #include "dit_net.h" #include "dit_hal.h" @@ -112,52 +112,52 @@ static bool dit_hw_capa_matched(u32 mask) static void dit_print_dump(enum dit_direction dir, u32 dump_bits) { - struct dit_desc_info *desc_info; - struct dit_src_desc *src_desc = NULL; - struct dit_dst_desc *dst_desc = NULL; - struct nat_local_port local_port; - u16 reply_port_dst, reply_port_dst_h, reply_port_dst_l; - u16 origin_port_src; u16 ring_num; u32 i; - if (dump_bits & BIT(DIT_DUMP_SNAPSHOT_BIT)) { - mif_err("---- SNAPSHOT[dir:%d] ----\n", dir); + if (cpif_check_bit(dump_bits, DIT_DUMP_SNAPSHOT_BIT)) { + mif_info("---- SNAPSHOT[dir:%d] ----\n", dir); for (ring_num = 0; ring_num < DIT_DESC_RING_MAX; ring_num++) { - pr_info("%s head:%d,tail:%d\n", snapshot[dir][ring_num].name, + mif_info("%s head:%d,tail:%d\n", snapshot[dir][ring_num].name, snapshot[dir][ring_num].head, snapshot[dir][ring_num].tail); } } - if (dump_bits & BIT(DIT_DUMP_DESC_BIT)) { - desc_info = &dc->desc_info[dir]; + if (cpif_check_bit(dump_bits, DIT_DUMP_DESC_BIT)) { + struct dit_desc_info *desc_info = &dc->desc_info[dir]; + struct dit_src_desc *src_desc = NULL; + struct dit_dst_desc *dst_desc = NULL; - mif_err("---- SRC RING[dir:%d] wp:%u,rp:%u ----\n", dir, - desc_info->src_wp, desc_info->src_rp); src_desc = desc_info->src_desc_ring; + mif_info("---- SRC RING[dir:%d] wp:%u,rp:%u ----\n", dir, + desc_info->src_wp, desc_info->src_rp); for (i = 0; i < desc_info->src_desc_ring_len; i++) { if (!(src_desc[i].control & DIT_SRC_KICK_CONTROL_MASK)) continue; - pr_info("src[%06d] ctrl:0x%02X,stat:0x%02X,ch_id:%02u\n", + mif_info("src[%06d] ctrl:0x%02X,stat:0x%02X,ch_id:%03u\n", i, src_desc[i].control, src_desc[i].status, src_desc[i].ch_id); } for (ring_num = DIT_DST_DESC_RING_0; ring_num < DIT_DST_DESC_RING_MAX; ring_num++) { dst_desc = desc_info->dst_desc_ring[ring_num]; - mif_err("---- DST RING%d[dir:%d] wp:%u,rp:%u ----\n", ring_num, dir, + mif_info("---- DST RING%d[dir:%d] wp:%u,rp:%u ----\n", ring_num, dir, desc_info->dst_wp[ring_num], desc_info->dst_rp[ring_num]); for (i = 0; i < desc_info->dst_desc_ring_len; i++) { if (!dst_desc[i].control && !dst_desc[i].status) continue; - pr_info("dst[%d][%06d] ctrl:0x%02X,stat:0x%02X,p_info:0x%03X\n", + mif_info("dst[%d][%06d] ctrl:0x%02X,stat:0x%02X,p_info:0x%03X\n", ring_num, i, dst_desc[i].control, dst_desc[i].status, dst_desc[i].packet_info); } } } - if ((dump_bits & BIT(DIT_DUMP_PORT_TABLE_BIT)) && (dir == DIT_DIR_RX)) { - mif_err("---- PORT TABLE[dir:%d] ----\n", dir); + if (cpif_check_bit(dump_bits, DIT_DUMP_PORT_TABLE_BIT) && dir == DIT_DIR_RX) { + struct nat_local_port local_port; + u16 reply_port_dst, reply_port_dst_h, reply_port_dst_l; + u16 origin_port_src; + + mif_info("---- PORT TABLE[dir:%d] ----\n", dir); for (i = 0; i < DIT_REG_NAT_LOCAL_PORT_MAX; i++) { local_port.hw_val = READ_REG_VALUE(dc, DIT_REG_NAT_RX_PORT_TABLE_SLOT + (i * DIT_REG_NAT_LOCAL_INTERVAL)); @@ -178,14 +178,14 @@ static void dit_print_dump(enum dit_direction dir, u32 dump_bits) origin_port_src = htons(origin_port_src); } - pr_info("[%04d] en:%d,o_port:%5d,r_port:%5d,addr_idx:%02d,dst:%d,udp:%d\n", + mif_info("[%04d] en:%d,o_port:%5d,r_port:%5d,addr_idx:%02d,dst:%d,udp:%d\n", i, local_port.enable, origin_port_src, reply_port_dst, local_port.addr_index, local_port.dst_ring, local_port.is_udp); } } } -static bool dit_is_kicked_any(void) +bool dit_is_kicked_any(void) { unsigned int dir; @@ -276,7 +276,7 @@ static void dit_debug_out_of_order(enum dit_direction dir, enum dit_desc_ring ri seq = ntohl(*seq_p); if (seq < last_seq[dir][ring]) { - mif_err("dir[%d] out of order at ring[%d] seq:0x%08x last:0x%08x\n", dir, ring, + mif_info("dir[%d] out of order at ring[%d] seq:0x%08x last:0x%08x\n", dir, ring, seq, last_seq[dir][ring]); if (++out_count[dir][ring] > 5) { dit_print_dump(dir, DIT_DUMP_ALL); @@ -290,7 +290,7 @@ static void dit_debug_out_of_order(enum dit_direction dir, enum dit_desc_ring ri } #endif -static int dit_check_dst_ready(enum dit_direction dir, enum dit_desc_ring ring_num) +int dit_check_dst_ready(enum dit_direction dir, enum dit_desc_ring ring_num) { struct dit_desc_info *desc_info; @@ -322,6 +322,22 @@ static int dit_check_dst_ready(enum dit_direction dir, enum dit_desc_ring ring_n return 0; } +static inline bool dit_check_queues_empty(enum dit_direction dir) +{ + struct dit_desc_info *desc_info = &dc->desc_info[dir]; + unsigned int ring_num; + + if (!circ_empty(desc_info->src_wp, desc_info->src_rp)) + return false; + + for (ring_num = DIT_DST_DESC_RING_0; ring_num < DIT_DST_DESC_RING_MAX; ring_num++) { + if (!circ_empty(desc_info->dst_wp[ring_num], desc_info->dst_rp[ring_num])) + return false; + } + + return true; +} + static bool dit_is_reg_value_valid(u32 value, u32 offset) { struct nat_local_port local_port; @@ -349,7 +365,7 @@ int dit_enqueue_reg_value_with_ext_lock(u32 value, u32 offset) struct dit_reg_value_item *reg_item; if (dit_is_kicked_any() || !dc->init_done || !list_empty(&dc->reg_value_q)) { - reg_item = devm_kzalloc(dc->dev, sizeof(struct dit_reg_value_item), GFP_ATOMIC); + reg_item = kvzalloc(sizeof(struct dit_reg_value_item), GFP_ATOMIC); if (!reg_item) { mif_err("set reg value 0x%08X at 0x%08X enqueue failed\n", value, offset); return -ENOMEM; @@ -389,7 +405,7 @@ static void dit_clean_reg_value_with_ext_lock(void) if (dit_is_reg_value_valid(reg_item->value, reg_item->offset)) WRITE_REG_VALUE(dc, reg_item->value, reg_item->offset); list_del(®_item->list); - devm_kfree(dc->dev, reg_item); + kvfree(reg_item); } } @@ -435,8 +451,8 @@ static inline void dit_set_skb_checksum(struct dit_dst_desc *dst_desc, if (dst_desc->status & DIT_CHECKSUM_FAILED_STATUS_MASK) return; - if ((dst_desc->status & BIT(DIT_DESC_S_TCPC)) && - (dst_desc->status & BIT(DIT_DESC_S_IPCS))) + if (cpif_check_bit(dst_desc->status, DIT_DESC_S_TCPC) && + cpif_check_bit(dst_desc->status, DIT_DESC_S_IPCS)) skb->ip_summed = CHECKSUM_UNNECESSARY; } @@ -449,17 +465,21 @@ static inline void dit_set_skb_udp_csum_zero(struct dit_dst_desc *dst_desc, if (ring_num == DIT_DST_DESC_RING_0) return; - if (!dst_desc->udp_csum_zero) - return; - - /* it must be IPv4 */ - off = sizeof(struct ethhdr); - if ((*(skb->data + off) & 0xFF) != 0x45) + /* every packets on DST1/2 are IPv4 NATed */ + if (!cpif_check_bit(dst_desc->packet_info, DIT_PACKET_INFO_IPV4_BIT) || + !cpif_check_bit(dst_desc->packet_info, DIT_PACKET_INFO_UDP_BIT)) return; - off += sizeof(struct iphdr); + off = sizeof(struct ethhdr) + sizeof(struct iphdr); uh = (struct udphdr *)(skb->data + off); - uh->check = 0; + + /* set to 0 if csum was 0 from SRC. + * set to CSUM_MANGLED_0 if csum is 0 after the hw csum magic. + */ + if (dst_desc->udp_csum_zero) + uh->check = 0; + else if (!uh->check) + uh->check = CSUM_MANGLED_0; } static int dit_pass_to_net(enum dit_desc_ring ring_num, @@ -512,29 +532,6 @@ static inline void dit_reset_src_desc_kick_control(struct dit_src_desc *src_desc src_desc->control &= ~mask; } -static inline void dit_set_src_desc_filter_bypass( - struct dit_src_desc *src_desc, bool bypass) -{ - /* LRO start/end bit can be used for filter bypass - * 1/1: filtered - * 0/0: filter bypass - * dit does not support checksum yet - */ - u8 mask = (BIT(DIT_DESC_C_END) | BIT(DIT_DESC_C_START)); - -#if defined(DIT_DEBUG_LOW) - if (dc->force_bypass == 1) - bypass = true; - else if (dc->force_bypass == 2) - bypass = false; -#endif - - if (bypass) - src_desc->control &= ~mask; - else - src_desc->control |= mask; -} - static inline void dit_set_src_desc_udp_csum_zero(struct dit_src_desc *src_desc, u8 *src) { @@ -576,8 +573,8 @@ static void dit_set_src_desc_kick_range(enum dit_direction dir, unsigned int src /* set current kick */ head = src_rp; src_desc = &desc_info->src_desc_ring[head]; - src_desc->control |= BIT(DIT_DESC_C_HEAD); - p_desc = virt_to_phys(src_desc); + cpif_set_bit(src_desc->control, DIT_DESC_C_HEAD); + p_desc = desc_info->src_desc_ring_daddr + (sizeof(struct dit_src_desc) * head); if (dir == DIT_DIR_TX) { offset_lo = DIT_REG_NAT_TX_DESC_ADDR_0_SRC; @@ -595,11 +592,12 @@ static void dit_set_src_desc_kick_range(enum dit_direction dir, unsigned int src tail = circ_prev_ptr(desc_info->src_desc_ring_len, src_wp, 1); src_desc = &desc_info->src_desc_ring[tail]; - src_desc->control |= BIT(DIT_DESC_C_TAIL); - src_desc->control |= BIT(DIT_DESC_C_INT); + cpif_set_bit(src_desc->control, DIT_DESC_C_TAIL); + cpif_set_bit(src_desc->control, DIT_DESC_C_INT); + DIT_INDIRECT_CALL(dc, set_src_desc_tail, dir, desc_info, tail); src_desc = &desc_info->src_desc_ring[desc_info->src_desc_ring_len - 1]; - src_desc->control |= BIT(DIT_DESC_C_RINGEND); + cpif_set_bit(src_desc->control, DIT_DESC_C_RINGEND); dit_set_snapshot(dir, DIT_SRC_DESC_RING, head, tail, circ_get_usage(desc_info->src_desc_ring_len, tail, head) + 1); @@ -616,7 +614,8 @@ static void dit_set_dst_desc_int_range(enum dit_direction dir, dst_desc = desc_info->dst_desc_ring[ring_num]; dst_wp_pos = desc_info->dst_wp[ring_num]; - p_desc = virt_to_phys(&dst_desc[dst_wp_pos]); + p_desc = desc_info->dst_desc_ring_daddr[ring_num] + + (sizeof(struct dit_dst_desc) * dst_wp_pos); switch (ring_num) { case DIT_DST_DESC_RING_0: @@ -653,21 +652,20 @@ static void dit_set_dst_desc_int_range(enum dit_direction dir, if (offset_lo && offset_hi && (desc_info->dst_desc_ring_len > 0)) { WRITE_REG_PADDR_LO(dc, p_desc, offset_lo); WRITE_REG_PADDR_HI(dc, p_desc, offset_hi); - dst_desc[desc_info->dst_desc_ring_len - 1].control |= BIT(DIT_DESC_C_RINGEND); + cpif_set_bit(dst_desc[desc_info->dst_desc_ring_len - 1].control, + DIT_DESC_C_RINGEND); } } static int dit_enqueue_src_desc_ring_internal(enum dit_direction dir, u8 *src, unsigned long src_paddr, - u16 len, u16 ch_id, bool csum) + u16 len, u8 ch_id, bool csum) { struct dit_desc_info *desc_info; struct dit_src_desc *src_desc; int remain; - struct net_device *upstream_netdev; - struct io_device *iod; int src_wp = 0; - bool filter_bypass = true; + bool is_upstream_pkt = false; #if defined(DIT_DEBUG) static unsigned int overflow; static unsigned int last_max_overflow; @@ -714,35 +712,23 @@ static int dit_enqueue_src_desc_ring_internal(enum dit_direction dir, src_desc->udp_csum_zero = 0; src_desc->control = 0; if (src_wp == (desc_info->src_desc_ring_len - 1)) - src_desc->control |= BIT(DIT_DESC_C_RINGEND); + cpif_set_bit(src_desc->control, DIT_DESC_C_RINGEND); src_desc->status = 0; - do { - if (dir != DIT_DIR_RX) - break; - /* - * check ipv6 for clat. - * port table does not have entries for tun device or ipv6. - * every ipv6 packets from any rmnet can see port table. - */ - if ((src[0] & 0xF0) == 0x60) { - filter_bypass = false; - break; - } + DIT_INDIRECT_CALL(dc, set_desc_filter_bypass, dir, src_desc, src, &is_upstream_pkt); + if (is_upstream_pkt) + dit_set_src_desc_udp_csum_zero(src_desc, src); - /* check upstream netdev */ - upstream_netdev = dit_hal_get_dst_netdev(DIT_DST_DESC_RING_0); - if (upstream_netdev) { - iod = link_get_iod_with_channel(dc->ld, ch_id); - if (iod && (upstream_netdev == iod->ndev)) { - dit_set_src_desc_udp_csum_zero(src_desc, src); - filter_bypass = false; - break; - } - } - } while (0); + if (dc->use_dma_map && dir == DIT_DIR_TX) { + dma_addr_t daddr; - dit_set_src_desc_filter_bypass(src_desc, filter_bypass); + daddr = dma_map_single(dc->dev, src, len, DMA_TO_DEVICE); + if (dma_mapping_error(dc->dev, daddr)) { + mif_err("dit dir[%d] src skb[%d] dma_map_single failed\n", dir, src_wp); + return -ENOMEM; + } + dma_unmap_single(dc->dev, daddr, len, DMA_TO_DEVICE); + } barrier(); @@ -762,7 +748,7 @@ static int dit_enqueue_src_desc_ring_internal(enum dit_direction dir, int dit_enqueue_src_desc_ring(enum dit_direction dir, u8 *src, unsigned long src_paddr, - u16 len, u16 ch_id, bool csum) + u16 len, u8 ch_id, bool csum) { return dit_enqueue_src_desc_ring_internal( dir, src, src_paddr, len, ch_id, csum); @@ -817,7 +803,6 @@ static int dit_fill_rx_dst_data_buffer(enum dit_desc_ring ring_num, unsigned int struct dit_desc_info *desc_info; struct dit_dst_desc *dst_desc; struct sk_buff **dst_skb; - unsigned int buf_size; unsigned int dst_rp_pos; gfp_t gfp_mask; int i; @@ -834,18 +819,28 @@ static int dit_fill_rx_dst_data_buffer(enum dit_desc_ring ring_num, unsigned int return 0; if (unlikely(!desc_info->dst_skb_buf[ring_num])) { - buf_size = sizeof(struct sk_buff *) * desc_info->dst_desc_ring_len; - desc_info->dst_skb_buf[ring_num] = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + unsigned int buf_size = sizeof(struct sk_buff *) * desc_info->dst_desc_ring_len; + + desc_info->dst_skb_buf[ring_num] = kvzalloc(buf_size, GFP_KERNEL); if (!desc_info->dst_skb_buf[ring_num]) { mif_err("dit dst[%d] skb container alloc failed\n", ring_num); return -ENOMEM; } } + if (dc->use_dma_map && unlikely(!desc_info->dst_skb_buf_daddr[ring_num])) { + unsigned int buf_size = sizeof(dma_addr_t) * desc_info->dst_desc_ring_len; + + desc_info->dst_skb_buf_daddr[ring_num] = kvzalloc(buf_size, GFP_KERNEL); + if (!desc_info->dst_skb_buf_daddr[ring_num]) { + mif_err("dit dst[%d] skb dma addr container alloc failed\n", ring_num); + return -ENOMEM; + } + } + dst_desc = desc_info->dst_desc_ring[ring_num]; dst_skb = desc_info->dst_skb_buf[ring_num]; dst_rp_pos = desc_info->dst_rp[ring_num]; - buf_size = desc_info->buf_size; /* fill free space */ for (i = 0; i < read; i++) { @@ -853,25 +848,67 @@ static int dit_fill_rx_dst_data_buffer(enum dit_desc_ring ring_num, unsigned int goto next; if (unlikely(dst_skb[dst_rp_pos])) - goto next; + goto dma_map; - if (initial) { + if (desc_info->dst_page_pool[ring_num]) { + void *data; + bool used_tmp_alloc; + u16 len = SKB_DATA_ALIGN(dc->desc_info[DIT_DIR_RX].buf_size); + + len += SKB_DATA_ALIGN(dc->page_recycling_skb_padding); + len += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + + data = cpif_page_alloc(desc_info->dst_page_pool[ring_num], len, + &used_tmp_alloc); + if (!data) { + mif_err("dit dst[%d] skb[%d] recycle pg alloc failed\n", + ring_num, dst_rp_pos); + return -ENOMEM; + } + + dst_skb[dst_rp_pos] = build_skb(data, len); + } else if (initial) { gfp_mask = GFP_KERNEL; if (ring_num == DIT_DST_DESC_RING_0) gfp_mask = GFP_ATOMIC; - dst_skb[dst_rp_pos] = __netdev_alloc_skb(dc->netdev, buf_size, gfp_mask); - } else - dst_skb[dst_rp_pos] = napi_alloc_skb(&dc->napi, buf_size); + dst_skb[dst_rp_pos] = __netdev_alloc_skb_ip_align(dc->netdev, + desc_info->buf_size, + gfp_mask); + } else { + dst_skb[dst_rp_pos] = napi_alloc_skb(&dc->napi, desc_info->buf_size); + } if (unlikely(!dst_skb[dst_rp_pos])) { mif_err("dit dst[%d] skb[%d] build failed\n", ring_num, dst_rp_pos); return -ENOMEM; } + if (desc_info->dst_page_pool[ring_num]) + skb_reserve(dst_skb[dst_rp_pos], dc->page_recycling_skb_padding); + #if defined(DIT_DEBUG_LOW) snapshot[DIT_DIR_RX][ring_num].alloc_skbs++; #endif + +dma_map: + if (dc->use_dma_map && !desc_info->dst_skb_buf_daddr[ring_num][dst_rp_pos]) { + dma_addr_t daddr; + + daddr = dma_map_single(dc->dev, dst_skb[dst_rp_pos]->data, + desc_info->buf_size, DMA_FROM_DEVICE); + if (dma_mapping_error(dc->dev, daddr)) { + mif_err("dit dst[%d] skb[%d] dma_map_single failed\n", + ring_num, dst_rp_pos); + return -ENOMEM; + } + + desc_info->dst_skb_buf_daddr[ring_num][dst_rp_pos] = daddr; +#if defined(DIT_DEBUG_LOW) + snapshot[DIT_DIR_RX][ring_num].dma_maps++; +#endif + } + dst_desc[dst_rp_pos].dst_addr = virt_to_phys(dst_skb[dst_rp_pos]->data); next: @@ -916,6 +953,16 @@ static int dit_free_dst_data_buffer(enum dit_direction dir, enum dit_desc_ring r for (i = 0; i < desc_info->dst_desc_ring_len; i++) { if (dst_skb[i]) { + if (dc->use_dma_map && desc_info->dst_skb_buf_daddr[ring_num] && + desc_info->dst_skb_buf_daddr[ring_num][i]) { +#if defined(DIT_DEBUG_LOW) + snapshot[DIT_DIR_RX][ring_num].dma_maps--; +#endif + dma_unmap_single(dc->dev, + desc_info->dst_skb_buf_daddr[ring_num][i], + desc_info->buf_size, DMA_FROM_DEVICE); + } + #if defined(DIT_DEBUG_LOW) snapshot[dir][ring_num].alloc_skbs--; #endif @@ -925,7 +972,13 @@ static int dit_free_dst_data_buffer(enum dit_direction dir, enum dit_desc_ring r } mif_info("free dst[%d] skb buffers\n", ring_num); - devm_kfree(dc->dev, dst_skb); + + if (dc->use_dma_map) { + kvfree(desc_info->dst_skb_buf_daddr[ring_num]); + desc_info->dst_skb_buf_daddr[ring_num] = NULL; + } + + kvfree(dst_skb); desc_info->dst_skb_buf[ring_num] = NULL; desc_info->dst_skb_buf_filled[ring_num] = false; @@ -985,6 +1038,7 @@ int dit_read_rx_dst_poll(struct napi_struct *napi, int budget) struct sk_buff *skb; unsigned int rcvd_total = 0; unsigned int usage; + unsigned int dst_rp_pos; unsigned int ring_num; int i, ret; #if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) @@ -999,15 +1053,32 @@ int dit_read_rx_dst_poll(struct napi_struct *napi, int budget) if (rcvd_total >= budget) break; + dst_rp_pos = desc_info->dst_rp[ring_num]; + /* get dst desc and skb */ - dst_desc = &desc_info->dst_desc_ring[ring_num][desc_info->dst_rp[ring_num]]; - skb = desc_info->dst_skb_buf[ring_num][desc_info->dst_rp[ring_num]]; + dst_desc = &desc_info->dst_desc_ring[ring_num][dst_rp_pos]; + + if (dc->use_dma_map) { + dma_addr_t daddr = + desc_info->dst_skb_buf_daddr[ring_num][dst_rp_pos]; + + if (daddr) { +#if defined(DIT_DEBUG_LOW) + snapshot[DIT_DIR_RX][ring_num].dma_maps--; +#endif + dma_unmap_single(dc->dev, daddr, desc_info->buf_size, + DMA_FROM_DEVICE); + desc_info->dst_skb_buf_daddr[ring_num][dst_rp_pos] = 0; + } + } + + skb = desc_info->dst_skb_buf[ring_num][dst_rp_pos]; /* try to fill dst data buffers */ - desc_info->dst_skb_buf[ring_num][desc_info->dst_rp[ring_num]] = NULL; + desc_info->dst_skb_buf[ring_num][dst_rp_pos] = NULL; ret = dit_fill_rx_dst_data_buffer(ring_num, 1, false); if (ret) { - desc_info->dst_skb_buf[ring_num][desc_info->dst_rp[ring_num]] = skb; + desc_info->dst_skb_buf[ring_num][dst_rp_pos] = skb; break; } @@ -1021,8 +1092,8 @@ int dit_read_rx_dst_poll(struct napi_struct *napi, int budget) skbpriv(skb)->napi = napi; /* clat */ - if ((dst_desc->packet_info & BIT(DIT_PACKET_INFO_IPV6_BIT)) && - ((skb->data[0] & 0xFF) == 0x45)) { + if (cpif_check_bit(dst_desc->packet_info, DIT_PACKET_INFO_IPV6_BIT) && + ((skb->data[0] & 0xFF) == 0x45)) { skbpriv(skb)->rx_clat = 1; snapshot[DIT_DIR_RX][ring_num].clat_packets++; } @@ -1030,22 +1101,25 @@ int dit_read_rx_dst_poll(struct napi_struct *napi, int budget) /* hw checksum */ dit_set_skb_checksum(dst_desc, ring_num, skb); - /* reset udp checksum if it was 0 */ + /* adjust udp zero checksum */ dit_set_skb_udp_csum_zero(dst_desc, ring_num, skb); dst_desc->packet_info = 0; + dst_desc->control = 0; + if (dst_rp_pos == desc_info->dst_desc_ring_len - 1) + cpif_set_bit(dst_desc->control, DIT_DESC_C_RINGEND); dst_desc->status = 0; - rcvd_total++; + ret = dit_pass_to_net(ring_num, skb); - /* update dst rp */ + /* update dst rp after dit_pass_to_net */ desc_info->dst_rp[ring_num] = circ_new_ptr(desc_info->dst_desc_ring_len, - desc_info->dst_rp[ring_num], 1); - + dst_rp_pos, 1); + rcvd_total++; #if defined(DIT_DEBUG_LOW) snapshot[DIT_DIR_RX][ring_num].alloc_skbs--; #endif - ret = dit_pass_to_net(ring_num, skb); + if (ret < 0) break; } @@ -1056,14 +1130,6 @@ int dit_read_rx_dst_poll(struct napi_struct *napi, int budget) mld->tpmon->start(); #endif - if (atomic_read(&dc->stop_napi_poll)) { - atomic_set(&dc->stop_napi_poll, 0); - napi_complete(napi); - /* kick can be reserved if dst buffer was not enough */ - dit_kick(DIT_DIR_RX, true); - return 0; - } - if (rcvd_total < budget) { napi_complete_done(napi, rcvd_total); /* kick can be reserved if dst buffer was not enough */ @@ -1087,11 +1153,11 @@ static void dit_update_dst_desc_pos(enum dit_direction dir, enum dit_desc_ring r do { dst_desc = &desc_info->dst_desc_ring[ring_num][desc_info->dst_wp[ring_num]]; - if (!(dst_desc->status & BIT(DIT_DESC_S_DONE))) + if (!cpif_check_bit(dst_desc->status, DIT_DESC_S_DONE)) break; /* update dst */ - dst_desc->status &= ~BIT(DIT_DESC_S_DONE); + cpif_clear_bit(dst_desc->status, DIT_DESC_S_DONE); /* tx does not use status field */ if (dir == DIT_DIR_TX) dst_desc->status = 0; @@ -1114,7 +1180,7 @@ static void dit_update_dst_desc_pos(enum dit_direction dir, enum dit_desc_ring r #if defined(DIT_DEBUG) if (desc_info->dst_wp[ring_num] == desc_info->dst_rp[ring_num]) { - mif_err("dst[%d] wp[%d] would overwrite rp (dir:%d)", ring_num, + mif_err("dst[%d] wp[%d] would overwrite rp (dir:%d)\n", ring_num, desc_info->dst_wp[ring_num], dir); } #endif @@ -1128,6 +1194,8 @@ static void dit_update_dst_desc_pos(enum dit_direction dir, enum dit_desc_ring r } while (1); if (packets > 0) { + u32 qnum = desc_info->pktproc_queue_num; + dit_set_dst_desc_int_range(dir, ring_num); dit_set_snapshot(dir, ring_num, last_dst_wp, circ_prev_ptr(desc_info->dst_desc_ring_len, @@ -1139,13 +1207,11 @@ static void dit_update_dst_desc_pos(enum dit_direction dir, enum dit_desc_ring r desc_info->dst_rp[ring_num] = circ_new_ptr(desc_info->dst_desc_ring_len, desc_info->dst_rp[ring_num], packets); #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) - mld->pktproc_ul.q[DIT_PKTPROC_TX_QUEUE_NUM]->update_fore_ptr( - mld->pktproc_ul.q[DIT_PKTPROC_TX_QUEUE_NUM], packets); + mld->pktproc_ul.q[qnum]->update_fore_ptr(mld->pktproc_ul.q[qnum], packets); #endif break; case DIT_DIR_RX: - mld->pktproc.q[DIT_PKTPROC_RX_QUEUE_NUM]->update_fore_ptr( - mld->pktproc.q[DIT_PKTPROC_RX_QUEUE_NUM], packets); + mld->pktproc.q[qnum]->update_fore_ptr(mld->pktproc.q[qnum], packets); break; default: mif_err_limited("dir error:%d\n", dir); @@ -1159,8 +1225,25 @@ irqreturn_t dit_irq_handler(int irq, void *arg) int pending_bit = *((int *)(arg)); enum dit_desc_ring ring_num; struct mem_link_device *mld; + struct modem_ctl *mc; enum dit_direction dir = DIT_DIR_MAX; u32 pending_mask = DIT_ALL_INT_PENDING_MASK; + unsigned long flags; + + switch (pending_bit) { + case RX_DST0_INT_PENDING_BIT: + case TX_DST0_INT_PENDING_BIT: + ring_num = DIT_DST_DESC_RING_0; + break; + case RX_DST1_INT_PENDING_BIT: + ring_num = DIT_DST_DESC_RING_1; + break; + case RX_DST2_INT_PENDING_BIT: + ring_num = DIT_DST_DESC_RING_2; + break; + default: + break; + } switch (pending_bit) { case RX_DST0_INT_PENDING_BIT: @@ -1169,7 +1252,6 @@ irqreturn_t dit_irq_handler(int irq, void *arg) dir = DIT_DIR_RX; pending_mask = DIT_RX_INT_PENDING_MASK; - ring_num = (enum dit_desc_ring)(pending_bit - RX_DST0_INT_PENDING_BIT); dit_update_dst_desc_pos(DIT_DIR_RX, ring_num); if (napi_schedule_prep(&dc->napi)) __napi_schedule(&dc->napi); @@ -1177,14 +1259,18 @@ irqreturn_t dit_irq_handler(int irq, void *arg) case TX_DST0_INT_PENDING_BIT: dir = DIT_DIR_TX; pending_mask = DIT_TX_INT_PENDING_MASK; - mld = ld_to_mem_link_device(dc->ld); - dit_update_dst_desc_pos(DIT_DIR_TX, DIT_DST_DESC_RING_0); - send_ipc_irq(mld, mask2int(MASK_SEND_DATA)); + mc = dc->ld->mc; + + dit_update_dst_desc_pos(DIT_DIR_TX, ring_num); + spin_lock_irqsave(&mc->lock, flags); + if (ipc_active(mld)) + send_ipc_irq(mld, mask2int(MASK_SEND_DATA)); + spin_unlock_irqrestore(&mc->lock, flags); break; case ERR_INT_PENDING_BIT: /* nothing to do when ERR interrupt */ - mif_err_limited("ERR interrupt!! int_pending: 0x%X", + mif_err_limited("ERR interrupt!! int_pending: 0x%X\n", READ_REG_VALUE(dc, DIT_REG_INT_PENDING)); break; default: @@ -1216,7 +1302,7 @@ irqreturn_t dit_irq_handler(int irq, void *arg) return IRQ_HANDLED; } -static bool dit_is_busy(enum dit_direction dir) +bool dit_is_busy(enum dit_direction dir) { u32 status_bits = 0; u32 status_mask = 0; @@ -1304,10 +1390,10 @@ int dit_kick(enum dit_direction dir, bool retry) switch (dir) { case DIT_DIR_TX: - kick_mask = BIT(TX_COMMAND_BIT); + cpif_set_bit(kick_mask, TX_COMMAND_BIT); break; case DIT_DIR_RX: - kick_mask = BIT(RX_COMMAND_BIT); + cpif_set_bit(kick_mask, RX_COMMAND_BIT); break; default: break; @@ -1346,7 +1432,7 @@ static bool dit_check_nat_enabled(void) static void dit_check_clat_enabled_internal(struct io_device *iod, void *args) { - bool *enabled = (bool *) args; + bool *enabled = (bool *)args; if (*enabled || !dc->ld->is_ps_ch(iod->ch)) return; @@ -1368,14 +1454,15 @@ static bool dit_check_clat_enabled(void) } static int dit_reg_backup_restore_internal(bool backup, const u16 *offset, - const u16 *size, void **buf, const unsigned int arr_len) + const u16 *size, void **buf, + const unsigned int arr_len) { unsigned int i; int ret = 0; for (i = 0; i < arr_len; i++) { if (!buf[i]) { - buf[i] = devm_kzalloc(dc->dev, size[i], GFP_KERNEL); + buf[i] = kvzalloc(size[i], GFP_KERNEL); if (!buf[i]) { ret = -ENOMEM; goto exit; @@ -1409,9 +1496,9 @@ static int dit_reg_backup_restore(bool backup) DIT_REG_NAT_RX_PORT_TABLE_SLOT, }; static const u16 nat_size[] = { - DIT_REG_NAT_LOCAL_ADDR_MAX * DIT_REG_NAT_LOCAL_INTERVAL, - DIT_REG_NAT_LOCAL_ADDR_MAX * DIT_REG_ETHERNET_MAC_INTERVAL, - DIT_REG_NAT_LOCAL_PORT_MAX * DIT_REG_NAT_LOCAL_INTERVAL, + (DIT_REG_NAT_LOCAL_ADDR_MAX * DIT_REG_NAT_LOCAL_INTERVAL), + (DIT_REG_NAT_LOCAL_ADDR_MAX * DIT_REG_ETHERNET_MAC_INTERVAL), + (DIT_REG_NAT_LOCAL_PORT_MAX * DIT_REG_NAT_LOCAL_INTERVAL), }; static const unsigned int nat_len = ARRAY_SIZE(nat_offset); static void *nat_buf[ARRAY_SIZE(nat_offset)]; @@ -1423,27 +1510,30 @@ static int dit_reg_backup_restore(bool backup) DIT_REG_CLAT_TX_CLAT_SRC_0, }; static const u16 clat_size[] = { - DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_FILTER_INTERVAL, - DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL, - DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL, + (DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_FILTER_INTERVAL), + (DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL), + (DIT_REG_CLAT_ADDR_MAX * DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL), }; static const unsigned int clat_len = ARRAY_SIZE(clat_offset); static void *clat_buf[ARRAY_SIZE(clat_offset)]; int ret = 0; + if (unlikely(!dc)) + return -EPERM; + /* NAT */ if (dit_check_nat_enabled()) { - ret = dit_reg_backup_restore_internal(backup, nat_offset, nat_size, nat_buf, - nat_len); + ret = dit_reg_backup_restore_internal(backup, nat_offset, + nat_size, nat_buf, nat_len); if (ret) goto error; } /* CLAT */ if (dit_check_clat_enabled()) { - ret = dit_reg_backup_restore_internal(backup, clat_offset, clat_size, clat_buf, - clat_len); + ret = dit_reg_backup_restore_internal(backup, clat_offset, + clat_size, clat_buf, clat_len); if (ret) goto error; } @@ -1456,6 +1546,40 @@ static int dit_reg_backup_restore(bool backup) return ret; } +#define POOL_PAGE_SIZE 32768 +static int dit_init_page_pool(enum dit_direction dir, enum dit_desc_ring ring_num) +{ + struct dit_desc_info *desc_info; + u64 total_page_count; + u64 num_pkt_per_page; + u64 max_pkt_size; + + if (!dc->use_page_recycling_rx) + return 0; + + /* Support Rx DST0 only */ + if (dir != DIT_DIR_RX || ring_num != DIT_DST_DESC_RING_0) + return 0; + + desc_info = &dc->desc_info[dir]; + if (desc_info->dst_page_pool[ring_num]) + return 0; + + max_pkt_size = desc_info->buf_size + dc->page_recycling_skb_padding + + sizeof(struct skb_shared_info); + num_pkt_per_page = POOL_PAGE_SIZE / max_pkt_size; + total_page_count = desc_info->dst_desc_ring_len / num_pkt_per_page; + + desc_info->dst_page_pool[ring_num] = cpif_page_pool_create(total_page_count, + POOL_PAGE_SIZE); + if (unlikely(!desc_info->dst_page_pool[ring_num])) + return -ENOMEM; + + cpif_page_init_tmp_page(desc_info->dst_page_pool[ring_num]); + + return 0; +} + static int dit_init_hw(void) { unsigned int dir; @@ -1512,11 +1636,15 @@ static int dit_init_hw(void) WRITE_REG_VALUE(dc, DIT_RX_BURST_16BEAT, DIT_REG_RX_CHKSUM_CTRL); WRITE_REG_VALUE(dc, DIT_INT_ENABLE_MASK, DIT_REG_INT_ENABLE); - WRITE_REG_VALUE(dc, DIT_INT_ENABLE_MASK, DIT_REG_INT_MASK); + WRITE_REG_VALUE(dc, DIT_INT_MASK_MASK, DIT_REG_INT_MASK); WRITE_REG_VALUE(dc, DIT_ALL_INT_PENDING_MASK, DIT_REG_INT_PENDING); WRITE_REG_VALUE(dc, 0x0, DIT_REG_CLK_GT_OFF); + DIT_INDIRECT_CALL(dc, do_init_hw); + if (!dc->reg_version) + DIT_INDIRECT_CALL(dc, get_reg_version, &dc->reg_version); + WRITE_SHR_VALUE(dc, dc->sharability_value); return 0; @@ -1527,22 +1655,31 @@ static int dit_init_desc(enum dit_direction dir) struct dit_desc_info *desc_info = &dc->desc_info[dir]; void *buf = NULL; unsigned int buf_size; - phys_addr_t p_buf; + phys_addr_t p_desc; int ret = 0, ring_num; u32 offset_lo = 0, offset_hi = 0; if (!desc_info->src_desc_ring) { buf_size = sizeof(struct dit_src_desc) * (desc_info->src_desc_ring_len + DIT_SRC_DESC_RING_LEN_PADDING); - buf = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + + if (dc->use_dma_map) { + buf = dma_alloc_coherent(dc->dev, buf_size, &desc_info->src_desc_ring_daddr, + GFP_KERNEL); + } else { + buf = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + } if (!buf) { mif_err("dit dir[%d] src desc alloc failed\n", dir); return -ENOMEM; } + desc_info->src_desc_ring = buf; + if (!dc->use_dma_map) + desc_info->src_desc_ring_daddr = virt_to_phys(buf); } - p_buf = virt_to_phys(desc_info->src_desc_ring); + p_desc = desc_info->src_desc_ring_daddr; if (dir == DIT_DIR_TX) { offset_lo = DIT_REG_TX_RING_START_ADDR_0_SRC; offset_hi = DIT_REG_TX_RING_START_ADDR_1_SRC; @@ -1550,12 +1687,12 @@ static int dit_init_desc(enum dit_direction dir) offset_lo = DIT_REG_RX_RING_START_ADDR_0_SRC; offset_hi = DIT_REG_RX_RING_START_ADDR_1_SRC; } - WRITE_REG_PADDR_LO(dc, p_buf, offset_lo); - WRITE_REG_PADDR_HI(dc, p_buf, offset_hi); + WRITE_REG_PADDR_LO(dc, p_desc, offset_lo); + WRITE_REG_PADDR_HI(dc, p_desc, offset_hi); if (!desc_info->src_skb_buf) { buf_size = sizeof(struct sk_buff *) * desc_info->src_desc_ring_len; - buf = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + buf = kvzalloc(buf_size, GFP_KERNEL); if (!buf) { mif_err("dit dir[%d] src skb container alloc failed\n", dir); return -ENOMEM; @@ -1568,16 +1705,33 @@ static int dit_init_desc(enum dit_direction dir) offset_hi = 0; if (!desc_info->dst_desc_ring[ring_num]) { - buf_size = sizeof(struct dit_dst_desc) * desc_info->dst_desc_ring_len; - buf = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + buf_size = sizeof(struct dit_dst_desc) * + (desc_info->dst_desc_ring_len + DIT_DST_DESC_RING_LEN_PADDING); + + if (dc->use_dma_map) { + buf = dma_alloc_coherent(dc->dev, buf_size, + &desc_info->dst_desc_ring_daddr[ring_num], + GFP_KERNEL); + } else { + buf = devm_kzalloc(dc->dev, buf_size, GFP_KERNEL); + } if (!buf) { mif_err("dit dir[%d] dst desc[%d] alloc failed\n", dir, ring_num); return -ENOMEM; } + desc_info->dst_desc_ring[ring_num] = buf; + if (!dc->use_dma_map) + desc_info->dst_desc_ring_daddr[ring_num] = virt_to_phys(buf); + } + + ret = dit_init_page_pool(dir, ring_num); + if (ret) { + mif_err("dit dir[%d] dst desc[%d] page pool init failed\n", dir, ring_num); + return -ENOMEM; } - p_buf = virt_to_phys(desc_info->dst_desc_ring[ring_num]); + p_desc = desc_info->dst_desc_ring_daddr[ring_num]; switch (ring_num) { case DIT_DST_DESC_RING_0: if (dir == DIT_DIR_TX) { @@ -1621,13 +1775,15 @@ static int dit_init_desc(enum dit_direction dir) } if (offset_lo && offset_hi) { - WRITE_REG_PADDR_LO(dc, p_buf, offset_lo); - WRITE_REG_PADDR_HI(dc, p_buf, offset_hi); + WRITE_REG_PADDR_LO(dc, p_desc, offset_lo); + WRITE_REG_PADDR_HI(dc, p_desc, offset_hi); } dit_set_dst_desc_int_range(dir, ring_num); } + DIT_INDIRECT_CALL(dc, do_init_desc, dir); + mif_info("dir:%d src_len:%d dst_len:%d\n", dir, desc_info->src_desc_ring_len, desc_info->dst_desc_ring_len); @@ -1658,7 +1814,9 @@ int dit_init(struct link_device *ld, enum dit_init_type type, enum dit_store_typ } if (dit_is_kicked_any()) { - dc->init_reserved = true; + if (type != DIT_INIT_DEINIT) + dc->init_reserved = true; + spin_unlock_irqrestore(&dc->src_lock, flags); return -EEXIST; } @@ -1730,46 +1888,40 @@ int dit_init(struct link_device *ld, enum dit_init_type type, enum dit_store_typ } EXPORT_SYMBOL(dit_init); -int dit_deinit(void) -{ - return 0; -} -EXPORT_SYMBOL(dit_deinit); - static int dit_register_irq(struct platform_device *pdev) { - static int irq_pending_bit[] = { - RX_DST0_INT_PENDING_BIT, RX_DST1_INT_PENDING_BIT, RX_DST2_INT_PENDING_BIT, - TX_DST0_INT_PENDING_BIT, ERR_INT_PENDING_BIT}; - static char const *irq_name[] = { - "DIT-RxDst0", "DIT-RxDst1", "DIT-RxDst2", - "DIT-Tx", "DIT-Err"}; - struct device *dev = &pdev->dev; - int irq_len = ARRAY_SIZE(irq_pending_bit); - int irq_num; int ret = 0; int i; - dc->irq_buf = devm_kzalloc(dev, sizeof(int) * irq_len, GFP_KERNEL); + if (!dc->irq_len) { + mif_err("dit irq not defined\n"); + return -ENODEV; + } + + dc->irq_buf = devm_kzalloc(dev, sizeof(int) * dc->irq_len, GFP_KERNEL); if (!dc->irq_buf) { mif_err("dit irq buf alloc failed\n"); ret = -ENOMEM; goto error; } - for (i = 0; i < irq_len; i++) { - irq_num = platform_get_irq_byname(pdev, irq_name[i]); - ret = devm_request_irq(dev, irq_num, dit_irq_handler, 0, irq_name[i], - &irq_pending_bit[i]); + for (i = 0; i < dc->irq_len; i++) { + int irq_num; + + irq_num = platform_get_irq_byname(pdev, dc->irq_name[i]); + ret = devm_request_irq(dev, irq_num, dit_irq_handler, 0, dc->irq_name[i], + &dc->irq_pending_bit[i]); if (ret) { mif_err("failed to request irq: %d, ret: %d\n", i, ret); ret = -EIO; goto error; } + + if (dc->irq_pending_bit[i] == TX_DST0_INT_PENDING_BIT) + dc->irq_num_tx = irq_num; dc->irq_buf[i] = irq_num; } - dc->irq_len = irq_len; return 0; @@ -1789,8 +1941,12 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch unsigned int wp, rp, desc_len; unsigned int dir, ring_num; - count += scnprintf(&buf[count], PAGE_SIZE - count, "use tx: %d, rx: %d, clat: %d\n", - dc->use_tx, dc->use_rx, dc->use_clat); + count += scnprintf(&buf[count], PAGE_SIZE - count, "hw_ver:0x%08X reg_ver:0x%X\n", + dc->hw_version, dc->reg_version); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "use tx:%d rx:%d(stop:%d) clat:%d page_recycle:%d\n", + dc->use_dir[DIT_DIR_TX], dc->use_dir[DIT_DIR_RX], dc->stop_enqueue[DIT_DIR_RX], + dc->use_clat, dc->use_page_recycling_rx); for (dir = 0; dir < DIT_DIR_MAX; dir++) { desc_info = &dc->desc_info[dir]; @@ -1806,10 +1962,12 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch } count += scnprintf(&buf[count], PAGE_SIZE - count, - "%s max_usage(d)/alloc(d)/total: %u/%u/%u\n", + "%s max_usage(d)/alloc(d)/map(d)/total: %u/%u/%u/%u\n", snapshot[dir][ring_num].name, snapshot[dir][ring_num].max_usage, - snapshot[dir][ring_num].alloc_skbs, desc_len); + snapshot[dir][ring_num].alloc_skbs, + snapshot[dir][ring_num].dma_maps, + desc_len); count += scnprintf(&buf[count], PAGE_SIZE - count, " wp: %u, rp: %u\n", wp, rp); count += scnprintf(&buf[count], PAGE_SIZE - count, @@ -1990,14 +2148,14 @@ static ssize_t debug_use_tx_store(struct device *dev, struct device_attribute *a if (ret) return -EINVAL; - dc->use_tx = (flag > 0 ? true : false); + dc->use_dir[DIT_DIR_TX] = (flag > 0 ? true : false); return count; } static ssize_t debug_use_tx_show(struct device *dev, struct device_attribute *attr, char *buf) { - return scnprintf(buf, PAGE_SIZE, "use_tx: %d\n", dc->use_tx); + return scnprintf(buf, PAGE_SIZE, "use_tx: %d\n", dc->use_dir[DIT_DIR_TX]); } static ssize_t debug_use_rx_store(struct device *dev, struct device_attribute *attr, @@ -2010,14 +2168,14 @@ static ssize_t debug_use_rx_store(struct device *dev, struct device_attribute *a if (ret) return -EINVAL; - dc->use_rx = (flag > 0 ? true : false); + dc->use_dir[DIT_DIR_RX] = (flag > 0 ? true : false); return count; } static ssize_t debug_use_rx_show(struct device *dev, struct device_attribute *attr, char *buf) { - return scnprintf(buf, PAGE_SIZE, "use_rx: %d\n", dc->use_rx); + return scnprintf(buf, PAGE_SIZE, "use_rx: %d\n", dc->use_dir[DIT_DIR_RX]); } static ssize_t debug_use_clat_store(struct device *dev, struct device_attribute *attr, @@ -2027,6 +2185,7 @@ static ssize_t debug_use_clat_store(struct device *dev, struct device_attribute unsigned int i; unsigned int flag; int ret; + struct mem_link_device *mld = ld_to_mem_link_device(dc->ld); ret = kstrtoint(buf, 0, &flag); if (ret) @@ -2035,9 +2194,9 @@ static ssize_t debug_use_clat_store(struct device *dev, struct device_attribute if (!flag) { memset(&clat, 0, sizeof(clat)); for (i = 0; i < DIT_REG_CLAT_ADDR_MAX; i++) { - clat.rmnet_index = i; + clat.clat_index = i; scnprintf(clat.ipv6_iface, IFNAMSIZ, "rmnet%d", i); - dit_hal_set_clat_info(&clat); + dit_hal_set_clat_info(mld, &clat); } } @@ -2051,6 +2210,26 @@ static ssize_t debug_use_clat_show(struct device *dev, struct device_attribute * { return scnprintf(buf, PAGE_SIZE, "use_clat: %d\n", dc->use_clat); } + +static ssize_t debug_hal_support_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned int flag; + int ret; + + ret = kstrtoint(buf, 0, &flag); + if (ret) + return -EINVAL; + + dc->hal_support = (flag > 0 ? true : false); + return count; +} + +static ssize_t debug_hal_support_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "hal_support: %d\n", dc->hal_support); +} #endif #if defined(DIT_DEBUG_LOW) @@ -2063,6 +2242,7 @@ static ssize_t debug_pktgen_ch_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { + struct io_device *iod; int ch; int ret; @@ -2072,6 +2252,16 @@ static ssize_t debug_pktgen_ch_store(struct device *dev, dc->pktgen_ch = ch; + if (!dc->ld) + goto out; + + iod = link_get_iod_with_channel(dc->ld, dc->pktgen_ch); + if (iod) + DIT_INDIRECT_CALL(dc, set_reg_upstream, iod->ndev); + else + DIT_INDIRECT_CALL(dc, set_reg_upstream, NULL); + +out: return count; } @@ -2100,6 +2290,7 @@ static DEVICE_ATTR_WO(debug_reset_usage); static DEVICE_ATTR_RW(debug_use_tx); static DEVICE_ATTR_RW(debug_use_rx); static DEVICE_ATTR_RW(debug_use_clat); +static DEVICE_ATTR_RW(debug_hal_support); #endif #if defined(DIT_DEBUG_LOW) static DEVICE_ATTR_RW(debug_pktgen_ch); @@ -2116,6 +2307,7 @@ static struct attribute *dit_attrs[] = { &dev_attr_debug_use_tx.attr, &dev_attr_debug_use_rx.attr, &dev_attr_debug_use_clat.attr, + &dev_attr_debug_hal_support.attr, #endif #if defined(DIT_DEBUG_LOW) &dev_attr_debug_pktgen_ch.attr, @@ -2128,23 +2320,19 @@ ATTRIBUTE_GROUPS(dit); bool dit_check_dir_use_queue(enum dit_direction dir, unsigned int queue_num) { + struct dit_desc_info *desc_info; + if (!dc) return false; - switch (dir) { - case DIT_DIR_TX: - if (dc->use_tx && (queue_num == DIT_PKTPROC_TX_QUEUE_NUM)) - return true; - break; - case DIT_DIR_RX: - if (dc->use_rx && (queue_num == DIT_PKTPROC_RX_QUEUE_NUM)) - return true; - break; - default: - break; - } + desc_info = &dc->desc_info[dir]; + if (!dc->use_dir[dir] || queue_num != desc_info->pktproc_queue_num) + return false; - return false; + if (dc->stop_enqueue[dir] && dit_check_queues_empty(dir)) + return false; + + return true; } EXPORT_SYMBOL(dit_check_dir_use_queue); @@ -2178,14 +2366,34 @@ int dit_set_irq_affinity(int affinity) dc->irq_affinity = affinity; for (i = 0; i < dc->irq_len; i++) { - mif_debug("num:%d affinity:%d\n", dc->irq_buf[i], affinity); - irq_set_affinity_hint(dc->irq_buf[i], cpumask_of(affinity)); + int val = dc->irq_affinity; + + if (dc->irq_buf[i] == dc->irq_num_tx) + val = dc->irq_affinity_tx; + + mif_debug("num:%d affinity:%d\n", dc->irq_buf[i], val); + irq_set_affinity_hint(dc->irq_buf[i], cpumask_of(val)); } return 0; } EXPORT_SYMBOL(dit_set_irq_affinity); +int dit_set_pktproc_queue_num(enum dit_direction dir, u32 queue_num) +{ + struct dit_desc_info *desc_info; + + if (!dc) + return -EPERM; + + desc_info = &dc->desc_info[dir]; + desc_info->pktproc_queue_num = queue_num; + mif_info("dir:%d queue_num:%d\n", dir, desc_info->pktproc_queue_num); + + return 0; +} +EXPORT_SYMBOL(dit_set_pktproc_queue_num); + int dit_set_buf_size(enum dit_direction dir, u32 size) { struct dit_desc_info *desc_info = NULL; @@ -2264,7 +2472,7 @@ int dit_reset_dst_wp_rp(enum dit_direction dir) return -EPERM; desc_info = &dc->desc_info[dir]; - for (ring_num = 0; ring_num < DIT_DST_DESC_RING_MAX; ring_num++) { + for (ring_num = DIT_DST_DESC_RING_0; ring_num < DIT_DST_DESC_RING_MAX; ring_num++) { desc_info->dst_wp[ring_num] = 0; desc_info->dst_rp[ring_num] = 0; dit_set_dst_desc_int_range(dir, ring_num); @@ -2283,36 +2491,74 @@ struct net_device *dit_get_netdev(void) } EXPORT_SYMBOL(dit_get_netdev); -int dit_stop_napi_poll(void) +bool dit_support_clat(void) { if (!dc) - return -EPERM; + return false; - atomic_set(&dc->stop_napi_poll, 1); + return dc->use_clat; +} +EXPORT_SYMBOL(dit_support_clat); - return 0; +#if IS_ENABLED(CONFIG_EXYNOS_ITMON) +static int itmon_notifier_callback(struct notifier_block *nb, + unsigned long action, void *nb_data) +{ + struct itmon_notifier *itmon_data = nb_data; + + if (IS_ERR_OR_NULL(itmon_data)) + return NOTIFY_DONE; + + if (itmon_data->port && !strncmp("DIT", itmon_data->port, sizeof("DIT") - 1)) { + dit_print_dump(DIT_DIR_TX, DIT_DUMP_ALL); + dit_print_dump(DIT_DIR_RX, DIT_DUMP_ALL); + return NOTIFY_BAD; + } + + return NOTIFY_DONE; } -EXPORT_SYMBOL(dit_stop_napi_poll); +#endif -static int dit_read_dt(struct device_node *np) +static void dit_set_hw_specific(void) { - mif_dt_read_u32(np, "dit_sharability_offset", dc->sharability_offset); - mif_dt_read_u32(np, "dit_sharability_value", dc->sharability_value); +#if defined(CONFIG_EXYNOS_DIT_VERSION) + dc->hw_version = CONFIG_EXYNOS_DIT_VERSION; +#else + dc->hw_version = DIT_VERSION(2, 1, 0); +#endif - mif_dt_read_u32(np, "dit_hw_version", dc->hw_version); - mif_dt_read_u32(np, "dit_hw_capabilities", dc->hw_capabilities); #if defined(CONFIG_SOC_GS101) dc->hw_capabilities |= DIT_CAP_MASK_PORT_BIG_ENDIAN; /* chipid: A0 = 0, B0 = 1 */ if (gs_chipid_get_type() >= 1) dc->hw_capabilities &= ~DIT_CAP_MASK_PORT_BIG_ENDIAN; #endif - mif_dt_read_bool(np, "dit_use_tx", dc->use_tx); - mif_dt_read_bool(np, "dit_use_rx", dc->use_rx); +} + +static int dit_read_dt(struct device_node *np) +{ + if (!IS_ERR_OR_NULL(dc->sharability_base)) { + mif_dt_read_u32(np, "dit_sharability_offset", dc->sharability_offset); + mif_dt_read_u32(np, "dit_sharability_value", dc->sharability_value); + } + + mif_dt_read_u32(np, "dit_hw_capabilities", dc->hw_capabilities); + + mif_dt_read_bool(np, "dit_use_tx", dc->use_dir[DIT_DIR_TX]); + mif_dt_read_bool(np, "dit_use_rx", dc->use_dir[DIT_DIR_RX]); mif_dt_read_bool(np, "dit_use_clat", dc->use_clat); - mif_dt_read_bool(np, "dit_hal_linked", dc->hal_linked); + mif_dt_read_bool(np, "dit_use_recycling", dc->use_page_recycling_rx); + + mif_dt_read_bool(np, "dit_hal_support", dc->hal_support); + if (dc->hal_support) { + mif_dt_read_bool(np, "dit_hal_enqueue_rx", dc->hal_enqueue_rx); + if (dc->hal_enqueue_rx) + dc->stop_enqueue[DIT_DIR_RX] = true; + } + mif_dt_read_u32(np, "dit_rx_extra_desc_ring_len", dc->rx_extra_desc_ring_len); mif_dt_read_u32(np, "dit_irq_affinity", dc->irq_affinity); + dc->irq_affinity_tx = dc->irq_affinity; return 0; } @@ -2321,36 +2567,37 @@ int dit_create(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - struct resource *res; +#if IS_ENABLED(CONFIG_EXYNOS_ITMON) + struct notifier_block *itmon_nb = NULL; +#endif int ret; if (!np) { mif_err("of_node is null\n"); - return -EINVAL; + ret = -EINVAL; + goto error; } dc = devm_kzalloc(dev, sizeof(struct dit_ctrl_t), GFP_KERNEL); if (!dc) { mif_err("dit ctrl alloc failed\n"); - return -ENOMEM; + ret = -ENOMEM; + goto error; } dc->dev = dev; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dit"); - dc->register_base = devm_ioremap_resource(dev, res); - if (!dc->register_base) { + dc->register_base = devm_platform_ioremap_resource_byname(pdev, "dit"); + if (IS_ERR_OR_NULL(dc->register_base)) { mif_err("register devm_ioremap error\n"); ret = -EFAULT; goto error; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sysreg"); - dc->sharability_base = devm_ioremap_resource(dev, res); - if (!dc->sharability_base) { - mif_err("sharability devm_ioremap error\n"); - ret = -EFAULT; - goto error; + dc->sharability_base = devm_platform_ioremap_resource_byname(pdev, "sysreg"); + if (IS_ERR_OR_NULL(dc->sharability_base)) { + mif_err("sharability devm_ioremap error. use dma map.\n"); + dc->use_dma_map = true; } ret = dit_read_dt(np); @@ -2359,6 +2606,14 @@ int dit_create(struct platform_device *pdev) goto error; } + dit_set_hw_specific(); + + ret = dit_ver_create(dc); + if (ret) { + mif_err("dit versioning failed\n"); + goto error; + } + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); ret = dit_register_irq(pdev); @@ -2370,7 +2625,6 @@ int dit_create(struct platform_device *pdev) spin_lock_init(&dc->src_lock); INIT_LIST_HEAD(&dc->reg_value_q); atomic_set(&dc->init_running, 0); - atomic_set(&dc->stop_napi_poll, 0); dit_set_irq_affinity(dc->irq_affinity); dev_set_drvdata(dev, dc); @@ -2386,29 +2640,44 @@ int dit_create(struct platform_device *pdev) exynos_update_ip_idle_status(dc->idle_ip_index, DIT_IDLE_IP_IDLE); #endif +#if IS_ENABLED(CONFIG_EXYNOS_ITMON) + itmon_nb = devm_kzalloc(dev, sizeof(struct notifier_block), GFP_KERNEL); + if (!itmon_nb) { + mif_err("itmon notifier block alloc failed\n"); + goto error; + } + + itmon_nb->notifier_call = itmon_notifier_callback; + itmon_notifier_chain_register(itmon_nb); +#endif + ret = sysfs_create_groups(&dev->kobj, dit_groups); if (ret != 0) { mif_err("sysfs_create_group() error %d\n", ret); goto error; } - dit_hal_create(dc); + ret = dit_hal_create(dc); if (ret) { mif_err("dit hal create failed\n"); goto error; } - mif_info("dit created. hw_ver:0x%08X, tx:%d, rx:%d, clat:%d, hal:%d, ext_len:%d, irq:%d\n", - dc->hw_version, dc->use_tx, dc->use_rx, dc->use_clat, dc->hal_linked, - dc->rx_extra_desc_ring_len, dc->irq_affinity); + if (dc->use_page_recycling_rx) + dc->page_recycling_skb_padding = NET_SKB_PAD + NET_IP_ALIGN; + + mif_info("dit created. hw_ver:0x%08X tx:%d rx:%d clat:%d hal:%d ext:%d irq:%d pg_r:%d\n", + dc->hw_version, dc->use_dir[DIT_DIR_TX], dc->use_dir[DIT_DIR_RX], dc->use_clat, + dc->hal_support, dc->rx_extra_desc_ring_len, dc->irq_affinity, + dc->use_page_recycling_rx); return 0; error: - if (dc->sharability_base) + if (!IS_ERR_OR_NULL(dc->sharability_base)) devm_iounmap(dev, dc->sharability_base); - if (dc->register_base) + if (!IS_ERR_OR_NULL(dc->register_base)) devm_iounmap(dev, dc->register_base); if (dc) { @@ -2416,6 +2685,7 @@ int dit_create(struct platform_device *pdev) dc = NULL; } + panic("DIT driver probe failed\n"); return ret; } @@ -2449,23 +2719,17 @@ static int dit_suspend(struct device *dev) static int dit_resume(struct device *dev) { struct dit_ctrl_t *dc = dev_get_drvdata(dev); - unsigned int dir; int ret; - if (unlikely(!dc)) { - mif_err_limited("dc is null\n"); - return -EPERM; - } - - if (unlikely(!dc->ld)) { - mif_err_limited("dc->ld is null\n"); - return -EPERM; - } + if (unlikely(!dc) || unlikely(!dc->ld)) + return 0; dit_set_irq_affinity(dc->irq_affinity); ret = dit_init(NULL, DIT_INIT_NORMAL, DIT_STORE_RESTORE); if (ret) { + unsigned int dir; + mif_err("init failed ret:%d\n", ret); for (dir = 0; dir < DIT_DIR_MAX; dir++) { if (dit_is_busy(dir)) diff --git a/drivers/soc/google/cpif/dit/dit_2_1_0.c b/drivers/soc/google/cpif/dit/dit_2_1_0.c new file mode 100644 index 000000000000..4979106cfe18 --- /dev/null +++ b/drivers/soc/google/cpif/dit/dit_2_1_0.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS DIT(Direct IP Translator) Driver support + * + */ + +#include "dit_common.h" +#include "dit_hal.h" + +static struct dit_ctrl_t *dc; + +static int dit_set_desc_filter_bypass(enum dit_direction dir, struct dit_src_desc *src_desc, + u8 *src, bool *is_upstream_pkt) +{ + struct net_device *upstream_netdev; + bool bypass = true; + u8 mask = 0; + + /* + * LRO start/end bit can be used for filter bypass + * 1/1: filtered + * 0/0: filter bypass + * dit does not support checksum yet + */ + cpif_set_bit(mask, DIT_DESC_C_END); + cpif_set_bit(mask, DIT_DESC_C_START); + + if (dir != DIT_DIR_RX) + goto out; + + /* + * check ipv6 for clat. + * port table does not have entries for tun device or ipv6. + * every ipv6 packets from any rmnet can see port table. + */ + if ((src[0] & 0xF0) == 0x60) { + bypass = false; + goto out; + } + + /* check upstream netdev */ + upstream_netdev = dit_hal_get_dst_netdev(DIT_DST_DESC_RING_0); + if (upstream_netdev) { + struct io_device *iod = link_get_iod_with_channel(dc->ld, src_desc->ch_id); + + if (iod && iod->ndev == upstream_netdev) { + *is_upstream_pkt = true; + bypass = false; + goto out; + } + } + +out: +#if defined(DIT_DEBUG_LOW) + if (dc->force_bypass == 1) + bypass = true; + else if (dc->force_bypass == 2) + bypass = false; +#endif + + if (bypass) + src_desc->control &= ~mask; + else + src_desc->control |= mask; + + return 0; +} + +static void __dit_set_interrupt(void) +{ + static int irq_pending_bit[] = { + RX_DST0_INT_PENDING_BIT, RX_DST1_INT_PENDING_BIT, + RX_DST2_INT_PENDING_BIT, TX_DST0_INT_PENDING_BIT, + ERR_INT_PENDING_BIT}; + static char const *irq_name[] = { + "DIT-RxDst0", "DIT-RxDst1", + "DIT-RxDst2", "DIT-Tx", + "DIT-Err"}; + + dc->irq_pending_bit = irq_pending_bit; + dc->irq_name = irq_name; + dc->irq_len = ARRAY_SIZE(irq_pending_bit); +} + +int dit_ver_create(struct dit_ctrl_t *dc_ptr) +{ + if (unlikely(!dc_ptr)) + return -EPERM; + + dc = dc_ptr; + + __dit_set_interrupt(); + + dc->set_desc_filter_bypass = dit_set_desc_filter_bypass; + + return 0; +} + diff --git a/drivers/soc/google/cpif/dit/dit_2_1_0.h b/drivers/soc/google/cpif/dit/dit_2_1_0.h new file mode 100644 index 000000000000..32775012ebf8 --- /dev/null +++ b/drivers/soc/google/cpif/dit/dit_2_1_0.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __DIT_2_1_0_H__ +#define __DIT_2_1_0_H__ + +#define DIT_REG_CLK_GT_OFF 0x0004 /* 20 bit */ +#define DIT_REG_DMA_INIT_DATA 0x0008 /* 28 bit */ + +/* 0:16beat, 1:8beat, 2:4beat, 3:2beat, 4:1beat */ +#define DIT_REG_TX_DESC_CTRL_SRC 0x000C /* 3 bit */ +#define DIT_REG_TX_DESC_CTRL_DST 0x0010 /* 3 bit */ +#define DIT_REG_TX_HEAD_CTRL 0x0014 /* 3 bit */ +#define DIT_REG_TX_MOD_HD_CTRL 0x0018 /* 3 bit */ +#define DIT_REG_TX_PKT_CTRL 0x001C /* 3 bit */ +#define DIT_REG_TX_CHKSUM_CTRL 0x0020 /* 3 bit */ + +#define DIT_REG_RX_DESC_CTRL_SRC 0x0024 /* 3 bit */ +#define DIT_REG_RX_DESC_CTRL_DST 0x0028 /* 3 bit */ +#define DIT_REG_RX_HEAD_CTRL 0x002C /* 3 bit */ +#define DIT_REG_RX_MOD_HD_CTRL 0x0030 /* 3 bit */ +#define DIT_REG_RX_PKT_CTRL 0x0034 /* 3 bit */ +#define DIT_REG_RX_CHKSUM_CTRL 0x0038 /* 3 bit */ + +#define DIT_REG_DMA_CHKSUM_OFF 0x003C /* 2 bit */ + +/* start address for Tx desc */ +#define DIT_REG_TX_RING_START_ADDR_0_SRC 0x0044 +#define DIT_REG_TX_RING_START_ADDR_1_SRC 0x0048 +#define DIT_REG_TX_RING_START_ADDR_0_DST0 0x004C +#define DIT_REG_TX_RING_START_ADDR_1_DST0 0x0050 +#define DIT_REG_TX_RING_START_ADDR_0_DST1 0x0054 +#define DIT_REG_TX_RING_START_ADDR_1_DST1 0x0058 +#define DIT_REG_TX_RING_START_ADDR_0_DST2 0x005C +#define DIT_REG_TX_RING_START_ADDR_1_DST2 0x0060 + +/* start address for Rx desc */ +#define DIT_REG_RX_RING_START_ADDR_0_SRC 0x0064 +#define DIT_REG_RX_RING_START_ADDR_1_SRC 0x0068 +#define DIT_REG_RX_RING_START_ADDR_0_DST0 0x006C +#define DIT_REG_RX_RING_START_ADDR_1_DST0 0x0070 +#define DIT_REG_RX_RING_START_ADDR_0_DST1 0x0074 +#define DIT_REG_RX_RING_START_ADDR_1_DST1 0x0078 +#define DIT_REG_RX_RING_START_ADDR_0_DST2 0x007C +#define DIT_REG_RX_RING_START_ADDR_1_DST2 0x0080 + +#define DIT_REG_INT_ENABLE 0x0084 +#define DIT_REG_INT_MASK 0x0088 +#define DIT_REG_INT_PENDING 0x008C +#define DIT_REG_STATUS 0x0090 + +/* address for Tx desc */ +#define DIT_REG_NAT_TX_DESC_ADDR_0_SRC 0x4000 /* 32 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_1_SRC 0x4004 /* 4 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_EN_SRC 0x4008 /* 1 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST0 0x4018 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST0 0x401C +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST1 0x4020 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST1 0x4024 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST2 0x4028 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST2 0x402C + +/* address for Rx desc */ +#define DIT_REG_NAT_RX_DESC_ADDR_0_SRC 0x4030 /* 32 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_1_SRC 0x4034 /* 4 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_EN_SRC 0x4038 /* 1 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST0 0x4048 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST0 0x404C +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST1 0x4050 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST1 0x4054 +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST2 0x4058 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST2 0x405C + +struct dit_src_desc { + u64 src_addr:36, + _reserved_0:12, + /* the below 16 bits are "private info" on the document */ + ch_id:8, + pre_csum:1, /* checksum successful from pktproc */ + udp_csum_zero:1, /* reset udp checksum 0 after NAT */ + _reserved_2:6; + u64 length:16, + _reserved_1:32, + control:8, + status:8; +} __packed; + +/* DIT_INT_PENDING */ +enum dit_int_pending_bits { + TX_DST0_INT_PENDING_BIT = 0, + TX_DST1_INT_PENDING_BIT, + TX_DST2_INT_PENDING_BIT, + RX_DST0_INT_PENDING_BIT = 3, + RX_DST1_INT_PENDING_BIT, + RX_DST2_INT_PENDING_BIT, + ERR_INT_PENDING_BIT = 14, +}; + +#define DIT_TX_INT_PENDING_MASK \ + (BIT(TX_DST0_INT_PENDING_BIT) | BIT(TX_DST1_INT_PENDING_BIT) | \ + BIT(TX_DST2_INT_PENDING_BIT) | BIT(ERR_INT_PENDING_BIT)) + +#define DIT_RX_INT_PENDING_MASK \ + (BIT(RX_DST0_INT_PENDING_BIT) | BIT(RX_DST1_INT_PENDING_BIT) | \ + BIT(RX_DST2_INT_PENDING_BIT) | BIT(ERR_INT_PENDING_BIT)) + +enum dit_int_enable_bits { + TX_DST0_INT_ENABLE_BIT = 0, + TX_DST1_INT_ENABLE_BIT, + TX_DST2_INT_ENABLE_BIT, + RX_DST0_INT_ENABLE_BIT = 3, + RX_DST1_INT_ENABLE_BIT, + RX_DST2_INT_ENABLE_BIT, + ERR_INT_ENABLE_BIT = 14, +}; + +#define DIT_INT_ENABLE_MASK \ + (BIT(TX_DST0_INT_ENABLE_BIT) | BIT(TX_DST1_INT_ENABLE_BIT) | \ + BIT(TX_DST2_INT_ENABLE_BIT) | \ + BIT(RX_DST0_INT_ENABLE_BIT) | BIT(RX_DST1_INT_ENABLE_BIT) | \ + BIT(RX_DST2_INT_ENABLE_BIT) | \ + BIT(ERR_INT_ENABLE_BIT)) + +#define DIT_INT_MASK_MASK DIT_INT_ENABLE_MASK + +#endif /* __DIT_2_1_0_H__ */ diff --git a/drivers/soc/google/cpif/dit/dit_2_2_0.c b/drivers/soc/google/cpif/dit/dit_2_2_0.c new file mode 100644 index 000000000000..886860dc3b10 --- /dev/null +++ b/drivers/soc/google/cpif/dit/dit_2_2_0.c @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS DIT(Direct IP Translator) Driver support + * + */ + +#include "dit_common.h" +#include "dit_hal.h" + +static struct dit_ctrl_t *dc; +static int upstream_ch = -1; + +static int dit_get_reg_version(u32 *version) +{ + *version = READ_REG_VALUE(dc, DIT_REG_VERSION); + + return 0; +} + +static void dit_set_reg_nat_interface(int ch) +{ + unsigned int part = 0, value = 0; + unsigned int i, offset; + unsigned long flags; + + if (ch >= 0) { + part = (ch >> 5) & 0x7; + value = 1 << (ch & 0x1F); + } + + spin_lock_irqsave(&dc->src_lock, flags); + for (i = 0; i < DIT_REG_NAT_INTERFACE_NUM_MAX; i++) { + offset = i * DIT_REG_NAT_INTERFACE_NUM_INTERVAL; + dit_enqueue_reg_value_with_ext_lock((i == part ? value : 0), + DIT_REG_NAT_INTERFACE_NUM + offset); + } + spin_unlock_irqrestore(&dc->src_lock, flags); +} + +static void dit_set_reg_upstream_internal(struct io_device *iod, void *args) +{ + struct net_device *netdev = (struct net_device *)args; + + if (iod->ndev == netdev) { + upstream_ch = (int)iod->ch; + dit_set_reg_nat_interface(iod->ch); + } +} + +static int dit_set_reg_upstream(struct net_device *netdev) +{ + if (!netdev) { + dit_set_reg_nat_interface(-1); + upstream_ch = -1; + } else { + if (unlikely(!dc->ld)) + return -EINVAL; + + iodevs_for_each(dc->ld->msd, dit_set_reg_upstream_internal, netdev); + } + + return 0; +} + +static int dit_set_desc_filter_bypass(enum dit_direction dir, struct dit_src_desc *src_desc, + u8 *src, bool *is_upstream_pkt) +{ + bool bypass = false; + u8 mask = 0; + + /* + * LRO start/end bit can be used for filter bypass + * 1/1: filtered + * 0/0: filter bypass + * dit does not support checksum yet + */ + cpif_set_bit(mask, DIT_DESC_C_END); + cpif_set_bit(mask, DIT_DESC_C_START); + + if (dir != DIT_DIR_RX) { + bypass = true; + goto out; + } + + /* ToDo: not need if HW supports UDP zero checksum. + * check if the packet will be filtered by DIT_REG_NAT_INTERFACE_NUM. + */ + if (upstream_ch >= 0 && src_desc->ch_id == upstream_ch) + *is_upstream_pkt = true; + +out: +#if defined(DIT_DEBUG_LOW) + if (dc->force_bypass == 1) + bypass = true; +#endif + + if (bypass) { + src_desc->control &= ~mask; + } else { + src_desc->control |= mask; + src_desc->interface = src_desc->ch_id; + } + + return 0; +} + +static int dit_set_src_desc_tail(enum dit_direction dir, struct dit_desc_info *desc_info, + unsigned int tail) +{ + phys_addr_t p_desc; + u32 offset_lo = 0, offset_hi = 0, offset_en = 0; + + p_desc = desc_info->src_desc_ring_daddr + (sizeof(struct dit_src_desc) * tail); + if (dir == DIT_DIR_TX) { + offset_lo = DIT_REG_TX_SRC_A_TAIL_ADDR_0_TEMP; + offset_hi = DIT_REG_TX_SRC_A_TAIL_ADDR_1_TEMP; + offset_en = DIT_REG_TX_SRC_A_TAIL_VALID; + } else { + offset_lo = DIT_REG_RX_SRC_A_TAIL_ADDR_0_TEMP; + offset_hi = DIT_REG_RX_SRC_A_TAIL_ADDR_1_TEMP; + offset_en = DIT_REG_RX_SRC_A_TAIL_VALID; + } + + WRITE_REG_PADDR_LO(dc, p_desc, offset_lo); + WRITE_REG_PADDR_HI(dc, p_desc, offset_hi); + WRITE_REG_VALUE(dc, 0x1, offset_en); + + return 0; +} + +static int dit_do_init_desc(enum dit_direction dir) +{ + struct dit_desc_info *desc_info; + phys_addr_t p_desc; + + /* dst01-dst03 is not used but hw checks the registers */ + u32 tx_offset_lo[] = { + DIT_REG_TX_RING_START_ADDR_0_DST01, DIT_REG_TX_RING_START_ADDR_0_DST02, + DIT_REG_TX_RING_START_ADDR_0_DST03, + DIT_REG_NAT_TX_DESC_ADDR_0_DST01, DIT_REG_NAT_TX_DESC_ADDR_0_DST02, + DIT_REG_NAT_TX_DESC_ADDR_0_DST03}; + u32 tx_offset_hi[] = { + DIT_REG_TX_RING_START_ADDR_1_DST01, DIT_REG_TX_RING_START_ADDR_1_DST02, + DIT_REG_TX_RING_START_ADDR_1_DST03, + DIT_REG_NAT_TX_DESC_ADDR_1_DST01, DIT_REG_NAT_TX_DESC_ADDR_1_DST02, + DIT_REG_NAT_TX_DESC_ADDR_1_DST03}; + u32 rx_offset_lo[] = { + DIT_REG_RX_RING_START_ADDR_0_DST01, DIT_REG_RX_RING_START_ADDR_0_DST02, + DIT_REG_RX_RING_START_ADDR_0_DST03, + DIT_REG_NAT_RX_DESC_ADDR_0_DST01, DIT_REG_NAT_RX_DESC_ADDR_0_DST02, + DIT_REG_NAT_RX_DESC_ADDR_0_DST03}; + u32 rx_offset_hi[] = { + DIT_REG_RX_RING_START_ADDR_1_DST01, DIT_REG_RX_RING_START_ADDR_1_DST02, + DIT_REG_RX_RING_START_ADDR_1_DST03, + DIT_REG_NAT_RX_DESC_ADDR_1_DST01, DIT_REG_NAT_RX_DESC_ADDR_1_DST02, + DIT_REG_NAT_RX_DESC_ADDR_1_DST03}; + + u32 *offset_lo; + u32 *offset_hi; + unsigned int offset_len; + unsigned int i; + + if (dir == DIT_DIR_TX) { + offset_lo = tx_offset_lo; + offset_hi = tx_offset_hi; + offset_len = ARRAY_SIZE(tx_offset_lo); + } else { + offset_lo = rx_offset_lo; + offset_hi = rx_offset_hi; + offset_len = ARRAY_SIZE(rx_offset_lo); + } + + desc_info = &dc->desc_info[dir]; + p_desc = desc_info->dst_desc_ring_daddr[DIT_DST_DESC_RING_0]; + + for (i = 0; i < offset_len; i++) { + WRITE_REG_PADDR_LO(dc, p_desc, offset_lo[i]); + WRITE_REG_PADDR_HI(dc, p_desc, offset_hi[i]); + } + + return 0; +} + +static int dit_do_init_hw(void) +{ + WRITE_REG_VALUE(dc, BIT(RX_TTLDEC_EN_BIT), DIT_REG_NAT_TTLDEC_EN); + WRITE_REG_VALUE(dc, BIT(TX_DST_DESC_RESET_BIT), DIT_REG_DST_DESC_RESET); + WRITE_REG_VALUE(dc, BIT(RX_DST_DESC_RESET_BIT), DIT_REG_DST_DESC_RESET); + dit_set_reg_upstream(NULL); + + return 0; +} + +static void __dit_set_interrupt(void) +{ + static int irq_pending_bit[] = { + RX_DST00_INT_PENDING_BIT, RX_DST1_INT_PENDING_BIT, + RX_DST2_INT_PENDING_BIT, TX_DST00_INT_PENDING_BIT}; + static char const *irq_name[] = { + "DIT-RxDst00", "DIT-RxDst1", + "DIT-RxDst2", "DIT-Tx"}; + + dc->irq_pending_bit = irq_pending_bit; + dc->irq_name = irq_name; + dc->irq_len = ARRAY_SIZE(irq_pending_bit); +} + +int dit_ver_create(struct dit_ctrl_t *dc_ptr) +{ + if (unlikely(!dc_ptr)) + return -EPERM; + + dc = dc_ptr; + + __dit_set_interrupt(); + + dc->get_reg_version = dit_get_reg_version; + dc->set_reg_upstream = dit_set_reg_upstream; + dc->set_desc_filter_bypass = dit_set_desc_filter_bypass; + dc->set_src_desc_tail = dit_set_src_desc_tail; + dc->do_init_desc = dit_do_init_desc; + dc->do_init_hw = dit_do_init_hw; + + return 0; +} + diff --git a/drivers/soc/google/cpif/dit/dit_2_2_0.h b/drivers/soc/google/cpif/dit/dit_2_2_0.h new file mode 100644 index 000000000000..8c4e5242a958 --- /dev/null +++ b/drivers/soc/google/cpif/dit/dit_2_2_0.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __DIT_2_2_0_H__ +#define __DIT_2_2_0_H__ + +#define DIT_REG_CLK_GT_OFF 0x0100 /* 20 bit */ +#define DIT_REG_DMA_INIT_DATA 0x0104 /* 28 bit */ + +/* 0:16beat, 1:8beat, 2:4beat, 3:2beat, 4:1beat */ +#define DIT_REG_TX_DESC_CTRL_SRC 0x0108 /* 3 bit */ +#define DIT_REG_TX_DESC_CTRL_DST 0x010C /* 3 bit */ +#define DIT_REG_TX_HEAD_CTRL 0x0110 /* 3 bit */ +#define DIT_REG_TX_MOD_HD_CTRL 0x0114 /* 3 bit */ +#define DIT_REG_TX_PKT_CTRL 0x0118 /* 3 bit */ +#define DIT_REG_TX_CHKSUM_CTRL 0x011C /* 3 bit */ + +#define DIT_REG_RX_DESC_CTRL_SRC 0x0120 /* 3 bit */ +#define DIT_REG_RX_DESC_CTRL_DST 0x0124 /* 3 bit */ +#define DIT_REG_RX_HEAD_CTRL 0x0128 /* 3 bit */ +#define DIT_REG_RX_MOD_HD_CTRL 0x012C /* 3 bit */ +#define DIT_REG_RX_PKT_CTRL 0x0130 /* 3 bit */ +#define DIT_REG_RX_CHKSUM_CTRL 0x0134 /* 3 bit */ + +#define DIT_REG_DMA_CHKSUM_OFF 0x0138 /* 2 bit */ +#define DIT_REG_INT_ENABLE 0x0140 +#define DIT_REG_INT_MASK 0x0144 +#define DIT_REG_INT_PENDING 0x0148 +#define DIT_REG_STATUS 0x014C + +/* start address for Tx desc */ +#define DIT_REG_TX_RING_START_ADDR_0_SRC_A 0x0200 +#define DIT_REG_TX_RING_START_ADDR_1_SRC_A 0x0204 +#define DIT_REG_TX_RING_START_ADDR_0_SRC DIT_REG_TX_RING_START_ADDR_0_SRC_A +#define DIT_REG_TX_RING_START_ADDR_1_SRC DIT_REG_TX_RING_START_ADDR_1_SRC_A +#define DIT_REG_TX_RING_START_ADDR_0_DST00 0x0218 +#define DIT_REG_TX_RING_START_ADDR_1_DST00 0x021C +#define DIT_REG_TX_RING_START_ADDR_0_DST0 DIT_REG_TX_RING_START_ADDR_0_DST00 +#define DIT_REG_TX_RING_START_ADDR_1_DST0 DIT_REG_TX_RING_START_ADDR_1_DST00 +#define DIT_REG_TX_RING_START_ADDR_0_DST1 0x0220 +#define DIT_REG_TX_RING_START_ADDR_1_DST1 0x0224 +#define DIT_REG_TX_RING_START_ADDR_0_DST2 0x0228 +#define DIT_REG_TX_RING_START_ADDR_1_DST2 0x022C +#define DIT_REG_TX_RING_START_ADDR_0_DST01 0x0230 +#define DIT_REG_TX_RING_START_ADDR_1_DST01 0x0234 +#define DIT_REG_TX_RING_START_ADDR_0_DST02 0x0238 +#define DIT_REG_TX_RING_START_ADDR_1_DST02 0x023C +#define DIT_REG_TX_RING_START_ADDR_0_DST03 0x0240 +#define DIT_REG_TX_RING_START_ADDR_1_DST03 0x0244 + +/* start address for Rx desc */ +#define DIT_REG_RX_RING_START_ADDR_0_SRC_A 0x0248 +#define DIT_REG_RX_RING_START_ADDR_1_SRC_A 0x024C +#define DIT_REG_RX_RING_START_ADDR_0_SRC DIT_REG_RX_RING_START_ADDR_0_SRC_A +#define DIT_REG_RX_RING_START_ADDR_1_SRC DIT_REG_RX_RING_START_ADDR_1_SRC_A +#define DIT_REG_RX_RING_START_ADDR_0_DST00 0x0260 +#define DIT_REG_RX_RING_START_ADDR_1_DST00 0x0264 +#define DIT_REG_RX_RING_START_ADDR_0_DST0 DIT_REG_RX_RING_START_ADDR_0_DST00 +#define DIT_REG_RX_RING_START_ADDR_1_DST0 DIT_REG_RX_RING_START_ADDR_1_DST00 +#define DIT_REG_RX_RING_START_ADDR_0_DST1 0x0268 +#define DIT_REG_RX_RING_START_ADDR_1_DST1 0x026C +#define DIT_REG_RX_RING_START_ADDR_0_DST2 0x0270 +#define DIT_REG_RX_RING_START_ADDR_1_DST2 0x0274 +#define DIT_REG_RX_RING_START_ADDR_0_DST01 0x0278 +#define DIT_REG_RX_RING_START_ADDR_1_DST01 0x027C +#define DIT_REG_RX_RING_START_ADDR_0_DST02 0x0280 +#define DIT_REG_RX_RING_START_ADDR_1_DST02 0x0284 +#define DIT_REG_RX_RING_START_ADDR_0_DST03 0x0288 +#define DIT_REG_RX_RING_START_ADDR_1_DST03 0x028C + +/* tail for 2.2.1 */ +#define DIT_REG_TX_SRC_A_TAIL_ADDR_0_TEMP 0x0290 +#define DIT_REG_TX_SRC_A_TAIL_ADDR_1_TEMP 0x0294 +#define DIT_REG_RX_SRC_A_TAIL_ADDR_0_TEMP 0x0308 +#define DIT_REG_RX_SRC_A_TAIL_ADDR_1_TEMP 0x030C +#define DIT_REG_TX_SRC_A_TAIL_VALID 0x0320 +#define DIT_REG_RX_SRC_A_TAIL_VALID 0x032C +#define DIT_REG_DST_DESC_RESET 0x0338 + +/* address for Tx desc */ +#define DIT_REG_NAT_TX_DESC_ADDR_0_SRC_A 0x4000 /* 32 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_1_SRC_A 0x4004 /* 4 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_EN_SRC_A 0x4008 /* 1 bit */ +#define DIT_REG_NAT_TX_DESC_ADDR_0_SRC DIT_REG_NAT_TX_DESC_ADDR_0_SRC_A +#define DIT_REG_NAT_TX_DESC_ADDR_1_SRC DIT_REG_NAT_TX_DESC_ADDR_1_SRC_A +#define DIT_REG_NAT_TX_DESC_ADDR_EN_SRC DIT_REG_NAT_TX_DESC_ADDR_EN_SRC_A +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST00 0x4024 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST00 0x4028 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST0 DIT_REG_NAT_TX_DESC_ADDR_0_DST00 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST0 DIT_REG_NAT_TX_DESC_ADDR_1_DST00 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST1 0x402C +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST1 0x4030 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST2 0x4034 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST2 0x4038 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST01 0x403C +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST01 0x4040 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST02 0x4044 +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST02 0x4048 +#define DIT_REG_NAT_TX_DESC_ADDR_0_DST03 0x404C +#define DIT_REG_NAT_TX_DESC_ADDR_1_DST03 0x4050 + +/* address for Rx desc */ +#define DIT_REG_NAT_RX_DESC_ADDR_0_SRC_A 0x4054 /* 32 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_1_SRC_A 0x4058 /* 4 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_EN_SRC_A 0x405C /* 1 bit */ +#define DIT_REG_NAT_RX_DESC_ADDR_0_SRC DIT_REG_NAT_RX_DESC_ADDR_0_SRC_A +#define DIT_REG_NAT_RX_DESC_ADDR_1_SRC DIT_REG_NAT_RX_DESC_ADDR_1_SRC_A +#define DIT_REG_NAT_RX_DESC_ADDR_EN_SRC DIT_REG_NAT_RX_DESC_ADDR_EN_SRC_A +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST00 0x4078 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST00 0x407C +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST0 DIT_REG_NAT_RX_DESC_ADDR_0_DST00 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST0 DIT_REG_NAT_RX_DESC_ADDR_1_DST00 +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST1 0x4080 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST1 0x4084 +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST2 0x4088 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST2 0x408C +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST01 0x4090 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST01 0x4094 +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST02 0x4098 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST02 0x409C +#define DIT_REG_NAT_RX_DESC_ADDR_0_DST03 0x40A0 +#define DIT_REG_NAT_RX_DESC_ADDR_1_DST03 0x40A4 + +#define DIT_REG_NAT_TTLDEC_EN 0x4150 + +/* total: DIT_REG_NAT_INTERFACE_NUM_MAX, interval: DIT_REG_NAT_INTERFACE_NUM_INTERVAL */ +#define DIT_REG_NAT_INTERFACE_NUM 0x4200 + +#define DIT_REG_VERSION 0x9000 + +#define DIT_REG_NAT_INTERFACE_NUM_MAX (8) +#define DIT_REG_NAT_INTERFACE_NUM_INTERVAL (4) + +enum dit_nat_ttldec_en_bits { + TX_TTLDEC_EN_BIT, + RX_TTLDEC_EN_BIT, +}; + +enum dit_dst_desc_reset_bits { + TX_DST_DESC_RESET_BIT, + RX_DST_DESC_RESET_BIT, +}; + +struct dit_src_desc { + u64 src_addr:36, + _reserved_0:12, + /* the below 16 bits are "private info" on the document */ + ch_id:8, + pre_csum:1, /* checksum successful from pktproc */ + udp_csum_zero:1, /* reset udp checksum 0 after NAT */ + _reserved_2:6; + u64 length:16, + interface:8, + _reserved_1:24, + control:8, + status:8; +} __packed; + +/* DIT_INT_PENDING */ +enum dit_int_pending_bits { + TX_DST00_INT_PENDING_BIT = 3, + TX_DST0_INT_PENDING_BIT = TX_DST00_INT_PENDING_BIT, + TX_DST1_INT_PENDING_BIT = 7, + TX_DST2_INT_PENDING_BIT, + RX_DST00_INT_PENDING_BIT = 19, + RX_DST0_INT_PENDING_BIT = RX_DST00_INT_PENDING_BIT, + RX_DST1_INT_PENDING_BIT = 23, + RX_DST2_INT_PENDING_BIT, + RSVD0_INT_PENDING_BIT = 30, + ERR_INT_PENDING_BIT = RSVD0_INT_PENDING_BIT, /* No ERR interrupt */ +}; + +#define DIT_TX_INT_PENDING_MASK \ + (BIT(TX_DST00_INT_PENDING_BIT) | BIT(TX_DST1_INT_PENDING_BIT) | \ + BIT(TX_DST2_INT_PENDING_BIT)) + +#define DIT_RX_INT_PENDING_MASK \ + (BIT(RX_DST00_INT_PENDING_BIT) | BIT(RX_DST1_INT_PENDING_BIT) | \ + BIT(RX_DST2_INT_PENDING_BIT)) + +enum dit_int_enable_bits { + TX_DST00_INT_ENABLE_BIT = 3, + TX_DST1_INT_ENABLE_BIT = 7, + TX_DST2_INT_ENABLE_BIT, + RX_DST00_INT_ENABLE_BIT = 19, + RX_DST1_INT_ENABLE_BIT = 23, + RX_DST2_INT_ENABLE_BIT, +}; + +#define DIT_INT_ENABLE_MASK \ + (BIT(TX_DST00_INT_ENABLE_BIT) | BIT(TX_DST1_INT_ENABLE_BIT) | \ + BIT(TX_DST2_INT_ENABLE_BIT) | \ + BIT(RX_DST00_INT_ENABLE_BIT) | BIT(RX_DST1_INT_ENABLE_BIT) | \ + BIT(RX_DST2_INT_ENABLE_BIT)) + +#define DIT_INT_MASK_MASK (0xFFFFFFFF) + +#endif /* __DIT_2_2_0_H__ */ diff --git a/drivers/soc/google/cpif/dit/dit_common.h b/drivers/soc/google/cpif/dit/dit_common.h new file mode 100644 index 000000000000..fdcb82a46921 --- /dev/null +++ b/drivers/soc/google/cpif/dit/dit_common.h @@ -0,0 +1,340 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS DIT(Direct IP Translator) Driver support + * + */ + +#ifndef __DIT_COMMON_H__ +#define __DIT_COMMON_H__ + +#ifndef DIT_DEBUG +#define DIT_DEBUG +#endif + +#ifdef DIT_DEBUG +#define DIT_DEBUG_LOW +#endif + +#include "dit.h" +#include "cpif_page.h" + +#define DIT_VERSION(x, y, z) \ + ((((x) & 0xFF) << 24) | (((y) & 0xFF) << 16) | (((z) & 0xFF) << 8)) + +#if defined(CONFIG_EXYNOS_DIT_VERSION) && (DIT_VERSION(2, 2, 0) == CONFIG_EXYNOS_DIT_VERSION) +#include "dit_2_2_0.h" +#else +#include "dit_2_1_0.h" +#endif + +#define DIT_REG_SW_COMMAND 0x0000 + +/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_FILTER_INTERVAL */ +#define DIT_REG_CLAT_TX_FILTER 0x2000 +/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL */ +#define DIT_REG_CLAT_TX_PLAT_PREFIX_0 0x2020 +#define DIT_REG_CLAT_TX_PLAT_PREFIX_1 0x2024 +#define DIT_REG_CLAT_TX_PLAT_PREFIX_2 0x2028 +/* total: DIT_REG_CLAT_ADDR_MAX, interval: DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL */ +#define DIT_REG_CLAT_TX_CLAT_SRC_0 0x2080 +#define DIT_REG_CLAT_TX_CLAT_SRC_1 0x2084 +#define DIT_REG_CLAT_TX_CLAT_SRC_2 0x2088 +#define DIT_REG_CLAT_TX_CLAT_SRC_3 0x208C + +/* total: DIT_REG_NAT_LOCAL_ADDR_MAX, interval: DIT_REG_NAT_LOCAL_INTERVAL */ +#define DIT_REG_NAT_LOCAL_ADDR 0x4100 + +#define DIT_REG_NAT_ZERO_CHK_OFF 0x4144 +#define DIT_REG_NAT_ETHERNET_EN 0x414C + +/* total: DIT_REG_NAT_LOCAL_ADDR_MAX, interval: DIT_REG_ETHERNET_MAC_INTERVAL */ +#define DIT_REG_NAT_ETHERNET_DST_MAC_ADDR_0 0x6000 /* 32 bit */ +#define DIT_REG_NAT_ETHERNET_DST_MAC_ADDR_1 0x6004 /* 16 bit */ +#define DIT_REG_NAT_ETHERNET_SRC_MAC_ADDR_0 0x6008 /* 32 bit */ +#define DIT_REG_NAT_ETHERNET_SRC_MAC_ADDR_1 0x600C /* 16 bit */ +#define DIT_REG_NAT_ETHERNET_TYPE 0x6010 /* 16 bit */ + +#define DIT_REG_NAT_TX_PORT_INIT_START 0x6210 +#define DIT_REG_NAT_TX_PORT_INIT_DONE 0x6214 +#define DIT_REG_NAT_RX_PORT_INIT_START 0x6228 +#define DIT_REG_NAT_RX_PORT_INIT_DONE 0x622C + +/* total: DIT_REG_NAT_LOCAL_PORT_MAX, interval: DIT_REG_NAT_LOCAL_INTERVAL */ +#define DIT_REG_NAT_RX_PORT_TABLE_SLOT 0xC000 + +/* total numbers and intervals */ +#define DIT_REG_NAT_LOCAL_ADDR_MAX (16) +#define DIT_REG_NAT_LOCAL_PORT_MAX (2048) +#define DIT_REG_NAT_LOCAL_INTERVAL (4) +#define DIT_REG_ETHERNET_MAC_INTERVAL (0x20) +#define DIT_REG_CLAT_ADDR_MAX (8) +#define DIT_REG_CLAT_TX_FILTER_INTERVAL (4) +#define DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL (12) +#define DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL (16) + +/* macro for DIT register operation */ +#define WRITE_REG_PADDR_LO(dc, paddr, offset) \ + writel(PADDR_LO(paddr), dc->register_base + offset) +#define WRITE_REG_PADDR_HI(dc, paddr, offset) \ + writel(PADDR_HI(paddr), dc->register_base + offset) +#define WRITE_REG_VALUE(dc, value, offset) \ + writel(value, dc->register_base + offset) +#define READ_REG_VALUE(dc, offset) \ + readl(dc->register_base + offset) +#define WRITE_SHR_VALUE(dc, value) \ + ({ \ + if (!IS_ERR_OR_NULL(dc->sharability_base)) \ + writel(value, dc->sharability_base + dc->sharability_offset); \ + }) +#define BACKUP_REG_VALUE(dc, dst, offset, size) \ + memcpy_fromio(dst, dc->register_base + offset, size) +#define RESTORE_REG_VALUE(dc, src, offset, size) \ + memcpy_toio(dc->register_base + offset, src, size) + +/* macro for DIT function pointer */ +#define DIT_INDIRECT_CALL(dc, f, ...) \ + ({ \ + dc->f ? dc->f(__VA_ARGS__) : -EOPNOTSUPP; \ + }) + +#define DIT_RX_BURST_16BEAT (0) + +enum dit_desc_ring { + DIT_DST_DESC_RING_0, + DIT_DST_DESC_RING_1, + DIT_DST_DESC_RING_2, + DIT_DST_DESC_RING_MAX, + DIT_SRC_DESC_RING = DIT_DST_DESC_RING_MAX, + DIT_DESC_RING_MAX +}; + +enum dit_desc_control_bits { + DIT_DESC_C_RESERVED, /* Reserved */ + DIT_DESC_C_END, /* end packet of LRO */ + DIT_DESC_C_START, /* first packet of LRO */ + DIT_DESC_C_RINGEND, /* End of descriptor */ + DIT_DESC_C_INT, /* Interrupt enabled */ + DIT_DESC_C_CSUM, /* csum enabled */ + DIT_DESC_C_TAIL, /* last buffer */ + DIT_DESC_C_HEAD /* first buffer */ +}; + +#define DIT_SRC_KICK_CONTROL_MASK \ + (BIT(DIT_DESC_C_HEAD) | BIT(DIT_DESC_C_TAIL) | \ + BIT(DIT_DESC_C_INT) | BIT(DIT_DESC_C_RINGEND)) + +enum dit_desc_status_bits { + DIT_DESC_S_DONE, /* DMA done */ + DIT_DESC_S_RESERVED, /* Reserved */ + DIT_DESC_S_TCPCF, /* Failed TCP csum */ + DIT_DESC_S_IPCSF, /* Failed IP csum */ + DIT_DESC_S_IGNR, /* Ignore csum */ + DIT_DESC_S_TCPC, /* TCP/UDP csum done: should be 0 if IGNR */ + DIT_DESC_S_IPCS, /* IP header csum done: should be 0 if IGNR */ + DIT_DESC_S_PFD /* passed packet filter */ +}; + +#define DIT_CHECKSUM_FAILED_STATUS_MASK \ + (BIT(DIT_DESC_S_TCPCF) | BIT(DIT_DESC_S_IPCSF) | BIT(DIT_DESC_S_IGNR)) + +enum dit_sw_command_bits { + DMA_INIT_COMMAND_BIT, + TX_COMMAND_BIT, + RX_COMMAND_BIT, +}; + +enum dit_nat_ethernet_en_bits { + TX_ETHERNET_EN_BIT, + RX_ETHERNET_EN_BIT, +}; + +#define DIT_ALL_INT_PENDING_MASK \ + (DIT_TX_INT_PENDING_MASK | DIT_RX_INT_PENDING_MASK) + +/* DIT_STATUS + * zero means idle + */ +enum dit_status_mask { + TX_STATUS_MASK = 0x0F, + RX_STATUS_MASK = 0xF0, +}; + +enum dit_packet_info_bits { + DIT_PACKET_INFO_UDP_BIT = 6, + DIT_PACKET_INFO_TCP_BIT, + DIT_PACKET_INFO_IPV6_BIT = 10, + DIT_PACKET_INFO_IPV4_BIT, +}; + +struct dit_dst_desc { + u64 dst_addr:36, + packet_info:12, + /* the below 16 bits are "private info" on the document */ + ch_id:8, + pre_csum:1, + udp_csum_zero:1, + _reserved_2:6; + u64 length:16, + org_port:16, + trans_port:16, + control:8, + status:8; +} __packed; + +struct dit_desc_info { + unsigned int src_wp; + unsigned int src_rp; + unsigned int dst_wp[DIT_DST_DESC_RING_MAX]; + unsigned int dst_rp[DIT_DST_DESC_RING_MAX]; + + unsigned int src_desc_ring_len; + struct dit_src_desc *src_desc_ring; + struct sk_buff **src_skb_buf; + u32 buf_size; + + phys_addr_t pktproc_pbase; + u32 pktproc_queue_num; + u32 pktproc_desc_len; + u32 *pktproc_fore_ptr; + + unsigned int dst_desc_ring_len; + struct dit_dst_desc *dst_desc_ring[DIT_DST_DESC_RING_MAX]; + struct sk_buff **dst_skb_buf[DIT_DST_DESC_RING_MAX]; + bool dst_skb_buf_filled[DIT_DST_DESC_RING_MAX]; + + /* use_dma_map */ + dma_addr_t src_desc_ring_daddr; + dma_addr_t dst_desc_ring_daddr[DIT_DST_DESC_RING_MAX]; + dma_addr_t *dst_skb_buf_daddr[DIT_DST_DESC_RING_MAX]; + + /* page pool */ + struct cpif_page_pool *dst_page_pool[DIT_DST_DESC_RING_MAX]; +}; + +struct dit_ctrl_t { + struct device *dev; + struct link_device *ld; + struct net_device *netdev; + struct napi_struct napi; + int *irq_pending_bit; + char const **irq_name; + int *irq_buf; + int irq_len; + int irq_affinity; + int irq_num_tx; + int irq_affinity_tx; + int idle_ip_index; + + void __iomem *register_base; + void __iomem *sharability_base; + u32 sharability_offset; + u32 sharability_value; + bool use_dma_map; + + u32 hw_version; + u32 reg_version; + u32 hw_capabilities; + bool use_dir[DIT_DIR_MAX]; + bool stop_enqueue[DIT_DIR_MAX]; + bool use_clat; + bool hal_support; + bool hal_enqueue_rx; + u32 rx_extra_desc_ring_len; + + struct dit_desc_info desc_info[DIT_DIR_MAX]; + + /* for kicked flag, reg_value_q and init_done */ + spinlock_t src_lock; + bool kicked[DIT_DIR_MAX]; + bool kick_reserved[DIT_DIR_MAX]; + struct list_head reg_value_q; + bool init_done; + bool init_reserved; + + atomic_t init_running; + + bool use_page_recycling_rx; + u32 page_recycling_skb_padding; + +#if defined(DIT_DEBUG_LOW) + int pktgen_ch; + int force_bypass; +#endif + + /* every functions should return int for DIT_INDIRECT_CALL */ + int (*get_reg_version)(u32 *version); + int (*set_reg_upstream)(struct net_device *netdev); + int (*set_desc_filter_bypass)(enum dit_direction dir, struct dit_src_desc *src_desc, + u8 *src, bool *is_upstream_pkt); + int (*set_src_desc_tail)(enum dit_direction dir, struct dit_desc_info *desc_info, + unsigned int tail); + int (*do_init_hw)(void); + int (*do_init_desc)(enum dit_direction dir); +}; + +struct dit_snapshot_t { + char *name; + int head; + int tail; + + u64 packets; + /* cumulative amount */ + u64 total_packets; + u64 clat_packets; + + u32 max_usage; + u32 alloc_skbs; + u32 dma_maps; +}; + +struct dit_reg_value_item { + struct list_head list; + u32 value; + u32 offset; +}; + +struct dit_iface { + u8 upstream_ch; +}; + +enum dit_dump_bits { + DIT_DUMP_SNAPSHOT_BIT, + DIT_DUMP_DESC_BIT, + DIT_DUMP_PORT_TABLE_BIT, + DIT_DUMP_MAX, +}; + +#define DIT_DUMP_ALL \ + (BIT(DIT_DUMP_SNAPSHOT_BIT) | BIT(DIT_DUMP_DESC_BIT) | \ + BIT(DIT_DUMP_PORT_TABLE_BIT)) + +enum dit_idle_ip { + DIT_IDLE_IP_ACTIVE = 0, + DIT_IDLE_IP_IDLE, +}; + +/* + * if there is 1 src desc and it is at the ring_end, + * DIT will reads 3 descs from the ring_end. + * for the safety, add additional 2 descs. + */ +#define DIT_SRC_DESC_RING_LEN_PADDING (2) + +/* prevent zero size alloc */ +#define DIT_DST_DESC_RING_LEN_PADDING (1) + +bool dit_is_kicked_any(void); +int dit_check_dst_ready(enum dit_direction dir, enum dit_desc_ring ring_num); +int dit_enqueue_reg_value_with_ext_lock(u32 value, u32 offset); +int dit_enqueue_reg_value(u32 value, u32 offset); +int dit_read_rx_dst_poll(struct napi_struct *napi, int budget); +int dit_manage_rx_dst_data_buffers(bool fill); +bool dit_is_busy(enum dit_direction dir); + +int dit_ver_create(struct dit_ctrl_t *dc_ptr); + +#endif /* __DIT_COMMON_H__ */ + diff --git a/drivers/soc/google/cpif/dit_hal.c b/drivers/soc/google/cpif/dit/dit_hal.c similarity index 90% rename from drivers/soc/google/cpif/dit_hal.c rename to drivers/soc/google/cpif/dit/dit_hal.c index a8012a7fca44..a6a8e671dcdb 100644 --- a/drivers/soc/google/cpif/dit_hal.c +++ b/drivers/soc/google/cpif/dit/dit_hal.c @@ -60,7 +60,7 @@ static ssize_t dit_hal_read(struct file *filp, char *buf, size_t count, loff_t * spin_unlock_irqrestore(&dhc->event_lock, flags); event.event_num = event_item->event_num; - devm_kfree(dc->dev, event_item); + kvfree(event_item); if (copy_to_user((void __user *)buf, (void *)&event, sizeof(event))) return 0; @@ -76,7 +76,7 @@ static int dit_hal_init(void) struct offload_event_item *event_item; unsigned long flags; - if (!dc->hal_linked) { + if (!dc->hal_support) { mif_err("does not support hal\n"); return -EPERM; } @@ -99,7 +99,7 @@ static int dit_hal_init(void) while (!list_empty(&dhc->event_q)) { event_item = list_first_entry(&dhc->event_q, struct offload_event_item, list); list_del(&event_item->list); - devm_kfree(dc->dev, event_item); + kvfree(event_item); } spin_unlock_irqrestore(&dhc->event_lock, flags); @@ -114,7 +114,7 @@ static int dit_hal_set_event(enum offload_event_num event_num) if (event_num == dhc->last_event_num) return -EEXIST; - event_item = devm_kzalloc(dc->dev, sizeof(struct offload_event_item), GFP_ATOMIC); + event_item = kvzalloc(sizeof(struct offload_event_item), GFP_ATOMIC); if (!event_item) { mif_err("event=%d generation failed\n", event_num); return -ENOMEM; @@ -133,10 +133,13 @@ static int dit_hal_set_event(enum offload_event_num event_num) struct net_device *dit_hal_get_dst_netdev(enum dit_desc_ring ring_num) { -#if defined(DIT_DEBUG_LOW) - struct io_device *iod; + if (ring_num < DIT_DST_DESC_RING_0 || ring_num >= DIT_DST_DESC_RING_MAX) + return NULL; +#if defined(DIT_DEBUG_LOW) if (dc->pktgen_ch && (ring_num == DIT_DST_DESC_RING_0)) { + struct io_device *iod; + iod = link_get_iod_with_channel(dc->ld, dc->pktgen_ch); return iod ? iod->ndev : NULL; @@ -437,45 +440,7 @@ static bool dit_hal_set_local_port(struct nat_local_port *local_port) return true; } -static void dit_hal_set_iod_clat_netdev(struct io_device *iod, void *args) -{ - struct clat_info *clat = (struct clat_info *) args; - struct net_device *ndev = NULL; - unsigned long flags; - - if (!dc->ld || !dc->ld->is_ps_ch(iod->ch)) - return; - - if (strncmp(iod->name, clat->ipv6_iface, IFNAMSIZ) != 0) - return; - - if (clat->ipv4_iface[0]) - ndev = dev_get_by_name(&init_net, clat->ipv4_iface); - - if (!clat->ipv4_iface[0] || ndev) { - spin_lock_irqsave(&iod->clat_lock, flags); - if (iod->clat_ndev) - dev_put(iod->clat_ndev); - - iod->clat_ndev = ndev; - spin_unlock_irqrestore(&iod->clat_lock, flags); - -#if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) - if (iod->clat_ndev) { - struct mem_link_device *mld = to_mem_link_device(dc->ld); - - mif_info("set RPS again\n"); - mld->tpmon->reset_data("RPS"); - } -#endif - - mif_info("%s clat netdev[%d] ch: %d, iface v6/v4: %s/%s\n", - (ndev ? "set" : "clear"), clat->rmnet_index, iod->ch, - clat->ipv6_iface, clat->ipv4_iface); - } -} - -bool dit_hal_set_clat_info(struct clat_info *clat) +bool dit_hal_set_clat_info(struct mem_link_device *mld, struct clat_info *clat) { unsigned int offset; unsigned long flags; @@ -486,13 +451,13 @@ bool dit_hal_set_clat_info(struct clat_info *clat) spin_lock_irqsave(&dc->src_lock, flags); /* IPv4 addr of TUN device */ - offset = clat->rmnet_index * DIT_REG_CLAT_TX_FILTER_INTERVAL; + offset = clat->clat_index * DIT_REG_CLAT_TX_FILTER_INTERVAL; if (dit_enqueue_reg_value_with_ext_lock(clat->ipv4_local_subnet.s_addr, DIT_REG_CLAT_TX_FILTER + offset) < 0) goto exit; /* IPv6 addr for TUN device */ - offset = clat->rmnet_index * DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL; + offset = clat->clat_index * DIT_REG_CLAT_TX_CLAT_SRC_INTERVAL; if (dit_enqueue_reg_value_with_ext_lock(clat->ipv6_local_subnet.s6_addr32[0], DIT_REG_CLAT_TX_CLAT_SRC_0 + offset) < 0) goto exit; @@ -507,7 +472,7 @@ bool dit_hal_set_clat_info(struct clat_info *clat) goto exit; /* PLAT prefix */ - offset = clat->rmnet_index * DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL; + offset = clat->clat_index * DIT_REG_CLAT_TX_PLAT_PREFIX_INTERVAL; if (dit_enqueue_reg_value_with_ext_lock(clat->plat_subnet.s6_addr32[0], DIT_REG_CLAT_TX_PLAT_PREFIX_0 + offset) < 0) goto exit; @@ -522,7 +487,7 @@ bool dit_hal_set_clat_info(struct clat_info *clat) /* set clat_ndev with clat registers */ if (clat->ipv4_iface[0]) - iodevs_for_each(dc->ld->msd, dit_hal_set_iod_clat_netdev, clat); + iodevs_for_each(dc->ld->msd, mld->tc->set_iod_clat_netdev, clat); exit: spin_unlock_irqrestore(&dc->src_lock, flags); @@ -530,11 +495,34 @@ bool dit_hal_set_clat_info(struct clat_info *clat) /* clear clat_ndev but take a delay to prevent null ndev */ if (ret && !clat->ipv4_iface[0]) { msleep(100); - iodevs_for_each(dc->ld->msd, dit_hal_set_iod_clat_netdev, clat); + iodevs_for_each(dc->ld->msd, mld->tc->set_iod_clat_netdev, clat); } return ret; } +EXPORT_SYMBOL(dit_hal_set_clat_info); + +static void dit_hal_try_stop_enqueue_rx(bool stop) +{ + if (unlikely(!dc)) + return; + + if (dc->hal_enqueue_rx) + dc->stop_enqueue[DIT_DIR_RX] = stop; +} + +static void dit_hal_set_reg_upstream(void) +{ + struct net_device *netdev = NULL; + + if (unlikely(!dc)) + return; + + if (dhc->dst_iface[DIT_DST_DESC_RING_0].iface_set) + netdev = dhc->dst_iface[DIT_DST_DESC_RING_0].netdev; + + DIT_INDIRECT_CALL(dc, set_reg_upstream, netdev); +} static long dit_hal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { @@ -543,7 +531,6 @@ static long dit_hal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg struct forward_limit limit; struct nat_local_addr local_addr; struct nat_local_port local_port; - struct clat_info clat; struct hw_info hw; int ret; @@ -556,32 +543,41 @@ static long dit_hal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg switch (cmd) { case OFFLOAD_IOCTL_INIT_OFFLOAD: mif_info("hal init\n"); + ret = dit_hal_init(); if (ret) { mif_err("hal init failed. ret: %d\n", ret); return ret; } + mutex_lock(&dhc->ioctl_lock); ret = dit_manage_rx_dst_data_buffers(true); + mutex_unlock(&dhc->ioctl_lock); if (ret) { mif_err("hal buffer fill failed. ret: %d\n", ret); return ret; } + + dit_hal_try_stop_enqueue_rx(false); spin_lock(&dhc->hal_lock); dhc->hal_enabled = true; spin_unlock(&dhc->hal_lock); break; case OFFLOAD_IOCTL_STOP_OFFLOAD: mif_info("hal stopped\n"); + spin_lock(&dhc->hal_lock); dhc->hal_enabled = false; spin_unlock(&dhc->hal_lock); + dit_hal_try_stop_enqueue_rx(true); dit_hal_set_event(INTERNAL_OFFLOAD_STOPPED); /* init port table and take a delay for the prior kick */ dit_init(NULL, DIT_INIT_NORMAL, DIT_STORE_NONE); msleep(100); + mutex_lock(&dhc->ioctl_lock); ret = dit_manage_rx_dst_data_buffers(false); + mutex_unlock(&dhc->ioctl_lock); if (ret) mif_err("hal buffer free. ret: %d\n", ret); @@ -621,10 +617,13 @@ static long dit_hal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg return -EFAULT; /* hal can remove upstream by null iface name */ - if (dit_hal_add_dst_iface(true, &info) < 0) { + ret = dit_hal_add_dst_iface(true, &info); + dit_hal_set_reg_upstream(); + if (ret < 0) { dit_hal_set_event(OFFLOAD_STOPPED_ERROR); break; } + if (dit_hal_check_ready_to_start()) dit_hal_set_event(OFFLOAD_STARTED); break; @@ -671,13 +670,6 @@ static long dit_hal_ioctl(struct file *filp, unsigned int cmd, unsigned long arg if (!dit_hal_set_local_port(&local_port)) return -EINVAL; break; - case OFFLOAD_IOCTL_SET_CLAT_INFO: - if (copy_from_user(&clat, (const void __user *)arg, sizeof(struct clat_info))) - return -EFAULT; - - if (!dit_hal_set_clat_info(&clat)) - return -EINVAL; - break; case OFFLOAD_IOCTL_GET_HW_INFO: hw.version = dc->hw_version; hw.capabilities = dc->hw_capabilities; @@ -732,6 +724,7 @@ int dit_hal_create(struct dit_ctrl_t *dc_ptr) spin_lock_init(&dhc->hal_lock); spin_lock_init(&dhc->event_lock); spin_lock_init(&dhc->stats_lock); + mutex_init(&dhc->ioctl_lock); ret = misc_register(&dit_misc); if (ret) { diff --git a/drivers/soc/google/cpif/dit_hal.h b/drivers/soc/google/cpif/dit/dit_hal.h similarity index 88% rename from drivers/soc/google/cpif/dit_hal.h rename to drivers/soc/google/cpif/dit/dit_hal.h index bba388555491..6d88865e3523 100644 --- a/drivers/soc/google/cpif/dit_hal.h +++ b/drivers/soc/google/cpif/dit/dit_hal.h @@ -10,11 +10,7 @@ #ifndef __DIT_HAL_H__ #define __DIT_HAL_H__ -#include -#include -#include - -#include "dit.h" +#include "dit_common.h" #define DIT_HAL_DEV_NAME "dit2" @@ -67,15 +63,6 @@ struct nat_local_port { }; } __packed; -struct clat_info { - unsigned int rmnet_index; - char ipv6_iface[IFNAMSIZ]; - char ipv4_iface[IFNAMSIZ]; - struct in6_addr ipv6_local_subnet; - struct in_addr ipv4_local_subnet; - struct in6_addr plat_subnet; -} __packed; - struct hw_info { u32 version; u32 capabilities; @@ -96,8 +83,6 @@ struct hw_info { #define OFFLOAD_IOCTL_SET_NAT_LOCAL_ADDR _IOW(OFFLOAD_IOC_MAGIC, 0x20, struct nat_local_addr) #define OFFLOAD_IOCTL_SET_NAT_LOCAL_PORT _IOW(OFFLOAD_IOC_MAGIC, 0x21, struct nat_local_port) -#define OFFLOAD_IOCTL_SET_CLAT_INFO _IOW(OFFLOAD_IOC_MAGIC, 0x40, struct clat_info) - /* mandatory */ #define OFFLOAD_IOCTL_GET_HW_INFO _IOR(OFFLOAD_IOC_MAGIC, 0xE0, struct hw_info) @@ -157,12 +142,12 @@ struct dit_hal_ctrl_t { wait_queue_head_t wq; struct list_head event_q; spinlock_t event_lock; + struct mutex ioctl_lock; }; int dit_hal_create(struct dit_ctrl_t *dc_ptr); struct net_device *dit_hal_get_dst_netdev(enum dit_desc_ring ring_num); void dit_hal_add_data_bytes(u64 rx_bytes, u64 tx_bytes); -bool dit_hal_set_clat_info(struct clat_info *clat); #endif /* __DIT_HAL_H__ */ diff --git a/drivers/soc/google/cpif/dit_net.c b/drivers/soc/google/cpif/dit/dit_net.c similarity index 99% rename from drivers/soc/google/cpif/dit_net.c rename to drivers/soc/google/cpif/dit/dit_net.c index b1e327451a84..4ba00416ee8e 100644 --- a/drivers/soc/google/cpif/dit_net.c +++ b/drivers/soc/google/cpif/dit/dit_net.c @@ -16,7 +16,6 @@ #include #include "modem_utils.h" -#include "dit.h" #include "dit_net.h" int dit_net_receive_skb(struct sk_buff *skb) diff --git a/drivers/soc/google/cpif/dit_net.h b/drivers/soc/google/cpif/dit/dit_net.h similarity index 93% rename from drivers/soc/google/cpif/dit_net.h rename to drivers/soc/google/cpif/dit/dit_net.h index f3cd4b2cd9d9..2b0d135b659a 100644 --- a/drivers/soc/google/cpif/dit_net.h +++ b/drivers/soc/google/cpif/dit/dit_net.h @@ -12,6 +12,8 @@ #define DIT_NET_DEV_NAME "dit%d" +#include "dit_common.h" + struct dit_net_priv { struct dit_ctrl_t *dc; }; diff --git a/drivers/soc/google/cpif/hook.c b/drivers/soc/google/cpif/hook.c new file mode 100644 index 000000000000..0b931d4ac841 --- /dev/null +++ b/drivers/soc/google/cpif/hook.c @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * tracepoint hook handling + * + * Copyright (C) 2021 Samsung Electronics Co., Ltd + * + */ + +#include +#include "../../../kernel/sched/sched.h" + +#define TASK_VENDOR 0x2000 +/****************************************************************************** + * tracepoint of Android vendor hook * + ******************************************************************************/ +static void cpif_hook_do_wake_up_sync(void *data, + struct wait_queue_head *wq_head, int *done) +{ +#ifdef WF_ANDROID_VENDOR + *done = 1; + __wake_up_sync_key(wq_head, TASK_INTERRUPTIBLE | TASK_VENDOR, + poll_to_key(EPOLLIN | EPOLLPRI | EPOLLRDNORM | EPOLLRDBAND)); +#endif +} + +static void cpif_hook_set_wake_flags(void *data, + int *wake_flags, unsigned int *mode) +{ +#ifdef WF_ANDROID_VENDOR + if (*mode & TASK_VENDOR) { + *mode &= ~TASK_VENDOR; + *wake_flags = WF_ANDROID_VENDOR; + } +#endif +} + +int hook_init(void) +{ + int ret; + + ret = register_trace_android_vh_do_wake_up_sync(cpif_hook_do_wake_up_sync, NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_set_wake_flags(cpif_hook_set_wake_flags, NULL); + if (ret) + return ret; + + return 0; +} +EXPORT_SYMBOL(hook_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Samsung CPIF vendor hook driver"); diff --git a/drivers/soc/google/cpif/include/circ_queue.h b/drivers/soc/google/cpif/include/circ_queue.h index 25c064cf942d..acaa6fe0ed68 100644 --- a/drivers/soc/google/cpif/include/circ_queue.h +++ b/drivers/soc/google/cpif/include/circ_queue.h @@ -17,14 +17,6 @@ #include #include -#define GROUP_CIRC_QUEUE - -#ifdef GROUP_CIRC_QUEUE -/* - * @defgroup group_circ_queue Circular Queue - * @{ - */ - /* * @brief the structure for a circular queue in a memory-type interface */ @@ -287,10 +279,4 @@ static inline void circ_write(u8 *dst, u8 *src, unsigned int qsize, } } -/* - * End of GROUP_CIRC_QUEUE - * @} - */ -#endif - #endif diff --git a/drivers/soc/google/cpif/include/exynos_ipc.h b/drivers/soc/google/cpif/include/exynos_ipc.h index 0118277ee3ac..d1b62283791a 100644 --- a/drivers/soc/google/cpif/include/exynos_ipc.h +++ b/drivers/soc/google/cpif/include/exynos_ipc.h @@ -42,13 +42,6 @@ #define EXYNOS_FMT_NUM 1 #define EXYNOS_RFS_NUM 10 -struct __packed frag_config { - u8 frame_first:1, - frame_last:1, - packet_index:6; - u8 frame_index; -}; - /* EXYNOS link-layer header */ struct __packed exynos_link_header { u16 sync; @@ -64,32 +57,6 @@ struct __packed exynos_seq_num { u8 ch_cnt[255]; }; -struct exynos_frame_data { - /* Frame length calculated from the length fields */ - unsigned int len; - - /* The length of link layer header */ - unsigned int hdr_len; - - /* The length of received header */ - unsigned int hdr_rcvd; - - /* The length of link layer payload */ - unsigned int pay_len; - - /* The length of received data */ - unsigned int pay_rcvd; - - /* The length of link layer padding */ - unsigned int pad_len; - - /* The length of received padding */ - unsigned int pad_rcvd; - - /* Header buffer */ - u8 hdr[EXYNOS_HEADER_SIZE]; -}; - static inline bool exynos_start_valid(u8 *frm) { u16 cfg = *(u16 *)(frm + EXYNOS_START_OFFSET); diff --git a/drivers/soc/google/cpif/include/legacy.h b/drivers/soc/google/cpif/include/legacy.h index f38b63503c94..8e04de22b11f 100644 --- a/drivers/soc/google/cpif/include/legacy.h +++ b/drivers/soc/google/cpif/include/legacy.h @@ -10,11 +10,6 @@ #include "circ_queue.h" #include "sipc5.h" -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) -#define DOORBELL_INT_ADD 0x10000 -#define MODEM_INT_NUM 16 -#endif - #define BAD_MSG_BUFFER_SIZE 32 enum legacy_ipc_map { @@ -23,7 +18,7 @@ enum legacy_ipc_map { IPC_MAP_HPRIO_RAW, #endif IPC_MAP_NORM_RAW, - MAX_SIPC_MAP, + IPC_MAP_MAX, }; struct legacy_ipc_device { @@ -54,9 +49,7 @@ struct legacy_link_device { u32 __iomem *magic; u32 __iomem *mem_access; - struct legacy_ipc_device *dev[MAX_SIPC_MAP]; - - + struct legacy_ipc_device *dev[IPC_MAP_MAX]; }; int create_legacy_link_device(struct mem_link_device *mld); diff --git a/drivers/soc/google/cpif/include/sbd.h b/drivers/soc/google/cpif/include/sbd.h index d63eadcf8d32..f5cd4d9ce3c7 100644 --- a/drivers/soc/google/cpif/include/sbd.h +++ b/drivers/soc/google/cpif/include/sbd.h @@ -48,7 +48,7 @@ #define BUFF_RGN_OFFSET (CMD_DESC_RGN_SIZE) #define MAX_SBD_SIPC_CHANNELS IOD_CH_ID_MAX /* 2 ^ 8 */ -#define MAX_SBD_LINK_IDS 64 /* up to 64 ids */ +#define MAX_SBD_LINK_IDS 32 /* up to 32 ids */ /* * @brief Priority for QoS(Quality of Service) @@ -145,18 +145,12 @@ struct sbd_ring_buffer { /* Pointer to the "SBD link" device instance to which an RB belongs */ struct sbd_link_device *sl; - /* Pointer to the "zerocopy_adaptor" device instance to which an RB belongs */ - struct zerocopy_adaptor *zdptr; - /* UL/DL socket buffer queues */ struct sk_buff_head skb_q; /* Whether or not link-layer header is used */ bool lnk_hdr; - /* Whether or not zerocopy is used */ - bool zerocopy; - /* * Variables for receiving a frame with the SIPC5 "EXT_LEN" attribute * (With SBD architecture, a frame with EXT_LEN can be scattered into @@ -209,34 +203,6 @@ struct sbd_link_attr { /* Size of the data buffer for each SBD in an SBD RB */ unsigned int buff_size[ULDL]; - - /* Bool variable to check if SBD ipc device supports zerocopy */ - bool zerocopy; -}; - -struct zerocopy_adaptor { - /* Spin-lock for each zerocopy_adaptor */ - spinlock_t lock; - - /* Spin-lock for kfifo */ - spinlock_t lock_kfifo; - - /* SBD ring buffer that matches this zerocopy_adaptor */ - struct sbd_ring_buffer *rb; - - /* Variables to manage previous rp */ - u16 pre_rp; - - /* Pointers to variables in the shared region for a physical SBD RB */ - u16 *rp; - u16 *wp; - u16 len; - - /* Pointer to kfifo for saving dma_addr */ - struct kfifo fifo; - - /* Timer for when buffer pool is full */ - struct hrtimer datalloc_timer; }; struct sbd_ipc_device { @@ -249,16 +215,8 @@ struct sbd_ipc_device { /* SIPC Channel ID --> rb.ch */ u16 ch; - atomic_t config_done; - /* UL/DL SBD RB pair in the kernel space */ struct sbd_ring_buffer rb[ULDL]; - - /* Bool variable to check if SBD ipc device supports zerocopy */ - bool zerocopy; - - /* Pointer to Zerocopy adaptor : memory is allocated for UL/DL zerocopy_adaptor */ - struct zerocopy_adaptor *zdptr; }; struct sbd_link_device { @@ -315,8 +273,6 @@ struct sbd_link_device { struct sbd_global_desc *g_desc; unsigned long rxdone_mask; - - bool reset_zerocopy_done; }; static inline void sbd_activate(struct sbd_link_device *sl) @@ -392,64 +348,25 @@ static inline struct sbd_ring_buffer *sbd_id2rb(struct sbd_link_device *sl, return (id < MAX_SBD_LINK_IDS) ? &sl->ipc_dev[id].rb[dir] : NULL; } -static inline bool zerocopy_adaptor_empty(struct zerocopy_adaptor *zdptr) -{ - return circ_empty(zdptr->pre_rp, *zdptr->rp); -} - static inline bool rb_empty(struct sbd_ring_buffer *rb) { WARN_ON(!rb); - if (rb->zdptr) - return zerocopy_adaptor_empty(rb->zdptr); - else - return circ_empty(*rb->rp, *rb->wp); -} - -static inline unsigned int zerocopy_adaptor_space(struct zerocopy_adaptor *zdptr) -{ - return circ_get_space(zdptr->len, *zdptr->wp, zdptr->pre_rp); + return circ_empty(*rb->rp, *rb->wp); } static inline unsigned int rb_space(struct sbd_ring_buffer *rb) { WARN_ON(!rb); - if (rb->zdptr) - return zerocopy_adaptor_space(rb->zdptr); - else - return circ_get_space(rb->len, *rb->wp, *rb->rp); -} - -static inline unsigned int zerocopy_adaptor_usage(struct zerocopy_adaptor *zdptr) -{ - return circ_get_usage(zdptr->len, *zdptr->rp, zdptr->pre_rp); + return circ_get_space(rb->len, *rb->wp, *rb->rp); } static inline unsigned int rb_usage(struct sbd_ring_buffer *rb) { WARN_ON(!rb); - if (rb->zdptr) - return zerocopy_adaptor_usage(rb->zdptr); - else - return circ_get_usage(rb->len, *rb->wp, *rb->rp); -} - -static inline unsigned int zerocopy_adaptor_full(struct zerocopy_adaptor *zdptr) -{ - return (zerocopy_adaptor_space(zdptr) == 0); -} - -static inline unsigned int rb_full(struct sbd_ring_buffer *rb) -{ - WARN_ON(!rb); - - if (rb->zdptr) - return zerocopy_adaptor_full(rb->zdptr); - else - return (rb_space(rb) == 0); + return circ_get_usage(rb->len, *rb->wp, *rb->rp); } static inline void set_lnk_hdr(struct sbd_ring_buffer *rb, struct sk_buff *skb) @@ -477,6 +394,7 @@ static inline void check_more(struct sbd_ring_buffer *rb, struct sk_buff *skb) } } +#if IS_ENABLED(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) int create_sbd_link_device(struct link_device *ld, struct sbd_link_device *sl, u8 *shmem_base, unsigned int shmem_size); @@ -484,22 +402,21 @@ int init_sbd_link(struct sbd_link_device *sl); bool check_sbd_tx_pending(struct mem_link_device *mld); int sbd_pio_tx(struct sbd_ring_buffer *rb, struct sk_buff *skb); -struct sk_buff *sbd_pio_rx(struct sbd_ring_buffer *rb); - -#define SBD_UL_LIMIT 16 /* Uplink burst limit */ +int sbd_pio_rx(struct sbd_ring_buffer *rb, struct sk_buff **skb); +#else +static inline int create_sbd_link_device(struct link_device *ld, struct sbd_link_device *sl, + u8 *shmem_base, unsigned int shmem_size) { return 0; } -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) -extern const struct attribute_group zerocopy_group; +static inline int init_sbd_link(struct sbd_link_device *sl) { return 0; } +static inline bool check_sbd_tx_pending(struct mem_link_device *mld) + { return false; } -struct sk_buff *sbd_pio_rx_zerocopy_adaptor(struct sbd_ring_buffer *rb, int use_memcpy); -int allocate_data_in_advance(struct zerocopy_adaptor *zdptr); -int setup_zerocopy_adaptor(struct sbd_ipc_device *ipc_dev); -extern enum hrtimer_restart datalloc_timer_func(struct hrtimer *timer); -#else -static inline struct sk_buff *sbd_pio_rx_zerocopy_adaptor(struct sbd_ring_buffer *rb, - int use_memcpy) { return NULL; } -static inline int allocate_data_in_advance(struct zerocopy_adaptor *zdptr) { return 0; } -static inline int setup_zerocopy_adaptor(struct sbd_ipc_device *ipc_dev) { return 0; } +static inline int sbd_pio_tx(struct sbd_ring_buffer *rb, + struct sk_buff *skb) { return 0; } +static inline int sbd_pio_rx(struct sbd_ring_buffer *rb, struct sk_buff **skb) + { return 0; } #endif +#define SBD_UL_LIMIT 16 /* Uplink burst limit */ + #endif diff --git a/drivers/soc/google/cpif/include/sipc5.h b/drivers/soc/google/cpif/include/sipc5.h index d7a9485da283..2bfd250e7d40 100644 --- a/drivers/soc/google/cpif/include/sipc5.h +++ b/drivers/soc/google/cpif/include/sipc5.h @@ -203,7 +203,11 @@ static inline bool sipc5_ipc_ch(u8 ch) static inline bool sipc_ps_ch(u8 ch) { +#if IS_ENABLED(CONFIG_CH_EXTENSION) + return (ch >= SIPC_CH_EX_ID_PDP_0 && ch <= SIPC_CH_EX_ID_PDP_MAX) ? +#else return (ch >= SIPC_CH_ID_PDP_0 && ch <= SIPC_CH_ID_PDP_14) ? +#endif true : false; } @@ -230,66 +234,4 @@ static inline bool sipc_misc_ch(u8 ch) return (ch == SIPC_CH_ID_CASS) ? true : false; } -struct sipc5_frame_data { - /* Frame length calculated from the length fields */ - unsigned int len; - - /* The length of link layer header */ - unsigned int hdr_len; - - /* The length of received header */ - unsigned int hdr_rcvd; - - /* The length of link layer payload */ - unsigned int pay_len; - - /* The length of received data */ - unsigned int pay_rcvd; - - /* The length of link layer padding */ - unsigned int pad_len; - - /* The length of received padding */ - unsigned int pad_rcvd; - - /* Header buffer */ - u8 hdr[SIPC5_MAX_HEADER_SIZE]; -}; - -#define STD_UDL_STEP_MASK 0x0000000F -#define STD_UDL_SEND 0x1 -#define STD_UDL_CRC 0xC - -struct std_dload_info { - u32 size; - u32 mtu; - u32 num_frames; -} __packed; - - -/* - * @brief get BOOT/DUMP command - * @param frm the pointer to an SIPC5 link frame - * @return the standard BOOT/DUMP command in an SIPC5 BOOT/DUMP frame - */ -static inline u32 std_bootdump_get_cmd(u8 *frm) -{ - u8 *cmd = frm + sipc5_get_hdr_len(frm); - - return *((u32 *)cmd); -} - -/* - * @brief check whether or not a command came with a payload - * @param cmd the standard BOOT/DUMP command - * @retval "true" if the STD_UDL command has a payload - * @retval "false" otherwise - */ -static inline bool std_bootdump_with_payload(u32 cmd) -{ - u32 mask = cmd & STD_UDL_STEP_MASK; - - return (mask && mask < STD_UDL_CRC) ? true : false; -} - #endif diff --git a/drivers/soc/google/cpif/ipc_io_device.c b/drivers/soc/google/cpif/ipc_io_device.c index a76189ec525f..91ac40dcfc5f 100644 --- a/drivers/soc/google/cpif/ipc_io_device.c +++ b/drivers/soc/google/cpif/ipc_io_device.c @@ -100,32 +100,24 @@ static unsigned int ipc_poll(struct file *filp, struct poll_table_struct *wait) switch (mc->phone_state) { case STATE_BOOTING: case STATE_ONLINE: - if (!mc->sim_state.changed) { - if (!skb_queue_empty(rxq)) - return POLLIN | POLLRDNORM; - else /* wq is waken up without rx, return for wait */ - return 0; - } - /* fall through, if sim_state has been changed */ + if (!skb_queue_empty(rxq)) + return POLLIN | POLLRDNORM; + break; case STATE_CRASH_EXIT: case STATE_CRASH_RESET: case STATE_NV_REBUILDING: case STATE_CRASH_WATCHDOG: mif_err_limited("%s: %s.state == %s\n", iod->name, mc->name, mc_state(mc)); + if (iod->format == IPC_FMT) return POLLHUP; - - /* give delay to prevent infinite sys_poll call from - * select() in APP layer without 'sleep' user call takes - * almost 100% cpu usage when it is looked up by 'top' - * command. - */ - msleep(20); break; + case STATE_RESET: + mif_err_limited("%s: %s.state == %s\n", iod->name, mc->name, mc_state(mc)); - case STATE_OFFLINE: - if (iod->ch == EXYNOS_CH_ID_CPLOG && ld->protocol == PROTOCOL_SIT) + if (iod->attrs & IO_ATTR_STATE_RESET_NOTI) return POLLHUP; + break; default: break; } @@ -151,15 +143,17 @@ static long ipc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) iod->name, cp_state_str(p_state)); } - if (mc->sim_state.changed) { - enum modem_state s_state = mc->sim_state.online ? - STATE_SIM_ATTACH : STATE_SIM_DETACH; - mc->sim_state.changed = false; - return s_state; - } - - if (p_state == STATE_NV_REBUILDING) + switch (p_state) { + case STATE_NV_REBUILDING: mc->phone_state = STATE_ONLINE; + break; + /* Do not return an internal state */ + case STATE_RESET: + p_state = STATE_OFFLINE; + break; + default: + break; + } return p_state; @@ -217,33 +211,27 @@ static long ipc_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return 0; } +#define INIT_END_WAIT_MS 150 + static ssize_t ipc_write(struct file *filp, const char __user *data, size_t count, loff_t *fpos) { struct io_device *iod = (struct io_device *)filp->private_data; struct link_device *ld = get_current_link(iod); + struct mem_link_device *mld = to_mem_link_device(ld); struct modem_ctl *mc = iod->mc; - struct sk_buff *skb; - char *buff; - int ret; u8 cfg = 0; u16 cfg_sit = 0; - unsigned int headroom; - unsigned int tailroom; - unsigned int tx_bytes; + unsigned int headroom = 0; unsigned int copied = 0, tot_frame = 0, copied_frm = 0; - unsigned int remains; - unsigned int alloc_size; /* 64bit prevent */ unsigned int cnt = (unsigned int)count; -#ifdef DEBUG_MODEM_IF struct timespec64 ts; -#endif + int curr_init_end_cnt; + int retry = 0; -#ifdef DEBUG_MODEM_IF /* Record the timestamp */ ktime_get_ts64(&ts); -#endif if (iod->format <= IPC_RFS && iod->ch == 0) return -EINVAL; @@ -259,44 +247,61 @@ static ssize_t ipc_write(struct file *filp, const char __user *data, case PROTOCOL_SIPC: cfg = sipc5_build_config(iod, ld, cnt); headroom = sipc5_get_hdr_len(&cfg); - break; + break; case PROTOCOL_SIT: cfg_sit = exynos_build_fr_config(iod, ld, cnt); headroom = EXYNOS_HEADER_SIZE; - break; + break; default: mif_err("protocol error %d\n", ld->protocol); return -EINVAL; } - } else { - cfg = 0; - cfg_sit = 0; - headroom = 0; } - switch (ld->protocol) { - case PROTOCOL_SIPC: - if (unlikely(!mc->receive_first_ipc) && ld->is_log_ch(iod->ch)) - return -EBUSY; - break; - case PROTOCOL_SIT: - break; - default: - mif_err("protocol error %d\n", ld->protocol); - return -EINVAL; + /* Wait for a while if a new CMD_INIT_END is sent */ + while ((curr_init_end_cnt = atomic_read(&mld->init_end_cnt)) != mld->last_init_end_cnt && + retry++ < 3) { + mif_info_limited("%s: wait for INIT_END done (%dms) cnt:%d last:%d cmd:0x%02X\n", + iod->name, INIT_END_WAIT_MS, + curr_init_end_cnt, mld->last_init_end_cnt, + mld->read_ap2cp_irq(mld)); + + if (atomic_inc_return(&mld->init_end_busy) > 1) + curr_init_end_cnt = -1; + + msleep(INIT_END_WAIT_MS); + if (curr_init_end_cnt >= 0) + mld->last_init_end_cnt = curr_init_end_cnt; + + atomic_dec(&mld->init_end_busy); + } + + if (unlikely(!mld->last_init_end_cnt)) { + mif_err_limited("%s: INIT_END is not done\n", iod->name); + return -EAGAIN; } while (copied < cnt) { - remains = cnt - copied; + struct sk_buff *skb; + char *buff; + unsigned int remains = cnt - copied; + unsigned int tailroom = 0; + unsigned int tx_bytes; + unsigned int alloc_size; + int ret; + + if (check_add_overflow(remains, headroom, &alloc_size)) + alloc_size = SZ_2K; switch (ld->protocol) { case PROTOCOL_SIPC: - alloc_size = min_t(unsigned int, remains + headroom, - iod->max_tx_size ?: remains + headroom); - break; + if (iod->max_tx_size) + alloc_size = min_t(unsigned int, alloc_size, + iod->max_tx_size); + break; case PROTOCOL_SIT: - alloc_size = min_t(unsigned int, remains + headroom, SZ_2K); - break; + alloc_size = min_t(unsigned int, alloc_size, SZ_2K); + break; default: mif_err("protocol error %d\n", ld->protocol); return -EINVAL; @@ -305,8 +310,6 @@ static ssize_t ipc_write(struct file *filp, const char __user *data, /* Calculate tailroom for padding size */ if (iod->link_header && ld->aligned) tailroom = ld->calc_padding_size(alloc_size); - else - tailroom = 0; alloc_size += tailroom; @@ -343,10 +346,8 @@ static ssize_t ipc_write(struct file *filp, const char __user *data, skbpriv(skb)->lnk_hdr = iod->link_header; skbpriv(skb)->sipc_ch = iod->ch; -#ifdef DEBUG_MODEM_IF /* Copy the timestamp to the skb */ skbpriv(skb)->ts = ts; -#endif #ifdef DEBUG_MODEM_IF_IODEV_TX mif_pkt(iod->ch, "IOD-TX", skb); #endif @@ -359,14 +360,13 @@ static ssize_t ipc_write(struct file *filp, const char __user *data, case PROTOCOL_SIPC: sipc5_build_header(iod, buff, cfg, tx_bytes, cnt - copied); - break; + break; case PROTOCOL_SIT: exynos_build_header(iod, ld, buff, cfg_sit, 0, tx_bytes); /* modify next link header for multiframe */ if (((cfg_sit >> 8) & EXYNOS_SINGLE_MASK) != EXYNOS_SINGLE_MASK) cfg_sit = modify_next_frame(cfg_sit); - - break; + break; default: mif_err("protocol error %d\n", ld->protocol); return -EINVAL; diff --git a/drivers/soc/google/cpif/link_ctrlmsg_iosm.c b/drivers/soc/google/cpif/link_ctrlmsg_iosm.c deleted file mode 100644 index c127c10124f5..000000000000 --- a/drivers/soc/google/cpif/link_ctrlmsg_iosm.c +++ /dev/null @@ -1,402 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2014 Samsung Electronics. - * - */ - -#include "modem_utils.h" -#include "link_device_memory.h" -#include "link_device_memory_ctrlmsg_iosm.h" - -#define pr_circ_idx(hdr) \ - mif_info("circ: in=%d, out=%d\n", hdr->w_idx, hdr->r_idx) - -struct iosm_msg_area_head { - u32 w_idx; /* Write index */ - u32 r_idx; /* Read index */ - u32 reserved[2]; - u32 num_msg; /* Is this actually required? */ -} __packed; - -struct iosm_msg { - u8 msg_id; /* message id */ - u8 trs_id; /* transaction id */ - union { - struct __packed { - u8 reserved[2]; - u32 addr; - } ap_ready; - struct __packed { - u8 ch_id; - u8 cfg; - } open_ch; - struct __packed { - u8 ch_id; - u8 cfg; - } close_ch; - struct __packed { - u8 ch_id; - u8 cfg; - } conf_ch_req; - struct __packed { - u8 ch_id; - u8 cfg; - } conf_ch_rsp; - struct __packed { - u8 ch_id; - } stop_tx_ch; - struct __packed { - u8 ch_id; - } start_tx_ch; - struct __packed { - u8 ch_id; - u8 msg_id; - } ack; - struct __packed { - u8 ch_id; - u8 msg_id; - u8 err_class; - u8 err_subclass; - } nack; - u8 reserved[10]; - }; -} __packed; - -#define IOSM_NUM_ELEMENTS ( \ - (IOSM_MSG_AREA_SIZE - sizeof(struct iosm_msg_area_head)) \ - / sizeof(struct iosm_msg)) - -/* Message Area definition */ -struct iosm_msg_area { - struct iosm_msg_area_head hdr; - struct iosm_msg elements[IOSM_NUM_ELEMENTS]; -} __packed; - -static struct workqueue_struct *iosm_wq; -static struct mutex iosm_mtx; -static atomic_t mdm_ready; - -static const char * const tx_iosm_str[] = { - [IOSM_A2C_AP_READY] = "AP_READY", - [IOSM_A2C_CONF_CH_REQ] = "CONF_CH_REQ", - [IOSM_A2C_OPEN_CH] = "OPEN_CH", - [IOSM_A2C_CLOSE_CH] = "CLOSE_CH", - [IOSM_A2C_STOP_TX_CH] = "STOP_TX_CH", - [IOSM_A2C_START_TX_CH] = "START_TX_CH", - [IOSM_A2C_ACK] = "ACK", - [IOSM_A2C_NACK] = "NACK", -}; - -/* 8-bit transaction ID: holds unique id value (1 ~ 255) - * different number than the last message and incremented by one - * also to be echoed back in the response of received message - */ -static atomic_t tid = ATOMIC_INIT(-1); - -static inline int get_transaction_id(void) -{ - return atomic_inc_return(&tid) % IOSM_TRANS_ID_MAX + 1; -} - -static inline int check_ul_space(u32 qlen, u32 in, u32 out) -{ - u32 usage, space; - - if (!circ_valid(qlen, in, out)) { - mif_err("ERR! TXQ DIRTY (qlen:%d in:%d out:%d)\n", - qlen, in, out); - return -EIO; - } - - usage = circ_get_usage(qlen, in, out); - if (unlikely(usage > SBD_UL_LIMIT)) { - mif_err("TXQ BUSY (qlen:%d in:%d out:%d usage:%d)\n", - qlen, in, out, usage); - return -EBUSY; - } - - space = circ_get_space(qlen, in, out); - if (unlikely(space < 1)) { - mif_err("TXQ NOSPC (qlen:%d in:%d out:%d)\n", qlen, in, out); - return -ENOSPC; - } - - return space; -} - -inline void create_iosm_message(struct iosm_msg *txmsg, u8 mid, u32 *args) -{ - struct iosm_msg *msg; - - txmsg->msg_id = mid; - - switch (mid) { - case IOSM_A2C_AP_READY: - /* set global descriptor address */ - txmsg->ap_ready.addr = IOSM_MSG_DESC_OFFSET; - break; - case IOSM_A2C_CONF_CH_REQ: - txmsg->conf_ch_req.ch_id = *((u32 *)args); - txmsg->conf_ch_req.cfg = 0x1; - break; - case IOSM_A2C_OPEN_CH: - case IOSM_A2C_CLOSE_CH: - txmsg->close_ch.ch_id = *((u32 *)args); - txmsg->close_ch.cfg = 0x7; - break; - case IOSM_A2C_ACK: - case IOSM_A2C_NACK: - msg = (struct iosm_msg *) args; - txmsg->ack.msg_id = msg->msg_id; - if (msg->msg_id == IOSM_C2A_CONF_CH_RSP) - txmsg->ack.ch_id = msg->conf_ch_rsp.ch_id; - if (msg->msg_id == IOSM_C2A_STOP_TX_CH) - txmsg->ack.ch_id = msg->stop_tx_ch.ch_id; - if (msg->msg_id == IOSM_C2A_START_TX_CH) - txmsg->ack.ch_id = msg->start_tx_ch.ch_id; - /* trans_id shouldn't be modified from end of this function */ - txmsg->trs_id = msg->trs_id; - return; - default: - mif_err("0x%x message is not supported.\n", mid); - } - - txmsg->trs_id = get_transaction_id(); -} - -void tx_iosm_message(struct mem_link_device *mld, u8 id, u32 *args) -{ - struct iosm_msg_area *base; - struct iosm_msg_area_head *hdr; - struct iosm_msg *msg; - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - int space, retry_cnt = 500; - - if (!cp_online(mc)) - return; - - mutex_lock(&iosm_mtx); - - base = (struct iosm_msg_area *) (mld->base + IOSM_MSG_TX_OFFSET); - hdr = &base->hdr; - - /* A message sender reads the read and write index and - * determines whether there are free elements. - */ - space = check_ul_space(IOSM_NUM_ELEMENTS, hdr->w_idx, hdr->r_idx); - if (space <= 0) { - mutex_unlock(&iosm_mtx); - return; - } - - msg = &base->elements[hdr->w_idx]; - create_iosm_message(msg, id, args); - - /* The write index is incremented and interrupt is triggered - * to the message receiver. - */ - hdr->w_idx = circ_new_ptr(IOSM_NUM_ELEMENTS, hdr->w_idx, 1); - pr_circ_idx(hdr); - - mutex_unlock(&iosm_mtx); - - if (cp_online(mc) && mld->forbid_cp_sleep) - mld->forbid_cp_sleep(mld); - - /* As of now, tx path of iosm message should always guarantee - * process context. We don't have to care rx path because cp - * might try to mount lli i/f before sending data. - */ - while (!mld->link_active(mld)) { - if (--retry_cnt == 0) { - modemctl_notify_event(MDM_EVENT_CP_FORCE_CRASH); - return; - } - usleep_range(10000, 11000); - } - - send_ipc_irq(mld, mask2int(MASK_CMD_VALID)); - mif_info("sent msg %s\n", tx_iosm_str[msg->msg_id]); - - if (cp_online(mc) && mld->permit_cp_sleep) - mld->permit_cp_sleep(mld); -} - -void mdm_ready_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - int err; - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - - mif_err("%s: %s.state:%s cp_boot_done:%d\n", ld->name, - mc->name, mc_state(mc), atomic_read(&mld->cp_boot_done)); - - if (!ld->sbd_ipc) { - mif_err("%s: LINK_ATTR_SBD_IPC is NOT set\n", ld->name); - return; - } - - ld->netif_stop_mask = 0; - atomic_set(&ld->netif_stopped, 0); - atomic_set(&mc->forced_cp_crash, 0); - - change_modem_state(mc, STATE_ONLINE); - - tx_iosm_message(mld, IOSM_A2C_ACK, (u32 *)msg); - - err = init_sbd_link(&mld->sbd_link_dev); - if (err < 0) { - mif_err("%s: init_sbd_link fail(%d)\n", ld->name, err); - return; - } - - if (mld->attrs & LINK_ATTR_IPC_ALIGNED) - ld->aligned = true; - else - ld->aligned = false; - - sbd_activate(&mld->sbd_link_dev); - - tx_iosm_message(mld, IOSM_A2C_AP_READY, 0); - - mif_info("%s: %s mdm_ready done\n", ld->name, mc->name); -} - -void conf_ch_rsp_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - struct sbd_link_device *sl = &mld->sbd_link_dev; - int dev_id = sbd_ch2id(sl, msg->ack.ch_id); - struct sbd_ipc_device *sid = sbd_id2dev(sl, dev_id); - - atomic_set(&sid->config_done, 1); - tx_iosm_message(mld, IOSM_A2C_ACK, (u32 *)msg); - - mif_info("ch_id : %d, dev_id : %d\n", sid->ch, dev_id); -} - -void stop_tx_ch_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - struct link_device *ld = &mld->link_dev; - - stop_net_iface(ld, msg->stop_tx_ch.ch_id); - tx_iosm_message(mld, IOSM_A2C_ACK, (u32 *)msg); -} - -void start_tx_ch_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - struct link_device *ld = &mld->link_dev; - - resume_net_iface(ld, msg->start_tx_ch.ch_id); - tx_iosm_message(mld, IOSM_A2C_ACK, (u32 *)msg); -} - -static void action(struct io_device *iod, void *args) -{ - struct mem_link_device *mld = (struct mem_link_device *) args; - - tx_iosm_message(mld, IOSM_A2C_CONF_CH_REQ, (u32 *)&iod->ch); -} - -void ack_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - - mif_err("got ack for msg id = 0x%x\n", msg->ack.msg_id); - - switch (msg->ack.msg_id) { - case IOSM_A2C_AP_READY: - atomic_set(&mdm_ready, 1); - iodevs_for_each(ld->msd, action, mld); - break; - case IOSM_A2C_OPEN_CH: - break; - case IOSM_A2C_CLOSE_CH: - default: - break; - } -} - -void nack_handler(struct mem_link_device *mld, struct iosm_msg *msg) -{ - mif_err("got nack for msg id = 0x%x\n", msg->nack.msg_id); -} - -static struct { - u16 cmd; - char *name; - void (*handler)(struct mem_link_device *mld, struct iosm_msg *msg); -} iosm_handler[] = { - { IOSM_C2A_MDM_READY, "MDM_READY", mdm_ready_handler }, - { IOSM_C2A_CONF_CH_RSP, "CONFG_CH_RSP", conf_ch_rsp_handler }, - { IOSM_C2A_STOP_TX_CH, "STOP_TX_CH", stop_tx_ch_handler }, - { IOSM_C2A_START_TX_CH, "START_TX_CH", start_tx_ch_handler }, - { IOSM_C2A_ACK, "ACK", ack_handler }, - { IOSM_C2A_NACK, "NACK", nack_handler }, -}; - -void iosm_event_work(struct work_struct *work) -{ - struct iosm_msg_area *base; - struct iosm_msg_area_head *hdr; - struct iosm_msg *msg; - u32 i, size; - struct mem_link_device *mld = - container_of(work, struct mem_link_device, iosm_w); - - base = (struct iosm_msg_area *) (mld->base + IOSM_MSG_RX_OFFSET); - hdr = &base->hdr; - - if (unlikely(circ_empty(hdr->w_idx, hdr->r_idx))) { - mif_info("iosm message area is full\n"); - return; - } - - /* The message receiver determines the number of available messages - * based on the read and write index. - */ - size = circ_get_usage(IOSM_NUM_ELEMENTS, hdr->w_idx, hdr->r_idx); - mif_debug("number of available messages = %d\n", size); - - while (size--) { - msg = &base->elements[hdr->r_idx]; - for (i = 0; i < ARRAY_SIZE(iosm_handler); i++) - if (iosm_handler[i].cmd == msg->msg_id) { - mif_info("got msg %s\n", iosm_handler[i].name); - (*iosm_handler[i].handler)(mld, msg); - break; - } - if (i >= ARRAY_SIZE(iosm_handler)) - mif_err("0x%x message is not supported\n", msg->msg_id); - /* read index is increamented by the number of read messages */ - hdr->r_idx = circ_new_ptr(IOSM_NUM_ELEMENTS, hdr->r_idx, 1); - } - pr_circ_idx(hdr); -} - -void iosm_event_bh(struct mem_link_device *mld, u16 cmd) -{ - queue_work(iosm_wq, &mld->iosm_w); -} - -static int __init iosm_init(void) -{ - iosm_wq = create_singlethread_workqueue("iosm_wq"); - if (!iosm_wq) { - mif_err("ERR! fail to create tx_wq\n"); - return -ENOMEM; - } - mutex_init(&iosm_mtx); - atomic_set(&mdm_ready, 0); - mif_info("iosm_msg size = %ld, num of iosm elements = %ld\n", - (long)sizeof(struct iosm_msg), (long)IOSM_NUM_ELEMENTS); - return 0; -} -module_init(iosm_init); - -static void __exit iosm_exit(void) -{ - destroy_workqueue(iosm_wq); -} -module_exit(iosm_exit); diff --git a/drivers/soc/google/cpif/link_ctrlmsg_iosm.h b/drivers/soc/google/cpif/link_ctrlmsg_iosm.h deleted file mode 100644 index cb47ca9396e1..000000000000 --- a/drivers/soc/google/cpif/link_ctrlmsg_iosm.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2014 Samsung Electronics. - * - * Author: Chulhee Park - * - */ - -#ifndef LINK_CONTROL_MSG_IOSM_H -#define LINK_CONTROL_MSG_IOSM_H - -/* direction: CP -> AP */ -#define IOSM_C2A_MDM_READY 0x80 -#define IOSM_C2A_CONF_CH_RSP 0xA3 /* The answer of flow control msg */ -#define IOSM_C2A_STOP_TX_CH 0xB0 -#define IOSM_C2A_START_TX_CH 0xB1 -#define IOSM_C2A_ACK 0xE0 -#define IOSM_C2A_NACK 0xE1 - -/* direction: AP -> CP */ -#define IOSM_A2C_AP_READY 0x00 -#define IOSM_A2C_CONF_CH_REQ 0x22 /* flow control on/off */ -#define IOSM_A2C_OPEN_CH 0x24 -#define IOSM_A2C_CLOSE_CH 0x25 -#define IOSM_A2C_STOP_TX_CH 0x30 -#define IOSM_A2C_START_TX_CH 0x30 -#define IOSM_A2C_ACK 0x60 -#define IOSM_A2C_NACK 0x61 - -#define IOSM_TRANS_ID_MAX 255 -#define IOSM_MSG_AREA_SIZE (CTRL_RGN_SIZE / 2) -#define IOSM_MSG_TX_OFFSET CMD_RGN_OFFSET -#define IOSM_MSG_RX_OFFSET (CMD_RGN_OFFSET + IOSM_MSG_AREA_SIZE) -#define IOSM_MSG_DESC_OFFSET (CMD_RGN_OFFSET + CMD_RGN_SIZE) - -void tx_iosm_message(struct mem_link_device *mld, u8 id, u32 *args); -void iosm_event_work(struct work_struct *work); -void iosm_event_bh(struct mem_link_device *mld, u16 cmd); -#endif diff --git a/drivers/soc/google/cpif/link_device.c b/drivers/soc/google/cpif/link_device.c index e77f3a4b96d7..24c74a2c18b5 100644 --- a/drivers/soc/google/cpif/link_device.c +++ b/drivers/soc/google/cpif/link_device.c @@ -17,95 +17,31 @@ #include #include #include -#include -#include -#include #include -#if IS_ENABLED(CONFIG_PCI_EXYNOS) -#include -#endif #if IS_ENABLED(CONFIG_ECT) #include #endif +#include +#include #include +#include #include #include #include "modem_prj.h" #include "modem_utils.h" #include "link_device.h" #include "modem_dump.h" -#include "link_ctrlmsg_iosm.h" #include "modem_ctrl.h" #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) #include "s51xx_pcie.h" -#if IS_ENABLED(CONFIG_GS_S2MPU) -#include -#endif #endif +#if IS_ENABLED(CONFIG_EXYNOS_DIT) #include "dit.h" +#endif +#include "direct_dm.h" #define MIF_TX_QUOTA 64 -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) -#define CRC32_XINIT 0xFFFFFFFFL /* initial value */ -#define CRC32_XOROT 0xFFFFFFFFL /* final xor value */ - -static const unsigned long CRC32_TABLE[256] = { - 0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL, 0x076DC419L, - 0x706AF48FL, 0xE963A535L, 0x9E6495A3L, 0x0EDB8832L, 0x79DCB8A4L, - 0xE0D5E91EL, 0x97D2D988L, 0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, - 0x90BF1D91L, 0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL, - 0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L, 0x136C9856L, - 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL, 0x14015C4FL, 0x63066CD9L, - 0xFA0F3D63L, 0x8D080DF5L, 0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, - 0xA2677172L, 0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL, - 0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L, 0x32D86CE3L, - 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L, 0x26D930ACL, 0x51DE003AL, - 0xC8D75180L, 0xBFD06116L, 0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, - 0xB8BDA50FL, 0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L, - 0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL, 0x76DC4190L, - 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL, 0x71B18589L, 0x06B6B51FL, - 0x9FBFE4A5L, 0xE8B8D433L, 0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, - 0xE10E9818L, 0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L, - 0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL, 0x6C0695EDL, - 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L, 0x65B0D9C6L, 0x12B7E950L, - 0x8BBEB8EAL, 0xFCB9887CL, 0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, - 0xFBD44C65L, 0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L, - 0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL, 0x4369E96AL, - 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L, 0x44042D73L, 0x33031DE5L, - 0xAA0A4C5FL, 0xDD0D7CC9L, 0x5005713CL, 0x270241AAL, 0xBE0B1010L, - 0xC90C2086L, 0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL, - 0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L, 0x59B33D17L, - 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL, 0xEDB88320L, 0x9ABFB3B6L, - 0x03B6E20CL, 0x74B1D29AL, 0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, - 0x73DC1683L, 0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L, - 0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L, 0xF00F9344L, - 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL, 0xF762575DL, 0x806567CBL, - 0x196C3671L, 0x6E6B06E7L, 0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, - 0x67DD4ACCL, 0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L, - 0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L, 0xD1BB67F1L, - 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL, 0xD80D2BDAL, 0xAF0A1B4CL, - 0x36034AF6L, 0x41047A60L, 0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, - 0x4669BE79L, 0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L, - 0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL, 0xC5BA3BBEL, - 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L, 0xC2D7FFA7L, 0xB5D0CF31L, - 0x2CD99E8BL, 0x5BDEAE1DL, 0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, - 0x026D930AL, 0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L, - 0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L, 0x92D28E9BL, - 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L, 0x86D3D2D4L, 0xF1D4E242L, - 0x68DDB3F8L, 0x1FDA836EL, 0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, - 0x18B74777L, 0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL, - 0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L, 0xA00AE278L, - 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L, 0xA7672661L, 0xD06016F7L, - 0x4969474DL, 0x3E6E77DBL, 0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, - 0x37D83BF0L, 0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L, - 0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L, 0xBAD03605L, - 0xCDD70693L, 0x54DE5729L, 0x23D967BFL, 0xB3667A2EL, 0xC4614AB8L, - 0x5D681B02L, 0x2A6F2B94L, 0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, - 0x2D02EF8DL -}; -#endif - enum smc_error_flag { CP_NO_ERROR = 0, CP_NOT_ALIGN_64KB, @@ -140,70 +76,11 @@ enum smc_error_flag { static inline void start_tx_timer(struct mem_link_device *mld, struct hrtimer *timer); -#if IS_ENABLED(CONFIG_CP_SECURE_BOOT) -static char *smc_err_string[32] = { - "CP_NO_ERROR", - "CP_NOT_ALIGN_64KB", - "CP_MEM_TOO_BIG", - "CP_FLAG_OUT_RANGE", - "CP_WRONG_TZASC_REGION_NUM", - "CP_WRONG_BL_SIZE", - "CP_MEM_OUT_OF_RANGE", - "CP_NOT_ALIGN_16B", - "CP_MEM_IN_SECURE_DRAM", - "CP_ASP_ENABLE_FAIL", - "CP_ASP_DISABLE_FAIL", - "CP_NOT_WORKING", - "CP_ALREADY_WORKING", - "CP_ALREADY_DUMP_MODE", - "CP_NOT_VALID_MAGIC", - "CP_SHOULD_BE_DISABLE", - "CP_ALREADY_ENABLE_CPMEM_ON", - "CP_ALREADY_SET_WND", - "CP_FAIL_TO_SET_WND", - "CP_INVALID_CP_BASE", - "CP_CORRUPTED_CP_MEM_INFO", - "CP_WHILE_CHECKING_SIGN", - "CP_NOT_WHILE_CHECKING_SIGN", - "CP_IS_IN_INVALID_STATE", - "CP_IS_IN_INVALID_STATE2", - "CP_ERR_WHILE_CP_SIGN_CHECK", -}; +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) +#define SYSMMU_BAAW_SIZE 0x8000000 #endif /*============================================================================*/ -static inline bool ipc_active(struct mem_link_device *mld) -{ - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - - if (unlikely(!cp_online(mc))) { - mif_err("%s<->%s: %s.state %s != ONLINE <%ps>\n", - ld->name, mc->name, mc->name, mc_state(mc), CALLER); - return false; - } - - if (mld->dpram_magic) { - unsigned int magic = ioread32(mld->legacy_link_dev.magic); - unsigned int mem_access = ioread32(mld->legacy_link_dev.mem_access); - - if (magic != ld->magic_ipc || mem_access != 1) { - mif_err("%s<->%s: ERR! magic:0x%X access:%d <%ps>\n", - ld->name, mc->name, magic, mem_access, CALLER); - return false; - } - } - - if (atomic_read(&mld->forced_cp_crash)) { - mif_err("%s<->%s: ERR! forced_cp_crash:%d <%ps>\n", - ld->name, mc->name, atomic_read(&mld->forced_cp_crash), - CALLER); - return false; - } - - return true; -} - static inline void purge_txq(struct mem_link_device *mld) { struct link_device *ld = &mld->link_dev; @@ -223,7 +100,7 @@ static inline void purge_txq(struct mem_link_device *mld) /* Purge the skb_txq in every IPC device * (IPC_MAP_FMT, IPC_MAP_NORM_RAW, etc.) */ - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[i]; skb_queue_purge(dev->skb_txq); @@ -245,7 +122,7 @@ static void shmem_handle_cp_crash(struct mem_link_device *mld, tpmon_stop(); #endif - stop_net_ifaces(ld); + stop_net_ifaces(ld, 0); purge_txq(mld); if (cp_online(mc)) { @@ -271,29 +148,20 @@ static void shmem_handle_cp_crash(struct mem_link_device *mld, atomic_set(&mld->forced_cp_crash, 0); } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) static void handle_no_cp_crash_ack(struct timer_list *t) -#else -static void handle_no_cp_crash_ack(unsigned long arg) -#endif { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) struct mem_link_device *mld = from_timer(mld, t, crash_ack_timer); -#else - struct mem_link_device *mld = (struct mem_link_device *)arg; -#endif struct link_device *ld = &mld->link_dev; struct modem_ctl *mc = ld->mc; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) && IS_ENABLED(CONFIG_CP_WRESET_WA) if (ld->link_type == LINKDEV_PCIE) { - if (mif_gpio_get_value(&mc->s5100_gpio_phone_active, true) == 0) { - mif_info("Set s5100_cp_reset_required to FALSE\n"); + if (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], true) == 0) mc->s5100_cp_reset_required = false; - } else { - mif_info("Set s5100_cp_reset_required to TRUE\n"); + else mc->s5100_cp_reset_required = true; - } + + mif_info("Set s5100_cp_reset_required to %u\n", mc->s5100_cp_reset_required); } #endif @@ -306,11 +174,11 @@ static void handle_no_cp_crash_ack(unsigned long arg) } static void link_trigger_cp_crash(struct mem_link_device *mld, u32 crash_type, - char *crash_reason_string) + char *reason) { struct link_device *ld = &mld->link_dev; struct modem_ctl *mc = ld->mc; - char string[CP_CRASH_INFO_SIZE]; + bool reason_done = false; if (!cp_online(mc) && !cp_booting(mc)) { mif_err("%s: %s.state %s != ONLINE <%ps>\n", @@ -329,58 +197,47 @@ static void link_trigger_cp_crash(struct mem_link_device *mld, u32 crash_type, mif_stop_logging(); - memset(string, 0, CP_CRASH_INFO_SIZE); - if (crash_reason_string) - strcpy(string, crash_reason_string); - memset(ld->crash_reason.string, 0, CP_CRASH_INFO_SIZE); - - if (ld->crash_reason.type != crash_type) - ld->crash_reason.type = crash_type; - switch (ld->protocol) { case PROTOCOL_SIPC: - switch (crash_type) { - case CRASH_REASON_USER: - case CRASH_REASON_MIF_TX_ERR: - case CRASH_REASON_MIF_RIL_BAD_CH: - case CRASH_REASON_MIF_RX_BAD_DATA: - case CRASH_REASON_MIF_FORCED: - case CRASH_REASON_CLD: - if (strlen(string)) - strlcat(ld->crash_reason.string, string, - CP_CRASH_INFO_SIZE); - break; - - default: - break; - } - break; - case PROTOCOL_SIT: - switch (crash_type) { - case CRASH_REASON_MIF_TX_ERR: - case CRASH_REASON_MIF_RIL_BAD_CH: - case CRASH_REASON_MIF_RX_BAD_DATA: - case CRASH_REASON_MIF_FORCED: - case CRASH_REASON_RIL_TRIGGER_CP_CRASH: - if (strlen(string)) - strlcat(ld->crash_reason.string, string, - CP_CRASH_INFO_SIZE); - break; - - default: - break; - } break; - default: mif_err("ERR - unknown protocol\n"); + goto set_type; + } + + switch (crash_type) { + case CRASH_REASON_MIF_TX_ERR: + case CRASH_REASON_MIF_RIL_BAD_CH: + case CRASH_REASON_MIF_RX_BAD_DATA: + case CRASH_REASON_MIF_FORCED: break; + case CRASH_REASON_USER: + case CRASH_REASON_CLD: + if (ld->protocol != PROTOCOL_SIPC) + goto set_type; + break; + case CRASH_REASON_RIL_TRIGGER_CP_CRASH: + if (ld->protocol != PROTOCOL_SIT) + goto set_type; + reason_done = true; + break; + default: + goto set_type; + } + + if (!reason_done && reason && reason[0] != '\0') { + strlcpy(ld->crash_reason.string, reason, CP_CRASH_INFO_SIZE); + reason_done = true; } - mif_info("CP Crash type:%d string:%s\n", crash_type, - ld->crash_reason.string); - stop_net_ifaces(ld); +set_type: + if (!reason_done) + memset(ld->crash_reason.string, 0, CP_CRASH_INFO_SIZE); + + ld->crash_reason.type = crash_type; + + stop_net_ifaces(ld, 0); if (mld->debug_info) mld->debug_info(); @@ -390,11 +247,7 @@ static void link_trigger_cp_crash(struct mem_link_device *mld, u32 crash_type, * handle_no_cp_crash_ack() will be executed. */ mif_add_timer(&mld->crash_ack_timer, FORCE_CRASH_ACK_TIMEOUT, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) handle_no_cp_crash_ack); -#else - handle_no_cp_crash_ack, (unsigned long)mld); -#endif update_ctrl_msg(&mld->ap2cp_united_status, ld->crash_reason.type, mc->sbi_crash_type_mask, mc->sbi_crash_type_pos); @@ -402,13 +255,7 @@ static void link_trigger_cp_crash(struct mem_link_device *mld, u32 crash_type, #if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) if (ld->interrupt_types == INTERRUPT_MAILBOX) { /* Send CRASH_EXIT command to a CP */ - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); - - send_ipc_irq(mld, cmd2int(CMD_CRASH_EXIT)); - - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); + send_ipc_irq_debug(mld, cmd2int(CMD_CRASH_EXIT)); } #endif @@ -470,17 +317,24 @@ static void write_clk_table_to_shmem(struct mem_link_device *mld) clk_tb = (struct clock_table *)mld->clk_table; - strcpy(clk_tb->parser_version, "CT0"); + strcpy(clk_tb->parser_version, "CT1"); clk_tb->total_table_count = mld->total_freq_table_count; - strcpy(clk_tb->table_info[0].table_name, "MIF"); + memcpy(clk_tb->table_info[0].table_name, "MIF\0", 4); clk_tb->table_info[0].table_count = mld->mif_table.num_of_table; - strcpy(clk_tb->table_info[1].table_name, "CP"); - clk_tb->table_info[1].table_count = mld->cp_table.num_of_table; + memcpy(clk_tb->table_info[1].table_name, "CP_C", 4); + clk_tb->table_info[1].table_count = mld->cp_cpu_table.num_of_table; + + memcpy(clk_tb->table_info[2].table_name, "CP\0", 4); + clk_tb->table_info[2].table_count = mld->cp_table.num_of_table; + + memcpy(clk_tb->table_info[3].table_name, "CP_E", 4); + clk_tb->table_info[3].table_count = mld->cp_em_table.num_of_table; + + memcpy(clk_tb->table_info[4].table_name, "CP_M", 4); + clk_tb->table_info[4].table_count = mld->cp_mcw_table.num_of_table; - strcpy(clk_tb->table_info[2].table_name, "MDM"); - clk_tb->table_info[2].table_count = mld->modem_table.num_of_table; clk_data = (u32 *)&(clk_tb->table_info[clk_tb->total_table_count]); @@ -490,15 +344,27 @@ static void write_clk_table_to_shmem(struct mem_link_device *mld) clk_data++; } + /* CP_CPU */ + for (i = 0; i < mld->cp_cpu_table.num_of_table; i++) { + *clk_data = mld->cp_cpu_table.freq[i]; + clk_data++; + } + /* CP */ for (i = 0; i < mld->cp_table.num_of_table; i++) { *clk_data = mld->cp_table.freq[i]; clk_data++; } - /* MODEM */ - for (i = 0; i < mld->modem_table.num_of_table; i++) { - *clk_data = mld->modem_table.freq[i]; + /* CP_EM */ + for (i = 0; i < mld->cp_em_table.num_of_table; i++) { + *clk_data = mld->cp_em_table.freq[i]; + clk_data++; + } + + /* CP_MCW */ + for (i = 0; i < mld->cp_mcw_table.num_of_table; i++) { + *clk_data = mld->cp_mcw_table.freq[i]; clk_data++; } @@ -523,34 +389,66 @@ static void write_clk_table_to_shmem(struct mem_link_device *mld) } } -static void write_ap_capabilities(struct mem_link_device *mld) +static void set_ap_capabilities(struct mem_link_device *mld) { + int part; + #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) - mld->ap_capability_0 = mld->ap_capability_0 | AP_CAP_PKTPROC_UL; + cpif_set_bit(mld->ap_capability[0], AP_CAP_0_PKTPROC_UL_BIT); #endif #if IS_ENABLED(CONFIG_CH_EXTENSION) - mld->ap_capability_0 = mld->ap_capability_0 | AP_CAP_CH_EXTENSION; + cpif_set_bit(mld->ap_capability[0], AP_CAP_0_CH_EXTENSION_BIT); #endif - iowrite32(mld->ap_capability_0, mld->ap_capability_0_offset); - iowrite32(mld->ap_capability_1, mld->ap_capability_1_offset); + if (mld->pktproc_use_36bit_addr) + cpif_set_bit(mld->ap_capability[0], AP_CAP_0_PKTPROC_36BIT_ADDR_BIT); + + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + iowrite32(mld->ap_capability[part], mld->ap_capability_offset[part]); - mif_info("ap_capability_0:0x%08x ap_capability_1:0x%08x\n", - mld->ap_capability_0, mld->ap_capability_1); + mif_info("capability part:%d AP:0x%08x\n", part, mld->ap_capability[part]); + } } -static void init_enabled_capabilities(struct mem_link_device *mld) +static int init_ap_capabilities(struct mem_link_device *mld, int part) { -#if IS_ENABLED(CONFIG_CP_PKTPROC_UL) - int err; + int cap; + int ret = 0; - if (mld->ap_capability_0 & AP_CAP_PKTPROC_UL) { - err = pktproc_init_ul(&mld->pktproc_ul); - if (err < 0) { - mif_err("pktproc_init_ul() error %d\n", err); - return; + if (!mld->ap_capability[part]) + goto out; + + for (cap = 0; cap < AP_CP_CAP_BIT_MAX; cap++) { + if (!cpif_check_bit(mld->ap_capability[part], cap)) + continue; + + /* should handle the matched capability */ + ret = -EINVAL; + + if (part == 0) { + switch (cap) { + case AP_CAP_0_PKTPROC_UL_BIT: +#if IS_ENABLED(CONFIG_CP_PKTPROC_UL) + ret = pktproc_init_ul(&mld->pktproc_ul); + if (ret) + mif_err("pktproc_init_ul() ret:%d\n", ret); +#endif + break; + case AP_CAP_0_CH_EXTENSION_BIT: + case AP_CAP_0_PKTPROC_36BIT_ADDR_BIT: + ret = 0; + break; + default: + mif_err("unsupported capability part:%d cap:%d\n", part, cap); + break; + } } + + if (ret) + break; } -#endif + +out: + return ret; } static void cmd_init_start_handler(struct mem_link_device *mld) @@ -559,9 +457,9 @@ static void cmd_init_start_handler(struct mem_link_device *mld) struct modem_ctl *mc = ld->mc; int err; - mif_err("%s: INIT_START <- %s (%s.state:%s cp_boot_done:%d)\n", + mif_info("%s: INIT_START <- %s (%s.state:%s init_end_cnt:%d)\n", ld->name, mc->name, mc->name, mc_state(mc), - atomic_read(&mld->cp_boot_done)); + atomic_read(&mld->init_end_cnt)); #if IS_ENABLED(CONFIG_CP_PKTPROC) err = pktproc_init(&mld->pktproc); @@ -579,12 +477,22 @@ static void cmd_init_start_handler(struct mem_link_device *mld) } #endif +#if IS_ENABLED(CONFIG_CPIF_DIRECT_DM) + err = direct_dm_init(ld); + if (err < 0) { + mif_err("direct_dm_init() error %d\n", err); + return; + } +#endif + #if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) tpmon_init(); #endif + toe_dev_init(mld); + if (ld->capability_check) - write_ap_capabilities(mld); + set_ap_capabilities(mld); if (!ld->sbd_ipc) { mif_err("%s: LINK_ATTR_SBD_IPC is NOT set\n", ld->name); @@ -607,61 +515,44 @@ static void cmd_init_start_handler(struct mem_link_device *mld) init_exit: send_ipc_irq(mld, cmd2int(CMD_PIF_INIT_DONE)); - mif_err("%s: PIF_INIT_DONE -> %s\n", ld->name, mc->name); + mif_info("%s: PIF_INIT_DONE -> %s\n", ld->name, mc->name); } +#define PHONE_START_IRQ_MARGIN 4 +#define PHONE_START_ACK_MARGIN 5 static void cmd_phone_start_handler(struct mem_link_device *mld) { + static int phone_start_count; struct link_device *ld = &mld->link_dev; struct modem_ctl *mc = ld->mc; unsigned long flags; int err; - static int phone_start_count; - mif_info_limited("%s: PHONE_START <- %s (%s.state:%s cp_boot_done:%d)\n", - ld->name, mc->name, mc->name, mc_state(mc), - atomic_read(&mld->cp_boot_done)); + mif_info_limited("%s: PHONE_START <- %s (%s.state:%s init_end_cnt:%d)\n", + ld->name, mc->name, mc->name, mc_state(mc), + atomic_read(&mld->init_end_cnt)); if (mld->state == LINK_STATE_OFFLINE) phone_start_count = 0; - if (atomic_read(&mld->cp_boot_done)) { + if (atomic_read(&mld->init_end_cnt)) { mif_err_limited("Abnormal PHONE_START from CP\n"); - if (phone_start_count < 100) { - if (phone_start_count++ > 3) { - phone_start_count = 101; -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - send_ipc_irq(mld, - cmd2int(phone_start_count - 100)); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - return; - } - } else { - if (phone_start_count++ < 105) { - mif_err("%s: CMD(0x%x) -> %s\n", ld->name, - cmd2int(phone_start_count - 100), - mc->name); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - send_ipc_irq(mld, cmd2int(phone_start_count - 100)); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - } else { + if (++phone_start_count > PHONE_START_IRQ_MARGIN) { + int ack_count = phone_start_count - + PHONE_START_IRQ_MARGIN; + + if (ack_count > PHONE_START_ACK_MARGIN) { link_trigger_cp_crash(mld, - CRASH_REASON_CP_RSV_0, - "Abnormal CP_START from CP"); + CRASH_REASON_CP_RSV_0, + "Abnormal PHONE_START from CP"); + return; } + + mif_err("%s: CMD(0x%x) -> %s\n", ld->name, + cmd2int(ack_count), mc->name); + send_ipc_irq_debug(mld, cmd2int(ack_count)); + return; } } @@ -676,44 +567,37 @@ static void cmd_phone_start_handler(struct mem_link_device *mld) */ if (rild_ready(ld)) { mif_info("%s: INIT_END -> %s\n", ld->name, mc->name); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - send_ipc_irq(mld, cmd2int(CMD_INIT_END)); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - atomic_set(&mld->cp_boot_done, 1); + atomic_inc(&mld->init_end_cnt); + send_ipc_irq_debug(mld, cmd2int(CMD_INIT_END)); } goto exit; } if (ld->capability_check) { - /* get cp_capability */ - mld->cp_capability_0 = ioread32(mld->cp_capability_0_offset); - mld->cp_capability_1 = ioread32(mld->cp_capability_1_offset); - - if ((mld->ap_capability_0 ^ mld->cp_capability_0) & mld->ap_capability_0) { - /* if at least one feature is owned by AP only, crash CP */ - mif_err("AP capability 0: 0x%08x CP capability 0: 0x%08x\n", - mld->ap_capability_0, mld->cp_capability_0); - goto capability_fail; - } - if ((mld->ap_capability_1 ^ mld->cp_capability_1) & mld->ap_capability_1) { - /* if at least one feature is owned by AP only, crash CP */ - mif_err("AP capability 1: 0x%08x CP capability 1: 0x%08x\n", - mld->ap_capability_1, mld->cp_capability_1); - goto capability_fail; - } + int part; + + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + /* get cp_capability */ + mld->cp_capability[part] = ioread32(mld->cp_capability_offset[part]); + + if ((mld->ap_capability[part] ^ mld->cp_capability[part]) & + mld->ap_capability[part]) { + /* if at least one feature is owned by AP only, crash CP */ + mif_err("ERR! capability part:%d AP:0x%08x CP:0x%08x\n", + part, mld->ap_capability[part], mld->cp_capability[part]); + goto capability_failed; + } - mif_info("ap_capability_0:0x%08x ap_capability_1:0x%08x\n", - mld->ap_capability_0, mld->ap_capability_1); - mif_info("cp_capability_0:0x%08x cp_capability_1:0x%08x\n", - mld->cp_capability_0, mld->cp_capability_1); + mif_info("capability part:%d AP:0x%08x CP:0x%08x\n", + part, mld->ap_capability[part], mld->cp_capability[part]); - init_enabled_capabilities(mld); + err = init_ap_capabilities(mld, part); + if (err) { + mif_err("%s: init_ap_capabilities part:%d fail(%d)\n", + ld->name, part, err); + goto exit; + } + } } err = init_legacy_link(&mld->legacy_link_dev); @@ -721,20 +605,14 @@ static void cmd_phone_start_handler(struct mem_link_device *mld) mif_err("%s: init_legacy_link fail(%d)\n", ld->name, err); goto exit; } + atomic_set(&ld->netif_stopped, 0); + ld->tx_flowctrl_mask = 0; if (rild_ready(ld)) { mif_info("%s: INIT_END -> %s\n", ld->name, mc->name); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - send_ipc_irq(mld, cmd2int(CMD_INIT_END)); -#if IS_ENABLED(CONFIG_MCU_IPC) - if (mld->ap2cp_msg.type == MAILBOX_SR) - cp_mbox_dump_sr(); -#endif - atomic_set(&mld->cp_boot_done, 1); + atomic_inc(&mld->init_end_cnt); + send_ipc_irq_debug(mld, cmd2int(CMD_INIT_END)); } #if IS_ENABLED(CONFIG_MCU_IPC) @@ -759,10 +637,9 @@ static void cmd_phone_start_handler(struct mem_link_device *mld) spin_unlock_irqrestore(&mld->state_lock, flags); return; -capability_fail: +capability_failed: spin_unlock_irqrestore(&mld->state_lock, flags); - link_trigger_cp_crash(mld, CRASH_REASON_MIF_FORCED, - "CP lacks capability\n"); + link_trigger_cp_crash(mld, CRASH_REASON_MIF_FORCED, "CP lacks capability\n"); return; } @@ -805,15 +682,14 @@ static void cmd_crash_exit_handler(struct mem_link_device *mld) else mif_err("%s<-%s: ERR! CP_CRASH_EXIT\n", ld->name, mc->name); -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) && IS_ENABLED(CONFIG_CP_WRESET_WA) if (ld->link_type == LINKDEV_PCIE) { - if (mif_gpio_get_value(&mc->s5100_gpio_phone_active, true) == 0) { - mif_info("Set s5100_cp_reset_required to FALSE\n"); + if (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], true) == 0) mc->s5100_cp_reset_required = false; - } else { - mif_info("Set s5100_cp_reset_required to TRUE\n"); + else mc->s5100_cp_reset_required = true; - } + + mif_info("Set s5100_cp_reset_required to %u\n", mc->s5100_cp_reset_required); } #endif @@ -959,23 +835,14 @@ static enum hrtimer_restart tx_timer_func(struct hrtimer *timer) if (unlikely(!ipc_active(mld))) goto exit; - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[i]; int ret; - if (unlikely(under_tx_flow_ctrl(mld, dev))) { - ret = check_tx_flow_ctrl(mld, dev); - if (ret < 0) { - if (ret == -EBUSY || ret == -ETIME) { - need_schedule = true; - continue; - } else { - link_trigger_cp_crash(mld, CRASH_REASON_MIF_TX_ERR, - "check_tx_flow_ctrl error"); - need_schedule = false; - goto exit; - } - } + ret = txq_check_busy(mld, dev); + if (ret) { + need_schedule = true; + continue; } ret = tx_frames_to_dev(mld, dev); @@ -1009,7 +876,7 @@ static enum hrtimer_restart tx_timer_func(struct hrtimer *timer) exit: if (need_schedule) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + ktime_t ktime = ktime_set(0, mld->tx_period_ns); hrtimer_start(timer, ktime, HRTIMER_MODE_REL); } @@ -1066,7 +933,7 @@ static int tx_func(struct mem_link_device *mld, struct hrtimer *timer, exit: if (need_schedule) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + ktime_t ktime = ktime_set(0, mld->tx_period_ns); hrtimer_start(timer, ktime, HRTIMER_MODE_REL); @@ -1091,7 +958,7 @@ static inline void start_tx_timer(struct mem_link_device *mld, spin_lock_irqsave(&mc->tx_timer_lock, flags); if (!hrtimer_is_queued(timer)) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + ktime_t ktime = ktime_set(0, mld->tx_period_ns); hrtimer_start(timer, ktime, HRTIMER_MODE_REL); } @@ -1131,61 +998,6 @@ static inline void shmem_stop_timers(struct mem_link_device *mld) cancel_tx_timer(mld, &mld->tx_timer); } -static inline void start_datalloc_timer(struct mem_link_device *mld, - struct hrtimer *timer) -{ - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - unsigned long flags; - - spin_lock_irqsave(&mc->lock, flags); - - if (unlikely(cp_offline(mc))) - goto exit; - - if (!hrtimer_is_queued(timer)) { - ktime_t ktime = ktime_set(0, ms2ns(DATALLOC_PERIOD_MS)); - - hrtimer_start(timer, ktime, HRTIMER_MODE_REL); - } - -exit: - spin_unlock_irqrestore(&mc->lock, flags); -} - -static inline void __cancel_datalloc_timer(struct mem_link_device *mld, - struct hrtimer *timer) -{ - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - unsigned long flags; - - spin_lock_irqsave(&mc->lock, flags); - - if (hrtimer_active(timer)) - hrtimer_cancel(timer); - - spin_unlock_irqrestore(&mc->lock, flags); -} - -static inline void cancel_datalloc_timer(struct mem_link_device *mld) -{ - struct sbd_link_device *sl = &mld->sbd_link_dev; - struct sbd_ipc_device *ipc_dev = sl->ipc_dev; - int i; - - for (i = 0; i < sl->num_channels; i++) { - struct sbd_ring_buffer *rb = &ipc_dev[i].rb[DL]; - - if (rb->zerocopy) { - struct zerocopy_adaptor *zdptr = rb->zdptr; - - __cancel_datalloc_timer(mld, &zdptr->datalloc_timer); - } - } - -} - static int tx_frames_to_rb(struct sbd_ring_buffer *rb) { struct sk_buff_head *skb_txq = &rb->skb_q; @@ -1239,20 +1051,10 @@ static enum hrtimer_restart sbd_tx_timer_func(struct hrtimer *timer) struct sbd_ring_buffer *rb = sbd_id2rb(sl, i, TX); int ret; - if (unlikely(sbd_under_tx_flow_ctrl(rb))) { - ret = sbd_check_tx_flow_ctrl(rb); - if (ret < 0) { - if (ret == -EBUSY || ret == -ETIME) { - need_schedule = true; - continue; - } else { - link_trigger_cp_crash(mld, - CRASH_REASON_MIF_TX_ERR, - "check_sbd_tx_flow_ctrl error"); - need_schedule = false; - goto exit; - } - } + ret = sbd_txq_check_busy(rb); + if (ret) { + need_schedule = true; + continue; } ret = tx_frames_to_rb(rb); @@ -1290,7 +1092,7 @@ static enum hrtimer_restart sbd_tx_timer_func(struct hrtimer *timer) exit: if (need_schedule) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + ktime_t ktime = ktime_set(0, mld->tx_period_ns); hrtimer_start(timer, ktime, HRTIMER_MODE_REL); } @@ -1346,7 +1148,7 @@ static int sbd_tx_func(struct mem_link_device *mld, struct hrtimer *timer, exit: if (need_schedule) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + ktime_t ktime = ktime_set(0, mld->tx_period_ns); hrtimer_start(timer, ktime, HRTIMER_MODE_REL); return -1; @@ -1354,39 +1156,6 @@ static int sbd_tx_func(struct mem_link_device *mld, struct hrtimer *timer, return 1; } -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) -enum hrtimer_restart datalloc_timer_func(struct hrtimer *timer) -{ - struct zerocopy_adaptor *zdptr = - container_of(timer, struct zerocopy_adaptor, datalloc_timer); - struct sbd_ring_buffer *rb = zdptr->rb; - struct link_device *ld = rb->ld; - struct mem_link_device *mld = ld_to_mem_link_device(ld); - struct modem_ctl *mc = ld->mc; - bool need_schedule = false; - unsigned long flags; - - spin_lock_irqsave(&mc->lock, flags); - if (unlikely(!ipc_active(mld))) { - spin_unlock_irqrestore(&mc->lock, flags); - goto exit; - } - spin_unlock_irqrestore(&mc->lock, flags); - - if (-ENOMEM == allocate_data_in_advance(zdptr)) - need_schedule = true; - - if (need_schedule) { - ktime_t ktime = ktime_set(0, ms2ns(DATALLOC_PERIOD_MS)); - - hrtimer_start(timer, ktime, HRTIMER_MODE_REL); - } -exit: - - return HRTIMER_NORESTART; -} -#endif - #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) static enum hrtimer_restart pktproc_tx_timer_func(struct hrtimer *timer) { @@ -1395,36 +1164,32 @@ static enum hrtimer_restart pktproc_tx_timer_func(struct hrtimer *timer) struct modem_ctl *mc = mld->link_dev.mc; bool need_schedule = false; bool need_irq = false; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) bool need_dit = false; +#endif unsigned long flags; unsigned int count; int ret, i; - spin_lock_irqsave(&mc->lock, flags); - if (unlikely(!ipc_active(mld))) { - spin_unlock_irqrestore(&mc->lock, flags); - return HRTIMER_NORESTART; - } - spin_unlock_irqrestore(&mc->lock, flags); - for (i = 0; i < ppa_ul->num_queue; i++) { struct pktproc_queue_ul *q = ppa_ul->q[i]; - if (unlikely(pktproc_under_ul_flow_ctrl(q))) { - ret = pktproc_check_ul_flow_ctrl(q); - if (ret < 0) { - need_schedule = true; - continue; - } + ret = pktproc_ul_q_check_busy(q); + if (ret) { + need_schedule = true; + continue; } do { +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (dit_check_dir_use_queue(DIT_DIR_TX, q->q_idx)) { if (circ_empty(q->done_ptr, q->q_info->fore_ptr)) break; need_dit = true; - } else { + } else +#endif + { count = circ_get_usage(q->q_info->num_desc, q->done_ptr, q->q_info->fore_ptr); if (count == 0) @@ -1437,16 +1202,27 @@ static enum hrtimer_restart pktproc_tx_timer_func(struct hrtimer *timer) } while (0); } +#if IS_ENABLED(CONFIG_EXYNOS_DIT) /* irq will be raised after dit_kick() */ - if (need_dit) + if (need_dit) { dit_kick(DIT_DIR_TX, false); - else if (need_irq) - send_ipc_irq(mld, mask2int(MASK_SEND_DATA)); + } else +#endif + if (need_irq) { + spin_lock_irqsave(&mc->lock, flags); + if (ipc_active(mld)) + send_ipc_irq(mld, mask2int(MASK_SEND_DATA)); + spin_unlock_irqrestore(&mc->lock, flags); + } if (need_schedule) { - ktime_t ktime = ktime_set(0, mld->tx_period_ms * NSEC_PER_MSEC); + spin_lock_irqsave(&mc->tx_timer_lock, flags); + if (!hrtimer_is_queued(timer)) { + ktime_t ktime = ktime_set(0, mld->tx_period_ns); - hrtimer_start(timer, ktime, HRTIMER_MODE_REL); + hrtimer_start(timer, ktime, HRTIMER_MODE_REL); + } + spin_unlock_irqrestore(&mc->tx_timer_lock, flags); } return HRTIMER_NORESTART; @@ -1455,26 +1231,42 @@ static enum hrtimer_restart pktproc_tx_timer_func(struct hrtimer *timer) static int xmit_ipc_to_pktproc(struct mem_link_device *mld, struct sk_buff *skb) { struct pktproc_adaptor_ul *ppa_ul = &mld->pktproc_ul; - struct pktproc_queue_ul *q; + // Set the ul queue to high priority by default. + struct pktproc_queue_ul *q = ppa_ul->q[PKTPROC_UL_HIPRIO]; int len; int ret = -EBUSY; unsigned long flags; - if (skb->queue_mapping == 1) - q = ppa_ul->q[PKTPROC_HIPRIO_UL]; - else /* normal ul queue */ - q = ppa_ul->q[PKTPROC_NORM_UL]; - if (ppa_ul->padding_required) len = skb->len + CP_PADDING; else len = skb->len; - if (len > ppa_ul->max_packet_size) { - mif_err_limited("ERR! PKTPROC UL QUEUE %d\n" - "skb len %d too large\n", - q->q_idx, len); - return -EINVAL; + /* Set ul queue + * 1) The queue is high priority(PKTPROC_UL_HIPRIO) by default. + * 2) If there is only one UL queue, set queue to PKTPROC_UL_QUEUE_0. + * This check need to enable CONFIG_CP_PKTPROC_UL_SINGLE_QUEUE. + * 3) If queue_mapping of skb is not 1(normal priority), set queue to + * PKTPROC_UL_NORM. + * 4) If queue_mapping of skb is 1(high priority), and skb length larger then + * the maximum packet size of high priority queue, set queue to + * PKTPROC_UL_NORM. + * 5) Check again if the skb length exceeds the maximum size of + * PKTPROC_UL_NORM queue. + */ +#if IS_ENABLED(CONFIG_CP_PKTPROC_UL_SINGLE_QUEUE) + if (ppa_ul->num_queue == 1) + q = ppa_ul->q[PKTPROC_UL_QUEUE_0]; + else +#endif + if (skb->queue_mapping != 1 || + (skb->queue_mapping == 1 && len > q->max_packet_size)) { + q = ppa_ul->q[PKTPROC_UL_NORM]; + if (len > q->max_packet_size) { + mif_err_limited("ERR!PKTPROC UL QUEUE:%d skb len:%d too large (max:%u)\n", + q->q_idx, len, q->max_packet_size); + return -EINVAL; + } } if (spin_trylock_irqsave(&q->lock, flags)) { @@ -1493,11 +1285,9 @@ static int xmit_ipc_to_pktproc(struct mem_link_device *mld, struct sk_buff *skb) goto exit; } -#ifdef DEBUG_MODEM_IF_LINK_TX - mif_pkt(skbpriv(skb)->sipc_ch, "LNK-TX", skb); -#endif - +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (!dit_check_dir_use_queue(DIT_DIR_TX, q->q_idx)) +#endif dev_consume_skb_any(skb); exit: @@ -1647,23 +1437,24 @@ static int xmit_to_cp(struct mem_link_device *mld, struct io_device *iod, else return -ENODEV; } else { - if (ld->is_fmt_ch(ch) || (ld->is_wfs0_ch != NULL && ld->is_wfs0_ch(ch))) + if (ld->is_fmt_ch(ch) || ld->is_oem_ch(ch) || + (ld->is_wfs0_ch != NULL && ld->is_wfs0_ch(ch))) return xmit_ipc_to_dev(mld, ch, skb, IPC_MAP_FMT); + #if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - return xmit_ipc_to_dev(mld, ch, skb, - (skb->queue_mapping == 1) ? IPC_MAP_HPRIO_RAW : IPC_MAP_NORM_RAW); -#else - return xmit_ipc_to_dev(mld, ch, skb, IPC_MAP_NORM_RAW); + if (skb->queue_mapping == 1) + return xmit_ipc_to_dev(mld, ch, skb, IPC_MAP_HPRIO_RAW); #endif + return xmit_ipc_to_dev(mld, ch, skb, IPC_MAP_NORM_RAW); } } /*============================================================================*/ -static void pass_skb_to_demux(struct mem_link_device *mld, struct sk_buff *skb) +static int pass_skb_to_demux(struct mem_link_device *mld, struct sk_buff *skb) { struct link_device *ld = &mld->link_dev; struct io_device *iod = skbpriv(skb)->iod; - int ret; + int ret = 0; u8 ch = skbpriv(skb)->sipc_ch; if (unlikely(!iod)) { @@ -1671,7 +1462,7 @@ static void pass_skb_to_demux(struct mem_link_device *mld, struct sk_buff *skb) dev_kfree_skb_any(skb); link_trigger_cp_crash(mld, CRASH_REASON_MIF_RIL_BAD_CH, "ERR! No IOD for CH.XX"); - return; + return -EACCES; } #ifdef DEBUG_MODEM_IF_LINK_RX @@ -1686,6 +1477,8 @@ static void pass_skb_to_demux(struct mem_link_device *mld, struct sk_buff *skb) ld->name, iod->name, mc->name, iod->name, ret); dev_kfree_skb_any(skb); } + + return ret; } static int pass_skb_to_net(struct mem_link_device *mld, struct sk_buff *skb) @@ -1693,15 +1486,8 @@ static int pass_skb_to_net(struct mem_link_device *mld, struct sk_buff *skb) struct link_device *ld = &mld->link_dev; struct skbuff_private *priv; struct io_device *iod; - struct modem_ctl *mc = ld->mc; int ret = 0; - if (unlikely(!cp_online(mc))) { - mif_err_limited("ERR! CP not online!, skb:%pK\n", skb); - dev_kfree_skb_any(skb); - return -EACCES; - } - priv = skbpriv(skb); if (unlikely(!priv)) { mif_err("%s: ERR! No PRIV in skb@%pK\n", ld->name, skb); @@ -1736,64 +1522,7 @@ static int pass_skb_to_net(struct mem_link_device *mld, struct sk_buff *skb) return ret; } -#define FREE_RB_BUF_COUNT 200 -static int rx_net_frames_from_zerocopy_adaptor(struct sbd_ring_buffer *rb, - int budget, int *work_done) -{ - int rcvd = 0; - struct link_device *ld = rb->ld; - struct mem_link_device *mld = ld_to_mem_link_device(ld); - struct zerocopy_adaptor *zdptr = rb->zdptr; - unsigned int num_frames; - int use_memcpy = 0; - int ret = 0; - - num_frames = min_t(unsigned int, rb_usage(rb), budget); - - ld->mif_buff_mng->enable_sw_zerocopy ? - (mld->force_use_memcpy = 0) : (mld->force_use_memcpy = 1); - - if (mld->force_use_memcpy || (num_frames > ld->mif_buff_mng->free_cell_count) - || (circ_get_space(zdptr->len, *(zdptr->rp), *(zdptr->wp)) < FREE_RB_BUF_COUNT)) { - use_memcpy = 1; - mld->memcpy_packet_count++; - } else { - use_memcpy = 0; - mld->zeromemcpy_packet_count++; - } - - while (rcvd < num_frames) { - struct sk_buff *skb; - - skb = sbd_pio_rx_zerocopy_adaptor(rb, use_memcpy); - if (!skb) - break; - - /* The $rcvd must be accumulated here, because $skb can be freed - * in pass_skb_to_net(). - */ - rcvd++; - - ret = pass_skb_to_net(mld, skb); - if (ret < 0) - break; - } - - if (ret != -EBUSY && rcvd < num_frames) { - struct io_device *iod = rb->iod; - struct link_device *ld = rb->ld; - struct modem_ctl *mc = ld->mc; - - mif_err_limited("%s: %s<-%s: WARN! rcvd %d < num_frames %d\n", - ld->name, iod->name, mc->name, rcvd, num_frames); - } - - *work_done = rcvd; - allocate_data_in_advance(zdptr); - - return ret; -} - +#if IS_ENABLED(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) static int rx_net_frames_from_rb(struct sbd_ring_buffer *rb, int budget, int *work_done) { @@ -1806,11 +1535,11 @@ static int rx_net_frames_from_rb(struct sbd_ring_buffer *rb, int budget, num_frames = min_t(unsigned int, rb_usage(rb), budget); while (rcvd < num_frames) { - struct sk_buff *skb; + struct sk_buff *skb = NULL; - skb = sbd_pio_rx(rb); - if (!skb) - return -ENOMEM; + ret = sbd_pio_rx(rb, &skb); + if (unlikely(ret)) + return ret; /* The $rcvd must be accumulated here, because $skb can be freed * in pass_skb_to_net(). @@ -1845,13 +1574,14 @@ static int rx_ipc_frames_from_rb(struct sbd_ring_buffer *rb) unsigned int in = *rb->wp; unsigned int out = *rb->rp; unsigned int num_frames = circ_get_usage(qlen, in, out); + int ret = 0; while (rcvd < num_frames) { - struct sk_buff *skb; + struct sk_buff *skb = NULL; - skb = sbd_pio_rx(rb); - if (!skb) - return -ENOMEM; + ret = sbd_pio_rx(rb, &skb); + if (unlikely(ret)) + return ret; /* The $rcvd must be accumulated here, because $skb can be freed * in pass_skb_to_demux(). @@ -1893,10 +1623,7 @@ static int sbd_ipc_rx_func_napi(struct link_device *ld, struct io_device *iod, int rcvd = 0; int ret; - if (rb->zerocopy) - ret = rx_net_frames_from_zerocopy_adaptor(rb, budget, &rcvd); - else - ret = rx_net_frames_from_rb(rb, budget, &rcvd); + ret = rx_net_frames_from_rb(rb, budget, &rcvd); if (IS_ERR_VALUE((unsigned long)ret) && (ret != -EBUSY)) mif_err_limited("RX error (%d)\n", ret); @@ -1904,11 +1631,13 @@ static int sbd_ipc_rx_func_napi(struct link_device *ld, struct io_device *iod, *work_done = rcvd; return ret; } +#endif //CONFIG_LINK_DEVICE_WITH_SBD_ARCH static int legacy_ipc_rx_func_napi(struct mem_link_device *mld, struct legacy_ipc_device *dev, int budget, int *work_done) { struct link_device *ld = &mld->link_dev; + struct modem_data *modem = ld->mdm_data; unsigned int qsize = get_rxq_buff_size(dev); unsigned int in = get_rxq_head(dev); unsigned int out = get_rxq_tail(dev); @@ -1919,8 +1648,7 @@ static int legacy_ipc_rx_func_napi(struct mem_link_device *mld, struct legacy_ip if (unlikely(circ_empty(in, out))) return 0; -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - if (dev->id == IPC_MAP_NORM_RAW) { + if (modem->legacy_raw_rx_buffer_cached && dev->id == IPC_MAP_NORM_RAW) { char *src = get_rxq_buff(dev); if (!src) { @@ -1938,7 +1666,6 @@ static int legacy_ipc_rx_func_napi(struct mem_link_device *mld, struct legacy_ip DMA_FROM_DEVICE); } } -#endif while ((budget != 0) && (rcvd < size)) { struct sk_buff *skb; @@ -1993,6 +1720,7 @@ static int legacy_ipc_rx_func_napi(struct mem_link_device *mld, struct legacy_ip static int legacy_ipc_rx_func(struct mem_link_device *mld, struct legacy_ipc_device *dev) { struct link_device *ld = &mld->link_dev; + struct modem_data *modem = ld->mdm_data; unsigned int qsize = get_rxq_buff_size(dev); unsigned int in = get_rxq_head(dev); unsigned int out = get_rxq_tail(dev); @@ -2003,8 +1731,7 @@ static int legacy_ipc_rx_func(struct mem_link_device *mld, struct legacy_ipc_dev if (unlikely(circ_empty(in, out))) return 0; -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - if (dev->id == IPC_MAP_NORM_RAW) { + if (modem->legacy_raw_rx_buffer_cached && dev->id == IPC_MAP_NORM_RAW) { char *src = get_rxq_buff(dev); if (!src) { @@ -2022,7 +1749,6 @@ static int legacy_ipc_rx_func(struct mem_link_device *mld, struct legacy_ipc_dev DMA_FROM_DEVICE); } } -#endif while (rcvd < size) { struct sk_buff *skb; @@ -2161,7 +1887,7 @@ static int bootdump_rx_func(struct mem_link_device *mld) if (!work_pending(&mld->page_reclaim_work)) { struct link_device *ld = &mld->link_dev; - mif_err_limited("Rx ENOMEM, try reclaim work"); + mif_err_limited("Rx ENOMEM, try reclaim work\n"); queue_work(ld->rx_wq, &mld->page_reclaim_work); } @@ -2202,81 +1928,42 @@ static int shmem_init_comm(struct link_device *ld, struct io_device *iod) { struct mem_link_device *mld = to_mem_link_device(ld); struct modem_ctl *mc = ld->mc; - struct io_device *check_iod; + struct io_device *check_iod = NULL; + bool allow_no_check_iod = false; int id = iod->ch; int fmt2rfs = (ld->chid_rfs_0 - ld->chid_fmt_0); int rfs2fmt = (ld->chid_fmt_0 - ld->chid_rfs_0); - if (atomic_read(&mld->cp_boot_done)) - return 0; - -#if IS_ENABLED(CONFIG_LINK_CONTROL_MSG_IOSM) - if (mld->iosm) { - struct sbd_link_device *sl = &mld->sbd_link_dev; - struct sbd_ipc_device *sid = sbd_ch2dev(sl, iod->ch); - - if (!atomic_read(&sid->config_done)) { - mif_err("%s isn't configured channel\n", iod->name); - return -ENODEV; - } - - tx_iosm_message(mld, IOSM_A2C_OPEN_CH, (u32 *)&id); + if (atomic_read(&mld->init_end_cnt)) return 0; - } -#endif if (ld->protocol == PROTOCOL_SIT) return 0; + /* FMT will check RFS and vice versa */ if (ld->is_fmt_ch(id)) { check_iod = link_get_iod_with_channel(ld, (id + fmt2rfs)); - if (check_iod ? atomic_read(&check_iod->opened) : true) { - if (ld->link_type == LINKDEV_SHMEM) - write_clk_table_to_shmem(mld); - - mif_err("%s: %s->INIT_END->%s\n", - ld->name, iod->name, mc->name); - if (!atomic_read(&mld->cp_boot_done)) { - send_ipc_irq(mld, cmd2int(CMD_INIT_END)); - atomic_set(&mld->cp_boot_done, 1); - } - } else { - mif_err("%s is not opened yet\n", check_iod->name); - } + allow_no_check_iod = true; + } else if (ld->is_rfs_ch(id)) { + check_iod = link_get_iod_with_channel(ld, (id + rfs2fmt)); } - if (ld->is_rfs_ch(id)) { - check_iod = link_get_iod_with_channel(ld, (id + rfs2fmt)); - if (check_iod) { - if (atomic_read(&check_iod->opened)) { - if (ld->link_type == LINKDEV_SHMEM) - write_clk_table_to_shmem(mld); - - mif_err("%s: %s->INIT_END->%s\n", - ld->name, iod->name, mc->name); - if (!atomic_read(&mld->cp_boot_done)) { - send_ipc_irq(mld, cmd2int(CMD_INIT_END)); - atomic_set(&mld->cp_boot_done, 1); - } - } else { - mif_err("%s not opened yet\n", check_iod->name); - } + if (check_iod ? atomic_read(&check_iod->opened) : allow_no_check_iod) { + if (ld->link_type == LINKDEV_SHMEM) + write_clk_table_to_shmem(mld); + + if (cp_online(mc) && !atomic_read(&mld->init_end_cnt)) { + mif_err("%s: %s -> INIT_END -> %s\n", ld->name, iod->name, mc->name); + atomic_inc(&mld->init_end_cnt); + send_ipc_irq(mld, cmd2int(CMD_INIT_END)); } + } else if (check_iod) { + mif_err("%s is not opened yet\n", check_iod->name); } return 0; } -static void shmem_terminate_comm(struct link_device *ld, struct io_device *iod) -{ -#if IS_ENABLED(CONFIG_LINK_CONTROL_MSG_IOSM) - struct mem_link_device *mld = to_mem_link_device(ld); - - if (mld->iosm) - tx_iosm_message(mld, IOSM_A2C_CLOSE_CH, (u32 *)&iod->ch); -#endif -} - static int shmem_send(struct link_device *ld, struct io_device *iod, struct sk_buff *skb) { @@ -2291,7 +1978,9 @@ static void link_prepare_normal_boot(struct link_device *ld, struct io_device *i struct mem_link_device *mld = to_mem_link_device(ld); unsigned long flags; - atomic_set(&mld->cp_boot_done, 0); + atomic_set(&mld->init_end_cnt, 0); + atomic_set(&mld->init_end_busy, 0); + mld->last_init_end_cnt = 0; spin_lock_irqsave(&mld->state_lock, flags); mld->state = LINK_STATE_OFFLINE; @@ -2304,12 +1993,6 @@ static void link_prepare_normal_boot(struct link_device *ld, struct io_device *i sbd_deactivate(&mld->sbd_link_dev); #endif cancel_tx_timer(mld, &mld->sbd_tx_timer); - cancel_datalloc_timer(mld); - - if (mld->iosm) { - memset(mld->base + CMD_RGN_OFFSET, 0, CMD_RGN_SIZE); - mif_info("Control message region has been initialized\n"); - } } #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) @@ -2323,33 +2006,49 @@ static int link_load_cp_image(struct link_device *ld, struct io_device *iod, unsigned long arg) { struct mem_link_device *mld = to_mem_link_device(ld); -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) - struct resource *cpmem_info = mld->syscp_info; -#endif void __iomem *dst; void __user *src; - int err; struct cp_image img; void __iomem *v_base; size_t valid_space; + int ret = 0; /** * Get the information about the boot image */ memset(&img, 0, sizeof(struct cp_image)); - err = copy_from_user(&img, (const void __user *)arg, sizeof(img)); - if (err) { + ret = copy_from_user(&img, (const void __user *)arg, sizeof(img)); + if (ret) { mif_err("%s: ERR! INFO copy_from_user fail\n", ld->name); return -EFAULT; } + mutex_lock(&mld->vmap_lock); + + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE) { + struct modem_data *modem = mld->link_dev.mdm_data; + + /* + * Copy boot img to data buffer for keeping the IPC region integrity. + * boot_img_offset should be 64KB aligned. + */ + mld->boot_img_offset = round_up(modem->legacy_raw_buffer_offset, SZ_64K); + mld->boot_img_size = img.size; + + valid_space = mld->size - mld->boot_img_offset; + v_base = mld->base + mld->boot_img_offset; + + goto check_img; + } + if (mld->boot_base == NULL) { mld->boot_base = cp_shmem_get_nc_region(cp_shmem_get_base(ld->mdm_data->cp_num, SHMEM_CP), mld->boot_size); if (!mld->boot_base) { mif_err("Failed to vmap boot_region\n"); - return -EINVAL; /* TODO : need better return */ + ret = -EINVAL; + goto out; } } @@ -2358,6 +2057,7 @@ static int link_load_cp_image(struct link_device *ld, struct io_device *iod, /* Calculate base address (0: BOOT_MODE, 1: DUMP_MODE) */ v_base = (img.mode) ? mld->base : mld->boot_base; +check_img: /** * Check the size of the boot image * fix the integer overflow of "img.m_offset + img.len" from Jose Duart @@ -2366,106 +2066,73 @@ static int link_load_cp_image(struct link_device *ld, struct io_device *iod, || img.m_offset > valid_space - img.len) { mif_err("%s: ERR! Invalid args: size %x, offset %x, len %x\n", ld->name, img.size, img.m_offset, img.len); - return -EINVAL; + ret = -EINVAL; + goto out; } dst = (void __iomem *)(v_base + img.m_offset); src = (void __user *)((unsigned long)img.binary); - -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) - if (img.m_offset == (u32)cpmem_info->start) - mld->cp_binary_size = img.size; -#endif - - err = copy_from_user(dst, src, img.len); - if (err) { + ret = copy_from_user_memcpy_toio(dst, src, img.len); + if (ret) { mif_err("%s: ERR! BOOT copy_from_user fail\n", ld->name); - return err; + goto out; } - return 0; -} - -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) -unsigned long shmem_calculate_CRC32(const unsigned char *buf, unsigned long len) -{ - unsigned long ul_crc; - - if (buf == 0) - return 0L; - - ul_crc = CRC32_XINIT; - while (len--) - ul_crc = CRC32_TABLE[(ul_crc ^ *buf++) & 0xFF] ^ (ul_crc >> 8); - - ul_crc ^= CRC32_XOROT; - - return ul_crc; -} - -void shmem_check_modem_binary_crc(struct link_device *ld) -{ - struct mem_link_device *mld = to_mem_link_device(ld); - struct resource *cpmem_info = mld->syscp_info; - unsigned char *data; - unsigned long CRC; - - data = (unsigned char *)mld->boot_base + (u32)cpmem_info->start; - - CRC = shmem_calculate_CRC32(data, mld->cp_binary_size); - - mif_info("Modem Main Binary CRC: %08X\n", (unsigned int)CRC); +out: + mutex_unlock(&mld->vmap_lock); + return ret; } -#endif -unsigned long shm_get_security_param2(u32 cp_num, unsigned long mode, u32 bl_size) +int shm_get_security_param2(u32 cp_num, unsigned long mode, u32 bl_size, + unsigned long *param) { - unsigned long ret; + int ret = 0; switch (mode) { case CP_BOOT_MODE_NORMAL: case CP_BOOT_MODE_DUMP: - ret = bl_size; + *param = bl_size; break; case CP_BOOT_RE_INIT: - ret = 0; + *param = 0; break; case CP_BOOT_MODE_MANUAL: - ret = cp_shmem_get_base(cp_num, SHMEM_CP) + bl_size; + *param = cp_shmem_get_base(cp_num, SHMEM_CP) + bl_size; break; default: mif_info("Invalid sec_mode(%lu)\n", mode); - ret = 0; + ret = -EINVAL; break; } return ret; } -unsigned long shm_get_security_param3(u32 cp_num, unsigned long mode, u32 main_size) +int shm_get_security_param3(u32 cp_num, unsigned long mode, u32 main_size, + unsigned long *param) { - unsigned long ret; + int ret = 0; switch (mode) { case CP_BOOT_MODE_NORMAL: - ret = main_size; + *param = main_size; break; case CP_BOOT_MODE_DUMP: #ifdef CP_NONSECURE_BOOT - ret = cp_shmem_get_base(cp_num, SHMEM_CP); + *param = cp_shmem_get_base(cp_num, SHMEM_CP); #else - ret = cp_shmem_get_base(cp_num, SHMEM_IPC); + *param = cp_shmem_get_base(cp_num, SHMEM_IPC); #endif break; case CP_BOOT_RE_INIT: - ret = 0; + *param = 0; break; case CP_BOOT_MODE_MANUAL: - ret = main_size; + *param = main_size; break; default: mif_info("Invalid sec_mode(%lu)\n", mode); - ret = 0; + ret = -EINVAL; break; } return ret; @@ -2485,6 +2152,9 @@ static int shmem_security_request(struct link_device *ld, struct io_device *iod, #endif u32 cp_num = ld->mdm_data->cp_num; struct mem_link_device *mld = ld->mdm_data->mld; +#if IS_ENABLED(CONFIG_CP_PKTPROC) && IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + struct pktproc_adaptor *ppa = &mld->pktproc; +#endif err = copy_from_user(&msr, (const void __user *)arg, sizeof(msr)); if (err) { @@ -2494,23 +2164,27 @@ static int shmem_security_request(struct link_device *ld, struct io_device *iod, } mode = (unsigned long)msr.mode; - param2 = shm_get_security_param2(cp_num, mode, msr.param2); - param3 = shm_get_security_param3(cp_num, mode, msr.param3); - -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) - if (mode == CP_BOOT_MODE_NORMAL) - shmem_check_modem_binary_crc(ld); - /* boot_base should be unmapped after its usage on crc check */ - if (mld->boot_base != NULL) { - vunmap(mld->boot_base); - mld->boot_base = NULL; + err = shm_get_security_param2(cp_num, mode, msr.param2, ¶m2); + if (err) { + mif_err("%s: ERR! parameter2 is invalid\n", ld->name); + goto exit; } -#else - /* boot_base is in no use at this point */ + err = shm_get_security_param3(cp_num, mode, msr.param3, ¶m3); + if (err) { + mif_err("%s: ERR! parameter3 is invalid\n", ld->name); + goto exit; + } + + + mutex_lock(&mld->vmap_lock); if (mld->boot_base != NULL) { + /* boot_base is in no use at this point */ vunmap(mld->boot_base); mld->boot_base = NULL; } + mutex_unlock(&mld->vmap_lock); + +#if IS_ENABLED(CONFIG_CP_SECURE_BOOT) exynos_smc(SMC_ID_CLK, SSS_CLK_ENABLE, 0, 0); if ((mode == CP_BOOT_MODE_NORMAL) && cp_shmem_get_mem_map_on_cp_flag(cp_num)) mode |= cp_shmem_get_base(cp_num, SHMEM_CP); @@ -2526,25 +2200,37 @@ static int shmem_security_request(struct link_device *ld, struct io_device *iod, exynos_smc(SMC_ID_CLK, SSS_CLK_DISABLE, 0, 0); - if (try_cnt >= MAX_TRY_CNT) { - mif_info("%s: it fails to check signature of main binary.\n" - , ld->name); - } + if (try_cnt >= MAX_TRY_CNT) + mif_info("%s: it fails to check signature of main binary.\n", ld->name); - mif_info("%s: return_value=0x%08x(%s)\n", ld->name, err, - err < sizeof(smc_err_string) ? smc_err_string[err] : "NULL"); + mif_info("%s: return_value=%d\n", ld->name, err); #endif #if IS_ENABLED(CONFIG_CP_PKTPROC) if ((mode == CP_BOOT_RE_INIT) && mld->pktproc.use_dedicated_baaw) { - mif_info("memaddr:0x%lx memsize:0x%08x", + mif_info("memaddr:0x%lx memsize:0x%08x\n", cp_shmem_get_base(cp_num, SHMEM_PKTPROC), - cp_shmem_get_size(cp_num, SHMEM_PKTPROC)); + cp_shmem_get_size(cp_num, SHMEM_PKTPROC) +#if IS_ENABLED(CONFIG_CP_PKTPROC_UL) + + cp_shmem_get_size(cp_num, SHMEM_PKTPROC_UL)); +#else + ); +#endif exynos_smc(SMC_ID_CLK, SSS_CLK_ENABLE, 0, 0); +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + err = (int)exynos_smc(SMC_ID, CP_BOOT_EXT_BAAW, + ppa->cp_base, SYSMMU_BAAW_SIZE); +#else err = (int)exynos_smc(SMC_ID, CP_BOOT_EXT_BAAW, (unsigned long)cp_shmem_get_base(cp_num, SHMEM_PKTPROC), - (unsigned long)cp_shmem_get_size(cp_num, SHMEM_PKTPROC)); + (unsigned long)cp_shmem_get_size(cp_num, SHMEM_PKTPROC) +#if IS_ENABLED(CONFIG_CP_PKTPROC_UL) + + (unsigned long)cp_shmem_get_size(cp_num, SHMEM_PKTPROC_UL)); +#else + ); +#endif +#endif exynos_smc(SMC_ID_CLK, SSS_CLK_DISABLE, 0, 0); if (err) @@ -2556,6 +2242,7 @@ static int shmem_security_request(struct link_device *ld, struct io_device *iod, return err; } +#if IS_ENABLED(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) static int sbd_link_rx_func_napi(struct sbd_link_device *sl, struct link_device *ld, int budget, int *work_done) { @@ -2574,7 +2261,7 @@ static int sbd_link_rx_func_napi(struct sbd_link_device *sl, struct link_device ret = rx_ipc_frames_from_rb(rb); else /* ps channels */ ret = sbd_ipc_rx_func_napi(ld, rb->iod, budget, &ps_rcvd); - if ((ret == -EBUSY) || (ret == -ENOMEM)) + if ((ret == -EBUSY) || (ret == -ENOMEM) || (ret == -EFAULT)) break; if (ld->is_ps_ch(sbd_id2ch(sl, i))) { /* count budget only for ps frames */ @@ -2584,13 +2271,14 @@ static int sbd_link_rx_func_napi(struct sbd_link_device *sl, struct link_device } return ret; } +#endif//CONFIG_LINK_DEVICE_WITH_SBD_ARCH static int legacy_link_rx_func_napi(struct mem_link_device *mld, int budget, int *work_done) { int i = 0; int ret = 0; - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[i]; int ps_rcvd = 0; @@ -2634,29 +2322,47 @@ static int mld_rx_int_poll(struct napi_struct *napi, int budget) mld_napi); struct link_device *ld = &mld->link_dev; struct modem_ctl *mc = ld->mc; +#if IS_ENABLED(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) struct sbd_link_device *sl = &mld->sbd_link_dev; +#endif int total_ps_rcvd = 0; int ps_rcvd = 0; -#if IS_ENABLED(CONFIG_CP_PKTPROC) - int i = 0; -#endif - int ret = 1; + int ret = 0; int total_budget = budget; u32 qlen = 0; + mld->rx_poll_count++; + +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (!mld->pktproc.use_exclusive_irq) { + int i = 0; + for (i = 0; i < mld->pktproc.num_queue; i++) { + ret = mld->pktproc.q[i]->clean_rx_ring(mld->pktproc.q[i], budget, &ps_rcvd); + if ((ret == -EBUSY) || (ret == -ENOMEM)) { + goto keep_poll; + } + + budget -= ps_rcvd; + total_ps_rcvd += ps_rcvd; + ps_rcvd = 0; + } + } +#endif + #if IS_ENABLED(CONFIG_MCU_IPC) if (ld->interrupt_types == INTERRUPT_MAILBOX) ret = cp_mbox_check_handler(CP_MBOX_IRQ_IDX_0, mld->irq_cp2ap_msg); -#endif + if (IS_ERR_VALUE((unsigned long)ret)) { mif_err_limited("mbox check irq fails: err: %d\n", ret); goto dummy_poll_complete; } - mld->rx_poll_count++; - - if (ret) { /* if an irq is raised, take care of commands */ - if (shmem_enqueue_snapshot(mld)) + if (ret) +#endif + { /* if an irq is raised, take care of commands */ + ret = shmem_enqueue_snapshot(mld); + if (ret != -ENOMSG && ret != 0) goto dummy_poll_complete; qlen = mld->msb_rxq.qlen; @@ -2680,14 +2386,22 @@ static int mld_rx_int_poll(struct napi_struct *napi, int budget) } } +#if IS_ENABLED(CONFIG_LINK_DEVICE_WITH_SBD_ARCH) if (sbd_active(&mld->sbd_link_dev)) { ret = sbd_link_rx_func_napi(sl, ld, budget, &ps_rcvd); if ((ret == -EBUSY) || (ret == -ENOMEM)) goto keep_poll; + else if (ret == -EFAULT) { /* unrecoverable error */ + link_trigger_cp_crash(mld, CRASH_REASON_MIF_RX_BAD_DATA, + "rp exceeds ring buffer size"); + goto dummy_poll_complete; + } budget -= ps_rcvd; total_ps_rcvd += ps_rcvd; ps_rcvd = 0; - } else { /* legacy buffer */ + } else +#endif + { /* legacy buffer */ ret = legacy_link_rx_func_napi(mld, budget, &ps_rcvd); if ((ret == -EBUSY) || (ret == -ENOMEM)) goto keep_poll; @@ -2696,35 +2410,11 @@ static int mld_rx_int_poll(struct napi_struct *napi, int budget) ps_rcvd = 0; } -#if IS_ENABLED(CONFIG_CP_PKTPROC) - if (pktproc_check_support(&mld->pktproc) && - !mld->pktproc.use_exclusive_irq && - mld->pktproc.use_napi) { - for (i = 0; i < mld->pktproc.num_queue; i++) { - if (!pktproc_check_active(&mld->pktproc, i)) - continue; - - ret = mld->pktproc.q[i]->clean_rx_ring(mld->pktproc.q[i], budget, &ps_rcvd); - if ((ret == -EBUSY) || (ret == -ENOMEM)) - goto keep_poll; - - budget -= ps_rcvd; - total_ps_rcvd += ps_rcvd; - ps_rcvd = 0; - } - } -#endif - #if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) if (total_ps_rcvd) tpmon_start(); #endif - if (atomic_read(&mld->stop_napi_poll)) { - atomic_set(&mld->stop_napi_poll, 0); - goto dummy_poll_complete; - } - if (total_ps_rcvd < total_budget) { napi_complete_done(napi, total_ps_rcvd); ld->enable_rx_int(ld); @@ -2809,7 +2499,7 @@ static int link_start_dump_boot(struct link_device *ld, struct io_device *iod) ld->name, magic, ld->magic_dump); return -EFAULT; } - mif_err("%s: magic == 0x%08X\n", ld->name, magic); + mif_info("%s: magic == 0x%08X\n", ld->name, magic); } return 0; @@ -2827,7 +2517,7 @@ static void shmem_close_tx(struct link_device *ld) if (timer_pending(&mld->crash_ack_timer)) del_timer(&mld->crash_ack_timer); - stop_net_ifaces(ld); + stop_net_ifaces(ld, 0); purge_txq(mld); } @@ -2894,14 +2584,14 @@ static void pcie_send_ap2cp_irq(struct mem_link_device *mld, u16 mask) spin_lock_irqsave(&mc->pcie_tx_lock, flags); if (mutex_is_locked(&mc->pcie_onoff_lock)) { - mif_err_limited("Reserve doorbell interrupt: PCI on/off working\n"); + mif_info_limited("Reserve doorbell interrupt: PCI on/off working\n"); set_ctrl_msg(&mld->ap2cp_msg, mask); mc->reserve_doorbell_int = true; goto exit; } if (!mc->pcie_powered_on) { - mif_err_limited("Reserve doorbell interrupt: PCI not powered on\n"); + mif_info_limited("Reserve doorbell interrupt: PCI not powered on\n"); set_ctrl_msg(&mld->ap2cp_msg, mask); mc->reserve_doorbell_int = true; s5100_try_gpio_cp_wakeup(mc); @@ -2931,33 +2621,6 @@ struct shmem_srinfo { char buf[0]; }; -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) -static void shmem_clr_sbdcplog(struct mem_link_device *mld) -{ - u8 __iomem *base = mld->base + mld->size - SHMEM_BOOTSBDLOG_SIZE; - - memset(base, 0, SHMEM_BOOTSBDLOG_SIZE); -} - -void shmem_pr_sbdcplog(struct timer_list *t) -{ - struct link_device *ld = from_timer(ld, t, cplog_timer); - struct mem_link_device *mld = ld_to_mem_link_device(ld); - u8 __iomem *base = mld->base + mld->size - SHMEM_BOOTSBDLOG_SIZE; - u8 __iomem *offset; - int i; - - mif_info("dump cp logs: size: 0x%x, base: %pK\n", (unsigned int)mld->size, base); - - for (i = 0; i * 32 < SHMEM_BOOTSBDLOG_SIZE; i++) { - offset = base + i * 32; - mif_info("%6X: %*ph\n", (unsigned int)(offset - mld->base), 32, offset); - } - - shmem_clr_sbdcplog(mld); -} -#endif - /* not in use */ static int shmem_ioctl(struct link_device *ld, struct io_device *iod, unsigned int cmd, unsigned long arg) @@ -3004,7 +2667,6 @@ static int shmem_ioctl(struct link_device *ld, struct io_device *iod, case IOCTL_GET_CP_BOOTLOG: { -#if !IS_ENABLED(CONFIG_SBD_BOOTLOG) u8 __iomem *base = mld->base + SHMEM_BOOTLOG_BASE; char str[SHMEM_BOOTLOG_BUFF]; unsigned int size = base[0] + (base[1] << 8) @@ -3017,20 +2679,15 @@ static int shmem_ioctl(struct link_device *ld, struct io_device *iod, strncpy(str, base + SHMEM_BOOTLOG_OFFSET, size); mif_info("CP boot log[%d] : %s\n", size, str); -#else - mif_add_timer(&ld->cplog_timer, 0, shmem_pr_sbdcplog); -#endif break; } case IOCTL_CLR_CP_BOOTLOG: { -#if !IS_ENABLED(CONFIG_SBD_BOOTLOG) u8 __iomem *base = mld->base + SHMEM_BOOTLOG_BASE; mif_info("Clear CP boot log\n"); memset(base, 0, SHMEM_BOOTLOG_BUFF); -#endif break; } @@ -3042,7 +2699,7 @@ static int shmem_ioctl(struct link_device *ld, struct io_device *iod, return 0; } -static irqreturn_t shmem_tx_state_handler(int irq, void *data) +irqreturn_t shmem_tx_state_handler(int irq, void *data) { struct mem_link_device *mld = (struct mem_link_device *)data; struct link_device *ld = &mld->link_dev; @@ -3101,18 +2758,19 @@ static int shmem_enqueue_snapshot(struct mem_link_device *mld) return -EINVAL; } + if (unlikely(!cmd_valid(msb->snapshot.int2ap))) { + msb_free(msb); + return -ENOMSG; + } + msb_queue_tail(&mld->msb_rxq, msb); return 0; } -static irqreturn_t shmem_irq_handler(int irq, void *data) +irqreturn_t shmem_irq_handler(int irq, void *data) { struct mem_link_device *mld = (struct mem_link_device *)data; -#if IS_ENABLED(CONFIG_CP_PKTPROC) - struct pktproc_adaptor *ppa = &mld->pktproc; - int i; -#endif mld->rx_int_count++; if (napi_schedule_prep(&mld->mld_napi)) { @@ -3122,22 +2780,6 @@ static irqreturn_t shmem_irq_handler(int irq, void *data) __napi_schedule(&mld->mld_napi); } -/* ToDo: irq might be disabled by disable_rx_int() */ -#if IS_ENABLED(CONFIG_CP_PKTPROC) - if (pktproc_check_support(&mld->pktproc) && - !mld->pktproc.use_exclusive_irq && - !mld->pktproc.use_napi) { - for (i = 0; i < ppa->num_queue; i++) { - struct pktproc_queue *q = ppa->q[i]; - - if (!pktproc_check_active(&mld->pktproc, i)) - continue; - - q->irq_handler(irq, q); - } - } -#endif - return IRQ_HANDLED; } @@ -3147,7 +2789,7 @@ static irqreturn_t shmem_cp2ap_wakelock_handler(int irq, void *data) struct mem_link_device *mld = (struct mem_link_device *)data; unsigned int req; - mif_err("%s\n", __func__); + mif_info("%s\n", __func__); req = extract_ctrl_msg(&mld->cp2ap_united_status, mld->sbi_cp2ap_wakelock_mask, mld->sbi_cp2ap_wakelock_pos); @@ -3155,16 +2797,16 @@ static irqreturn_t shmem_cp2ap_wakelock_handler(int irq, void *data) if (req == 0) { if (cpif_wake_lock_active(mld->ws)) { cpif_wake_unlock(mld->ws); - mif_err("cp_wakelock unlocked\n"); + mif_info("cp_wakelock unlocked\n"); } else { - mif_err("cp_wakelock already unlocked\n"); + mif_info("cp_wakelock already unlocked\n"); } } else if (req == 1) { if (cpif_wake_lock_active(mld->ws)) { - mif_err("cp_wakelock already unlocked\n"); + mif_info("cp_wakelock already unlocked\n"); } else { cpif_wake_lock(mld->ws); - mif_err("cp_wakelock locked\n"); + mif_info("cp_wakelock locked\n"); } } else { mif_err("unsupported request: cp_wakelock\n"); @@ -3174,7 +2816,7 @@ static irqreturn_t shmem_cp2ap_wakelock_handler(int irq, void *data) } #endif -#if IS_ENABLED(CONFIG_MCU_IPC) && IS_ENABLED(CONFIG_PCI_EXYNOS) +#if IS_ENABLED(CONFIG_MCU_IPC) && IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) static irqreturn_t shmem_cp2ap_rat_mode_handler(int irq, void *data) { struct mem_link_device *mld = (struct mem_link_device *)data; @@ -3183,31 +2825,132 @@ static irqreturn_t shmem_cp2ap_rat_mode_handler(int irq, void *data) req = extract_ctrl_msg(&mld->cp2ap_united_status, mld->sbi_cp_rat_mode_mask, mld->sbi_cp_rat_mode_pos); - mif_err("value: %u\n", req); + mif_info("value: %u\n", req); if (req) { - exynos_pcie_l1ss_ctrl(0, PCIE_L1SS_CTRL_MODEM_IF); - mif_err("cp requests pcie l1ss disable\n"); + s51xx_pcie_l1ss_ctrl(0); + mif_info("cp requests pcie l1ss disable\n"); } else { - exynos_pcie_l1ss_ctrl(1, PCIE_L1SS_CTRL_MODEM_IF); - mif_err("cp requests pcie l1ss enable\n"); + s51xx_pcie_l1ss_ctrl(1); + mif_info("cp requests pcie l1ss enable\n"); } return IRQ_HANDLED; } #endif -#if IS_ENABLED(CONFIG_ECT) -static int parse_ect(struct mem_link_device *mld, char *dvfs_domain_name) +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) +#define CLATINFO_ACK_TIMEOUT (1000) /* ms */ +bool shmem_ap2cp_write_clatinfo(struct mem_link_device *mld, struct clat_info *clat) { - int i, counter = 0; - u32 mif_max_freq, mif_max_num_of_table = 0; - void *dvfs_block; - struct ect_dvfs_domain *dvfs_domain; + u8 *buff; + u32 addr; + struct link_device *ld = &mld->link_dev; + struct modem_ctl *mc = ld->mc; + unsigned long remain; + unsigned long timeout = msecs_to_jiffies(CLATINFO_ACK_TIMEOUT); + bool ret = true; - dvfs_block = ect_get_block(BLOCK_DVFS); - if (dvfs_block == NULL) - return -ENODEV; + if (mld->disable_hw_clat) + return false; + + mutex_lock(&mld->clatinfo_lock); + + buff = (u8 *)&clat->ipv4_local_subnet; + memcpy(&addr, &clat->ipv4_local_subnet, sizeof(addr)); + mif_info("xlat_v4_addr: %02X %02X %02X %02X\n", buff[0], buff[1], buff[2], buff[3]); + set_ctrl_msg(&mld->ap2cp_clatinfo_xlat_v4_addr, addr); + + buff = (u8 *)&clat->ipv6_local_subnet; + memcpy(&addr, buff, sizeof(addr)); + mif_info("xlat_addr_0: %02X %02X %02X %02X\n", buff[0], buff[1], buff[2], buff[3]); + set_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_0, addr); + + buff += sizeof(addr); + memcpy(&addr, buff, sizeof(addr)); + mif_info("xlat_addr_1: %02X %02X %02X %02X\n", buff[0], buff[1], buff[2], buff[3]); + set_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_1, addr); + + buff += sizeof(addr); + memcpy(&addr, buff, sizeof(addr)); + mif_info("xlat_addr_2: %02X %02X %02X %02X\n", buff[0], buff[1], buff[2], buff[3]); + set_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_2, addr); + + buff += sizeof(addr); + memcpy(&addr, buff, sizeof(addr)); + mif_info("xlat_addr_3: %02X %02X %02X %02X\n", buff[0], buff[1], buff[2], buff[3]); + set_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_3, addr); + + mif_info("clat_index: %d\n", clat->clat_index); + set_ctrl_msg(&mld->ap2cp_clatinfo_index, clat->clat_index); + + mif_info("send ap2cp_clatinfo_irq: %d\n", mld->int_ap2cp_clatinfo_send); + reinit_completion(&mc->clatinfo_ack); + cp_mbox_set_interrupt(CP_MBOX_IRQ_IDX_0, mld->int_ap2cp_clatinfo_send); + + remain = wait_for_completion_timeout(&mc->clatinfo_ack, timeout); + if (remain == 0) { + mif_err("clatinfo ack not delivered from cp\n"); + ret = false; + goto out; + } + + /* set clat_ndev with clat registers */ + if (clat->ipv4_iface[0]) + iodevs_for_each(ld->msd, toe_set_iod_clat_netdev, clat); + +out: + mutex_unlock(&mld->clatinfo_lock); + + /* clear clat_ndev but take a delay to prevent null ndev */ + if (!clat->ipv4_iface[0]) { + msleep(100); + iodevs_for_each(ld->msd, toe_set_iod_clat_netdev, clat); + } + + return ret; +} +EXPORT_SYMBOL(shmem_ap2cp_write_clatinfo); + +static irqreturn_t shmem_cp2ap_clatinfo_ack(int irq, void *data) +{ + struct mem_link_device *mld = (struct mem_link_device *)data; + struct link_device *ld = &mld->link_dev; + struct modem_ctl *mc = ld->mc; + + mif_info("CP replied clatinfo ack - use v4-rmmet path\n"); + + complete_all(&mc->clatinfo_ack); + + return IRQ_HANDLED; +} + +static void clatinfo_test(struct mem_link_device *mld) +{ + struct clat_info clat; + int i; + unsigned char *buff = (unsigned char *)&clat; + + for (i = 0; i < sizeof(clat); i++) + buff[i] = i; + + clat.clat_index = 0; + + shmem_ap2cp_write_clatinfo(mld, &clat); +} +#endif + +#if IS_ENABLED(CONFIG_ECT) +static int parse_ect(struct mem_link_device *mld, char *dvfs_domain_name) +{ + int i, counter = 0; + u32 mif_max_freq, mif_max_num_of_table = 0; + void *dvfs_block; + struct ect_dvfs_domain *dvfs_domain; + + dvfs_block = ect_get_block(BLOCK_DVFS); + if (dvfs_block == NULL) + return -ENODEV; dvfs_domain = ect_dvfs_get_domain(dvfs_block, (char *)dvfs_domain_name); if (dvfs_domain == NULL) @@ -3230,7 +2973,7 @@ static int parse_ect(struct mem_link_device *mld, char *dvfs_domain_name) } mld->mif_table.freq[mif_max_num_of_table - 1 - i] = mif_max_freq; - mif_err("MIF_LEV[%d] : %u\n", + mif_info("MIF_LEV[%d] : %u\n", mif_max_num_of_table - i, mif_max_freq); } } @@ -3238,26 +2981,44 @@ static int parse_ect(struct mem_link_device *mld, char *dvfs_domain_name) for (i = mif_max_num_of_table - 1; i >= 0; i--) { mld->mif_table.freq[i] = dvfs_domain->list_level[counter++].level; - mif_err("MIF_LEV[%d] : %u\n", i + 1, + mif_info("MIF_LEV[%d] : %u\n", i + 1, mld->mif_table.freq[i]); } } else if (!strcmp(dvfs_domain_name, "CP_CPU")) { + mld->cp_cpu_table.num_of_table = dvfs_domain->num_of_level; + mld->total_freq_table_count++; + for (i = dvfs_domain->num_of_level - 1; i >= 0; i--) { + mld->cp_cpu_table.freq[i] = + dvfs_domain->list_level[counter++].level; + mif_info("CP_CPU_LEV[%d] : %u\n", i + 1, + mld->cp_cpu_table.freq[i]); + } + } else if (!strcmp(dvfs_domain_name, "CP")) { mld->cp_table.num_of_table = dvfs_domain->num_of_level; mld->total_freq_table_count++; for (i = dvfs_domain->num_of_level - 1; i >= 0; i--) { mld->cp_table.freq[i] = dvfs_domain->list_level[counter++].level; - mif_err("CP_LEV[%d] : %u\n", i + 1, + mif_info("CP_LEV[%d] : %u\n", i + 1, mld->cp_table.freq[i]); } - } else if (!strcmp(dvfs_domain_name, "CP")) { - mld->modem_table.num_of_table = dvfs_domain->num_of_level; + } else if (!strcmp(dvfs_domain_name, "CP_EM")) { + mld->cp_em_table.num_of_table = dvfs_domain->num_of_level; + mld->total_freq_table_count++; + for (i = dvfs_domain->num_of_level - 1; i >= 0; i--) { + mld->cp_em_table.freq[i] = + dvfs_domain->list_level[counter++].level; + mif_info("CP_LEV[%d] : %u\n", i + 1, + mld->cp_em_table.freq[i]); + } + } else if (!strcmp(dvfs_domain_name, "CP_MCW")) { + mld->cp_mcw_table.num_of_table = dvfs_domain->num_of_level; mld->total_freq_table_count++; for (i = dvfs_domain->num_of_level - 1; i >= 0; i--) { - mld->modem_table.freq[i] = + mld->cp_mcw_table.freq[i] = dvfs_domain->list_level[counter++].level; - mif_err("MODEM_LEV[%d] : %u\n", i + 1, - mld->modem_table.freq[i]); + mif_info("CP_LEV[%d] : %u\n", i + 1, + mld->cp_mcw_table.freq[i]); } } @@ -3269,8 +3030,10 @@ static int parse_ect(struct mem_link_device *mld, char *dvfs_domain_name) mif_err("ECT is not defined(%s)\n", __func__); mld->mif_table.num_of_table = 0; + mld->cp_cpu_table.num_of_table = 0; mld->cp_table.num_of_table = 0; - mld->modem_table.num_of_table = 0; + mld->cp_em_table.num_of_table = 0; + mld->cp_mcw_table.num_of_table = 0; return 0; } @@ -3288,172 +3051,6 @@ static int shmem_rx_setup(struct link_device *ld) return 0; } -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) -int request_pcie_msi_int(struct link_device *ld, - struct platform_device *pdev) -{ - int ret, base_irq; - struct mem_link_device *mld = to_mem_link_device(ld); - struct device *dev = &pdev->dev; - struct modem_ctl *mc = ld->mc; - int irq_offset = 0; -#if IS_ENABLED(CONFIG_CP_PKTPROC) - struct pktproc_adaptor *ppa = &mld->pktproc; - int i; -#endif - - mif_info("Request MSI interrupt.\n"); - -#if IS_ENABLED(CONFIG_CP_PKTPROC) - if (ppa->use_exclusive_irq) - base_irq = s51xx_pcie_request_msi_int(mc->s51xx_pdev, 5); - else -#endif - base_irq = s51xx_pcie_request_msi_int(mc->s51xx_pdev, 4); - - mif_info("Request MSI interrupt. : BASE_IRQ(%d)\n", base_irq); - mld->msi_irq_base = base_irq; - - if (base_irq <= 0) { - mif_err("Can't get MSI IRQ!!!\n"); - return -EFAULT; - } - - ret = devm_request_irq(dev, base_irq + irq_offset, - shmem_irq_handler, IRQF_SHARED, "mif_cp2ap_msg", mld); - if (ret) { - mif_err("Can't request cp2ap_msg interrupt!!!\n"); - return -EIO; - } - irq_offset++; - - ret = devm_request_irq(dev, base_irq + irq_offset, - shmem_tx_state_handler, IRQF_SHARED, "mif_cp2ap_status", mld); - if (ret) { - mif_err("Can't request cp2ap_status interrupt!!!\n"); - return -EIO; - } - irq_offset++; - -#if IS_ENABLED(CONFIG_CP_PKTPROC) - if (ppa->use_exclusive_irq) { - for (i = 0; i < ppa->num_queue; i++) { - struct pktproc_queue *q = ppa->q[i]; - - q->irq = mld->msi_irq_base + irq_offset + q->irq_idx; - ret = devm_request_irq(dev, q->irq, q->irq_handler, IRQF_SHARED, - "pktproc", q); - if (ret) { - mif_err("devm_request_irq() for pktproc%d error %d\n", i, ret); - return -EIO; - } - irq_offset++; - } - } -#endif - - mld->msi_irq_base_enabled = 1; - mld->s51xx_pdev = mc->s51xx_pdev; - - return base_irq; -} - -static int shmem_register_pcie(struct link_device *ld) -{ - struct modem_ctl *mc = ld->mc; - struct platform_device *pdev = to_platform_device(mc->dev); - static int is_registered; - struct mem_link_device *mld = to_mem_link_device(ld); - -#if IS_ENABLED(CONFIG_GS_S2MPU) - u32 cp_num; - u32 shmem_idx; - int ret; - struct device_node *s2mpu_dn; -#endif - mif_err("CP EP driver initialization start.\n"); - -#if IS_ENABLED(CONFIG_GS_S2MPU) - - s2mpu_dn = of_parse_phandle(mc->dev->of_node, "s2mpu", 0); - if (!s2mpu_dn) { - mif_err("Failed to find s2mpu from device tree\n"); - return -EINVAL; - } - - mc->s2mpu = s2mpu_fwnode_to_info(&s2mpu_dn->fwnode); - if (!mc->s2mpu) { - mif_err("Failed to get S2MPU\n"); - return -EPROBE_DEFER; - } - - cp_num = ld->mdm_data->cp_num; - - for (shmem_idx = 0 ; shmem_idx < MAX_CP_SHMEM ; shmem_idx++) { - if (shmem_idx == SHMEM_MSI) - continue; - - if (cp_shmem_get_base(cp_num, shmem_idx)) { - ret = s2mpu_open(mc->s2mpu, - cp_shmem_get_base(cp_num, shmem_idx), - cp_shmem_get_size(cp_num, shmem_idx), - DMA_BIDIRECTIONAL); - if (ret) { - mif_err("S2MPU open failed error=%d\n", ret); - return -EINVAL; - } - } - } - - /* Also setup AoC window for voice calls */ - ret = s2mpu_open(mc->s2mpu, - AOC_PCIE_WINDOW_START, AOC_PCIE_WINDOW_SIZE, - DMA_BIDIRECTIONAL); - - if (ret) { - mif_err("S2MPU AoC open failed error=%d\n", ret); - return -EINVAL; - } - -#endif - - msleep(200); - - s5100_poweron_pcie(mc); - - if (is_registered == 0) { - /* initialize the pci_dev for modem_ctl */ - mif_err("s51xx_pcie_init start\n"); - s51xx_pcie_init(mc); - if (mc->s51xx_pdev == NULL) { - mif_err("s51xx_pdev is NULL. Check if CP wake up is done.\n"); - return -EINVAL; - } - - /* debug: check MSI 32bit or 64bit - should be set as 32bit before this point*/ - // debug: pci_read_config_dword(s51xx_pcie.s51xx_pdev, 0x50, &msi_val); - // debug: mif_err("MSI Control Reg : 0x%x\n", msi_val); - - request_pcie_msi_int(ld, pdev); - first_save_s51xx_status(mc->s51xx_pdev); - - is_registered = 1; - } else { - if (mc->phone_state == STATE_CRASH_RESET) { - print_msi_register(mc->s51xx_pdev); - enable_irq(mld->msi_irq_base); - } - } - - print_msi_register(mc->s51xx_pdev); - mc->pcie_registered = true; - - mif_err("CP EP driver initialization end.\n"); - - return 0; -} -#endif - /* sysfs */ static ssize_t tx_period_ms_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -3461,7 +3058,7 @@ static ssize_t tx_period_ms_show(struct device *dev, struct modem_data *modem; modem = (struct modem_data *)dev->platform_data; - return scnprintf(buf, PAGE_SIZE, "%d\n", modem->mld->tx_period_ms); + return scnprintf(buf, PAGE_SIZE, "%ld\n", modem->mld->tx_period_ns / NSEC_PER_MSEC); } static ssize_t tx_period_ms_store(struct device *dev, @@ -3473,9 +3070,10 @@ static ssize_t tx_period_ms_store(struct device *dev, modem = (struct modem_data *)dev->platform_data; - ret = kstrtouint(buf, 0, &modem->mld->tx_period_ms); + ret = kstrtouint(buf, 0, &modem->mld->tx_period_ns); if (ret) return -EINVAL; + modem->mld->tx_period_ns *= NSEC_PER_MSEC; ret = count; return ret; @@ -3516,21 +3114,20 @@ static ssize_t info_region_show(struct device *dev, ioread32(mld->buff_desc_offset)); if (modem->offset_capability_offset) { + int part; + count += scnprintf(&buf[count], PAGE_SIZE - count, "capability_offset:0x%08X\n", ioread32(mld->capability_offset)); - count += scnprintf(&buf[count], PAGE_SIZE - count, - "ap_capability_0_offset:0x%08X\n", - ioread32(mld->ap_capability_0_offset)); - count += scnprintf(&buf[count], PAGE_SIZE - count, - "ap_capability_1_offset:0x%08X\n", - ioread32(mld->ap_capability_1_offset)); - count += scnprintf(&buf[count], PAGE_SIZE - count, - "cp_capability_0_offset:0x%08X\n", - ioread32(mld->cp_capability_0_offset)); - count += scnprintf(&buf[count], PAGE_SIZE - count, - "cp_capability_1_offset:0x%08X\n", - ioread32(mld->cp_capability_1_offset)); + + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + count += scnprintf(&buf[count], PAGE_SIZE - count, + "ap_capability_offset[%d]:0x%08X\n", part, + ioread32(mld->ap_capability_offset[part])); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "cp_capability_offset[%d]:0x%08X\n", part, + ioread32(mld->cp_capability_offset[part])); + } } count += scnprintf(&buf[count], PAGE_SIZE - count, "ap2cp_msg:0x%08X\n", @@ -3694,6 +3291,86 @@ static const struct attribute_group napi_group = { .name = "napi", }; +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) +static ssize_t debug_hw_clat_test_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct modem_data *modem; + struct mem_link_device *mld; + unsigned int val = 0; + + int ret; + + modem = (struct modem_data *)dev->platform_data; + mld = modem->mld; + ret = kstrtouint(buf, 0, &val); + + if (val == 1) + clatinfo_test(mld); + + return count; +} + +#define PKTPROC_CLAT_ADDR_MAX (4) +static ssize_t debug_disable_hw_clat_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct clat_info clat; + unsigned int i; + unsigned int flag; + int ret; + struct modem_data *modem; + struct mem_link_device *mld; + + modem = (struct modem_data *)dev->platform_data; + mld = modem->mld; + + ret = kstrtoint(buf, 0, &flag); + if (ret) + return -EINVAL; + + if (flag) { + memset(&clat, 0, sizeof(clat)); + for (i = 0; i < PKTPROC_CLAT_ADDR_MAX; i++) { + clat.clat_index = i; + scnprintf(clat.ipv6_iface, IFNAMSIZ, "rmnet%d", i); + shmem_ap2cp_write_clatinfo(mld, &clat); + msleep(1000); + } + } + + mld->disable_hw_clat = (flag > 0 ? true : false); + + return count; +} + +static ssize_t debug_disable_hw_clat_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct modem_data *modem; + struct mem_link_device *mld; + + modem = (struct modem_data *)dev->platform_data; + mld = modem->mld; + + return scnprintf(buf, PAGE_SIZE, "disable_hw_clat: %d\n", mld->disable_hw_clat); +} + +static DEVICE_ATTR_WO(debug_hw_clat_test); +static DEVICE_ATTR_RW(debug_disable_hw_clat); + +static struct attribute *hw_clat_attrs[] = { + &dev_attr_debug_hw_clat_test.attr, + &dev_attr_debug_disable_hw_clat.attr, + NULL, +}; + +static const struct attribute_group hw_clat_group = { + .attrs = hw_clat_attrs, + .name = "hw_clat", +}; +#endif + #if IS_ENABLED(CONFIG_CP_PKTPROC) static u32 p_pktproc[3]; static u32 c_pktproc[3]; @@ -3774,82 +3451,100 @@ static enum hrtimer_restart sbd_print(struct hrtimer *timer) return HRTIMER_RESTART; } -struct link_device *create_link_device(struct platform_device *pdev, u32 link_type) +static int set_protocol_attr(struct link_device *ld) { - struct modem_data *modem; - struct mem_link_device *mld; - struct link_device *ld; - int err; - u32 cp_num; - struct device_node *np_acpm = NULL; - u32 acpm_addr; - u8 __iomem *cmsg_base; - - mif_err("+++\n"); + switch (ld->protocol) { + case PROTOCOL_SIPC: + ld->chid_fmt_0 = SIPC5_CH_ID_FMT_0; + ld->chid_rfs_0 = SIPC5_CH_ID_RFS_0; + ld->magic_boot = MEM_BOOT_MAGIC; + ld->magic_crash = MEM_CRASH_MAGIC; + ld->magic_dump = MEM_DUMP_MAGIC; + ld->magic_ipc = MEM_IPC_MAGIC; - /** - * Get the modem (platform) data - */ - modem = (struct modem_data *)pdev->dev.platform_data; - if (!modem) { - mif_err("ERR! modem == NULL\n"); - return NULL; - } + ld->is_start_valid = sipc5_start_valid; + ld->is_padding_exist = sipc5_padding_exist; + ld->is_multi_frame = sipc5_multi_frame; + ld->has_ext_len = sipc5_ext_len; + ld->get_ch = sipc5_get_ch; + ld->get_ctrl = sipc5_get_ctrl; + ld->calc_padding_size = sipc5_calc_padding_size; + ld->get_hdr_len = sipc5_get_hdr_len; + ld->get_frame_len = sipc5_get_frame_len; + ld->get_total_len = sipc5_get_total_len; + ld->is_fmt_ch = sipc5_fmt_ch; + ld->is_ps_ch = sipc_ps_ch; + ld->is_rfs_ch = sipc5_rfs_ch; + ld->is_boot_ch = sipc5_boot_ch; + ld->is_dump_ch = sipc5_dump_ch; + ld->is_bootdump_ch = sipc5_bootdump_ch; + ld->is_ipc_ch = sipc5_ipc_ch; + ld->is_csd_ch = sipc_csd_ch; + ld->is_log_ch = sipc_log_ch; + ld->is_router_ch = sipc_router_ch; + ld->is_misc_ch = sipc_misc_ch; + ld->is_embms_ch = NULL; + ld->is_uts_ch = NULL; + ld->is_wfs0_ch = NULL; + ld->is_wfs1_ch = NULL; + break; + case PROTOCOL_SIT: + ld->chid_fmt_0 = EXYNOS_CH_ID_FMT_0; + ld->chid_rfs_0 = EXYNOS_CH_ID_RFS_0; + ld->magic_boot = SHM_BOOT_MAGIC; + ld->magic_crash = SHM_DUMP_MAGIC; + ld->magic_dump = SHM_DUMP_MAGIC; + ld->magic_ipc = SHM_IPC_MAGIC; - if (!modem->mbx) { - mif_err("%s: ERR! mbx == NULL\n", modem->link_name); - return NULL; - } - - if (modem->ipc_version < SIPC_VER_50) { - mif_err("%s<->%s: ERR! IPC version %d < SIPC_VER_50\n", - modem->link_name, modem->name, modem->ipc_version); - return NULL; - } - - mif_err("MODEM:%s LINK:%s\n", modem->name, modem->link_name); - - /* - * Alloc an instance of mem_link_device structure - */ - mld = kzalloc(sizeof(struct mem_link_device), GFP_KERNEL); - if (!mld) { - mif_err("%s<->%s: ERR! mld kzalloc fail\n", - modem->link_name, modem->name); - return NULL; + ld->is_start_valid = exynos_start_valid; + ld->is_padding_exist = exynos_padding_exist; + ld->is_multi_frame = exynos_multi_frame; + ld->has_ext_len = exynos_ext_len; + ld->get_ch = exynos_get_ch; + ld->get_ctrl = exynos_get_ctrl; + ld->calc_padding_size = exynos_calc_padding_size; + ld->get_hdr_len = exynos_get_hdr_len; + ld->get_frame_len = exynos_get_frame_len; + ld->get_total_len = exynos_get_total_len; + ld->is_fmt_ch = exynos_fmt_ch; + ld->is_ps_ch = exynos_ps_ch; + ld->is_rfs_ch = exynos_rfs_ch; + ld->is_boot_ch = exynos_boot_ch; + ld->is_dump_ch = exynos_dump_ch; + ld->is_bootdump_ch = exynos_bootdump_ch; + ld->is_ipc_ch = exynos_ipc_ch; + ld->is_csd_ch = exynos_rcs_ch; + ld->is_log_ch = exynos_log_ch; + ld->is_router_ch = exynos_router_ch; + ld->is_embms_ch = exynos_embms_ch; + ld->is_uts_ch = exynos_uts_ch; + ld->is_wfs0_ch = exynos_wfs0_ch; + ld->is_wfs1_ch = exynos_wfs1_ch; + ld->is_oem_ch = exynos_oem_ch; + break; + default: + mif_err("protocol error %d\n", ld->protocol); + return -EINVAL; } - /* - * Retrieve modem-specific attributes value - */ - mld->attrs = modem->link_attrs; - mif_info("link_attrs:0x%08lx\n", mld->attrs); - - /*==================================================================== - * Initialize "memory snapshot buffer (MSB)" framework - *==================================================================== - */ - if (msb_init() < 0) { - mif_err("%s<->%s: ERR! msb_init() fail\n", - modem->link_name, modem->name); - goto error; - } + return 0; +} - /*==================================================================== - * Set attributes as a "link_device" - *==================================================================== - */ - ld = &mld->link_dev; +static int set_ld_attr(struct platform_device *pdev, + u32 link_type, struct modem_data *modem, + struct mem_link_device *mld, struct link_device *ld) +{ + int err = 0; ld->name = modem->link_name; if (mld->attrs & LINK_ATTR_SBD_IPC) { - mif_err("%s<->%s: LINK_ATTR_SBD_IPC\n", ld->name, modem->name); + mif_info("%s<->%s: LINK_ATTR_SBD_IPC\n", ld->name, modem->name); ld->sbd_ipc = true; } if (mld->attrs & LINK_ATTR_IPC_ALIGNED) { - mif_err("%s<->%s: LINK_ATTR_IPC_ALIGNED\n", + mif_info("%s<->%s: LINK_ATTR_IPC_ALIGNED\n", ld->name, modem->name); ld->aligned = true; } @@ -3866,45 +3561,38 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty */ ld->ioctl = shmem_ioctl; - if (link_type == LINKDEV_SHMEM) - ld->init_comm = shmem_init_comm; - ld->terminate_comm = shmem_terminate_comm; + ld->init_comm = shmem_init_comm; + ld->terminate_comm = NULL; ld->send = shmem_send; - ld->reset_zerocopy = NULL; ld->link_prepare_normal_boot = link_prepare_normal_boot; - if (mld->attrs & LINK_ATTR_MEM_BOOT) { - if (mld->attrs & LINK_ATTR_XMIT_BTDLR) { - if (mld->attrs & LINK_ATTR_XMIT_BTDLR_SPI) { - u32 bus_num = 0; - - err = of_property_read_u32(pdev->dev.of_node, "cpboot_spi_bus_num", - &bus_num); - if (err) { - mif_err("cpboot_spi_bus_num error:%d\n", err); - goto error; - } - mld->boot_spi = cpboot_spi_get_device(bus_num); - if (!mld->boot_spi) { - mif_err("boot_spi is null\n"); - goto error; - } - ld->load_cp_image = cpboot_spi_load_cp_image; - } else { - ld->load_cp_image = link_load_cp_image; - } - } + ld->link_trigger_cp_crash = link_trigger_cp_crash; + + do { + if (!(mld->attrs & LINK_ATTR_MEM_BOOT)) + break; + ld->link_start_normal_boot = link_start_normal_boot; if (link_type == LINKDEV_SHMEM) ld->security_req = shmem_security_request; - } - ld->link_trigger_cp_crash = link_trigger_cp_crash; + if (!(mld->attrs & LINK_ATTR_XMIT_BTDLR)) + break; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) - if (link_type == LINKDEV_PCIE) - ld->register_pcie = shmem_register_pcie; -#endif + ld->load_cp_image = link_load_cp_image; + mld->spi_bus_num = -1; + mif_dt_read_u32_noerr(pdev->dev.of_node, "cpboot_spi_bus_num", + mld->spi_bus_num); + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_SPI) { + ld->load_cp_image = cpboot_spi_load_cp_image; + + if (mld->spi_bus_num < 0) { + mif_err("cpboot_spi_bus_num error\n"); + err = -ENODEV; + goto error; + } + } + } while (0); if (mld->attrs & LINK_ATTR_MEM_DUMP) ld->link_start_dump_boot = link_start_dump_boot; @@ -3915,92 +3603,404 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty ld->protocol = modem->protocol; ld->capability_check = modem->capability_check; - switch (ld->protocol) { - case PROTOCOL_SIPC: - ld->chid_fmt_0 = SIPC5_CH_ID_FMT_0; - ld->chid_rfs_0 = SIPC5_CH_ID_RFS_0; - ld->magic_boot = MEM_BOOT_MAGIC; - ld->magic_crash = MEM_CRASH_MAGIC; - ld->magic_dump = MEM_DUMP_MAGIC; - ld->magic_ipc = MEM_IPC_MAGIC; + err = set_protocol_attr(ld); + if (err) + goto error; - ld->is_start_valid = sipc5_start_valid; - ld->is_padding_exist = sipc5_padding_exist; - ld->is_multi_frame = sipc5_multi_frame; - ld->has_ext_len = sipc5_ext_len; - ld->get_ch = sipc5_get_ch; - ld->get_ctrl = sipc5_get_ctrl; - ld->calc_padding_size = sipc5_calc_padding_size; - ld->get_hdr_len = sipc5_get_hdr_len; - ld->get_frame_len = sipc5_get_frame_len; - ld->get_total_len = sipc5_get_total_len; - ld->is_fmt_ch = sipc5_fmt_ch; - ld->is_ps_ch = sipc_ps_ch; - ld->is_rfs_ch = sipc5_rfs_ch; - ld->is_boot_ch = sipc5_boot_ch; - ld->is_dump_ch = sipc5_dump_ch; - ld->is_bootdump_ch = sipc5_bootdump_ch; - ld->is_ipc_ch = sipc5_ipc_ch; - ld->is_csd_ch = sipc_csd_ch; - ld->is_log_ch = sipc_log_ch; - ld->is_router_ch = sipc_router_ch; - ld->is_misc_ch = sipc_misc_ch; - ld->is_embms_ch = NULL; - ld->is_uts_ch = NULL; - ld->is_wfs0_ch = NULL; - ld->is_wfs1_ch = NULL; - break; - case PROTOCOL_SIT: - ld->chid_fmt_0 = EXYNOS_CH_ID_FMT_0; - ld->chid_rfs_0 = EXYNOS_CH_ID_RFS_0; - ld->magic_boot = SHM_BOOT_MAGIC; - ld->magic_crash = SHM_DUMP_MAGIC; - ld->magic_dump = SHM_DUMP_MAGIC; - ld->magic_ipc = SHM_IPC_MAGIC; + ld->enable_rx_int = shmem_enable_rx_int; + ld->disable_rx_int = shmem_disable_rx_int; - ld->is_start_valid = exynos_start_valid; - ld->is_padding_exist = exynos_padding_exist; - ld->is_multi_frame = exynos_multi_frame; - ld->has_ext_len = exynos_ext_len; - ld->get_ch = exynos_get_ch; - ld->get_ctrl = exynos_get_ctrl; - ld->calc_padding_size = exynos_calc_padding_size; - ld->get_hdr_len = exynos_get_hdr_len; - ld->get_frame_len = exynos_get_frame_len; - ld->get_total_len = exynos_get_total_len; - ld->is_fmt_ch = exynos_fmt_ch; - ld->is_ps_ch = exynos_ps_ch; - ld->is_rfs_ch = exynos_rfs_ch; - ld->is_boot_ch = exynos_boot_ch; - ld->is_dump_ch = exynos_dump_ch; - ld->is_bootdump_ch = exynos_bootdump_ch; - ld->is_ipc_ch = exynos_ipc_ch; - ld->is_csd_ch = exynos_rcs_ch; - ld->is_log_ch = exynos_log_ch; - ld->is_router_ch = exynos_router_ch; - ld->is_embms_ch = exynos_embms_ch; - ld->is_uts_ch = exynos_uts_ch; - ld->is_wfs0_ch = exynos_wfs0_ch; - ld->is_wfs1_ch = exynos_wfs1_ch; - ld->is_oem_ch = exynos_oem_ch; + ld->start_timers = shmem_start_timers; + ld->stop_timers = shmem_stop_timers; + + ld->handover_block_info = update_handover_block_info; + + return 0; + +error: + mif_err("xxx\n"); + return err; +} + +static int init_shmem_maps(u32 link_type, struct modem_data *modem, + struct mem_link_device *mld, struct link_device *ld, u32 cp_num) +{ + int err = 0; + struct device_node *np_acpm = NULL; + u32 acpm_addr; + +#if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) + if (link_type == LINKDEV_SHMEM) { + mld->boot_size = cp_shmem_get_size(cp_num, SHMEM_CP) + + cp_shmem_get_size(cp_num, SHMEM_VSS); + mld->boot_base = NULL; + mif_info("boot_base=NULL, boot_size=%lu\n", + (unsigned long)mld->boot_size); + } +#endif + + /* + * Initialize SHMEM maps for IPC (physical map -> logical map) + */ + mld->size = cp_shmem_get_size(cp_num, SHMEM_IPC); + if (modem->legacy_raw_rx_buffer_cached) + mld->base = cp_shmem_get_nc_region(cp_shmem_get_base(cp_num, SHMEM_IPC), + modem->legacy_raw_buffer_offset + modem->legacy_raw_txq_size); + else + mld->base = cp_shmem_get_region(cp_num, SHMEM_IPC); + +#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) + mld->hiprio_base = cp_shmem_get_nc_region(cp_shmem_get_base(cp_num, SHMEM_IPC) + + modem->legacy_raw_qos_buffer_offset, modem->legacy_raw_qos_txq_size + + modem->legacy_raw_qos_rxq_size); +#endif + if (!mld->base) { + mif_err("Failed to vmap ipc_region\n"); + err = -ENOMEM; + goto error; + } + mif_info("ipc_base=%pK, ipc_size=%lu\n", + mld->base, (unsigned long)mld->size); + + switch (link_type) { + case LINKDEV_SHMEM: + /* + * Initialize SHMEM maps for VSS (physical map -> logical map) + */ + mld->vss_base = cp_shmem_get_region(cp_num, SHMEM_VSS); + if (!mld->vss_base) { + mif_err("Failed to vmap vss_region\n"); + err = -ENOMEM; + goto error; + } + mif_info("vss_base=%pK\n", mld->vss_base); + + /* + * Initialize memory maps for ACPM (physical map -> logical map) + */ + np_acpm = of_find_node_by_name(NULL, "acpm_ipc"); + if (!np_acpm) + break; + + of_property_read_u32(np_acpm, "dump-size", &mld->acpm_size); + of_property_read_u32(np_acpm, "dump-base", &acpm_addr); + mld->acpm_base = cp_shmem_get_nc_region(acpm_addr, mld->acpm_size); + if (!mld->acpm_base) { + mif_err("Failed to vmap acpm_region\n"); + err = -ENOMEM; + goto error; + } + mif_info("acpm_base=%pK acpm_size:0x%X\n", mld->acpm_base, + mld->acpm_size); break; default: - mif_err("protocol error %d\n", ld->protocol); + break; + } + + ld->link_type = link_type; + create_legacy_link_device(mld); + + if (ld->sbd_ipc) { + hrtimer_init(&mld->sbd_tx_timer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + mld->sbd_tx_timer.function = sbd_tx_timer_func; + + hrtimer_init(&mld->sbd_print_timer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + mld->sbd_print_timer.function = sbd_print; + + err = create_sbd_link_device(ld, + &mld->sbd_link_dev, mld->base, mld->size); + if (err < 0) + goto error; + } + + return 0; + +error: + mif_err("xxx\n"); + return err; +} + +static int init_info_region(struct modem_data *modem, + struct mem_link_device *mld, struct link_device *ld) +{ + u8 __iomem *cmsg_base; + int part; + + if (modem->offset_ap_version) + mld->ap_version = (u32 __iomem *)(mld->base + modem->offset_ap_version); + if (modem->offset_cp_version) + mld->cp_version = (u32 __iomem *)(mld->base + modem->offset_cp_version); + if (modem->offset_cmsg_offset) { + mld->cmsg_offset = (u32 __iomem *)(mld->base + modem->offset_cmsg_offset); + cmsg_base = mld->base + modem->cmsg_offset; + iowrite32(modem->cmsg_offset, mld->cmsg_offset); + } else { + cmsg_base = mld->base; + } + + if (modem->offset_srinfo_offset) { + mld->srinfo_offset = (u32 __iomem *)(mld->base + modem->offset_srinfo_offset); + iowrite32(modem->srinfo_offset, mld->srinfo_offset); + } + if (modem->offset_clk_table_offset) { + mld->clk_table_offset = (u32 __iomem *)(mld->base + modem->offset_clk_table_offset); + iowrite32(modem->clk_table_offset, mld->clk_table_offset); + } + if (modem->offset_buff_desc_offset) { + mld->buff_desc_offset = (u32 __iomem *)(mld->base + modem->offset_buff_desc_offset); + iowrite32(modem->buff_desc_offset, mld->buff_desc_offset); + } + + mld->srinfo_base = (u32 __iomem *)(mld->base + modem->srinfo_offset); + mld->srinfo_size = modem->srinfo_size; + mld->clk_table = (u32 __iomem *)(mld->base + modem->clk_table_offset); + + if (ld->capability_check) { + u8 __iomem *offset; + + /* AP/CP capability */ + offset = mld->base + modem->offset_capability_offset; + mld->capability_offset = (u32 __iomem *)(offset); + iowrite32(modem->capability_offset, mld->capability_offset); + + offset = mld->base + modem->capability_offset; + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + mld->ap_capability_offset[part] = + (u32 __iomem *)(offset + (AP_CP_CAP_PART_LEN * 2 * part)); + mld->cp_capability_offset[part] = + (u32 __iomem *)(offset + (AP_CP_CAP_PART_LEN * 2 * part) + + AP_CP_CAP_PART_LEN); + + /* Initial values */ + iowrite32(0, mld->ap_capability_offset[part]); + iowrite32(0, mld->cp_capability_offset[part]); + } + } + + construct_ctrl_msg(&mld->cp2ap_msg, modem->cp2ap_msg, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_msg, modem->ap2cp_msg, cmsg_base); + construct_ctrl_msg(&mld->cp2ap_united_status, modem->cp2ap_united_status, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_united_status, modem->ap2cp_united_status, cmsg_base); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + construct_ctrl_msg(&mld->ap2cp_clatinfo_xlat_v4_addr, + modem->ap2cp_clatinfo_xlat_v4_addr, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_0, + modem->ap2cp_clatinfo_xlat_addr_0, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_1, + modem->ap2cp_clatinfo_xlat_addr_1, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_2, + modem->ap2cp_clatinfo_xlat_addr_2, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_clatinfo_xlat_addr_3, + modem->ap2cp_clatinfo_xlat_addr_3, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_clatinfo_index, + modem->ap2cp_clatinfo_index, cmsg_base); +#endif + construct_ctrl_msg(&mld->ap2cp_kerneltime, modem->ap2cp_kerneltime, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_kerneltime_sec, modem->ap2cp_kerneltime_sec, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_kerneltime_usec, modem->ap2cp_kerneltime_usec, cmsg_base); + construct_ctrl_msg(&mld->ap2cp_handover_block_info, + modem->ap2cp_handover_block_info, cmsg_base); + + for (part = 0; part < AP_CP_CAP_PARTS; part++) + mld->ap_capability[part] = modem->ap_capability[part]; + + return 0; +} + +#if IS_ENABLED(CONFIG_MCU_IPC) +static int register_irq_handler(struct modem_data *modem, + struct mem_link_device *mld, struct link_device *ld) +{ + unsigned int irq_num; + int err; + + if (ld->interrupt_types != INTERRUPT_MAILBOX) { + err = -EPERM; + goto error; + } + + irq_num = mld->irq_cp2ap_msg; + err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, irq_num, + shmem_irq_handler, mld); + if (err) + goto irq_error; + + /** + * Retrieve SHMEM MBOX# and IRQ# for wakelock + */ + mld->ws = cpif_wake_lock_register(ld->dev, ld->name); + if (mld->ws == NULL) { + mif_err("%s: wakeup_source_register fail\n", ld->name); + err = -EINVAL; goto error; } - ld->enable_rx_int = shmem_enable_rx_int; - ld->disable_rx_int = shmem_disable_rx_int; + irq_num = mld->irq_cp2ap_wakelock; + err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, irq_num, + shmem_cp2ap_wakelock_handler, mld); + if (err) + goto irq_error; + + /** + * Retrieve SHMEM MBOX# and IRQ# for RAT_MODE + */ +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) + irq_num = mld->irq_cp2ap_rat_mode; + err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, irq_num, + shmem_cp2ap_rat_mode_handler, mld); + if (err) + goto irq_error; +#endif + + irq_num = mld->irq_cp2ap_status; + err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, irq_num, + shmem_tx_state_handler, mld); + if (err) + goto irq_error; + +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + irq_num = mld->irq_cp2ap_clatinfo_ack; + err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, irq_num, + shmem_cp2ap_clatinfo_ack, mld); + if (err) + goto irq_error; +#endif + + return 0; + +irq_error: + mif_err("%s: ERR! cp_mbox_register_handler(MBOX_IRQ_IDX_0, %u) fail (%d)\n", + ld->name, irq_num, err); + +error: + mif_err("xxx\n"); + + return err; +} +#endif + +static int parse_ect_tables(struct platform_device *pdev, + struct mem_link_device *mld) +{ + int err = 0; + + err = of_property_read_u32(pdev->dev.of_node, + "devfreq_use_dfs_max_freq", &mld->mif_table.use_dfs_max_freq); + if (err) { + mif_err("devfreq_use_dfs_max_freq error:%d\n", err); + return err; + } + + if (mld->mif_table.use_dfs_max_freq) { + err = of_property_read_u32(pdev->dev.of_node, + "devfreq_cal_id_mif", &mld->mif_table.cal_id_mif); + if (err) { + mif_err("devfreq_cal_id_mif error:%d\n", err); + return err; + } + } + + /* Parsing devfreq, cpufreq table from ECT */ + mif_info("Parsing MIF frequency table...\n"); + err = parse_ect(mld, "MIF"); + if (err < 0) + mif_err("Can't get MIF frequency table!!!!!\n"); + + mif_info("Parsing CP_CPU frequency table...\n"); + err = parse_ect(mld, "CP_CPU"); + if (err < 0) + mif_err("Can't get CP_CPU frequency table!!!!!\n"); + + mif_info("Parsing CP frequency table...\n"); + err = parse_ect(mld, "CP"); + if (err < 0) + mif_err("Can't get CP frequency table!!!!!\n"); + + mif_info("Parsing CP_EM frequency table...\n"); + err = parse_ect(mld, "CP_EM"); + if (err < 0) + mif_err("Can't get CP_EM frequency table!!!!!\n"); + + mif_info("Parsing CP_MCW frequency table...\n"); + err = parse_ect(mld, "CP_MCW"); + if (err < 0) + mif_err("Can't get CP_MCW frequency table!!!!!\n"); + + return 0; +} + +struct link_device *create_link_device(struct platform_device *pdev, u32 link_type) +{ + struct modem_data *modem; + struct mem_link_device *mld; + struct link_device *ld; + int err; + u32 cp_num; + + mif_info("+++\n"); + + /** + * Get the modem (platform) data + */ + modem = (struct modem_data *)pdev->dev.platform_data; + if (!modem) { + mif_err("ERR! modem == NULL\n"); + return NULL; + } + + if (!modem->mbx) { + mif_err("%s: ERR! mbx == NULL\n", modem->link_name); + return NULL; + } + + if (modem->ipc_version < SIPC_VER_50) { + mif_err("%s<->%s: ERR! IPC version %d < SIPC_VER_50\n", + modem->link_name, modem->name, modem->ipc_version); + return NULL; + } - ld->start_timers = shmem_start_timers; - ld->stop_timers = shmem_stop_timers; + mif_info("MODEM:%s LINK:%s\n", modem->name, modem->link_name); - ld->handover_block_info = update_handover_block_info; + /* + * Alloc an instance of mem_link_device structure + */ + mld = kzalloc(sizeof(struct mem_link_device), GFP_KERNEL); + if (!mld) { + mif_err("%s<->%s: ERR! mld kzalloc fail\n", + modem->link_name, modem->name); + return NULL; + } + + /* + * Retrieve modem-specific attributes value + */ + mld->attrs = modem->link_attrs; + mif_info("link_attrs:0x%08lx\n", mld->attrs); + + /*==================================================================== + * Initialize "memory snapshot buffer (MSB)" framework + *==================================================================== + */ + if (msb_init() < 0) { + mif_err("%s<->%s: ERR! msb_init() fail\n", + modem->link_name, modem->name); + goto error; + } + + /*==================================================================== + * Set attributes as a "link_device" + *==================================================================== + */ + ld = &mld->link_dev; + err = set_ld_attr(pdev, link_type, modem, mld, ld); + if (err) + goto error; init_dummy_netdev(&mld->dummy_net); netif_napi_add(&mld->dummy_net, &mld->mld_napi, mld_rx_int_poll, NAPI_POLL_WEIGHT); napi_enable(&mld->mld_napi); - atomic_set(&mld->stop_napi_poll, 0); INIT_LIST_HEAD(&ld->list); @@ -4012,19 +4012,19 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty goto error; if (mld->attrs & LINK_ATTR_DPRAM_MAGIC) { - mif_err("%s<->%s: LINK_ATTR_DPRAM_MAGIC\n", + mif_info("%s<->%s: LINK_ATTR_DPRAM_MAGIC\n", ld->name, modem->name); mld->dpram_magic = true; } -#if IS_ENABLED(CONFIG_LINK_CONTROL_MSG_IOSM) - mld->iosm = true; - mld->cmd_handler = iosm_event_bh; - INIT_WORK(&mld->iosm_w, iosm_event_work); -#else + mld->cmd_handler = shmem_cmd_handler; -#endif spin_lock_init(&mld->state_lock); + mutex_init(&mld->vmap_lock); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + mutex_init(&mld->clatinfo_lock); +#endif + mld->state = LINK_STATE_OFFLINE; /* @@ -4079,294 +4079,70 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty * Initialize SHMEM maps for BOOT (physical map -> logical map) */ cp_num = ld->mdm_data->cp_num; -#if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) - if (link_type == LINKDEV_SHMEM) { - mld->boot_size = cp_shmem_get_size(cp_num, SHMEM_CP) + - cp_shmem_get_size(cp_num, SHMEM_VSS); - mld->boot_base = NULL; - mif_err("boot_base=NULL, boot_size=%lu\n", - (unsigned long)mld->boot_size); - } -#endif - - /* - * Initialize SHMEM maps for IPC (physical map -> logical map) - */ - mld->size = cp_shmem_get_size(cp_num, SHMEM_IPC); -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - mld->base = cp_shmem_get_nc_region(cp_shmem_get_base(cp_num, SHMEM_IPC), SZ_2M); -#else - mld->base = cp_shmem_get_region(cp_num, SHMEM_IPC); -#endif - -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - mld->hiprio_base = cp_shmem_get_nc_region(cp_shmem_get_base(cp_num, SHMEM_IPC) - + modem->legacy_raw_qos_buffer_offset, modem->legacy_raw_qos_txq_size - + modem->legacy_raw_qos_rxq_size); -#endif - if (!mld->base) { - mif_err("Failed to vmap ipc_region\n"); + err = init_shmem_maps(link_type, modem, mld, ld, cp_num); + if (err) goto error; - } - mif_err("ipc_base=%pK, ipc_size=%lu\n", - mld->base, (unsigned long)mld->size); - - switch (link_type) { - case LINKDEV_SHMEM: - /* - * Initialize SHMEM maps for VSS (physical map -> logical map) - */ - mld->vss_base = cp_shmem_get_region(cp_num, SHMEM_VSS); - if (!mld->vss_base) { - mif_err("Failed to vmap vss_region\n"); - goto error; - } - mif_err("vss_base=%pK\n", mld->vss_base); - - /* - * Initialize memory maps for ACPM (physical map -> logical map) - */ - np_acpm = of_find_node_by_name(NULL, "acpm_ipc"); - if (!np_acpm) - break; - - of_property_read_u32(np_acpm, "dump-size", &mld->acpm_size); - of_property_read_u32(np_acpm, "dump-base", &acpm_addr); - mld->acpm_base = cp_shmem_get_nc_region(acpm_addr, mld->acpm_size); - if (!mld->acpm_base) { - mif_err("Failed to vmap acpm_region\n"); - goto error; - } - mif_err("acpm_base=%pK acpm_size:0x%X\n", mld->acpm_base, - mld->acpm_size); - break; - default: - break; - } - - ld->link_type = link_type; - create_legacy_link_device(mld); - - if (ld->sbd_ipc) { - hrtimer_init(&mld->sbd_tx_timer, - CLOCK_MONOTONIC, HRTIMER_MODE_REL); - mld->sbd_tx_timer.function = sbd_tx_timer_func; - - hrtimer_init(&mld->sbd_print_timer, - CLOCK_MONOTONIC, HRTIMER_MODE_REL); - mld->sbd_print_timer.function = sbd_print; - - err = create_sbd_link_device(ld, - &mld->sbd_link_dev, mld->base, mld->size); - if (err < 0) - goto error; - } /* * Info region */ - if (modem->offset_ap_version) - mld->ap_version = (u32 __iomem *)(mld->base + modem->offset_ap_version); - if (modem->offset_cp_version) - mld->cp_version = (u32 __iomem *)(mld->base + modem->offset_cp_version); - if (modem->offset_cmsg_offset) { - mld->cmsg_offset = (u32 __iomem *)(mld->base + modem->offset_cmsg_offset); - cmsg_base = mld->base + modem->cmsg_offset; - iowrite32(modem->cmsg_offset, mld->cmsg_offset); - } else { - cmsg_base = mld->base; - } - - if (modem->offset_srinfo_offset) { - mld->srinfo_offset = (u32 __iomem *)(mld->base + modem->offset_srinfo_offset); - iowrite32(modem->srinfo_offset, mld->srinfo_offset); - } - if (modem->offset_clk_table_offset) { - mld->clk_table_offset = (u32 __iomem *)(mld->base + modem->offset_clk_table_offset); - iowrite32(modem->clk_table_offset, mld->clk_table_offset); - } - if (modem->offset_buff_desc_offset) { - mld->buff_desc_offset = (u32 __iomem *)(mld->base + modem->offset_buff_desc_offset); - iowrite32(modem->buff_desc_offset, mld->buff_desc_offset); - } - - mld->srinfo_base = (u32 __iomem *)(mld->base + modem->srinfo_offset); - mld->srinfo_size = modem->srinfo_size; - mld->clk_table = (u32 __iomem *)(mld->base + modem->clk_table_offset); - - if (ld->capability_check) { - /* AP/CP capability */ - mld->capability_offset = - (u32 __iomem *)(mld->base + modem->offset_capability_offset); - iowrite32(modem->capability_offset, mld->capability_offset); - - mld->ap_capability_0_offset = - (u32 __iomem *)(mld->base + modem->capability_offset); - mld->cp_capability_0_offset = - (u32 __iomem *)(mld->base + modem->capability_offset + 0x4); - mld->ap_capability_1_offset = - (u32 __iomem *)(mld->base + modem->capability_offset + 0x8); - mld->cp_capability_1_offset = - (u32 __iomem *)(mld->base + modem->capability_offset + 0xC); - - /* Initial value */ - iowrite32(0, mld->ap_capability_0_offset); - iowrite32(0, mld->cp_capability_0_offset); - iowrite32(0, mld->ap_capability_1_offset); - iowrite32(0, mld->cp_capability_1_offset); - } - - construct_ctrl_msg(&mld->cp2ap_msg, modem->cp2ap_msg, cmsg_base); - construct_ctrl_msg(&mld->ap2cp_msg, modem->ap2cp_msg, cmsg_base); - construct_ctrl_msg(&mld->cp2ap_united_status, modem->cp2ap_united_status, cmsg_base); - construct_ctrl_msg(&mld->ap2cp_united_status, modem->ap2cp_united_status, cmsg_base); - construct_ctrl_msg(&mld->ap2cp_kerneltime, modem->ap2cp_kerneltime, cmsg_base); - construct_ctrl_msg(&mld->ap2cp_kerneltime_sec, modem->ap2cp_kerneltime_sec, cmsg_base); - construct_ctrl_msg(&mld->ap2cp_kerneltime_usec, modem->ap2cp_kerneltime_usec, cmsg_base); + err = init_info_region(modem, mld, ld); + if (err) + goto error; /* * Retrieve SHMEM MBOX#, IRQ#, etc. */ - mld->irq_cp2ap_msg = modem->mbx->irq_cp2ap_msg; mld->int_ap2cp_msg = modem->mbx->int_ap2cp_msg; + mld->irq_cp2ap_msg = modem->mbx->irq_cp2ap_msg; mld->sbi_cp_status_mask = modem->sbi_cp_status_mask; mld->sbi_cp_status_pos = modem->sbi_cp_status_pos; + mld->irq_cp2ap_status = modem->mbx->irq_cp2ap_status; + mld->sbi_cp2ap_wakelock_mask = modem->sbi_cp2ap_wakelock_mask; mld->sbi_cp2ap_wakelock_pos = modem->sbi_cp2ap_wakelock_pos; + mld->irq_cp2ap_wakelock = modem->mbx->irq_cp2ap_wakelock; + mld->sbi_cp_rat_mode_mask = modem->sbi_cp2ap_rat_mode_mask; mld->sbi_cp_rat_mode_pos = modem->sbi_cp2ap_rat_mode_pos; + mld->irq_cp2ap_rat_mode = modem->mbx->irq_cp2ap_rat_mode; - mld->ap_capability_0 = modem->ap_capability_0; - mld->ap_capability_1 = modem->ap_capability_1; - - /* - * Register interrupt handlers - */ -#if IS_ENABLED(CONFIG_MCU_IPC) - if (ld->interrupt_types == INTERRUPT_MAILBOX) { - err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, mld->irq_cp2ap_msg, - shmem_irq_handler, mld); - if (err) { - mif_err("%s: ERR! cp_mbox_register_handler(MBOX_IRQ_IDX_0, %u) fail (%d)\n", - ld->name, mld->irq_cp2ap_msg, err); - goto error; - } - } -#endif - -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) - /* Set doorbell interrupt value for separating interrupts */ - mld->intval_ap2cp_msg = modem->mbx->int_ap2cp_msg + DOORBELL_INT_ADD; - mld->intval_ap2cp_status = modem->mbx->int_ap2cp_status - + DOORBELL_INT_ADD; - mld->intval_ap2cp_active = modem->mbx->int_ap2cp_active - + DOORBELL_INT_ADD; + mld->pktproc_use_36bit_addr = modem->pktproc_use_36bit_addr; +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + mld->int_ap2cp_clatinfo_send = modem->mbx->int_ap2cp_clatinfo_send; + mld->irq_cp2ap_clatinfo_ack = modem->mbx->irq_cp2ap_clatinfo_ack; #endif /** - * Retrieve SHMEM MBOX# and IRQ# for wakelock + * For TX Flow-control command from CP */ - mld->irq_cp2ap_wakelock = modem->mbx->irq_cp2ap_wakelock; + mld->tx_flowctrl_cmd = 0; - mld->ws = cpif_wake_lock_register(ld->dev, ld->name); - if (mld->ws == NULL) { - mif_err("%s: wakeup_source_register fail\n", ld->name); - goto error; - } + /* Link mem_link_device to modem_data */ + modem->mld = mld; -#if IS_ENABLED(CONFIG_MCU_IPC) - if (ld->interrupt_types == INTERRUPT_MAILBOX) { - err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, mld->irq_cp2ap_wakelock, - shmem_cp2ap_wakelock_handler, mld); - if (err) { - mif_err("%s: ERR! cp_mbox_register_handler(MBOX_IRQ_IDX_0, %u) fail (%d)\n", - ld->name, mld->irq_cp2ap_wakelock, err); - goto error; - } - } -#endif + mld->tx_period_ns = TX_PERIOD_MS * NSEC_PER_MSEC; - /** - * Retrieve SHMEM MBOX# and IRQ# for RAT_MODE - */ -#if IS_ENABLED(CONFIG_MCU_IPC) && IS_ENABLED(CONFIG_PCI_EXYNOS) - mld->irq_cp2ap_rat_mode = modem->mbx->irq_cp2ap_rat_mode; + mld->pass_skb_to_net = pass_skb_to_net; + mld->pass_skb_to_demux = pass_skb_to_demux; - err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, mld->irq_cp2ap_rat_mode, - shmem_cp2ap_rat_mode_handler, mld); + /* + * Register interrupt handlers + */ +#if IS_ENABLED(CONFIG_MCU_IPC) + err = register_irq_handler(modem, mld, ld); if (err) { - mif_err("%s: ERR! cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, %u) fail (%d)\n", - ld->name, mld->irq_cp2ap_rat_mode, err); + mif_err("register_irq_handler() error %d\n", err); goto error; } #endif if (ld->link_type == LINKDEV_SHMEM) { - err = of_property_read_u32(pdev->dev.of_node, "devfreq_use_dfs_max_freq", - &mld->mif_table.use_dfs_max_freq); - if (err) { - mif_err("devfreq_use_dfs_max_freq error:%d\n", err); - goto error; - } - - if (mld->mif_table.use_dfs_max_freq) { - err = of_property_read_u32(pdev->dev.of_node, - "devfreq_cal_id_mif", &mld->mif_table.cal_id_mif); - if (err) { - mif_err("devfreq_cal_id_mif error:%d\n", err); - goto error; - } - } - - /* Parsing devfreq, cpufreq table from ECT */ - mif_info("Parsing MIF frequency table...\n"); - err = parse_ect(mld, "MIF"); - if (err < 0) - mif_err("Can't get MIF frequency table!!!!!\n"); - - mif_info("Parsing CP frequency table...\n"); - err = parse_ect(mld, "CP_CPU"); - if (err < 0) - mif_err("Can't get CP frequency table!!!!!\n"); - - mif_info("Parsing MODEM frequency table...\n"); - err = parse_ect(mld, "CP"); - if (err < 0) - mif_err("Can't get MODEM frequency table!!!!!\n"); - } - - /** - * For TX Flow-control command from CP - */ - construct_ctrl_msg(&mld->ap2cp_handover_block_info, - modem->ap2cp_handover_block_info, cmsg_base); - - mld->irq_cp2ap_status = modem->mbx->irq_cp2ap_status; - mld->tx_flowctrl_cmd = 0; - -#if IS_ENABLED(CONFIG_MCU_IPC) - if (ld->interrupt_types == INTERRUPT_MAILBOX) { - err = cp_mbox_register_handler(CP_MBOX_IRQ_IDX_0, mld->irq_cp2ap_status, - shmem_tx_state_handler, mld); - if (err) { - mif_err("%s: ERR! cp_mbox_register_handler(MBOX_IRQ_IDX_0, %u) fail (%d)\n", - ld->name, mld->irq_cp2ap_status, err); + err = parse_ect_tables(pdev, mld); + if (err) goto error; - } } -#endif - -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) - mld->syscp_info = platform_get_resource(pdev, IORESOURCE_MEM, 0); -#endif - - /* Link mem_link_device to modem_data */ - modem->mld = mld; - - mld->tx_period_ms = TX_PERIOD_MS; - - mld->pass_skb_to_net = pass_skb_to_net; #if IS_ENABLED(CONFIG_CP_PKTPROC) err = pktproc_create(pdev, mld, cp_shmem_get_base(cp_num, SHMEM_PKTPROC), @@ -4378,7 +4154,7 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty #endif #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) - err = pktproc_create_ul(pdev, mld, cp_shmem_get_base(cp_num, SHMEM_PKTPROC_UL), + err = pktproc_create_ul(pdev, mld, cp_shmem_get_base(cp_num, SHMEM_PKTPROC), cp_shmem_get_size(cp_num, SHMEM_PKTPROC_UL)); if (err < 0) { mif_err("pktproc_create_ul() error %d\n", err); @@ -4403,12 +4179,15 @@ struct link_device *create_link_device(struct platform_device *pdev, u32 link_ty if (sysfs_create_group(&pdev->dev.kobj, &napi_group)) mif_err("failed to create sysfs node related napi\n"); - mif_err("---\n"); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + if (sysfs_create_group(&pdev->dev.kobj, &hw_clat_group)) + mif_err("failed to create sysfs node related hw clat\n"); +#endif + + mif_info("---\n"); return ld; error: - //shm_release_regions(); - kfree(mld); mif_err("xxx\n"); return NULL; diff --git a/drivers/soc/google/cpif/link_device.h b/drivers/soc/google/cpif/link_device.h index d6db63fee91b..1f8ebe613af2 100644 --- a/drivers/soc/google/cpif/link_device.h +++ b/drivers/soc/google/cpif/link_device.h @@ -5,16 +5,46 @@ #include #include "link_device_memory.h" +#include "modem_toe_device.h" -bool check_mem_link_tx_pending(struct mem_link_device *mld); +static inline bool ipc_active(struct mem_link_device *mld) +{ + struct link_device *ld = &mld->link_dev; + struct modem_ctl *mc = ld->mc; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) -int request_pcie_msi_int(struct link_device *ld, - struct platform_device *pdev); -#endif + if (unlikely(!cp_online(mc))) { + mif_err("%s<->%s: %s.state %s != ONLINE <%ps>\n", + ld->name, mc->name, mc->name, mc_state(mc), CALLER); + return false; + } + + if (mld->dpram_magic) { + unsigned int magic = ioread32(mld->legacy_link_dev.magic); + unsigned int mem_access = ioread32(mld->legacy_link_dev.mem_access); + + if (magic != ld->magic_ipc || mem_access != 1) { + mif_err("%s<->%s: ERR! magic:0x%X access:%d <%ps>\n", + ld->name, mc->name, magic, mem_access, CALLER); + return false; + } + } + + if (atomic_read(&mld->forced_cp_crash)) { + mif_err("%s<->%s: ERR! forced_cp_crash:%d <%ps>\n", + ld->name, mc->name, atomic_read(&mld->forced_cp_crash), + CALLER); + return false; + } + + return true; +} + +bool check_mem_link_tx_pending(struct mem_link_device *mld); +irqreturn_t shmem_tx_state_handler(int irq, void *data); +irqreturn_t shmem_irq_handler(int irq, void *data); -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) -void shmem_pr_sbdcplog(struct timer_list *t); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) +bool shmem_ap2cp_write_clatinfo(struct mem_link_device *mld, struct clat_info *clat); #endif #endif /* end of __LINK_DEVICE_H__ */ diff --git a/drivers/soc/google/cpif/link_device_memory.h b/drivers/soc/google/cpif/link_device_memory.h index 7b837a25cf68..daea450709d0 100644 --- a/drivers/soc/google/cpif/link_device_memory.h +++ b/drivers/soc/google/cpif/link_device_memory.h @@ -23,12 +23,10 @@ #include #include #include -#include -#include #include +#include #include "modem_prj.h" -#include "modem_utils.h" #include "include/circ_queue.h" #include "include/sbd.h" #include "include/sipc5.h" @@ -86,8 +84,6 @@ enum mem_iface_type { #define CMD_SILENT_NV_REBUILD 0x000E #define CMD_NORMAL_POWER_OFF 0x000F -#define DATALLOC_PERIOD_MS 2 /* 2 ms */ - /*============================================================================*/ #define MAX_SKB_TXQ_DEPTH 1024 #define TX_PERIOD_MS 1 /* 1 ms */ @@ -96,8 +92,11 @@ enum mem_iface_type { #define RES_ACK_WAIT_TIMEOUT 10 /* 10 ms */ -#define TXQ_STOP_MASK (0x1<<0) -#define TX_SUSPEND_MASK (0x1<<1) +enum tx_flowctrl_mask_bit { + TXQ_STOP_MASK = 1, + TX_SUSPEND_MASK, +}; + #define SHM_FLOWCTL_BIT BIT(2) /*============================================================================*/ @@ -106,14 +105,9 @@ enum mem_iface_type { /*============================================================================*/ #define SHMEM_SRINFO_DATA_STR 64 -#if !IS_ENABLED(CONFIG_SBD_BOOTLOG) #define SHMEM_BOOTLOG_BASE 0xC00 #define SHMEM_BOOTLOG_BUFF 0x1FF #define SHMEM_BOOTLOG_OFFSET 0x4 -#else -#define SHMEM_BOOTSBDLOG_SIZE 0x1000 /* 4KB */ -#define SHMEM_BOOTSBDLOG_MAIN_BASE 0x400 -#endif /*============================================================================*/ struct __packed mem_snapshot { @@ -127,8 +121,8 @@ struct __packed mem_snapshot { unsigned int magic; unsigned int access; - unsigned int head[MAX_SIPC_MAP][MAX_DIR]; - unsigned int tail[MAX_SIPC_MAP][MAX_DIR]; + unsigned int head[IPC_MAP_MAX][MAX_DIR]; + unsigned int tail[IPC_MAP_MAX][MAX_DIR]; u16 int2ap; u16 int2cp; @@ -189,24 +183,25 @@ struct mem_link_device { * Flags */ bool dpram_magic; /* DPRAM-style magic code */ - bool iosm; /* IOSM message */ /** * {physical address, size, virtual address} for BOOT region */ phys_addr_t boot_start; size_t boot_size; - struct page **boot_pages; /* pointer to the page table for vmap */ u8 __iomem *boot_base; + u32 boot_img_offset; /* From IPC base */ + u32 boot_img_size; /** * {physical address, size, virtual address} for IPC region */ phys_addr_t start; size_t size; - struct page **pages; /* pointer to the page table for vmap */ u8 __iomem *base; /* virtual address of ipc mem start */ +#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) u8 __iomem *hiprio_base; /* virtual address of priority queue start */ +#endif /** * vss region for dump @@ -219,60 +214,49 @@ struct mem_link_device { u8 __iomem *acpm_base; int acpm_size; - /** - * CP Binary size for CRC checking - */ - u32 cp_binary_size; - - /** - * (u32 *) syscp_alive[0] = Magic Code, Version - * (u32 *) syscp_alive[1] = CP Reserved Size - * (u32 *) syscp_alive[2] = Shared Mem Size - */ - struct resource *syscp_info; - /* Boot link device */ struct legacy_link_device legacy_link_dev; /* sbd link device */ struct sbd_link_device sbd_link_dev; - struct work_struct iosm_w; /** * GPIO#, MBOX#, IRQ# for IPC */ - unsigned int mbx_cp2ap_msg; /* MBOX# for IPC RX */ - unsigned int irq_cp2ap_msg; /* IRQ# for IPC RX */ + unsigned int int_ap2cp_msg; /* INTR# for IPC TX */ + unsigned int irq_cp2ap_msg; /* IRQ# for IPC RX */ unsigned int sbi_cp2ap_wakelock_mask; unsigned int sbi_cp2ap_wakelock_pos; - - unsigned int mbx_ap2cp_msg; /* MBOX# for IPC TX */ - unsigned int int_ap2cp_msg; /* INTR# for IPC TX */ + unsigned int irq_cp2ap_wakelock; /* IRQ# for wakelock */ unsigned int sbi_cp_status_mask; unsigned int sbi_cp_status_pos; + unsigned int irq_cp2ap_status; /* IRQ# for TX FLOWCTL */ unsigned int total_freq_table_count; struct freq_table mif_table; + struct freq_table cp_cpu_table; struct freq_table cp_table; - struct freq_table modem_table; + struct freq_table cp_em_table; + struct freq_table cp_mcw_table; - unsigned int irq_cp2ap_wakelock; /* INTR# for wakelock */ + unsigned int sbi_cp_rat_mode_mask; /* MBOX# for pcie */ + unsigned int sbi_cp_rat_mode_pos; /* MBOX# for pcie */ + unsigned int irq_cp2ap_rat_mode; /* IRQ# for pcie */ - unsigned int sbi_cp_rat_mode_mask; /* MBOX# for pcie */ - unsigned int sbi_cp_rat_mode_pos; /* MBOX# for pcie */ - unsigned int irq_cp2ap_rat_mode; /* INTR# for pcie */ - - unsigned int irq_cp2ap_change_ul_path; - - unsigned int mbx_cp2ap_status; /* MBOX# for TX FLOWCTL */ - unsigned int irq_cp2ap_status; /* INTR# for TX FLOWCTL */ unsigned int tx_flowctrl_cmd; struct wakeup_source *ws; +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + unsigned int int_ap2cp_clatinfo_send; + unsigned int irq_cp2ap_clatinfo_ack; + + struct mutex clatinfo_lock; +#endif + /** * Member variables for TX & RX */ @@ -291,8 +275,9 @@ struct mem_link_device { * Member variables for CP booting and crash dump */ struct delayed_work bootdump_rx_dwork; - struct std_dload_info img_info; /* Information of each binary image */ - atomic_t cp_boot_done; + atomic_t init_end_cnt; + atomic_t init_end_busy; + int last_init_end_cnt; /** * Mandatory methods for the common memory-type interface framework @@ -310,18 +295,7 @@ struct mem_link_device { void (*debug_info)(void); void (*cmd_handler)(struct mem_link_device *mld, u16 cmd); -#ifdef DEBUG_MODEM_IF - /* for logging MEMORY dump */ - struct work_struct dump_work; - char dump_path[MIF_MAX_PATH_LEN]; -#endif - -#ifdef DEBUG_MODEM_IF - struct dentry *dbgfs_dir; - struct debugfs_blob_wrapper mem_dump_blob; - struct dentry *dbgfs_frame; -#endif - unsigned int tx_period_ms; + unsigned int tx_period_ns; unsigned int force_use_memcpy; unsigned int memcpy_packet_count; unsigned int zeromemcpy_packet_count; @@ -330,21 +304,17 @@ struct mem_link_device { struct timer_list crash_ack_timer; spinlock_t state_lock; + /* protects boot_base nc region */ + struct mutex vmap_lock; enum link_state state; struct net_device dummy_net; struct napi_struct mld_napi; - atomic_t stop_napi_poll; unsigned int rx_int_enable; unsigned int rx_int_count; unsigned int rx_poll_count; unsigned long long rx_int_disabled_time; - /* Doorbell interrupt value to separate interrupt */ - unsigned int intval_ap2cp_msg; - unsigned int intval_ap2cp_status; - unsigned int intval_ap2cp_active; - /* Location for arguments in shared memory */ u32 __iomem *ap_version; u32 __iomem *cp_version; @@ -354,46 +324,67 @@ struct mem_link_device { u32 __iomem *buff_desc_offset; u32 __iomem *capability_offset; - u32 __iomem *ap_capability_0_offset; - u32 __iomem *cp_capability_0_offset; - u32 __iomem *ap_capability_1_offset; - u32 __iomem *cp_capability_1_offset; + u32 __iomem *ap_capability_offset[AP_CP_CAP_PARTS]; + u32 __iomem *cp_capability_offset[AP_CP_CAP_PARTS]; /* Location for control messages in shared memory */ struct ctrl_msg ap2cp_msg; struct ctrl_msg cp2ap_msg; struct ctrl_msg ap2cp_united_status; struct ctrl_msg cp2ap_united_status; +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + struct ctrl_msg ap2cp_clatinfo_xlat_v4_addr; + struct ctrl_msg ap2cp_clatinfo_xlat_addr_0; + struct ctrl_msg ap2cp_clatinfo_xlat_addr_1; + struct ctrl_msg ap2cp_clatinfo_xlat_addr_2; + struct ctrl_msg ap2cp_clatinfo_xlat_addr_3; + struct ctrl_msg ap2cp_clatinfo_index; +#endif struct ctrl_msg ap2cp_kerneltime; /* for DRAM_V1 and MAILBOX_SR */ struct ctrl_msg ap2cp_kerneltime_sec; /* for DRAM_V2 */ struct ctrl_msg ap2cp_kerneltime_usec; /* for DRAM_V2 */ struct ctrl_msg ap2cp_handover_block_info; - u32 __iomem *doorbell_addr; - struct pci_dev *s51xx_pdev; +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) + /* Doorbell */ + unsigned int intval_ap2cp_msg; + unsigned int intval_ap2cp_pcie_link_ack; + /* MSI */ + u8 __iomem *msi_reg_base; + bool msi_irq_enabled; int msi_irq_base; - int msi_irq_base_enabled; + bool msi_irq_base_wake; + u32 msi_irq_base_cpu; + u32 msi_irq_q_cpu[PKTPROC_MAX_QUEUE]; +#endif u32 __iomem *srinfo_base; u32 srinfo_size; u32 __iomem *clk_table; - u32 ap_capability_0; - u32 cp_capability_0; - u32 ap_capability_1; - u32 cp_capability_1; + u32 ap_capability[AP_CP_CAP_PARTS]; + u32 cp_capability[AP_CP_CAP_PARTS]; int (*pass_skb_to_net)(struct mem_link_device *mld, struct sk_buff *skb); + int (*pass_skb_to_demux)(struct mem_link_device *mld, struct sk_buff *skb); struct pktproc_adaptor pktproc; #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) struct pktproc_adaptor_ul pktproc_ul; #endif - struct cpboot_spi *boot_spi; + int pktproc_use_36bit_addr; + + int spi_bus_num; struct cpif_tpmon *tpmon; + + struct toe_ctrl_t *tc; + +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + bool disable_hw_clat; +#endif }; #define to_mem_link_device(ld) \ @@ -612,6 +603,8 @@ static inline int construct_ctrl_msg(struct ctrl_msg *cmsg, u32 *arr_from_dt, case DRAM_V2: cmsg->addr = (u32 __iomem *)(base + arr_from_dt[1]); break; + case CMSG_TYPE_NONE: + break; default: mif_err("ERR! wrong type for ctrl msg\n"); return -EINVAL; @@ -750,6 +743,19 @@ static inline void send_ipc_irq(struct mem_link_device *mld, u16 val) mld->send_ap2cp_irq(mld, val); } +static inline void send_ipc_irq_debug(struct mem_link_device *mld, u16 val) +{ +#if IS_ENABLED(CONFIG_MCU_IPC) + if (mld->ap2cp_msg.type == MAILBOX_SR) + cp_mbox_dump_sr(); +#endif + send_ipc_irq(mld, val); +#if IS_ENABLED(CONFIG_MCU_IPC) + if (mld->ap2cp_msg.type == MAILBOX_SR) + cp_mbox_dump_sr(); +#endif +} + void mem_irq_handler(struct mem_link_device *mld, struct mst_buff *msb); /*============================================================================*/ @@ -774,26 +780,19 @@ int mem_reset_ipc_link(struct mem_link_device *mld); void mem_cmd_handler(struct mem_link_device *mld, u16 cmd); /*============================================================================*/ -void sbd_txq_stop(struct sbd_ring_buffer *rb); -void sbd_txq_start(struct sbd_ring_buffer *rb); - -int sbd_under_tx_flow_ctrl(struct sbd_ring_buffer *rb); -int sbd_check_tx_flow_ctrl(struct sbd_ring_buffer *rb); - #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) void pktproc_ul_q_stop(struct pktproc_queue_ul *q); -void pktproc_ul_q_start(struct pktproc_queue_ul *q); -int pktproc_under_ul_flow_ctrl(struct pktproc_queue_ul *q); -int pktproc_check_ul_flow_ctrl(struct pktproc_queue_ul *q); +int pktproc_ul_q_check_busy(struct pktproc_queue_ul *q); #endif -void tx_flowctrl_suspend(struct mem_link_device *mld); -void tx_flowctrl_resume(struct mem_link_device *mld); +void sbd_txq_stop(struct sbd_ring_buffer *rb); +int sbd_txq_check_busy(struct sbd_ring_buffer *rb); + void txq_stop(struct mem_link_device *mld, struct legacy_ipc_device *dev); -void txq_start(struct mem_link_device *mld, struct legacy_ipc_device *dev); +int txq_check_busy(struct mem_link_device *mld, struct legacy_ipc_device *dev); -int under_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *dev); -int check_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *dev); +void tx_flowctrl_suspend(struct mem_link_device *mld); +void tx_flowctrl_resume(struct mem_link_device *mld); void send_req_ack(struct mem_link_device *mld, struct legacy_ipc_device *dev); void recv_res_ack(struct mem_link_device *mld, struct legacy_ipc_device *dev, @@ -839,33 +838,6 @@ static inline struct sk_buff *mem_alloc_skb(unsigned int len) } /*============================================================================*/ -/* direction: CP -> AP */ -#define IOSM_C2A_MDM_READY 0x80 -#define IOSM_C2A_CONF_CH_RSP 0xA3 /* answer of flow control msg */ -#define IOSM_C2A_STOP_TX_CH 0xB0 -#define IOSM_C2A_START_TX_CH 0xB1 -#define IOSM_C2A_ACK 0xE0 -#define IOSM_C2A_NACK 0xE1 - -/* direction: AP -> CP */ -#define IOSM_A2C_AP_READY 0x00 -#define IOSM_A2C_CONF_CH_REQ 0x22 /* flow control on/off */ -#define IOSM_A2C_OPEN_CH 0x24 -#define IOSM_A2C_CLOSE_CH 0x25 -#define IOSM_A2C_STOP_TX_CH 0x30 -#define IOSM_A2C_START_TX_CH 0x30 -#define IOSM_A2C_ACK 0x60 -#define IOSM_A2C_NACK 0x61 - -#define IOSM_TRANS_ID_MAX 255 -#define IOSM_MSG_AREA_SIZE (CTRL_RGN_SIZE / 2) -#define IOSM_MSG_TX_OFFSET CMD_RGN_OFFSET -#define IOSM_MSG_RX_OFFSET (CMD_RGN_OFFSET + IOSM_MSG_AREA_SIZE) -#define IOSM_MSG_DESC_OFFSET (CMD_RGN_OFFSET + CMD_RGN_SIZE) - -void tx_iosm_message(struct mem_link_device *mld, u8 id, u32 *args); -void iosm_event_work(struct work_struct *work); -void iosm_event_bh(struct mem_link_device *mld, u16 cmd); #define NET_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) diff --git a/drivers/soc/google/cpif/link_device_memory_debug.c b/drivers/soc/google/cpif/link_device_memory_debug.c index 0c53e4c55f55..5d3005564627 100644 --- a/drivers/soc/google/cpif/link_device_memory_debug.c +++ b/drivers/soc/google/cpif/link_device_memory_debug.c @@ -33,7 +33,7 @@ void print_req_ack(struct mem_link_device *mld, struct mem_snapshot *mst, unsigned int usage = circ_get_usage(qsize, in, out); unsigned int space = circ_get_space(qsize, in, out); - mif_err("REQ_ACK: %s%s%s: %s_%s.%d {in:%u out:%u usage:%u space:%u}\n", + mif_info("REQ_ACK: %s%s%s: %s_%s.%d {in:%u out:%u usage:%u space:%u}\n", ld->name, arrow(dir), mc->name, dev->name, q_dir(dir), dev->req_ack_cnt[dir], in, out, usage, space); #endif @@ -53,7 +53,7 @@ void print_res_ack(struct mem_link_device *mld, struct mem_snapshot *mst, unsigned int usage = circ_get_usage(qsize, in, out); unsigned int space = circ_get_space(qsize, in, out); - mif_err("RES_ACK: %s%s%s: %s_%s.%d {in:%u out:%u usage:%u space:%u}\n", + mif_info("RES_ACK: %s%s%s: %s_%s.%d {in:%u out:%u usage:%u space:%u}\n", ld->name, arrow(dir), mc->name, dev->name, q_dir(opp_dir), dev->req_ack_cnt[opp_dir], in, out, usage, space); #endif @@ -61,33 +61,29 @@ void print_res_ack(struct mem_link_device *mld, struct mem_snapshot *mst, void print_mem_snapshot(struct mem_link_device *mld, struct mem_snapshot *mst) { -#ifdef DEBUG_MODEM_IF struct link_device *ld = &mld->link_dev; - mif_err("%s: [%s] ACC{%X %d} FMT{TI:%u TO:%u RI:%u RO:%u} RAW{TI:%u TO:%u RI:%u RO:%u} INTR{RX:0x%X TX:0x%X}\n", + mif_info("%s: [%s] ACC{%X %d} FMT{TI:%u TO:%u RI:%u RO:%u} RAW{TI:%u TO:%u RI:%u RO:%u} INTR{RX:0x%X TX:0x%X}\n", ld->name, ipc_dir(mst->dir), mst->magic, mst->access, mst->head[IPC_MAP_FMT][TX], mst->tail[IPC_MAP_FMT][TX], mst->head[IPC_MAP_FMT][RX], mst->tail[IPC_MAP_FMT][RX], mst->head[IPC_MAP_NORM_RAW][TX], mst->tail[IPC_MAP_NORM_RAW][TX], mst->head[IPC_MAP_NORM_RAW][RX], mst->tail[IPC_MAP_NORM_RAW][RX], mst->int2ap, mst->int2cp); -#endif } void print_dev_snapshot(struct mem_link_device *mld, struct mem_snapshot *mst, struct legacy_ipc_device *dev) { -#ifdef DEBUG_MODEM_IF struct link_device *ld = &mld->link_dev; enum legacy_ipc_map id = dev->id; - if (id >= MAX_SIPC_MAP) + if (id >= IPC_MAP_MAX) return; - mif_err("%s: [%s] %s | TXQ{in:%u out:%u} RXQ{in:%u out:%u} | INTR{0x%02X}\n", + mif_info("%s: [%s] %s | TXQ{in:%u out:%u} RXQ{in:%u out:%u} | INTR{0x%02X}\n", ld->name, ipc_dir(mst->dir), dev->name, mst->head[id][TX], mst->tail[id][TX], mst->head[id][RX], mst->tail[id][RX], (mst->dir == RX) ? mst->int2ap : mst->int2cp); -#endif } diff --git a/drivers/soc/google/cpif/link_device_memory_flow_control.c b/drivers/soc/google/cpif/link_device_memory_flow_control.c index 5ebae8bc138c..7b8bc937ac24 100644 --- a/drivers/soc/google/cpif/link_device_memory_flow_control.c +++ b/drivers/soc/google/cpif/link_device_memory_flow_control.c @@ -23,295 +23,176 @@ #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) void pktproc_ul_q_stop(struct pktproc_queue_ul *q) { - if (atomic_read(&q->busy) == 0) { - struct link_device *ld = &(q->mld->link_dev); - - if (!test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - - atomic_set(&q->busy, 1); - set_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); - stop_net_ifaces(ld); - - spin_unlock_irqrestore(&q->lock, flags); + struct link_device *ld = &q->mld->link_dev; + unsigned long flags; - /* Currently, - * CP is not doing anything when CP receive req_ack - * command from AP. So, we'll skip this scheme. - */ - /* send_req_ack(mld, dev); */ - mif_info_limited("PKTPROC UL QUEUE %d tx_flowctrl=0x%04lx\n", - q->q_idx, ld->tx_flowctrl_mask); - } + spin_lock_irqsave(&ld->netif_lock, flags); + if (!atomic_read(&q->busy)) { + mif_info("Requested stop on PKTPROC UL QUEUE %d\n", q->q_idx); + atomic_set(&q->busy, 1); + stop_net_ifaces(ld, TXQ_STOP_MASK); } + spin_unlock_irqrestore(&ld->netif_lock, flags); } -void pktproc_ul_q_start(struct pktproc_queue_ul *q) +static void pktproc_ul_q_start(struct pktproc_queue_ul *q) { - if (atomic_read(&q->busy) > 0) { - struct link_device *ld = &q->mld->link_dev; - - if (test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; - - spin_lock_irqsave(&q->lock, flags); - - atomic_set(&q->busy, 0); - clear_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); + struct link_device *ld = &q->mld->link_dev; + unsigned long flags; - if (ld->tx_flowctrl_mask == 0) { - resume_net_ifaces(ld); - mif_info_limited("PKTPROC UL QUEUE %d,\n" - "tx_flowctrl=0x%04lx\n", - q->q_idx, ld->tx_flowctrl_mask); - } + mif_info("Requested start on PKTPROC UL QUEUE %d\n", q->q_idx); - spin_unlock_irqrestore(&q->lock, flags); - } - } + spin_lock_irqsave(&ld->netif_lock, flags); + atomic_set(&q->busy, 0); + resume_net_ifaces(ld, TXQ_STOP_MASK); + spin_unlock_irqrestore(&ld->netif_lock, flags); } -int pktproc_under_ul_flow_ctrl(struct pktproc_queue_ul *q) -{ - return atomic_read(&q->busy); -} - -int pktproc_check_ul_flow_ctrl(struct pktproc_queue_ul *q) +int pktproc_ul_q_check_busy(struct pktproc_queue_ul *q) { struct link_device *ld = &q->mld->link_dev; - struct modem_ctl *mc = ld->mc; - int busy_count = atomic_read(&q->busy); + int busy_count; unsigned long flags; + spin_lock_irqsave(&ld->netif_lock, flags); + busy_count = atomic_read(&q->busy); + if (unlikely(busy_count)) + atomic_inc(&q->busy); + spin_unlock_irqrestore(&ld->netif_lock, flags); + + if (!busy_count) + return 0; + spin_lock_irqsave(&q->lock, flags); if (pktproc_ul_q_empty(q->q_info)) { spin_unlock_irqrestore(&q->lock, flags); #ifdef DEBUG_MODEM_IF_FLOW_CTRL - if (cp_online(mc)) { - mif_err("PKTPROC UL Queue %d: No RES_ACK,\n" - "but EMPTY (busy_cnt %d)\n", - q->q_idx, busy_count); - } + if (cp_online(ld->mc)) + mif_err("PKTPROC UL Queue %d: EMPTY (busy_cnt %d)\n", q->q_idx, busy_count); #endif pktproc_ul_q_start(q); return 0; } - spin_unlock_irqrestore(&q->lock, flags); - atomic_inc(&q->busy); - - if (cp_online(mc) && count_flood(busy_count, BUSY_COUNT_MASK)) - return -ETIME; - return -EBUSY; } #endif /* CONFIG_CP_PKTPROC_UL */ void sbd_txq_stop(struct sbd_ring_buffer *rb) { - if (rb->ld->is_ps_ch(rb->ch) && atomic_read(&rb->busy) == 0) { - struct link_device *ld = rb->ld; - - if (!test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; - - spin_lock_irqsave(&rb->lock, flags); - - atomic_set(&rb->busy, 1); - set_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); - stop_net_ifaces(ld); + struct link_device *ld = rb->ld; + unsigned long flags; - spin_unlock_irqrestore(&rb->lock, flags); + if (!ld->is_ps_ch(rb->ch)) + return; - /* Currently, - * CP is not doing anything when CP receive req_ack - * command from AP. So, we'll skip this scheme. - */ - /* send_req_ack(mld, dev); */ - mif_info_limited("%s, tx_flowctrl=0x%04lx\n", - rb->iod->name, ld->tx_flowctrl_mask); - } + spin_lock_irqsave(&ld->netif_lock, flags); + if (!atomic_read(&rb->busy)) { + mif_info("Requested stop on rb ch: %d name: %s\n", rb->ch, rb->iod->name); + atomic_set(&rb->busy, 1); + stop_net_ifaces(ld, TXQ_STOP_MASK); } + spin_unlock_irqrestore(&ld->netif_lock, flags); } -void sbd_txq_start(struct sbd_ring_buffer *rb) +static void sbd_txq_start(struct sbd_ring_buffer *rb) { - if (rb->ld->is_ps_ch(rb->ch) && atomic_read(&rb->busy) > 0) { - struct link_device *ld = rb->ld; - - if (test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; - - spin_lock_irqsave(&rb->lock, flags); - - atomic_set(&rb->busy, 0); - clear_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); + struct link_device *ld = rb->ld; + unsigned long flags; - if (ld->tx_flowctrl_mask == 0) { - resume_net_ifaces(ld); - mif_info_limited("%s, tx_flowctrl=0x%04lx\n", - rb->iod->name, ld->tx_flowctrl_mask); - } + if (!ld->is_ps_ch(rb->ch)) + return; - spin_unlock_irqrestore(&rb->lock, flags); - } - } -} + mif_info("Requested start on rb ch: %d name: %s\n", rb->ch, rb->iod->name); -int sbd_under_tx_flow_ctrl(struct sbd_ring_buffer *rb) -{ - return atomic_read(&rb->busy); + spin_lock_irqsave(&ld->netif_lock, flags); + atomic_set(&rb->busy, 0); + resume_net_ifaces(ld, TXQ_STOP_MASK); + spin_unlock_irqrestore(&ld->netif_lock, flags); } -int sbd_check_tx_flow_ctrl(struct sbd_ring_buffer *rb) +int sbd_txq_check_busy(struct sbd_ring_buffer *rb) { struct link_device *ld = rb->ld; - struct modem_ctl *mc = ld->mc; - int busy_count = atomic_read(&rb->busy); + int busy_count; + unsigned long flags; + + spin_lock_irqsave(&ld->netif_lock, flags); + busy_count = atomic_read(&rb->busy); + if (unlikely(busy_count)) + atomic_inc(&rb->busy); + spin_unlock_irqrestore(&ld->netif_lock, flags); + + if (!busy_count) + return 0; if (rb_empty(rb)) { #ifdef DEBUG_MODEM_IF_FLOW_CTRL - if (cp_online(mc)) { - mif_err("%s TXQ: No RES_ACK, but EMPTY (busy_cnt %d)\n", - rb->iod->name, busy_count); - } + if (cp_online(ld->mc)) + mif_err("%s TXQ: EMPTY (busy_cnt %d)\n", rb->iod->name, busy_count); #endif sbd_txq_start(rb); return 0; } - atomic_inc(&rb->busy); - - if (cp_online(mc) && count_flood(busy_count, BUSY_COUNT_MASK)) { - /* Currently, - * CP is not doing anything when CP receive req_ack - * command from AP. So, we'll skip this scheme. - */ - /* send_req_ack(mld, dev); */ - return -ETIME; - } - return -EBUSY; } void txq_stop(struct mem_link_device *mld, struct legacy_ipc_device *dev) -{ -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - if (dev->id == IPC_MAP_HPRIO_RAW && atomic_read(&dev->txq.busy) == 0) { -#else - if (dev->id == IPC_MAP_NORM_RAW && atomic_read(&dev->txq.busy) == 0) { -#endif - struct link_device *ld = &mld->link_dev; - - if (!test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; - - spin_lock_irqsave(&dev->txq.lock, flags); - - atomic_set(&dev->txq.busy, 1); - set_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); - stop_net_ifaces(&mld->link_dev); - - spin_unlock_irqrestore(&dev->txq.lock, flags); - - send_req_ack(mld, dev); - mif_info_limited("%s: %s TXQ BUSY, tx_flowctrl_mask=0x%04lx\n", - ld->name, dev->name, ld->tx_flowctrl_mask); - } - } -} - -void tx_flowctrl_suspend(struct mem_link_device *mld) { struct link_device *ld = &mld->link_dev; + unsigned long flags; + bool ret = false; - if (!test_bit(TX_SUSPEND_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[IPC_MAP_HPRIO_RAW]; -#else - struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[IPC_MAP_NORM_RAW]; -#endif - - spin_lock_irqsave(&dev->txq.lock, flags); - - set_bit(TX_SUSPEND_MASK, &ld->tx_flowctrl_mask); - stop_net_ifaces(&mld->link_dev); - - spin_unlock_irqrestore(&dev->txq.lock, flags); + if (dev->id == IPC_MAP_FMT) + return; - mif_info_limited("%s: %s TX suspended, tx_flowctrl_mask=0x%04lx\n", - ld->name, dev->name, ld->tx_flowctrl_mask); + spin_lock_irqsave(&ld->netif_lock, flags); + if (!atomic_read(&dev->txq.busy)) { + mif_info("Requested stop on dev: %s\n", dev->name); + atomic_set(&dev->txq.busy, 1); + ret = stop_net_ifaces(ld, TXQ_STOP_MASK); } -} - -void txq_start(struct mem_link_device *mld, struct legacy_ipc_device *dev) -{ -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - if (dev->id == IPC_MAP_HPRIO_RAW && atomic_read(&dev->txq.busy) > 0) { -#else - if (dev->id == IPC_MAP_NORM_RAW && atomic_read(&dev->txq.busy) > 0) { -#endif - struct link_device *ld = &mld->link_dev; - - if (test_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; + spin_unlock_irqrestore(&ld->netif_lock, flags); - spin_lock_irqsave(&dev->txq.lock, flags); - - atomic_set(&dev->txq.busy, 0); - clear_bit(TXQ_STOP_MASK, &ld->tx_flowctrl_mask); - - if (ld->tx_flowctrl_mask == 0) { - resume_net_ifaces(&mld->link_dev); - mif_info_limited("%s:%s TXQ restart, tx_flowctrl_mask=0x%04lx\n", - ld->name, dev->name, ld->tx_flowctrl_mask); - } - - spin_unlock_irqrestore(&dev->txq.lock, flags); - } + if (ret) { + /* notify cp that legacy buffer is stuck. required for legacy only */ + send_req_ack(mld, dev); } } -void tx_flowctrl_resume(struct mem_link_device *mld) +static void txq_start(struct mem_link_device *mld, struct legacy_ipc_device *dev) { struct link_device *ld = &mld->link_dev; + unsigned long flags; - if (test_bit(TX_SUSPEND_MASK, &ld->tx_flowctrl_mask)) { - unsigned long flags; -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[IPC_MAP_HPRIO_RAW]; -#else - struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[IPC_MAP_NORM_RAW]; -#endif - - spin_lock_irqsave(&dev->txq.lock, flags); - - clear_bit(TX_SUSPEND_MASK, &ld->tx_flowctrl_mask); - - if (ld->tx_flowctrl_mask == 0) { - resume_net_ifaces(&mld->link_dev); - mif_info_limited("%s:%s TX resumed, tx_flowctrl_mask=0x%04lx\n", - ld->name, dev->name, ld->tx_flowctrl_mask); - } + if (dev->id == IPC_MAP_FMT) + return; - spin_unlock_irqrestore(&dev->txq.lock, flags); - } -} + mif_info("Requested start on dev: %s\n", dev->name); -int under_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *dev) -{ - return atomic_read(&dev->txq.busy); + spin_lock_irqsave(&ld->netif_lock, flags); + atomic_set(&dev->txq.busy, 0); + resume_net_ifaces(ld, TXQ_STOP_MASK); + spin_unlock_irqrestore(&ld->netif_lock, flags); } -int check_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *dev) +int txq_check_busy(struct mem_link_device *mld, struct legacy_ipc_device *dev) { struct link_device *ld = &mld->link_dev; struct modem_ctl *mc = ld->mc; - int busy_count = atomic_read(&dev->txq.busy); + int busy_count; + unsigned long flags; + + spin_lock_irqsave(&ld->netif_lock, flags); + busy_count = atomic_read(&dev->txq.busy); + if (unlikely(busy_count)) + atomic_inc(&dev->txq.busy); + spin_unlock_irqrestore(&ld->netif_lock, flags); + + if (!busy_count) + return 0; if (txq_empty(dev)) { #ifdef DEBUG_MODEM_IF_FLOW_CTRL @@ -324,9 +205,8 @@ int check_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *de return 0; } - atomic_inc(&dev->txq.busy); - if (cp_online(mc) && count_flood(busy_count, BUSY_COUNT_MASK)) { + /* notify cp that legacy buffer is stuck. required for legacy only */ send_req_ack(mld, dev); return -ETIME; } @@ -334,6 +214,26 @@ int check_tx_flow_ctrl(struct mem_link_device *mld, struct legacy_ipc_device *de return -EBUSY; } +void tx_flowctrl_suspend(struct mem_link_device *mld) +{ + struct link_device *ld = &mld->link_dev; + unsigned long flags; + + spin_lock_irqsave(&ld->netif_lock, flags); + stop_net_ifaces(ld, TX_SUSPEND_MASK); + spin_unlock_irqrestore(&ld->netif_lock, flags); +} + +void tx_flowctrl_resume(struct mem_link_device *mld) +{ + struct link_device *ld = &mld->link_dev; + unsigned long flags; + + spin_lock_irqsave(&ld->netif_lock, flags); + resume_net_ifaces(ld, TX_SUSPEND_MASK); + spin_unlock_irqrestore(&ld->netif_lock, flags); +} + void send_req_ack(struct mem_link_device *mld, struct legacy_ipc_device *dev) { #ifdef DEBUG_MODEM_IF_FLOW_CTRL diff --git a/drivers/soc/google/cpif/link_device_memory_legacy.c b/drivers/soc/google/cpif/link_device_memory_legacy.c index 72a76426a32e..e3c5e0a9dc87 100644 --- a/drivers/soc/google/cpif/link_device_memory_legacy.c +++ b/drivers/soc/google/cpif/link_device_memory_legacy.c @@ -53,7 +53,7 @@ static ssize_t status_show(struct device *dev, count += scnprintf(&buf[count], PAGE_SIZE - count, "magic:0x%08X mem_access:0x%08X\n", ioread32(bl->magic), ioread32(bl->mem_access)); - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { ipc_dev = bl->dev[i]; count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); @@ -192,13 +192,13 @@ int create_legacy_link_device(struct mem_link_device *mld) atomic_set(&dev->rxq.busy, 0); dev->rxq.head = (void __iomem *)(mld->base + modem->legacy_raw_head_tail_offset + 8); dev->rxq.tail = (void __iomem *)(mld->base + modem->legacy_raw_head_tail_offset + 12); -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - dev->rxq.buff = phys_to_virt(cp_shmem_get_base(bl->ld->mdm_data->cp_num, SHMEM_IPC) + + if (modem->legacy_raw_rx_buffer_cached) + dev->rxq.buff = + phys_to_virt(cp_shmem_get_base(bl->ld->mdm_data->cp_num, SHMEM_IPC) + modem->legacy_raw_buffer_offset + modem->legacy_raw_txq_size); -#else - dev->rxq.buff = (void __iomem *)(mld->base + modem->legacy_raw_buffer_offset + + else + dev->rxq.buff = (void __iomem *)(mld->base + modem->legacy_raw_buffer_offset + modem->legacy_raw_txq_size); -#endif dev->rxq.size = modem->legacy_raw_rxq_size; dev->msg_mask = MASK_SEND_RAW; @@ -229,12 +229,14 @@ int init_legacy_link(struct legacy_link_device *bl) { unsigned int magic; unsigned int mem_access; + struct modem_data *modem = bl->ld->mdm_data; + int i = 0; iowrite32(0, bl->magic); iowrite32(0, bl->mem_access); - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { struct legacy_ipc_device *dev = bl->dev[i]; /* initialize circ_queues */ iowrite32(0, dev->txq.head); @@ -250,11 +252,9 @@ int init_legacy_link(struct legacy_link_device *bl) atomic_set(&dev->rxq.busy, 0); dev->req_ack_cnt[RX] = 0; -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - if (i == IPC_MAP_NORM_RAW) + if (modem->legacy_raw_rx_buffer_cached && i == IPC_MAP_NORM_RAW) dma_sync_single_for_device(bl->ld->dev, virt_to_phys(dev->rxq.buff), dev->rxq.size, DMA_FROM_DEVICE); -#endif } iowrite32(bl->ld->magic_ipc, bl->magic); @@ -393,10 +393,8 @@ struct sk_buff *recv_from_legacy_link(struct mem_link_device *mld, /* Finish reading data before incrementing tail */ smp_mb(); -#ifdef DEBUG_MODEM_IF /* Record the time-stamp */ ktime_get_ts64(&skbpriv(skb)->ts); -#endif return skb; @@ -426,7 +424,7 @@ bool check_legacy_tx_pending(struct mem_link_device *mld) unsigned int head, tail; struct legacy_ipc_device *dev; - for (i = IPC_MAP_FMT ; i < MAX_SIPC_MAP ; i++) { + for (i = IPC_MAP_FMT ; i < IPC_MAP_MAX ; i++) { dev = mld->legacy_link_dev.dev[i]; head = get_txq_head(dev); tail = get_txq_tail(dev); diff --git a/drivers/soc/google/cpif/link_device_memory_sbd.c b/drivers/soc/google/cpif/link_device_memory_sbd.c index 42b2f8b3f987..c115d595560b 100644 --- a/drivers/soc/google/cpif/link_device_memory_sbd.c +++ b/drivers/soc/google/cpif/link_device_memory_sbd.c @@ -11,15 +11,14 @@ */ #include +#include #include "modem_prj.h" #include "modem_utils.h" #include "link_device_memory.h" #include "include/sbd.h" -#include static void print_sbd_config(struct sbd_link_device *sl) { -#ifdef DEBUG_MODEM_IF int i, dir; struct sbd_rb_channel *rb_ch; struct sbd_rb_desc *rbd; @@ -43,7 +42,6 @@ static void print_sbd_config(struct sbd_link_device *sl) rbd->buff_size, rbd->payload_offset); } } -#endif } /* sysfs */ @@ -120,19 +118,11 @@ static ssize_t status_show(struct device *dev, "TX ch:%d len:%d buff_size:%d rp:%d wp:%d space:%d usage:%d\n", rb_tx->ch, rb_tx->len, rb_rx->buff_size, *rb_tx->rp, *rb_tx->wp, rb_space(rb_tx) + 1, rb_usage(rb_tx)); - - if (rb_rx->zerocopy) - count += scnprintf(&buf[count], PAGE_SIZE - count, - "RX ch:%d len:%d buff_size:%d rp:%d pre_rp:%d wp:%d, space:%d usage:%d\n", - rb_rx->ch, rb_rx->len, rb_rx->buff_size, - *rb_rx->rp, rb_rx->zdptr->pre_rp, - *rb_rx->wp, rb_space(rb_rx) + 1, rb_usage(rb_rx)); - else - count += scnprintf(&buf[count], PAGE_SIZE - count, - "RX ch:%d len:%d buff_size:%d rp:%d wp:%d, space:%d usage:%d\n", - rb_rx->ch, rb_rx->len, rb_rx->buff_size, - *rb_rx->rp, *rb_rx->wp, - rb_space(rb_rx) + 1, rb_usage(rb_rx)); + count += scnprintf(&buf[count], PAGE_SIZE - count, + "RX ch:%d len:%d buff_size:%d rp:%d wp:%d, space:%d usage:%d\n", + rb_rx->ch, rb_rx->len, rb_rx->buff_size, + *rb_rx->rp, *rb_rx->wp, + rb_space(rb_rx) + 1, rb_usage(rb_rx)); } return count; @@ -168,13 +158,6 @@ static void setup_link_attr(struct sbd_link_attr *link_attr, u16 id, u16 ch, link_attr->rb_len[DL] = io_dev->dl_num_buffers; link_attr->buff_size[DL] = io_dev->dl_buffer_size; -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) - if (io_dev->attrs & IO_ATTR_ZEROCOPY) - link_attr->zerocopy = true; - else - link_attr->zerocopy = false; -#endif - } /* @@ -229,15 +212,6 @@ static unsigned int init_ctrl_tables(struct sbd_link_device *sl) id++; } -#if !IS_ENABLED(CONFIG_MODEM_IF_QOS) - for (i = 0; i < sl->ld->mdm_data->num_iodevs; i++) { - int ch = iodevs[i]->ch; - - if (sipc_ps_ch(ch)) - sl->ch2id[ch] = sl->ch2id[QOS_HIPRIO]; - } -#endif - /* Finally, id has the number of actual link channels. */ return id; } @@ -268,8 +242,6 @@ int init_sbd_link(struct sbd_link_device *sl) ipc_dev->id = link_attr->id; ipc_dev->ch = link_attr->ch; - atomic_set(&ipc_dev->config_done, 0); - ipc_dev->zerocopy = link_attr->zerocopy; for (dir = 0; dir < ULDL; dir++) { /* @@ -279,7 +251,6 @@ int init_sbd_link(struct sbd_link_device *sl) rb->sl = sl; rb->lnk_hdr = link_attr->lnk_hdr; - rb->zerocopy = link_attr->zerocopy; rb->more = false; rb->total = 0; rb->rcvd = 0; @@ -288,7 +259,11 @@ int init_sbd_link(struct sbd_link_device *sl) * Initialize an SBD RB instance in the kernel space. */ rb->id = link_attr->id; +#if IS_ENABLED(CONFIG_CH_EXTENSION) + rb->ch = link_attr->ch ?: SIPC_CH_EX_ID_PDP_0; +#else rb->ch = link_attr->ch ?: SIPC_CH_ID_PDP_0; +#endif rb->dir = dir; rb->len = link_attr->rb_len[dir]; rb->buff_size = link_attr->buff_size[dir]; @@ -322,15 +297,6 @@ int init_sbd_link(struct sbd_link_device *sl) rb->rb_ch->buff_pos_array_offset = calc_offset(rb->buff_pos_array, sl->shmem); } - -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) - /* - * Setup zerocopy_adaptor if zerocopy ipc_dev - */ - ret = setup_zerocopy_adaptor(ipc_dev); - if (ret < 0) - return ret; -#endif } print_sbd_config(sl); @@ -403,18 +369,10 @@ int create_sbd_mem_map(struct sbd_link_device *sl) for (idx = 0; idx < rb_len; idx++) rb->buff[idx] = rb->buff_rgn + (idx * rb_buff_size); - mif_err("RB[%d:%d][%s] buff_rgn {addr:0x%pK offset:%d size:%u}\n", + mif_info("RB[%d:%d][%s] buff_rgn {addr:0x%pK offset:%d size:%u}\n", i, sbd_id2ch(sl, i), udl_str(dir), rb->buff_rgn, calc_offset(rb->buff_rgn, sl->shmem), (rb_len * rb_buff_size)); -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) - if (rb->buff_rgn + (rb_len * rb_buff_size) >= - sl->shmem + sl->shmem_size - SHMEM_BOOTSBDLOG_SIZE) { - mif_err("sbd buffer break boot log area\n"); - return -ENOMEM; - } -#endif - rb->rp = &sl->rp[dir][i]; rb->wp = &sl->wp[dir][i]; @@ -455,7 +413,6 @@ int create_sbd_link_device(struct link_device *ld, struct sbd_link_device *sl, sl->zmb_offset = shmem_size; sl->num_channels = init_ctrl_tables(sl); - sl->reset_zerocopy_done = 1; ret = create_sbd_mem_map(sl); if (ret < 0) { @@ -485,14 +442,6 @@ int create_sbd_link_device(struct link_device *ld, struct sbd_link_device *sl, return ret; } -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) - ret = sysfs_create_group(&sl->ld->dev->kobj, &zerocopy_group); - if (ret != 0) { - mif_err("sysfs_create_group() zerocopy_group error %d\n", ret); - return ret; - } -#endif - mif_info("Complete!!\n"); return 0; @@ -621,7 +570,7 @@ static inline void set_skb_priv(struct sbd_ring_buffer *rb, struct sk_buff *skb) /* Record the IO device, the link device, etc. into &skb->cb */ if (sipc_ps_ch(rb->ch)) { - unsigned int ch = (rb->buff_len_array[out] >> 16) & 0xffff; + unsigned int ch = (rb->buff_len_array[out] >> 16) & 0xff; skbpriv(skb)->iod = link_get_iod_with_channel(rb->ld, ch); skbpriv(skb)->ld = rb->ld; @@ -635,23 +584,27 @@ static inline void set_skb_priv(struct sbd_ring_buffer *rb, struct sk_buff *skb) } } -struct sk_buff *sbd_pio_rx(struct sbd_ring_buffer *rb) +int sbd_pio_rx(struct sbd_ring_buffer *rb, struct sk_buff **skb) { - struct sk_buff *skb; unsigned int qlen = rb->len; unsigned int out = *rb->rp; - skb = recv_data(rb, out); - if (unlikely(!skb)) - return NULL; + if (out >= qlen) { + mif_err("out value exceeds ring buffer size\n"); + return -EFAULT; + } - set_lnk_hdr(rb, skb); + *skb = recv_data(rb, out); + if (unlikely(!(*skb))) + return -ENOMEM; + + set_lnk_hdr(rb, *skb); - set_skb_priv(rb, skb); + set_skb_priv(rb, *skb); - check_more(rb, skb); + check_more(rb, *skb); *rb->rp = circ_new_ptr(qlen, out, 1); - return skb; + return 0; } diff --git a/drivers/soc/google/cpif/link_device_memory_snapshot.c b/drivers/soc/google/cpif/link_device_memory_snapshot.c index ef0bae00ed75..7340ace367ea 100644 --- a/drivers/soc/google/cpif/link_device_memory_snapshot.c +++ b/drivers/soc/google/cpif/link_device_memory_snapshot.c @@ -192,7 +192,7 @@ static void __take_mem_status(struct mem_link_device *mld, enum direction dir, mst->magic = ioread32(mld->legacy_link_dev.magic); mst->access = ioread32(mld->legacy_link_dev.mem_access); - for (i = 0; i < MAX_SIPC_MAP; i++) { + for (i = 0; i < IPC_MAP_MAX; i++) { struct legacy_ipc_device *dev = mld->legacy_link_dev.dev[i]; mst->head[i][TX] = get_txq_head(dev); diff --git a/drivers/soc/google/cpif/link_device_pcie_iommu.c b/drivers/soc/google/cpif/link_device_pcie_iommu.c new file mode 100644 index 000000000000..a78e60d244f9 --- /dev/null +++ b/drivers/soc/google/cpif/link_device_pcie_iommu.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#include "link_device_pcie_iommu.h" + +#define PCIE_CH2HSI(ch) ((ch) + 1) + +extern void pcie_iommu_tlb_invalidate_all(int hsi_block_num); +extern int pcie_iommu_map(unsigned long iova, phys_addr_t paddr, size_t size, + int prot, int hsi_block_num); +extern size_t pcie_iommu_unmap(unsigned long iova, size_t size, int hsi_block_num); + +void cpif_pcie_iommu_enable_regions(struct mem_link_device *mld) +{ + static bool enabled_region; + + struct pktproc_adaptor *ppa = &mld->pktproc; + struct link_device *ld = &mld->link_dev; + struct modem_ctl *mc = ld->mc; + + u32 cp_num = ld->mdm_data->cp_num; + u32 shmem_idx; + u32 size; + int ret; + + if (enabled_region) + return; + + for (shmem_idx = 0 ; shmem_idx < MAX_CP_SHMEM ; shmem_idx++) { + if (shmem_idx == SHMEM_MSI && !(mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)) + continue; + + if (shmem_idx == SHMEM_PKTPROC) + size = ppa->buff_rgn_offset; + else + size = cp_shmem_get_size(cp_num, shmem_idx); + + if (cp_shmem_get_base(cp_num, shmem_idx)) { + ret = pcie_iommu_map(cp_shmem_get_base(cp_num, shmem_idx), + cp_shmem_get_base(cp_num, shmem_idx), + size, 0, PCIE_CH2HSI(mc->pcie_ch_num)); + mif_info("pcie iommu idx:%d addr:0x%08lx size:0x%08x ret:%d\n", + shmem_idx, cp_shmem_get_base(cp_num, shmem_idx), size, ret); + } + } + + enabled_region = true; +} + +int cpif_pcie_iommu_init(struct pktproc_queue *q) +{ + struct cpif_pcie_iommu_ctrl *ioc = &q->ioc; + size_t size = sizeof(void *) * q->num_desc; + + mif_info("iommu init num_desc:%u\n", q->num_desc); + + if (ioc->pf_buf) { + memset(ioc->pf_buf, 0, size); + } else { + ioc->pf_buf = kvzalloc(size, GFP_KERNEL); + if (!ioc->pf_buf) + return -ENOMEM; + } + + return 0; +} + +void cpif_pcie_iommu_reset(struct pktproc_queue *q) +{ + struct modem_ctl *mc = dev_get_drvdata(q->ppa->dev); + struct pktproc_desc_sktbuf *desc = q->desc_sktbuf; + struct cpif_pcie_iommu_ctrl *ioc = &q->ioc; + unsigned int usage, idx; + bool do_unmap = true; + + if (!ioc->pf_buf) + return; + + usage = circ_get_usage(q->num_desc, ioc->curr_fore, q->done_ptr); + idx = q->done_ptr; + + mif_info("iommu reset done:%u curr_fore:%u usage:%u, fore:%u\n", + q->done_ptr, ioc->curr_fore, usage, *q->fore_ptr); + + while (usage--) { + if (do_unmap) { + unsigned long src_pa; + + src_pa = desc[idx].cp_data_paddr - q->cp_buff_pbase + + q->q_buff_pbase - q->ppa->skb_padding_size; + cpif_pcie_iommu_try_ummap_va(q, src_pa, ioc->pf_buf[idx], idx); + + /* Just free the frags if not mapped yet */ + if (idx == *q->fore_ptr) + do_unmap = false; + } + + page_frag_free(ioc->pf_buf[idx]); + idx = circ_new_ptr(q->num_desc, idx, 1); + } + + /* Initialize */ + pcie_iommu_tlb_invalidate_all(PCIE_CH2HSI(mc->pcie_ch_num)); + if (ioc->pf_cache.va) { + __page_frag_cache_drain(virt_to_page(ioc->pf_cache.va), + ioc->pf_cache.pagecnt_bias); + } + memset(&q->ioc, 0, offsetof(struct cpif_pcie_iommu_ctrl, pf_buf)); +} + +void *cpif_pcie_iommu_map_va(struct pktproc_queue *q, unsigned long src_pa, + u32 idx, u32 *map_cnt) +{ + struct modem_ctl *mc = dev_get_drvdata(q->ppa->dev); + struct cpif_pcie_iommu_ctrl *ioc = &q->ioc; + const size_t pf_size = q->ppa->true_packet_size; + void *addr_des, *addr_asc; + + /* + * Every page orders are compatible with IOMMU granularity. + * But the poped addrs are in descending order. + */ + addr_des = page_frag_alloc(&ioc->pf_cache, pf_size, GFP_ATOMIC); + if (!addr_des) { + mif_err_limited("failed to alloc page frag\n"); + return NULL; + } + + /* Map the last page */ + *map_cnt = 0; + if (ioc->map_page_va != ioc->pf_cache.va) { + unsigned long map_size, tailroom; + int ret; + + if (!ioc->map_src_pa) + goto set_map; + + map_size = page_size(virt_to_page(ioc->map_page_va)); + tailroom = q->q_buff_pbase + q->q_buff_size - ioc->map_src_pa; + if (map_size > tailroom) + map_size = tailroom; + +#ifdef LINK_DEVICE_PCIE_IOMMU_DEBUG + mif_debug("map idx:%u src_pa:0x%lX va:0x%p size:0x%lX\n", + ioc->map_idx, ioc->map_src_pa, ioc->map_page_va, map_size); +#endif + + ret = pcie_iommu_map(ioc->map_src_pa, virt_to_phys(ioc->map_page_va), + map_size, 0, PCIE_CH2HSI(mc->pcie_ch_num)); + if (ret) { + mif_err("map failure idx:%u src_pa:0x%lX va:0x%p size:0x%lX\n", + ioc->map_idx, ioc->map_src_pa, ioc->map_page_va, map_size); + return NULL; + } + ioc->mapped_cnt++; + ioc->mapped_size += map_size; + + /* Store the last mapping size */ + if (!idx) + ioc->end_map_size = (u32)map_size; + + *map_cnt = circ_get_usage(q->num_desc, idx, ioc->map_idx); + +set_map: + ioc->map_src_pa = src_pa; + ioc->map_page_va = ioc->pf_cache.va; + ioc->map_idx = idx; + ioc->pf_offset = 0; + } + + /* Convert an address in accending order */ + addr_asc = ioc->pf_cache.va + ioc->pf_offset; + + ioc->pf_buf[idx] = addr_asc; + ioc->pf_offset += pf_size; + ioc->curr_fore = idx; + + /* + * The first buffer should be mapped with a new page. + * Drain the page frag cache at the last buffer. + */ + if (idx == (q->num_desc - 1)) { + __page_frag_cache_drain(virt_to_page(ioc->pf_cache.va), + ioc->pf_cache.pagecnt_bias); + ioc->pf_cache.va = NULL; + } + + return addr_asc; +} + +void cpif_pcie_iommu_try_ummap_va(struct pktproc_queue *q, unsigned long src_pa, + void *addr, u32 idx) +{ + struct modem_ctl *mc = dev_get_drvdata(q->ppa->dev); + struct cpif_pcie_iommu_ctrl *ioc = &q->ioc; + u32 unmap_size; + size_t ret; + + if (!ioc->unmap_src_pa) + goto set_unmap; + + unmap_size = !idx ? ioc->end_map_size : ioc->unmap_page_size; + + if (src_pa >= ioc->unmap_src_pa && src_pa < ioc->unmap_src_pa + unmap_size) + return; + +#ifdef LINK_DEVICE_PCIE_IOMMU_DEBUG + mif_debug("unmap src_pa:0x%lX size:0x%X\n", ioc->unmap_src_pa, unmap_size); +#endif + + ret = pcie_iommu_unmap(ioc->unmap_src_pa, unmap_size, PCIE_CH2HSI(mc->pcie_ch_num)); + if (ret != unmap_size) { + mif_err("invalid unmap size:0x%zX expected:0x%X src_pa:0x%lX\n", + ret, unmap_size, ioc->unmap_src_pa); + } + ioc->mapped_cnt--; + ioc->mapped_size -= unmap_size; + +set_unmap: + ioc->unmap_src_pa = src_pa; + ioc->unmap_page_size = page_size(virt_to_head_page(addr)); +} diff --git a/drivers/soc/google/cpif/link_device_pcie_iommu.h b/drivers/soc/google/cpif/link_device_pcie_iommu.h new file mode 100644 index 000000000000..74b2a7b89f53 --- /dev/null +++ b/drivers/soc/google/cpif/link_device_pcie_iommu.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 Samsung Electronics. + * + */ + +#ifndef __LINK_DEVICE_PCIE_IOMMU_H__ +#define __LINK_DEVICE_PCIE_IOMMU_H__ + +#include "link_device_memory.h" + +void cpif_pcie_iommu_enable_regions(struct mem_link_device *mld); +int cpif_pcie_iommu_init(struct pktproc_queue *q); +void cpif_pcie_iommu_reset(struct pktproc_queue *q); + +void *cpif_pcie_iommu_map_va(struct pktproc_queue *q, unsigned long src_pa, + u32 idx, u32 *map_cnt); +void cpif_pcie_iommu_try_ummap_va(struct pktproc_queue *q, unsigned long src_pa, + void *addr, u32 idx); + +#endif /* __LINK_DEVICE_PCIE_IOMMU_H__ */ diff --git a/drivers/soc/google/cpif/link_rx_pktproc.c b/drivers/soc/google/cpif/link_rx_pktproc.c index bbada938a87d..14388411c43d 100644 --- a/drivers/soc/google/cpif/link_rx_pktproc.c +++ b/drivers/soc/google/cpif/link_rx_pktproc.c @@ -5,14 +5,21 @@ */ #include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include #include "modem_prj.h" #include "modem_utils.h" #include "link_device_memory.h" +#if IS_ENABLED(CONFIG_EXYNOS_DIT) #include "dit.h" +#endif +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) +#include "link_device_pcie_iommu.h" +#endif static struct pktproc_perftest_data perftest_data[PERFTEST_MODE_MAX] = { { @@ -171,10 +178,7 @@ static int pktproc_get_pkt_from_ringbuf_mode(struct pktproc_queue *q, struct sk_ ret = -EPERM; goto rx_error_on_desc; } - if (q->ppa->use_36bit_data_addr) - src = desc[*q->rear_ptr].cp_data_paddr - q->q_buff_pbase + q->q_buff_vbase; - else - src = desc[*q->rear_ptr].cp_data_paddr - q->cp_buff_pbase + q->q_buff_vbase; + src = desc[*q->rear_ptr].cp_data_paddr - q->cp_buff_pbase + q->q_buff_vbase; if ((src < q->q_buff_vbase) || (src > q->q_buff_vbase + q->q_buff_size)) { mif_err_limited("Data address is invalid:%pK q_buff_vbase:%pK size:0x%08x\n", src, q->q_buff_vbase, q->q_buff_size); @@ -182,15 +186,16 @@ static int pktproc_get_pkt_from_ringbuf_mode(struct pktproc_queue *q, struct sk_ ret = -EINVAL; goto rx_error_on_desc; } + +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc) dma_sync_single_for_cpu(q->ppa->dev, virt_to_phys(src), len, DMA_FROM_DEVICE); +#endif + pp_debug("len:%d ch_id:%d src:%pK\n", len, ch_id, src); /* Build skb */ - if (q->ppa->use_napi) - skb = napi_alloc_skb(q->napi_ptr, len); - else - skb = dev_alloc_skb(len); + skb = napi_alloc_skb(q->napi_ptr, len); if (unlikely(!skb)) { mif_err_limited("alloc_skb() error\n"); q->stat.err_nomem++; @@ -208,10 +213,7 @@ static int pktproc_get_pkt_from_ringbuf_mode(struct pktproc_queue *q, struct sk_ skbpriv(skb)->sipc_ch = ch_id; skbpriv(skb)->iod = link_get_iod_with_channel(ld, skbpriv(skb)->sipc_ch); skbpriv(skb)->ld = ld; - if (q->ppa->use_napi) - skbpriv(skb)->napi = q->napi_ptr; - else - skbpriv(skb)->napi = NULL; + skbpriv(skb)->napi = q->napi_ptr; switch (q->ppa->version) { case PKTPROC_V2: @@ -252,36 +254,33 @@ static int pktproc_get_pkt_from_ringbuf_mode(struct pktproc_queue *q, struct sk_ static int pktproc_clear_data_addr(struct pktproc_queue *q) { struct pktproc_desc_sktbuf *desc = q->desc_sktbuf; - u8 *src; + struct pktproc_adaptor *ppa = q->ppa; - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) { - mif_err_limited("Invalid desc_mode %d\n", q->ppa->desc_mode); + if (ppa->desc_mode != DESC_MODE_SKTBUF) { + mif_err_limited("Invalid desc_mode %d\n", ppa->desc_mode); return -EINVAL; } - if (!q->ppa->use_buff_mng) { + if (!ppa->use_netrx_mng) { mif_err_limited("Buffer manager is not set\n"); return -EPERM; } mif_info("Unmap buffer from %d to %d\n", q->done_ptr, *q->fore_ptr); while (*q->fore_ptr != q->done_ptr) { - if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc && - q->dma_addr[q->done_ptr]) - dma_unmap_single_attrs(q->ppa->dev, q->dma_addr[q->done_ptr], - q->manager->cell_size, DMA_FROM_DEVICE, 0); - - if (q->ppa->use_36bit_data_addr) - src = desc[q->done_ptr].cp_data_paddr - q->q_buff_pbase + - q->q_buff_vbase - q->ppa->skb_padding_size; - else - src = desc[q->done_ptr].cp_data_paddr - q->cp_buff_pbase + - q->q_buff_vbase - q->ppa->skb_padding_size; - if (src) - free_mif_buff(q->manager, src); - +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + if (ppa->buff_rgn_cached && !ppa->use_hw_iocc && q->dma_addr[q->done_ptr]) { + dma_unmap_single_attrs(ppa->dev, q->dma_addr[q->done_ptr], + ppa->max_packet_size, DMA_FROM_DEVICE, 0); + q->dma_addr[q->done_ptr] = 0; + } +#endif + desc[q->done_ptr].cp_data_paddr = 0; q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); } + + cpif_init_netrx_mng(q->manager); + memset(desc, 0, q->desc_size); return 0; @@ -290,25 +289,27 @@ static int pktproc_clear_data_addr(struct pktproc_queue *q) static int pktproc_clear_data_addr_without_bm(struct pktproc_queue *q) { struct pktproc_desc_sktbuf *desc = q->desc_sktbuf; - int i; - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) { - mif_err_limited("Invalid desc_mode %d\n", q->ppa->desc_mode); - return -EINVAL; - } - - if (q->ppa->use_buff_mng) { +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->ppa->use_netrx_mng) { mif_err_limited("Buffer manager is set\n"); return -EPERM; } +#endif - mif_info("Unmap buffer from %d to %d\n", q->done_ptr, *q->fore_ptr); - for (i = 0; i < q->num_desc; i++) { - if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc && - q->dma_addr[i]) - dma_unmap_single_attrs(q->ppa->dev, q->dma_addr[i], - q->ppa->max_packet_size, DMA_FROM_DEVICE, 0); +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + mif_info("Unmap all buffers\n"); + if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc) { + int i; + for (i = 0; i < q->num_desc; i++) { + if(q->dma_addr[i]) { + dma_unmap_single_attrs(q->ppa->dev, q->dma_addr[i], + q->ppa->max_packet_size, DMA_FROM_DEVICE, 0); + q->dma_addr[i] = 0; + } + } } +#endif memset(desc, 0, q->desc_size); return 0; @@ -317,18 +318,18 @@ static int pktproc_clear_data_addr_without_bm(struct pktproc_queue *q) static int pktproc_fill_data_addr(struct pktproc_queue *q) { struct pktproc_desc_sktbuf *desc = q->desc_sktbuf; - u8 *dst_vaddr = NULL; + struct pktproc_adaptor *ppa = q->ppa; u32 space; u32 fore; int i; unsigned long flags; - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) { - mif_err_limited("Invalid desc_mode %d\n", q->ppa->desc_mode); + if (ppa->desc_mode != DESC_MODE_SKTBUF) { + mif_err_limited("Invalid desc_mode %d\n", ppa->desc_mode); return -EINVAL; } - if (!q->ppa->use_buff_mng) { + if (!ppa->use_netrx_mng) { mif_err_limited("Buffer manager is not set\n"); return -EPERM; } @@ -336,42 +337,34 @@ static int pktproc_fill_data_addr(struct pktproc_queue *q) spin_lock_irqsave(&q->lock, flags); space = circ_get_space(q->num_desc, *q->fore_ptr, q->done_ptr); - pp_debug("Q%d:%d/%d/%d Space:%d BM:%d/%d/%d\n", - q->q_idx, *q->fore_ptr, *q->rear_ptr, q->done_ptr, space, - q->manager->cell_count, q->manager->used_cell_count, q->manager->free_cell_count); + pp_debug("Q%d:%d/%d/%d Space:%d\n", + q->q_idx, *q->fore_ptr, *q->rear_ptr, q->done_ptr, space); fore = *q->fore_ptr; for (i = 0; i < space; i++) { - dst_vaddr = alloc_mif_buff(q->manager); - if (!dst_vaddr) { - mif_err_limited("alloc error for space: %d Q%d:%d/%d/%d BM:%d/%d/%d\n", - space, q->q_idx, *q->fore_ptr, *q->rear_ptr, q->done_ptr, - q->manager->cell_count, q->manager->used_cell_count, - q->manager->free_cell_count); - + struct cpif_addr_pair *addrpair = cpif_map_rx_buf(q->manager); + if (unlikely(!addrpair)) { + mif_err_limited("skb alloc error due to no memory\n"); q->stat.err_bm_nomem++; spin_unlock_irqrestore(&q->lock, flags); return -ENOMEM; } - pp_debug("Q:%d fore_ptr:%d dst_vaddr:%pK\n", q->q_idx, *q->fore_ptr, dst_vaddr); - - if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc) { - q->dma_addr[fore] = dma_map_single_attrs(q->ppa->dev, dst_vaddr, - q->manager->cell_size, DMA_FROM_DEVICE, 0); - if (dma_mapping_error(q->ppa->dev, q->dma_addr[fore])) { +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + if (ppa->buff_rgn_cached && !ppa->use_hw_iocc) { + q->dma_addr[fore] = dma_map_single_attrs(ppa->dev, + (u8 *)addrpair->ap_addr + ppa->skb_padding_size, + ppa->max_packet_size, DMA_FROM_DEVICE, 0); + if (dma_mapping_error(ppa->dev, q->dma_addr[fore])) { mif_err_limited("dma_map_single_attrs() failed\n"); + q->dma_addr[fore] = 0; spin_unlock_irqrestore(&q->lock, flags); return -ENOMEM; } } +#endif - if (q->ppa->use_36bit_data_addr) - desc[fore].cp_data_paddr = (dst_vaddr - q->q_buff_vbase) + - q->q_buff_pbase + q->ppa->skb_padding_size; - else - desc[fore].cp_data_paddr = (dst_vaddr - q->q_buff_vbase) + - q->cp_buff_pbase + q->ppa->skb_padding_size; + desc[fore].cp_data_paddr = addrpair->cp_addr + ppa->skb_padding_size; if (fore == 0) desc[fore].control |= (1 << 7); /* HEAD */ @@ -379,6 +372,13 @@ static int pktproc_fill_data_addr(struct pktproc_queue *q) if (fore == (q->num_desc - 1)) desc[fore].control |= (1 << 3); /* RINGEND */ + if (unlikely(desc[fore].reserved0 != 0)) { /* W/A to detect mem poison */ + mif_err("mem poison:0x%llX r0:%d c:%d s:%d l%d cl%d r1:%d\n", + desc[fore].cp_data_paddr, desc[fore].reserved0, + desc[fore].control, desc[fore].status, + desc[fore].lro, desc[fore].clat, desc[fore].reserved1); + panic("memory poison\n"); + } *q->fore_ptr = circ_new_ptr(q->num_desc, *q->fore_ptr, 1); fore = circ_new_ptr(q->num_desc, fore, 1); } @@ -394,73 +394,111 @@ static int pktproc_fill_data_addr(struct pktproc_queue *q) static int pktproc_fill_data_addr_without_bm(struct pktproc_queue *q) { struct pktproc_desc_sktbuf *desc = q->desc_sktbuf; - u8 *dst_vaddr = NULL; unsigned long dst_paddr; u32 fore; int i; unsigned long flags; + u32 space; + u32 fore_inc = 1; - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) { - mif_err_limited("Invalid desc_mode %d\n", q->ppa->desc_mode); - return -EINVAL; - } - - if (q->ppa->use_buff_mng) { +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->ppa->use_netrx_mng) { mif_err_limited("Buffer manager is set\n"); return -EPERM; } +#endif - mif_info("Q%d:%d/%d/%d\n", - q->q_idx, *q->fore_ptr, *q->rear_ptr, q->done_ptr); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + fore = q->ioc.curr_fore; +#else + fore = *q->fore_ptr; +#endif + + pp_debug("Q%d:%d/%d/%d\n", + q->q_idx, fore, *q->rear_ptr, q->done_ptr); spin_lock_irqsave(&q->lock, flags); - fore = *q->fore_ptr; - for (i = 0; i < q->num_desc; i++) { - dst_paddr = q->q_buff_pbase + (q->ppa->max_packet_size * fore); + if (q->ppa->buff_rgn_cached) { + space = circ_get_space(q->num_desc, fore, q->done_ptr); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + if (space > q->ppa->space_margin) + space -= q->ppa->space_margin; + else + space = 0; +#endif + } else { + space = q->num_desc; + } + + for (i = 0; i < space; i++) { +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) || !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + u8 *dst_vaddr = NULL; +#endif + + dst_paddr = q->q_buff_pbase + (q->ppa->true_packet_size * fore); if (dst_paddr > (q->q_buff_pbase + q->q_buff_size)) mif_err_limited("dst_paddr:0x%lx is over 0x%lx\n", dst_paddr, q->q_buff_pbase + q->q_buff_size); pp_debug("Q:%d fore_ptr:%d dst_paddr:0x%lx\n", - q->q_idx, *q->fore_ptr, dst_paddr); + q->q_idx, fore, dst_paddr); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + dst_vaddr = cpif_pcie_iommu_map_va(q, dst_paddr, fore, &fore_inc); + if (!dst_vaddr) { + mif_err_limited("cpif_pcie_iommu_get_va() failed\n"); + spin_unlock_irqrestore(&q->lock, flags); + return -ENOMEM; + } +#endif + +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc) { - dst_vaddr = q->q_buff_vbase + (q->ppa->max_packet_size * i); + if (dst_vaddr) + goto dma_map; + + dst_vaddr = q->q_buff_vbase + (q->ppa->true_packet_size * fore); if (dst_vaddr > (q->q_buff_vbase + q->q_buff_size)) mif_err_limited("dst_vaddr:%pK is over %pK\n", dst_vaddr, q->q_buff_vbase + q->q_buff_size); - q->dma_addr[fore] = dma_map_single_attrs(q->ppa->dev, dst_vaddr, - q->ppa->max_packet_size, DMA_FROM_DEVICE, 0); +dma_map: + q->dma_addr[fore] = + dma_map_single_attrs(q->ppa->dev, + dst_vaddr + q->ppa->skb_padding_size, + q->ppa->max_packet_size, DMA_FROM_DEVICE, 0); if (dma_mapping_error(q->ppa->dev, q->dma_addr[fore])) { mif_err_limited("dma_map_single_attrs() failed\n"); + q->dma_addr[fore] = 0; spin_unlock_irqrestore(&q->lock, flags); return -ENOMEM; } } +#endif - if (q->ppa->use_36bit_data_addr) - desc[fore].cp_data_paddr = dst_paddr + - q->ppa->skb_padding_size; - else - desc[fore].cp_data_paddr = (dst_paddr - q->q_buff_pbase) + - q->cp_buff_pbase + - q->ppa->skb_padding_size; + desc[fore].cp_data_paddr = (dst_paddr - q->q_buff_pbase) + + q->cp_buff_pbase + + q->ppa->skb_padding_size; if (fore == 0) desc[fore].control |= (1 << 7); /* HEAD */ if (fore == (q->num_desc - 1)) { desc[fore].control |= (1 << 3); /* RINGEND */ - continue; + if (!q->ppa->buff_rgn_cached) + continue; } - *q->fore_ptr = circ_new_ptr(q->num_desc, *q->fore_ptr, 1); + if (fore_inc) + *q->fore_ptr = circ_new_ptr(q->num_desc, *q->fore_ptr, fore_inc); fore = circ_new_ptr(q->num_desc, fore, 1); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + q->ioc.curr_fore = fore; +#endif } - mif_info("Q:%d fore/rear/done:%d/%d/%d\n", + pp_debug("Q:%d fore/rear/done:%d/%d/%d\n", q->q_idx, *q->fore_ptr, *q->rear_ptr, q->done_ptr); spin_unlock_irqrestore(&q->lock, flags); @@ -470,84 +508,322 @@ static int pktproc_fill_data_addr_without_bm(struct pktproc_queue *q) static int pktproc_update_fore_ptr(struct pktproc_queue *q, u32 count) { - *q->fore_ptr = circ_new_ptr(q->num_desc, *q->fore_ptr, count); + int ret = 0; + unsigned long flags; - return 0; + if (!count) + return 0; + + if (q->ppa->buff_rgn_cached) { + ret = q->alloc_rx_buf(q); + if (ret) + mif_err_limited("alloc_rx_buf() error %d Q%d\n", ret, q->q_idx); + } else { + spin_lock_irqsave(&q->lock, flags); + *q->fore_ptr = circ_new_ptr(q->num_desc, *q->fore_ptr, count); + spin_unlock_irqrestore(&q->lock, flags); + } + + return ret; } -static int pktproc_get_pkt_from_sktbuf_mode(struct pktproc_queue *q, struct sk_buff **new_skb) +static bool is_desc_valid(struct pktproc_queue *q, struct pktproc_desc_sktbuf *desc) { - int ret = 0; - u16 len, tmp_len; - u16 ch_id; - u8 *src; - unsigned long src_paddr; - struct sk_buff *skb = NULL; - struct pktproc_desc_sktbuf desc_done_ptr = q->desc_sktbuf[q->done_ptr]; - struct link_device *ld = &q->mld->link_dev; - u32 packet_size = 0; - bool csum = false; + if (desc->length > q->ppa->max_packet_size) { + mif_err_limited("Length is invalid:%d\n", desc->length); + q->stat.err_len++; + return false; + } - if (!pktproc_check_active(q->ppa, q->q_idx)) { - mif_err_limited("Queue %d not activated\n", q->q_idx); - return -EACCES; + if (desc->channel_id == SIPC5_CH_ID_MAX) { + mif_err_limited("Channel ID is invalid:%d\n", desc->channel_id); + q->stat.err_chid++; + return false; } - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) { - mif_err_limited("Invalid desc_mode %d\n", q->ppa->desc_mode); - return -EINVAL; + return true; +} + +static u8 *get_packet_vaddr(struct pktproc_queue *q, struct pktproc_desc_sktbuf *desc) +{ + u8 *ret; + struct pktproc_adaptor *ppa = q->ppa; + +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->manager) { + ret = (u8 *)cpif_unmap_rx_buf(q->manager, + desc->cp_data_paddr - + ppa->skb_padding_size, false); + if (!ret) { + mif_err_limited("invalid data address. null given\n"); + q->stat.err_addr++; + return NULL; + } + } else +#endif + { +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + unsigned long src_paddr = desc->cp_data_paddr - q->cp_buff_pbase + + q->q_buff_pbase - ppa->skb_padding_size; + + ret = (u8 *)q->ioc.pf_buf[q->done_ptr]; + cpif_pcie_iommu_try_ummap_va(q, src_paddr, ret, q->done_ptr); +#else + ret = desc->cp_data_paddr - q->cp_buff_pbase + + q->q_buff_vbase - ppa->skb_padding_size; + + if ((ret < q->q_buff_vbase) || (ret > q->q_buff_vbase + q->q_buff_size)) { + mif_err_limited("Data address is invalid:%pK data:%pK size:0x%08x\n", + ret, q->q_buff_vbase, q->q_buff_size); + q->stat.err_addr++; + return NULL; + } +#endif } - /* Get data */ - len = desc_done_ptr.length; - if (len > q->ppa->max_packet_size) { - mif_err_limited("Length is invalid:%d\n", len); - q->stat.err_len++; - ret = -EPERM; - goto rx_error_on_desc; + ret += ppa->skb_padding_size; + +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + if (ppa->buff_rgn_cached && !ppa->use_hw_iocc && q->dma_addr[q->done_ptr]) { + dma_unmap_single_attrs(ppa->dev, q->dma_addr[q->done_ptr], + ppa->max_packet_size, DMA_FROM_DEVICE, 0); + q->dma_addr[q->done_ptr] = 0; } +#endif - ch_id = desc_done_ptr.channel_id; - if (ch_id == SIPC5_CH_ID_MAX) { - mif_err_limited("Channel ID is invalid:%d\n", ch_id); - q->stat.err_chid++; - ret = -EPERM; - goto rx_error_on_desc; + return ret; +} + +static struct sk_buff *cpif_build_skb_single(struct pktproc_queue *q, u8 *src, u16 len, + u16 front_pad_size, u16 rear_pad_size, int *buffer_count) +{ + struct sk_buff *skb; + +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->manager) { + skb = build_skb(src - front_pad_size, q->manager->frag_size); + if (unlikely(!skb)) + goto error; + + skb_reserve(skb, front_pad_size); + } else +#endif + { +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + skb = build_skb(src - front_pad_size, q->ppa->true_packet_size); + if (unlikely(!skb)) + goto error; + + skb_reserve(skb, front_pad_size); +#else + skb = napi_alloc_skb(q->napi_ptr, len); + if (unlikely(!skb)) + goto error; + + skb_copy_to_linear_data(skb, src, len); +#endif } - if (q->ppa->use_36bit_data_addr) { - src_paddr = desc_done_ptr.cp_data_paddr - q->ppa->skb_padding_size; - src = desc_done_ptr.cp_data_paddr - q->q_buff_pbase + - q->q_buff_vbase - q->ppa->skb_padding_size; - } else { - src_paddr = desc_done_ptr.cp_data_paddr - q->cp_buff_pbase + - q->q_buff_pbase - q->ppa->skb_padding_size; - src = desc_done_ptr.cp_data_paddr - q->cp_buff_pbase + - q->q_buff_vbase - q->ppa->skb_padding_size; + skb_put(skb, len); + *buffer_count += 1; + q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); + + return skb; + +error: + mif_err_limited("getting skb failed\n"); + + q->stat.err_nomem++; +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->manager && !q->manager->already_retrieved) + q->manager->already_retrieved = src; +#endif + + return NULL; +} + +#if IS_ENABLED(CONFIG_CP_PKTPROC_LRO) +static u32 cpif_prepare_lro_and_get_headlen(struct sk_buff *skb, bool *is_udp) +{ + u32 headlen = 0; + struct iphdr *iph = (struct iphdr *)skb->data; + + if (iph->version == 6) { + struct ipv6hdr *ipv6h = (struct ipv6hdr *)skb->data; + + headlen += sizeof(struct ipv6hdr); + if (ipv6h->nexthdr == NEXTHDR_TCP) { + struct tcphdr *th = (struct tcphdr *)(skb->data + headlen); + + headlen += th->doff * 4; + skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6; + } else { + struct udphdr *uh = (struct udphdr *)(skb->data + headlen); + __be16 backup_len = uh->len; + + uh->check = 0; + uh->len = htons(skb->len - headlen); + uh->check = csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, + ntohs(uh->len), IPPROTO_UDP, + csum_partial(uh, ntohs(uh->len), 0)); + uh->len = backup_len; + headlen += sizeof(struct udphdr); + skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_L4 | SKB_GSO_FRAGLIST; + *is_udp = true; + } + } else { /* ipv4 */ + headlen += sizeof(struct iphdr); + if (iph->protocol == IPPROTO_TCP) { + struct tcphdr *th = (struct tcphdr *)(skb->data + headlen); + + headlen += th->doff * 4; + skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4; + } else { + headlen += sizeof(struct udphdr); + skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_L4 | SKB_GSO_FRAGLIST; + *is_udp = true; + } } - if ((src < q->q_buff_vbase) || (src > q->q_buff_vbase + q->q_buff_size)) { - mif_err_limited("Data address is invalid:%pK data:%pK size:0x%08x\n", - src, q->q_buff_vbase, q->q_buff_size); - q->stat.err_addr++; + + return headlen; +} + +static struct sk_buff *cpif_build_skb_gro(struct pktproc_queue *q, u8 *src, u16 len, + int *buffer_count, bool *nomem) +{ + struct sk_buff *skb_head, *skb, *last; + struct pktproc_desc_sktbuf *desc; + struct iphdr *iph; + struct ipv6hdr *ipv6h; + struct udphdr *uh; + u32 hdr_len; + bool is_udp = false; + + skb_head = cpif_build_skb_single(q, src, len, q->ppa->skb_padding_size, + sizeof(struct skb_shared_info), buffer_count); + if (unlikely(!skb_head)) + goto gro_fail_nomem; + + hdr_len = cpif_prepare_lro_and_get_headlen(skb_head, &is_udp); + skb_shinfo(skb_head)->gso_size = skb_head->len - hdr_len; + skb_shinfo(skb_head)->gso_segs = 1; + skb_frag_list_init(skb_head); + skb_head->csum_level = 1; + + last = NULL; + while (q->desc_sktbuf[q->done_ptr].lro & (LRO_MID_SEG | LRO_LAST_SEG)) { + u8 *tmp_src; + u16 tmp_len; + bool last_seg = (q->desc_sktbuf[q->done_ptr].lro & LRO_LAST_SEG) ? + true : false; + + desc = &q->desc_sktbuf[q->done_ptr]; + + if (!is_desc_valid(q, desc)) { + mif_err_limited("Err! invalid desc. HW GRO failed\n"); + goto gro_fail_inval; + } + + tmp_src = get_packet_vaddr(q, desc); + if (!tmp_src) { + mif_err_limited("Err! invalid packet vaddr. HW GRO failed\n"); + goto gro_fail_inval; + } + + tmp_len = desc->length; + skb = cpif_build_skb_single(q, tmp_src, tmp_len, q->ppa->skb_padding_size, + sizeof(struct skb_shared_info), buffer_count); + if (unlikely(!skb)) + goto gro_fail_nomem; + skb->transport_header = q->ppa->skb_padding_size - hdr_len; + skb->network_header = q->ppa->skb_padding_size - hdr_len; + skb->mac_header = q->ppa->skb_padding_size - hdr_len; + + if (is_udp) { /* need to generate header including checksum */ + u8 *hdr_start = skb->data - hdr_len; + + skb_copy_from_linear_data(skb_head, hdr_start, hdr_len); + iph = (struct iphdr *)hdr_start; + if (iph->version == 4) { + uh = (struct udphdr *)(hdr_start + sizeof(struct iphdr)); + iph->tot_len = htons(tmp_len + hdr_len); + iph->check = ip_fast_csum((unsigned char *)iph, + iph->ihl); + } else { /* ipv6 */ + uh = (struct udphdr *)(hdr_start + sizeof(struct ipv6hdr)); + ipv6h = (struct ipv6hdr *)hdr_start; + ipv6h->payload_len = htons(tmp_len + sizeof(struct udphdr)); + } + + uh->len = htons(tmp_len + sizeof(struct udphdr)); + if (iph->version == 6) { /* checksum required for udp v6 only */ + uh->check = 0; + uh->check = csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr, + ntohs(uh->len), IPPROTO_UDP, + csum_partial(uh, ntohs(uh->len), 0)); + } + } + + if (last) + last->next = skb; + else + skb_shinfo(skb_head)->frag_list = skb; + last = skb; + skb_head->data_len += skb->len; + skb_head->truesize += skb->truesize; + skb_head->len += skb->len; + skb_shinfo(skb_head)->gso_segs += 1; + + if (last_seg) + break; + } + + iph = (struct iphdr *)skb_head->data; + if (iph->version == 4) + iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl); + + return skb_head; + +gro_fail_nomem: + *nomem = true; +gro_fail_inval: + if (skb_head) + dev_kfree_skb_any(skb_head); + return NULL; +} +#endif + +static int pktproc_get_pkt_from_sktbuf_mode(struct pktproc_queue *q, struct sk_buff **new_skb) +{ + int ret = 0; + int buffer_count = 0; + u16 len; + u8 ch_id; + /* It will be the start of skb->data */ + u8 *src; + struct pktproc_adaptor *ppa = q->ppa; + struct sk_buff *skb = NULL; + struct pktproc_desc_sktbuf desc_done_ptr = q->desc_sktbuf[q->done_ptr]; + struct link_device *ld = &q->mld->link_dev; + bool csum = false; + + if (!is_desc_valid(q, &desc_done_ptr)) { ret = -EINVAL; goto rx_error_on_desc; } - if (q->ppa->buff_rgn_cached && !q->ppa->use_hw_iocc) { - if (q->manager) - packet_size = q->manager->cell_size; - else - packet_size = q->ppa->max_packet_size; - - dma_unmap_single_attrs(q->ppa->dev, q->dma_addr[q->done_ptr], - packet_size, DMA_FROM_DEVICE, 0); + src = get_packet_vaddr(q, &desc_done_ptr); + if (!src) { + ret = -EINVAL; + goto rx_error_on_desc; } + len = desc_done_ptr.length; + ch_id = desc_done_ptr.channel_id; csum = pktproc_check_hw_checksum(desc_done_ptr.status); if (!csum) q->stat.err_csum++; - - if (unlikely(q->ppa->pktgen_gro)) { + if (unlikely(ppa->pktgen_gro)) { pktproc_set_pktgen_checksum(q, src); csum = true; } @@ -556,10 +832,18 @@ static int pktproc_get_pkt_from_sktbuf_mode(struct pktproc_queue *q, struct sk_b q->q_idx, q->done_ptr, len, ch_id, src, csum); #ifdef PKTPROC_DEBUG_PKT - pr_buffer("pktproc", (char *)src, (size_t)len, (size_t)40); + pr_buffer("pktproc", (char *)src + ppa->skb_padding_size, (size_t)len, (size_t)40); #endif +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)) { +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + unsigned long src_paddr = 0; +#else + unsigned long src_paddr = desc_done_ptr.cp_data_paddr - q->cp_buff_pbase + + q->q_buff_pbase; +#endif + ret = dit_enqueue_src_desc_ring(DIT_DIR_RX, src, src_paddr, len, ch_id, csum); if (ret < 0) { @@ -573,63 +857,77 @@ static int pktproc_get_pkt_from_sktbuf_mode(struct pktproc_queue *q, struct sk_b q->stat.pass_cnt++; q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); - return 0; + return 1; /* dit cannot support HW GRO packets */ } +#endif - /* Build skb */ - if (q->use_memcpy) { - if (q->ppa->use_napi) - skb = napi_alloc_skb(q->napi_ptr, len); - else - skb = dev_alloc_skb(len); +#if IS_ENABLED(CONFIG_CP_PKTPROC_LRO) + /* guaranteed that only TCP/IP, UDP/IP in this case */ + if (desc_done_ptr.lro == (LRO_MODE_ON | LRO_FIRST_SEG)) { + bool nomem = false; + + if (!csum) + mif_info("CSUM error on LRO: 0x%X\n", desc_done_ptr.status); + + skb = cpif_build_skb_gro(q, src, len, &buffer_count, &nomem); if (unlikely(!skb)) { - mif_err_limited("alloc_skb() error\n"); - q->stat.err_nomem++; - ret = -ENOMEM; - goto rx_error; + if (nomem) { + ret = -ENOMEM; + if (buffer_count != 0) /* intermediate seg */ + q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); + goto rx_error; + } else { + ret = -EINVAL; + goto rx_error_on_desc; + } } - skb_put(skb, len); - skb_copy_to_linear_data(skb, src + q->ppa->skb_padding_size, len); - if (q->manager) - free_mif_buff(q->manager, src); - q->stat.use_memcpy_cnt++; + q->stat.lro_cnt++; } else { - tmp_len = SKB_DATA_ALIGN(len + q->ppa->skb_padding_size); - tmp_len += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); - skb = build_skb(src, tmp_len); + skb = cpif_build_skb_single(q, src, len, ppa->skb_padding_size, + sizeof(struct skb_shared_info), &buffer_count); if (unlikely(!skb)) { - mif_err_limited("build_skb() error\n"); - q->stat.err_nomem++; ret = -ENOMEM; goto rx_error; } - skb->head_frag = 0; - skb_reserve(skb, q->ppa->skb_padding_size); - skb_put(skb, len); } +#else + skb = cpif_build_skb_single(q, src, len, ppa->skb_padding_size, + sizeof(struct skb_shared_info), &buffer_count); + if (unlikely(!skb)) { + ret = -ENOMEM; + goto rx_error; + } +#endif if (csum) skb->ip_summed = CHECKSUM_UNNECESSARY; + if (ppa->use_exclusive_irq) + skb_record_rx_queue(skb, q->q_idx); + /* Set priv */ skbpriv(skb)->lnk_hdr = 0; skbpriv(skb)->sipc_ch = ch_id; skbpriv(skb)->iod = link_get_iod_with_channel(ld, ch_id); skbpriv(skb)->ld = ld; - if (q->ppa->use_napi) - skbpriv(skb)->napi = q->napi_ptr; - else - skbpriv(skb)->napi = NULL; + skbpriv(skb)->napi = q->napi_ptr; + +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + /* CLAT[1:0] = {CLAT On, CLAT Pkt} */ + if (desc_done_ptr.clat == 0x03) + skbpriv(skb)->rx_clat = 1; +#endif *new_skb = skb; - q->stat.pass_cnt++; - q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); + q->stat.pass_cnt += buffer_count; - return 0; + return buffer_count; rx_error_on_desc: - mif_err_limited("Skip invalid descriptor at %d\n", q->done_ptr); + mif_err_limited("Skip invalid descriptor at %d and crash\n", q->done_ptr); + ld->link_trigger_cp_crash(q->mld, CRASH_REASON_MIF_RX_BAD_DATA, + "invalid descriptor given"); q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); rx_error: @@ -680,50 +978,26 @@ int pktproc_get_usage_fore_rear(struct pktproc_queue *q) return usage; } -static bool pktproc_check_memcpy_mode(struct pktproc_queue *q, u32 budget) -{ - if (q->ppa->desc_mode != DESC_MODE_SKTBUF) - return true; - - if (!q->manager) - return true; - - if (!q->manager->enable_sw_zerocopy) - return true; - - if (q->manager->free_cell_count < budget) - return true; - - if (circ_get_space(q->num_desc, *q->rear_ptr, *q->fore_ptr) < budget) - return true; - - return false; -} - static int pktproc_clean_rx_ring(struct pktproc_queue *q, int budget, int *work_done) { int ret = 0; u32 num_frames = 0; - u32 rcvd = 0; - - if (!pktproc_check_active(q->ppa, q->q_idx)) - return -EACCES; + u32 rcvd_total = 0; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + u32 rcvd_dit = 0; +#endif + u32 budget_used = 0; - if (q->ppa->use_napi) - num_frames = min_t(unsigned int, pktproc_get_usage(q), budget); - else - num_frames = pktproc_get_usage(q); + num_frames = pktproc_get_usage(q); if (!num_frames) return 0; - q->use_memcpy = pktproc_check_memcpy_mode(q, budget); - - pp_debug("Q%d num_frames:%d memcpy:%d %d/%d/%d\n", - q->q_idx, num_frames, q->use_memcpy, + pp_debug("Q%d num_frames:%d fore/rear/done: %d/%d/%d\n", + q->q_idx, num_frames, *q->fore_ptr, *q->rear_ptr, q->done_ptr); - while (rcvd < num_frames) { + while (rcvd_total < num_frames && budget_used < budget) { struct sk_buff *skb = NULL; ret = q->get_packet(q, &skb); @@ -731,45 +1005,50 @@ static int pktproc_clean_rx_ring(struct pktproc_queue *q, int budget, int *work_ mif_err_limited("get_packet() error %d\n", ret); break; } - - if (dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)) { - rcvd++; + rcvd_total += ret; + budget_used++; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + /* skb will be null if dit fills the skb */ + if (!skb) { + rcvd_dit += ret; /* ret will be always 1 */ continue; } - - if (unlikely(!skb)) { - mif_err_limited("skb is null\n"); - ret = -ENOMEM; - break; - } - - rcvd++; +#endif ret = q->mld->pass_skb_to_net(q->mld, skb); if (ret < 0) break; } - if (dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)) { - pp_debug("rcvd for dit:%d\n", rcvd); - if (rcvd > 0) - dit_kick(DIT_DIR_RX, false); - } else { +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + if (rcvd_dit) { + dit_kick(DIT_DIR_RX, false); + + /* dit processed every packets*/ + if (rcvd_dit == rcvd_total) + goto out; + } +#endif + #if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) - if (rcvd) - tpmon_start(); +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + if (rcvd_total - rcvd_dit > 0) +#else + if (rcvd_total > 0) +#endif + tpmon_start(); #endif - if (q->ppa->manager) { - ret = q->alloc_rx_buf(q); - if (ret) - mif_err_limited("alloc_rx_buf() error %d Q%d\n", ret, q->q_idx); - } else { - q->update_fore_ptr(q, rcvd); - } - } - if (q->ppa->use_napi) - *work_done = rcvd; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) + q->update_fore_ptr(q, rcvd_total - rcvd_dit); +#else + q->update_fore_ptr(q, rcvd_total); +#endif + +#if IS_ENABLED(CONFIG_EXYNOS_DIT) +out: +#endif + *work_done = rcvd_total; return ret; } @@ -822,12 +1101,12 @@ static unsigned int pktproc_perftest_gen_rx_packet_sktbuf_mode( desc[rear_ptr].channel_id = perf->ch; /* set data */ - if (q->ppa->use_36bit_data_addr) - src = desc[rear_ptr].cp_data_paddr - - q->q_buff_pbase + q->q_buff_vbase; - else - src = desc[rear_ptr].cp_data_paddr - - q->cp_buff_pbase + q->q_buff_vbase; +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + src = q->ioc.pf_buf[rear_ptr] + q->ppa->skb_padding_size; +#else + src = desc[rear_ptr].cp_data_paddr - + q->cp_buff_pbase + q->q_buff_vbase; +#endif memset(src, 0x0, desc[rear_ptr].length); memcpy(src, perftest_data[perf->mode].header, header_len); seq = (u32 *)(src + header_len); @@ -868,25 +1147,23 @@ static int pktproc_perftest_thread(void *arg) pkts = (perf->session > 0 ? (1023 / perf->session) : 0); do { for (i = 0 ; i < perf->session ; i++) { + int napi_cpu = perf->ipi_cpu[0]; + if (session_queue) q = ppa->q[i]; if (!pktproc_perftest_gen_rx_packet_sktbuf_mode(q, pkts, i)) continue; - if (ppa->use_napi) { - if (session_queue) { - if (cpu_online(perf->ipi_cpu[i])) - smp_call_function_single(perf->ipi_cpu[i], - pktproc_perftest_napi_schedule, - (void *)q, 0); - else - pktproc_perftest_napi_schedule(q); - } else { - pktproc_perftest_napi_schedule(q); - } + if (session_queue) + napi_cpu = perf->ipi_cpu[i]; + + if (napi_cpu >= 0 && cpu_online(napi_cpu)) { + smp_call_function_single(napi_cpu, + pktproc_perftest_napi_schedule, + (void *)q, 0); } else { - q->irq_handler(q->irq, q); + pktproc_perftest_napi_schedule(q); } } @@ -911,8 +1188,8 @@ static ssize_t perftest_store(struct device *dev, static struct task_struct *worker_task; int ret; - int cpu = 5; + perf->ipi_cpu[0] = -1; if (ppa->use_exclusive_irq) { perf->ipi_cpu[0] = 4; perf->ipi_cpu[1] = 4; @@ -920,11 +1197,23 @@ static ssize_t perftest_store(struct device *dev, perf->ipi_cpu[3] = 4; } - ret = sscanf(buf, "%d %d %hu %d %d %hx:%hx:%hx:%hx:%hx:%hx:%hx:%hx %d %d %d %d", - &perf->mode, &perf->session, &perf->ch, &cpu, &perf->udelay, - &perf->clat_ipv6[0], &perf->clat_ipv6[1], &perf->clat_ipv6[2], &perf->clat_ipv6[3], - &perf->clat_ipv6[4], &perf->clat_ipv6[5], &perf->clat_ipv6[6], &perf->clat_ipv6[7], - &perf->ipi_cpu[0], &perf->ipi_cpu[1], &perf->ipi_cpu[2], &perf->ipi_cpu[3]); + switch (perf->mode) { + case PERFTEST_MODE_CLAT: + ret = sscanf(buf, "%d %d %hu %d %d %hx:%hx:%hx:%hx:%hx:%hx:%hx:%hx %d %d %d %d", + &perf->mode, &perf->session, &perf->ch, &perf->cpu, &perf->udelay, + &perf->clat_ipv6[0], &perf->clat_ipv6[1], &perf->clat_ipv6[2], + &perf->clat_ipv6[3], &perf->clat_ipv6[4], &perf->clat_ipv6[5], + &perf->clat_ipv6[6], &perf->clat_ipv6[7], + &perf->ipi_cpu[0], &perf->ipi_cpu[1], &perf->ipi_cpu[2], + &perf->ipi_cpu[3]); + break; + default: + ret = sscanf(buf, "%d %d %hu %d %d %d %d %d %d", + &perf->mode, &perf->session, &perf->ch, &perf->cpu, &perf->udelay, + &perf->ipi_cpu[0], &perf->ipi_cpu[1], &perf->ipi_cpu[2], + &perf->ipi_cpu[3]); + break; + } if (ret < 1) return -EINVAL; @@ -948,8 +1237,8 @@ static ssize_t perftest_store(struct device *dev, perf->test_run = true; worker_task = kthread_create_on_node(pktproc_perftest_thread, - mld, cpu_to_node(cpu), "perftest/%d", cpu); - kthread_bind(worker_task, cpu); + mld, cpu_to_node(perf->cpu), "perftest/%d", perf->cpu); + kthread_bind(worker_task, perf->cpu); wake_up_process(worker_task); break; default: @@ -1025,11 +1314,6 @@ static int pktproc_poll(struct napi_struct *napi, int budget) if ((ret == -EBUSY) || (ret == -ENOMEM)) goto poll_retry; - if (atomic_read(&q->stop_napi_poll)) { - atomic_set(&q->stop_napi_poll, 0); - goto poll_exit; - } - if (rcvd < budget) { napi_complete_done(napi, rcvd); q->enable_irq(q); @@ -1053,7 +1337,6 @@ static int pktproc_poll(struct napi_struct *napi, int budget) static irqreturn_t pktproc_irq_handler(int irq, void *arg) { struct pktproc_queue *q = (struct pktproc_queue *)arg; - int ret = 0; if (!q) { mif_err_limited("q is null\n"); @@ -1067,15 +1350,9 @@ static irqreturn_t pktproc_irq_handler(int irq, void *arg) tpmon_start(); #endif - if (q->ppa->use_napi) { - if (napi_schedule_prep(q->napi_ptr)) { - q->disable_irq(q); - __napi_schedule(q->napi_ptr); - } - } else { - ret = q->clean_rx_ring(q, 0, NULL); - if ((ret == -EBUSY) || (ret == -ENOMEM)) - return IRQ_HANDLED; + if (napi_schedule_prep(q->napi_ptr)) { + q->disable_irq(q); + __napi_schedule(q->napi_ptr); } return IRQ_HANDLED; @@ -1094,42 +1371,31 @@ static ssize_t region_show(struct device *dev, struct device_attribute *attr, ch int i; count += scnprintf(&buf[count], PAGE_SIZE - count, "Version:%d\n", ppa->version); - count += scnprintf(&buf[count], PAGE_SIZE - count, "CP base:0x%08x\n", ppa->cp_base); + count += scnprintf(&buf[count], PAGE_SIZE - count, "CP base:0x%08llx\n", ppa->cp_base); count += scnprintf(&buf[count], PAGE_SIZE - count, "Descriptor mode:%d\n", ppa->desc_mode); count += scnprintf(&buf[count], PAGE_SIZE - count, "Num of queue:%d\n", ppa->num_queue); - count += scnprintf(&buf[count], PAGE_SIZE - count, "Buffer manager:%d\n", - ppa->use_buff_mng); - count += scnprintf(&buf[count], PAGE_SIZE - count, "NAPI:%d\n", ppa->use_napi); + count += scnprintf(&buf[count], PAGE_SIZE - count, "NetRX manager:%d\n", + ppa->use_netrx_mng); count += scnprintf(&buf[count], PAGE_SIZE - count, "Exclusive interrupt:%d\n", ppa->use_exclusive_irq); count += scnprintf(&buf[count], PAGE_SIZE - count, "HW cache coherency:%d\n", ppa->use_hw_iocc); count += scnprintf(&buf[count], PAGE_SIZE - count, "Max packet size:%d\n", ppa->max_packet_size); + if (ppa->true_packet_size != ppa->max_packet_size) { + count += scnprintf(&buf[count], PAGE_SIZE - count, "True packet size:%d\n", + ppa->true_packet_size); + } count += scnprintf(&buf[count], PAGE_SIZE - count, "Padding size:%d\n", ppa->skb_padding_size); count += scnprintf(&buf[count], PAGE_SIZE - count, "Dedicated BAAW:%d\n", ppa->use_dedicated_baaw); - count += scnprintf(&buf[count], PAGE_SIZE - count, "36bit data addr:%d\n", - ppa->use_36bit_data_addr); - count += scnprintf(&buf[count], PAGE_SIZE - count, "info_desc:%s/buff:%s\n", - ppa->info_desc_rgn_cached ? "C" : "NC", + count += scnprintf(&buf[count], PAGE_SIZE - count, "info:%s desc:%s/buff:%s\n", + ppa->info_rgn_cached ? "C" : "NC", + ppa->desc_rgn_cached ? "C" : "NC", ppa->buff_rgn_cached ? "C" : "NC"); count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); - if (ppa->manager) { - count += scnprintf(&buf[count], PAGE_SIZE - count, "Buffer manager\n"); - count += scnprintf(&buf[count], PAGE_SIZE - count, " buffer size:0x%08x\n", - ppa->manager->buffer_size); - count += scnprintf(&buf[count], PAGE_SIZE - count, " total cell count:%d\n", - ppa->manager->cell_count); - count += scnprintf(&buf[count], PAGE_SIZE - count, " cell size:%d\n", - ppa->manager->cell_size); - count += scnprintf(&buf[count], PAGE_SIZE - count, " enable sw zerocopy:%d\n", - ppa->manager->enable_sw_zerocopy); - count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); - } - for (i = 0; i < ppa->num_queue; i++) { struct pktproc_queue *q = ppa->q[i]; @@ -1150,8 +1416,24 @@ static ssize_t region_show(struct device *dev, struct device_attribute *attr, ch q->q_info_ptr->cp_buff_pbase); count += scnprintf(&buf[count], PAGE_SIZE - count, " q_buff_size:0x%08x\n", q->q_buff_size); +#if IS_ENABLED(CONFIG_EXYNOS_DIT) count += scnprintf(&buf[count], PAGE_SIZE - count, " DIT:%d\n", dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)); +#endif + +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->manager) { + count += scnprintf(&buf[count], PAGE_SIZE - count, + "Buffer manager\n"); + count += scnprintf(&buf[count], PAGE_SIZE - count, + " total number of packets:%llu\n", + q->manager->num_packet); + count += scnprintf(&buf[count], PAGE_SIZE - count, + " frag size:%llu\n", + q->manager->frag_size); + count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); + } +#endif } return count; @@ -1166,14 +1448,6 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch ssize_t count = 0; int i; - if (ppa->manager) { - count += scnprintf(&buf[count], PAGE_SIZE - count, - "Buffer manager total/use/free:%d/%d/%d\n", - ppa->manager->cell_count, ppa->manager->used_cell_count, - ppa->manager->free_cell_count); - count += scnprintf(&buf[count], PAGE_SIZE - count, "\n"); - } - for (i = 0; i < ppa->num_queue; i++) { struct pktproc_queue *q = ppa->q[i]; @@ -1202,25 +1476,29 @@ static ssize_t status_show(struct device *dev, struct device_attribute *attr, ch circ_get_usage(q->num_desc, *q->fore_ptr, *q->rear_ptr), circ_get_usage(q->num_desc, *q->rear_ptr, q->done_ptr), circ_get_usage(q->num_desc, *q->rear_ptr, *q->fore_ptr)); - if (!dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)) - count += scnprintf(&buf[count], PAGE_SIZE - count, - " use memcpy:%d count:%lld\n", - q->use_memcpy, q->stat.use_memcpy_cnt); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + count += scnprintf(&buf[count], PAGE_SIZE - count, + " iommu_mapped cnt:%u size:0x%llX\n", + q->ioc.mapped_cnt, q->ioc.mapped_size); +#endif break; default: break; } - count += scnprintf(&buf[count], PAGE_SIZE - count, " pass:%lld\n", - q->stat.pass_cnt); + count += scnprintf(&buf[count], PAGE_SIZE - count, " pass:%lld lro:%lld\n", + q->stat.pass_cnt, q->stat.lro_cnt); count += scnprintf(&buf[count], PAGE_SIZE - count, " fail:len%lld chid%lld addr%lld nomem%lld bmnomem%lld csum%lld\n", q->stat.err_len, q->stat.err_chid, q->stat.err_addr, q->stat.err_nomem, q->stat.err_bm_nomem, q->stat.err_csum); + +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (dit_check_dir_use_queue(DIT_DIR_RX, q->q_idx)) count += scnprintf(&buf[count], PAGE_SIZE - count, " fail:enqueue_dit%lld\n", q->stat.err_enqueue_dit); +#endif } return count; @@ -1251,38 +1529,40 @@ int pktproc_init(struct pktproc_adaptor *ppa) { int i; int ret = 0; + struct mem_link_device *mld; if (!ppa) { mif_err("ppa is null\n"); return -EPERM; } - if (!pktproc_check_support(ppa)) - return 0; + mld = container_of(ppa, struct mem_link_device, pktproc); - mif_info("version:%d cp_base:0x%08x desc_mode:%d num_queue:%d\n", + mif_info("version:%d cp_base:0x%08llx desc_mode:%d num_queue:%d\n", ppa->version, ppa->cp_base, ppa->desc_mode, ppa->num_queue); - mif_info("interrupt:%d napi:%d iocc:%d max_packet_size:%d\n", - ppa->use_exclusive_irq, ppa->use_napi, - ppa->use_hw_iocc, ppa->max_packet_size); - - if (ppa->manager) - mif_info("buffer_size:0x%08x cell_count:%d cell_size:%d sw_zeocopy:%d\n", - ppa->manager->buffer_size, ppa->manager->cell_count, - ppa->manager->cell_size, ppa->manager->enable_sw_zerocopy); + mif_info("interrupt:%d iocc:%d max_packet_size:%d\n", + ppa->use_exclusive_irq, ppa->use_hw_iocc, ppa->max_packet_size); for (i = 0; i < ppa->num_queue; i++) { struct pktproc_queue *q = ppa->q[i]; mif_info("Q%d\n", i); - if (ppa->use_napi) - napi_synchronize(&q->napi); + napi_synchronize(&q->napi); switch (ppa->desc_mode) { case DESC_MODE_SKTBUF: +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + cpif_pcie_iommu_reset(q); +#endif if (pktproc_check_active(q->ppa, q->q_idx)) q->clear_data_addr(q); +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR) + if (q->manager) + mif_info("num packets:%llu frag size:%llu\n", + q->manager->num_packet, + q->manager->frag_size); +#endif break; default: break; @@ -1292,17 +1572,30 @@ int pktproc_init(struct pktproc_adaptor *ppa) *q->rear_ptr = 0; q->done_ptr = 0; - q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; + if (mld->pktproc_use_36bit_addr) { + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase >> 4; + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase >> 4; + } else { + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; + } + q->q_info_ptr->num_desc = q->num_desc; - q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; memset(&q->stat, 0, sizeof(struct pktproc_statistics)); switch (ppa->desc_mode) { case DESC_MODE_SKTBUF: +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + ret = cpif_pcie_iommu_init(q); + if (ret) { + mif_err("cpif_pcie_iommu_init() error %d Q%d\n", ret, q->q_idx); + continue; + } +#endif ret = q->alloc_rx_buf(q); if (ret) { - mif_err_limited("alloc_rx_buf() error %d Q%d\n", ret, q->q_idx); + mif_err("alloc_rx_buf() error %d Q%d\n", ret, q->q_idx); continue; } break; @@ -1311,8 +1604,9 @@ int pktproc_init(struct pktproc_adaptor *ppa) } mif_info("num_desc:0x%08x cp_desc_pbase:0x%08x desc_size:0x%08x\n", - q->num_desc, q->cp_desc_pbase, q->desc_size); - mif_info("cp_buff_pbase:0x%08x q_buff_size:0x%08x\n", + q->q_info_ptr->num_desc, q->q_info_ptr->cp_desc_pbase, + q->desc_size); + mif_info("cp_buff_pbase:0x%08llx q_buff_size:0x%08x\n", q->cp_buff_pbase, q->q_buff_size); mif_info("fore:%d rear:%d done:%d\n", *q->fore_ptr, *q->rear_ptr, q->done_ptr); @@ -1326,40 +1620,82 @@ int pktproc_init(struct pktproc_adaptor *ppa) /* * Create PktProc */ -static int pktproc_create_buffer_manager(struct pktproc_adaptor *ppa, u32 buff_size) +static int pktproc_create_buffer_manager(struct pktproc_queue *q, u64 ap_desc_pbase) { + struct pktproc_adaptor *ppa; + unsigned int desc_total_size = 0; + struct cpif_addr_pair desc_addr_pair; + u64 frag_size = 0; /* size of fragmenting a page */ + + if (!q) { + mif_err("q is null\n"); + return -EINVAL; + } + + desc_total_size = q->num_desc * sizeof(struct pktproc_desc_sktbuf); + ppa = q->ppa; if (!ppa) { mif_err("ppa is null\n"); return -EINVAL; } - if (!ppa->use_buff_mng) { - mif_err("use_buff_mng is not set\n"); + if (!ppa->use_netrx_mng) { + mif_err("use_netrx_mng is not set\n"); return -EINVAL; } - if (ppa->manager != NULL) { + if (q->manager != NULL) { mif_info("buffer manager is already initialized\n"); return 0; } - /* Use only one buffer manager for all queues */ - ppa->manager = init_mif_buff_mng(ppa->buff_vbase, buff_size, - ppa->max_packet_size + MIF_BUFF_CELL_PADDING_SIZE); - if (!ppa->manager) { - mif_err("init_mif_buff_mng() error\n"); + desc_addr_pair.cp_addr = q->cp_desc_pbase; + desc_addr_pair.ap_addr = phys_to_virt(ap_desc_pbase); + frag_size = SKB_DATA_ALIGN(ppa->max_packet_size + ppa->skb_padding_size) + + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + mif_info("about to init netrx mng: cp_addr: 0x%llX ap_addr: %pK frag_size: %llu\n", + q->cp_desc_pbase, q->desc_sktbuf, frag_size); + mif_info("desc_total_size:%d cp_buff_pbase: 0x%llX num_desc: %d\n", + desc_total_size, q->cp_buff_pbase, q->num_desc); + q->manager = cpif_create_netrx_mng(&desc_addr_pair, desc_total_size, + q->cp_buff_pbase, frag_size, + q->num_desc); + if (!q->manager) { + mif_err("cpif_create_netrx_mng() error\n"); return -ENOMEM; } return 0; } +static void pktproc_adjust_size(struct pktproc_adaptor *ppa) +{ +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + ppa->skb_padding_size = SKB_FRONT_PADDING; +#else + if (ppa->use_netrx_mng) + ppa->skb_padding_size = SKB_FRONT_PADDING; + else + ppa->skb_padding_size = 0; +#endif + + ppa->true_packet_size = ppa->max_packet_size; +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + ppa->true_packet_size += ppa->skb_padding_size; + ppa->true_packet_size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + + mif_info("adjusted iommu required:%u true_packet_size:%lu\n", + ppa->true_packet_size, roundup_pow_of_two(ppa->true_packet_size)); + ppa->true_packet_size = roundup_pow_of_two(ppa->true_packet_size); + ppa->space_margin = PAGE_FRAG_CACHE_MAX_SIZE / ppa->true_packet_size; +#endif +} + static int pktproc_get_info(struct pktproc_adaptor *ppa, struct device_node *np) { - int ret = 0; + mif_dt_read_u64(np, "pktproc_cp_base", ppa->cp_base); + mif_dt_read_u32(np, "pktproc_dl_version", ppa->version); - mif_dt_read_u32(np, "pktproc_version", ppa->version); - mif_dt_read_u32(np, "pktproc_cp_base", ppa->cp_base); switch (ppa->version) { case PKTPROC_V1: ppa->desc_mode = DESC_MODE_RINGBUF; @@ -1367,52 +1703,87 @@ static int pktproc_get_info(struct pktproc_adaptor *ppa, struct device_node *np) ppa->use_exclusive_irq = 0; break; case PKTPROC_V2: - mif_dt_read_u32(np, "pktproc_desc_mode", ppa->desc_mode); - mif_dt_read_u32(np, "pktproc_num_queue", ppa->num_queue); - mif_dt_read_u32(np, "pktproc_use_buff_mng", ppa->use_buff_mng); - mif_dt_read_u32(np, "pktproc_desc_num_ratio_percent", ppa->desc_num_ratio_percent); - mif_dt_read_u32(np, "pktproc_use_exclusive_irq", ppa->use_exclusive_irq); + mif_dt_read_u32(np, "pktproc_dl_desc_mode", ppa->desc_mode); + mif_dt_read_u32(np, "pktproc_dl_num_queue", ppa->num_queue); +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + mif_dt_read_u32(np, "pktproc_dl_use_netrx_mng", ppa->use_netrx_mng); + mif_dt_read_u32(np, "pktproc_dl_netrx_capacity", ppa->netrx_capacity); + /* Check if config and dt are consistent */ + if(ppa->use_netrx_mng != IS_ENABLED(CONFIG_EXYNOS_CPIF_NETRX_MGR)) { + mif_err("netrx mgr config and dt are inconsistent\n"); + panic("netrx mgr config and dt are inconsistent\n"); + return -EINVAL; + } +#else + ppa->use_netrx_mng = 0; + ppa->netrx_capacity = 0; +#endif + mif_dt_read_u32(np, "pktproc_dl_use_exclusive_irq", ppa->use_exclusive_irq); +#if IS_ENABLED(CONFIG_MCU_IPC) if (ppa->use_exclusive_irq) { - ret = of_property_read_u32_array(np, "pktproc_exclusive_irq_idx", + int ret; + + ret = of_property_read_u32_array(np, "pktproc_dl_exclusive_irq_idx", ppa->exclusive_irq_idx, ppa->num_queue); if (ret) { - mif_err("pktproc_exclusive_irq_idx error:%d\n", ret); + mif_err("pktproc_dl_exclusive_irq_idx error:%d\n", ret); return ret; } } - mif_dt_read_bool(np, "pktproc_use_napi", ppa->use_napi); - mif_dt_read_u32(np, "pktproc_use_36bit_data_addr", ppa->use_36bit_data_addr); +#endif break; default: mif_err("Unsupported version:%d\n", ppa->version); return -EINVAL; } - mif_info("version:%d cp_base:0x%08x mode:%d num_queue:%d\n", + mif_info("version:%d cp_base:0x%08llx mode:%d num_queue:%d\n", ppa->version, ppa->cp_base, ppa->desc_mode, ppa->num_queue); - mif_info("use_buff_mng:%d use_napi:%d exclusive_irq:%d\n", - ppa->use_buff_mng, ppa->use_napi, ppa->use_exclusive_irq); - - mif_dt_read_u32(np, "pktproc_use_hw_iocc", ppa->use_hw_iocc); - mif_dt_read_u32(np, "pktproc_max_packet_size", ppa->max_packet_size); - mif_dt_read_u32(np, "pktproc_use_dedicated_baaw", ppa->use_dedicated_baaw); - mif_info("iocc:%d max_packet_size:%d baaw:%d 36bit_data:%d\n", - ppa->use_hw_iocc, ppa->max_packet_size, - ppa->use_dedicated_baaw, ppa->use_36bit_data_addr); - - mif_dt_read_u32(np, "pktproc_info_rgn_offset", ppa->info_rgn_offset); - mif_dt_read_u32(np, "pktproc_info_rgn_size", ppa->info_rgn_size); - mif_dt_read_u32(np, "pktproc_desc_rgn_offset", ppa->desc_rgn_offset); - mif_dt_read_u32(np, "pktproc_desc_rgn_size", ppa->desc_rgn_size); - mif_dt_read_u32(np, "pktproc_buff_rgn_offset", ppa->buff_rgn_offset); - mif_info("info_rgn 0x%08x 0x%08x desc_rgn 0x%08x 0x%08x %u buff_rgn 0x%08x\n", + mif_info("use_netrx_mng:%d netrx_capacity:%d exclusive_irq:%d\n", + ppa->use_netrx_mng, ppa->netrx_capacity, ppa->use_exclusive_irq); + + mif_dt_read_u32(np, "pktproc_dl_use_hw_iocc", ppa->use_hw_iocc); + mif_dt_read_u32(np, "pktproc_dl_max_packet_size", ppa->max_packet_size); + mif_dt_read_u32(np, "pktproc_dl_use_dedicated_baaw", ppa->use_dedicated_baaw); + mif_info("iocc:%d max_packet_size:%d baaw:%d\n", + ppa->use_hw_iocc, ppa->max_packet_size, ppa->use_dedicated_baaw); + + mif_dt_read_u32(np, "pktproc_dl_info_rgn_offset", ppa->info_rgn_offset); + mif_dt_read_u32(np, "pktproc_dl_info_rgn_size", ppa->info_rgn_size); + mif_dt_read_u32(np, "pktproc_dl_desc_rgn_offset", ppa->desc_rgn_offset); + mif_dt_read_u32(np, "pktproc_dl_desc_rgn_size", ppa->desc_rgn_size); + mif_dt_read_u32(np, "pktproc_dl_buff_rgn_offset", ppa->buff_rgn_offset); + mif_dt_read_u32(np, "pktproc_dl_buff_rgn_size", ppa->buff_rgn_size); + mif_info("info_rgn 0x%08x 0x%08x desc_rgn 0x%08x 0x%08x %u buff_rgn 0x%08x 0x%08x\n", ppa->info_rgn_offset, ppa->info_rgn_size, ppa->desc_rgn_offset, ppa->desc_rgn_size, - ppa->desc_num_ratio_percent, ppa->buff_rgn_offset); + ppa->desc_num_ratio_percent, + ppa->buff_rgn_offset, ppa->buff_rgn_size); + + mif_dt_read_u32(np, "pktproc_dl_info_rgn_cached", ppa->info_rgn_cached); + mif_dt_read_u32(np, "pktproc_dl_desc_rgn_cached", ppa->desc_rgn_cached); + mif_dt_read_u32(np, "pktproc_dl_buff_rgn_cached", ppa->buff_rgn_cached); + mif_info("cached:%d/%d/%d\n", ppa->info_rgn_cached, ppa->desc_rgn_cached, + ppa->buff_rgn_cached); + if (ppa->use_netrx_mng && !ppa->buff_rgn_cached) { + mif_err("Buffer manager requires cached buff region\n"); + return -EINVAL; + } +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + if (ppa->use_netrx_mng || !ppa->buff_rgn_cached || ppa->desc_mode != DESC_MODE_SKTBUF) { + mif_err("not compatible with pcie iommu\n"); + return -EINVAL; + } +#endif + + /* Check if config and dt are consistent */ + if (ppa->use_hw_iocc != IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC)) { + mif_err("PCIe IOCC config and dt are inconsistent\n"); + panic("PCIe IOCC config and dt are inconsistent\n"); + return -EINVAL; + } - mif_dt_read_u32(np, "pktproc_info_desc_rgn_cached", ppa->info_desc_rgn_cached); - mif_dt_read_u32(np, "pktproc_buff_rgn_cached", ppa->buff_rgn_cached); - mif_info("cached:%d/%d\n", ppa->info_desc_rgn_cached, ppa->buff_rgn_cached); + pktproc_adjust_size(ppa); return 0; } @@ -1422,7 +1793,8 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, { struct device_node *np = pdev->dev.of_node; struct pktproc_adaptor *ppa = &mld->pktproc; - u32 buff_size, buff_size_by_q; + u32 buff_size_by_q, accum_buff_size; + u32 alloc_size; int i; int ret = 0; @@ -1437,9 +1809,10 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, ppa->dev = &pdev->dev; - mif_dt_read_u32_noerr(np, "pktproc_support", ppa->support); + mif_dt_read_u32_noerr(np, "pktproc_dl_support", ppa->support); if (!ppa->support) { - mif_info("pktproc_support is 0. Just return\n"); + mif_err("pktproc_support is 0.\n"); + panic("pktproc_support is 0\n"); return 0; } @@ -1450,46 +1823,68 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, return ret; } + if (!ppa->use_hw_iocc && ppa->info_rgn_cached) { + mif_err("cannot support sw iocc based caching on info region\n"); + return -EINVAL; + } + + if (!ppa->use_hw_iocc && ppa->desc_rgn_cached) { + mif_err("cannot support sw iocc based caching on desc region\n"); + return -EINVAL; + } + /* Get base addr */ mif_info("memaddr:0x%lx memsize:0x%08x\n", memaddr, memsize); - if (ppa->info_desc_rgn_cached) { + + if (ppa->info_rgn_cached) ppa->info_vbase = phys_to_virt(memaddr + ppa->info_rgn_offset); - ppa->desc_vbase = phys_to_virt(memaddr + ppa->desc_rgn_offset); - } else { + else { ppa->info_vbase = cp_shmem_get_nc_region(memaddr + ppa->info_rgn_offset, - ppa->info_rgn_size + ppa->desc_rgn_size); + ppa->info_rgn_size); if (!ppa->info_vbase) { mif_err("ppa->info_base error\n"); return -ENOMEM; } - ppa->desc_vbase = ppa->info_vbase + ppa->info_rgn_size; } - memset(ppa->info_vbase, 0, ppa->info_rgn_size + ppa->desc_rgn_size); - mif_info("info + desc size:0x%08x\n", ppa->info_rgn_size + ppa->desc_rgn_size); - buff_size = memsize - (ppa->info_rgn_size + ppa->desc_rgn_size); - buff_size_by_q = buff_size / ppa->num_queue; - ppa->buff_pbase = memaddr + ppa->buff_rgn_offset; - if (ppa->buff_rgn_cached) - ppa->buff_vbase = phys_to_virt(ppa->buff_pbase); - else - ppa->buff_vbase = cp_shmem_get_nc_region(ppa->buff_pbase, buff_size); - mif_info("Total buff buffer size:0x%08x Queue:%d Size by queue:0x%08x\n", - buff_size, ppa->num_queue, buff_size_by_q); - - /* Create buffer manager */ - if (ppa->use_buff_mng) { - mif_info("create buffer manager\n"); - ret = pktproc_create_buffer_manager(ppa, buff_size); - if (ret < 0) { - mif_err("pktproc_create_buffer_manager() error:%d\n", ret); - goto create_error; + if (ppa->desc_rgn_cached) + ppa->desc_vbase = phys_to_virt(memaddr + ppa->desc_rgn_offset); + else { + ppa->desc_vbase = cp_shmem_get_nc_region(memaddr + ppa->desc_rgn_offset, + ppa->desc_rgn_size); + if (!ppa->desc_vbase) { + mif_err("ppa->desc_base error\n"); + return -ENOMEM; } - ppa->skb_padding_size = NET_SKB_PAD + NET_IP_ALIGN; - } else { - ppa->manager = NULL; - ppa->skb_padding_size = 0; } + memset(ppa->info_vbase, 0, ppa->info_rgn_size); + memset(ppa->desc_vbase, 0, ppa->desc_rgn_size); + mif_info("info + desc size:0x%08x\n", ppa->info_rgn_size + ppa->desc_rgn_size); + + if (!ppa->use_netrx_mng) { + buff_size_by_q = ppa->buff_rgn_size / ppa->num_queue; +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + mif_info("Rounded down queue size from 0x%08x to 0x%08x\n", + buff_size_by_q, rounddown(buff_size_by_q, SZ_4K)); + buff_size_by_q = rounddown(buff_size_by_q, SZ_4K); +#endif + ppa->buff_pbase = memaddr + ppa->buff_rgn_offset; + if (ppa->buff_rgn_cached) { + ppa->buff_vbase = phys_to_virt(ppa->buff_pbase); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + mif_info("release iommu buffer region offset:0x%08x\n", + ppa->buff_rgn_offset); + cp_shmem_release_rmem(mld->link_dev.mdm_data->cp_num, + SHMEM_PKTPROC, ppa->buff_rgn_offset); +#endif + } else { + ppa->buff_vbase = cp_shmem_get_nc_region(ppa->buff_pbase, + ppa->buff_rgn_size); + } + mif_info("Total buff buffer size:0x%08x Queue:%d Size by queue:0x%08x\n", + ppa->buff_rgn_size, ppa->num_queue, buff_size_by_q); + } else + accum_buff_size = 0; /* Create queue */ for (i = 0; i < ppa->num_queue; i++) { @@ -1504,9 +1899,9 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, goto create_error; } q = ppa->q[i]; + q->ppa = ppa; atomic_set(&q->active, 0); - atomic_set(&q->stop_napi_poll, 0); /* Info region */ switch (ppa->version) { @@ -1520,7 +1915,6 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->info_v2->desc_mode = ppa->desc_mode; q->info_v2->irq_mode = ppa->use_exclusive_irq; q->info_v2->max_packet_size = ppa->max_packet_size; - q->q_info_ptr = &q->info_v2->q_info[i]; break; default: @@ -1536,13 +1930,17 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->q_buff_vbase = ppa->buff_vbase + (i * buff_size_by_q); q->cp_buff_pbase = ppa->cp_base + ppa->buff_rgn_offset + (i * buff_size_by_q); - q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; + if (mld->pktproc_use_36bit_addr) + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase >> 4; + else + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; q->q_buff_size = buff_size_by_q; - if (q->ppa->buff_rgn_cached && !ppa->use_hw_iocc) - dma_sync_single_for_device(q->ppa->dev, +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + if (ppa->buff_rgn_cached && !ppa->use_hw_iocc) + dma_sync_single_for_device(ppa->dev, q->q_buff_pbase, q->q_buff_size, DMA_FROM_DEVICE); - - q->num_desc = buff_size_by_q / ppa->max_packet_size; +#endif + q->num_desc = buff_size_by_q / ppa->true_packet_size; q->q_info_ptr->num_desc = q->num_desc; q->desc_ringbuf = ppa->desc_vbase + @@ -1551,34 +1949,39 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->cp_desc_pbase = ppa->cp_base + ppa->desc_rgn_offset + (i * sizeof(struct pktproc_desc_ringbuf) * q->num_desc); - q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; + if (mld->pktproc_use_36bit_addr) + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase >> 4; + else + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; q->desc_size = sizeof(struct pktproc_desc_ringbuf) * q->num_desc; q->get_packet = pktproc_get_pkt_from_ringbuf_mode; q->irq_handler = pktproc_irq_handler; break; case DESC_MODE_SKTBUF: - q->manager = ppa->manager; - if (q->manager) { - q->q_buff_pbase = ppa->buff_pbase; - q->q_buff_vbase = ppa->buff_vbase; - q->cp_buff_pbase = ppa->cp_base + ppa->buff_rgn_offset; - q->q_buff_size = buff_size; - q->num_desc = (buff_size_by_q / q->manager->cell_size) * - ppa->desc_num_ratio_percent / 100; + if (ppa->use_netrx_mng) { + q->num_desc = ppa->netrx_capacity; q->alloc_rx_buf = pktproc_fill_data_addr; q->clear_data_addr = pktproc_clear_data_addr; + q->cp_buff_pbase = ppa->cp_base + ppa->buff_rgn_offset + + accum_buff_size; + } else { q->q_buff_pbase = ppa->buff_pbase + (i * buff_size_by_q); q->q_buff_vbase = ppa->buff_vbase + (i * buff_size_by_q); q->cp_buff_pbase = ppa->cp_base + ppa->buff_rgn_offset + (i * buff_size_by_q); q->q_buff_size = buff_size_by_q; - q->num_desc = buff_size_by_q / ppa->max_packet_size; + q->num_desc = buff_size_by_q / ppa->true_packet_size; q->alloc_rx_buf = pktproc_fill_data_addr_without_bm; q->clear_data_addr = pktproc_clear_data_addr_without_bm; } - q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; + + if (mld->pktproc_use_36bit_addr) + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase >> 4; + else + q->q_info_ptr->cp_buff_pbase = q->cp_buff_pbase; + q->q_info_ptr->num_desc = q->num_desc; q->desc_sktbuf = ppa->desc_vbase + @@ -1587,16 +1990,38 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->cp_desc_pbase = ppa->cp_base + ppa->desc_rgn_offset + (i * sizeof(struct pktproc_desc_sktbuf) * q->num_desc); - q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; + if (mld->pktproc_use_36bit_addr) + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase >> 4; + else + q->q_info_ptr->cp_desc_pbase = q->cp_desc_pbase; + + mif_info("cp_desc_pbase - 36bit addr: 0x%08llx, 32bit addr: 0x%08x\n", + q->cp_desc_pbase, q->q_info_ptr->cp_desc_pbase); + q->desc_size = sizeof(struct pktproc_desc_sktbuf) * q->num_desc; - q->dma_addr = kzalloc(q->desc_size, GFP_KERNEL); + alloc_size = sizeof(dma_addr_t) * q->num_desc; + q->dma_addr = kzalloc(alloc_size, GFP_KERNEL); if (!q->dma_addr) { mif_err("kzalloc() dma_addr failed\n"); ret = -ENOMEM; goto create_error; } + if (ppa->use_netrx_mng) { + /* to make phys_to_virt macro operable */ + u64 ap_desc_pbase = memaddr + ppa->desc_rgn_offset + + (i * sizeof(struct pktproc_desc_sktbuf) + * q->num_desc); + mif_info("create buffer manager\n"); + ret = pktproc_create_buffer_manager(q, ap_desc_pbase); + if (ret < 0) { + mif_err("failed to create netrx mng:%d\n", ret); + goto create_error; + } + accum_buff_size += q->manager->total_buf_size; + } + q->get_packet = pktproc_get_pkt_from_sktbuf_mode; q->irq_handler = pktproc_irq_handler; q->update_fore_ptr = pktproc_update_fore_ptr; @@ -1607,8 +2032,9 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, goto create_error; } - if ((q->cp_desc_pbase + q->desc_size) > q->cp_buff_pbase) { - mif_err("Descriptor overflow:0x%08x 0x%08x 0x%08x\n", + if ((!q->manager) && + (q->cp_desc_pbase + q->desc_size) > q->cp_buff_pbase) { + mif_err("Descriptor overflow:0x%08llx 0x%08x 0x%08llx\n", q->cp_desc_pbase, q->desc_size, q->cp_buff_pbase); ret = -EINVAL; goto create_error; @@ -1620,27 +2046,23 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->q_idx = i; q->mld = mld; - q->ppa = ppa; /* NAPI */ - if (ppa->use_napi) { - if (ppa->use_exclusive_irq) { - init_dummy_netdev(&q->netdev); - netif_napi_add(&q->netdev, &q->napi, pktproc_poll, - NAPI_POLL_WEIGHT); - napi_enable(&q->napi); - q->napi_ptr = &q->napi; - } else { - q->napi_ptr = &q->mld->mld_napi; - } + if (ppa->use_exclusive_irq) { + init_dummy_netdev(&q->netdev); + netif_napi_add(&q->netdev, &q->napi, pktproc_poll, NAPI_POLL_WEIGHT); + napi_enable(&q->napi); + q->napi_ptr = &q->napi; + } else { + q->napi_ptr = &q->mld->mld_napi; } /* IRQ handler */ q->enable_irq = pktproc_enable_irq; q->disable_irq = pktproc_disable_irq; if (ppa->use_exclusive_irq) { - q->irq_idx = ppa->exclusive_irq_idx[q->q_idx]; #if IS_ENABLED(CONFIG_MCU_IPC) + q->irq_idx = ppa->exclusive_irq_idx[q->q_idx]; ret = cp_mbox_register_handler(q->irq_idx, mld->irq_cp2ap_msg, q->irq_handler, q); if (ret) { @@ -1660,22 +2082,28 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, q->rear_ptr = &q->q_info_ptr->rear_ptr; q->done_ptr = *q->rear_ptr; - mif_info("num_desc:%d cp_desc_pbase:0x%08x desc_size:0x%08x\n", + mif_info("num_desc:%d cp_desc_pbase:0x%08llx desc_size:0x%08x\n", q->num_desc, q->cp_desc_pbase, q->desc_size); - mif_info("cp_buff_pbase:0x%08x buff_size:0x%08x\n", - q->cp_buff_pbase, q->q_buff_size); - } + if (!q->manager) + mif_info("cp_buff_pbase:0x%08llx buff_size:0x%08x\n", + q->cp_buff_pbase, q->q_buff_size); #if IS_ENABLED(CONFIG_EXYNOS_DIT) - ret = dit_set_buf_size(DIT_DIR_RX, ppa->max_packet_size); - if (ret) - mif_err("dit_set_buf_size() error:%d\n", ret); + if (q->q_idx == 0) { + ret = dit_set_pktproc_queue_num(DIT_DIR_RX, q->q_idx); + if (ret) + mif_err("dit_set_buf_size() error:%d\n", ret); - ret = dit_set_desc_ring_len(DIT_DIR_RX, - ppa->q[DIT_PKTPROC_RX_QUEUE_NUM]->num_desc - 1); - if (ret) - mif_err("dit_set_desc_ring_len() error:%d\n", ret); + ret = dit_set_buf_size(DIT_DIR_RX, ppa->max_packet_size); + if (ret) + mif_err("dit_set_buf_size() error:%d\n", ret); + + ret = dit_set_desc_ring_len(DIT_DIR_RX, q->num_desc - 1); + if (ret) + mif_err("dit_set_desc_ring_len() error:%d\n", ret); + } #endif + } /* Debug */ ret = sysfs_create_group(&pdev->dev.kobj, &pktproc_group); @@ -1688,18 +2116,22 @@ int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, create_error: for (i = 0; i < ppa->num_queue; i++) { + if (!ppa->q[i]) + continue; + + if (ppa->q[i]->manager) + cpif_exit_netrx_mng(ppa->q[i]->manager); + kfree(ppa->q[i]->dma_addr); kfree(ppa->q[i]); } - if (ppa->manager) - exit_mif_buff_mng(ppa->manager); - + if (!ppa->info_rgn_cached && ppa->info_vbase) + vunmap(ppa->info_vbase); + if (!ppa->desc_rgn_cached && ppa->desc_vbase) + vunmap(ppa->desc_vbase); if (!ppa->buff_rgn_cached && ppa->buff_vbase) vunmap(ppa->buff_vbase); - if (!ppa->info_desc_rgn_cached && ppa->info_vbase) - vunmap(ppa->info_vbase); - return ret; } diff --git a/drivers/soc/google/cpif/link_rx_pktproc.h b/drivers/soc/google/cpif/link_rx_pktproc.h index bc9cfba79813..2f26213ebd8d 100644 --- a/drivers/soc/google/cpif/link_rx_pktproc.h +++ b/drivers/soc/google/cpif/link_rx_pktproc.h @@ -7,6 +7,8 @@ #ifndef __LINK_RX_PKTPROC_H__ #define __LINK_RX_PKTPROC_H__ +#include "cpif_netrx_mng.h" + /* Debug */ /* #define PKTPROC_DEBUG */ /* #define PKTPROC_DEBUG_PKT */ @@ -28,6 +30,20 @@ #define PKTPROC_STATUS_IPCS 0x40 #define PKTPROC_STATUS_PFD 0x80 +#if IS_ENABLED(CONFIG_CP_PKTPROC_LRO) +/* LRO bit field */ +#define LRO_LAST_SEG 0x01 +#define LRO_MID_SEG 0x02 +#define LRO_FIRST_SEG 0x04 +#define LRO_PACKET 0x08 +#define LRO_MODE_ON 0x10 + +/* W/A padding for LRO packet (except first) TCP (60 bytes) + IPv6 (40 bytes) = 100 */ +#define SKB_FRONT_PADDING (NET_SKB_PAD + NET_IP_ALIGN + SKB_DATA_ALIGN(100)) +#else +#define SKB_FRONT_PADDING (NET_SKB_PAD + NET_IP_ALIGN) +#endif + /* * PktProc info region */ @@ -80,7 +96,8 @@ struct pktproc_desc_sktbuf { control:8, status:8, lro:5, - reserved1:3; + clat:2, + reserved1:1; u16 length; u16 filter_result; u16 information; @@ -93,16 +110,41 @@ struct pktproc_desc_sktbuf { /* Statistics */ struct pktproc_statistics { u64 pass_cnt; + u64 lro_cnt; u64 err_len; u64 err_chid; u64 err_addr; u64 err_nomem; u64 err_bm_nomem; u64 err_csum; - u64 use_memcpy_cnt; u64 err_enqueue_dit; }; +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) +struct cpif_pcie_iommu_ctrl { + struct page_frag_cache pf_cache; + u32 pf_offset; + u32 curr_fore; + + /* Will */ + unsigned long map_src_pa; + void *map_page_va; + u32 map_idx; + + unsigned long unmap_src_pa; + u32 unmap_page_size; + + /* Was */ + u32 end_map_size; + + /* These elements must be at the end */ + void **pf_buf; + /* Debug */ + u32 mapped_cnt; + u64 mapped_size; +}; +#endif + /* Logical view for each queue */ struct pktproc_queue { u32 q_idx; @@ -120,9 +162,9 @@ struct pktproc_queue { u32 done_ptr; /* Store */ - u32 cp_desc_pbase; + u64 cp_desc_pbase; u32 num_desc; - u32 cp_buff_pbase; + u64 cp_buff_pbase; /* Pointer to info region by version */ union { @@ -151,20 +193,27 @@ struct pktproc_queue { unsigned long q_buff_pbase; u32 q_buff_size; - /* Buffer manager */ - struct mif_buff_mng *manager; /* Pointer to buffer manager */ + /* CP interface network rx manager */ + struct cpif_netrx_mng *manager; /* Pointer to rx manager */ dma_addr_t *dma_addr; - bool use_memcpy; /* memcpy mode on sktbuf mode */ + +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + struct cpif_pcie_iommu_ctrl ioc; +#endif /* IRQ */ int irq; +#if IS_ENABLED(CONFIG_MCU_IPC) u32 irq_idx; +#endif +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) + bool msi_irq_wake; +#endif /* NAPI */ struct net_device netdev; struct napi_struct napi; struct napi_struct *napi_ptr; - atomic_t stop_napi_poll; /* Statistics */ struct pktproc_statistics stat; @@ -216,10 +265,10 @@ struct pktproc_perftest { int session; u16 ch; int cpu; + int ipi_cpu[PKTPROC_MAX_QUEUE]; int udelay; u32 seq_counter[PKTPROC_MAX_QUEUE]; u16 clat_ipv6[8]; - int ipi_cpu[PKTPROC_MAX_QUEUE]; }; struct pktproc_perftest_data { @@ -234,31 +283,37 @@ struct pktproc_adaptor { bool support; /* Is support PktProc feature? */ enum pktproc_version version; /* Version */ - u32 cp_base; /* CP base address for pktproc */ + u64 cp_base; /* CP base address for pktproc */ u32 info_rgn_offset; /* Offset of info region */ u32 info_rgn_size; /* Size of info region */ u32 desc_rgn_offset; /* Offset of descriptor region */ u32 desc_rgn_size; /* Size of descriptor region */ u32 buff_rgn_offset; /* Offset of data buffer region */ + u32 buff_rgn_size; /* Size of data buffer region */ - bool info_desc_rgn_cached; + bool info_rgn_cached; + bool desc_rgn_cached; bool buff_rgn_cached; enum pktproc_desc_mode desc_mode; /* Descriptor structure mode */ u32 desc_num_ratio_percent; /* Number of descriptors ratio as percent */ u32 num_queue; /* Number of queue */ +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + u32 space_margin; +#endif bool use_exclusive_irq; /* Exclusive interrupt */ +#if IS_ENABLED(CONFIG_MCU_IPC) u32 exclusive_irq_idx[PKTPROC_MAX_QUEUE]; +#endif bool use_hw_iocc; /* H/W IO cache coherency */ - u32 max_packet_size; /* Max packet size */ + u32 max_packet_size; /* Max packet size CP sees */ + u32 true_packet_size; /* True packet size AP allocated */ bool use_dedicated_baaw; /* BAAW for 36bit address */ - bool use_36bit_data_addr; /* Data is located to 36bit address range */ struct device *dev; - bool use_napi; - bool use_buff_mng; - struct mif_buff_mng *manager; /* Buffer manager */ + bool use_netrx_mng; + u32 netrx_capacity; u32 skb_padding_size; void __iomem *info_vbase; /* I/O region for information */ @@ -286,30 +341,11 @@ static inline int pktproc_check_support(struct pktproc_adaptor *ppa) static inline int pktproc_check_active(struct pktproc_adaptor *ppa, u32 q_idx) { - if (!pktproc_check_support(ppa)) - return 0; - if (!ppa->q[q_idx]) return 0; return atomic_read(&ppa->q[q_idx]->active); } - -static inline int pktproc_stop_napi_poll(struct pktproc_adaptor *ppa, u32 q_idx) -{ - if (!pktproc_check_support(ppa)) - return 0; - - if (!ppa->use_napi) - return 0; - - if (!ppa->q[q_idx]) - return 0; - - atomic_set(&ppa->q[q_idx]->stop_napi_poll, 1); - - return 0; -} #else static inline int pktproc_create(struct platform_device *pdev, struct mem_link_device *mld, unsigned long memaddr, u32 memsize) { return 0; } @@ -318,7 +354,6 @@ static inline int pktproc_get_usage(struct pktproc_queue *q) { return 0; } static inline int pktproc_get_usage_fore_rear(struct pktproc_queue *q) { return 0; } static inline int pktproc_check_support(struct pktproc_adaptor *ppa) { return 0; } static inline int pktproc_check_active(struct pktproc_adaptor *ppa, u32 q_idx) { return 0; } -static inline int pktproc_stop_napi_poll(struct pktproc_adaptor *ppa, u32 q_idx) { return 0; } #endif #endif /* __LINK_RX_PKTPROC_H__ */ diff --git a/drivers/soc/google/cpif/link_rx_zerocopy.c b/drivers/soc/google/cpif/link_rx_zerocopy.c deleted file mode 100644 index 2dd8da9bd137..000000000000 --- a/drivers/soc/google/cpif/link_rx_zerocopy.c +++ /dev/null @@ -1,497 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018 Samsung Electronics. - * - */ - -#include -#include "modem_prj.h" -#include "modem_utils.h" -#include "link_device_memory.h" -#include "include/sbd.h" - - -static u64 recv_offset_from_zerocopy_adaptor(struct zerocopy_adaptor *zdptr) -{ - struct sbd_ring_buffer *rb = zdptr->rb; - u16 out = zdptr->pre_rp; - u8 *src = rb->buff[out] + rb->payload_offset; - u64 offset; - - memcpy(&offset, src, sizeof(offset)); - - return offset; -} - -static u8 *data_offset_to_buffer(u64 offset, struct sbd_ring_buffer *rb) -{ - struct sbd_link_device *sl = rb->sl; - struct device *dev = sl->ld->dev; - u8 *v_zmb = cp_shmem_get_region(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - unsigned int zmb_size = cp_shmem_get_size(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - struct zerocopy_adaptor *zdptr = rb->zdptr; - dma_addr_t dma_addr; - int buf_offset; - u8 *buf = NULL; - - if (offset < (sl->zmb_offset + zmb_size)) { - buf_offset = offset - NET_HEADROOM; - buf = v_zmb + (buf_offset - sl->zmb_offset); - if (!(buf >= v_zmb && buf < (v_zmb + zmb_size))) { - mif_err("invalid buf (1st pool) : %p\n", buf); - return NULL; - } - } else { - mif_err("unexpected offset : %llx\n", offset); - return NULL; - } - - if (kfifo_out_spinlocked(&zdptr->fifo, &dma_addr, sizeof(dma_addr), - &zdptr->lock_kfifo) != sizeof(dma_addr)) { - mif_err("ERR! kfifo_out fails\n"); - mif_err("kfifo_len:%d\n", kfifo_len(&zdptr->fifo)); - mif_err("kfifo_is_empty:%d\n", kfifo_is_empty(&zdptr->fifo)); - mif_err("kfifo_is_full:%d\n", kfifo_is_full(&zdptr->fifo)); - mif_err("kfifo_avail:%d\n", kfifo_avail(&zdptr->fifo)); - return NULL; - } - dma_unmap_single(dev, dma_addr, MIF_BUFF_DEFAULT_CELL_SIZE, DMA_FROM_DEVICE); - - return buf; -} - -static u8 *unused_data_offset_to_buffer(u64 offset, struct sbd_ring_buffer *rb) -{ - struct sbd_link_device *sl = rb->sl; - u8 *v_zmb = cp_shmem_get_region(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - unsigned int zmb_size = cp_shmem_get_size(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - int buf_offset; - u8 *buf = NULL; - - if (offset < (sl->zmb_offset + zmb_size)) { - buf_offset = offset - NET_HEADROOM; - buf = v_zmb + (buf_offset - sl->zmb_offset); - if (!(buf >= v_zmb && buf < (v_zmb + zmb_size))) { - mif_err("invalid buf (1st pool) : %p\n", buf); - return NULL; - } - } else { - mif_err("unexpected offset : %llx\n", offset); - return NULL; - } - - return buf; -} - -static inline void free_zerocopy_data(struct sbd_ring_buffer *rb, u16 *out) -{ - struct zerocopy_adaptor *zdptr = rb->zdptr; - unsigned int qlen = zdptr->len; - u64 offset; - u8 *buff; - u8 *src = rb->buff[*out] + rb->payload_offset; - - memcpy(&offset, src, sizeof(offset)); - - buff = unused_data_offset_to_buffer(offset, rb); - - free_mif_buff(g_mif_buff_mng, buff); - - *out = circ_new_ptr(qlen, *out, 1); -} - -static void __reset_zerocopy(struct mem_link_device *mld, struct sbd_ring_buffer *rb) -{ - struct zerocopy_adaptor *zdptr = rb->zdptr; - u16 out = *zdptr->rp; - struct link_device *ld = &mld->link_dev; - struct modem_ctl *mc = ld->mc; - unsigned long flags; - - mif_err("ch: %d\n", rb->ch); - - /* cancel timer */ - spin_lock_irqsave(&mc->lock, flags); - if (hrtimer_active(&zdptr->datalloc_timer)) - hrtimer_cancel(&zdptr->datalloc_timer); - spin_unlock_irqrestore(&mc->lock, flags); - - /* free data */ - spin_lock_irqsave(&zdptr->lock, flags); - while (*zdptr->wp != out) - free_zerocopy_data(rb, &out); - spin_unlock_irqrestore(&zdptr->lock, flags); -} - -static void reset_zerocopy(struct link_device *ld) -{ - struct mem_link_device *mld = ld_to_mem_link_device(ld); - struct sbd_link_device *sl = &mld->sbd_link_dev; - struct sbd_ipc_device *ipc_dev = sl->ipc_dev; - struct sbd_ring_buffer *rb; - int i; - - if (sl->reset_zerocopy_done) - return; - - mif_err("+++\n"); - - for (i = 0; i < sl->num_channels; i++) { - rb = &ipc_dev[i].rb[DL]; - if (rb->zerocopy) - __reset_zerocopy(mld, rb); - } - - /* set done flag 1 as reset_zerocopy func works once */ - sl->reset_zerocopy_done = 1; - - mif_err("---\n"); -} - -/* sysfs */ -static ssize_t zmc_count_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct modem_data *modem; - - modem = (struct modem_data *)dev->platform_data; - - return scnprintf(buf, PAGE_SIZE, "memcpy_packet(%d)/zeromemcpy_packet(%d)\n", - modem->mld->memcpy_packet_count, modem->mld->zeromemcpy_packet_count); -} - -static ssize_t zmc_count_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct modem_data *modem; - unsigned int val = 0; - int ret; - - modem = (struct modem_data *)dev->platform_data; - ret = kstrtouint(buf, 0, &val); - - if (val == 0) { - modem->mld->memcpy_packet_count = 0; - modem->mld->zeromemcpy_packet_count = 0; - } - - return count; -} - -/* sysfs */ -static ssize_t mif_buff_mng_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - if (!g_mif_buff_mng) - return 0; - - return scnprintf(buf, PAGE_SIZE, "used(%d)/free(%d)/total(%d)\n", - g_mif_buff_mng->used_cell_count, g_mif_buff_mng->free_cell_count, - g_mif_buff_mng->cell_count); -} - -static ssize_t force_use_memcpy_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct modem_data *modem; - - modem = (struct modem_data *)dev->platform_data; - return scnprintf(buf, PAGE_SIZE, "%d\n", modem->mld->force_use_memcpy); -} - -static ssize_t force_use_memcpy_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct modem_data *modem; - unsigned int val = 0; - int ret; - - modem = (struct modem_data *)dev->platform_data; - ret = kstrtouint(buf, 0, &val); - - if (val == 0) - modem->mld->force_use_memcpy = 0; - else if (val == 1) - modem->mld->force_use_memcpy = 1; - return count; -} - -static DEVICE_ATTR_RO(mif_buff_mng); -static DEVICE_ATTR_RW(zmc_count); -static DEVICE_ATTR_RW(force_use_memcpy); - -static struct attribute *zerocopy_attrs[] = { - &dev_attr_mif_buff_mng.attr, - &dev_attr_zmc_count.attr, - &dev_attr_force_use_memcpy.attr, - NULL, -}; - -const struct attribute_group zerocopy_group = { - .attrs = zerocopy_attrs, - .name = "zerocopy", -}; - -/* Init */ -int setup_zerocopy_adaptor(struct sbd_ipc_device *ipc_dev) -{ - struct zerocopy_adaptor *zdptr; - struct sbd_ring_buffer *rb; - struct link_device *ld; - struct sbd_link_device *sl; - u32 cp_num; - - if (ipc_dev->zerocopy == false) { - ipc_dev->zdptr = NULL; - return 0; - } - - if (ipc_dev->zdptr == NULL) { - ipc_dev->zdptr = kzalloc(sizeof(struct zerocopy_adaptor), GFP_ATOMIC); - if (!ipc_dev->zdptr) { - mif_err("fail to allocate memory!\n"); - return -ENOMEM; - } - } - - /* register reset_zerocopy func */ - rb = &ipc_dev->rb[DL]; - sl = rb->sl; - ld = sl->ld; - ld->reset_zerocopy = reset_zerocopy; - - /* - * Initialize memory maps for Zero Memory Copy - */ - cp_num = ld->mdm_data->cp_num; - if (ld->mif_buff_mng == NULL) { - cp_shmem_get_region(cp_num, SHMEM_ZMC); - mif_info("zmb_base=%pK zmb_size:0x%X\n", - cp_shmem_get_region(cp_num, SHMEM_ZMC), - cp_shmem_get_size(cp_num, SHMEM_ZMC)); - - ld->mif_buff_mng = init_mif_buff_mng( - (unsigned char *)cp_shmem_get_region(cp_num, SHMEM_ZMC), - cp_shmem_get_size(cp_num, SHMEM_ZMC), - MIF_BUFF_DEFAULT_CELL_SIZE); - g_mif_buff_mng = ld->mif_buff_mng; - mif_info("g_mif_buff_mng:0x%pK size:0x%08x\n", - g_mif_buff_mng, cp_shmem_get_size(cp_num, SHMEM_ZMC)); - } - - zdptr = ipc_dev->zdptr; - - /* Setup DL direction RB & Zerocopy adaptor */ - rb->zdptr = zdptr; - - spin_lock_init(&zdptr->lock); - spin_lock_init(&zdptr->lock_kfifo); - zdptr->rb = rb; - zdptr->rp = rb->wp; /* swap wp, rp when zerocopy DL */ - zdptr->wp = rb->rp; /* swap wp, rp when zerocopy DL */ - zdptr->pre_rp = *zdptr->rp; - zdptr->len = rb->len; - - if (kfifo_initialized(&zdptr->fifo)) { - struct sbd_link_device *sl = rb->sl; - struct device *dev = sl->ld->dev; - dma_addr_t dma_addr; - - while (kfifo_out_spinlocked(&zdptr->fifo, &dma_addr, sizeof(dma_addr), - &zdptr->lock_kfifo) == sizeof(dma_addr)) { - dma_unmap_single(dev, dma_addr, MIF_BUFF_DEFAULT_CELL_SIZE, - DMA_FROM_DEVICE); - } - - kfifo_free(&zdptr->fifo); - } - - if (kfifo_alloc(&zdptr->fifo, zdptr->len * sizeof(dma_addr_t), GFP_KERNEL)) { - mif_err("kfifo alloc fail\n"); - return -ENOMEM; - } - - hrtimer_init(&zdptr->datalloc_timer, - CLOCK_MONOTONIC, HRTIMER_MODE_REL); - zdptr->datalloc_timer.function = datalloc_timer_func; - - allocate_data_in_advance(zdptr); - - /* set done flag 0 as reset_zerocopy func works */ - sl->reset_zerocopy_done = 0; - - return 0; -} - -static inline void set_skb_priv_zerocopy_adaptor(struct sbd_ring_buffer *rb, struct sk_buff *skb) -{ - struct zerocopy_adaptor *zdptr = rb->zdptr; - unsigned int out = zdptr->pre_rp; - struct link_device *ld = rb->ld; - struct mem_link_device *mld = ld_to_mem_link_device(ld); - - /* Record the IO device, the link device, etc. into &skb->cb */ - if (sipc_ps_ch(rb->ch)) { - unsigned int ch = (rb->buff_len_array[out] >> 16) & 0xffff; - - skbpriv(skb)->iod = link_get_iod_with_channel(rb->ld, ch); - skbpriv(skb)->ld = rb->ld; - skbpriv(skb)->sipc_ch = ch; - skbpriv(skb)->napi = &mld->mld_napi; - } else { - skbpriv(skb)->iod = rb->iod; - skbpriv(skb)->ld = rb->ld; - skbpriv(skb)->sipc_ch = rb->ch; - skbpriv(skb)->napi = NULL; - } -} - -struct sk_buff *zerocopy_alloc_skb(u8 *buf, unsigned int data_len) -{ - struct sk_buff *skb; - - skb = build_skb(buf, SKB_DATA_ALIGN(data_len + NET_HEADROOM) - + SKB_DATA_ALIGN(sizeof(struct skb_shared_info))); - - if (unlikely(!skb)) { - mif_err("skb is null\n"); - return NULL; - } - skb->head_frag = 0; - - skb_reserve(skb, NET_HEADROOM); - skb_put(skb, data_len); - - return skb; -} - -struct sk_buff *zerocopy_alloc_skb_with_memcpy(u8 *buf, unsigned int data_len) -{ - struct sk_buff *skb; - u8 *src; - - skb = dev_alloc_skb(data_len); - if (unlikely(!skb)) - return NULL; - - src = buf + NET_HEADROOM; - skb_put(skb, data_len); - skb_copy_to_linear_data(skb, src, data_len); - - free_mif_buff(g_mif_buff_mng, buf); - - return skb; -} - -struct sk_buff *sbd_pio_rx_zerocopy_adaptor(struct sbd_ring_buffer *rb, int use_memcpy) -{ - struct sk_buff *skb; - struct zerocopy_adaptor *zdptr = rb->zdptr; - unsigned int qlen = zdptr->len; - unsigned int out = zdptr->pre_rp; - unsigned int data_len = rb->buff_len_array[out] & 0xFFFF; - u64 offset; - u8 *buff; - - offset = recv_offset_from_zerocopy_adaptor(zdptr); - buff = data_offset_to_buffer(offset, rb); - - if (unlikely(!buff)) { - mif_err("ERR! buff doesn't exist\n"); - return NULL; - } - - if (use_memcpy) - skb = zerocopy_alloc_skb_with_memcpy(buff, data_len); - else - skb = zerocopy_alloc_skb(buff, data_len); - - if (unlikely(!skb)) { - mif_err("ERR! Socket buffer doesn't exist\n"); - return NULL; - } - - set_lnk_hdr(rb, skb); - - set_skb_priv_zerocopy_adaptor(rb, skb); - - check_more(rb, skb); - - zdptr->pre_rp = circ_new_ptr(qlen, out, 1); - - return skb; -} - -static u64 buffer_to_data_offset(u8 *buf, struct sbd_ring_buffer *rb) -{ - struct sbd_link_device *sl = rb->sl; - struct device *dev = sl->ld->dev; - struct zerocopy_adaptor *zdptr = rb->zdptr; - dma_addr_t dma_addr; - u8 *v_zmb = cp_shmem_get_region(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - unsigned int zmb_size = cp_shmem_get_size(sl->ld->mdm_data->cp_num, SHMEM_ZMC); - u8 *data; - u64 offset; - - data = buf + NET_HEADROOM; - - if (buf >= v_zmb && buf < (v_zmb + zmb_size)) { - offset = data - v_zmb + sl->zmb_offset; - } else { - mif_err("unexpected buff address : %lx\n", (unsigned long)virt_to_phys(buf)); - return -EINVAL; - } - - dma_addr = dma_map_single(dev, buf, MIF_BUFF_DEFAULT_CELL_SIZE, DMA_FROM_DEVICE); - kfifo_in_spinlocked(&zdptr->fifo, &dma_addr, sizeof(dma_addr), &zdptr->lock_kfifo); - - return offset; -} - -int allocate_data_in_advance(struct zerocopy_adaptor *zdptr) -{ - struct sbd_ring_buffer *rb = zdptr->rb; - struct modem_ctl *mc = rb->sl->ld->mc; - struct mif_buff_mng *mif_buff_mng = rb->ld->mif_buff_mng; - unsigned int qlen = rb->len; - unsigned long flags; - u8 *buffer; - u64 offset; - u8 *dst; - int alloc_cnt = 0; - - spin_lock_irqsave(&zdptr->lock, flags); - if (cp_offline(mc)) { - spin_unlock_irqrestore(&zdptr->lock, flags); - return 0; - } - - while (zerocopy_adaptor_space(zdptr) > 0) { - buffer = alloc_mif_buff(mif_buff_mng); - if (!buffer) { - spin_unlock_irqrestore(&zdptr->lock, flags); - return -ENOMEM; - } - - offset = buffer_to_data_offset(buffer, rb); - - dst = rb->buff[*zdptr->wp] + rb->payload_offset; - - memcpy(dst, &offset, sizeof(offset)); - - barrier(); - - *zdptr->wp = circ_new_ptr(qlen, *zdptr->wp, 1); - - alloc_cnt++; - - } - barrier(); - spin_unlock_irqrestore(&zdptr->lock, flags); - - /* Commit the item before incrementing the head */ - smp_mb(); - return alloc_cnt; -} diff --git a/drivers/soc/google/cpif/link_tx_pktproc.c b/drivers/soc/google/cpif/link_tx_pktproc.c index 22f913f6b32f..bfb04c3ee63a 100644 --- a/drivers/soc/google/cpif/link_tx_pktproc.c +++ b/drivers/soc/google/cpif/link_tx_pktproc.c @@ -5,11 +5,13 @@ */ #include -#include +#include #include "modem_prj.h" #include "modem_utils.h" #include "link_device_memory.h" +#if IS_ENABLED(CONFIG_EXYNOS_DIT) #include "dit.h" +#endif static int pktproc_send_pkt_to_cp(struct pktproc_queue_ul *q, struct sk_buff *skb) { @@ -17,35 +19,42 @@ static int pktproc_send_pkt_to_cp(struct pktproc_queue_ul *q, struct sk_buff *sk struct pktproc_desc_ul *desc; void *target_addr; int len = skb->len; - int ret; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) bool use_dit; +#endif u32 space; q->stat.total_cnt++; if (!pktproc_check_ul_q_active(q->ppa_ul, q->q_idx)) { - mif_err_limited("Queue %d not activated\n", q->q_idx); + mif_err_limited("Queue[%d] not activated\n", q->q_idx); q->stat.inactive_cnt++; return -EACCES; } + /* avoid race with the done_ptr disordering */ + smp_rmb(); + space = circ_get_space(q->num_desc, q->done_ptr, q_info->rear_ptr); if (space < 1) { - mif_err_limited("NOSPC num_desc:%d fore:%d done:%d rear:%d\n", - q->num_desc, q_info->fore_ptr, q->done_ptr, q_info->rear_ptr); + mif_err_limited("NOSPC Queue[%d] num_desc:%d fore:%d done:%d rear:%d\n", + q->q_idx, q->num_desc, q_info->fore_ptr, q->done_ptr, + q_info->rear_ptr); q->stat.buff_full_cnt++; return -ENOSPC; } +#if IS_ENABLED(CONFIG_EXYNOS_DIT) use_dit = dit_check_dir_use_queue(DIT_DIR_TX, q->q_idx); - - if (!use_dit) { + if (!use_dit) +#endif + { target_addr = (void *)(q->q_buff_vbase + - (q->done_ptr * q->ppa_ul->max_packet_size)); + (q->done_ptr * q->max_packet_size)); skb_copy_from_linear_data(skb, target_addr, skb->len); } desc = &q->desc_ul[q->done_ptr]; - desc->sktbuf_point = q->buff_addr_cp + (q->done_ptr * q->ppa_ul->max_packet_size); + desc->sktbuf_point = q->buff_addr_cp + (q->done_ptr * q->max_packet_size); desc->data_size = skb->len; if (q->ppa_ul->padding_required) @@ -58,15 +67,19 @@ static int pktproc_send_pkt_to_cp(struct pktproc_queue_ul *q, struct sk_buff *sk barrier(); +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (use_dit) { + int ret; /* skb may not be valid after dit_enqueue is done */ ret = dit_enqueue_src_desc_ring_skb(DIT_DIR_TX, skb); if (ret < 0) { - mif_err_limited("Enqueue failed for %d, ret: %d\n", q->done_ptr, ret); + mif_err_limited("Enqueue failed Queue[%d] done:%d ret:%d\n", + q->q_idx, q->done_ptr, ret); q->stat.buff_full_cnt++; return ret; } } +#endif q->done_ptr = circ_new_ptr(q->num_desc, q->done_ptr, 1); @@ -92,11 +105,6 @@ static int pktproc_set_end(struct pktproc_queue_ul *q, unsigned int desc_index, if (desc_index == q->q_info->fore_ptr) return -ERANGE; - if (!pktproc_check_ul_q_active(q->ppa_ul, q->q_idx)) { - q->stat.inactive_cnt++; - return -EACCES; - } - prev_index = circ_prev_ptr(q->num_desc, desc_index, prev_offset); prev_desc = &q->desc_ul[prev_index]; @@ -166,7 +174,7 @@ static ssize_t region_show(struct device *dev, struct device_attribute *attr, ssize_t count = 0; int i; - count += scnprintf(&buf[count], PAGE_SIZE - count, "CP base:0x%08lx\n", ppa_ul->cp_base); + count += scnprintf(&buf[count], PAGE_SIZE - count, "CP base:0x%08llx\n", ppa_ul->cp_base); count += scnprintf(&buf[count], PAGE_SIZE - count, "Num of queue:%d\n", ppa_ul->num_queue); count += scnprintf(&buf[count], PAGE_SIZE - count, "HW cache coherency:%d\n", ppa_ul->use_hw_iocc); @@ -257,8 +265,11 @@ static const struct attribute_group pktproc_ul_group = { int pktproc_init_ul(struct pktproc_adaptor_ul *ppa_ul) { int i; + struct mem_link_device *mld; struct pktproc_info_ul *info; + mld = container_of(ppa_ul, struct mem_link_device, pktproc_ul); + if (!ppa_ul) { mif_err("ppa_ul is null\n"); return -EPERM; @@ -288,18 +299,26 @@ int pktproc_init_ul(struct pktproc_adaptor_ul *ppa_ul) q->done_ptr = 0; *q->rear_ptr = 0; /* sets q_info->rear_ptr to 0 */ - q->q_info->cp_desc_pbase = q->cp_desc_pbase; + if (mld->pktproc_use_36bit_addr) { + q->q_info->cp_desc_pbase = q->cp_desc_pbase >> 4; + q->q_info->cp_buff_pbase = q->cp_buff_pbase >> 4; + } else { + q->q_info->cp_desc_pbase = q->cp_desc_pbase; + q->q_info->cp_buff_pbase = q->cp_buff_pbase; + } + q->q_info->num_desc = q->num_desc; - q->q_info->cp_buff_pbase = q->cp_buff_pbase; +#if IS_ENABLED(CONFIG_EXYNOS_DIT) if (dit_check_dir_use_queue(DIT_DIR_TX, q->q_idx)) dit_reset_dst_wp_rp(DIT_DIR_TX); +#endif memset(&q->stat, 0, sizeof(struct pktproc_statistics_ul)); atomic_set(&q->active, 1); atomic_set(&q->busy, 0); - mif_info("num_desc:0x%08x cp_desc_pbase:0x%08x cp_buff_pbase:0x%08x\n", + mif_info("num_desc:0x%08x cp_desc_pbase:0x%08llx cp_buff_pbase:0x%08llx\n", q->num_desc, q->cp_desc_pbase, q->cp_buff_pbase); mif_info("fore:%d rear:%d\n", q->q_info->fore_ptr, q->q_info->rear_ptr); @@ -314,19 +333,27 @@ int pktproc_init_ul(struct pktproc_adaptor_ul *ppa_ul) static int pktproc_get_info_ul(struct pktproc_adaptor_ul *ppa_ul, struct device_node *np) { - mif_dt_read_u32(np, "pktproc_ul_cp_base", ppa_ul->cp_base); + mif_dt_read_u64(np, "pktproc_cp_base", ppa_ul->cp_base); mif_dt_read_u32(np, "pktproc_ul_num_queue", ppa_ul->num_queue); - mif_dt_read_u32(np, "pktproc_ul_max_packet_size", - ppa_ul->max_packet_size); + if (ppa_ul->num_queue == 1 && !IS_ENABLED(CONFIG_CP_PKTPROC_UL_SINGLE_QUEUE)) { + mif_err("Need to enable UL single queue config for single UL queue\n"); + panic("Need to enable UL single queue config for single UL queue.\n"); + return -EINVAL; + } + mif_dt_read_u32(np, "pktproc_ul_max_packet_size", ppa_ul->default_max_packet_size); + mif_dt_read_u32_noerr(np, "pktproc_ul_hiprio_ack_only", ppa_ul->hiprio_ack_only); mif_dt_read_u32(np, "pktproc_ul_use_hw_iocc", ppa_ul->use_hw_iocc); - mif_dt_read_u32(np, "pktproc_ul_info_desc_rgn_cached", ppa_ul->info_desc_rgn_cached); + mif_dt_read_u32(np, "pktproc_ul_info_rgn_cached", ppa_ul->info_rgn_cached); + mif_dt_read_u32(np, "pktproc_ul_desc_rgn_cached", ppa_ul->desc_rgn_cached); mif_dt_read_u32(np, "pktproc_ul_buff_rgn_cached", ppa_ul->buff_rgn_cached); mif_dt_read_u32(np, "pktproc_ul_padding_required", ppa_ul->padding_required); - mif_info("cp_base:0x%08lx num_queue:%d max_packet_size:%d iocc:%d\n", - ppa_ul->cp_base, ppa_ul->num_queue, ppa_ul->max_packet_size, ppa_ul->use_hw_iocc); - mif_info("info/desc rgn cache: %d buff rgn cache: %d padding_required:%d\n", - ppa_ul->info_desc_rgn_cached, ppa_ul->buff_rgn_cached, ppa_ul->padding_required); + mif_info("cp_base:0x%08llx num_queue:%d max_packet_size:%d hiprio_ack_only:%d iocc:%d\n", + ppa_ul->cp_base, ppa_ul->num_queue, ppa_ul->default_max_packet_size, + ppa_ul->hiprio_ack_only, ppa_ul->use_hw_iocc); + mif_info("cached: %d/%d/%d padding_required:%d\n", ppa_ul->info_rgn_cached, + ppa_ul->desc_rgn_cached, ppa_ul->buff_rgn_cached, + ppa_ul->padding_required); mif_dt_read_u32(np, "pktproc_ul_info_rgn_offset", ppa_ul->info_rgn_offset); @@ -338,9 +365,11 @@ static int pktproc_get_info_ul(struct pktproc_adaptor_ul *ppa_ul, ppa_ul->desc_rgn_size); mif_dt_read_u32(np, "pktproc_ul_buff_rgn_offset", ppa_ul->buff_rgn_offset); - mif_info("info_rgn 0x%08lx 0x%08lx desc_rgn 0x%08lx 0x%08lx buff_rgn 0x%08lx\n", + mif_dt_read_u32(np, "pktproc_ul_buff_rgn_size", + ppa_ul->buff_rgn_size); + mif_info("info_rgn 0x%08lx 0x%08lx desc_rgn 0x%08lx 0x%08lx buff_rgn 0x%08lx 0x%08lx\n", ppa_ul->info_rgn_offset, ppa_ul->info_rgn_size, ppa_ul->desc_rgn_offset, - ppa_ul->desc_rgn_size, ppa_ul->buff_rgn_offset); + ppa_ul->desc_rgn_size, ppa_ul->buff_rgn_offset, ppa_ul->buff_rgn_size); return 0; } @@ -352,8 +381,11 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, struct pktproc_adaptor_ul *ppa_ul = &mld->pktproc_ul; struct pktproc_info_ul *ul_info; u32 buff_size, buff_size_by_q; - int i; - int ret; + u32 last_q_desc_offset; + int i, ret; +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + u64 temp; +#endif if (!np) { mif_err("of_node is null\n"); @@ -364,7 +396,7 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, return -EINVAL; } - mif_dt_read_u32_noerr(np, "pktproc_support_ul", ppa_ul->support); + mif_dt_read_u32_noerr(np, "pktproc_ul_support", ppa_ul->support); if (!ppa_ul->support) { mif_info("pktproc_support_ul is 0. Just return\n"); return 0; @@ -377,31 +409,103 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, return ret; } +#if !IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOCC) + if (!ppa_ul->use_hw_iocc && ppa_ul->info_rgn_cached) { + mif_err("cannot support sw iocc based caching on info region\n"); + return -EINVAL; + } + + if (!ppa_ul->use_hw_iocc && ppa_ul->desc_rgn_cached) { + mif_err("cannot support sw iocc based caching on desc region\n"); + return -EINVAL; + } + + if (!ppa_ul->use_hw_iocc && ppa_ul->buff_rgn_cached) { + mif_err("cannot support sw iocc based caching on buff region\n"); + return -EINVAL; + } +#endif + /* Get base addr */ mif_info("memaddr:0x%lx memsize:0x%08x\n", memaddr, memsize); - if (ppa_ul->info_desc_rgn_cached) - ppa_ul->info_vbase = phys_to_virt(memaddr); - else - ppa_ul->info_vbase = cp_shmem_get_nc_region(memaddr, - ppa_ul->info_rgn_size + ppa_ul->desc_rgn_size); - if (!ppa_ul->info_vbase) { - mif_err("ppa->info_vbase error\n"); - return -ENOMEM; + + if (ppa_ul->info_rgn_cached) { + ppa_ul->info_vbase = phys_to_virt(memaddr + ppa_ul->info_rgn_offset); + } else { + ppa_ul->info_vbase = cp_shmem_get_nc_region(memaddr + + ppa_ul->info_rgn_offset, ppa_ul->info_rgn_size); + if (!ppa_ul->info_vbase) { + mif_err("ppa->info_vbase error\n"); + ret = -ENOMEM; + goto create_error; + } } - ppa_ul->desc_vbase = ppa_ul->info_vbase + ppa_ul->info_rgn_size; - memset(ppa_ul->info_vbase, 0, - ppa_ul->info_rgn_size + ppa_ul->desc_rgn_size); + +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + ppa_ul->desc_map = cpif_vmap_create(ppa_ul->cp_base + ppa_ul->desc_rgn_offset, + ppa_ul->desc_rgn_size, ppa_ul->desc_rgn_size); + if (unlikely(!ppa_ul->desc_map)) { + mif_err("failed to create desc map for pktproc ul\n"); + ret = -ENOMEM; + goto create_error; + } + + ppa_ul->buff_map = cpif_vmap_create(ppa_ul->cp_base + ppa_ul->buff_rgn_offset, + ppa_ul->buff_rgn_size, ppa_ul->buff_rgn_size); + if (unlikely(!ppa_ul->buff_map)) { + mif_err("failed to create buff map for pktproc ul\n"); + cpif_vmap_free(ppa_ul->desc_map); + ret = -ENOMEM; + goto create_error; + } + + temp = cpif_vmap_map_area(ppa_ul->desc_map, 0, 0, memaddr + ppa_ul->desc_rgn_offset); + if (temp != ppa_ul->cp_base + ppa_ul->desc_rgn_offset) { + cpif_vmap_free(ppa_ul->desc_map); + cpif_vmap_free(ppa_ul->buff_map); + ret = -EINVAL; + goto create_error; + } + + temp = cpif_vmap_map_area(ppa_ul->buff_map, 0, 0, memaddr + ppa_ul->buff_rgn_offset); + if (temp != ppa_ul->cp_base + ppa_ul->buff_rgn_offset) { + cpif_vmap_free(ppa_ul->desc_map); + cpif_vmap_free(ppa_ul->buff_map); + ret = -EINVAL; + goto create_error; + } +#endif + if (ppa_ul->desc_rgn_cached) { + ppa_ul->desc_vbase = phys_to_virt(memaddr + ppa_ul->desc_rgn_offset); + } else { + ppa_ul->desc_vbase = cp_shmem_get_nc_region(memaddr + + ppa_ul->desc_rgn_offset, ppa_ul->desc_rgn_size); + if (!ppa_ul->desc_vbase) { + mif_err("ppa->desc_vbase error\n"); + ret = -ENOMEM; + goto create_error; + } + } + + memset(ppa_ul->info_vbase, 0, ppa_ul->info_rgn_size); + memset(ppa_ul->desc_vbase, 0, ppa_ul->desc_rgn_size); + mif_info("info + desc size:0x%08lx\n", ppa_ul->info_rgn_size + ppa_ul->desc_rgn_size); - buff_size = memsize - (ppa_ul->info_rgn_size + ppa_ul->desc_rgn_size); + + buff_size = ppa_ul->buff_rgn_size; buff_size_by_q = buff_size / ppa_ul->num_queue; - if (ppa_ul->buff_rgn_cached) - ppa_ul->buff_vbase = - phys_to_virt(memaddr + ppa_ul->buff_rgn_offset); - else - ppa_ul->buff_vbase = - cp_shmem_get_nc_region(memaddr + - ppa_ul->buff_rgn_offset, buff_size); + if (ppa_ul->buff_rgn_cached) { + ppa_ul->buff_vbase = phys_to_virt(memaddr + ppa_ul->buff_rgn_offset); + } else { + ppa_ul->buff_vbase = cp_shmem_get_nc_region(memaddr + + ppa_ul->buff_rgn_offset, buff_size); + if (!ppa_ul->buff_vbase) { + mif_err("ppa->buff_vbase error\n"); + ret = -ENOMEM; + goto create_error; + } + } mif_info("Total buffer size:0x%08x Queue:%d Size by queue:0x%08x\n", buff_size, ppa_ul->num_queue, @@ -411,6 +515,7 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, ul_info->num_queues = ppa_ul->num_queue; /* Create queue */ + last_q_desc_offset = 0; for (i = 0; i < ppa_ul->num_queue; i++) { struct pktproc_queue_ul *q; @@ -434,25 +539,40 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, q->q_buff_vbase = ppa_ul->buff_vbase + (i * buff_size_by_q); q->cp_buff_pbase = ppa_ul->cp_base + ppa_ul->buff_rgn_offset + (i * buff_size_by_q); - q->q_info->cp_buff_pbase = q->cp_buff_pbase; + + if (mld->pktproc_use_36bit_addr) + q->q_info->cp_buff_pbase = q->cp_buff_pbase >> 4; + else + q->q_info->cp_buff_pbase = q->cp_buff_pbase; + + if (ppa_ul->num_queue > 1 && i == PKTPROC_UL_HIPRIO && ppa_ul->hiprio_ack_only) { + struct link_device *ld = &mld->link_dev; + + ld->hiprio_ack_only = true; + q->max_packet_size = HIPRIO_MAX_PACKET_SIZE; + } else { + q->max_packet_size = ppa_ul->default_max_packet_size; + } + q->q_buff_size = buff_size_by_q; - q->num_desc = buff_size_by_q / ppa_ul->max_packet_size; + q->num_desc = buff_size_by_q / q->max_packet_size; q->q_info->num_desc = q->num_desc; - q->desc_ul = ppa_ul->desc_vbase + - (i * sizeof(struct pktproc_desc_ul) * q->num_desc); + q->desc_ul = ppa_ul->desc_vbase + last_q_desc_offset; q->cp_desc_pbase = ppa_ul->cp_base + - ppa_ul->desc_rgn_offset + - (i * sizeof(struct pktproc_desc_ul) * q->num_desc); - q->q_info->cp_desc_pbase = q->cp_desc_pbase; + ppa_ul->desc_rgn_offset + last_q_desc_offset; + if (mld->pktproc_use_36bit_addr) + q->q_info->cp_desc_pbase = q->cp_desc_pbase >> 4; + else + q->q_info->cp_desc_pbase = q->cp_desc_pbase; q->desc_size = sizeof(struct pktproc_desc_ul) * q->num_desc; q->buff_addr_cp = ppa_ul->cp_base + ppa_ul->buff_rgn_offset + (i * buff_size_by_q); q->send_packet = pktproc_send_pkt_to_cp; q->update_fore_ptr = pktproc_ul_update_fore_ptr; - if ((q->cp_desc_pbase + q->desc_size) > q->cp_buff_pbase) { - mif_err("Descriptor overflow:0x%08x 0x%08x 0x%08x\n", - q->cp_desc_pbase, q->desc_size, q->cp_buff_pbase); + if ((last_q_desc_offset + q->desc_size) > ppa_ul->desc_rgn_size) { + mif_err("Descriptor overflow. 0x%08x + 0x%08x > 0x%08lx\n", + last_q_desc_offset, q->desc_size, ppa_ul->desc_rgn_size); goto create_error; } @@ -469,27 +589,34 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, q->rear_ptr = &q->q_info->rear_ptr; q->done_ptr = *q->fore_ptr; - mif_info("num_desc:%d desc_offset:0x%08x desc_size:0x%08x\n", - q->num_desc, q->cp_desc_pbase, q->desc_size); - mif_info("buff_offset:0x%08x buff_size:0x%08x\n", + last_q_desc_offset += q->desc_size; + + mif_info("num_desc:%d desc_offset:0x%08llx desc_size:0x%08x max_packet_size: %d\n", + q->num_desc, q->cp_desc_pbase, q->desc_size, q->max_packet_size); + mif_info("buff_offset:0x%08llx buff_size:0x%08x\n", q->cp_buff_pbase, q->q_buff_size); - } #if IS_ENABLED(CONFIG_EXYNOS_DIT) - ret = dit_set_buf_size(DIT_DIR_TX, ppa_ul->max_packet_size); - if (ret) - mif_err("dit_set_buf_size() error:%d\n", ret); - - ret = dit_set_pktproc_base(DIT_DIR_TX, - memaddr + ppa_ul->buff_rgn_offset + (DIT_PKTPROC_TX_QUEUE_NUM * buff_size_by_q)); - if (ret) - mif_err("dit_set_pktproc_base() error:%d\n", ret); - - ret = dit_set_desc_ring_len(DIT_DIR_TX, - ppa_ul->q[DIT_PKTPROC_TX_QUEUE_NUM]->num_desc); - if (ret) - mif_err("dit_set_desc_ring_len() error:%d\n", ret); + if (ppa_ul->num_queue == 1 || q->q_idx == PKTPROC_UL_NORM) { + ret = dit_set_pktproc_queue_num(DIT_DIR_TX, q->q_idx); + if (ret) + mif_err("dit_set_pktproc_queue_num() error:%d\n", ret); + + ret = dit_set_buf_size(DIT_DIR_TX, q->max_packet_size); + if (ret) + mif_err("dit_set_buf_size() error:%d\n", ret); + + ret = dit_set_pktproc_base(DIT_DIR_TX, memaddr + ppa_ul->buff_rgn_offset + + (q->q_idx * buff_size_by_q)); + if (ret) + mif_err("dit_set_pktproc_base() error:%d\n", ret); + + ret = dit_set_desc_ring_len(DIT_DIR_TX, q->num_desc); + if (ret) + mif_err("dit_set_desc_ring_len() error:%d\n", ret); + } #endif + } /* Debug */ ret = sysfs_create_group(&pdev->dev.kobj, &pktproc_ul_group); @@ -504,8 +631,10 @@ int pktproc_create_ul(struct platform_device *pdev, struct mem_link_device *mld, for (i = 0; i < ppa_ul->num_queue; i++) kfree(ppa_ul->q[i]); - if (!ppa_ul->info_desc_rgn_cached && ppa_ul->info_vbase) + if (!ppa_ul->info_rgn_cached && ppa_ul->info_vbase) vunmap(ppa_ul->info_vbase); + if (!ppa_ul->desc_rgn_cached && ppa_ul->desc_vbase) + vunmap(ppa_ul->desc_vbase); if (!ppa_ul->buff_rgn_cached && ppa_ul->buff_vbase) vunmap(ppa_ul->buff_vbase); diff --git a/drivers/soc/google/cpif/link_tx_pktproc.h b/drivers/soc/google/cpif/link_tx_pktproc.h index dcbd02f07e97..363dcaf626d3 100644 --- a/drivers/soc/google/cpif/link_tx_pktproc.h +++ b/drivers/soc/google/cpif/link_tx_pktproc.h @@ -9,11 +9,17 @@ #include #include "link_device_memory.h" +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) +#include "cpif_vmapper.h" +#endif -/* Numbers */ -#define PKTPROC_HIPRIO_UL 0 -#define PKTPROC_NORM_UL 1 -#define PKTPROC_MAX_QUEUE_UL 2 +/* Queue Numbers */ +enum pktproc_ul_queue_t { + PKTPROC_UL_HIPRIO = 0, + PKTPROC_UL_QUEUE_0 = PKTPROC_UL_HIPRIO, + PKTPROC_UL_NORM = 1, + PKTPROC_UL_QUEUE_MAX +}; /* * Descriptor structure mode @@ -27,6 +33,8 @@ enum pktproc_end_bit_owner { /* Padding required by CP */ #define CP_PADDING 76 +#define MAX_UL_PACKET_SIZE 512 +#define HIPRIO_MAX_PACKET_SIZE roundup_pow_of_two(MAX_UL_PACKET_SIZE + CP_PADDING) /* Q_info */ struct pktproc_q_info_ul { @@ -41,7 +49,7 @@ struct pktproc_q_info_ul { struct pktproc_info_ul { u32 num_queues:4, mode:4, max_packet_size:16, end_bit_owner:1, reserve1:7; u32 cp_quota:16, reserve2:16; - struct pktproc_q_info_ul q_info[PKTPROC_MAX_QUEUE_UL]; + struct pktproc_q_info_ul q_info[PKTPROC_UL_QUEUE_MAX]; } __packed; struct pktproc_desc_ul { @@ -82,9 +90,9 @@ struct pktproc_queue_ul { u32 *rear_ptr; /* indicates the last desc read by CP */ /* Store */ - u32 cp_desc_pbase; + u64 cp_desc_pbase; u32 num_desc; - u32 cp_buff_pbase; + u64 cp_buff_pbase; struct pktproc_info_ul *ul_info; struct pktproc_q_info_ul *q_info; /* Pointer to q_info of info_v */ @@ -92,6 +100,7 @@ struct pktproc_queue_ul { u32 desc_size; u64 buff_addr_cp; /* base data address value for cp */ + u32 max_packet_size; /* Pointer to data buffer */ u8 __iomem *q_buff_vbase; @@ -109,26 +118,32 @@ struct pktproc_queue_ul { struct pktproc_adaptor_ul { bool support; /* Is support PktProc feature? */ - unsigned long cp_base; /* CP base address for pktproc */ + unsigned long long cp_base; /* CP base address for pktproc */ unsigned long info_rgn_offset; /* Offset of info region */ unsigned long info_rgn_size; /* Size of info region */ unsigned long desc_rgn_offset; /* Offset of descriptor region */ unsigned long desc_rgn_size; /* Size of descriptor region */ unsigned long buff_rgn_offset; /* Offset of data buffer region */ + unsigned long buff_rgn_size; /* Size of data buffer region */ u32 num_queue; /* Number of queue */ - u32 max_packet_size; /* packet size pktproc UL can hold */ + u32 default_max_packet_size; /* packet size pktproc UL can hold */ + u32 hiprio_ack_only; enum pktproc_end_bit_owner end_bit_owner; /* owner to set end bit. AP:0, CP:1 */ u32 cp_quota; /* max number of buffers cp allows us to transfer */ bool use_hw_iocc; /* H/W IO cache coherency */ - bool info_desc_rgn_cached; + bool info_rgn_cached; + bool desc_rgn_cached; bool buff_rgn_cached; bool padding_required; /* requires extra length. (s5123 EVT1 only) */ - +#if IS_ENABLED(CONFIG_EXYNOS_CPIF_IOMMU) + struct cpif_va_mapper *desc_map; + struct cpif_va_mapper *buff_map; +#endif void __iomem *info_vbase; /* I/O region for information */ void __iomem *desc_vbase; /* I/O region for descriptor */ void __iomem *buff_vbase; /* I/O region for data buffer */ - struct pktproc_queue_ul *q[PKTPROC_MAX_QUEUE_UL];/* Logical queue */ + struct pktproc_queue_ul *q[PKTPROC_UL_QUEUE_MAX];/* Logical queue */ }; #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) diff --git a/drivers/soc/google/cpif/mcu_ipc.c b/drivers/soc/google/cpif/mcu_ipc.c index 258f3fbeba5c..06f9bb07acf8 100644 --- a/drivers/soc/google/cpif/mcu_ipc.c +++ b/drivers/soc/google/cpif/mcu_ipc.c @@ -14,12 +14,10 @@ #include #include -#include +#include #include "mcu_ipc_priv.h" #include "modem_utils.h" -#define USE_FIXED_AFFINITY - /* IRQ handler */ static irqreturn_t cp_mbox_irq_handler(int irq, void *data) { @@ -433,23 +431,7 @@ int cp_mbox_set_affinity(u32 idx, int affinity) mif_debug("idx:%d affinity:0x%x\n", idx, affinity); irq_data->affinity = affinity; -#if IS_ENABLED(CONFIG_ARGOS) -#ifdef USE_FIXED_AFFINITY return irq_set_affinity_hint(irq_data->irq, cpumask_of(affinity)); -#else - if (!zalloc_cpumask_var(&irq_data->dmask, GFP_KERNEL)) - return -ENOMEM; - if (!zalloc_cpumask_var(&irq_data->imask, GFP_KERNEL)) - return -ENOMEM; - - cpumask_or(irq_data->imask, irq_data->imask, cpumask_of(mask)); - cpumask_copy(irq_data->dmask, get_default_cpu_mask()); - - return argos_irq_affinity_setup_label(irq, "IPC", irq_data->imask, irq_data->dmask); -#endif -#else /* CONFIG_ARGOS */ - return irq_set_affinity_hint(irq_data->irq, cpumask_of(affinity)); -#endif /* CONFIG_ARGOS */ } EXPORT_SYMBOL(cp_mbox_set_affinity); @@ -457,7 +439,6 @@ EXPORT_SYMBOL(cp_mbox_set_affinity); static int cp_mbox_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res = NULL; struct device_node *irq_np = NULL; struct device_node *irq_child_np = NULL; u32 count = 0; @@ -470,7 +451,8 @@ static int cp_mbox_probe(struct platform_device *pdev) if (!dev->of_node) { mif_err("dev->of_node is null\n"); - return -ENODEV; + err = -ENODEV; + goto fail; } /* DMA mask */ @@ -480,11 +462,11 @@ static int cp_mbox_probe(struct platform_device *pdev) pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); /* Region */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - mbox_data.ioaddr = devm_ioremap_resource(&pdev->dev, res); + mbox_data.ioaddr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(mbox_data.ioaddr)) { mif_err("failed to request memory resource\n"); - return PTR_ERR(mbox_data.ioaddr); + err = PTR_ERR(mbox_data.ioaddr); + goto fail; } mbox_data.dev = &pdev->dev; @@ -504,14 +486,16 @@ static int cp_mbox_probe(struct platform_device *pdev) irq_np = of_get_child_by_name(dev->of_node, "cp_mailbox_irqs"); if (!irq_np) { mif_err("of_get_child_by_name() error:irq_np\n"); - return -EINVAL; + err = -EINVAL; + goto fail; } for_each_child_of_node(irq_np, irq_child_np) { struct cp_mbox_irq_data *irq_data = NULL; if (count >= MAX_CP_MBOX_IRQ_IDX) { mif_err("count is full:%d\n", count); - return -ENOMEM; + err = -ENOMEM; + goto fail; } /* IRQ index */ @@ -519,7 +503,8 @@ static int cp_mbox_probe(struct platform_device *pdev) irq_data = &mbox_data.irq_data[idx]; if (!irq_data) { mif_err("irq_data %d is null\n", idx); - return -EINVAL; + err = -EINVAL; + goto fail; } irq_data->idx = idx; @@ -558,12 +543,12 @@ static int cp_mbox_probe(struct platform_device *pdev) IRQF_ONESHOT, irq_data->name, irq_data); if (err) { mif_err("devm_request_irq() error:%d\n", err); - return err; + goto fail; } err = enable_irq_wake(irq); if (err) { mif_err("enable_irq_wake() error:%d\n", err); - return err; + goto fail; } irq_data->irq = irq; @@ -588,9 +573,13 @@ static int cp_mbox_probe(struct platform_device *pdev) dev_set_drvdata(dev, &mbox_data); - mif_err("---\n"); + mif_info("---\n"); return 0; + +fail: + panic("CP mbox probe failed\n"); + return err; } static int cp_mbox_remove(struct platform_device *pdev) diff --git a/drivers/soc/google/cpif/mcu_ipc_priv.h b/drivers/soc/google/cpif/mcu_ipc_priv.h index ff190109e4bd..b0f50c709715 100644 --- a/drivers/soc/google/cpif/mcu_ipc_priv.h +++ b/drivers/soc/google/cpif/mcu_ipc_priv.h @@ -51,14 +51,6 @@ struct cp_mbox_irq_data { unsigned long unmasked_irq; struct cp_mbox_handler hd[MAX_CP_MBOX_HANDLER]; - -#if IS_ENABLED(CONFIG_ARGOS) - /** - * irq affinity cpu mask - */ - cpumask_var_t dmask; /* default cpu mask */ - cpumask_var_t imask; /* irq affinity cpu mask */ -#endif }; struct cp_mbox_drv_data { @@ -90,31 +82,4 @@ static inline u32 mcu_ipc_read(u32 reg) return readl(mbox_data.ioaddr + reg); } -#if IS_ENABLED(CONFIG_ARGOS) -/* kernel team needs to provide argos header file. !!! - * As of now, there's nothing to use. - */ -#if IS_ENABLED(CONFIG_SCHED_HMP) -extern struct cpumask hmp_slow_cpu_mask; -extern struct cpumask hmp_fast_cpu_mask; - -static inline struct cpumask *get_default_cpu_mask(void) -{ - return &hmp_slow_cpu_mask; -} -#else -static inline struct cpumask *get_default_cpu_mask(void) -{ - return cpu_all_mask; -} -#endif - -int argos_irq_affinity_setup_label(unsigned int irq, const char *label, - struct cpumask *affinity_cpu_mask, - struct cpumask *default_cpu_mask); -int argos_task_affinity_setup_label(struct task_struct *p, const char *label, - struct cpumask *affinity_cpu_mask, - struct cpumask *default_cpu_mask); -#endif - #endif /* __MCU_IPC_PRIV_H__ */ diff --git a/drivers/soc/google/cpif/modem_argos_notifier.c b/drivers/soc/google/cpif/modem_argos_notifier.c deleted file mode 100644 index 493499ff0edb..000000000000 --- a/drivers/soc/google/cpif/modem_argos_notifier.c +++ /dev/null @@ -1,294 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2015 Samsung Electronics. - * - */ - -#include -#include - -#include "modem_prj.h" - -#define MIF_MAX_RPS_STR 8 -#define MIF_MAX_NDEV_NUM 8 -#define MIF_ARGOS_IPC_LABEL "IPC" -#define MIF_ARGOS_CLAT_LABEL "CLAT" - -//#define MIF_ARGOS_DEBUG - -const char *ndev_prefix[2] = {"rmnet", "v4-rmnet"}; - -enum ndev_prefix_idx { - IPC = 0, - CLAT -}; - -struct argos_notifier { - struct notifier_block ipc_nb; - struct notifier_block clat_nb; - unsigned int prev_ipc_rps; - unsigned int prev_clat_rps; -}; - -unsigned int lit_rmnet_rps = 0x06; -module_param(lit_rmnet_rps, uint, 0664); -MODULE_PARM_DESC(lit_rmnet_rps, "rps_cpus for rmnetx: LITTLE(only rmnetx up)"); - -unsigned int lit_rmnet_clat_rps = 0x06; -module_param(lit_rmnet_clat_rps, uint, 0664); -MODULE_PARM_DESC(lit_rmnet_clat_rps, "rps_cpus for rmnetx: LITTLE(both up)"); - -unsigned int lit_clat_rps = 0x70; -module_param(lit_clat_rps, uint, 0664); -MODULE_PARM_DESC(lit_clat_rps, "rps_cpus for v4-rmnetx: LITTLE(both up)"); - -unsigned int big_rmnet_rps = 0x70; -module_param(big_rmnet_rps, uint, 0664); -MODULE_PARM_DESC(big_rmnet_rps, "rps_cpus for rmnetx: BIG(only rmnetx up)"); - -unsigned int big_rmnet_clat_rps = 0x70; -module_param(big_rmnet_clat_rps, uint, 0664); -MODULE_PARM_DESC(big_rmnet_clat_rps, "rps_cpus for rmnetx: BIG(both up)"); - -unsigned int big_clat_rps = 0xc0; -module_param(big_clat_rps, uint, 0664); -MODULE_PARM_DESC(big_clat_rps, "rps_cpus for v4-rmnetx: BIG(both up)"); - -unsigned int mif_rps_thresh = 300; -module_param(mif_rps_thresh, uint, 0664); -MODULE_PARM_DESC(mif_rps_thresh, "threshold speed"); - -int mif_gro_flush_thresh[] = {100, 200, -1}; -long mif_gro_flush_time[] = {10000, 50000, 100000}; - -static int mif_store_rps_map(struct netdev_rx_queue *queue, char *buf, size_t len) -{ - struct rps_map *old_map, *map; - cpumask_var_t mask; - int err, cpu, i; - static DEFINE_SPINLOCK(rps_map_lock); - - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { - mif_err("failed to alloc_cpumask\n"); - return -ENOMEM; - } - - err = bitmap_parse(buf, len, cpumask_bits(mask), nr_cpumask_bits); - if (err) { - free_cpumask_var(mask); - mif_err("failed to parse bitmap\n"); - return err; - } - - map = kzalloc(max_t(unsigned long, - RPS_MAP_SIZE(cpumask_weight(mask)), L1_CACHE_BYTES), - GFP_KERNEL); - if (!map) { - free_cpumask_var(mask); - mif_err("failed to alloc kmem\n"); - return -ENOMEM; - } - - i = 0; - for_each_cpu_and(cpu, mask, cpu_online_mask) { - map->cpus[i++] = cpu; - } - - if (i) { - map->len = i; - } else { - kfree(map); - map = NULL; - - free_cpumask_var(mask); - mif_err("failed to map rps_cpu\n"); - return -EINVAL; - } - - spin_lock(&rps_map_lock); - old_map = rcu_dereference_protected(queue->rps_map, - lockdep_is_held(&rps_map_lock)); - rcu_assign_pointer(queue->rps_map, map); - - if (map) - static_branch_inc(&rps_needed); - if (old_map) - static_branch_dec(&rps_needed); - - spin_unlock(&rps_map_lock); - - if (old_map) - kfree_rcu(old_map, rcu); - - free_cpumask_var(mask); -#ifdef MIF_ARGOS_DEBUG - mif_info("map:%d\n", map->len); -#endif - return map->len; -} - -static void mif_update_ndevs_rps(const char *ndev_prefix, unsigned int rps_value) -{ - struct net_device *ndev; - char ndev_name[IFNAMSIZ]; - char value[MIF_MAX_RPS_STR]; - int ret; - int i; - - if (!rps_value) - return; - - snprintf(value, MIF_MAX_RPS_STR, "%x", rps_value); - - for (i = 0; i < MIF_MAX_NDEV_NUM; i++) { - memset(ndev_name, 0, IFNAMSIZ); - snprintf(ndev_name, IFNAMSIZ, "%s%d", ndev_prefix, i); - - ndev = dev_get_by_name(&init_net, ndev_name); - if (!ndev) { -#ifdef MIF_ARGOS_DEBUG - mif_info("Cannot find %s from init_net\n", ndev_name); -#endif - continue; - } - - ret = mif_store_rps_map(ndev->_rx, value, strlen(value)); - dev_put(ndev); - - if (ret < 0) { - mif_err("failed to update ndevs_rps (%s)\n", ndev_name); - continue; - } - -#ifdef MIF_ARGOS_DEBUG - mif_info("%s's rps: 0x%s\n", ndev_name, value); -#endif - } -} - -static void mif_argos_notifier_gro_flushtime(unsigned long speed) -{ - int loop; - - for (loop = 0; mif_gro_flush_thresh[loop] != -1; loop++) - if (speed < mif_gro_flush_thresh[loop]) - break; - gro_flush_time = mif_gro_flush_time[loop]; - - mif_info("Speed: %luMbps, GRO flush time: %ld\n", speed, gro_flush_time); -} - -static int mif_argos_notifier_ipc(struct notifier_block *nb, unsigned long speed, void *data) -{ - struct argos_notifier *nf = container_of(nb, struct argos_notifier, ipc_nb); - unsigned int prev_ipc_rps = nf->prev_ipc_rps, new_ipc_rps = 0; - -#ifdef MIF_ARGOS_DEBUG - mif_info("Speed: %luMbps, IPC|CLAT: 0x%02x|0x%02x\n", - speed, prev_ipc_rps, nf->prev_clat_rps); -#endif - - if (speed >= mif_rps_thresh) - new_ipc_rps = nf->prev_clat_rps ? big_rmnet_clat_rps : big_rmnet_rps; - else - new_ipc_rps = nf->prev_clat_rps ? lit_rmnet_clat_rps : lit_rmnet_rps; - - if (prev_ipc_rps != new_ipc_rps) { - mif_update_ndevs_rps(ndev_prefix[IPC], new_ipc_rps); - nf->prev_ipc_rps = new_ipc_rps; - - mif_info("Speed: %luMbps, IPC|CLAT: 0x%02x|0x%02x -> 0x%02x|0x%02x\n", - speed, prev_ipc_rps, nf->prev_clat_rps, new_ipc_rps, nf->prev_clat_rps); - } - - mif_argos_notifier_gro_flushtime(speed); - - return NOTIFY_OK; -} - -#ifdef SUPPORT_CLATD -static int mif_argos_notifier_clat(struct notifier_block *nb, unsigned long speed, void *data) -{ - struct argos_notifier *nf = container_of(nb, struct argos_notifier, clat_nb); - unsigned int prev_clat_rps = nf->prev_clat_rps, new_clat_rps = 0; - unsigned int prev_ipc_rps = nf->prev_ipc_rps, new_ipc_rps = 0; - bool changed = false; - -#ifdef MIF_ARGOS_DEBUG - mif_info("Speed: %luMbps, IPC|CLAT: 0x%02x|0x%02x\n", - speed, prev_ipc_rps, nf->prev_clat_rps); -#endif - - /* If already set to Big core */ - if (nf->prev_ipc_rps > 0xF) { - new_clat_rps = (speed > 0) ? big_clat_rps : 0; - new_ipc_rps = (new_clat_rps > 0) ? big_rmnet_clat_rps : big_rmnet_rps; - } else { - new_clat_rps = (speed > 0) ? lit_clat_rps : 0; - new_ipc_rps = (new_clat_rps > 0) ? lit_rmnet_clat_rps : lit_rmnet_rps; - } - - if (prev_clat_rps != new_clat_rps) { - mif_update_ndevs_rps(ndev_prefix[CLAT], new_clat_rps); - nf->prev_clat_rps = new_clat_rps; - changed = true; - } - - if (prev_ipc_rps != new_ipc_rps) { - mif_update_ndevs_rps(ndev_prefix[IPC], new_ipc_rps); - nf->prev_ipc_rps = new_ipc_rps; - changed = true; - } - - if (changed) { - mif_info("Speed: %luMbps, IPC|CLAT: 0x%02x|0x%02x -> 0x%02x|0x%02x\n", - speed, prev_ipc_rps, prev_clat_rps, new_ipc_rps, new_clat_rps); - } - - mif_argos_notifier_gro_flushtime(speed); - - return NOTIFY_OK; -} -#endif - -int mif_init_argos_notifier(void) -{ - struct argos_notifier *argos_nf; - int ret; - - mif_info("++\n"); - - argos_nf = kzalloc(sizeof(struct argos_notifier), GFP_ATOMIC); - if (!argos_nf) { - mif_err("failed to allocate argos_nf\n"); - return -ENOMEM; - } - - argos_nf->ipc_nb.notifier_call = mif_argos_notifier_ipc; - ret = sec_argos_register_notifier(&argos_nf->ipc_nb, MIF_ARGOS_IPC_LABEL); - if (ret < 0) { - mif_err("failed to register ipc_nb(%d)\n", ret); - goto exit; - } - -#ifdef SUPPORT_CLATD - argos_nf->clat_nb.notifier_call = mif_argos_notifier_clat; - ret = sec_argos_register_notifier(&argos_nf->clat_nb, MIF_ARGOS_CLAT_LABEL); - if (ret < 0) { - mif_err("failed to register clat_nb(%d)\n", ret); - sec_argos_unregister_notifier(&argos_nf->ipc_nb, MIF_ARGOS_IPC_LABEL); - goto exit; - } -#endif - - /* default rmnetx rps: 0x06 */ - mif_update_ndevs_rps(ndev_prefix[IPC], lit_rmnet_rps); - - mif_info("--\n"); - return 0; - -exit: - kfree(argos_nf); - return ret; -} - diff --git a/drivers/soc/google/cpif/modem_ctrl.c b/drivers/soc/google/cpif/modem_ctrl.c index 98a68807072b..819022fb9a7a 100644 --- a/drivers/soc/google/cpif/modem_ctrl.c +++ b/drivers/soc/google/cpif/modem_ctrl.c @@ -14,7 +14,7 @@ void modem_ctrl_set_kerneltime(struct modem_ctl *mc) struct utc_time t; get_utc_time(&t); - mif_info("time = %d.%d\n", t.sec + (t.min * 60), t.us); + mif_info("time = %d.%06d\n", t.sec + (t.min * 60), t.us); if (mld->ap2cp_kerneltime_sec.type == DRAM_V2) { set_ctrl_msg(&mld->ap2cp_kerneltime_sec, t.sec + (t.min * 60)); @@ -106,7 +106,7 @@ void change_modem_state(struct modem_ctl *mc, enum modem_state state) mc->phone_state = state; spin_unlock_irqrestore(&mc->lock, flags); - mif_err("%s->state changed (%s -> %s)\n", mc->name, + mif_info("%s->state changed (%s -> %s)\n", mc->name, cp_state_str(old_state), cp_state_str(state)); list_for_each_entry(iod, &mc->modem_state_notify_list, list) { diff --git a/drivers/soc/google/cpif/modem_ctrl.h b/drivers/soc/google/cpif/modem_ctrl.h index e0b47a73302b..339ff5ade50d 100644 --- a/drivers/soc/google/cpif/modem_ctrl.h +++ b/drivers/soc/google/cpif/modem_ctrl.h @@ -9,8 +9,51 @@ #define MIF_INIT_TIMEOUT (15 * HZ) +#if IS_ENABLED(CONFIG_SEC_MODEM_S5100) +struct msi_reg_type { + u32 msi_data; + u32 msi_check; + u32 err_report; + u32 reserved; + u32 boot_stage; + u32 img_addr_lo; + u32 img_addr_hi; + u32 img_size; +}; + +enum boot_stage_bit { + BOOT_STAGE_ROM_BIT, + BOOT_STAGE_PCI_LINKUP_START_BIT, + BOOT_STAGE_PCI_PHY_INIT_DONE_BIT, + BOOT_STAGE_PCI_DBI_DONE_BIT, + BOOT_STAGE_PCI_LTSSM_DISABLE_BIT, + BOOT_STAGE_PCI_LTSSM_ENABLE_BIT, + BOOT_STAGE_PCI_MSI_START_BIT, + BOOT_STAGE_PCI_WAIT_DOORBELL_BIT, + BOOT_STAGE_DOWNLOAD_PBL_BIT, + BOOT_STAGE_DOWNLOAD_PBL_DONE_BIT, + BOOT_STAGE_SECURITY_START_BIT, + BOOT_STAGE_CHECK_BL1_ID_BIT, + BOOT_STAGE_JUMP_BL1_BIT, + /* Not documented but the it is the last stage */ + BOOT_STAGE_DONE_BIT, +}; + +/* Every bits of boot_stage_bit are filled */ +#define BOOT_STAGE_DONE_MASK (BIT(BOOT_STAGE_DONE_BIT + 1) - 1) +#endif + void modem_ctrl_set_kerneltime(struct modem_ctl *mc); int modem_ctrl_check_offset_data(struct modem_ctl *mc); void change_modem_state(struct modem_ctl *mc, enum modem_state state); +#if IS_ENABLED(CONFIG_SEC_MODEM_S5100) +int s5100_force_crash_exit_ext(void); +int s5100_poweron_pcie(struct modem_ctl *mc, bool boot_on); +int s5100_try_gpio_cp_wakeup(struct modem_ctl *mc); +void s5100_set_pcie_irq_affinity(struct modem_ctl *mc); +int s5100_set_outbound_atu(struct modem_ctl *mc, struct cp_btl *btl, + loff_t *pos, u32 map_size); +#endif + #endif /* __MODEM_CTRL_H__ */ diff --git a/drivers/soc/google/cpif/modem_ctrl_s5000ap.c b/drivers/soc/google/cpif/modem_ctrl_s5000ap.c index f7c7745fb775..7294edc82a9e 100644 --- a/drivers/soc/google/cpif/modem_ctrl_s5000ap.c +++ b/drivers/soc/google/cpif/modem_ctrl_s5000ap.c @@ -12,9 +12,9 @@ #include #include #include -#include -#include #include +#include +#include #include #include #if IS_ENABLED(CONFIG_EXYNOS_PMU_IF) @@ -29,9 +29,6 @@ #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) #include "s51xx_pcie.h" #endif -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) -#include "link_device.h" -#endif #if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) #include "../../../video/fbdev/exynos/dpu30/decon.h" static int s5000ap_lcd_notifier(struct notifier_block *notifier, @@ -41,14 +38,37 @@ static int s5000ap_lcd_notifier(struct notifier_block *notifier, /* * CP_WDT interrupt handler */ +#if IS_ENABLED(CONFIG_SOC_S5E9925) && IS_ENABLED(CONFIG_SOC_S5E9925_EVT0) +#define PMU_CP_INT_IN 0x3940 +#define CP_SCANDUMP_MASK (0x1 << 7) +#elif IS_ENABLED(CONFIG_SOC_S5E9925) +#define PMU_CP_INT_IN 0x3930 +#define CP_SCANDUMP_MASK (0x1 << 7) +#elif IS_ENABLED(CONFIG_SOC_S5E8825) +#define PMU_CP_INT_IN 0x3540 +#define CP_SCANDUMP_MASK (0x1 << 7) +#endif static irqreturn_t cp_wdt_handler(int irq, void *arg) { struct modem_ctl *mc = (struct modem_ctl *)arg; enum modem_state new_state; struct link_device *ld = get_current_link(mc->bootd); +#if IS_ENABLED(CONFIG_SOC_S5E9925) || IS_ENABLED(CONFIG_SOC_S5E8825) + u32 val; +#endif - mif_disable_irq(&mc->irq_cp_wdt); mif_info("%s: CP_WDT occurred\n", mc->name); + mif_disable_irq(&mc->irq_cp_wdt); + +#if IS_ENABLED(CONFIG_SOC_S5E9925) || IS_ENABLED(CONFIG_SOC_S5E8825) + mif_info("enable CP scandump request\n"); + exynos_pmu_read(PMU_CP_INT_IN, &val); + if (val & CP_SCANDUMP_MASK) { + mif_info("cp scandump request detected\n"); + dbg_snapshot_expire_watchdog(); + return IRQ_HANDLED; + } +#endif if (mc->phone_state == STATE_ONLINE) modem_notify_event(MODEM_EVENT_WATCHDOG, mc); @@ -231,6 +251,7 @@ static int init_control_messages(struct modem_ctl *mc) int ds_det; #if IS_ENABLED(CONFIG_CP_BTL) unsigned int sbi_ext_backtrace_mask, sbi_ext_backtrace_pos; + unsigned int sbi_ext_backtrace_ext_mask, sbi_ext_backtrace_ext_pos; #endif if (modem->offset_cmsg_offset) @@ -250,10 +271,12 @@ static int init_control_messages(struct modem_ctl *mc) set_ctrl_msg(&mld->cp2ap_msg, 0); if (ld->capability_check) { - iowrite32(0, mld->ap_capability_0_offset); - iowrite32(0, mld->cp_capability_0_offset); - iowrite32(0, mld->ap_capability_1_offset); - iowrite32(0, mld->cp_capability_1_offset); + int part; + + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + iowrite32(0, mld->ap_capability_offset[part]); + iowrite32(0, mld->cp_capability_offset[part]); + } } if (!np) { @@ -267,6 +290,14 @@ static int init_control_messages(struct modem_ctl *mc) mif_dt_read_u32(np, "sbi_ext_backtrace_pos", sbi_ext_backtrace_pos); update_ctrl_msg(&mld->ap2cp_united_status, mc->mdm_data->btl.enabled, sbi_ext_backtrace_mask, sbi_ext_backtrace_pos); + + if (mc->mdm_data->btl.support_extension) { + mif_info("btl extension enable:%d\n", mc->mdm_data->btl.extension_enabled); + mif_dt_read_u32(np, "sbi_ext_backtrace_ext_mask", sbi_ext_backtrace_ext_mask); + mif_dt_read_u32(np, "sbi_ext_backtrace_ext_pos", sbi_ext_backtrace_ext_pos); + update_ctrl_msg(&mld->ap2cp_united_status, mc->mdm_data->btl.extension_enabled, + sbi_ext_backtrace_ext_mask, sbi_ext_backtrace_ext_pos); + } #endif mif_dt_read_u32(np, "sbi_sys_rev_mask", sbi_sys_rev_mask); @@ -301,12 +332,6 @@ static int power_on_cp(struct modem_ctl *mc) { mif_info("+++\n"); - mc->receive_first_ipc = 0; - -#if !IS_ENABLED(CONFIG_CP_SECURE_BOOT) - exynos_cp_init(); -#endif - change_modem_state(mc, STATE_OFFLINE); if (cal_cp_status() == 0) { @@ -371,8 +396,6 @@ static int power_reset_cp(struct modem_ctl *mc) mif_info("+++\n"); - mc->receive_first_ipc = 0; - /* 2cp dump WA */ if (timer_pending(&mld->crash_ack_timer)) del_timer(&mld->crash_ack_timer); @@ -381,7 +404,6 @@ static int power_reset_cp(struct modem_ctl *mc) if (ld->sbd_ipc && hrtimer_active(&mld->sbd_print_timer)) hrtimer_cancel(&mld->sbd_print_timer); - /* mc->phone_state = STATE_OFFLINE; */ if (mc->phone_state == STATE_OFFLINE) { mif_info("already offline\n"); return 0; @@ -390,7 +412,8 @@ static int power_reset_cp(struct modem_ctl *mc) if (mc->phone_state == STATE_ONLINE) modem_notify_event(MODEM_EVENT_RESET, mc); - /* Change phone state to OFFLINE */ + change_modem_state(mc, STATE_RESET); + msleep(STATE_RESET_INTERVAL_MS); change_modem_state(mc, STATE_OFFLINE); if (cal_cp_status()) { @@ -417,8 +440,6 @@ static int power_reset_dump_cp(struct modem_ctl *mc) mif_info("+++\n"); - mc->receive_first_ipc = 0; - /* 2cp dump WA */ if (timer_pending(&mld->crash_ack_timer)) del_timer(&mld->crash_ack_timer); @@ -546,9 +567,6 @@ static int complete_normal_boot(struct modem_ctl *mc) struct modem_data *modem = mc->mdm_data; struct mem_link_device *mld = modem->mld; #endif -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) - struct link_device *ld = get_current_link(mc->bootd); -#endif mif_info("+++\n"); @@ -582,7 +600,7 @@ static int complete_normal_boot(struct modem_ctl *mc) mc->lcd_notifier.notifier_call = s5000ap_lcd_notifier; ret = register_lcd_status_notifier(&mc->lcd_notifier); if (ret) { - mif_err("failed to register LCD notifier"); + mif_err("failed to register LCD notifier\n"); return ret; } } @@ -592,9 +610,6 @@ static int complete_normal_boot(struct modem_ctl *mc) mc->sbi_lcd_status_pos); #endif /* CONFIG_CP_LCD_NOTIFIER */ -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) - mif_add_timer(&ld->cplog_timer, (10 * HZ), shmem_pr_sbdcplog); -#endif mif_info("---\n"); exit: @@ -606,41 +621,10 @@ static int trigger_cp_crash(struct modem_ctl *mc) struct link_device *ld = get_current_link(mc->bootd); struct mem_link_device *mld = to_mem_link_device(ld); u32 crash_type = ld->crash_reason.type; -#if IS_ENABLED(CONFIG_SOC_EXYNOS9630) - unsigned int val = 0; /* value used for PMU registers */ -#endif - mif_info("+++\n"); -#if IS_ENABLED(CONFIG_SOC_EXYNOS9630) - exynos_pmu_read(0x3200, &val); /* CP_CONFIGURATION */ - mif_info("CP_CONFIGURATION: 0x%08X\n", val); - exynos_pmu_read(0x3204, &val); /* CP_STATUS */ - mif_info("CP_STATUS: 0x%08X\n", val); - exynos_pmu_read(0x3208, &val); /* CP_STATES */ - mif_info("CP_STATES: 0x%08X\n", val); - exynos_pmu_read(0x320C, &val); /* CP_OPTION */ - mif_info("CP_OPTION: 0x%08X\n", val); - exynos_pmu_read(0x3210, &val); /* CP_CTRL_NS */ - mif_info("CP_CTRL_NS: 0x%08X\n", val); - exynos_pmu_read(0x3220, &val); /* CP_OUT */ - mif_info("CP_OUT: 0x%08X\n", val); - exynos_pmu_read(0x3224, &val); /* CP_IN */ - mif_info("CP_IN: 0x%08X\n", val); - exynos_pmu_read(0x3240, &val); /* CP_INT_IN */ - mif_info("CP_INT_IN: 0x%08X\n", val); - exynos_pmu_read(0x3244, &val); /* CP_INT_EN */ - mif_info("CP_INT_EN: 0x%08X\n", val); - exynos_pmu_read(0x3248, &val); /* CP_INT_TYPE */ - mif_info("CP_INT_TYPE: 0x%08X\n", val); - exynos_pmu_read(0x324c, &val); /* CP_INT_DIR */ - mif_info("CP_INT_DIR: 0x%08X\n", val); -#endif + mif_info("+++\n"); - if (ld->protocol == PROTOCOL_SIT && - crash_type == CRASH_REASON_RIL_TRIGGER_CP_CRASH) - ld->link_trigger_cp_crash(mld, crash_type, ld->crash_reason.string); - else - ld->link_trigger_cp_crash(mld, crash_type, "Forced crash is called"); + ld->link_trigger_cp_crash(mld, crash_type, "Forced crash is called"); mif_info("---\n"); return 0; @@ -670,82 +654,6 @@ EXPORT_SYMBOL(modem_force_crash_exit_ext); #if IS_ENABLED(CONFIG_CP_UART_NOTI) #if IS_ENABLED(CONFIG_PMU_UART_SWITCH) -#if IS_ENABLED(CONFIG_SOC_EXYNOS9630) -static void __iomem *uart_txd_addr; /* SEL_TXD_GPIO_UART_DEBUG */ -static void __iomem *uart_rxd_addr; /* SEL_RXD_CP_UART */ -void change_to_cp_uart(void) -{ - if (uart_txd_addr == NULL) { - uart_txd_addr = devm_ioremap(g_mc->dev, 0x10E2062C, SZ_64); - if (uart_txd_addr == NULL) { - mif_err("Err: failed to ioremap UART TXD!\n"); - return; - } - } - if (uart_rxd_addr == NULL) { - uart_rxd_addr = devm_ioremap(g_mc->dev, 0x10E20650, SZ_64); - if (uart_rxd_addr == NULL) { - mif_err("Err: failed to ioremap UART RXD!\n"); - return; - } - } - mif_info("CHANGE TO CP UART\n"); - __raw_writel(0x2, uart_txd_addr); - mif_info("SEL_TXD_GPIO_UART_DEBUG val: %08X\n", __raw_readl(uart_txd_addr)); - __raw_writel(0x1, uart_rxd_addr); - mif_info("SEL_RXD_CP_UART val: %08X\n", __raw_readl(uart_rxd_addr)); -} - -void change_to_ap_uart(void) -{ - if (uart_txd_addr == NULL) { - uart_txd_addr = devm_ioremap(g_mc->dev, 0x10E2062C, SZ_64); - if (uart_txd_addr == NULL) { - mif_err("Err: failed to ioremap UART TXD!\n"); - return; - } - } - if (uart_rxd_addr == NULL) { - uart_rxd_addr = devm_ioremap(g_mc->dev, 0x10E20650, SZ_64); - if (uart_rxd_addr == NULL) { - mif_err("Err: failed to ioremap UART RXD!\n"); - return; - } - } - mif_info("CHANGE TO CP UART\n"); - __raw_writel(0x0, uart_txd_addr); - mif_info("SEL_TXD_GPIO_UART_DEBUG val: %08X\n", __raw_readl(uart_txd_addr)); - __raw_writel(0x0, uart_rxd_addr); - mif_info("SEL_RXD_CP_UART val: %08X\n", __raw_readl(uart_rxd_addr)); -} -#elif IS_ENABLED(CONFIG_SOC_EXYNOS3830) -void change_to_cp_uart(void) -{ - int ret = 0; - - ret = exynos_pmu_write(0x0760, 0x11002000); - if (ret < 0) { - mif_err("ERR(%d) set CP UART_IO_SHARE_CTRL\n", ret); - return; - } - - mif_info("CHANGE TO CP UART\n"); -} - -void change_to_ap_uart(void) -{ - int ret = 0; - - ret = exynos_pmu_write(0x0760, 0x00120000); - if (ret < 0) { - mif_err("ERR(%d) set AP UART_IO_SHARE_CTRL\n", ret); - return; - } - - mif_info("CHANGE TO AP UART\n"); -} -#endif /* CONFIG_SOC_EXYNOSxxxx */ - void send_uart_noti_to_modem(int val) { struct modem_data *modem; @@ -871,6 +779,8 @@ static int suspend_cp(struct modem_ctl *mc) struct modem_data *modem = mc->mdm_data; struct mem_link_device *mld = modem->mld; + mld->link_dev.stop_timers(mld); + modem_ctrl_set_kerneltime(mc); mif_info("%s: pda_active:0\n", mc->name); @@ -897,6 +807,8 @@ static int resume_cp(struct modem_ctl *mc) cp_mbox_set_interrupt(CP_MBOX_IRQ_IDX_0, mc->int_pda_active); + mld->link_dev.start_timers(mld); + return 0; } @@ -923,15 +835,9 @@ static void s5000ap_get_pdata(struct modem_ctl *mc, struct modem_data *modem) struct modem_mbox *mbx = modem->mbx; mc->int_pda_active = mbx->int_ap2cp_active; - mc->int_cp_wakeup = mbx->int_ap2cp_wakeup; - - mc->irq_phone_active = mbx->irq_cp2ap_active; - - mc->mbx_ap_status = mbx->mbx_ap2cp_status; - mc->mbx_cp_status = mbx->mbx_cp2ap_status; - mc->int_uart_noti = mbx->int_ap2cp_uart_noti; + mc->irq_phone_active = mbx->irq_cp2ap_active; mc->sbi_lte_active_mask = modem->sbi_lte_active_mask; mc->sbi_lte_active_pos = modem->sbi_lte_active_pos; @@ -952,9 +858,11 @@ static void s5000ap_get_pdata(struct modem_ctl *mc, struct modem_data *modem) mc->sbi_ds_det_mask = modem->sbi_ds_det_mask; mc->sbi_ds_det_pos = modem->sbi_ds_det_pos; +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) mc->sbi_lcd_status_mask = modem->sbi_lcd_status_mask; mc->sbi_lcd_status_pos = modem->sbi_lcd_status_pos; mc->int_lcd_status = mbx->int_ap2cp_lcd_status; +#endif } static int send_panic_to_cp_notifier(struct notifier_block *nb, @@ -991,11 +899,12 @@ static int cp_itmon_notifier(struct notifier_block *nb, if (IS_ERR_OR_NULL(itmon_data)) return NOTIFY_DONE; - if (itmon_data->port && (strncmp("MODEM", itmon_data->port, - sizeof("MODEM") - 1) == 0)) { - modem_force_crash_exit_ext(); + if (itmon_data->port && + (strncmp("CP_", itmon_data->port, sizeof("CP_") - 1) == 0 || + strncmp("MODEM", itmon_data->port, sizeof("MODEM") - 1) == 0) && + itmon_data->errcode == 1) { /* force cp crash when decode error */ mif_info("CP itmon notifier: cp crash request complete\n"); - return NOTIFY_OK; + modem_force_crash_exit_ext(); } return NOTIFY_DONE; @@ -1078,6 +987,9 @@ int s5000ap_init_modemctl_device(struct modem_ctl *mc, struct modem_data *pdata) init_completion(&mc->init_cmpl); init_completion(&mc->off_cmpl); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + init_completion(&mc->clatinfo_ack); +#endif /* AP2CP_CFG */ mif_dt_read_u32_noerr(np, "ap2cp_cfg_addr", mc->ap2cp_cfg_addr); diff --git a/drivers/soc/google/cpif/modem_ctrl_s5100.c b/drivers/soc/google/cpif/modem_ctrl_s5100.c index 00198ead3c50..b4058148f4f7 100644 --- a/drivers/soc/google/cpif/modem_ctrl_s5100.c +++ b/drivers/soc/google/cpif/modem_ctrl_s5100.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -25,13 +24,9 @@ #include #include -#if IS_ENABLED(CONFIG_MUIC_NOTIFIER) -#include -#include -#endif - #include -#include +#include +#include #include "modem_prj.h" #include "modem_utils.h" @@ -44,10 +39,9 @@ #include #endif -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_S2MPU) -#include +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) +#include "link_device_pcie_iommu.h" #endif - #if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) #include "../../../video/fbdev/exynos/dpu30/decon.h" static int s5100_lcd_notifier(struct notifier_block *notifier, @@ -60,22 +54,7 @@ static int s5100_lcd_notifier(struct notifier_block *notifier, static struct modem_ctl *g_mc; -static int register_phone_active_interrupt(struct modem_ctl *mc); -static int register_cp2ap_wakeup_interrupt(struct modem_ctl *mc); - -#if defined(MODULE) -/* GKI TODO */ -#else /* MODULE */ -static int sys_rev; -static int __init console_setup(char *str) -{ - get_option(&str, &sys_rev); - mif_info("board_rev : %d\n", sys_rev); - - return 0; -} -__setup("androidboot.revision=", console_setup); -#endif /* MODULE */ +static int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off); static int s5100_reboot_handler(struct notifier_block *nb, unsigned long l, void *p) @@ -93,20 +72,20 @@ static int s5100_reboot_handler(struct notifier_block *nb, static void print_mc_state(struct modem_ctl *mc) { - int pwr = mif_gpio_get_value(&mc->s5100_gpio_cp_pwr, false); - int reset = mif_gpio_get_value(&mc->s5100_gpio_cp_reset, false); - int pshold = mif_gpio_get_value(&mc->s5100_gpio_cp_ps_hold, false); + int pwr = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR], false); + int reset = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], false); + int pshold = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_PS_HOLD], false); - int ap_wakeup = mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, false); - int cp_wakeup = mif_gpio_get_value(&mc->s5100_gpio_cp_wakeup, false); + int ap_wakeup = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], false); + int cp_wakeup = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP], false); - int dump = mif_gpio_get_value(&mc->s5100_gpio_cp_dump_noti, false); - int ap_status = mif_gpio_get_value(&mc->s5100_gpio_ap_status, false); - int phone_active = mif_gpio_get_value(&mc->s5100_gpio_phone_active, false); + int dump = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], false); + int ap_status = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], false); + int phone_active = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], false); - mif_debug("%s: %ps:GPIO - pwr:%d rst:%d phd:%d aw:%d cw:%d dmp:%d ap_status:%d phone_state:%d\n", - mc->name, CALLER, pwr, reset, pshold, ap_wakeup, cp_wakeup, - dump, ap_status, phone_active); + mif_debug("%s: %ps:GPIO pwr:%d rst:%d phd:%d c2aw:%d a2cw:%d dmp:%d ap_act:%d cp_act:%d\n", + mc->name, CALLER, pwr, reset, pshold, ap_wakeup, cp_wakeup, dump, + ap_status, phone_active); } static void pcie_clean_dislink(struct modem_ctl *mc) @@ -115,6 +94,8 @@ static void pcie_clean_dislink(struct modem_ctl *mc) if (mc->pcie_voice_call_on) { modem_notify_event(MODEM_EVENT_RESET, mc); mc->pcie_voice_call_on = false; + } else { + modem_notify_event(MODEM_EVENT_OFFLINE, mc); } #endif @@ -137,12 +118,15 @@ static void cp2ap_wakeup_work(struct work_struct *work) cp2ap_wakeup_time = ktime_get_boottime(); spin_lock_irqsave(&mc->power_stats_lock, flags); - mc->cp_power_stats.last_exit_timestamp_usec = ktime_to_us(cp2ap_wakeup_time); - mc->cp_power_stats.duration_usec += (mc->cp_power_stats.last_exit_timestamp_usec - - mc->cp_power_stats.last_entry_timestamp_usec); + if (mc->cp_power_stats.suspended) { + mc->cp_power_stats.last_exit_timestamp_usec = ktime_to_us(cp2ap_wakeup_time); + mc->cp_power_stats.duration_usec += (mc->cp_power_stats.last_exit_timestamp_usec - + mc->cp_power_stats.last_entry_timestamp_usec); + } + mc->cp_power_stats.suspended = false; spin_unlock_irqrestore(&mc->power_stats_lock, flags); - s5100_poweron_pcie(mc); + s5100_poweron_pcie(mc, false); } static void cp2ap_suspend_work(struct work_struct *work) @@ -157,8 +141,11 @@ static void cp2ap_suspend_work(struct work_struct *work) cp2ap_suspend_time = ktime_get_boottime(); spin_lock_irqsave(&mc->power_stats_lock, flags); - mc->cp_power_stats.last_entry_timestamp_usec = ktime_to_us(cp2ap_suspend_time); - mc->cp_power_stats.count++; + if (!mc->cp_power_stats.suspended) { + mc->cp_power_stats.last_entry_timestamp_usec = ktime_to_us(cp2ap_suspend_time); + mc->cp_power_stats.count++; + } + mc->cp_power_stats.suspended = true; spin_unlock_irqrestore(&mc->power_stats_lock, flags); s5100_poweroff_pcie(mc, false); @@ -173,8 +160,7 @@ static ssize_t power_stats_show(struct device *dev, u64 adjusted_duration_usec = mc->cp_power_stats.duration_usec; spin_lock_irqsave(&mc->power_stats_lock, flags); - if (mc->cp_power_stats.last_entry_timestamp_usec > - mc->cp_power_stats.last_exit_timestamp_usec) { + if (mc->cp_power_stats.suspended) { u64 now_usec = ktime_to_us(ktime_get_boottime()); adjusted_duration_usec += now_usec - mc->cp_power_stats.last_entry_timestamp_usec; @@ -257,10 +243,10 @@ static int check_link_order = 1; static irqreturn_t ap_wakeup_handler(int irq, void *data) { struct modem_ctl *mc = (struct modem_ctl *)data; - int gpio_val = mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, true); + int gpio_val = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], true); unsigned long flags; - mif_disable_irq(&mc->s5100_irq_ap_wakeup); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); if (mc->device_reboot) { mif_err("skip : device is rebooting..!!!\n"); @@ -289,9 +275,9 @@ static irqreturn_t ap_wakeup_handler(int irq, void *data) spin_unlock_irqrestore(&mc->pcie_pm_lock, flags); mc->apwake_irq_chip->irq_set_type( - irq_get_irq_data(mc->s5100_irq_ap_wakeup.num), + irq_get_irq_data(mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num), (gpio_val == 1 ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH)); - mif_enable_irq(&mc->s5100_irq_ap_wakeup); + mif_enable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); queue_work_on(RUNTIME_PM_AFFINITY_CORE, mc->wakeup_wq, (gpio_val == 1 ? &mc->wakeup_work : &mc->suspend_work)); @@ -307,6 +293,9 @@ static irqreturn_t cp_active_handler(int irq, void *data) int cp_active; enum modem_state old_state; enum modem_state new_state; + struct legacy_link_device *bl; + struct legacy_ipc_device *ipc_dev; + int i; if (mc == NULL) { mif_err_limited("modem_ctl is NOT initialized - IGNORING interrupt\n"); @@ -326,7 +315,7 @@ static irqreturn_t cp_active_handler(int irq, void *data) goto irq_done; } - cp_active = mif_gpio_get_value(&mc->s5100_gpio_phone_active, true); + cp_active = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], true); mif_err("[PHONE_ACTIVE Handler] state:%s cp_active:%d\n", cp_state_str(mc->phone_state), cp_active); @@ -347,8 +336,8 @@ static irqreturn_t cp_active_handler(int irq, void *data) if (ld->crash_reason.type == CRASH_REASON_NONE) ld->crash_reason.type = CRASH_REASON_CP_ACT_CRASH; - mif_info("Set s5100_cp_reset_required to false\n"); mc->s5100_cp_reset_required = false; + mif_info("Set s5100_cp_reset_required to 0\n"); if (old_state != new_state) { mif_err("new_state = %s\n", cp_state_str(new_state)); @@ -359,10 +348,19 @@ static irqreturn_t cp_active_handler(int irq, void *data) change_modem_state(mc, new_state); } + bl = &mld->legacy_link_dev; + + for (i = 0; i < IPC_MAP_MAX; i++) { + ipc_dev = bl->dev[i]; + mif_info("%s TX: head:%d tail:%d, RX: head: %d tail:%d\n", + ipc_dev->name, get_txq_head(ipc_dev), get_txq_tail(ipc_dev), + get_rxq_head(ipc_dev), get_rxq_tail(ipc_dev)); + } + atomic_set(&mld->forced_cp_crash, 0); irq_done: - mif_disable_irq(&mc->s5100_irq_phone_active); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); return IRQ_HANDLED; } @@ -374,19 +372,19 @@ static int register_phone_active_interrupt(struct modem_ctl *mc) if (mc == NULL) return -EINVAL; - if (mc->s5100_irq_phone_active.registered == true) + if (mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE].registered) return 0; mif_info("Register PHONE ACTIVE interrupt.\n"); - mif_init_irq(&mc->s5100_irq_phone_active, mc->s5100_irq_phone_active.num, - "phone_active", IRQF_TRIGGER_LOW); + mif_init_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE], + mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE].num, + "phone_active", IRQF_TRIGGER_LOW); - ret = mif_request_irq(&mc->s5100_irq_phone_active, cp_active_handler, mc); + ret = mif_request_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE], cp_active_handler, mc); if (ret) { mif_err("%s: ERR! request_irq(%s#%d) fail (%d)\n", - mc->name, mc->s5100_irq_phone_active.name, - mc->s5100_irq_phone_active.num, ret); - mif_err("xxx\n"); + mc->name, mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE].name, + mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE].num, ret); return ret; } @@ -400,25 +398,25 @@ static int register_cp2ap_wakeup_interrupt(struct modem_ctl *mc) if (mc == NULL) return -EINVAL; - if (mc->s5100_irq_ap_wakeup.registered == true) { + if (mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].registered) { mif_info("Set IRQF_TRIGGER_LOW to cp2ap_wakeup gpio\n"); check_link_order = 1; ret = mc->apwake_irq_chip->irq_set_type( - irq_get_irq_data(mc->s5100_irq_ap_wakeup.num), + irq_get_irq_data(mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num), IRQF_TRIGGER_LOW); return ret; } mif_info("Register CP2AP WAKEUP interrupt.\n"); - mif_init_irq(&mc->s5100_irq_ap_wakeup, mc->s5100_irq_ap_wakeup.num, "cp2ap_wakeup", - IRQF_TRIGGER_LOW); + mif_init_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP], + mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num, + "cp2ap_wakeup", IRQF_TRIGGER_LOW); - ret = mif_request_irq(&mc->s5100_irq_ap_wakeup, ap_wakeup_handler, mc); + ret = mif_request_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP], ap_wakeup_handler, mc); if (ret) { mif_err("%s: ERR! request_irq(%s#%d) fail (%d)\n", - mc->name, mc->s5100_irq_ap_wakeup.name, - mc->s5100_irq_ap_wakeup.num, ret); - mif_err("xxx\n"); + mc->name, mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].name, + mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num, ret); return ret; } @@ -507,20 +505,23 @@ static int init_control_messages(struct modem_ctl *mc) struct mem_link_device *mld = to_mem_link_device(ld); int ds_det; + if (modem->offset_cmsg_offset) + iowrite32(modem->cmsg_offset, mld->cmsg_offset); if (modem->offset_srinfo_offset) iowrite32(modem->srinfo_offset, mld->srinfo_offset); + if (ld->capability_check && modem->offset_capability_offset) + iowrite32(modem->capability_offset, mld->capability_offset); set_ctrl_msg(&mld->ap2cp_united_status, 0); set_ctrl_msg(&mld->cp2ap_united_status, 0); if (ld->capability_check) { - if (modem->offset_capability_offset) - iowrite32(modem->capability_offset, mld->capability_offset); + int part; - iowrite32(0, mld->ap_capability_0_offset); - iowrite32(0, mld->cp_capability_0_offset); - iowrite32(0, mld->ap_capability_1_offset); - iowrite32(0, mld->cp_capability_1_offset); + for (part = 0; part < AP_CP_CAP_PARTS; part++) { + iowrite32(0, mld->ap_capability_offset[part]); + iowrite32(0, mld->cp_capability_offset[part]); + } } ds_det = get_ds_detect(); @@ -536,6 +537,262 @@ static int init_control_messages(struct modem_ctl *mc) return 0; } +static void set_pcie_msi_int(struct link_device *ld, bool enabled) +{ + struct mem_link_device *mld = to_mem_link_device(ld); + int irq; + bool *irq_wake; +#if IS_ENABLED(CONFIG_CP_PKTPROC) + struct pktproc_adaptor *ppa = &mld->pktproc; + unsigned int q_idx = 0; +#endif + + if (!mld->msi_irq_base) + return; + + irq = mld->msi_irq_base; + irq_wake = &mld->msi_irq_base_wake; + + do { + if (enabled) { + int err; + + if (!mld->msi_irq_enabled) + enable_irq(irq); + + if (!*irq_wake) { + err = enable_irq_wake(irq); + *irq_wake = !err; + } + } else { + if (mld->msi_irq_enabled) + disable_irq(irq); + + if (*irq_wake) { + disable_irq_wake(irq); + *irq_wake = false; + } + } + + irq = 0; +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (q_idx < ppa->num_queue) { + struct pktproc_queue *q = ppa->q[q_idx]; + + irq = q->irq; + irq_wake = &q->msi_irq_wake; + q_idx++; + } +#endif + } while (irq); + + mld->msi_irq_enabled = enabled; +} + +static int request_pcie_int(struct link_device *ld, struct platform_device *pdev) +{ +#define DOORBELL_INT_MASK(x) ((x) | 0x10000) + + int ret, base_irq; + struct mem_link_device *mld = to_mem_link_device(ld); + struct device *dev = &pdev->dev; + struct modem_ctl *mc = ld->mc; + struct modem_data *modem = mc->mdm_data; + int irq_offset = 0; + + /* Doorbell */ + mld->intval_ap2cp_msg = DOORBELL_INT_MASK(modem->mbx->int_ap2cp_msg); + mld->intval_ap2cp_pcie_link_ack = DOORBELL_INT_MASK(modem->mbx->int_ap2cp_pcie_link_ack); + + /* MSI */ + base_irq = s51xx_pcie_request_msi_int(mc->s51xx_pdev, 4); + if (base_irq <= 0) { + mif_err("Can't get MSI IRQ!!!\n"); + return -EFAULT; + } + mif_info("MSI base_irq(%d)\n", base_irq); + + ret = devm_request_irq(dev, base_irq + irq_offset, shmem_irq_handler, + IRQF_SHARED, "mif_cp2ap_msg", mld); + if (ret) { + mif_err("Can't request cp2ap_msg interrupt!!!\n"); + return -EIO; + } + irq_offset++; + + ret = devm_request_irq(dev, base_irq + irq_offset, shmem_tx_state_handler, + IRQF_SHARED, "mif_cp2ap_status", mld); + if (ret) { + mif_err("Can't request cp2ap_status interrupt!!!\n"); + return -EIO; + } + irq_offset++; + +#if IS_ENABLED(CONFIG_CP_PKTPROC) + if (mld->pktproc.use_exclusive_irq) { + struct pktproc_adaptor *ppa = &mld->pktproc; + unsigned int i; + + for (i = 0; i < ppa->num_queue; i++) { + struct pktproc_queue *q = ppa->q[i]; + + ret = register_separated_msi_vector(mc->pcie_ch_num, q->irq_handler, q, + &q->irq); + if (ret < 0) { + mif_err("register_separated_msi_vector for pktproc q[%u] err:%d\n", + i, ret); + q->irq = 0; + return -EIO; + } + } + } +#endif + + mld->msi_irq_base = base_irq; + mld->msi_irq_enabled = true; + set_pcie_msi_int(ld, true); + + return base_irq; +} + +static int register_pcie(struct link_device *ld) +{ + struct modem_ctl *mc = ld->mc; + struct platform_device *pdev = to_platform_device(mc->dev); + static int is_registered; + struct mem_link_device *mld = to_mem_link_device(ld); + u32 cp_num = ld->mdm_data->cp_num; + +#if IS_ENABLED(CONFIG_GS_S2MPU) + u32 shmem_idx; + int ret; + struct device_node *s2mpu_dn; +#endif + mif_info("CP EP driver initialization start.\n"); + + if (!mld->msi_reg_base && (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)) + mld->msi_reg_base = cp_shmem_get_region(cp_num, SHMEM_MSI); + +#if IS_ENABLED(CONFIG_GS_S2MPU) + + s2mpu_dn = of_parse_phandle(mc->dev->of_node, "s2mpu", 0); + if (!s2mpu_dn) { + mif_err("Failed to find s2mpu from device tree\n"); + return -EINVAL; + } + + mc->s2mpu = s2mpu_fwnode_to_info(&s2mpu_dn->fwnode); + if (!mc->s2mpu) { + mif_err("Failed to get S2MPU\n"); + return -EPROBE_DEFER; + } + + for (shmem_idx = 0 ; shmem_idx < MAX_CP_SHMEM ; shmem_idx++) { + if (shmem_idx == SHMEM_MSI && !(mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)) + continue; + + if (cp_shmem_get_base(cp_num, shmem_idx)) { + ret = s2mpu_open(mc->s2mpu, + cp_shmem_get_base(cp_num, shmem_idx), + cp_shmem_get_size(cp_num, shmem_idx), + DMA_BIDIRECTIONAL); + if (ret) { + mif_err("S2MPU open failed error=%d\n", ret); + return -EINVAL; + } + } + } + + /* Also setup AoC window for voice calls */ + ret = s2mpu_open(mc->s2mpu, + AOC_PCIE_WINDOW_START, AOC_PCIE_WINDOW_SIZE, + DMA_BIDIRECTIONAL); + + if (ret) { + mif_err("S2MPU AoC open failed error=%d\n", ret); + return -EINVAL; + } + +#endif + +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + cpif_pcie_iommu_enable_regions(mld); +#endif + + msleep(200); + + s5100_poweron_pcie(mc, !!(mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)); + + if (is_registered == 0) { + /* initialize the pci_dev for modem_ctl */ + mif_info("s51xx_pcie_init start\n"); + s51xx_pcie_init(mc); + if (!mc->s51xx_pdev) { + mif_err("s51xx_pdev is NULL. Check if CP wake up is done.\n"); + return -EINVAL; + } + + /* debug: check MSI 32bit or 64bit - should be set as 32bit before this point*/ + // debug: pci_read_config_dword(s51xx_pcie.s51xx_pdev, 0x50, &msi_val); + // debug: mif_err("MSI Control Reg : 0x%x\n", msi_val); + + request_pcie_int(ld, pdev); + first_save_s51xx_status(mc->s51xx_pdev); + + is_registered = 1; + } else { + if (mc->phone_state == STATE_CRASH_RESET) { + print_msi_register(mc->s51xx_pdev); + enable_irq(mld->msi_irq_base); + } + } + + print_msi_register(mc->s51xx_pdev); + mc->pcie_registered = true; + + mif_info("CP EP driver initialization end.\n"); + + return 0; +} + +static void gpio_power_off_cp(struct modem_ctl *mc) +{ +#if IS_ENABLED(CONFIG_CP_WRESET_WA) + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], 0, 50); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR], 0, 0); +#else + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], 0, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N], 0, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR], 0, 30); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_PM_WRST_N], 0, 50); +#endif +} + +static void gpio_power_offon_cp(struct modem_ctl *mc) +{ + gpio_power_off_cp(mc); + +#if IS_ENABLED(CONFIG_CP_WRESET_WA) + udelay(50); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR], 1, 50); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], 1, 50); +#else + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_PM_WRST_N], 1, 10); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR], 1, 10); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], 1, 10); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N], 1, 0); +#endif +} + +static void gpio_power_wreset_cp(struct modem_ctl *mc) +{ +#if !IS_ENABLED(CONFIG_CP_WRESET_WA) + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N], 0, 50); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_PM_WRST_N], 0, 50); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N], 1, 50); +#endif +} + static int power_on_cp(struct modem_ctl *mc) { struct link_device *ld = get_current_link(mc->iod); @@ -544,10 +801,8 @@ static int power_on_cp(struct modem_ctl *mc) mif_info("%s: +++\n", mc->name); - mc->receive_first_ipc = 0; - - mif_disable_irq(&mc->s5100_irq_phone_active); - mif_disable_irq(&mc->s5100_irq_ap_wakeup); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); drain_workqueue(mc->wakeup_wq); print_mc_state(mc); @@ -555,28 +810,25 @@ static int power_on_cp(struct modem_ctl *mc) if (!cpif_wake_lock_active(mc->ws)) cpif_wake_lock(mc->ws); - mc->phone_state = STATE_OFFLINE; + if (mc->phone_state != STATE_OFFLINE) { + change_modem_state(mc, STATE_RESET); + msleep(STATE_RESET_INTERVAL_MS); + } + change_modem_state(mc, STATE_OFFLINE); + pcie_clean_dislink(mc); mc->pcie_registered = false; - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); - mif_gpio_set_value(&mc->s5100_gpio_cp_dump_noti, 0, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], 0, 0); /* Clear shared memory */ init_ctrl_msg(&mld->ap2cp_msg); init_ctrl_msg(&mld->cp2ap_msg); print_mc_state(mc); - - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 50); -#if IS_ENABLED(CONFIG_CP_WRESET_WA) - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 0, 0); - udelay(100); -#endif - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 1, 50); - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 1, 50); - + gpio_power_offon_cp(mc); mif_info("GPIO status after S5100 Power on\n"); print_mc_state(mc); @@ -596,9 +848,7 @@ static int power_off_cp(struct modem_ctl *mc) pcie_clean_dislink(mc); - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 0); - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 0, 0); - + gpio_power_off_cp(mc); print_mc_state(mc); exit: @@ -616,22 +866,20 @@ static int power_shutdown_cp(struct modem_ctl *mc) if (mc->phone_state == STATE_OFFLINE) goto exit; - mif_disable_irq(&mc->s5100_irq_phone_active); - mif_disable_irq(&mc->s5100_irq_ap_wakeup); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); drain_workqueue(mc->wakeup_wq); /* wait for cp_active for 3 seconds */ for (i = 0; i < 150; i++) { - if (mif_gpio_get_value(&mc->s5100_gpio_phone_active, false) == 1) { + if (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], false) == 1) { mif_err("PHONE_ACTIVE pin is HIGH...\n"); break; } msleep(20); } - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 0); - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 0, 0); - + gpio_power_off_cp(mc); print_mc_state(mc); pcie_clean_dislink(mc); @@ -649,14 +897,12 @@ static int power_reset_dump_cp(struct modem_ctl *mc) mif_info("%s: +++\n", mc->name); - mc->receive_first_ipc = 0; - if (ld->sbd_ipc && hrtimer_active(&mld->sbd_print_timer)) hrtimer_cancel(&mld->sbd_print_timer); mc->phone_state = STATE_CRASH_EXIT; - mif_disable_irq(&mc->s5100_irq_phone_active); - mif_disable_irq(&mc->s5100_irq_ap_wakeup); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); drain_workqueue(mc->wakeup_wq); pcie_clean_dislink(mc); @@ -664,33 +910,28 @@ static int power_reset_dump_cp(struct modem_ctl *mc) s51xx_pcie = pci_get_drvdata(mc->s51xx_pdev); if (s51xx_pcie && s51xx_pcie->link_status == 1) { - mif_err("link_satus:%d\n", s51xx_pcie->link_status); + mif_info("link_satus:%d\n", s51xx_pcie->link_status); s51xx_pcie_save_state(mc->s51xx_pdev); pcie_clean_dislink(mc); } #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_GPIO_WA) - if (mif_gpio_set_value(&mc->s5100_gpio_cp_dump_noti, 1, 10)) - mif_gpio_toggle_value(&mc->s5100_gpio_ap_status, 50); + if (mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], 1, 10)) + mif_gpio_toggle_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 50); #else - mif_gpio_set_value(&mc->s5100_gpio_cp_dump_noti, 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], 1, 0); #endif mif_info("s5100_cp_reset_required:%d\n", mc->s5100_cp_reset_required); - if (mc->s5100_cp_reset_required == true) { - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 50); -#if IS_ENABLED(CONFIG_CP_WRESET_WA) - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 0, 0); - udelay(100); - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 1, 50); -#endif - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 1, 50); - print_mc_state(mc); - } + if (mc->s5100_cp_reset_required) + gpio_power_offon_cp(mc); + else + gpio_power_wreset_cp(mc); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); + print_mc_state(mc); - mif_err("---\n"); + mif_info("---\n"); return 0; } @@ -703,8 +944,6 @@ static int power_reset_cp(struct modem_ctl *mc) mif_info("%s: +++\n", mc->name); - mc->receive_first_ipc = 0; - if (ld->sbd_ipc && hrtimer_active(&mld->sbd_print_timer)) hrtimer_cancel(&mld->sbd_print_timer); @@ -716,57 +955,119 @@ static int power_reset_cp(struct modem_ctl *mc) if (s51xx_pcie && s51xx_pcie->link_status == 1) { /* save_s5100_status(); */ - mif_err("link_satus:%d\n", s51xx_pcie->link_status); + mif_info("link_satus:%d\n", s51xx_pcie->link_status); pcie_clean_dislink(mc); } - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 50); -#if IS_ENABLED(CONFIG_CP_WRESET_WA) - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 0, 0); - udelay(100); - mif_gpio_set_value(&mc->s5100_gpio_cp_pwr, 1, 50); -#endif - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 1, 50); + gpio_power_offon_cp(mc); print_mc_state(mc); - mif_err("---\n"); + mif_info("---\n"); return 0; } -static int check_cp_status(struct modem_ctl *mc, unsigned int count) +static int check_cp_status(struct modem_ctl *mc, unsigned int count, bool check_msi) { - int ret = 0; +#define STATUS_NAME(msi) (msi ? "boot_stage" : "CP2AP_WAKEUP") + + struct link_device *ld = get_current_link(mc->bootd); + struct mem_link_device *mld = to_mem_link_device(ld); + bool check_done = false; int cnt = 0; int val; - while (1) { - val = mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, false); - mif_err_limited("CP2AP_WAKEUP == %d (cnt %d)\n", val, cnt); - - if (val != 0) { - ret = 0; - break; - } - - if (++cnt >= count) { - mif_err("ERR! CP2AP_WAKEUP == 0 (cnt %d)\n", cnt); - ret = -EFAULT; - break; + do { + if (check_msi) { + val = (int)ioread32(mld->msi_reg_base + + offsetof(struct msi_reg_type, boot_stage)); + if (val == BOOT_STAGE_DONE_MASK) { + check_done = true; + break; + } + } else { + val = mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], false); + if (val == 1) { + check_done = true; + break; + } } + mif_info_limited("%s == 0x%X (cnt %d)\n", STATUS_NAME(check_msi), val, cnt); msleep(20); - } + } while (++cnt < count); - if (ret == 0) - mif_info("CP2AP_WAKEUP == 1 cnt: %d\n", cnt); - else - mif_err("ERR: Checking count after sending bootloader: %d\n", cnt); + if (!check_done) { + mif_err("ERR! %s == 0x%X (cnt %d)\n", STATUS_NAME(check_msi), val, cnt); + return -EFAULT; + } + mif_info("%s == 0x%X (cnt %d)\n", STATUS_NAME(check_msi), val, cnt); if (cnt == 0) msleep(20); - return ret; + return 0; +} + +static int set_cp_rom_boot_img(struct mem_link_device *mld) +{ + struct link_device *ld = &mld->link_dev; + struct modem_ctl *mc = ld->mc; + struct modem_data *modem = mc->mdm_data; + unsigned long boot_img_addr; + + if (!(mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)) { + mif_err("Invalid attr:0x%lx\n", mld->attrs); + return -EPERM; + } + + if (!mld->msi_reg_base) { + mif_err("MSI region is not assigned yet\n"); + return -EINVAL; + } + + boot_img_addr = cp_shmem_get_base(modem->cp_num, SHMEM_IPC) + mld->boot_img_offset; + + iowrite32(PADDR_LO(boot_img_addr), + mld->msi_reg_base + offsetof(struct msi_reg_type, img_addr_lo)); + iowrite32(PADDR_HI(boot_img_addr), + mld->msi_reg_base + offsetof(struct msi_reg_type, img_addr_hi)); + iowrite32(mld->boot_img_size, + mld->msi_reg_base + offsetof(struct msi_reg_type, img_size)); + + mif_info("boot_img addr:0x%lX size:0x%X\n", boot_img_addr, mld->boot_img_size); + + s51xx_pcie_send_doorbell_int(mc->s51xx_pdev, mld->intval_ap2cp_msg); + + return 0; +} + +static void debug_cp_rom_boot_img(struct mem_link_device *mld) +{ + unsigned char str[64 * 3]; + u8 __iomem *img_base; + u32 img_size; + + if (!(mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE)) { + mif_err("Invalid attr:0x%lx\n", mld->attrs); + return; + } + + img_base = mld->base + mld->boot_img_offset; + img_size = ioread32(mld->msi_reg_base + offsetof(struct msi_reg_type, img_size)); + + mif_err("boot_stage:0x%X err_report:0x%X img_lo:0x%X img_hi:0x%X img_size:0x%X\n", + ioread32(mld->msi_reg_base + offsetof(struct msi_reg_type, boot_stage)), + ioread32(mld->msi_reg_base + offsetof(struct msi_reg_type, err_report)), + ioread32(mld->msi_reg_base + offsetof(struct msi_reg_type, img_addr_lo)), + ioread32(mld->msi_reg_base + offsetof(struct msi_reg_type, img_addr_hi)), + img_size); + + if (img_size > 64) + img_size = 64; + + dump2hex(str, (img_size ? img_size * 3 : 1), img_base, img_size); + mif_err("img_content:%s\n", str); } static int start_normal_boot(struct modem_ctl *mc) @@ -793,9 +1094,9 @@ static int start_normal_boot(struct modem_ctl *mc) change_modem_state(mc, STATE_BOOTING); mif_info("Disable phone actvie interrupt.\n"); - mif_disable_irq(&mc->s5100_irq_phone_active); + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); mc->phone_state = STATE_BOOTING; if (ld->link_start_normal_boot) { @@ -809,17 +1110,39 @@ static int start_normal_boot(struct modem_ctl *mc) return ret; } - ret = check_cp_status(mc, 200); + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE) { + register_pcie(ld); + if (mc->s51xx_pdev && mc->pcie_registered) + set_cp_rom_boot_img(mld); + + ret = check_cp_status(mc, 200, true); + if (ret < 0) + goto status_error; + + s5100_poweroff_pcie(mc, false); + + ret = check_cp_status(mc, 200, false); + if (ret < 0) + goto status_error; + + s5100_poweron_pcie(mc, false); + } else { + ret = check_cp_status(mc, 200, false); + if (ret < 0) + goto status_error; + + register_pcie(ld); + } + +status_error: if (ret < 0) { mif_err("ERR! check_cp_status fail (err %d)\n", ret); + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE) + debug_cp_rom_boot_img(mld); if (cpif_wake_lock_active(mc->ws)) cpif_wake_unlock(mc->ws); - return ret; - } - if (ld->register_pcie) { - mif_info("register_pcie\n"); - ld->register_pcie(ld); + return ret; } mif_info("---\n"); @@ -850,17 +1173,17 @@ static int complete_normal_boot(struct modem_ctl *mc) s51xx_pcie_l1ss_ctrl(1, mc->pcie_ch_num); /* Read cp_active before enabling irq */ - mif_gpio_get_value(&mc->s5100_gpio_phone_active, true); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], true); err = register_phone_active_interrupt(mc); if (err) mif_err("Err: register_phone_active_interrupt:%d\n", err); - mif_enable_irq(&mc->s5100_irq_phone_active); + mif_enable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_CP_ACTIVE]); err = register_cp2ap_wakeup_interrupt(mc); if (err) mif_err("Err: register_cp2ap_wakeup_interrupt:%d\n", err); - mif_enable_irq(&mc->s5100_irq_ap_wakeup); + mif_enable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); print_mc_state(mc); @@ -876,7 +1199,7 @@ static int complete_normal_boot(struct modem_ctl *mc) mc->lcd_notifier.notifier_call = s5100_lcd_notifier; ret = register_lcd_status_notifier(&mc->lcd_notifier); if (ret) { - mif_err("failed to register LCD notifier"); + mif_err("failed to register LCD notifier\n"); return ret; } } @@ -906,30 +1229,27 @@ static int trigger_cp_crash_internal(struct modem_ctl *mc) } print_mc_state(mc); + exynos_pcie_rc_print_msi_register(mc->pcie_ch_num); - if (mif_gpio_get_value(&mc->s5100_gpio_phone_active, true) == 1) { + if (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE], true) == 1) { #if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_GPIO_WA) if (atomic_inc_return(&mc->dump_toggle_issued) > 1) { atomic_dec(&mc->dump_toggle_issued); goto exit; } - if (mif_gpio_set_value(&mc->s5100_gpio_cp_dump_noti, 1, 10)) - mif_gpio_toggle_value(&mc->s5100_gpio_ap_status, 50); + if (mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], 1, 10)) + mif_gpio_toggle_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 50); atomic_dec(&mc->dump_toggle_issued); #else - mif_gpio_set_value(&mc->s5100_gpio_cp_dump_noti, 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI], 1, 0); #endif } else { mif_err("do not need to set dump_noti\n"); } - if (ld->protocol == PROTOCOL_SIT && - crash_type == CRASH_REASON_RIL_TRIGGER_CP_CRASH) - ld->link_trigger_cp_crash(mld, crash_type, ld->crash_reason.string); - else - ld->link_trigger_cp_crash(mld, crash_type, "Forced crash is called"); + ld->link_trigger_cp_crash(mld, crash_type, "Forced crash is called"); exit: mif_err("---\n"); @@ -980,8 +1300,9 @@ int s5100_send_panic_noti_ext(void) static int start_dump_boot(struct modem_ctl *mc) { - int err; struct link_device *ld = get_current_link(mc->bootd); + struct mem_link_device *mld = to_mem_link_device(ld); + int err = 0; mif_err("+++\n"); @@ -992,31 +1313,52 @@ static int start_dump_boot(struct modem_ctl *mc) mif_err("%s: link_start_dump_boot is null\n", ld->name); return -EFAULT; } + err = ld->link_start_dump_boot(ld, mc->bootd); if (err) return err; - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); + /* do not handle cp2ap_wakeup irq during dump process */ + mif_disable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); + + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE) { + register_pcie(ld); + if (mc->s51xx_pdev && mc->pcie_registered) + set_cp_rom_boot_img(mld); + + err = check_cp_status(mc, 200, true); + if (err < 0) + goto status_error; + + s5100_poweroff_pcie(mc, false); - err = check_cp_status(mc, 200); + err = check_cp_status(mc, 200, false); + if (err < 0) + goto status_error; + + s5100_poweron_pcie(mc, false); + } else { + err = check_cp_status(mc, 200, false); + if (err < 0) + goto status_error; + + register_pcie(ld); + } + +status_error: if (err < 0) { mif_err("ERR! check_cp_status fail (err %d)\n", err); + if (mld->attrs & LINK_ATTR_XMIT_BTDLR_PCIE) + debug_cp_rom_boot_img(mld); return err; } - /* do not handle cp2ap_wakeup irq during dump process */ - mif_disable_irq(&mc->s5100_irq_ap_wakeup); - - if (ld->register_pcie) { - mif_info("register_pcie\n"); - ld->register_pcie(ld); - } - mif_err("---\n"); return err; } -int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) +static int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) { struct link_device *ld = get_current_link(mc->iod); struct mem_link_device *mld = to_mem_link_device(ld); @@ -1030,7 +1372,7 @@ int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) if (!mc->pcie_powered_on && (s51xx_check_pcie_link_status(mc->pcie_ch_num) == 0)) { - mif_err("skip pci power off : already powered off\n"); + mif_info("Skip pci power off: already powered off\n"); goto exit; } @@ -1043,19 +1385,16 @@ int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) spin_unlock_irqrestore(&mc->pcie_tx_lock, flags); msleep(30); if (check_mem_link_tx_pending(mld) || - mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, true) == 1) { - mif_err("skip pci power off : condition not met\n"); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], true) == 1) { + mif_info("Skip pci power off: condition not met\n"); goto exit; } } - if (mld->msi_irq_base_enabled == 1) { - disable_irq(mld->msi_irq_base); - mld->msi_irq_base_enabled = 0; - } + set_pcie_msi_int(ld, false); if (mc->device_reboot) { - mif_err("skip pci power off : device is rebooting..!!!\n"); + mif_info("Skip pci power off: device is rebooting\n"); goto exit; } @@ -1065,6 +1404,11 @@ int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) mc->pcie_cto_retry_cnt = 0; } + if (exynos_pcie_rc_get_cpl_timeout_state(mc->pcie_ch_num)) { + exynos_pcie_rc_set_cpl_timeout_state(mc->pcie_ch_num, false); + in_pcie_recovery = true; + } + mc->pcie_powered_on = false; if (mc->s51xx_pdev != NULL && (mc->phone_state == STATE_ONLINE || @@ -1076,7 +1420,7 @@ int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) mif_debug("ignore save_s5100_status - phone_state:%d\n", mc->phone_state); - mif_gpio_set_value(&mc->s5100_gpio_cp_wakeup, 0, 5); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP], 0, 5); print_mc_state(mc); exynos_pcie_poweroff(mc->pcie_ch_num); @@ -1111,20 +1455,15 @@ int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off) return 0; } -int s5100_poweron_pcie(struct modem_ctl *mc) +int s5100_poweron_pcie(struct modem_ctl *mc, bool boot_on) { struct link_device *ld; struct mem_link_device *mld; bool force_crash = false; unsigned long flags; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_S2MPU) - int ret; - u32 cp_num; - u32 shmem_idx; -#endif if (mc == NULL) { - mif_info("Skip pci power on : mc is NULL\n"); + mif_err("Skip pci power on: mc is NULL\n"); return 0; } @@ -1132,7 +1471,7 @@ int s5100_poweron_pcie(struct modem_ctl *mc) mld = to_mem_link_device(ld); if (mc->phone_state == STATE_OFFLINE) { - mif_info("Skip pci power on : phone_state is OFFLINE\n"); + mif_info("Skip pci power on: phone_state is OFFLINE\n"); return 0; } @@ -1141,57 +1480,40 @@ int s5100_poweron_pcie(struct modem_ctl *mc) mif_debug("+++\n"); if (mc->pcie_powered_on && (s51xx_check_pcie_link_status(mc->pcie_ch_num) != 0)) { - mif_err("skip pci power on : already powered on\n"); + mif_info("Skip pci power on: already powered on\n"); goto exit; } - if (mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, true) == 0) { - mif_err("skip pci power on : condition not met\n"); + if (!boot_on && + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], true) == 0) { + mif_info("Skip pci power on: condition not met\n"); goto exit; } if (mc->device_reboot) { - mif_err("skip pci power on : device is rebooting..!!!\n"); + mif_info("Skip pci power on: device is rebooting\n"); goto exit; } if (!cpif_wake_lock_active(mc->ws)) cpif_wake_lock(mc->ws); - mif_gpio_set_value(&mc->s5100_gpio_cp_wakeup, 1, 5); + if (!boot_on) + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP], 1, 5); print_mc_state(mc); spin_lock_irqsave(&mc->pcie_tx_lock, flags); /* wait Tx done if it is running */ spin_unlock_irqrestore(&mc->pcie_tx_lock, flags); - if (exynos_pcie_poweron(mc->pcie_ch_num) != 0) + if (exynos_pcie_rc_get_cpl_timeout_state(mc->pcie_ch_num)) + exynos_pcie_set_ready_cto_recovery(mc->pcie_ch_num); + + if (exynos_pcie_poweron(mc->pcie_ch_num, (boot_on ? 1 : 3)) != 0) goto exit; mc->pcie_powered_on = true; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_S2MPU) - if (!mc->s5100_s2mpu_enabled) { - mc->s5100_s2mpu_enabled = true; - cp_num = ld->mdm_data->cp_num; - - for (shmem_idx = 0 ; shmem_idx < MAX_CP_SHMEM ; shmem_idx++) { - if (shmem_idx == SHMEM_MSI) - continue; - - if (cp_shmem_get_base(cp_num, shmem_idx)) { - ret = (int) exynos_set_dev_stage2_ap("hsi2", 0, - cp_shmem_get_base(cp_num, shmem_idx), - cp_shmem_get_size(cp_num, shmem_idx), ATTR_RW); - mif_info("pcie s2mpu idx:%d - addr:0x%08lx size:0x%08x ret:%d\n", - shmem_idx, - cp_shmem_get_base(cp_num, shmem_idx), - cp_shmem_get_size(cp_num, shmem_idx), ret); - } - } - } -#endif - if (mc->s51xx_pdev != NULL) { s51xx_pcie_restore_state(mc->s51xx_pdev); @@ -1201,15 +1523,13 @@ int s5100_poweron_pcie(struct modem_ctl *mc) mif_err("DBG: MSI sfr not set up, yet(s5100_pdev is NULL)"); } - if (mld->msi_irq_base_enabled == 0) { - enable_irq(mld->msi_irq_base); - mld->msi_irq_base_enabled = 1; - } + set_pcie_msi_int(ld, true); if ((mc->s51xx_pdev != NULL) && mc->pcie_registered) { /* DBG */ mif_info("DBG: doorbell: pcie_registered = %d\n", mc->pcie_registered); - if (s51xx_pcie_send_doorbell_int(mc->s51xx_pdev, mc->int_pcie_link_ack) != 0) { + if (s51xx_pcie_send_doorbell_int(mc->s51xx_pdev, + mld->intval_ap2cp_pcie_link_ack) != 0) { /* DBG */ mif_err("DBG: s5100pcie_send_doorbell_int() func. is failed !!!\n"); s5100_force_crash_exit_ext(); @@ -1246,6 +1566,30 @@ int s5100_poweron_pcie(struct modem_ctl *mc) return 0; } +void s5100_set_pcie_irq_affinity(struct modem_ctl *mc) +{ + struct link_device *ld = get_current_link(mc->iod); + struct mem_link_device *mld = to_mem_link_device(ld); +#if IS_ENABLED(CONFIG_CP_PKTPROC) + struct pktproc_adaptor *ppa = &mld->pktproc; + unsigned int num_queue = 1; + unsigned int i; + + if (ppa->use_exclusive_irq) + num_queue = ppa->num_queue; + + for (i = 0; i < num_queue; i++) { + if (!ppa->q[i]->irq) + break; + + irq_set_affinity_hint(ppa->q[i]->irq, cpumask_of(mld->msi_irq_q_cpu[i])); + } +#endif + + if (mld->msi_irq_base) + irq_set_affinity_hint(mld->msi_irq_base, cpumask_of(mld->msi_irq_base_cpu)); +} + int s5100_set_outbound_atu(struct modem_ctl *mc, struct cp_btl *btl, loff_t *pos, u32 map_size) { int ret = 0; @@ -1271,16 +1615,16 @@ static int suspend_cp(struct modem_ctl *mc) break; #endif - if (mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, true) == 1) { - mif_err("abort suspend"); + if (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], true) == 1) { + mif_err("abort suspend\n"); return -EBUSY; } } while (0); #if !IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) modem_ctrl_set_kerneltime(mc); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 0, 0); - mif_gpio_get_value(&mc->s5100_gpio_ap_status, true); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 0, 0); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], true); #endif return 0; @@ -1294,6 +1638,8 @@ static int resume_cp(struct modem_ctl *mc) if (!mc) return 0; + s5100_set_pcie_irq_affinity(mc); + #if IS_ENABLED(CONFIG_GS_S2MPU) if (!mc->s2mpu) @@ -1308,9 +1654,10 @@ static int resume_cp(struct modem_ctl *mc) #if !IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) modem_ctrl_set_kerneltime(mc); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); - mif_gpio_get_value(&mc->s5100_gpio_ap_status, true); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], true); #endif + return 0; } @@ -1343,9 +1690,9 @@ static int s5100_pm_notifier(struct notifier_block *notifier, mif_err("cp2ap_wakeup work resume. gpio_val : %d\n", gpio_val); mc->apwake_irq_chip->irq_set_type( - irq_get_irq_data(mc->s5100_irq_ap_wakeup.num), + irq_get_irq_data(mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num), (gpio_val == 1 ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH)); - mif_enable_irq(&mc->s5100_irq_ap_wakeup); + mif_enable_irq(&mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP]); queue_work_on(RUNTIME_PM_AFFINITY_CORE, mc->wakeup_wq, (gpio_val == 1 ? &mc->wakeup_work : &mc->suspend_work)); @@ -1362,10 +1709,10 @@ static int s5100_pm_notifier(struct notifier_block *notifier, int s5100_try_gpio_cp_wakeup(struct modem_ctl *mc) { - if ((mif_gpio_get_value(&mc->s5100_gpio_cp_wakeup, false) == 0) && - (mif_gpio_get_value(&mc->s5100_gpio_ap_wakeup, false) == 0) && - (s51xx_check_pcie_link_status(mc->pcie_ch_num) == 0)) { - mif_gpio_set_value(&mc->s5100_gpio_cp_wakeup, 1, 0); + if ((mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP], false) == 0) && + (mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP], false) == 0) && + (s51xx_check_pcie_link_status(mc->pcie_ch_num) == 0)) { + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP], 1, 0); return 0; } return -EPERM; @@ -1389,115 +1736,90 @@ static void s5100_get_ops(struct modem_ctl *mc) mc->ops.resume = resume_cp; } -static void s5100_get_pdata(struct modem_ctl *mc, struct modem_data *pdata) +static int s5100_get_pdata(struct modem_ctl *mc, struct modem_data *pdata) { struct platform_device *pdev = to_platform_device(mc->dev); struct device_node *np = pdev->dev.of_node; - int ret = 0; - - /* CP Power */ - mc->s5100_gpio_cp_pwr.num = of_get_named_gpio(np, "gpio_ap2cp_cp_pwr_on", 0); - if (mc->s5100_gpio_cp_pwr.num < 0) { - mif_err("Can't Get s5100_gpio_cp_pwr!\n"); - return; - } - mc->s5100_gpio_cp_pwr.label = "AP2CP_CP_PWR_ON"; - gpio_request(mc->s5100_gpio_cp_pwr.num, mc->s5100_gpio_cp_pwr.label); - gpio_direction_output(mc->s5100_gpio_cp_pwr.num, 0); + unsigned int i; + + /* label */ + mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR].label = "AP2CP_CP_PWR"; + mc->cp_gpio[CP_GPIO_AP2CP_NRESET].label = "AP2CP_NRESET"; + mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP].label = "AP2CP_WAKEUP"; + mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI].label = "AP2CP_DUMP_NOTI"; + mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE].label = "AP2CP_AP_ACTIVE"; +#if !IS_ENABLED(CONFIG_CP_WRESET_WA) + mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N].label = "AP2CP_CP_WRST_N"; + mc->cp_gpio[CP_GPIO_AP2CP_PM_WRST_N].label = "AP2CP_PM_WRST_N"; +#endif + mc->cp_gpio[CP_GPIO_CP2AP_PS_HOLD].label = "CP2AP_PS_HOLD"; + mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP].label = "CP2AP_WAKEUP"; + mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE].label = "CP2AP_CP_ACTIVE"; + + /* node name */ + mc->cp_gpio[CP_GPIO_AP2CP_CP_PWR].node_name = "gpio_ap2cp_cp_pwr_on"; + mc->cp_gpio[CP_GPIO_AP2CP_NRESET].node_name = "gpio_ap2cp_nreset_n"; + mc->cp_gpio[CP_GPIO_AP2CP_WAKEUP].node_name = "gpio_ap2cp_wake_up"; + mc->cp_gpio[CP_GPIO_AP2CP_DUMP_NOTI].node_name = "gpio_ap2cp_dump_noti"; + mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE].node_name = "gpio_ap2cp_pda_active"; +#if !IS_ENABLED(CONFIG_CP_WRESET_WA) + mc->cp_gpio[CP_GPIO_AP2CP_CP_WRST_N].node_name = "gpio_ap2cp_cp_wrst_n"; + mc->cp_gpio[CP_GPIO_AP2CP_PM_WRST_N].node_name = "gpio_ap2cp_pm_wrst_n"; +#endif + mc->cp_gpio[CP_GPIO_CP2AP_PS_HOLD].node_name = "gpio_cp2ap_cp_ps_hold"; + mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP].node_name = "gpio_cp2ap_wake_up"; + mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE].node_name = "gpio_cp2ap_phone_active"; - /* CP Reset */ - mc->s5100_gpio_cp_reset.num = of_get_named_gpio(np, "gpio_ap2cp_nreset_n", 0); - if (mc->s5100_gpio_cp_reset.num < 0) { - mif_err("Can't Get gpio_cp_nreset_n!\n"); - return; - } - mc->s5100_gpio_cp_reset.label = "AP2CP_NRESET_N"; - gpio_request(mc->s5100_gpio_cp_reset.num, mc->s5100_gpio_cp_reset.label); - gpio_direction_output(mc->s5100_gpio_cp_reset.num, 0); + /* irq */ + mc->cp_gpio[CP_GPIO_CP2AP_WAKEUP].irq_type = CP_GPIO_IRQ_CP2AP_WAKEUP; + mc->cp_gpio[CP_GPIO_CP2AP_CP_ACTIVE].irq_type = CP_GPIO_IRQ_CP2AP_CP_ACTIVE; - /* CP PS HOLD */ - mc->s5100_gpio_cp_ps_hold.num = of_get_named_gpio(np, "gpio_cp2ap_cp_ps_hold", 0); - if (mc->s5100_gpio_cp_ps_hold.num < 0) { - mif_err("Can't Get s5100_gpio_cp_ps_hold!\n"); - return; - } - mc->s5100_gpio_cp_ps_hold.label = "CP2AP_CP_PS_HOLD"; - gpio_request(mc->s5100_gpio_cp_ps_hold.num, mc->s5100_gpio_cp_ps_hold.label); - gpio_direction_input(mc->s5100_gpio_cp_ps_hold.num); + /* gpio */ + for (i = 0; i < CP_GPIO_MAX; i++) { + mc->cp_gpio[i].num = + of_get_named_gpio(np, mc->cp_gpio[i].node_name, 0); - /* AP2CP WAKE UP */ - mc->s5100_gpio_cp_wakeup.num = of_get_named_gpio(np, "gpio_ap2cp_wake_up", 0); - if (mc->s5100_gpio_cp_wakeup.num < 0) { - mif_err("Can't Get s5100_gpio_cp_wakeup!\n"); - return; - } - mc->s5100_gpio_cp_wakeup.label = "AP2CP_WAKE_UP"; - gpio_request(mc->s5100_gpio_cp_wakeup.num, mc->s5100_gpio_cp_wakeup.label); - gpio_direction_output(mc->s5100_gpio_cp_wakeup.num, 0); + if (!gpio_is_valid(mc->cp_gpio[i].num)) + continue; - /* CP2AP WAKE UP */ - mc->s5100_gpio_ap_wakeup.num = of_get_named_gpio(np, "gpio_cp2ap_wake_up", 0); - if (mc->s5100_gpio_ap_wakeup.num < 0) { - mif_err("Can't Get gpio_cp2ap_wake_up!\n"); - return; - } - mc->s5100_gpio_ap_wakeup.label = "CP2AP_WAKE_UP"; - gpio_request(mc->s5100_gpio_ap_wakeup.num, mc->s5100_gpio_ap_wakeup.label); - mc->s5100_irq_ap_wakeup.num = gpio_to_irq(mc->s5100_gpio_ap_wakeup.num); + mc->cp_gpio[i].valid = true; - /* DUMP NOTI */ - mc->s5100_gpio_cp_dump_noti.num = of_get_named_gpio(np, "gpio_ap2cp_dump_noti", 0); - if (mc->s5100_gpio_cp_dump_noti.num < 0) { - mif_err("Can't Get gpio_ap2cp_dump_noti!\n"); - return; - } - mc->s5100_gpio_cp_dump_noti.label = "AP2CP_DUMP_NOTI"; - gpio_request(mc->s5100_gpio_cp_dump_noti.num, mc->s5100_gpio_cp_dump_noti.label); - gpio_direction_output(mc->s5100_gpio_cp_dump_noti.num, 0); + gpio_request(mc->cp_gpio[i].num, mc->cp_gpio[i].label); + if (!strncmp(mc->cp_gpio[i].label, "AP2CP", 5)) + gpio_direction_output(mc->cp_gpio[i].num, 0); + else + gpio_direction_input(mc->cp_gpio[i].num); - /* PDA ACTIVE */ - mc->s5100_gpio_ap_status.num = of_get_named_gpio(np, "gpio_ap2cp_pda_active", 0); - if (mc->s5100_gpio_ap_status.num < 0) { - mif_err("Can't Get s5100_gpio_ap_status!\n"); - return; - } - mc->s5100_gpio_ap_status.label = "AP2CP_PDA_ACTIVE"; - gpio_request(mc->s5100_gpio_ap_status.num, mc->s5100_gpio_ap_status.label); - gpio_direction_output(mc->s5100_gpio_ap_status.num, 0); + if (mc->cp_gpio[i].irq_type != CP_GPIO_IRQ_NONE) { + mc->cp_gpio_irq[mc->cp_gpio[i].irq_type].num = + gpio_to_irq(mc->cp_gpio[i].num); - /* PHONE ACTIVE */ - mc->s5100_gpio_phone_active.num = of_get_named_gpio(np, "gpio_cp2ap_phone_active", 0); - if (mc->s5100_gpio_phone_active.num < 0) { - mif_err("Can't Get s5100_gpio_phone_active!\n"); - return; + if (i == CP_GPIO_CP2AP_CP_ACTIVE) { + mc->cp_gpio_irq[mc->cp_gpio[i].irq_type].not_alive = + pdata->cp2ap_active_not_alive; + } + } } - mc->s5100_gpio_phone_active.label = "CP2AP_PHONE_ACTIVE"; - gpio_request(mc->s5100_gpio_phone_active.num, mc->s5100_gpio_phone_active.label); - mc->s5100_irq_phone_active.num = gpio_to_irq(mc->s5100_gpio_phone_active.num); - mc->s5100_irq_phone_active.not_alive = pdata->cp2ap_active_not_alive; - ret = of_property_read_u32(np, "mif,int_ap2cp_pcie_link_ack", - &mc->int_pcie_link_ack); - if (ret) { - mif_err("Can't Get PCIe Link ACK interrupt number!!!\n"); - return; + /* validate */ + for (i = 0; i < CP_GPIO_MAX; i++) { + if (!mc->cp_gpio[i].valid) { + mif_err("Missing some of GPIOs\n"); + return -EINVAL; + } } - mc->int_pcie_link_ack += DOORBELL_INT_ADD; /* Get PCIe Channel Number */ - ret = of_property_read_u32(np, "pci_ch_num", - &mc->pcie_ch_num); - if (ret) { - mif_err("Can't Get PCIe channel!!!\n"); - return; - } - mif_info("S5100 PCIe Channel Number : %d\n", mc->pcie_ch_num); + mif_dt_read_u32(np, "pci_ch_num", mc->pcie_ch_num); + mif_info("PCIe Channel Number:%d\n", mc->pcie_ch_num); mc->sbi_crash_type_mask = pdata->sbi_crash_type_mask; mc->sbi_crash_type_pos = pdata->sbi_crash_type_pos; mc->sbi_ds_det_mask = pdata->sbi_ds_det_mask; mc->sbi_ds_det_pos = pdata->sbi_ds_det_pos; + + return 0; } static int send_panic_to_cp_notifier(struct notifier_block *nb, @@ -1510,26 +1832,6 @@ static int send_panic_to_cp_notifier(struct notifier_block *nb, return NOTIFY_DONE; } -#if IS_ENABLED(CONFIG_EXYNOS_BUSMONITOR) -static int s5100_busmon_notifier(struct notifier_block *nb, - unsigned long event, void *data) -{ - struct busmon_notifier *info = (struct busmon_notifier *)data; - char *init_desc = info->init_desc; - - if (init_desc != NULL && - (strncmp(init_desc, "CP", strlen(init_desc)) == 0 || - strncmp(init_desc, "APB_CORE_CP", strlen(init_desc)) == 0 || - strncmp(init_desc, "MIF_CP", strlen(init_desc)) == 0)) { - struct modem_ctl *mc = - container_of(nb, struct modem_ctl, busmon_nfb); - - mc->ops.trigger_cp_crash(mc); - } - return 0; -} -#endif - #if IS_ENABLED(CONFIG_SUSPEND_DURING_VOICE_CALL) static int s5100_call_state_notifier(struct notifier_block *nb, unsigned long action, void *nb_data) @@ -1568,15 +1870,15 @@ static int s5100_lcd_notifier(struct notifier_block *notifier, case LCD_OFF: mif_info("LCD_OFF Notification\n"); modem_ctrl_set_kerneltime(mc); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 0, 0); - mif_gpio_get_value(&mc->s5100_gpio_ap_status, true); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 0, 0); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], true); break; case LCD_ON: mif_info("LCD_ON Notification\n"); modem_ctrl_set_kerneltime(mc); - mif_gpio_set_value(&mc->s5100_gpio_ap_status, 1, 0); - mif_gpio_get_value(&mc->s5100_gpio_ap_status, true); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], 1, 0); + mif_gpio_get_value(&mc->cp_gpio[CP_GPIO_AP2CP_AP_ACTIVE], true); break; default: @@ -1592,12 +1894,14 @@ int s5100_init_modemctl_device(struct modem_ctl *mc, struct modem_data *pdata) { int ret = 0; struct platform_device *pdev = to_platform_device(mc->dev); - struct resource __maybe_unused *sysram_alive; g_mc = mc; s5100_get_ops(mc); - s5100_get_pdata(mc, pdata); + if (s5100_get_pdata(mc, pdata)) { + mif_err("DT error: failed to parse\n"); + return -EINVAL; + } dev_set_drvdata(mc->dev, mc); mc->ws = cpif_wake_lock_register(&pdev->dev, "s5100_wake_lock"); @@ -1614,10 +1918,10 @@ int s5100_init_modemctl_device(struct modem_ctl *mc, struct modem_data *pdata) atomic_set(&mc->dump_toggle_issued, 0); #endif - mif_gpio_set_value(&mc->s5100_gpio_cp_reset, 0, 0); + mif_gpio_set_value(&mc->cp_gpio[CP_GPIO_AP2CP_NRESET], 0, 0); - mif_err("Register GPIO interrupts\n"); - mc->apwake_irq_chip = irq_get_chip(mc->s5100_irq_ap_wakeup.num); + mif_info("Register GPIO interrupts\n"); + mc->apwake_irq_chip = irq_get_chip(mc->cp_gpio_irq[CP_GPIO_IRQ_CP2AP_WAKEUP].num); if (mc->apwake_irq_chip == NULL) { mif_err("Can't get irq_chip structure!!!!\n"); return -EINVAL; diff --git a/drivers/soc/google/cpif/modem_debug.h b/drivers/soc/google/cpif/modem_debug.h deleted file mode 100644 index f6575322cd16..000000000000 --- a/drivers/soc/google/cpif/modem_debug.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MODEM_DEBUG_H__ -#define __MODEM_DEBUG_H__ - -#include -#include -#include - -enum modemctl_event { - MDM_EVENT_CP_FORCE_RESET, - MDM_EVENT_CP_FORCE_CRASH, - MDM_EVENT_CP_ABNORMAL_RX, - MDM_CRASH_PM_FAIL, - MDM_CRASH_PM_CP_FAIL, - MDM_CRASH_INVALID_RB, - MDM_CRASH_INVALID_IOD, - MDM_CRASH_INVALID_SKBCB, - MDM_CRASH_INVALID_SKBIOD, - MDM_CRASH_NO_MEM, - MDM_CRASH_CMD_RESET = 90, - MDM_CRASH_CMD_EXIT, -}; - -int register_cp_crash_notifier(struct notifier_block *nb); -void modemctl_notify_event(enum modemctl_event evt); - -#endif diff --git a/drivers/soc/google/cpif/modem_dump.c b/drivers/soc/google/cpif/modem_dump.c index e16b6f1a8226..4ee3eca78038 100644 --- a/drivers/soc/google/cpif/modem_dump.c +++ b/drivers/soc/google/cpif/modem_dump.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "modem_prj.h" #include "modem_utils.h" @@ -70,6 +70,7 @@ static int save_log_dump(struct io_device *iod, struct link_device *ld, u8 __iom int cp_get_log_dump(struct io_device *iod, struct link_device *ld, unsigned long arg) { struct mem_link_device *mld = to_mem_link_device(ld); + struct modem_data *modem = ld->mdm_data; void __user *uarg = (void __user *)arg; struct cp_log_dump log_dump; u8 __iomem *base = NULL; @@ -88,13 +89,14 @@ int cp_get_log_dump(struct io_device *iod, struct link_device *ld, unsigned long cp_num = ld->mdm_data->cp_num; switch (log_dump.idx) { case LOG_IDX_SHMEM: -#if IS_ENABLED(CONFIG_CACHED_LEGACY_RAW_RX_BUFFER) - base = phys_to_virt(cp_shmem_get_base(cp_num, SHMEM_IPC)); - size = cp_shmem_get_size(cp_num, SHMEM_IPC); -#else - base = mld->base; - size = mld->size; -#endif + if (modem->legacy_raw_rx_buffer_cached) { + base = phys_to_virt(cp_shmem_get_base(cp_num, SHMEM_IPC)); + size = cp_shmem_get_size(cp_num, SHMEM_IPC); + } else { + base = mld->base; + size = mld->size; + } + break; case LOG_IDX_VSS: @@ -120,7 +122,11 @@ int cp_get_log_dump(struct io_device *iod, struct link_device *ld, unsigned long case LOG_IDX_DATABUF_DL: base = phys_to_virt(cp_shmem_get_base(cp_num, SHMEM_PKTPROC)); +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_IOMMU) + size = mld->pktproc.buff_rgn_offset; +#else size = cp_shmem_get_size(cp_num, SHMEM_PKTPROC); +#endif break; #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) @@ -135,6 +141,11 @@ int cp_get_log_dump(struct io_device *iod, struct link_device *ld, unsigned long size = cp_shmem_get_size(cp_num, SHMEM_L2B); break; + case LOG_IDX_DDM: + base = phys_to_virt(cp_shmem_get_base(cp_num, SHMEM_DDM)); + size = cp_shmem_get_size(cp_num, SHMEM_DDM); + break; + default: mif_err("%s: invalid index:%d\n", iod->name, log_dump.idx); return -EINVAL; diff --git a/drivers/soc/google/cpif/modem_io_device.c b/drivers/soc/google/cpif/modem_io_device.c index d161e6cce4f4..768faf226264 100644 --- a/drivers/soc/google/cpif/modem_io_device.c +++ b/drivers/soc/google/cpif/modem_io_device.c @@ -25,6 +25,7 @@ #include "modem_prj.h" #include "modem_utils.h" #include "modem_dump.h" +#include "modem_toe_device.h" static ssize_t waketime_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -61,22 +62,22 @@ static ssize_t waketime_store(struct device *dev, } iod->waketime = msecs_to_jiffies(msec); -#ifdef DEBUG_MODEM_IF - mif_err("%s: waketime = %lu ms\n", iod->name, msec); -#endif + mif_info("%s: waketime = %lu ms\n", iod->name, msec); if (iod->format == IPC_MULTI_RAW) { struct modem_shared *msd = iod->msd; unsigned int i; +#if IS_ENABLED(CONFIG_CH_EXTENSION) + for (i = SIPC_CH_EX_ID_PDP_0; i <= SIPC_CH_EX_ID_PDP_MAX; i++) { +#else for (i = SIPC_CH_ID_PDP_0; i < SIPC_CH_ID_BT_DUN; i++) { +#endif iod = get_iod_with_channel(msd, i); if (iod) { iod->waketime = msecs_to_jiffies(msec); -#ifdef DEBUG_MODEM_IF mif_err("%s: waketime = %lu ms\n", iod->name, msec); -#endif } } } @@ -147,12 +148,13 @@ static struct device_attribute attr_txlink = __ATTR_RW(txlink); enum gro_opt { - GRO_FULL_SUPPORT, + GRO_TCP_UDP, GRO_TCP_ONLY, GRO_NONE, MAX_GRO_OPTION }; -static enum gro_opt gro_support = GRO_FULL_SUPPORT; + +static enum gro_opt gro_support = GRO_TCP_UDP; static ssize_t gro_option_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -213,7 +215,6 @@ static int gather_multi_frame(struct sipc5_link_header *hdr, struct sk_buff_head *multi_q = &iod->sk_multi_q[ctrl.id]; int len = skb->len; -#ifdef DEBUG_MODEM_IF /* If there has been no multiple frame with this ID, ... */ if (skb_queue_empty(multi_q)) { struct sipc_fmt_hdr *fh = (struct sipc_fmt_hdr *)skb->data; @@ -221,7 +222,6 @@ static int gather_multi_frame(struct sipc5_link_header *hdr, mif_err("%s<-%s: start of multi-frame (ID:%d len:%d)\n", iod->name, mc->name, ctrl.id, fh->len); } -#endif skb_queue_tail(multi_q, skb); if (ctrl.more) { @@ -260,7 +260,7 @@ static int gather_multi_frame_sit(struct exynos_link_header *hdr, struct sk_buff #ifdef DEBUG_MODEM_IF_LINK_RX /* If there has been no multiple frame with this ID, ... */ if (skb_queue_empty(multi_q)) { - mif_err("%s<-%s: start of multi-frame (pkt_index:%d fr_index:%d len:%d)\n", + mif_debug("%s<-%s: start of multi-frame (pkt_index:%d fr_index:%d len:%d)\n", iod->name, mc->name, exynos_multi_packet_index(ctrl), exynos_multi_frame_index(ctrl), hdr->len); } @@ -269,21 +269,21 @@ static int gather_multi_frame_sit(struct exynos_link_header *hdr, struct sk_buff /* The last frame has not arrived yet. */ if (!exynos_multi_last(ctrl)) { - mif_err("%s<-%s: recv of multi-frame (CH_ID:0x%02x rcvd:%d)\n", + mif_debug("%s<-%s: recv of multi-frame (CH_ID:0x%02x rcvd:%d)\n", iod->name, mc->name, hdr->ch_id, skb->len); return ret; } /* It is the last frame because the "more" bit is 0. */ - mif_err("%s<-%s: end multi-frame (CH_ID:0x%02x rcvd:%d)\n", + mif_debug("%s<-%s: end multi-frame (CH_ID:0x%02x rcvd:%d)\n", iod->name, mc->name, hdr->ch_id, skb->len); /* check totoal multi packet size */ skb_queue_walk(multi_q, skb_cur) total_len += skb_cur->len; - mif_info("Total multi-frame packet size is %d\n", total_len); + mif_debug("Total multi-frame packet size is %d\n", total_len); skb_new = dev_alloc_skb(total_len); if (unlikely(!skb_new)) { @@ -369,27 +369,34 @@ static int rx_raw_misc(struct sk_buff *skb) return queue_skb_to_iod(skb, iod); } -static int check_gro_support(struct sk_buff *skb) +static bool check_gro_support(struct sk_buff *skb) { + u8 proto; if (gro_support == GRO_NONE) - return 0; + return false; switch (skb->data[0] & 0xF0) { case 0x40: - return (gro_support == GRO_FULL_SUPPORT) ? - ((ip_hdr(skb)->protocol == IPPROTO_TCP) || - (ip_hdr(skb)->protocol == IPPROTO_UDP)) : - (ip_hdr(skb)->protocol == IPPROTO_TCP); - + proto = ip_hdr(skb)->protocol; + break; case 0x60: - return (gro_support == GRO_FULL_SUPPORT) ? - ((ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP) || - (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP)) : - (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); + proto = ipv6_hdr(skb)->nexthdr; + break; + default: + return false; } - return 0; + switch (gro_support) { + case GRO_TCP_UDP: + return proto == IPPROTO_TCP || proto == IPPROTO_UDP; + case GRO_TCP_ONLY: + return proto == IPPROTO_TCP; + default: + break; + } + + return false; } static int rx_multi_pdp(struct sk_buff *skb) @@ -403,7 +410,7 @@ static int rx_multi_pdp(struct sk_buff *skb) skb->dev = (skbpriv(skb)->rx_clat ? iod->clat_ndev : iod->ndev); if (!skb->dev || !iod->ndev) { - mif_info("%s: ERR! no iod->ndev\n", iod->name); + mif_err("%s: ERR! no iod->ndev\n", iod->name); return -ENODEV; } @@ -464,7 +471,11 @@ static int rx_demux(struct link_device *ld, struct sk_buff *skb) /* IP loopback */ if (ch == DATA_LOOPBACK_CHANNEL && ld->msd->loopback_ipaddr) +#if IS_ENABLED(CONFIG_CH_EXTENSION) + ch = SIPC_CH_EX_ID_PDP_0; +#else ch = SIPC_CH_ID_PDP_0; +#endif iod = link_get_iod_with_channel(ld, ch); if (unlikely(!iod)) { @@ -480,19 +491,15 @@ static int rx_demux(struct link_device *ld, struct sk_buff *skb) switch (skb_ld->protocol) { case PROTOCOL_SIPC: - if (skb_ld->is_fmt_ch(ch)) { - iod->mc->receive_first_ipc = 1; + if (skb_ld->is_fmt_ch(ch)) return rx_fmt_ipc(skb); - } else if (skb_ld->is_ps_ch(ch)) + else if (skb_ld->is_ps_ch(ch)) return rx_multi_pdp(skb); else return rx_raw_misc(skb); break; case PROTOCOL_SIT: - if (skb_ld->is_fmt_ch(ch) || skb_ld->is_oem_ch(ch)) { - iod->mc->receive_first_ipc = 1; - return rx_fmt_ipc(skb); - } else if (skb_ld->is_wfs0_ch(ch)) + if (skb_ld->is_fmt_ch(ch) || skb_ld->is_oem_ch(ch) || skb_ld->is_wfs0_ch(ch)) return rx_fmt_ipc(skb); else if (skb_ld->is_ps_ch(ch) || skb_ld->is_embms_ch(ch)) return rx_multi_pdp(skb); @@ -548,31 +555,6 @@ static int io_dev_recv_net_skb_from_link_dev(struct io_device *iod, return rx_multi_pdp(skb); } -static void io_dev_sim_state_changed(struct io_device *iod, bool sim_online) -{ - if (atomic_read(&iod->opened) == 0) { - mif_info("%s: ERR! not opened\n", iod->name); - } else if (iod->mc->sim_state.online == sim_online) { - mif_info("%s: SIM state not changed\n", iod->name); - } else { - iod->mc->sim_state.online = sim_online; - iod->mc->sim_state.changed = true; - mif_info("%s: SIM state changed {online %d, changed %d}\n", - iod->name, iod->mc->sim_state.online, - iod->mc->sim_state.changed); - wake_up(&iod->wq); - } -} - -void iodev_dump_status(struct io_device *iod, void *args) -{ - if (iod->format == IPC_RAW && iod->io_typ == IODEV_NET) { - struct link_device *ld = get_current_link(iod); - - mif_com_log(iod->mc->msd, "%s: %s\n", iod->name, ld->name); - } -} - u16 exynos_build_fr_config(struct io_device *iod, struct link_device *ld, unsigned int count) { @@ -698,7 +680,8 @@ static int cpif_cdev_create_device(struct io_device *iod, const struct file_oper } idx++; - iod->cdevice = device_create(iod->msd->cdev_class, NULL, iod->cdev.dev, iod, iod->name); + iod->cdevice = device_create(iod->msd->cdev_class, NULL, iod->cdev.dev, iod, + "%s", iod->name); if (IS_ERR_OR_NULL(iod->cdevice)) { mif_err("device_create() for %s failed\n", iod->name); ret = -ENOMEM; @@ -709,11 +692,12 @@ static int cpif_cdev_create_device(struct io_device *iod, const struct file_oper return ret; } -int sipc5_init_io_device(struct io_device *iod) +int sipc5_init_io_device(struct io_device *iod, struct mem_link_device *mld) { int ret = 0; int i; struct vnet *vnet; + unsigned int txqs = 1, rxqs = 1; if (iod->attrs & IO_ATTR_SBD_IPC) iod->sbd_ipc = true; @@ -723,8 +707,6 @@ int sipc5_init_io_device(struct io_device *iod) else iod->link_header = true; - iod->sim_state_changed = io_dev_sim_state_changed; - /* Get data from link device */ iod->recv_skb_single = io_dev_recv_skb_single_from_link_dev; iod->recv_net_skb = io_dev_recv_net_skb_from_link_dev; @@ -770,12 +752,18 @@ int sipc5_init_io_device(struct io_device *iod) break; case IODEV_NET: +#if IS_ENABLED(CONFIG_MODEM_IF_QOS) + txqs = 2; +#endif +#if IS_ENABLED(CONFIG_CP_PKTPROC) + rxqs = mld->pktproc.num_queue; +#endif skb_queue_head_init(&iod->sk_rx_q); INIT_LIST_HEAD(&iod->node_ndev); iod->ndev = alloc_netdev_mqs(sizeof(struct vnet), iod->name, NET_NAME_UNKNOWN, vnet_setup, - MAX_NDEV_TX_Q, MAX_NDEV_RX_Q); + txqs, rxqs); if (!iod->ndev) { mif_info("%s: ERR! alloc_netdev fail\n", iod->name); return -ENOMEM; @@ -876,4 +864,3 @@ void sipc5_deinit_io_device(struct io_device *iod) break; } } - diff --git a/drivers/soc/google/cpif/modem_main.c b/drivers/soc/google/cpif/modem_main.c index 220f71b2dfc2..cc9c64ceae80 100644 --- a/drivers/soc/google/cpif/modem_main.c +++ b/drivers/soc/google/cpif/modem_main.c @@ -25,9 +25,7 @@ #include #include #include -#if IS_ENABLED(CONFIG_OF) #include -#endif #include #include #include @@ -37,14 +35,15 @@ #include #if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) -#include -#include +#include +#include #endif #include #include "modem_prj.h" #include "modem_variation.h" #include "modem_utils.h" +#include "modem_toe_device.h" #if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) #include "cpif_qos_info.h" @@ -113,7 +112,7 @@ static struct modem_ctl *create_modemctl_device(struct platform_device *pdev, modemctl->msd = msd; - modemctl->phone_state = STATE_INIT; + modemctl->phone_state = STATE_OFFLINE; INIT_LIST_HEAD(&modemctl->modem_state_notify_list); spin_lock_init(&modemctl->lock); @@ -151,7 +150,6 @@ static struct io_device *create_io_device(struct platform_device *pdev, } INIT_LIST_HEAD(&iod->list); - RB_CLEAR_NODE(&iod->node_chan); RB_CLEAR_NODE(&iod->node_fmt); iod->name = io_t->name; @@ -161,7 +159,6 @@ static struct io_device *create_io_device(struct platform_device *pdev, iod->link_type = io_t->link_type; iod->attrs = io_t->attrs; iod->max_tx_size = io_t->ul_buffer_size; - iod->net_typ = pdata->modem_net; iod->ipc_version = pdata->ipc_version; atomic_set(&iod->opened, 0); spin_lock_init(&iod->info_id_lock); @@ -186,7 +183,7 @@ static struct io_device *create_io_device(struct platform_device *pdev, if (iod->format == IPC_BOOT) { modemctl->bootd = iod; - mif_err("BOOT device = %s\n", iod->name); + mif_info("BOOT device = %s\n", iod->name); } /* link between io device and modem shared */ @@ -210,7 +207,7 @@ static struct io_device *create_io_device(struct platform_device *pdev, } /* register misc device or net device */ - ret = sipc5_init_io_device(iod); + ret = sipc5_init_io_device(iod, pdata->mld); if (ret) { devm_kfree(dev, iod); mif_err("sipc5_init_io_device fail (%d)\n", ret); @@ -231,6 +228,13 @@ static int attach_devices(struct io_device *iod, struct device *dev) if (IS_CONNECTED(iod, ld)) { mif_debug("set %s->%s\n", iod->name, ld->name); set_current_link(iod, ld); + + if (iod->io_typ == IODEV_NET && iod->ndev) { + struct vnet *vnet; + + vnet = netdev_priv(iod->ndev); + vnet->hiprio_ack_only = ld->hiprio_ack_only; + } } } @@ -254,7 +258,13 @@ static int attach_devices(struct io_device *iod, struct device *dev) iod->waketime = RAW_WAKE_TIME; break; +#if IS_ENABLED(CONFIG_CH_EXTENSION) + case SIPC_CH_EX_ID_PDP_0 ... SIPC_CH_EX_ID_PDP_MAX: + case SIPC_CH_ID_BT_DUN ... SIPC_CH_ID_CIQ_DATA: + case SIPC_CH_ID_CPLOG1 ... SIPC_CH_ID_LOOPBACK2: +#else case SIPC_CH_ID_PDP_0 ... SIPC_CH_ID_LOOPBACK2: +#endif iod->waketime = NET_WAKE_TIME; break; @@ -279,7 +289,6 @@ static int attach_devices(struct io_device *iod, struct device *dev) return 0; } -#if IS_ENABLED(CONFIG_OF) static int parse_dt_common_pdata(struct device_node *np, struct modem_data *pdata) { @@ -332,12 +341,21 @@ static int parse_dt_mbox_pdata(struct device *dev, struct device_node *np, #if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) mif_dt_read_u32(np, "mif,int_ap2cp_lcd_status", mbox->int_ap2cp_lcd_status); +#endif +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + mif_dt_read_u32(np, "mif,int_ap2cp_clatinfo_send", mbox->int_ap2cp_clatinfo_send); +#endif +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) + mif_dt_read_u32(np, "mif,int_ap2cp_pcie_link_ack", mbox->int_ap2cp_pcie_link_ack); #endif mif_dt_read_u32(np, "mif,int_ap2cp_uart_noti", mbox->int_ap2cp_uart_noti); mif_dt_read_u32(np, "mif,irq_cp2ap_msg", mbox->irq_cp2ap_msg); mif_dt_read_u32(np, "mif,irq_cp2ap_status", mbox->irq_cp2ap_status); mif_dt_read_u32(np, "mif,irq_cp2ap_active", mbox->irq_cp2ap_active); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + mif_dt_read_u32(np, "mif,irq_cp2ap_clatinfo_ack", mbox->irq_cp2ap_clatinfo_ack); +#endif mif_dt_read_u32(np, "mif,irq_cp2ap_wakelock", mbox->irq_cp2ap_wakelock); mif_dt_read_u32(np, "mif,irq_cp2ap_ratmode", mbox->irq_cp2ap_rat_mode); @@ -360,6 +378,8 @@ static int parse_dt_ipc_region_pdata(struct device *dev, struct device_node *np, mif_dt_read_u32(np, "legacy_raw_buffer_offset", pdata->legacy_raw_buffer_offset); mif_dt_read_u32(np, "legacy_raw_txq_size", pdata->legacy_raw_txq_size); mif_dt_read_u32(np, "legacy_raw_rxq_size", pdata->legacy_raw_rxq_size); + mif_dt_read_u32(np, "legacy_raw_rx_buffer_cached", + pdata->legacy_raw_rx_buffer_cached); mif_dt_read_u32_noerr(np, "offset_ap_version", pdata->offset_ap_version); mif_dt_read_u32_noerr(np, "offset_cp_version", pdata->offset_cp_version); @@ -391,14 +411,28 @@ static int parse_dt_ipc_region_pdata(struct device *dev, struct device_node *np, /* offset setting for capability */ if (pdata->capability_check) { mif_dt_read_u32(np, "capability_offset", pdata->capability_offset); - mif_dt_read_u32(np, "ap_capability_0", pdata->ap_capability_0); - mif_dt_read_u32(np, "ap_capability_1", pdata->ap_capability_1); + mif_dt_read_u32(np, "ap_capability_0", pdata->ap_capability[0]); + mif_dt_read_u32(np, "ap_capability_1", pdata->ap_capability[1]); } of_property_read_u32_array(np, "ap2cp_msg", pdata->ap2cp_msg, 2); of_property_read_u32_array(np, "cp2ap_msg", pdata->cp2ap_msg, 2); of_property_read_u32_array(np, "cp2ap_united_status", pdata->cp2ap_united_status, 2); of_property_read_u32_array(np, "ap2cp_united_status", pdata->ap2cp_united_status, 2); +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + mif_dt_count_u32_array(np, "ap2cp_clatinfo_xlat_v4_addr", + pdata->ap2cp_clatinfo_xlat_v4_addr, 2); + mif_dt_count_u32_array(np, "ap2cp_clatinfo_xlat_addr_0", + pdata->ap2cp_clatinfo_xlat_addr_0, 2); + mif_dt_count_u32_array(np, "ap2cp_clatinfo_xlat_addr_1", + pdata->ap2cp_clatinfo_xlat_addr_1, 2); + mif_dt_count_u32_array(np, "ap2cp_clatinfo_xlat_addr_2", + pdata->ap2cp_clatinfo_xlat_addr_2, 2); + mif_dt_count_u32_array(np, "ap2cp_clatinfo_xlat_addr_3", + pdata->ap2cp_clatinfo_xlat_addr_3, 2); + mif_dt_count_u32_array(np, "ap2cp_clatinfo_index", + pdata->ap2cp_clatinfo_index, 2); +#endif of_property_read_u32_array(np, "ap2cp_kerneltime", pdata->ap2cp_kerneltime, 2); of_property_read_u32_array(np, "ap2cp_kerneltime_sec", pdata->ap2cp_kerneltime_sec, 2); of_property_read_u32_array(np, "ap2cp_kerneltime_usec", pdata->ap2cp_kerneltime_usec, 2); @@ -437,6 +471,10 @@ static int parse_dt_ipc_region_pdata(struct device *dev, struct device_node *np, mif_dt_read_u32_noerr(np, "sbi_ap2cp_kerneltime_usec_pos", pdata->sbi_ap2cp_kerneltime_usec_pos); + /* Check pktproc use 36bit addr */ + mif_dt_read_u32(np, "pktproc_use_36bit_addr", + pdata->pktproc_use_36bit_addr); + return ret; } @@ -569,12 +607,6 @@ static const struct of_device_id cpif_dt_match[] = { {}, }; MODULE_DEVICE_TABLE(of, cpif_dt_match); -#else -static struct modem_data *modem_if_parse_dt_pdata(struct device *dev) -{ - return ERR_PTR(-ENODEV); -} -#endif enum mif_sim_mode { MIF_SIM_NONE = 0, @@ -713,33 +745,42 @@ static int cpif_probe(struct platform_device *pdev) err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); if (err) { mif_err("dma_set_mask_and_coherent() error:%d\n", err); - return err; + goto fail; } if (dev->of_node) { pdata = modem_if_parse_dt_pdata(dev); if (IS_ERR(pdata)) { mif_err("MIF DT parse error!\n"); - return PTR_ERR(pdata); + err = PTR_ERR(pdata); + goto fail; } } else { if (!pdata) { mif_err("Non-DT, incorrect pdata!\n"); - return -EINVAL; + err = -EINVAL; + goto fail; } } msd = create_modem_shared_data(pdev); if (!msd) { mif_err("%s: msd == NULL\n", pdata->name); - return -ENOMEM; + err = -ENOMEM; + goto fail; } modemctl = create_modemctl_device(pdev, msd); if (!modemctl) { mif_err("%s: modemctl == NULL\n", pdata->name); devm_kfree(dev, msd); - return -ENOMEM; + err = -ENOMEM; + goto fail; + } + + if (toe_dev_create(pdev)) { + mif_err("%s: toe dev not created\n", pdata->name); + goto free_mc; } /* create link device */ @@ -747,13 +788,13 @@ static int cpif_probe(struct platform_device *pdev) if (!ld) goto free_mc; - mif_err("%s: %s link created\n", pdata->name, ld->name); + mif_info("%s: %s link created\n", pdata->name, ld->name); ld->mc = modemctl; ld->msd = msd; list_add(&ld->list, &msd->link_dev_list); - /* set sime mode */ + /* get sim mode */ sim_mode = get_sim_mode(dev->of_node); /* char device */ @@ -787,9 +828,10 @@ static int cpif_probe(struct platform_device *pdev) goto free_iod; } - if (iod[i]->format == IPC_FMT || iod[i]->format == IPC_BOOT) - list_add_tail(&iod[i]->list, - &modemctl->modem_state_notify_list); + /* Basically, iods of IPC_FMT and IPC_BOOT will receive the state */ + if (iod[i]->format == IPC_FMT || iod[i]->format == IPC_BOOT || + iod[i]->attrs & IO_ATTR_STATE_RESET_NOTI) + list_add_tail(&iod[i]->list, &modemctl->modem_state_notify_list); attach_devices(iod[i], dev); } @@ -809,11 +851,13 @@ static int cpif_probe(struct platform_device *pdev) mif_err("failed to initialize hiprio list(%d)\n", err); #endif - err = mif_init_argos_notifier(); - if (err < 0) - mif_err("failed to initialize argos_notifier(%d)\n", err); +#if IS_ENABLED(CONFIG_CPIF_VENDOR_HOOK) + err = hook_init(); + if (err) + mif_err("failed to register vendor hook\n"); +#endif - mif_err("%s: done ---\n", pdev->name); + mif_info("%s: done ---\n", pdev->name); return 0; free_iod: @@ -836,8 +880,13 @@ static int cpif_probe(struct platform_device *pdev) if (msd) devm_kfree(dev, msd); + err = -ENOMEM; + +fail: mif_err("%s: xxx\n", pdev->name); - return -ENOMEM; + + panic("CP interface driver probe failed\n"); + return err; } static void cpif_shutdown(struct platform_device *pdev) @@ -860,7 +909,6 @@ static int modem_suspend(struct device *pdev) if (mc->ops.suspend) mc->ops.suspend(mc); - mif_err("%s\n", mc->name); set_wakeup_packet_log(true); return 0; @@ -875,8 +923,6 @@ static int modem_resume(struct device *pdev) if (mc->ops.resume) mc->ops.resume(mc); - mif_err("%s\n", mc->name); - return 0; } diff --git a/drivers/soc/google/cpif/modem_notifier.c b/drivers/soc/google/cpif/modem_notifier.c index b15d4a92ffa4..f5ef42f3cd25 100644 --- a/drivers/soc/google/cpif/modem_notifier.c +++ b/drivers/soc/google/cpif/modem_notifier.c @@ -30,8 +30,7 @@ EXPORT_SYMBOL(register_modem_event_notifier); void modem_notify_event(enum modem_event evt, void *mc) { - mif_info("event notify (%d)\n", evt); - raw_notifier_call_chain(&modem_event_notifier, evt, mc); + /* ToDo */ } EXPORT_SYMBOL(modem_notify_event); @@ -45,9 +44,9 @@ int register_modem_voice_call_event_notifier(struct notifier_block *nb) void modem_voice_call_notify_event(enum modem_voice_call_event evt, void *data) { - mif_err("voice call event notify (%d) ++\n", evt); + mif_info("voice call event notify (%d) ++\n", evt); raw_notifier_call_chain(&modem_voice_call_event_notifier, evt, data); - mif_err("voice call event notify (%d) --\n", evt); + mif_info("voice call event notify (%d) --\n", evt); } EXPORT_SYMBOL(modem_voice_call_notify_event); #endif diff --git a/drivers/soc/google/cpif/modem_prj.h b/drivers/soc/google/cpif/modem_prj.h index 6629b283bb5f..ab057bc00000 100644 --- a/drivers/soc/google/cpif/modem_prj.h +++ b/drivers/soc/google/cpif/modem_prj.h @@ -32,15 +32,12 @@ #include #endif #endif -#include "modem_debug.h" #include "modem_v1.h" #include "include/circ_queue.h" #include "include/sipc5.h" #include "include/exynos_ipc.h" -#define DEBUG_MODEM_IF -#ifdef DEBUG_MODEM_IF /* #define DEBUG_MODEM_IF_LINK_TX */ /* #define DEBUG_MODEM_IF_LINK_RX */ @@ -51,7 +48,6 @@ /* #define DEBUG_MODEM_IF_PS_DATA */ /* #define DEBUG_MODEM_IF_IP_DATA */ -#endif /* * IOCTL commands @@ -96,10 +92,6 @@ struct cp_image { #define IOCTL_GET_CP_BOOTLOG _IO(IOCTL_MAGIC, 0x47) #define IOCTL_CLR_CP_BOOTLOG _IO(IOCTL_MAGIC, 0x48) -/* AP capability index - considers first 32bits only*/ -#define AP_CAP_PKTPROC_UL 0x00000001 -#define AP_CAP_CH_EXTENSION 0x00000002 - /* Log dump */ #define IOCTL_MIF_LOG_DUMP _IO(IOCTL_MAGIC, 0x51) @@ -111,6 +103,7 @@ enum cp_log_dump_index { LOG_IDX_DATABUF_DL, LOG_IDX_DATABUF_UL, LOG_IDX_L2B, + LOG_IDX_DDM, MAX_LOG_DUMP_IDX }; struct cp_log_dump { @@ -187,6 +180,8 @@ struct t_handover_block_info { } __packed; #define IOCTL_HANDOVER_BLOCK_INFO _IO('o', 0x57) +#define IOCTL_SET_SPI_BOOT_MODE _IO('o', 0x58) + /* * Definitions for IO devices */ @@ -212,28 +207,29 @@ enum modem_state { STATE_ONLINE, STATE_NV_REBUILDING, /* <= rebuilding start */ STATE_LOADER_DONE, - STATE_SIM_ATTACH, - STATE_SIM_DETACH, + STATE_SIM_ATTACH, /* Deprecated */ + STATE_SIM_DETACH, /* Deprecated */ STATE_CRASH_WATCHDOG, /* cp watchdog crash */ - STATE_INIT, /* cp booting has not been tried yet */ + + /* Internal states */ + STATE_RESET, /* normal reset */ }; +/* Intervals in ms for the reset noti via poll */ +#define STATE_RESET_INTERVAL_MS (200) + enum link_state { LINK_STATE_OFFLINE = 0, LINK_STATE_IPC, LINK_STATE_CP_CRASH }; -struct sim_state { - bool online; /* SIM is online? */ - bool changed; /* online is changed? */ -}; - struct cp_power_stats { u64 count; /* count state was entered */ u64 duration_usec; /* total time (usecs) in state */ u64 last_entry_timestamp_usec; /* timestamp(usecs since boot) of last time entered */ u64 last_exit_timestamp_usec; /* timestamp(usecs since boot) of last time exited */ + bool suspended; /* whether the modem is currently in sleep */ }; struct sec_info { @@ -263,24 +259,9 @@ struct __packed sipc_fmt_hdr { #define sipc5_is_not_reserved_channel(ch) \ ((ch) != 0 && (ch) != 5 && (ch) != 6 && (ch) != 27 && (ch) != 255) -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) || IS_ENABLED(CONFIG_MODEM_IF_QOS) -#define MAX_NDEV_TX_Q 2 -#else -#define MAX_NDEV_TX_Q 1 -#endif -#define MAX_NDEV_RX_Q 1 /* mark value for high priority packet, hex QOSH */ #define RAW_HPRIO 0x514F5348 -/* for fragmented data from link devices */ -struct fragmented_data { - struct sk_buff *skb_recv; - struct sipc5_frame_data f_data; - /* page alloc fail retry*/ - unsigned int realloc_offset; -}; -#define fragdata(iod, ld) (&(iod)->fragments[(ld)->link_type]) - /** struct skbuff_priv - private data of struct sk_buff * this is matched to char cb[48] of struct sk_buff */ @@ -306,34 +287,10 @@ static inline struct skbuff_private *skbpriv(struct sk_buff *skb) return (struct skbuff_private *)&skb->cb; } -enum iod_rx_state { - IOD_RX_ON_STANDBY = 0, - IOD_RX_HEADER, - IOD_RX_PAYLOAD, - IOD_RX_PADDING, - MAX_IOD_RX_STATE -}; - -static const char * const rx_state_string[] = { - [IOD_RX_ON_STANDBY] = "RX_ON_STANDBY", - [IOD_RX_HEADER] = "RX_HEADER", - [IOD_RX_PAYLOAD] = "RX_PAYLOAD", - [IOD_RX_PADDING] = "RX_PADDING", -}; - -static const inline char *rx_state(enum iod_rx_state state) -{ - if (unlikely(state >= MAX_IOD_RX_STATE)) - return "INVALID_STATE"; - else - return rx_state_string[state]; -} - struct io_device { struct list_head list; /* rb_tree node for an io device */ - struct rb_node node_chan; struct rb_node node_fmt; /* Name of the IO device */ @@ -364,7 +321,6 @@ struct io_device { u32 link_type; u32 format; u32 io_typ; - enum modem_network net_typ; /* Attributes of an IO device */ u32 attrs; @@ -387,10 +343,6 @@ struct io_device { /* For keeping multi-frame packets temporarily */ struct sk_buff_head sk_multi_q[NUM_SIPC_MULTI_FRAME_IDS]; - /* RX state used in RX FSM */ - enum iod_rx_state curr_rx_state; - enum iod_rx_state next_rx_state; - /* * work for each io device, when delayed work needed * use this for private io device rx action @@ -403,17 +355,12 @@ struct io_device { u8 info_id; spinlock_t info_id_lock; - struct fragmented_data fragments[LINKDEV_MAX]; - int (*recv_skb_single)(struct io_device *iod, struct link_device *ld, struct sk_buff *skb); int (*recv_net_skb)(struct io_device *iod, struct link_device *ld, struct sk_buff *skb); - /* inform the IO device that the SIM is not inserting or removing */ - void (*sim_state_changed)(struct io_device *iod, bool sim_online); - struct modem_ctl *mc; struct modem_shared *msd; @@ -492,6 +439,8 @@ struct link_device { /* capability check */ u32 capability_check; + bool hiprio_ack_only; + /* Modem data */ struct modem_data *mdm_data; @@ -499,7 +448,6 @@ struct link_device { spinlock_t netif_lock; /* bit mask for stopped channel */ - unsigned long netif_stop_mask; unsigned long tx_flowctrl_mask; /* flag of stopped state for all channels */ @@ -507,8 +455,8 @@ struct link_device { struct workqueue_struct *rx_wq; - /* MIF buffer management */ - struct mif_buff_mng *mif_buff_mng; + /* CP interface network rx management */ + struct cpif_netrx_mng *cpif_netrx_mng; /* Save reason of forced crash */ struct crash_reason crash_reason; @@ -547,9 +495,6 @@ struct link_device { int (*get_cp_crash_reason)(struct link_device *ld, struct io_device *iod, unsigned long arg); - /* Reset buffer & dma_addr for zerocopy */ - void (*reset_zerocopy)(struct link_device *ld); - int (*enable_rx_int)(struct link_device *ld); int (*disable_rx_int)(struct link_device *ld); @@ -557,19 +502,8 @@ struct link_device { void (*stop_timers)(struct mem_link_device *mld); int (*handover_block_info)(struct link_device *ld, unsigned long arg); - -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) - int (*register_pcie)(struct link_device *ld); -#endif - -#if IS_ENABLED(CONFIG_SBD_BOOTLOG) - /* print cp boot/main logs */ - struct timer_list cplog_timer; -#endif }; -#define pm_to_link_device(pm) container_of(pm, struct link_device, pm) - static inline struct sk_buff *rx_alloc_skb(unsigned int length, struct io_device *iod, struct link_device *ld) { @@ -650,12 +584,9 @@ struct modem_ctl { struct device *dev; char *name; struct modem_data *mdm_data; - struct modem_shared *msd; - void __iomem *sysram_alive; enum modem_state phone_state; - struct sim_state sim_state; /* spin lock for each modem_ctl instance */ spinlock_t lock; @@ -670,25 +601,24 @@ struct modem_ctl { /* completion for waiting for CP power-off */ struct completion off_cmpl; +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + /* completion for waiting for cp2ap clatinfo ack */ + struct completion clatinfo_ack; +#endif + /* for broadcasting AP's PM state (active or sleep) */ unsigned int int_pda_active; unsigned int int_cp_wakeup; /* for checking aliveness of CP */ unsigned int irq_phone_active; +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) /* for broadcasting AP LCD state */ unsigned int int_lcd_status; +#endif #if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) - unsigned int mbx_pda_active; - unsigned int mbx_phone_active; - unsigned int mbx_ap_wakeup; - unsigned int mbx_ap_status; - unsigned int mbx_cp_wakeup; - unsigned int mbx_cp_status; - /* for notify uart connection with direction*/ - unsigned int mbx_uart_noti; unsigned int int_uart_noti; /* for checking aliveness of CP */ @@ -709,8 +639,10 @@ struct modem_ctl { unsigned int sbi_uart_noti_mask; unsigned int sbi_uart_noti_pos; +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) unsigned int sbi_lcd_status_mask; unsigned int sbi_lcd_status_pos; +#endif unsigned int ap2cp_cfg_addr; void __iomem *ap2cp_cfg_ioaddr; @@ -738,7 +670,6 @@ struct modem_ctl { spinlock_t pcie_pm_lock; struct pci_driver pci_driver; - int int_pcie_link_ack; int pcie_ch_num; int pcie_cto_retry_cnt; int pcie_cto_retry_cnt_all; @@ -762,23 +693,10 @@ struct modem_ctl { atomic_t dump_toggle_issued; #endif - struct cpif_gpio s5100_gpio_cp_pwr; - struct cpif_gpio s5100_gpio_cp_reset; - struct cpif_gpio s5100_gpio_cp_ps_hold; - struct cpif_gpio s5100_gpio_cp_wakeup; - struct cpif_gpio s5100_gpio_cp_dump_noti; - struct cpif_gpio s5100_gpio_ap_status; - struct cpif_gpio s5100_gpio_ap_wakeup; - struct cpif_gpio s5100_gpio_phone_active; - - struct modem_irq s5100_irq_ap_wakeup; - struct modem_irq s5100_irq_phone_active; + struct cpif_gpio cp_gpio[CP_GPIO_MAX]; + struct modem_irq cp_gpio_irq[CP_GPIO_IRQ_MAX]; bool s5100_cp_reset_required; - bool s5100_iommu_map_enabled; -#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE_S2MPU) - bool s5100_s2mpu_enabled; -#endif #if IS_ENABLED(CONFIG_GS_S2MPU) struct s2mpu_info *s2mpu; @@ -789,21 +707,7 @@ struct modem_ctl { #endif struct notifier_block send_panic_nb; - -#if IS_ENABLED(CONFIG_EXYNOS_BUSMONITOR) - struct notifier_block busmon_nfb; -#endif - -#if IS_ENABLED(CONFIG_MUIC_NOTIFIER) - struct notifier_block uart_notifier; -#endif - bool uart_connect; - bool uart_dir; - - const struct attribute_group *group; - - struct delayed_work dwork; - struct work_struct work; + struct notifier_block abox_call_state_nb; struct modemctl_ops ops; struct io_device *iod; @@ -813,13 +717,11 @@ struct modem_ctl { struct notifier_block itmon_nb; #endif - void (*gpio_revers_bias_clear)(void); - void (*gpio_revers_bias_restore)(void); void (*modem_complete)(struct modem_ctl *mc); - int receive_first_ipc; - +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) struct notifier_block lcd_notifier; +#endif struct cp_power_stats cp_power_stats; spinlock_t power_stats_lock; @@ -873,20 +775,14 @@ u8 sipc5_build_config(struct io_device *iod, struct link_device *ld, unsigned int count); void sipc5_build_header(struct io_device *iod, u8 *buff, u8 cfg, unsigned int tx_bytes, unsigned int remains); -void iodev_dump_status(struct io_device *iod, void *args); void vnet_setup(struct net_device *ndev); const struct file_operations *get_bootdump_io_fops(void); const struct file_operations *get_ipc_io_fops(void); -int sipc5_init_io_device(struct io_device *iod); +int sipc5_init_io_device(struct io_device *iod, struct mem_link_device *mld); void sipc5_deinit_io_device(struct io_device *iod); -#if IS_ENABLED(CONFIG_RPS) && IS_ENABLED(CONFIG_ARGOS) -extern struct net init_net; -extern int sec_argos_register_notifier(struct notifier_block *n, char *label); -extern int sec_argos_unregister_notifier(struct notifier_block *n, char *label); -int mif_init_argos_notifier(void); -#else -static inline int mif_init_argos_notifier(void) { return 0; } +#if IS_ENABLED(CONFIG_CPIF_VENDOR_HOOK) +int hook_init(void); #endif #endif diff --git a/drivers/soc/google/cpif/modem_toe_device.c b/drivers/soc/google/cpif/modem_toe_device.c new file mode 100644 index 000000000000..929dd7fe8583 --- /dev/null +++ b/drivers/soc/google/cpif/modem_toe_device.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * MODEM TOE device support + * + */ + +#include "modem_toe_device.h" +#include "dit.h" +#include "link_device.h" + +#define TOE_DEV_NAME "umts_toe0" + +static struct toe_ctrl_t *tc; + +void toe_set_iod_clat_netdev(struct io_device *iod, void *args) +{ + struct clat_info *clat = (struct clat_info *) args; + struct net_device *ndev = NULL; + struct link_device *ld = get_current_link(iod); + unsigned long flags; + + if (strncmp(iod->name, clat->ipv6_iface, IFNAMSIZ) != 0) + return; + + if (clat->ipv4_iface[0]) + ndev = dev_get_by_name(&init_net, clat->ipv4_iface); + + if (!clat->ipv4_iface[0] || ndev) { + spin_lock_irqsave(&iod->clat_lock, flags); + if (iod->clat_ndev) + dev_put(iod->clat_ndev); + + if (ndev) + ndev->features |= NETIF_F_GRO_FRAGLIST; + iod->clat_ndev = ndev; + spin_unlock_irqrestore(&iod->clat_lock, flags); + +#if IS_ENABLED(CONFIG_CPIF_TP_MONITOR) + if (iod->clat_ndev) { + struct mem_link_device *mld = to_mem_link_device(ld); + + mif_info("set RPS again\n"); + mld->tpmon->reset_data("RPS"); + } +#endif + + mif_info("%s clat netdev[%d] ch: %d, iface v6/v4: %s/%s\n", + (ndev ? "set" : "clear"), clat->clat_index, iod->ch, + clat->ipv6_iface, clat->ipv4_iface); + } +} + +static int toe_dev_open(struct inode *inode, struct file *filp) +{ + return 0; +} + +static int toe_dev_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static unsigned int toe_dev_poll(struct file *filp, struct poll_table_struct *wait) +{ + return 0; +} + +static ssize_t toe_dev_read(struct file *filp, char *buf, size_t count, loff_t *fpos) +{ + return 0; +} + +static long toe_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct clat_info clat; + u32 ready, num; + struct mem_link_device *mld = tc->mld; + + switch (cmd) { + case IOCTL_TOE_SET_CLAT_READY: + if (copy_from_user(&ready, (const void __user *)arg, sizeof(ready))) + return -EFAULT; + + tc->clat_hal_ready = (ready ? true : false); + break; + case IOCTL_TOE_SET_CLAT_IFACES_NUM: + if (copy_from_user(&num, (const void __user *)arg, sizeof(num))) + return -EFAULT; + + tc->clat_ifaces_num = num; + break; + case IOCTL_TOE_SET_CLAT_INFO: + if (copy_from_user(&clat, (const void __user *)arg, sizeof(struct clat_info))) + return -EFAULT; + + if (!tc->set_clat_info || !tc->set_clat_info(mld, &clat)) + return -EINVAL; + break; + default: + mif_err("unknown command: 0x%X\n", cmd); + return -EINVAL; + } + + return 0; +} + +static ssize_t status_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + ssize_t count = 0; + + count += scnprintf(&buf[count], PAGE_SIZE - count, + "hal_ready:%d ifaces_num:%d dev_support:%d\n", + tc->clat_hal_ready, tc->clat_ifaces_num, tc->clat_dev_support); + + return count; +} + +static DEVICE_ATTR_RO(status); + +static struct attribute *toe_attrs[] = { + &dev_attr_status.attr, + NULL, +}; + +static const struct attribute_group toe_group = { + .attrs = toe_attrs, + .name = "toe", +}; + +static const struct file_operations toe_dev_fops = { + .owner = THIS_MODULE, + .open = toe_dev_open, + .poll = toe_dev_poll, + .read = toe_dev_read, + .release = toe_dev_release, + .compat_ioctl = toe_dev_ioctl, + .unlocked_ioctl = toe_dev_ioctl, +}; + +static struct miscdevice toe_dev_misc = { + .minor = MISC_DYNAMIC_MINOR, + .name = TOE_DEV_NAME, + .fops = &toe_dev_fops, +}; + +int toe_dev_init(struct mem_link_device *mld) +{ + if (unlikely(!tc)) { + mif_err("toe not created\n"); + return -EPERM; + } + + tc->mld = mld; + tc->clat_dev_support = false; + tc->set_clat_info = NULL; + tc->set_iod_clat_netdev = toe_set_iod_clat_netdev; + + /* Can add the other devs or change the ordering */ + if (dit_support_clat()) { + tc->clat_dev_support = true; + tc->set_clat_info = dit_hal_set_clat_info; + } +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + else { + tc->clat_dev_support = true; + tc->set_clat_info = shmem_ap2cp_write_clatinfo; + } +#endif + mld->tc = tc; + + return 0; +} + +int toe_dev_create(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret = 0; + + tc = devm_kzalloc(dev, sizeof(struct toe_ctrl_t), GFP_KERNEL); + if (!tc) { + mif_err("toe ctrl alloc failed\n"); + return -ENOMEM; + } + + ret = sysfs_create_group(&dev->kobj, &toe_group); + if (ret != 0) { + mif_err("sysfs_create_group() error %d\n", ret); + goto error; + } + + ret = misc_register(&toe_dev_misc); + if (ret) { + mif_err("misc register error\n"); + goto error; + } + + return 0; + +error: + if (tc) { + devm_kfree(dev, tc); + tc = NULL; + } + + return ret; +} diff --git a/drivers/soc/google/cpif/modem_toe_device.h b/drivers/soc/google/cpif/modem_toe_device.h new file mode 100644 index 000000000000..f0175414fa07 --- /dev/null +++ b/drivers/soc/google/cpif/modem_toe_device.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * MODEM TOE device support + * + */ + +#ifndef __MODEM_TOE_DEVICE_H__ +#define __MODEM_TOE_DEVICE_H__ + +#include +#include +#include + +#include "modem_utils.h" + +#define IOCTL_TOE_MAGIC ('T') +#define IOCTL_TOE_SET_CLAT_READY _IOW(IOCTL_TOE_MAGIC, 0x00, uint32_t) +#define IOCTL_TOE_SET_CLAT_IFACES_NUM _IOW(IOCTL_TOE_MAGIC, 0x01, uint32_t) +#define IOCTL_TOE_SET_CLAT_INFO _IOW(IOCTL_TOE_MAGIC, 0x02, struct clat_info) + +struct clat_info { + u32 clat_index; + char ipv6_iface[IFNAMSIZ]; + char ipv4_iface[IFNAMSIZ]; + struct in6_addr ipv6_local_subnet; + struct in_addr ipv4_local_subnet; + struct in6_addr plat_subnet; +} __packed; + +struct toe_ctrl_t { + bool clat_hal_ready; + u32 clat_ifaces_num; + bool clat_dev_support; + struct mem_link_device *mld; + + bool (*set_clat_info)(struct mem_link_device *mld, struct clat_info *clat); + void (*set_iod_clat_netdev)(struct io_device *iod, void *args); +}; + +void toe_set_iod_clat_netdev(struct io_device *iod, void *args); +int toe_dev_init(struct mem_link_device *mld); +int toe_dev_create(struct platform_device *pdev); + +#endif /* __MODEM_TOE_DEVICE_H__ */ diff --git a/drivers/soc/google/cpif/modem_utils.c b/drivers/soc/google/cpif/modem_utils.c index e6320a0a70c4..caac179fb899 100644 --- a/drivers/soc/google/cpif/modem_utils.c +++ b/drivers/soc/google/cpif/modem_utils.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include @@ -38,9 +37,6 @@ #include "modem_utils.h" #include "cpif_version.h" -#define CMD_SUSPEND ((u16)(0x00CA)) -#define CMD_RESUME ((u16)(0x00CB)) - #define TX_SEPARATOR "cpif: >>>>>>>>>> Outgoing packet " #define RX_SEPARATOR "cpif: Incoming packet <<<<<<<<<<" #define LINE_SEPARATOR \ @@ -74,199 +70,6 @@ static unsigned long wakeup_dflags = module_param(wakeup_dflags, ulong, 0664); MODULE_PARM_DESC(wakeup_dflags, "modem_v1 wakeup debug flags"); -static const char *hex = "0123456789abcdef"; - -static struct raw_notifier_head cp_crash_notifier; - -struct mif_buff_mng *g_mif_buff_mng; - -static inline void ts642utc(struct timespec64 *ts, struct utc_time *utc) -{ - struct tm tm; - - time64_to_tm((ts->tv_sec - (sys_tz.tz_minuteswest * 60)), 0, &tm); - utc->year = 1900 + (u32)tm.tm_year; - utc->mon = 1 + tm.tm_mon; - utc->day = tm.tm_mday; - utc->hour = tm.tm_hour; - utc->min = tm.tm_min; - utc->sec = tm.tm_sec; - utc->us = (u32)ns2us(ts->tv_nsec); -} - -void get_utc_time(struct utc_time *utc) -{ - struct timespec64 ts; - - ktime_get_ts64(&ts); - ts642utc(&ts, utc); -} - -int mif_dump_log(struct modem_shared *msd, struct io_device *iod) -{ - unsigned long read_len = 0; - unsigned long flags; - - spin_lock_irqsave(&msd->lock, flags); - while (read_len < MAX_MIF_BUFF_SIZE) { - struct sk_buff *skb; - - skb = alloc_skb(MAX_IPC_SKB_SIZE, GFP_ATOMIC); - if (!skb) { - mif_err("ERR! alloc_skb fail\n"); - spin_unlock_irqrestore(&msd->lock, flags); - return -ENOMEM; - } - memcpy(skb_put(skb, MAX_IPC_SKB_SIZE), - msd->storage.addr + read_len, MAX_IPC_SKB_SIZE); - skb_queue_tail(&iod->sk_rx_q, skb); - read_len += MAX_IPC_SKB_SIZE; - wake_up(&iod->wq); - } - spin_unlock_irqrestore(&msd->lock, flags); - return 0; -} - -static unsigned long long get_kernel_time(void) -{ - int this_cpu; - unsigned long flags; - unsigned long long time; - - preempt_disable(); - raw_local_irq_save(flags); - - this_cpu = smp_processor_id(); - time = cpu_clock(this_cpu); - - preempt_enable(); - raw_local_irq_restore(flags); - - return time; -} - -void mif_ipc_log(enum mif_log_id id, - struct modem_shared *msd, const char *data, size_t len) -{ - struct mif_ipc_block *block; - unsigned long flags; - - spin_lock_irqsave(&msd->lock, flags); - - block = (struct mif_ipc_block *) - (msd->storage.addr + (MAX_LOG_SIZE * msd->storage.cnt)); - msd->storage.cnt = ((msd->storage.cnt + 1) < MAX_LOG_CNT) ? - msd->storage.cnt + 1 : 0; - - spin_unlock_irqrestore(&msd->lock, flags); - - block->id = id; - block->time = get_kernel_time(); - block->len = (len > MAX_IPC_LOG_SIZE) ? MAX_IPC_LOG_SIZE : len; - memcpy(block->buff, data, block->len); -} - -void _mif_irq_log(enum mif_log_id id, struct modem_shared *msd, - struct mif_irq_map map, const char *data, size_t len) -{ - struct mif_irq_block *block; - unsigned long flags; - - spin_lock_irqsave(&msd->lock, flags); - - block = (struct mif_irq_block *) - (msd->storage.addr + (MAX_LOG_SIZE * msd->storage.cnt)); - msd->storage.cnt = ((msd->storage.cnt + 1) < MAX_LOG_CNT) ? - msd->storage.cnt + 1 : 0; - - spin_unlock_irqrestore(&msd->lock, flags); - - block->id = id; - block->time = get_kernel_time(); - memcpy(&(block->map), &map, sizeof(struct mif_irq_map)); - if (data) - memcpy(block->buff, data, - (len > MAX_IRQ_LOG_SIZE) ? MAX_IRQ_LOG_SIZE : len); -} - -void _mif_com_log(enum mif_log_id id, - struct modem_shared *msd, const char *format, ...) -{ - struct mif_common_block *block; - unsigned long flags; - va_list args; - - spin_lock_irqsave(&msd->lock, flags); - - block = (struct mif_common_block *) - (msd->storage.addr + (MAX_LOG_SIZE * msd->storage.cnt)); - msd->storage.cnt = ((msd->storage.cnt + 1) < MAX_LOG_CNT) ? - msd->storage.cnt + 1 : 0; - - spin_unlock_irqrestore(&msd->lock, flags); - - block->id = id; - block->time = get_kernel_time(); - - va_start(args, format); - vsnprintf(block->buff, MAX_COM_LOG_SIZE, format, args); - va_end(args); -} - -void _mif_time_log(enum mif_log_id id, struct modem_shared *msd, - struct timespec64 epoch, const char *data, size_t len) -{ - struct mif_time_block *block; - unsigned long flags; - - spin_lock_irqsave(&msd->lock, flags); - - block = (struct mif_time_block *) - (msd->storage.addr + (MAX_LOG_SIZE * msd->storage.cnt)); - msd->storage.cnt = ((msd->storage.cnt + 1) < MAX_LOG_CNT) ? - msd->storage.cnt + 1 : 0; - - spin_unlock_irqrestore(&msd->lock, flags); - - block->id = id; - block->time = get_kernel_time(); - block->epoch = epoch; - - if (data) - memcpy(block->buff, data, - (len > MAX_IRQ_LOG_SIZE) ? MAX_IRQ_LOG_SIZE : len); -} - -/* dump2hex - * dump data to hex as fast as possible. - * the length of @buff must be greater than "@len * 3" - * it need 3 bytes per one data byte to print. - */ -static inline void dump2hex(char *buff, size_t buff_size, - const char *data, size_t data_len) -{ - char *dest = buff; - size_t len; - size_t i; - - if (buff_size < (data_len * 3)) - len = buff_size / 3; - else - len = data_len; - - for (i = 0; i < len; i++) { - *dest++ = hex[(data[i] >> 4) & 0xf]; - *dest++ = hex[data[i] & 0xf]; - *dest++ = ' '; - } - - /* The last character must be overwritten with NULL */ - if (likely(len > 0)) - dest--; - - *dest = 0; -} - static bool wakeup_log_enable; inline void set_wakeup_packet_log(bool enable) { @@ -278,11 +81,6 @@ inline unsigned long get_log_flags(void) return wakeup_log_enable ? wakeup_dflags : dflags; } -void set_dflags(unsigned long flag) -{ - dflags = flag; -} - static inline bool log_enabled(u8 ch, struct link_device *ld) { unsigned long flags = get_log_flags(); @@ -327,7 +125,6 @@ void mif_pkt(u8 ch, const char *tag, struct sk_buff *skb) } /* print buffer as hex string */ -#define PR_BUFFER_SIZE 128 int pr_buffer(const char *tag, const char *data, size_t data_len, size_t max_len) { @@ -344,35 +141,6 @@ int pr_buffer(const char *tag, const char *data, size_t data_len, str, (len == data_len) ? "" : " ..."); } -/* flow control CM from CP, it use in serial devices */ -int link_rx_flowctl_cmd(struct link_device *ld, const char *data, size_t len) -{ - struct modem_shared *msd = ld->msd; - unsigned short *cmd, *end = (unsigned short *)(data + len); - - mif_debug("flow control cmd: size=%ld\n", (long)len); - - for (cmd = (unsigned short *)data; cmd < end; cmd++) { - switch (*cmd) { - case CMD_SUSPEND: - iodevs_for_each(msd, iodev_netif_stop, 0); - mif_info("flowctl CMD_SUSPEND(%04X)\n", *cmd); - break; - - case CMD_RESUME: - iodevs_for_each(msd, iodev_netif_wake, 0); - mif_info("flowctl CMD_RESUME(%04X)\n", *cmd); - break; - - default: - mif_err("flowctl BAD CMD: %04X\n", *cmd); - break; - } - } - - return 0; -} - struct io_device *get_iod_with_format(struct modem_shared *msd, u32 format) { @@ -427,117 +195,62 @@ struct io_device *insert_iod_with_format(struct modem_shared *msd, return NULL; } -void iodev_netif_wake(struct io_device *iod, void *args) +/* netif wake/stop queue of iod having activated ndev */ +static void netif_tx_flowctl(struct modem_shared *msd, bool tx_stop) { - if (iod->io_typ == IODEV_NET && iod->ndev) { - netif_wake_queue(iod->ndev); - mif_info("%s\n", iod->name); - } -} + struct io_device *iod; -void iodev_netif_stop(struct io_device *iod, void *args) -{ - if (iod->io_typ == IODEV_NET && iod->ndev) { - netif_stop_queue(iod->ndev); - mif_info("%s\n", iod->name); + if (!msd) { + mif_err_limited("modem shared data does not exist\n"); + return; } -} - -void netif_tx_flowctl(struct modem_shared *msd, bool tx_stop) -{ - struct io_device *iod; spin_lock(&msd->active_list_lock); list_for_each_entry(iod, &msd->activated_ndev_list, node_ndev) { - if (tx_stop) { + if (tx_stop) netif_stop_subqueue(iod->ndev, 0); -#ifdef DEBUG_MODEM_IF_FLOW_CTRL - mif_err("tx_stop:%s, iod->ndev->name:%s\n", - tx_stop ? "suspend" : "resume", - iod->ndev->name); -#endif - } else { + else netif_wake_subqueue(iod->ndev, 0); + #ifdef DEBUG_MODEM_IF_FLOW_CTRL - mif_err("tx_stop:%s, iod->ndev->name:%s\n", - tx_stop ? "suspend" : "resume", - iod->ndev->name); + mif_err("tx_stop:%s, iod->ndev->name:%s\n", + tx_stop ? "suspend" : "resume", + iod->ndev->name); #endif - } } spin_unlock(&msd->active_list_lock); } -void stop_net_iface(struct link_device *ld, unsigned int channel) -{ - struct io_device *iod; - unsigned long flags; - - spin_lock_irqsave(&ld->netif_lock, flags); - - if (test_bit(channel, &ld->netif_stop_mask)) { - mif_err("channel %d was already stopped!\n", channel); - goto exit; - } - - iod = link_get_iod_with_channel(ld, channel); - iodev_netif_stop(iod, 0); - set_bit(channel, &ld->netif_stop_mask); - -exit: - spin_unlock_irqrestore(&ld->netif_lock, flags); -} - -void stop_net_ifaces(struct link_device *ld) +bool stop_net_ifaces(struct link_device *ld, unsigned long set_mask) { - unsigned long flags; + bool ret = false; - spin_lock_irqsave(&ld->netif_lock, flags); + if (set_mask > 0) + cpif_set_bit(ld->tx_flowctrl_mask, set_mask); if (!atomic_read(&ld->netif_stopped)) { - if (ld->msd) - netif_tx_flowctl(ld->msd, true); + mif_info_limited("tx queue stopped: tx_flowctrl=0x%04lx(set_bit:%lu)\n", + ld->tx_flowctrl_mask, set_mask); + netif_tx_flowctl(ld->msd, true); atomic_set(&ld->netif_stopped, 1); + ret = true; } - spin_unlock_irqrestore(&ld->netif_lock, flags); -} - -void resume_net_iface(struct link_device *ld, unsigned int channel) -{ - struct io_device *iod; - unsigned long flags; - - spin_lock_irqsave(&ld->netif_lock, flags); - - if (!test_bit(channel, &ld->netif_stop_mask)) { - mif_err("channel %d was already resumed!\n", channel); - goto exit; - } - - iod = link_get_iod_with_channel(ld, channel); - iodev_netif_wake(iod, 0); - clear_bit(channel, &ld->netif_stop_mask); - -exit: - spin_unlock_irqrestore(&ld->netif_lock, flags); + return ret; } -void resume_net_ifaces(struct link_device *ld) +void resume_net_ifaces(struct link_device *ld, unsigned long clear_mask) { - unsigned long flags; - - spin_lock_irqsave(&ld->netif_lock, flags); + cpif_clear_bit(ld->tx_flowctrl_mask, clear_mask); - if (atomic_read(&ld->netif_stopped) != 0) { - if (ld->msd) - netif_tx_flowctl(ld->msd, false); + if (!ld->tx_flowctrl_mask && atomic_read(&ld->netif_stopped)) { + mif_info_limited("tx queue resumed: tx_flowctrl=0x%04lx(clear_bit:%lu)\n", + ld->tx_flowctrl_mask, clear_mask); + netif_tx_flowctl(ld->msd, false); atomic_set(&ld->netif_stopped, 0); } - - spin_unlock_irqrestore(&ld->netif_lock, flags); } /* @@ -565,198 +278,18 @@ __be32 ipv4str_to_be32(const char *ipv4str, size_t count) } void mif_add_timer(struct timer_list *timer, unsigned long expire, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) void (*function)(struct timer_list *)) -#else - void (*function)(unsigned long), unsigned long data) -#endif { if (timer_pending(timer)) return; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) timer_setup(timer, function, 0); timer->expires = get_jiffies_64() + expire; -#else - init_timer(timer); - timer->expires = jiffies + expire; - timer->function = function; - timer->data = data; -#endif add_timer(timer); } -void mif_print_data(const u8 *data, int len) -{ - int words = len >> 4; - int residue = len - (words << 4); - int i; - char *b; - char last[80]; - - /* Make the last line, if ((len % 16) > 0) */ - if (residue > 0) { - char tb[8]; - - sprintf(last, "%04X: ", (words << 4)); - b = (char *)data + (words << 4); - - for (i = 0; i < residue; i++) { - sprintf(tb, "%02x ", b[i]); - strcat(last, tb); - if ((i & 0x3) == 0x3) { - sprintf(tb, " "); - strcat(last, tb); - } - } - } - - for (i = 0; i < words; i++) { - b = (char *)data + (i << 4); - mif_err("%04X: " - "%02x %02x %02x %02x %02x %02x %02x %02x " - "%02x %02x %02x %02x %02x %02x %02x %02x\n", - (i << 4), - b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7], - b[8], b[9], b[10], b[11], b[12], b[13], b[14], b[15]); - } - - /* Print the last line */ - if (residue > 0) - mif_err("%s\n", last); -} - -void mif_dump2format16(const u8 *data, int len, char *buff, char *tag) -{ - char *d; - int i; - int words = len >> 4; - int residue = len - (words << 4); - char line[LINE_BUFF_SIZE]; - - for (i = 0; i < words; i++) { - memset(line, 0, LINE_BUFF_SIZE); - d = (char *)data + (i << 4); - - if (tag) - sprintf(line, "%s%04X| " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x\n", - tag, (i << 4), - d[0], d[1], d[2], d[3], - d[4], d[5], d[6], d[7], - d[8], d[9], d[10], d[11], - d[12], d[13], d[14], d[15]); - else - sprintf(line, "%04X| " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x " - "%02x %02x %02x %02x\n", - (i << 4), - d[0], d[1], d[2], d[3], - d[4], d[5], d[6], d[7], - d[8], d[9], d[10], d[11], - d[12], d[13], d[14], d[15]); - - strcat(buff, line); - } - - /* Make the last line, if (len % 16) > 0 */ - if (residue > 0) { - char tb[8]; - - memset(line, 0, LINE_BUFF_SIZE); - memset(tb, 0, sizeof(tb)); - d = (char *)data + (words << 4); - - if (tag) - sprintf(line, "%s%04X|", tag, (words << 4)); - else - sprintf(line, "%04X|", (words << 4)); - - for (i = 0; i < residue; i++) { - sprintf(tb, " %02x", d[i]); - strcat(line, tb); - if ((i & 0x3) == 0x3) { - sprintf(tb, " "); - strcat(line, tb); - } - } - strcat(line, "\n"); - - strcat(buff, line); - } -} - -void mif_dump2format4(const u8 *data, int len, char *buff, char *tag) -{ - char *d; - int i; - int words = len >> 2; - int residue = len - (words << 2); - char line[LINE_BUFF_SIZE]; - - for (i = 0; i < words; i++) { - memset(line, 0, LINE_BUFF_SIZE); - d = (char *)data + (i << 2); - - if (tag) - sprintf(line, "%s%04X| %02x %02x %02x %02x\n", - tag, (i << 2), d[0], d[1], d[2], d[3]); - else - sprintf(line, "%04X| %02x %02x %02x %02x\n", - (i << 2), d[0], d[1], d[2], d[3]); - - strcat(buff, line); - } - - /* Make the last line, if (len % 4) > 0 */ - if (residue > 0) { - char tb[8]; - - memset(line, 0, LINE_BUFF_SIZE); - memset(tb, 0, sizeof(tb)); - d = (char *)data + (words << 2); - - if (tag) - sprintf(line, "%s%04X|", tag, (words << 2)); - else - sprintf(line, "%04X|", (words << 2)); - - for (i = 0; i < residue; i++) { - sprintf(tb, " %02x", d[i]); - strcat(line, tb); - } - strcat(line, "\n"); - - strcat(buff, line); - } -} - -void mif_print_dump(const u8 *data, int len, int width) -{ - char *buff; - - buff = kzalloc(len << 3, GFP_ATOMIC); - if (!buff) { - mif_err("ERR! kzalloc fail\n"); - return; - } - - if (width == 16) - mif_dump2format16(data, len, buff, LOG_TAG); - else - mif_dump2format4(data, len, buff, LOG_TAG); - - pr_info("%s", buff); - - kfree(buff); -} - +#ifdef DEBUG_MODEM_IF_IP_DATA static void strcat_tcp_header(char *buff, u8 *pkt) { struct tcphdr *tcph = (struct tcphdr *)pkt; @@ -987,36 +520,7 @@ void print_ipv4_packet(const u8 *ip_pkt, enum direction dir) kfree(buff); } - -bool is_dns_packet(const u8 *ip_pkt) -{ - struct iphdr *iph = (struct iphdr *)ip_pkt; - struct udphdr *udph = (struct udphdr *)(ip_pkt + (iph->ihl << 2)); - - /* If this packet is not a UDP packet, return here. */ - if (iph->protocol != 17) - return false; - - if (ntohs(udph->dest) == 53 || ntohs(udph->source) == 53) - return true; - else - return false; -} - -bool is_syn_packet(const u8 *ip_pkt) -{ - struct iphdr *iph = (struct iphdr *)ip_pkt; - struct tcphdr *tcph = (struct tcphdr *)(ip_pkt + (iph->ihl << 2)); - - /* If this packet is not a TCP packet, return here. */ - if (iph->protocol != 6) - return false; - - if (tcph->syn || tcph->fin) - return true; - else - return false; -} +#endif /* DEBUG_MODEM_IF_IP_DATA */ void mif_init_irq(struct modem_irq *irq, unsigned int num, const char *name, unsigned long flags) @@ -1116,8 +620,8 @@ bool mif_gpio_set_value(struct cpif_gpio *gpio, int value, unsigned int delay_ms { int dup = 0; - if (!gpio_is_valid(gpio->num)) { - mif_err("SET GPIO %d is failed\n", gpio->num); + if (!gpio->valid) { + mif_err("SET GPIO %d is not valid\n", gpio->num); return false; } @@ -1140,13 +644,14 @@ bool mif_gpio_set_value(struct cpif_gpio *gpio, int value, unsigned int delay_ms return (!dup); } +EXPORT_SYMBOL(mif_gpio_set_value); int mif_gpio_get_value(struct cpif_gpio *gpio, bool log_print) { int value; - if (!gpio_is_valid(gpio->num)) { - mif_err("GET GPIO %d is failed\n", gpio->num); + if (!gpio->valid) { + mif_err("GET GPIO %d is not valid\n", gpio->num); return -EINVAL; } @@ -1157,6 +662,7 @@ int mif_gpio_get_value(struct cpif_gpio *gpio, bool log_print) return value; } +EXPORT_SYMBOL(mif_gpio_get_value); int mif_gpio_toggle_value(struct cpif_gpio *gpio, int delay_ms) { @@ -1168,303 +674,34 @@ int mif_gpio_toggle_value(struct cpif_gpio *gpio, int delay_ms) return value; } - -int board_gpio_export(struct device *dev, - unsigned int gpio, bool dir, const char *name) -{ - int ret = 0; - - if (!gpio_is_valid(gpio)) { - mif_err("invalid gpio pins - %s\n", name); - return -EINVAL; - } - - ret = gpio_export(gpio, dir); - if (ret) { - mif_err("%s: failed to export gpio (%d)\n", name, ret); - return ret; - } - - ret = gpio_export_link(dev, name, gpio); - if (ret) { - mif_err("%s: failed to export link_gpio (%d)\n", name, ret); - return ret; - } - - mif_info("%s exported\n", name); - - return 0; -} - -void make_gpio_floating(unsigned int gpio, bool floating) -{ - if (floating) - gpio_direction_input(gpio); - else - gpio_direction_output(gpio, 0); -} - -int __ref register_cp_crash_notifier(struct notifier_block *nb) -{ - return raw_notifier_chain_register(&cp_crash_notifier, nb); -} - -void __ref modemctl_notify_event(enum modemctl_event evt) -{ - raw_notifier_call_chain(&cp_crash_notifier, evt, NULL); -} +EXPORT_SYMBOL(mif_gpio_toggle_value); void mif_stop_logging(void) { } -static LIST_HEAD(bm_list); -struct mif_buff_mng *init_mif_buff_mng(unsigned char *buffer_start, - unsigned int buffer_size, unsigned int cell_size) -{ - struct mif_buff_mng *bm; - unsigned long flags; - - if (buffer_start == NULL || buffer_size == 0 || cell_size == 0) { - mif_err("parameter ERR!\n"); - return NULL; - } - - mif_info("buffer:%pK, size:%u, cell_size:%u\n", - buffer_start, buffer_size, cell_size); - - bm = kzalloc(sizeof(struct mif_buff_mng), GFP_KERNEL); - if (bm == NULL) - return NULL; - - bm->buffer_start = buffer_start; - bm->buffer_end = buffer_start + buffer_size; - bm->buffer_size = buffer_size; - bm->cell_size = cell_size; - bm->cell_count = buffer_size / cell_size; - bm->free_cell_count = bm->cell_count; - bm->used_cell_count = 0; - - bm->current_map_index = 0; - bm->buffer_map_size = (unsigned int)(bm->cell_count / - MIF_BITS_FOR_MAP_CELL) + 1; - bm->buffer_map = kzalloc((MIF_BUFF_MAP_CELL_SIZE * bm->buffer_map_size), - GFP_KERNEL); - if (bm->buffer_map == NULL) { - kfree(bm); - return NULL; - } - - mif_info("cell_count:%u, map_size:%u, map_size_byte:%lu buff_map:%pK\n" - , bm->cell_count, bm->buffer_map_size, - (sizeof(unsigned int) * bm->buffer_map_size), bm->buffer_map); - -#ifdef MIF_BUFF_DEBUG - mif_info("MIF_BUFF_MAP_CELL_SIZE:%lu\n", MIF_BUFF_MAP_CELL_SIZE); - mif_info("MIF_BITS_FOR_BYTE:%u\n", MIF_BITS_FOR_BYTE); - mif_info("MIF_BITS_FOR_MAP_CELL:%lu\n", MIF_BITS_FOR_MAP_CELL); -#endif - - spin_lock_init(&bm->lock); - - spin_lock_irqsave(&bm->lock, flags); - list_add(&bm->node, &bm_list); - spin_unlock_irqrestore(&bm->lock, flags); - - return bm; -} - -void exit_mif_buff_mng(struct mif_buff_mng *bm) -{ - unsigned long flags; - - if (bm) { - spin_lock_irqsave(&bm->lock, flags); - list_del(&bm->node); - spin_unlock_irqrestore(&bm->lock, flags); - - kfree(bm->buffer_map); - kfree(bm); - } -} - -void *alloc_mif_buff(struct mif_buff_mng *bm) +const char *get_cpif_driver_version(void) { - unsigned char *buff_allocated; - int i, j; - unsigned int location; - int find_flag = false; - unsigned long flags; - uint64_t test_map; - int last_bit_set; - - if (bm == NULL || bm->buffer_map == NULL) - return NULL; - - if (bm->free_cell_count == 0) { -#ifdef MIF_BUFF_DEBUG - mif_info("ERR allocation fail\n"); -#endif - return NULL; - } - - spin_lock_irqsave(&bm->lock, flags); - - for (i = bm->current_map_index ; i < bm->buffer_map_size; i++) { - test_map = (uint64_t)bm->buffer_map[i]; - test_map = ~test_map; - last_bit_set = fls64(test_map); - - if (last_bit_set == 0) - continue; - else - j = MIF_BITS_FOR_MAP_CELL - last_bit_set; - - location = (i * MIF_BITS_FOR_MAP_CELL) + j; - - if (location >= bm->cell_count) - break; - - find_flag = true; - bm->buffer_map[i] |= (uint64_t)(MIF_64BIT_FIRST_BIT >> j); - bm->current_map_index = i; - -#ifdef MIF_BUFF_DEBUG - mif_info("map: %016llx\n", bm->buffer_map[i]); - mif_info("i:%d j:%d location:%d\n", i, j, location); -#endif - break; - } - - if (find_flag == false) { - for (i = 0 ; i < bm->current_map_index; i++) { - test_map = (uint64_t)bm->buffer_map[i]; - test_map = ~test_map; - last_bit_set = fls64(test_map); - - if (last_bit_set == 0) - continue; - else - j = MIF_BITS_FOR_MAP_CELL - last_bit_set; - - location = (i * MIF_BITS_FOR_MAP_CELL) + j; - - if (location >= bm->cell_count) - break; - - find_flag = true; - bm->buffer_map[i] |= (uint64_t)(MIF_64BIT_FIRST_BIT >> j); - bm->current_map_index = i; - -#ifdef MIF_BUFF_DEBUG - mif_info("map: %016llx\n", bm->buffer_map[i]); - mif_info("i:%d j:%d location:%d\n", i, j, location); -#endif - break; - } - } - - if (find_flag == false) { -#ifdef MIF_BUFF_DEBUG - mif_info("ERR allocation fail\n"); -#endif - spin_unlock_irqrestore(&bm->lock, flags); - return NULL; - } - - buff_allocated = bm->buffer_start; - buff_allocated += (location * bm->cell_size); - - bm->free_cell_count--; - bm->used_cell_count++; - - spin_unlock_irqrestore(&bm->lock, flags); - -#ifdef MIF_BUFF_DEBUG - mif_info("location:%d cell_size:%u\n", location, bm->cell_size); - mif_info("buffer_allocated:%pK\n", buff_allocated); - mif_info("used/free: %u/%u\n", get_mif_buff_used_count(bm), - get_mif_buff_free_count(bm)); -#endif - - return (void *)buff_allocated; + return &(cpif_driver_version[0]); } -int free_mif_buff(struct mif_buff_mng *bm, void *buffer) +int copy_from_user_memcpy_toio(void __iomem *dst, const void __user *src, size_t count) { - unsigned char *uc_buffer = (unsigned char *)buffer; - unsigned int addr_diff; - int i, j, location; - unsigned long flags; - - if (bm == NULL) - return -1; - - if (buffer == NULL) - return 0; + u8 buf[256]; - addr_diff = (unsigned int)(uc_buffer - bm->buffer_start); + while (count) { + size_t c = count; - if (addr_diff > bm->buffer_size) { - mif_err_limited("ERR Buffer:%pK is not my pool one.\n", uc_buffer); - return -1; - } - - location = addr_diff / bm->cell_size; - i = location / MIF_BITS_FOR_MAP_CELL; - j = location % MIF_BITS_FOR_MAP_CELL; - -#ifdef MIF_BUFF_DEBUG - mif_info("uc_buff:%pK diff:%u\n", uc_buffer, addr_diff); - mif_info("location:%d i:%d j:%d\n", location, i, j); -#endif + if (c > sizeof(buf)) + c = sizeof(buf); + if (copy_from_user(buf, src, c)) + return -EFAULT; - if ((bm->buffer_map[i] & (MIF_64BIT_FIRST_BIT >> j)) == 0) { - mif_err_limited("ERR Buffer:%pK is allready freed\n", uc_buffer); - return -1; + memcpy_toio(dst, buf, c); + count -= c; + dst += c; + src += c; } - spin_lock_irqsave(&bm->lock, flags); - - bm->buffer_map[i] &= ~(MIF_64BIT_FIRST_BIT >> j); - bm->free_cell_count++; - bm->used_cell_count--; - - spin_unlock_irqrestore(&bm->lock, flags); - -#ifdef MIF_BUFF_DEBUG - mif_info("used/free: %u/%u\n", get_mif_buff_used_count(bm), - get_mif_buff_free_count(bm)); -#endif return 0; } - -bool __skb_free_head_cp_zerocopy(struct sk_buff *skb) -{ - struct mif_buff_mng *bm; - - list_for_each_entry(bm, &bm_list, node) { - if ((bm->buffer_start <= skb->head) && (skb->head < bm->buffer_end)) { - free_mif_buff(bm, skb->head); - return true; - } - } - - return false; -} -EXPORT_SYMBOL(__skb_free_head_cp_zerocopy); - -void cpif_enable_sw_zerocopy(void) -{ - struct mif_buff_mng *bm; - - mif_info("enabled\n"); - list_for_each_entry(bm, &bm_list, node) - bm->enable_sw_zerocopy = true; -} -EXPORT_SYMBOL(cpif_enable_sw_zerocopy); - -const char *get_cpif_driver_version(void) -{ - return &(cpif_driver_version[0]); -} diff --git a/drivers/soc/google/cpif/modem_utils.h b/drivers/soc/google/cpif/modem_utils.h index 03a42ae09762..474c57e6bd69 100644 --- a/drivers/soc/google/cpif/modem_utils.h +++ b/drivers/soc/google/cpif/modem_utils.h @@ -11,6 +11,8 @@ #include "modem_prj.h" #include "link_device_memory.h" +#define CP_CPU_BASE_ADDRESS 0x40000000 + #define MIF_TAG "cpif" #define IS_CONNECTED(iod, ld) ((iod)->link_type == (ld)->link_type) @@ -37,6 +39,11 @@ (MAX_LOG_SIZE - sizeof(enum mif_log_id) \ - sizeof(unsigned long long) - sizeof(struct timespec64)) +#define PR_BUFFER_SIZE 128 + +#define PADDR_LO(paddr) ((paddr) & 0xFFFFFFFF) +#define PADDR_HI(paddr) (((paddr) >> 32) & 0xF) + enum mif_log_id { MIF_IPC_RL2AP = 1, MIF_IPC_AP2CP, @@ -213,7 +220,7 @@ static const char * const modem_state_string[] = { [STATE_SIM_ATTACH] = "SIM_ATTACH", [STATE_SIM_DETACH] = "SIM_DETACH", [STATE_CRASH_WATCHDOG] = "WDT_RESET", - [STATE_INIT] = "INIT", + [STATE_RESET] = "RESET", }; static const inline char *cp_state_str(enum modem_state state) @@ -264,31 +271,63 @@ static inline unsigned long ms2ns(unsigned long ms) return ms * 1E6L; } -void get_utc_time(struct utc_time *utc); +static inline void ts642utc(struct timespec64 *ts, struct utc_time *utc) +{ + struct tm tm; + + time64_to_tm((ts->tv_sec - (sys_tz.tz_minuteswest * 60)), 0, &tm); + utc->year = 1900 + (u32)tm.tm_year; + utc->mon = 1 + tm.tm_mon; + utc->day = tm.tm_mday; + utc->hour = tm.tm_hour; + utc->min = tm.tm_min; + utc->sec = tm.tm_sec; + utc->us = (u32)ns2us(ts->tv_nsec); +} -static inline unsigned int calc_offset(void *target, void *base) +static inline void get_utc_time(struct utc_time *utc) { - return (unsigned long)target - (unsigned long)base; + struct timespec64 ts; + + ktime_get_ts64(&ts); + ts642utc(&ts, utc); } -int mif_dump_log(struct modem_shared *, struct io_device *); +/* dump2hex + * dump data to hex as fast as possible. + * the length of @buff must be greater than "@len * 3" + * it need 3 bytes per one data byte to print. + */ +static inline void dump2hex(char *buff, size_t buff_size, + const char *data, size_t data_len) +{ + static const char *hex = "0123456789abcdef"; + char *dest = buff; + size_t len; + size_t i; -#define mif_irq_log(msd, map, data, len) \ - _mif_irq_log(MIF_IRQ, msd, map, data, len) -#define mif_com_log(msd, format, ...) \ - _mif_com_log(MIF_COM, msd, pr_fmt(format), ##__VA_ARGS__) -#define mif_time_log(msd, epoch, data, len) \ - _mif_time_log(MIF_TIME, msd, epoch, data, len) + if (buff_size < (data_len * 3)) + len = buff_size / 3; + else + len = data_len; + + for (i = 0; i < len; i++) { + *dest++ = hex[(data[i] >> 4) & 0xf]; + *dest++ = hex[data[i] & 0xf]; + *dest++ = ' '; + } -void mif_ipc_log(enum mif_log_id id, - struct modem_shared *msd, const char *data, size_t len); -void _mif_irq_log(enum mif_log_id id, - struct modem_shared *msd, struct mif_irq_map irq_map, const char *data, size_t len); -void _mif_com_log(enum mif_log_id id, - struct modem_shared *msd, const char *data, ...); -void _mif_time_log(enum mif_log_id id, - struct modem_shared *msd, struct timespec64 epoch, const char *data, - size_t len); + /* The last character must be overwritten with NULL */ + if (likely(len > 0)) + dest--; + + *dest = 0; +} + +static inline unsigned int calc_offset(void *target, void *base) +{ + return (unsigned long)target - (unsigned long)base; +} static inline struct link_device *find_linkdev(struct modem_shared *msd, u32 link_type) @@ -344,19 +383,9 @@ static inline void pr_skb(const char *tag, struct sk_buff *skb, struct link_devi pr_buffer(tag, (char *)((skb)->data), (size_t)((skb)->len), length); } -/* print a urb as hex string */ -#define pr_urb(tag, urb) \ - pr_buffer(tag, (char *)((urb)->transfer_buffer), \ - (size_t)((urb)->actual_length), (size_t)16) - -/* Stop/wake all TX queues in network interfaces */ -void stop_net_iface(struct link_device *ld, unsigned int channel); -void resume_net_iface(struct link_device *ld, unsigned int channel); -void stop_net_ifaces(struct link_device *ld); -void resume_net_ifaces(struct link_device *ld); - -/* flow control CMD from CP, it use in serial devices */ -int link_rx_flowctl_cmd(struct link_device *ld, const char *data, size_t len); +/* Stop/wake all normal priority TX queues in network interfaces */ +bool stop_net_ifaces(struct link_device *ld, unsigned long set_mask); +void resume_net_ifaces(struct link_device *ld, unsigned long clear_mask); /* Get an IO device */ struct io_device *get_iod_with_format(struct modem_shared *msd, @@ -382,7 +411,7 @@ static inline struct io_device *link_get_iod_with_channel( struct io_device *iod = get_iod_with_channel(ld->msd, channel); struct mem_link_device *mld = ld->mdm_data->mld; - if (!iod && atomic_read(&mld->cp_boot_done)) + if (!iod && atomic_read(&mld->init_end_cnt)) mif_err("No IOD matches channel (%d)\n", channel); return (iod && IS_CONNECTED(iod, ld)) ? iod : NULL; @@ -408,28 +437,10 @@ static inline void iodevs_for_each(struct modem_shared *msd, action_fn action, v } } -/* netif wake/stop queue of iod */ -void iodev_netif_wake(struct io_device *iod, void *args); -void iodev_netif_stop(struct io_device *iod, void *args); - -/* netif wake/stop queue of iod having activated ndev */ -void netif_tx_flowctl(struct modem_shared *msd, bool tx_stop); - __be32 ipv4str_to_be32(const char *ipv4str, size_t count); void mif_add_timer(struct timer_list *timer, unsigned long expire, -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) void (*function)(struct timer_list *)); -#else - void (*function)(unsigned long), unsigned long data); -#endif - -/* debug helper functions for sipc4, sipc5 */ -void mif_print_data(const u8 *data, int len); - -void mif_dump2format16(const u8 *data, int len, char *buff, char *tag); -void mif_dump2format4(const u8 *data, int len, char *buff, char *tag); -void mif_print_dump(const u8 *data, int len, int width); /* * --------------------------------------------------------------------------- @@ -509,9 +520,9 @@ void mif_print_dump(const u8 *data, int len, int width); */ #define UDP_HDR_SIZE 8 +#ifdef DEBUG_MODEM_IF_IP_DATA void print_ipv4_packet(const u8 *ip_pkt, enum direction dir); -bool is_dns_packet(const u8 *ip_pkt); -bool is_syn_packet(const u8 *ip_pkt); +#endif void mif_init_irq(struct modem_irq *irq, unsigned int num, const char *name, unsigned long flags); @@ -526,28 +537,6 @@ struct file *mif_open_file(const char *path); void mif_save_file(struct file *fp, const char *buff, size_t size); void mif_close_file(struct file *fp); -int board_gpio_export(struct device *dev, - unsigned int gpio, bool dir, const char *name); - -void make_gpio_floating(unsigned int gpio, bool floating); - -#if IS_ENABLED(CONFIG_ARGOS) -/* kernel team needs to provide argos header file. !!! - * As of now, there's nothing to use. - */ -#if IS_ENABLED(CONFIG_SCHED_HMP) -extern struct cpumask hmp_slow_cpu_mask; -extern struct cpumask hmp_fast_cpu_mask; -#endif - -int argos_irq_affinity_setup_label(unsigned int irq, const char *label, - struct cpumask *affinity_cpu_mask, - struct cpumask *default_cpu_mask); -int argos_task_affinity_setup_label(struct task_struct *p, const char *label, - struct cpumask *affinity_cpu_mask, - struct cpumask *default_cpu_mask); -#endif - void mif_stop_logging(void); void set_wakeup_packet_log(bool enable); @@ -561,65 +550,12 @@ void set_wakeup_packet_log(bool enable); * sizeof(struct skb_shared_info): 512 * 2048 + 512 = 2560 (0xA00) */ -#define MIF_BUFF_DEFAULT_PACKET_SIZE (2048) -#define MIF_BUFF_CELL_PADDING_SIZE (512) -#define MIF_BUFF_DEFAULT_CELL_SIZE (MIF_BUFF_DEFAULT_PACKET_SIZE+MIF_BUFF_CELL_PADDING_SIZE) -#define MIF_BUFF_MAP_CELL_SIZE (sizeof(uint64_t)) -#define MIF_BITS_FOR_BYTE (8) -#define MIF_BITS_FOR_MAP_CELL (MIF_BUFF_MAP_CELL_SIZE * MIF_BITS_FOR_BYTE) -#define MIF_64BIT_FIRST_BIT (0x8000000000000000ULL) - -struct mif_buff_mng { - unsigned char *buffer_start; - unsigned char *buffer_end; - unsigned int buffer_size; - unsigned int cell_size; - - unsigned int cell_count; - unsigned int used_cell_count; - unsigned int free_cell_count; - - spinlock_t lock; - - uint64_t *buffer_map; - unsigned int buffer_map_size; - int current_map_index; - - struct list_head node; - - bool enable_sw_zerocopy; -}; - -struct mif_buff_mng *init_mif_buff_mng(unsigned char *buffer_start, - unsigned int buffer_size, unsigned int cell_size); -void exit_mif_buff_mng(struct mif_buff_mng *bm); -void *alloc_mif_buff(struct mif_buff_mng *bm); -int free_mif_buff(struct mif_buff_mng *bm, void *buffer); - -static inline unsigned int get_mif_buff_free_count(struct mif_buff_mng *bm) -{ - if (bm) - return bm->free_cell_count; - else - return 0; -} - -static inline unsigned int get_mif_buff_used_count(struct mif_buff_mng *bm) -{ - if (bm) - return bm->used_cell_count; - else - return 0; -} - -extern struct mif_buff_mng *g_mif_buff_mng; -void set_dflags(unsigned long flag); +#define MIF_BUFF_DEFAULT_PACKET_SIZE (2048) +#define MIF_BUFF_CELL_PADDING_SIZE (512) +#define MIF_BUFF_DEFAULT_CELL_SIZE (MIF_BUFF_DEFAULT_PACKET_SIZE+MIF_BUFF_CELL_PADDING_SIZE) const char *get_cpif_driver_version(void); -extern bool __skb_free_head_cp_zerocopy(struct sk_buff *skb); -extern void cpif_enable_sw_zerocopy(void); - static inline struct wakeup_source *cpif_wake_lock_register(struct device *dev, const char *name) { struct wakeup_source *ws = NULL; @@ -683,4 +619,6 @@ static inline int cpif_wake_lock_active(struct wakeup_source *ws) return ws->active; } +int copy_from_user_memcpy_toio(void __iomem *dst, const void __user *src, size_t count); + #endif/*__MODEM_UTILS_H__*/ diff --git a/drivers/soc/google/cpif/modem_v1.h b/drivers/soc/google/cpif/modem_v1.h index 49ad45f49fb0..954d42807410 100644 --- a/drivers/soc/google/cpif/modem_v1.h +++ b/drivers/soc/google/cpif/modem_v1.h @@ -11,8 +11,8 @@ #include #include #include -#include #include +#include #include "cp_btl.h" @@ -25,24 +25,11 @@ #define SSS_CLK_ENABLE 0 #define SSS_CLK_DISABLE 1 -enum modem_network { - UMTS_NETWORK, - CDMA_NETWORK, - TDSCDMA_NETWORK, - LTE_NETWORK, - MAX_MODEM_NETWORK -}; - struct __packed multi_frame_control { u8 id:7, more:1; }; -enum io_mode { - PIO, - DMA -}; - enum direction { TX = 0, UL = 0, @@ -61,9 +48,6 @@ enum read_write { RDWR = 2 }; -#define STR_CP_FAIL "cp_fail" -#define STR_CP_WDT "cp_wdt" /* CP watchdog timer */ - /** * struct modem_io_t - declaration for io_device * @name: device name @@ -85,81 +69,63 @@ struct modem_io_t { u32 link_type; u32 attrs; char *option_region; - /*IS_ENABLED(CONFIG_LINK_DEVICE_MEMORY_SBD)*/ unsigned int ul_num_buffers; unsigned int ul_buffer_size; unsigned int dl_num_buffers; unsigned int dl_buffer_size; }; -struct modemlink_pm_data { - char *name; - struct device *dev; - /* link power control 2 types : pin & regulator control */ - int (*link_ldo_enable)(bool enable); - unsigned int gpio_link_enable; - unsigned int gpio_link_active; - unsigned int gpio_link_hostwake; - unsigned int gpio_link_slavewake; - int (*link_reconnect)(void *reconnect); - - /* usb hub only */ - int (*port_enable)(int i, int j); - int (*hub_standby)(void *standby); - void *hub_pm_data; - bool has_usbhub; - - /* cpu/bus frequency lock */ - atomic_t freqlock; - int (*freq_lock)(struct device *dev); - int (*freq_unlock)(struct device *dev); - - int autosuspend_delay_ms; /* if zero, the default value is used */ - void (*ehci_reg_dump)(struct device *dev); -}; - -struct modemlink_pm_link_activectl { - int gpio_initialized; - int gpio_request_host_active; -}; - #if IS_ENABLED(CONFIG_LINK_DEVICE_SHMEM) || IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) -enum shmem_type { - REAL_SHMEM, - C2C_SHMEM, - MAX_SHMEM_TYPE -}; - struct modem_mbox { - unsigned int mbx_ap2cp_msg; - unsigned int mbx_cp2ap_msg; - unsigned int mbx_ap2cp_wakeup; /* CP_WAKEUP */ - unsigned int mbx_cp2ap_wakeup; /* AP_WAKEUP */ - unsigned int mbx_ap2cp_status; /* AP_STATUS */ - unsigned int mbx_cp2ap_status; /* CP_STATUS */ - unsigned int mbx_cp2ap_wakelock; /* Wakelock for VoLTE */ - unsigned int mbx_cp2ap_ratmode; /* Wakelock for pcie */ - unsigned int mbx_ap2cp_kerneltime; /* Kernel time */ - unsigned int int_ap2cp_msg; unsigned int int_ap2cp_active; unsigned int int_ap2cp_wakeup; unsigned int int_ap2cp_status; +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) unsigned int int_ap2cp_lcd_status; +#endif +#if IS_ENABLED(CONFIG_CP_LLC) unsigned int int_ap2cp_llc_status; +#endif +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + unsigned int int_ap2cp_clatinfo_send; +#endif +#if IS_ENABLED(CONFIG_LINK_DEVICE_PCIE) + unsigned int int_ap2cp_pcie_link_ack; +#endif unsigned int int_ap2cp_uart_noti; unsigned int irq_cp2ap_msg; unsigned int irq_cp2ap_status; unsigned int irq_cp2ap_active; +#if IS_ENABLED(CONFIG_CP_LLC) unsigned int irq_cp2ap_llc_status; - unsigned int irq_cp2ap_wakeup; +#endif +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + unsigned int irq_cp2ap_clatinfo_ack; +#endif unsigned int irq_cp2ap_wakelock; unsigned int irq_cp2ap_rat_mode; - unsigned int irq_cp2ap_change_ul_path; }; #endif +#define AP_CP_CAP_PARTS 2 +#define AP_CP_CAP_PART_LEN 4 +#define AP_CP_CAP_BIT_MAX 32 + +/* AP capability[0] index */ +enum ap_capability_0_bits { + AP_CAP_0_PKTPROC_UL_BIT = 0, + AP_CAP_0_CH_EXTENSION_BIT, + AP_CAP_0_PKTPROC_36BIT_ADDR_BIT, + AP_CAP_0_MAX = AP_CP_CAP_BIT_MAX +}; + +/* AP capability[1] index */ +enum ap_capability_1_bits { + AP_CAP_1_MAX = AP_CP_CAP_BIT_MAX +}; + /* platform data */ struct modem_data { char *name; @@ -169,7 +135,6 @@ struct modem_data { struct mem_link_device *mld; /* Modem component */ - enum modem_network modem_net; u32 modem_type; u32 link_type; @@ -192,12 +157,6 @@ struct modem_data { /* check if cp2ap_active is in alive */ u32 cp2ap_active_not_alive; - /* Modem link PM support */ - struct modemlink_pm_data *link_pm_data; - - /* SIM Detect polarity */ - bool sim_polarity; - /* legacy buffer setting */ u32 legacy_fmt_head_tail_offset; u32 legacy_fmt_buffer_offset; @@ -207,6 +166,7 @@ struct modem_data { u32 legacy_raw_buffer_offset; u32 legacy_raw_txq_size; u32 legacy_raw_rxq_size; + u32 legacy_raw_rx_buffer_cached; /* several 4 byte length info in ipc region */ u32 offset_ap_version; @@ -222,8 +182,18 @@ struct modem_data { u32 cp2ap_msg[2]; u32 cp2ap_united_status[2]; u32 ap2cp_united_status[2]; +#if IS_ENABLED(CONFIG_CP_LLC) u32 ap2cp_llc_status[2]; u32 cp2ap_llc_status[2]; +#endif +#if IS_ENABLED(CONFIG_CP_PKTPROC_CLAT) + u32 ap2cp_clatinfo_xlat_v4_addr[2]; + u32 ap2cp_clatinfo_xlat_addr_0[2]; + u32 ap2cp_clatinfo_xlat_addr_1[2]; + u32 ap2cp_clatinfo_xlat_addr_2[2]; + u32 ap2cp_clatinfo_xlat_addr_3[2]; + u32 ap2cp_clatinfo_index[2]; +#endif u32 ap2cp_kerneltime[2]; u32 ap2cp_kerneltime_sec[2]; u32 ap2cp_kerneltime_usec[2]; @@ -255,8 +225,10 @@ struct modem_data { unsigned int sbi_crash_type_pos; unsigned int sbi_ds_det_mask; unsigned int sbi_ds_det_pos; +#if IS_ENABLED(CONFIG_CP_LCD_NOTIFIER) unsigned int sbi_lcd_status_mask; unsigned int sbi_lcd_status_pos; +#endif /* ulpath offset for 2CP models */ u32 ulpath_offset; @@ -276,8 +248,7 @@ struct modem_data { /* capability */ u32 capability_offset; - u32 ap_capability_0; - u32 ap_capability_1; + u32 ap_capability[AP_CP_CAP_PARTS]; #if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) /* SIT priority queue info */ @@ -288,8 +259,30 @@ struct modem_data { #endif struct cp_btl btl; /* CP background trace log */ - void (*gpio_revers_bias_clear)(void); - void (*gpio_revers_bias_restore)(void); + u32 pktproc_use_36bit_addr; /* Check pktproc use 36bit addr */ +}; + +enum cp_gpio_type { + CP_GPIO_AP2CP_CP_PWR, + CP_GPIO_AP2CP_NRESET, + CP_GPIO_AP2CP_WAKEUP, + CP_GPIO_AP2CP_DUMP_NOTI, + CP_GPIO_AP2CP_AP_ACTIVE, +#if !IS_ENABLED(CONFIG_CP_WRESET_WA) + CP_GPIO_AP2CP_CP_WRST_N, + CP_GPIO_AP2CP_PM_WRST_N, +#endif + CP_GPIO_CP2AP_PS_HOLD, + CP_GPIO_CP2AP_WAKEUP, + CP_GPIO_CP2AP_CP_ACTIVE, + CP_GPIO_MAX +}; + +enum cp_gpio_irq_type { + CP_GPIO_IRQ_NONE, + CP_GPIO_IRQ_CP2AP_WAKEUP, + CP_GPIO_IRQ_CP2AP_CP_ACTIVE, + CP_GPIO_IRQ_MAX }; struct modem_irq { @@ -303,11 +296,13 @@ struct modem_irq { }; struct cpif_gpio { + bool valid; int num; + enum cp_gpio_irq_type irq_type; const char *label; + const char *node_name; }; -#if IS_ENABLED(CONFIG_OF) #define mif_dt_read_enum(np, prop, dest) \ do { \ u32 val; \ @@ -353,10 +348,51 @@ struct cpif_gpio { if (!of_property_read_u32(np, prop, &val)) \ dest = val; \ } while (0) -#endif + +#define mif_dt_read_u64(np, prop, dest) \ + do { \ + u64 val; \ + if (of_property_read_u64(np, prop, &val)) { \ + mif_err("%s is not defined\n", prop); \ + return -EINVAL; \ + } \ + dest = val; \ + } while (0) + +#define mif_dt_read_u64_noerr(np, prop, dest) \ + do { \ + u64 val; \ + if (!of_property_read_u64(np, prop, &val)) \ + dest = val; \ + } while (0) + +#define mif_dt_count_u32_elems(np, prop, dest) \ + do { \ + int val; \ + val = of_property_count_u32_elems(np, prop); \ + if (val < 0) { \ + mif_err("can not get %s\n", prop); \ + return -EINVAL; \ + } \ + dest = (u32)val; \ + } while (0) + +#define mif_dt_count_u32_array(np, prop, dest, size) \ + do { \ + int val; \ + val = of_property_read_u32_array(np, prop, dest, size); \ + if (val < 0) { \ + mif_err("can not get %s %d\n", prop, size); \ + return -EINVAL; \ + } \ + } while (0) + + +#define cpif_set_bit(data, offset) ((data) |= BIT(offset)) +#define cpif_clear_bit(data, offset) ((data) &= ~BIT(offset)) +#define cpif_check_bit(data, offset) ((data) & BIT(offset)) #define LOG_TAG "cpif: " -#define FUNC (__func__) #define CALLER (__builtin_return_address(0)) #define mif_err_limited(fmt, ...) \ diff --git a/drivers/soc/google/cpif/net_io_device.c b/drivers/soc/google/cpif/net_io_device.c index b06e413fb2c4..f0de411a2d9c 100644 --- a/drivers/soc/google/cpif/net_io_device.c +++ b/drivers/soc/google/cpif/net_io_device.c @@ -31,19 +31,6 @@ #include "cpif_qos_info.h" #endif -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) || IS_ENABLED(CONFIG_CP_PKTPROC) -static int vnet_init(struct net_device *ndev) -{ - struct vnet *vnet = netdev_priv(ndev); - - vnet->free_head = __skb_free_head_cp_zerocopy; - if (vnet->enable_zerocopy) - cpif_enable_sw_zerocopy(); - - return 0; -} -#endif - static int vnet_open(struct net_device *ndev) { struct vnet *vnet = netdev_priv(ndev); @@ -116,14 +103,7 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) unsigned int headroom; unsigned int tailroom; unsigned int tx_bytes; -#ifdef DEBUG_MODEM_IF struct timespec64 ts; -#endif - -#ifdef DEBUG_MODEM_IF - /* Record the timestamp */ - ktime_get_ts64(&ts); -#endif if (unlikely(!cp_online(mc))) { if (!netif_queue_stopped(ndev)) @@ -132,6 +112,9 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) goto drop; } + /* Record the timestamp */ + ktime_get_ts64(&ts); + #if IS_ENABLED(CONFIG_CP_PKTPROC_UL) /* no need of head and tail */ cfg = 0; @@ -182,16 +165,20 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) skbpriv(skb_new)->lnk_hdr = iod->link_header; skbpriv(skb_new)->sipc_ch = iod->ch; -#ifdef DEBUG_MODEM_IF /* Copy the timestamp to the skb */ skbpriv(skb_new)->ts = ts; -#endif #if defined(DEBUG_MODEM_IF_IODEV_TX) && defined(DEBUG_MODEM_IF_PS_DATA) mif_pkt(iod->ch, "IOD-TX", skb_new); #endif /* Build SIPC5 link header*/ +#if IS_ENABLED(CONFIG_CP_PKTPROC_UL) + buff = skb_new->data; +#else buff = skb_push(skb_new, headroom); +#endif + +#if !IS_ENABLED(CONFIG_CP_PKTPROC_UL) if (cfg || cfg_sit) { switch (ld->protocol) { case PROTOCOL_SIPC: @@ -205,6 +192,7 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) return -EINVAL; } } +#endif /* IP loop-back */ if (iod->msd->loopback_ipaddr) { @@ -216,9 +204,11 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) } } +#if !IS_ENABLED(CONFIG_CP_PKTPROC_UL) /* Apply padding */ if (tailroom) skb_put(skb_new, tailroom); +#endif ret = ld->send(ld, iod, skb_new); if (unlikely(ret < 0)) { @@ -285,28 +275,36 @@ static netdev_tx_t vnet_xmit(struct sk_buff *skb, struct net_device *ndev) static bool _is_tcp_ack(struct sk_buff *skb) { + u16 payload_len = 0; + switch (skb->protocol) { - /* TCPv4 ACKs */ case htons(ETH_P_IP): - if ((ip_hdr(skb)->protocol == IPPROTO_TCP) && - (ntohs(ip_hdr(skb)->tot_len) - (ip_hdr(skb)->ihl << 2) == - tcp_hdr(skb)->doff << 2) && - ((tcp_flag_word(tcp_hdr(skb)) & - cpu_to_be32(0x00FF0000)) == TCP_FLAG_ACK)) - return true; - break; + if (ip_hdr(skb)->protocol != IPPROTO_TCP) + return false; - /* TCPv6 ACKs */ + if (skb->network_header == skb->transport_header) + skb->transport_header += (ip_hdr(skb)->ihl << 2); + payload_len = ntohs(ip_hdr(skb)->tot_len) - (ip_hdr(skb)->ihl << 2); + break; case htons(ETH_P_IPV6): - if ((ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) && - (ntohs(ipv6_hdr(skb)->payload_len) == - (tcp_hdr(skb)->doff) << 2) && - ((tcp_flag_word(tcp_hdr(skb)) & - cpu_to_be32(0x00FF0000)) == TCP_FLAG_ACK)) - return true; + if (ipv6_hdr(skb)->nexthdr != IPPROTO_TCP) + return false; + + if (skb->network_header == skb->transport_header) + skb->transport_header += sizeof(struct ipv6hdr); + payload_len = ntohs(ipv6_hdr(skb)->payload_len); + break; + default: break; } + if (!payload_len) + return false; + + if (payload_len == (tcp_hdr(skb)->doff << 2) && + (tcp_flag_word(tcp_hdr(skb)) & cpu_to_be32(0x00FF0000)) == TCP_FLAG_ACK) + return true; + return false; } @@ -321,35 +319,34 @@ static inline bool is_tcp_ack(struct sk_buff *skb) return false; } -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) || IS_ENABLED(CONFIG_MODEM_IF_QOS) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 4, 0)) +#if IS_ENABLED(CONFIG_MODEM_IF_QOS) static u16 vnet_select_queue(struct net_device *dev, struct sk_buff *skb, struct net_device *sb_dev) -#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) -static u16 vnet_select_queue(struct net_device *dev, struct sk_buff *skb, - struct net_device *sb_dev, select_queue_fallback_t fallback) -#else -static u16 vnet_select_queue(struct net_device *dev, struct sk_buff *skb, - void *accel_priv, select_queue_fallback_t fallback) -#endif { -#if IS_ENABLED(CONFIG_MODEM_IF_QOS) - return (skb && is_tcp_ack(skb)) ? 1 : 0; -#elif IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) - return ((skb && skb->truesize == 2) || - (skb && skb->sk && cpif_qos_get_node(skb->sk->sk_uid.val))) ? 1 : 0; +#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) + struct vnet *vnet = netdev_priv(dev); +#endif + + if (!skb) + return 0; + + if (is_tcp_ack(skb)) + return 1; + +#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) + if (!vnet->hiprio_ack_only && skb->sk && cpif_qos_get_node(skb->sk->sk_uid.val)) + return 1; #endif + + return 0; } #endif static const struct net_device_ops vnet_ops = { -#if IS_ENABLED(CONFIG_CP_ZEROCOPY) || IS_ENABLED(CONFIG_CP_PKTPROC) - .ndo_init = vnet_init, -#endif .ndo_open = vnet_open, .ndo_stop = vnet_stop, .ndo_start_xmit = vnet_xmit, -#if IS_ENABLED(CONFIG_MODEM_IF_LEGACY_QOS) || IS_ENABLED(CONFIG_MODEM_IF_QOS) +#if IS_ENABLED(CONFIG_MODEM_IF_QOS) .ndo_select_queue = vnet_select_queue, #endif }; diff --git a/drivers/soc/google/cpif/s51xx_pcie.c b/drivers/soc/google/cpif/s51xx_pcie.c index 972592402fa8..d8958f41b902 100644 --- a/drivers/soc/google/cpif/s51xx_pcie.c +++ b/drivers/soc/google/cpif/s51xx_pcie.c @@ -36,11 +36,12 @@ #include "modem_prj.h" #include "modem_utils.h" +#include "modem_ctrl.h" #include "s51xx_pcie.h" static int s51xx_pcie_read_procmem(struct seq_file *m, void *v) { - pr_err("Procmem READ!\n"); + mif_info("Procmem READ!\n"); return 0; } @@ -76,6 +77,8 @@ void s51xx_pcie_chk_ep_conf(struct pci_dev *pdev) inline int s51xx_pcie_send_doorbell_int(struct pci_dev *pdev, int int_num) { struct s51xx_pcie *s51xx_pcie = pci_get_drvdata(pdev); + struct pci_driver *driver = pdev->driver; + struct modem_ctl *mc = container_of(driver, struct modem_ctl, pci_driver); u32 reg, count = 0; int cnt = 0; u16 cmd; @@ -85,9 +88,15 @@ inline int s51xx_pcie_send_doorbell_int(struct pci_dev *pdev, int int_num) return -EAGAIN; } + if (exynos_pcie_rc_get_cpl_timeout_state(s51xx_pcie->pcie_channel_num)) { + mif_err_limited("Can't send Interrupt(cto_retry_cnt: %d)!!!\n", + mc->pcie_cto_retry_cnt); + return 0; + } + if (s51xx_check_pcie_link_status(s51xx_pcie->pcie_channel_num) == 0) { mif_err_limited("Can't send Interrupt(not linked)!!!\n"); - return -EAGAIN; + goto check_cpl_timeout; } pci_read_config_word(pdev, PCI_COMMAND, &cmd); @@ -120,7 +129,7 @@ inline int s51xx_pcie_send_doorbell_int(struct pci_dev *pdev, int int_num) mif_err_limited("BME is not set(cnt=%d)\n", cnt); exynos_pcie_rc_register_dump( s51xx_pcie->pcie_channel_num); - return -EAGAIN; + goto check_cpl_timeout; } } @@ -141,20 +150,31 @@ inline int s51xx_pcie_send_doorbell_int(struct pci_dev *pdev, int int_num) if (!in_interrupt()) udelay(1000); /* 1ms */ else { - mif_err_limited("Can't send doorbell in interrupt mode (0x%08X)\n" - , reg); + mif_err_limited("Can't send doorbell in interrupt mode (0x%08X)\n", + reg); return 0; } goto send_doorbell_again; } mif_err("[Need to CHECK] Can't send doorbell int (0x%x)\n", reg); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, ®); + mif_err("Check BAR0 register : %#x\n", reg); exynos_pcie_rc_register_dump(s51xx_pcie->pcie_channel_num); - return -EAGAIN; + goto check_cpl_timeout; } return 0; + +check_cpl_timeout: + if (exynos_pcie_rc_get_cpl_timeout_state(s51xx_pcie->pcie_channel_num)) { + mif_err_limited("Can't send Interrupt(cto_retry_cnt: %d)!!!\n", + mc->pcie_cto_retry_cnt); + return 0; + } + + return -EAGAIN; } void first_save_s51xx_status(struct pci_dev *pdev) @@ -171,7 +191,7 @@ void first_save_s51xx_status(struct pci_dev *pdev) if (s51xx_pcie->pci_saved_configs == NULL) mif_err("MSI-DBG: s51xx pcie.pci_saved_configs is NULL(s51xx config NOT saved)\n"); else - mif_err("first s51xx config status save: done\n"); + mif_info("first s51xx config status save: done\n"); } void s51xx_pcie_save_state(struct pci_dev *pdev) @@ -215,9 +235,6 @@ void s51xx_pcie_save_state(struct pci_dev *pdev) void s51xx_pcie_restore_state(struct pci_dev *pdev) { struct s51xx_pcie *s51xx_pcie = pci_get_drvdata(pdev); - struct pci_driver *driver = pdev->driver; - struct modem_ctl *mc = container_of(driver, struct modem_ctl, pci_driver); - int ret; u32 val; @@ -247,7 +264,9 @@ void s51xx_pcie_restore_state(struct pci_dev *pdev) ret = pci_enable_device(pdev); if (ret) - pr_err("Can't enable PCIe Device after linkup!\n"); + mif_err("Can't enable PCIe Device after linkup!\n"); + + dev_info(&pdev->dev, "[%s] PCIe RC bme bit setting\n", __func__); pci_set_master(pdev); /* DBG: print out EP config values after restore_state */ @@ -255,22 +274,17 @@ void s51xx_pcie_restore_state(struct pci_dev *pdev) /* BAR0 value correction */ pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &val); - dev_dbg(&pdev->dev, "[%s]restored:PCI_BASE_ADDRESS_0 = 0x%x\n", __func__, val); - if ((val & 0xfffffff0) != 0x40000000) { - pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x40000000); + dev_dbg(&pdev->dev, "restored:PCI_BASE_ADDRESS_0 = %#x\n", val); + if ((val & PCI_BASE_ADDRESS_MEM_MASK) != s51xx_pcie->dbaddr_changed_base) { + pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, + s51xx_pcie->dbaddr_changed_base); pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, 0x0); - mif_info("write BAR0 value: 0x40000000\n"); - dev_info(&pdev->dev, "[%s]:VALUE CHECK\n", __func__); + mif_info("write BAR0 value: %#x\n", s51xx_pcie->dbaddr_changed_base); s51xx_pcie_chk_ep_conf(pdev); } /* Enable L1.2 after PCIe power on */ - if (mc->phone_state == STATE_CRASH_EXIT) { - pr_err("Disable L1.2 on CP CRASH!!!\n"); - s51xx_pcie_l1ss_ctrl(0, s51xx_pcie->pcie_channel_num); - } else { - s51xx_pcie_l1ss_ctrl(1, s51xx_pcie->pcie_channel_num); - } + s51xx_pcie_l1ss_ctrl(1, s51xx_pcie->pcie_channel_num); s51xx_pcie->link_status = 1; /* pci_pme_active(s51xx_pcie.s51xx_pdev, 1); */ @@ -278,20 +292,12 @@ void s51xx_pcie_restore_state(struct pci_dev *pdev) int s51xx_check_pcie_link_status(int ch_num) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) return exynos_pcie_rc_chk_link_status(ch_num); -#else - return exynos_check_pcie_link_status(ch_num); -#endif } void s51xx_pcie_l1ss_ctrl(int enable, int ch_num) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) exynos_pcie_rc_l1ss_ctrl(enable, PCIE_L1SS_CTRL_MODEM_IF, ch_num); -#else - exynos_pcie_host_v1_l1ss_ctrl(enable, PCIE_L1SS_CTRL_MODEM_IF); -#endif } void disable_msi_int(struct pci_dev *pdev) @@ -312,40 +318,46 @@ int s51xx_pcie_request_msi_int(struct pci_dev *pdev, int int_num) int err = -EFAULT; if (int_num > MAX_MSI_NUM) { - pr_err("Too many MSI interrupts are requested(<=16)!!!\n"); + mif_err("Too many MSI interrupts are requested(<=16)!!!\n"); return -EFAULT; } -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) - /* old kernel(KC+S359): - * err = __pci_enable_msi_range(s51xx_pcie.s51xx_pdev, int_num, int_num); - */ err = pci_alloc_irq_vectors_affinity(pdev, int_num, int_num, PCI_IRQ_MSI, NULL); -#else - err = pci_enable_msi_block(pdev, int_num); -#endif - if (err <= 0) { - pr_err("Can't get msi IRQ!!!!!\n"); + mif_err("Can't get msi IRQ!!!!!\n"); return -EFAULT; } return pdev->irq; } -static void s51xx_pcie_linkdown_cb(struct exynos_pcie_notify *noti) +static void s51xx_pcie_event_cb(struct exynos_pcie_notify *noti) { struct pci_dev *pdev = (struct pci_dev *)noti->user; struct pci_driver *driver = pdev->driver; struct modem_ctl *mc = container_of(driver, struct modem_ctl, pci_driver); + int event = noti->event; - pr_err("s51xx Link-Down notification callback function!!!\n"); + mif_err("0x%X pcie event received!\n", event); - if (mc->pcie_powered_on == false) { - pr_info("%s: skip cp crash during dislink sequence\n", __func__); - exynos_pcie_set_perst_gpio(mc->pcie_ch_num, 0); - } else { - s5100_force_crash_exit_ext(); + if (event & EXYNOS_PCIE_EVENT_LINKDOWN) { + if (mc->pcie_powered_on == false) { + mif_info("skip cp crash during dislink sequence\n"); + exynos_pcie_set_perst_gpio(mc->pcie_ch_num, 0); + } else { + s5100_force_crash_exit_ext(); + } + } else if (event & EXYNOS_PCIE_EVENT_CPL_TIMEOUT) { + mif_err("s51xx CPL_TIMEOUT notification callback function!!!\n"); + mif_err("CPL: a=%d c=%d\n", mc->pcie_cto_retry_cnt_all++, mc->pcie_cto_retry_cnt); + + if (mc->pcie_cto_retry_cnt++ < 10) { + mif_err("[%d] retry pcie poweron !!!\n", mc->pcie_cto_retry_cnt); + queue_work_on(2, mc->wakeup_wq, &mc->wakeup_work); + } else { + mif_err("[%d] force crash !!!\n", mc->pcie_cto_retry_cnt); + s5100_force_crash_exit_ext(); + } } } @@ -384,10 +396,11 @@ static int s51xx_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *en pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &val); val &= PCI_BASE_ADDRESS_MEM_MASK; s51xx_pcie->dbaddr_offset = db_addr - val; + s51xx_pcie->dbaddr_changed_base = val; dev_info(dev, "db_addr : 0x%x , val : 0x%x, offset : 0x%x\n", db_addr, val, (unsigned int)s51xx_pcie->dbaddr_offset); - pr_err("Disable BAR resources.\n"); + mif_info("Disable BAR resources.\n"); for (i = 0; i < 6; i++) { pdev->resource[i].start = 0x0; pdev->resource[i].end = 0x0; @@ -406,7 +419,7 @@ static int s51xx_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *en dev_info(&bus_self->dev, "[%s] BAR %d: tmp rsc : %pR\n", __func__, resno, tmp_rsc); s51xx_pcie->dbaddr_base = tmp_rsc->start; - pr_err("Set Doorbell register address.\n"); + mif_info("Set Doorbell register address.\n"); s51xx_pcie->doorbell_addr = devm_ioremap(&pdev->dev, s51xx_pcie->dbaddr_base + s51xx_pcie->dbaddr_offset, SZ_4); @@ -417,21 +430,22 @@ static int s51xx_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *en * dev_err(dev, "PCIe doorbell setting for ABOX is failed\n"); */ - pr_info("s51xx_pcie.doorbell_addr = %p (start 0x%lx offset : %lx)\n", + mif_info("s51xx_pcie.doorbell_addr = %p (start 0x%lx offset : %lx)\n", s51xx_pcie->doorbell_addr, (unsigned long)s51xx_pcie->dbaddr_base, (unsigned long)s51xx_pcie->dbaddr_offset); if (s51xx_pcie->doorbell_addr == NULL) - pr_err("Can't ioremap doorbell address!!!\n"); + mif_err("Can't ioremap doorbell address!!!\n"); - pr_info("Register PCIE notification LINKDOWN event...\n"); - s51xx_pcie->pcie_event.events = EXYNOS_PCIE_EVENT_LINKDOWN; + mif_info("Register PCIE notification LINKDOWN and CPL_TIMEOUT events...\n"); + s51xx_pcie->pcie_event.events = + EXYNOS_PCIE_EVENT_LINKDOWN | EXYNOS_PCIE_EVENT_CPL_TIMEOUT; s51xx_pcie->pcie_event.user = pdev; s51xx_pcie->pcie_event.mode = EXYNOS_PCIE_TRIGGER_CALLBACK; - s51xx_pcie->pcie_event.callback = s51xx_pcie_linkdown_cb; + s51xx_pcie->pcie_event.callback = s51xx_pcie_event_cb; exynos_pcie_register_event(&s51xx_pcie->pcie_event); - pr_err("Enable PCI device...\n"); + mif_info("Enable PCI device...\n"); ret = pci_enable_device(pdev); pci_set_master(pdev); @@ -479,7 +493,7 @@ static void s51xx_pcie_remove(struct pci_dev *pdev) { struct s51xx_pcie *s51xx_pcie = pci_get_drvdata(pdev); - pr_err("s51xx PCIe Remove!!!\n"); + mif_err("s51xx PCIe Remove!!!\n"); if (s51xx_pcie->pci_saved_configs) kfree(s51xx_pcie->pci_saved_configs); @@ -510,7 +524,7 @@ int s51xx_pcie_init(struct modem_ctl *mc) int ch_num = mc->pcie_ch_num; int ret; - pr_err("Register PCIE drvier for s51xx.(chNum: %d, mc: 0x%p)\n", ch_num, mc); + mif_info("Register PCIE drvier for s51xx.(chNum: %d, mc: 0x%p)\n", ch_num, mc); mc->pci_driver = s51xx_driver; diff --git a/drivers/soc/google/cpif/s51xx_pcie.h b/drivers/soc/google/cpif/s51xx_pcie.h index 5502dfb7e15c..4f4e5cb42756 100644 --- a/drivers/soc/google/cpif/s51xx_pcie.h +++ b/drivers/soc/google/cpif/s51xx_pcie.h @@ -17,7 +17,10 @@ extern int exynos_pcie_register_event(struct exynos_pcie_register_event *reg); extern int exynos_pcie_deregister_event(struct exynos_pcie_register_event *reg); extern void exynos_pcie_rc_register_dump(int ch_num); +extern void exynos_pcie_rc_print_msi_register(int ch_num); extern int exynos_pcie_rc_set_outbound_atu(int ch_num, u32 target_addr, u32 offset, u32 size); +extern bool exynos_pcie_rc_get_cpl_timeout_state(int ch_num); +extern void exynos_pcie_rc_set_cpl_timeout_state(int ch_num, bool recovery); struct s51xx_pcie { unsigned int busdev_num; @@ -28,31 +31,30 @@ struct s51xx_pcie { u32 __iomem *reg_base; u64 dbaddr_base; u32 dbaddr_offset; + u32 dbaddr_changed_base; u32 link_status; bool suspend_try; struct exynos_pcie_register_event pcie_event; + struct exynos_pcie_register_event pcie_cpl_timeout_event; struct pci_saved_state *pci_saved_configs; }; //extern struct s51xx_pcie s5100pcie; -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) extern int exynos_pcie_rc_chk_link_status(int ch_num); extern int exynos_pcie_rc_l1ss_ctrl(int enable, int id, int ch_num); -#else -extern int exynos_check_pcie_link_status(int ch_num); -extern int exynos_pcie_host_v1_l1ss_ctrl(int enable, int id); -#endif -extern int exynos_pcie_poweron(int ch_num); +extern int exynos_pcie_poweron(int ch_num, int spd); extern int exynos_pcie_poweroff(int ch_num); extern void exynos_pcie_set_perst_gpio(int ch_num, bool on); extern void exynos_pcie_set_ready_cto_recovery(int ch_num); /* not used: extern int exynos_pcie_gpio_onoff(int ch_num, int val); */ /* not used(comment out): extern void exynos_pcie_msi_init_ext(int ch_num); */ -extern int exynos_pcie_rc_set_affinity(int ch_num, int affinity); +extern int register_separated_msi_vector(int ch_num, + irq_handler_t handler, void *context, + int *irq_num); #define AUTOSUSPEND_TIMEOUT 200 @@ -74,10 +76,4 @@ int s51xx_check_pcie_link_status(int ch_num); void s51xx_pcie_l1ss_ctrl(int enable, int ch_num); void disable_msi_int(struct pci_dev *pdev); void print_msi_register(struct pci_dev *pdev); -int s5100_force_crash_exit_ext(void); -int s5100_poweron_pcie(struct modem_ctl *mc); -int s5100_poweroff_pcie(struct modem_ctl *mc, bool force_off); -int s5100_try_gpio_cp_wakeup(struct modem_ctl *mc); -int s5100_send_panic_noti_ext(void); -int s5100_set_outbound_atu(struct modem_ctl *mc, struct cp_btl *btl, loff_t *pos, u32 map_size); #endif /* __S51xx_PCIE_H__ */ diff --git a/drivers/soc/google/cpif/shm_ipc.c b/drivers/soc/google/cpif/shm_ipc.c index e2758168ed9a..544a0f44c806 100644 --- a/drivers/soc/google/cpif/shm_ipc.c +++ b/drivers/soc/google/cpif/shm_ipc.c @@ -11,9 +11,9 @@ #include #include #include -#include #include #include +#include #include "modem_utils.h" @@ -250,14 +250,18 @@ static int cp_shmem_check_mem_map_on_cp(struct device *dev) shmem_index = SHMEM_IPC; else if (!strncmp((const char *)&name, "SSV\0", sizeof(name))) shmem_index = SHMEM_VSS; -#if IS_ENABLED(CONFIG_SOC_EXYNOS9820) - else if (!strncmp((const char *)&name, "APV\0", sizeof(name))) - shmem_index = SHMEM_VPA; -#endif else if (!strncmp((const char *)&name, "GOL\0", sizeof(name))) shmem_index = SHMEM_BTL; + else if (!strncmp((const char *)&name, "EGOL\0", sizeof(name))) + shmem_index = SHMEM_BTL_EXT; else if (!strncmp((const char *)&name, "B2L\0", sizeof(name))) shmem_index = SHMEM_L2B; + else if (!strncmp((const char *)&name, "PKP\0", sizeof(name))) + shmem_index = SHMEM_PKTPROC; + else if (!strncmp((const char *)&name, "UKP\0", sizeof(name))) + shmem_index = SHMEM_PKTPROC_UL; + else if (!strncmp((const char *)&name, "MDD\0", sizeof(name))) + shmem_index = SHMEM_DDM; else continue; @@ -274,7 +278,7 @@ static int cp_shmem_check_mem_map_on_cp(struct device *dev) if ((_cp_shmem[cp_num][shmem_index].p_base + _cp_shmem[cp_num][shmem_index].size) > (_cp_rmem[rmem_index].p_base + _cp_rmem[rmem_index].size)) { - mif_err("%d %d size error 0x%08lx 0x%08x 0x%08lx 0x%08x\n", + mif_err("rmem:%d shmem_index:%d size error 0x%08lx 0x%08x 0x%08lx 0x%08x\n", rmem_index, shmem_index, _cp_shmem[cp_num][shmem_index].p_base, _cp_shmem[cp_num][shmem_index].size, @@ -282,8 +286,8 @@ static int cp_shmem_check_mem_map_on_cp(struct device *dev) return -ENOMEM; } - mif_info("index:%d/%d base:0x%08lx offset:0x%08x size:0x%08x\n", - shmem_index, rmem_index, _cp_rmem[rmem_index].p_base, + mif_info("rmem:%d shmem_index:%d base:0x%08lx offset:0x%08x size:0x%08x\n", + rmem_index, shmem_index, _cp_rmem[rmem_index].p_base, map.ns_map[i].offset, map.ns_map[i].size); } @@ -295,23 +299,7 @@ static int cp_shmem_check_mem_map_on_cp(struct device *dev) */ unsigned long shm_get_msi_base(void) { -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0)) return cp_shmem_get_base(0, SHMEM_MSI); -#else - int i; - - for (i = 0; i < MAX_CP_RMEM; i++) { - if (!_cp_rmem[i].name) - continue; - - if (strncmp(_cp_rmem[i].name, "cp_msi_rmem", strlen("cp_msi_rmem")) == 0) { - mif_info("p_base:0x%08lx\n", _cp_rmem[i].p_base); - return _cp_rmem[i].p_base; - } - } - - return 0; -#endif } EXPORT_SYMBOL(shm_get_msi_base); @@ -362,28 +350,31 @@ int cp_shmem_get_mem_map_on_cp_flag(u32 cp_num) } EXPORT_SYMBOL(cp_shmem_get_mem_map_on_cp_flag); -static struct page *nc_region_pages[SZ_64K]; void __iomem *cp_shmem_get_nc_region(unsigned long base, u32 size) { - int i; - unsigned int num_pages = (size >> PAGE_SHIFT); + unsigned int num_pages = (unsigned int)DIV_ROUND_UP(size, PAGE_SIZE); pgprot_t prot = pgprot_writecombine(PAGE_KERNEL); + struct page **pages; void *v_addr; + unsigned int i; if (!base) return NULL; - if (size > (num_pages << PAGE_SHIFT)) - num_pages++; + pages = kvcalloc(num_pages, sizeof(struct page *), GFP_KERNEL); + if (!pages) + return NULL; for (i = 0; i < num_pages; i++) { - nc_region_pages[i] = phys_to_page(base); + pages[i] = phys_to_page(base); base += PAGE_SIZE; } - v_addr = vmap(nc_region_pages, num_pages, VM_MAP, prot); - if (v_addr == NULL) - mif_err("%s: Failed to vmap pages\n", __func__); + v_addr = vmap(pages, num_pages, VM_MAP, prot); + if (!v_addr) + mif_err("Failed to vmap pages\n"); + + kvfree(pages); return (void __iomem *)v_addr; } @@ -411,21 +402,23 @@ void cp_shmem_release_region(u32 cp, u32 idx) } EXPORT_SYMBOL(cp_shmem_release_region); -void cp_shmem_release_rmem(u32 cp, u32 idx) +void cp_shmem_release_rmem(u32 cp, u32 idx, u32 headroom) { int i; - unsigned long base; + unsigned long base, offset = 0; u32 size; struct page *page; base = cp_shmem_get_base(cp, idx); size = cp_shmem_get_size(cp, idx); - mif_info("Release rmem 0x%08lx 0x%08x\n", base, size); + mif_info("Release rmem base:0x%08lx size:0x%08x headroom:0x%08x\n", base, size, headroom); for (i = 0; i < (size >> PAGE_SHIFT); i++) { - page = phys_to_page(base); - base += PAGE_SIZE; - free_reserved_page(page); + if (offset >= headroom) { + page = phys_to_page(base + offset); + free_reserved_page(page); + } + offset += PAGE_SIZE; } } EXPORT_SYMBOL(cp_shmem_release_rmem); @@ -459,7 +452,7 @@ static int cp_shmem_probe(struct platform_device *pdev) ret = cp_rmem_setup_latecall(pdev); if (ret) { mif_err("cp_rmem_setup_latecall() error:%d\n", ret); - return ret; + goto fail; } } #endif @@ -467,7 +460,7 @@ static int cp_shmem_probe(struct platform_device *pdev) ret = cp_shmem_setup(dev); if (ret) { mif_err("cp_shmem_setup() error:%d\n", ret); - return ret; + goto fail; } mif_dt_read_u32(dev->of_node, "use_mem_map_on_cp", use_map_on_cp); @@ -475,7 +468,7 @@ static int cp_shmem_probe(struct platform_device *pdev) ret = cp_shmem_check_mem_map_on_cp(dev); if (ret) { mif_err("cp_shmem_check_mem_map_on_cp() error:%d\n", ret); - return ret; + goto fail; } } else { mif_info("use_mem_map_on_cp is disabled. Use dt information\n"); @@ -486,7 +479,7 @@ static int cp_shmem_probe(struct platform_device *pdev) if (!_cp_shmem[i][j].name) continue; - mif_info("%d %d %d %s 0x%08lx 0x%08x %d\n", + mif_info("cp_num:%d rmem:%d index:%d %s 0x%08lx 0x%08x %d\n", _cp_shmem[i][j].cp_num, _cp_shmem[i][j].rmem, _cp_shmem[i][j].index, _cp_shmem[i][j].name, _cp_shmem[i][j].p_base, _cp_shmem[i][j].size, @@ -497,6 +490,10 @@ static int cp_shmem_probe(struct platform_device *pdev) mif_info("---\n"); return 0; + +fail: + panic("CP shmem probe failed\n"); + return ret; } static int cp_shmem_remove(struct platform_device *pdev) diff --git a/drivers/soc/google/debug/Makefile b/drivers/soc/google/debug/Makefile index 4d165bb837ef..53077fc9b9a3 100644 --- a/drivers/soc/google/debug/Makefile +++ b/drivers/soc/google/debug/Makefile @@ -20,7 +20,9 @@ obj-$(CONFIG_EXYNOS_DEBUG_TEST) += exynos-debug-test.o obj-$(CONFIG_PIXEL_DEBUG_TEST) += pixel-debug-test.o -obj-$(CONFIG_EXYNOS_ITMON) += gs101-itmon.o +obj-$(CONFIG_EXYNOS_ITMON) += itmon.o +itmon-$(CONFIG_SOC_GS101) += gs101-itmon.o +itmon-$(CONFIG_SOC_GS201) += gs201-itmon.o obj-$(CONFIG_EXYNOS_CORESIGHT) += exynos-coresight.o diff --git a/drivers/soc/google/debug/debug-snapshot-dpm.c b/drivers/soc/google/debug/debug-snapshot-dpm.c index 044fffce0b4c..ef17ea96cc0e 100644 --- a/drivers/soc/google/debug/debug-snapshot-dpm.c +++ b/drivers/soc/google/debug/debug-snapshot-dpm.c @@ -17,6 +17,8 @@ #include +#include +#include #include #include "debug-snapshot-local.h" @@ -44,9 +46,8 @@ bool dbg_snapshot_get_enabled_debug_kinfo(void) } EXPORT_SYMBOL(dbg_snapshot_get_enabled_debug_kinfo); -void dbg_snapshot_do_dpm(struct pt_regs *regs) +static void dbg_snapshot_do_dpm(struct pt_regs *regs, unsigned int esr) { - unsigned int esr = read_sysreg(esr_el1); unsigned int val = 0; unsigned int policy = GO_DEFAULT_ID; @@ -101,7 +102,99 @@ void dbg_snapshot_do_dpm(struct pt_regs *regs) dbg_snapshot_do_dpm_policy(policy, dpm_policy[policy]); } } -EXPORT_SYMBOL_GPL(dbg_snapshot_do_dpm); + +/* trace/hooks/fault.h */ +static void dbg_snapshot_do_dpm_die_kernel_fault(void *data, struct pt_regs *regs, + unsigned int esr, unsigned long addr, + const char *msg) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +static void dbg_snapshot_do_dpm_do_sea(void *data, struct pt_regs *regs, unsigned int esr, + unsigned long addr, const char *msg) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +static void dbg_snapshot_do_dpm_do_mem_abort(void *data, struct pt_regs *regs, + unsigned int esr, unsigned long addr, const char *msg) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +static void dbg_snapshot_do_dpm_do_sp_pc_abort(void *data, struct pt_regs *regs, + unsigned int esr, unsigned long addr, bool user) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +/* trace/hooks/traps.h */ +static void dbg_snapshot_do_dpm_do_undefinstr(void *data, struct pt_regs *regs, bool user) +{ + unsigned int esr = read_sysreg(esr_el1); + + dbg_snapshot_do_dpm(regs, esr); +} + +static void dbg_snapshot_do_dpm_bad_mode(void *data, struct pt_regs *regs, unsigned int esr, + int reason) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +static void dbg_snapshot_do_dpm_do_serror(void *data, struct pt_regs *regs, unsigned int esr) +{ + dbg_snapshot_do_dpm(regs, esr); +} + +static void register_dbg_snapshot_do_dpm_vendor_hooks(void) +{ + static bool hook_registered; + + if (hook_registered) + return; + + /* trace/hooks/fault.h */ + if (register_trace_android_rvh_die_kernel_fault(dbg_snapshot_do_dpm_die_kernel_fault + , NULL)) { + pr_err("dpm: register die_kernel_fault hook failed\n"); + return; + } + + if (register_trace_android_rvh_do_sea(dbg_snapshot_do_dpm_do_sea, NULL)) { + pr_err("dpm: register do_sea hook failed\n"); + return; + } + + if (register_trace_android_rvh_do_mem_abort(dbg_snapshot_do_dpm_do_mem_abort, NULL)) { + pr_err("dpm: register do_mem_abort hook failed\n"); + return; + } + + if (register_trace_android_rvh_do_sp_pc_abort(dbg_snapshot_do_dpm_do_sp_pc_abort, NULL)) { + pr_err("dpm: register do_sp_pc_abort hook failed\n"); + return; + } + + /* trace/hooks/traps.h */ + if (register_trace_android_rvh_do_undefinstr(dbg_snapshot_do_dpm_do_undefinstr, NULL)) { + pr_err("dpm: register do_undefinstr failed\n"); + return; + } + + if (register_trace_android_rvh_bad_mode(dbg_snapshot_do_dpm_bad_mode, NULL)) { + pr_err("dpm: register bad_mode hook failed\n"); + return; + } + + if (register_trace_android_rvh_arm64_serror_panic(dbg_snapshot_do_dpm_do_serror, NULL)) { + pr_err("dpm: register arm64_serror_panic hook failed\n"); + return; + } + + hook_registered = true; +} static void dbg_snapshot_dt_scan_dpm_feature(struct device_node *node) { @@ -286,4 +379,6 @@ void dbg_snapshot_init_dpm(void) if (dbg_snapshot_get_dpm_none_dump_mode() > 0) dss_dpm.dump_mode_none = 1; + + register_dbg_snapshot_do_dpm_vendor_hooks(); } diff --git a/drivers/soc/google/debug/debug-snapshot-local.h b/drivers/soc/google/debug/debug-snapshot-local.h index c4a47135d26c..3e01db610258 100644 --- a/drivers/soc/google/debug/debug-snapshot-local.h +++ b/drivers/soc/google/debug/debug-snapshot-local.h @@ -76,6 +76,7 @@ struct dbg_snapshot_dpm { extern void dbg_snapshot_init_log(void); extern void dbg_snapshot_init_dpm(void); extern void dbg_snapshot_init_utils(void); +extern void dbg_snapshot_start_log(void); extern int dbg_snapshot_dt_scan_dpm(void); extern int dbg_snapshot_get_enable(void); extern void __iomem *dbg_snapshot_get_header_vaddr(void); @@ -159,7 +160,7 @@ extern struct itmon_logs *dss_itmon; #define DSS_OFFSET_GPR_POWER_STAT (0x480) #define DSS_OFFSET_PANIC_STAT (0x500) #define DSS_OFFSET_CORE_LAST_PC (0x600) -#define DSS_OFFSET_QD_ENTRY (0x660) +#define DSS_OFFSET_QD_ENTRY (0x680) #define DSS_OFFSET_PANIC_STRING (0xC00) #define ARM_CPU_PART_CORTEX_A78 0xD41 diff --git a/drivers/soc/google/debug/debug-snapshot-log.c b/drivers/soc/google/debug/debug-snapshot-log.c index ea766507a81a..7fe19395ae04 100644 --- a/drivers/soc/google/debug/debug-snapshot-log.c +++ b/drivers/soc/google/debug/debug-snapshot-log.c @@ -217,7 +217,7 @@ void dbg_snapshot_log_output(void) pr_info("debug-snapshot-log physical / virtual memory layout:\n"); for (i = 0; i < ARRAY_SIZE(dss_log_items); i++) { if (dss_log_items[i].entry.enabled) - pr_info("%-12s: phys:%pa / virt:%pK / size:0x%zx / en:%d\n", + pr_info("%-12s: phys:0x%pa / virt:0x%pK / size:0x%zx / en:%d\n", dss_log_items[i].name, &dss_log_items[i].entry.paddr, (void *) dss_log_items[i].entry.vaddr, @@ -647,13 +647,17 @@ static void dbg_snapshot_print_irq(void) pr_info("----------------------------------------------------------\n"); for_each_irq_nr(i) { - struct irq_desc *desc = irq_to_desc(i); + struct irq_data *data; + struct irq_desc *desc; unsigned int irq_stat = 0; const char *name; - if (!desc) + data = irq_get_irq_data(i); + if (!data) continue; + desc = irq_data_to_desc(data); + for_each_possible_cpu(cpu) irq_stat += *per_cpu_ptr(desc->kstat_irqs, cpu); @@ -687,10 +691,6 @@ void dbg_snapshot_init_log(void) { struct dbg_snapshot_item *item = &dss_items[DSS_ITEM_KEVENTS_ID]; struct dbg_snapshot_log_item *log_item; - struct device_node *np = dss_desc.dev->of_node; - struct property *prop; - const char *str; - unsigned int i = 0; log_item_set_filed(TASK, task); log_item_set_filed(WORK, work); @@ -706,6 +706,15 @@ void dbg_snapshot_init_log(void) log_item_set_filed(THERMAL, thermal); log_item_set_filed(ACPM, acpm); log_item_set_filed(PRINTK, print); +} + +void dbg_snapshot_start_log(void) +{ + struct property *prop; + const char *str; + unsigned int i = 0; + + struct device_node *np = dss_desc.dev->of_node; if (dbg_snapshot_is_log_item_enabled(DSS_LOG_SUSPEND_ID)) { register_trace_suspend_resume(dbg_snapshot_suspend_resume, NULL); diff --git a/drivers/soc/google/debug/debug-snapshot-utils.c b/drivers/soc/google/debug/debug-snapshot-utils.c index 967254081a16..532f92cd0c95 100644 --- a/drivers/soc/google/debug/debug-snapshot-utils.c +++ b/drivers/soc/google/debug/debug-snapshot-utils.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -199,6 +200,11 @@ static void dbg_snapshot_report_reason(unsigned int val) __raw_writel(val, header + DSS_OFFSET_EMERGENCY_REASON); } +static void dbg_snapshot_set_reboot_mode(enum reboot_mode mode) +{ + reboot_mode = mode; +} + static void dbg_snapshot_set_wdt_caller(unsigned long addr) { void __iomem *header = dbg_snapshot_get_header_vaddr(); @@ -581,6 +587,7 @@ static int dbg_snapshot_panic_handler(struct notifier_block *nb, dbg_snapshot_set_item_enable("log_kevents", false); dbg_snapshot_dump_panic(kernel_panic_msg, strlen(kernel_panic_msg)); dbg_snapshot_report_reason(DSS_SIGN_PANIC); + dbg_snapshot_set_reboot_mode(REBOOT_WARM); for_each_possible_cpu(cpu) { if (cpu_is_offline(cpu)) dbg_snapshot_set_core_power_stat(DSS_SIGN_DEAD, cpu); @@ -644,6 +651,7 @@ static int dbg_snapshot_restart_handler(struct notifier_block *nb, if (dss_desc.in_warm) { dev_emerg(dss_desc.dev, "warm reset\n"); dbg_snapshot_report_reason(DSS_SIGN_WARM_REBOOT); + dbg_snapshot_set_reboot_mode(REBOOT_WARM); dbg_snapshot_dump_task_info(); } else if (dss_desc.in_reboot) { dev_emerg(dss_desc.dev, "normal reboot starting\n"); @@ -651,6 +659,7 @@ static int dbg_snapshot_restart_handler(struct notifier_block *nb, } else { dev_emerg(dss_desc.dev, "emergency restart\n"); dbg_snapshot_report_reason(DSS_SIGN_EMERGENCY_REBOOT); + dbg_snapshot_set_reboot_mode(REBOOT_WARM); dbg_snapshot_dump_task_info(); } @@ -723,7 +732,7 @@ EXPORT_SYMBOL_GPL(dbg_snapshot_register_debug_ops); static void dbg_snapshot_ipi_stop(void *ignore, struct pt_regs *regs) { - if (!dss_desc.in_reboot) + if (!dss_desc.in_reboot || tombstone) dbg_snapshot_save_context(regs, true); } diff --git a/drivers/soc/google/debug/debug-snapshot.c b/drivers/soc/google/debug/debug-snapshot.c index 42ba16d61eff..03aa8fc08c46 100644 --- a/drivers/soc/google/debug/debug-snapshot.c +++ b/drivers/soc/google/debug/debug-snapshot.c @@ -319,7 +319,7 @@ void dbg_snapshot_output(void) for (i = 0; i < ARRAY_SIZE(dss_items); i++) { if (!dss_items[i].entry.enabled) continue; - pr_info("%-16s: phys:%pa / virt:%pK / size:0x%zx / en:%d\n", + pr_info("%-16s: phys:0x%pa / virt:0x%pK / size:0x%zx / en:%d\n", dss_items[i].name, &dss_items[i].entry.paddr, (void *) dss_items[i].entry.vaddr, @@ -389,9 +389,12 @@ static void dbg_snapshot_fixmap(void) } } - dss_log = (struct dbg_snapshot_log *)(dss_items[DSS_ITEM_KEVENTS_ID].entry.vaddr); - dss_itmon = (struct itmon_logs *)(dss_items[DSS_ITEM_ITMON_ID].entry.vaddr); - dss_itmon->magic = DSS_ITMON_MAGIC_INITIALIZED; + if (dss_items[DSS_ITEM_KEVENTS_ID].entry.enabled) + dss_log = (struct dbg_snapshot_log *)(dss_items[DSS_ITEM_KEVENTS_ID].entry.vaddr); + if (dss_items[DSS_ITEM_ITMON_ID].entry.enabled) { + dss_itmon = (struct itmon_logs *)(dss_items[DSS_ITEM_ITMON_ID].entry.vaddr); + dss_itmon->magic = DSS_ITMON_MAGIC_INITIALIZED; + } /* set fake translation to virtual address to debug trace */ dss_info.info_event = dss_log; @@ -602,6 +605,7 @@ static int dbg_snapshot_probe(struct platform_device *pdev) dbg_snapshot_set_slcdump_status(); dbg_snapshot_set_enable(true); + dbg_snapshot_start_log(); if (sysfs_create_groups(&pdev->dev.kobj, dss_sysfs_groups)) dev_err(dss_desc.dev, "fail to register debug-snapshot sysfs\n"); diff --git a/drivers/soc/google/debug/exynos-adv-tracer-s2d.c b/drivers/soc/google/debug/exynos-adv-tracer-s2d.c index d4f73158a382..53fcc870b8f1 100644 --- a/drivers/soc/google/debug/exynos-adv-tracer-s2d.c +++ b/drivers/soc/google/debug/exynos-adv-tracer-s2d.c @@ -39,7 +39,6 @@ struct plugin_s2d_info { int dbgsel_sw; bool arraydump_done; int blk_count; - bool *blk_en; const char **blk_names; }; @@ -64,7 +63,7 @@ void adv_tracer_s2d_scandump(void) int adv_tracer_s2d_arraydump(void) { - struct adv_tracer_ipc_cmd cmd; + struct adv_tracer_ipc_cmd cmd = { 0 }; int ret = 0; u32 cpu_mask; @@ -96,12 +95,11 @@ int adv_tracer_s2d_arraydump(void) static int adv_tracer_s2d_get_enable(void) { - struct adv_tracer_ipc_cmd cmd; + struct adv_tracer_ipc_cmd cmd = { 0 }; int ret = 0; cmd.cmd_raw.cmd = eS2D_IPC_CMD_GET_ENABLE; - ret = adv_tracer_ipc_send_data(plugin_s2d.s2d_dev->id, - (struct adv_tracer_ipc_cmd *)&cmd); + ret = adv_tracer_ipc_send_data(plugin_s2d.s2d_dev->id, &cmd); if (ret < 0) { dev_err(plugin_s2d.dev, "ipc can't get enable\n"); return ret; @@ -113,7 +111,7 @@ static int adv_tracer_s2d_get_enable(void) static int adv_tracer_s2d_set_enable(int en) { - struct adv_tracer_ipc_cmd cmd; + struct adv_tracer_ipc_cmd cmd = { 0 }; int ret = 0; cmd.cmd_raw.cmd = eS2D_IPC_CMD_SET_ENABLE; @@ -127,15 +125,40 @@ static int adv_tracer_s2d_set_enable(int en) return 0; } -bool adv_tracer_s2d_get_blk_by_idx(unsigned int index) +static int adv_tracer_s2d_get_all_blk(unsigned long *p_blocks) +{ + struct adv_tracer_ipc_cmd cmd = { 0 }; + int ret = 0; + + cmd.cmd_raw.cmd = eS2D_IPC_CMD_GET_ALL_BLK; + ret = adv_tracer_ipc_send_data(plugin_s2d.s2d_dev->id, &cmd); + if (ret < 0) { + dev_err(plugin_s2d.dev, "cannot get blk list\n"); + return ret; + } + + *p_blocks = (unsigned long)cmd.buffer[2] << 32 | cmd.buffer[1]; + + return 0; +} + +int adv_tracer_s2d_get_blk_by_idx(unsigned int index) { - if (index < plugin_s2d.blk_count) - return plugin_s2d.blk_en[index]; + unsigned long blocks; + int ret; + + if (index >= plugin_s2d.blk_count) + return -EINVAL; + + ret = adv_tracer_s2d_get_all_blk(&blocks); + + if (ret) + return ret; - return false; + return !!(blocks & BIT(index)); } -bool adv_tracer_s2d_get_blk_by_name(const char *name) +int adv_tracer_s2d_get_blk_by_name(const char *name) { unsigned int i; @@ -144,18 +167,17 @@ bool adv_tracer_s2d_get_blk_by_name(const char *name) return adv_tracer_s2d_get_blk_by_idx(i); } - return false; + return -EINVAL; } int adv_tracer_s2d_set_blk_by_idx(bool enabled, unsigned int index) { - struct adv_tracer_ipc_cmd cmd; + struct adv_tracer_ipc_cmd cmd = { 0 }; int ret = 0; if (index >= plugin_s2d.blk_count) return -EINVAL; - memset(&cmd, 0, sizeof(cmd)); cmd.cmd_raw.cmd = eS2D_IPC_CMD_SET_BLK; cmd.buffer[1] = enabled; cmd.buffer[2] = index; @@ -167,10 +189,12 @@ int adv_tracer_s2d_set_blk_by_idx(bool enabled, unsigned int index) return ret; } - if (cmd.cmd_raw.ret_err) - return -EINVAL; - - plugin_s2d.blk_en[index] = enabled; + if (cmd.cmd_raw.ret_err) { + dev_err(plugin_s2d.dev, "%sabling %s blk rejected\n", + enabled ? "en" : "dis", + plugin_s2d.blk_names[index]); + return -EPERM; + } return 0; } @@ -189,11 +213,9 @@ int adv_tracer_s2d_set_blk_by_name(bool enabled, const char *name) int adv_tracer_s2d_set_all_blk(bool en) { - struct adv_tracer_ipc_cmd cmd; - unsigned int i; + struct adv_tracer_ipc_cmd cmd = { 0 }; int ret = 0; - memset(&cmd, 0, sizeof(cmd)); cmd.cmd_raw.cmd = eS2D_IPC_CMD_SET_ALL_BLK; cmd.buffer[1] = en; ret = adv_tracer_ipc_send_data(plugin_s2d.s2d_dev->id, &cmd); @@ -202,36 +224,6 @@ int adv_tracer_s2d_set_all_blk(bool en) return ret; } - if (cmd.cmd_raw.ret_err) - return -EINVAL; - - for (i = 0; i < plugin_s2d.blk_count; i++) - plugin_s2d.blk_en[i] = en; - - return 0; -} - -int adv_tracer_s2d_get_all_blk(void) -{ - struct adv_tracer_ipc_cmd cmd; - int ret = 0; - unsigned long i, bits; - - memset(&cmd, 0, sizeof(cmd)); - cmd.cmd_raw.cmd = eS2D_IPC_CMD_GET_ALL_BLK; - ret = adv_tracer_ipc_send_data(plugin_s2d.s2d_dev->id, &cmd); - if (ret < 0) { - dev_err(plugin_s2d.dev, "cannot get blk list\n"); - return ret; - } - - bits = (unsigned long)cmd.buffer[1] | - (unsigned long)cmd.buffer[2] << 32; - for_each_set_bit(i, &bits, plugin_s2d.blk_count) - plugin_s2d.blk_en[i] = true; - for_each_clear_bit(i, &bits, plugin_s2d.blk_count) - plugin_s2d.blk_en[i] = false; - return 0; } @@ -363,10 +355,17 @@ static ssize_t print_all_block_show(struct device *dev, struct device_attribute *attr, char *buf) { unsigned int i, sz = 0; + unsigned long blocks; + int ret; + + ret = adv_tracer_s2d_get_all_blk(&blocks); + + if (ret) + return ret; for (i = 0; i < plugin_s2d.blk_count; i++) { sz += scnprintf(buf + sz, PAGE_SIZE - sz, "[%02u : %3s] %s\n", - i, plugin_s2d.blk_en[i] ? "on" : "off", + i, blocks & BIT(i) ? "on" : "off", plugin_s2d.blk_names[i]); } @@ -417,17 +416,6 @@ static int adv_tracer_s2d_dt_init(struct platform_device *pdev) of_property_read_string_array(node, "blk-list", plugin_s2d.blk_names, plugin_s2d.blk_count); - plugin_s2d.blk_en = devm_kcalloc(&pdev->dev, plugin_s2d.blk_count, - sizeof(bool), GFP_KERNEL); - if (!plugin_s2d.blk_en) { - devm_kfree(&pdev->dev, plugin_s2d.blk_names); - plugin_s2d.blk_names = NULL; - dev_err(&pdev->dev, "cannot allocate mem for blk enable\n"); - return -ENOMEM; - } - - adv_tracer_s2d_get_all_blk(); - return 0; } diff --git a/drivers/soc/google/debug/exynos-coresight-etm.c b/drivers/soc/google/debug/exynos-coresight-etm.c index 15b143a9d03c..6d40b035073e 100644 --- a/drivers/soc/google/debug/exynos-coresight-etm.c +++ b/drivers/soc/google/debug/exynos-coresight-etm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "core_regs.h" @@ -686,6 +687,7 @@ static int exynos_etm_c2_pm_notifier(struct notifier_block *self, static struct notifier_block exynos_etm_c2_pm_nb = { .notifier_call = exynos_etm_c2_pm_notifier, + .priority = CORESIGHT_CPUPM_PRIORITY, }; static int exynos_etm_pm_notifier(struct notifier_block *notifier, diff --git a/drivers/soc/google/debug/exynos-coresight.c b/drivers/soc/google/debug/exynos-coresight.c index 2aaa1158f158..1b51d9406db5 100644 --- a/drivers/soc/google/debug/exynos-coresight.c +++ b/drivers/soc/google/debug/exynos-coresight.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "core_regs.h" @@ -453,6 +454,7 @@ static int exynos_cs_c2_notifier(struct notifier_block *self, static struct notifier_block exynos_cs_c2_nb = { .notifier_call = exynos_cs_c2_notifier, + .priority = CORESIGHT_CPUPM_PRIORITY, }; static const struct of_device_id of_exynos_cs_matches[] __initconst= { diff --git a/drivers/soc/google/debug/exynos-debug-test.c b/drivers/soc/google/debug/exynos-debug-test.c index b69c8fd991da..e14ba2815243 100644 --- a/drivers/soc/google/debug/exynos-debug-test.c +++ b/drivers/soc/google/debug/exynos-debug-test.c @@ -203,6 +203,7 @@ static void simulate_SFR(char *arg) /* should not reach here */ } +#if IS_ENABLED(CONFIG_SOC_GS101) static void simulate_WP(char *arg) { unsigned int ps_hold_control; @@ -213,6 +214,7 @@ static void simulate_WP(char *arg) exynos_pmu_write(exynos_debug_desc.ps_hold_control_offset, ps_hold_control & 0xFFFFFEFF); } +#endif static void simulate_PANIC(char *arg) { @@ -497,7 +499,7 @@ static void simulate_OVERFLOW(char *arg) static char *buffer[NR_CPUS]; static void simulate_CPU_CONTEXT_CACHE_FLUSH_handler(void *info) { - int cpu = raw_smp_processor_id(); + u64 cpu = raw_smp_processor_id(); u64 i = 0; u64 addr = virt_to_phys((void *)(buffer[cpu])); local_irq_disable(); @@ -505,7 +507,7 @@ static void simulate_CPU_CONTEXT_CACHE_FLUSH_handler(void *info) memset(buffer[cpu], 0x5A, PAGE_SIZE * 2); dbg_snapshot_set_debug_test_buffer_addr(addr, cpu); - i = cpu << 16; + i = cpu << 48; /* populate registers with known values and infinite loop */ asm volatile("mov x0, %0\n\t" "add x1, x0, #1\n\t" @@ -613,7 +615,9 @@ static struct force_error_item force_error_vector[] = { {"QDP", &simulate_QDP}, {"SVC", &simulate_SVC}, {"SFR", &simulate_SFR}, +#if IS_ENABLED(CONFIG_SOC_GS101) {"WP", &simulate_WP}, +#endif {"panic", &simulate_PANIC}, {"bug", &simulate_BUG}, {"warn", &simulate_WARN}, @@ -808,7 +812,9 @@ static void exynos_debug_test_desc_init(void) static struct debug_trigger exynos_debug_test_trigger = { .hard_lockup = simulate_HARD_LOCKUP, +#if IS_ENABLED(CONFIG_SOC_GS101) .cold_reset = simulate_WP, +#endif .watchdog_emergency_reset = simulate_QDP, .halt = simulate_HALT, .arraydump = simulate_ARRAYDUMP, diff --git a/drivers/soc/google/debug/exynos-ecc-handler.c b/drivers/soc/google/debug/exynos-ecc-handler.c index 15c7a67215ef..0144cbfebf92 100644 --- a/drivers/soc/google/debug/exynos-ecc-handler.c +++ b/drivers/soc/google/debug/exynos-ecc-handler.c @@ -18,7 +18,12 @@ static irqreturn_t exynos_ecc_handler(int irq, void *dev_id) { - struct irq_desc *desc = irq_to_desc(irq); + struct irq_data *data; + struct irq_desc *desc = NULL; + + data = irq_get_irq_data(irq); + if (data) + desc = irq_data_to_desc(data); dbg_snapshot_ecc_dump(); if (desc && desc->action && desc->action->name) diff --git a/drivers/soc/google/debug/gs201-itmon.c b/drivers/soc/google/debug/gs201-itmon.c new file mode 100644 index 000000000000..b7fbd8f3f879 --- /dev/null +++ b/drivers/soc/google/debug/gs201-itmon.c @@ -0,0 +1,2338 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define OFFSET_TMOUT_REG (0x2000) +#define OFFSET_REQ_R (0x0) +#define OFFSET_REQ_W (0x20) +#define OFFSET_RESP_R (0x40) +#define OFFSET_RESP_W (0x60) +#define OFFSET_ERR_REPT (0x20) +#define OFFSET_PROT_CHK (0x100) +#define OFFSET_NUM (0x4) + +#define REG_INT_MASK (0x0) +#define REG_INT_CLR (0x4) +#define REG_INT_INFO (0x8) +#define REG_EXT_INFO_0 (0x10) +#define REG_EXT_INFO_1 (0x14) +#define REG_EXT_INFO_2 (0x18) +#define REG_EXT_USER (0x80) + +#define REG_DBG_CTL (0x10) +#define REG_TMOUT_INIT_VAL (0x14) +#define REG_TMOUT_FRZ_EN (0x18) +#define REG_TMOUT_FRZ_STATUS (0x1C) +#define REG_TMOUT_BUF_WR_OFFSET (0x20) + +#define REG_TMOUT_BUF_POINT_ADDR (0x20) +#define REG_TMOUT_BUF_ID (0x24) + +#define REG_TMOUT_BUF_PAYLOAD_0 (0x28) +#define REG_TMOUT_BUF_PAYLOAD_1 (0x30) +#define REG_TMOUT_BUF_PAYLOAD_2 (0x34) +#define REG_TMOUT_BUF_PAYLOAD_3 (0x38) +#define REG_TMOUT_BUF_PAYLOAD_4 (0x3C) + +#define REG_PROT_CHK_CTL (0x4) +#define REG_PROT_CHK_INT (0x8) +#define REG_PROT_CHK_INT_ID (0xC) +#define REG_PROT_CHK_START_ADDR_LOW (0x10) +#define REG_PROT_CHK_END_ADDR_LOW (0x14) +#define REG_PROT_CHK_START_END_ADDR_UPPER (0x18) + +#define RD_RESP_INT_ENABLE (1 << 0) +#define WR_RESP_INT_ENABLE (1 << 1) +#define ARLEN_RLAST_INT_ENABLE (1 << 2) +#define AWLEN_WLAST_INT_ENABLE (1 << 3) +#define INTEND_ACCESS_INT_ENABLE (1 << 4) + +#define BIT_PROT_CHK_ERR_OCCURRED(x) (((x) & (0x1 << 0)) >> 0) +#define BIT_PROT_CHK_ERR_CODE(x) (((x) & (0x7 << 1)) >> 1) + +#define BIT_ERR_CODE(x) (((x) & (0xF << 28)) >> 28) +#define BIT_ERR_OCCURRED(x) (((x) & (0x1 << 27)) >> 27) +#define BIT_ERR_VALID(x) (((x) & (0x1 << 26)) >> 26) +#define BIT_AXID(x) (((x) & (0xFFFF))) +#define BIT_AXUSER(x) (((x) & (0xFFFFFFFF))) +#define BIT_AXUSER_PERI(x) (((x) & (0xFFFF << 16)) >> 16) +#define BIT_AXBURST(x) (((x) & (0x3))) +#define BIT_AXPROT(x) (((x) & (0x3 << 2)) >> 2) +#define BIT_AXLEN(x) (((x) & (0xF << 16)) >> 16) +#define BIT_AXSIZE(x) (((x) & (0x7 << 28)) >> 28) + +#define ERRCODE_SLVERR (0) +#define ERRCODE_DECERR (1) +#define ERRCODE_UNSUPPORTED (2) +#define ERRCODE_POWER_DOWN (3) +#define ERRCODE_UNKNOWN_4 (4) +#define ERRCODE_UNKNOWN_5 (5) +#define ERRCODE_TMOUT (6) + +#define DATA (0) +#define PERI (1) +#define BUS_PATH_TYPE (2) + +#define TRANS_TYPE_WRITE (0) +#define TRANS_TYPE_READ (1) +#define TRANS_TYPE_NUM (2) + +#define FROM_CP (0) +#define FROM_CPU (2) + +#define NOT_AVAILABLE_STR "N/A" + +#define TMOUT (0xFFFFF) +#define TMOUT_TEST (0x1) + +#define PANIC_THRESHOLD (10) + +/* This value will be fixed */ +#define INTEND_ADDR_START (0) +#define INTEND_ADDR_END (0) + +#define log_dev_err(dev, fmt, ...) \ +do { \ + dev_printk_emit(LOGLEVEL_ERR, dev, fmt, ##__VA_ARGS__); \ + dbg_snapshot_itmon_backup_log(fmt, ##__VA_ARGS__); \ +} while (0) + +#define log_dev_info(dev, fmt, ...) \ +do { \ + dev_printk_emit(LOGLEVEL_INFO, dev, fmt, ##__VA_ARGS__); \ + dbg_snapshot_itmon_backup_log(fmt, ##__VA_ARGS__); \ +} while (0) + +#define log_dev_dbg(dev, fmt, ...) \ +do { \ + dev_printk_emit(LOGLEVEL_DEBUG, dev, fmt, ##__VA_ARGS__); \ + dbg_snapshot_itmon_backup_log(fmt, ##__VA_ARGS__); \ +} while (0) + +enum err_type { + FATAL = 0, + DREX_TMOUT, + CPU, + IP, + UNHANDLED, + TYPE_MAX, +}; + +struct itmon_policy { + char *name; + int policy; + bool error; +}; + +struct itmon_rpathinfo { + unsigned int id; + char *port_name; + char *dest_name; + unsigned int bits; + unsigned int shift_bits; +}; + +struct itmon_clientinfo { + char *port_name; + unsigned int user; + char *client_name; + unsigned int bits; +}; + +struct itmon_nodegroup; + +struct itmon_traceinfo { + char *port; + char *client; + unsigned int user; + char *dest; + unsigned long target_addr; + unsigned int errcode; + bool read; + bool onoff; + bool path_dirty; + bool dirty; + unsigned long from; + int path_type; + char buf[SZ_32]; + unsigned int axsize; + unsigned int axlen; + unsigned int axburst; + unsigned int axprot; + bool baaw_prot; + struct list_head list; +}; + +struct itmon_tracedata { + unsigned int int_info; + unsigned int ext_info_0; + unsigned int ext_info_1; + unsigned int ext_info_2; + unsigned int ext_user; + unsigned int dbg_mo_cnt; + unsigned int prot_chk_ctl; + unsigned int prot_chk_info; + unsigned int prot_chk_int_id; + unsigned int offset; + struct itmon_traceinfo *ref_info; + bool logging; + bool read; +}; + +struct itmon_nodeinfo { + unsigned int type; + char *name; + unsigned int phy_regs; + bool err_enabled; + bool prot_chk_enabled; + bool addr_detect_enabled; + bool retention; + unsigned int time_val; + bool tmout_enabled; + bool tmout_frz_enabled; + void __iomem *regs; + struct itmon_tracedata tracedata; + struct itmon_nodegroup *group; + struct list_head list; +}; + +struct itmon_nodegroup { + char *name; + unsigned int phy_regs; + bool ex_table; + struct itmon_nodeinfo *nodeinfo; + unsigned int nodesize; + unsigned int path_type; + void __iomem *regs; + int irq; +}; + +struct itmon_platdata { + const struct itmon_rpathinfo *rpathinfo; + const struct itmon_clientinfo *clientinfo; + struct itmon_nodegroup *nodegroup; + struct list_head infolist[TRANS_TYPE_NUM]; + struct list_head datalist[TRANS_TYPE_NUM]; + ktime_t last_time; + bool cp_crash_in_progress; + unsigned int sysfs_tmout_val; + + struct itmon_policy *policy; + unsigned int err_cnt_by_cpu; + unsigned int panic_threshold; + bool in_do_policy; + bool probed; +}; + +struct itmon_dev { + struct device *dev; + struct itmon_platdata *pdata; + int irq; + int id; + void __iomem *regs; + spinlock_t ctrl_lock; + struct itmon_notifier notifier_info; + char itmon_pattern[SZ_32]; + atomic_t itmon_pattern_cnt; +}; + +struct itmon_panic_block { + struct notifier_block nb_panic_block; + struct itmon_dev *pdev; +}; + +static struct itmon_policy err_policy[] = { + [FATAL] = {"err_fatal", 0, false}, + [DREX_TMOUT] = {"err_drex_tmout", 0, false}, + [CPU] = {"err_cpu", 0, false}, + [IP] = {"err_ip", 0, false}, + [UNHANDLED] = {"err_unhandled", 0, false}, +}; + +const static struct itmon_rpathinfo rpathinfo[] = { + /* 0x8000_0000 - 0xf_ffff_ffff */ + + /* NOCL0_M0 / M1 / M2 / M3 CPU specific */ + {0, "CPU0", "NOCL0_M0", 0x3F, 0}, + {0, "CPU1", "NOCL0_M1", 0x3F, 0}, + {0, "CPU2", "NOCL0_M2", 0x3F, 0}, + {0, "CPU3", "NOCL0_M3", 0x3F, 0}, + + /* CORE_M0 / M1 / M2 / M3 Common */ + {1, "AUR1", "NOCL0_M", 0x3F, 0}, + {2, "GPUMMU", "NOCL0_M", 0x3F, 0}, + {3, "AUR0", "NOCL0_M", 0x3F, 0}, + {4, "GPU0", "NOCL0_M", 0x3F, 0}, + {5, "GPU1", "NOCL0_M", 0x3F, 0}, + {6, "GPU2", "NOCL0_M", 0x3F, 0}, + {7, "GPU3", "NOCL0_M", 0x3F, 0}, + {8, "TPU", "NOCL0_M", 0x3F, 0}, + {9, "DPU0", "NOCL0_M", 0x3F, 0}, + {10, "DPU1", "NOCL0_M", 0x3F, 0}, + {11, "DPU2", "NOCL0_M", 0x3F, 0}, + {12, "CSIS0", "NOCL0_M", 0x3F, 0}, + {13, "CSIS1", "NOCL0_M", 0x3F, 0}, + {14, "DNS", "NOCL0_M", 0x3F, 0}, + {15, "GDC0", "NOCL0_M", 0x3F, 0}, + {16, "GDC1", "NOCL0_M", 0x3F, 0}, + {17, "GDC2", "NOCL0_M", 0x3F, 0}, + {18, "G3AA", "NOCL0_M", 0x3F, 0}, + {19, "IPP", "NOCL0_M", 0x3F, 0}, + {20, "MCSC0", "NOCL0_M", 0x3F, 0}, + {21, "MCSC1", "NOCL0_M", 0x3F, 0}, + {22, "MCSC2", "NOCL0_M", 0x3F, 0}, + {23, "TNR0", "NOCL0_M", 0x3F, 0}, + {24, "TNR1", "NOCL0_M", 0x3F, 0}, + {25, "TNR2", "NOCL0_M", 0x3F, 0}, + {26, "TNR3", "NOCL0_M", 0x3F, 0}, + {27, "TNR4", "NOCL0_M", 0x3F, 0}, + {28, "BO", "NOCL0_M", 0x3F, 0}, + {29, "G2D0", "NOCL0_M", 0x3F, 0}, + {30, "G2D1", "NOCL0_M", 0x3F, 0}, + {31, "G2D2", "NOCL0_M", 0x3F, 0}, + {32, "HSI2", "NOCL0_M", 0x3F, 0}, + {33, "MFC0", "NOCL0_M", 0x3F, 0}, + {34, "MFC1", "NOCL0_M", 0x3F, 0}, + {35, "MISC", "NOCL0_M", 0x3F, 0}, + {36, "ALIVE", "NOCL0_M", 0x3F, 0}, + {37, "AOC", "NOCL0_M", 0x3F, 0}, + {38, "CSSYS", "NOCL0_M", 0x3F, 0}, + {39, "GSA", "NOCL0_M", 0x3F, 0}, + {40, "HSI0", "NOCL0_M", 0x3F, 0}, + {41, "HSI1", "NOCL0_M", 0x3F, 0}, + + + /* 0x0 - 0x7fff_ffff */ + + {0, "CPU0", "NOCL0_DP", 0x3F, 0}, + {1, "CPU1", "NOCL0_DP", 0x3F, 0}, + {2, "CPU2", "NOCL0_DP", 0x3F, 0}, + {3, "CPU3", "NOCL0_DP", 0x3F, 0}, + {4, "AUR1", "NOCL0_DP", 0x3F, 0}, + {5, "GPUMMU", "NOCL0_DP", 0x3F, 0}, + {6, "AUR0", "NOCL0_DP", 0x3F, 0}, + {7, "GPU0", "NOCL0_DP", 0x3F, 0}, + {8, "GPU1", "NOCL0_DP", 0x3F, 0}, + {9, "GPU2", "NOCL0_DP", 0x3F, 0}, + {10, "GPU3", "NOCL0_DP", 0x3F, 0}, + {11, "TPU", "NOCL0_DP", 0x3F, 0}, + {12, "DPU0", "NOCL0_DP", 0x3F, 0}, + {13, "DPU1", "NOCL0_DP", 0x3F, 0}, + {14, "DPU2", "NOCL0_DP", 0x3F, 0}, + {15, "CSIS0", "NOCL0_DP", 0x3F, 0}, + {16, "CSIS1", "NOCL0_DP", 0x3F, 0}, + {17, "DNS", "NOCL0_DP", 0x3F, 0}, + {18, "GDC0", "NOCL0_DP", 0x3F, 0}, + {19, "GDC1", "NOCL0_DP", 0x3F, 0}, + {20, "GDC2", "NOCL0_DP", 0x3F, 0}, + {21, "G3AA", "NOCL0_DP", 0x3F, 0}, + {22, "IPP", "NOCL0_DP", 0x3F, 0}, + {23, "MCSC0", "NOCL0_DP", 0x3F, 0}, + {24, "MCSC1", "NOCL0_DP", 0x3F, 0}, + {25, "MCSC2", "NOCL0_DP", 0x3F, 0}, + {26, "TNR0", "NOCL0_DP", 0x3F, 0}, + {27, "TNR1", "NOCL0_DP", 0x3F, 0}, + {28, "TNR2", "NOCL0_DP", 0x3F, 0}, + {29, "TNR3", "NOCL0_DP", 0x3F, 0}, + {30, "TNR4", "NOCL0_DP", 0x3F, 0}, + {31, "BO", "NOCL0_DP", 0x3F, 0}, + {32, "G2D0", "NOCL0_DP", 0x3F, 0}, + {33, "G2D1", "NOCL0_DP", 0x3F, 0}, + {34, "G2D2", "NOCL0_DP", 0x3F, 0}, + {35, "MFC0", "NOCL0_DP", 0x3F, 0}, + {36, "MFC1", "NOCL0_DP", 0x3F, 0}, + {37, "HSI2", "NOCL0_DP", 0x3F, 0}, + {38, "MISC", "NOCL0_DP", 0x3F, 0}, + {39, "ALIVE", "NOCL0_DP", 0x3F, 0}, + {40, "AOC", "NOCL0_DP", 0x3F, 0}, + {41, "CSSYS", "NOCL0_DP", 0x3F, 0}, + {42, "GSA", "NOCL0_DP", 0x3F, 0}, + {43, "HSI0", "NOCL0_DP", 0x3F, 0}, + {44, "HSI1", "NOCL0_DP", 0x3F, 0}, + + {0, "AUR1", "CORE_CCI", 0x7F, 0}, + {35, "AUR1", "CORE_CCI", 0x7F, 0}, + {70, "AUR1", "CORE_CCI", 0x7F, 0}, + {105, "AUR1", "CORE_CCI", 0x7F, 0}, + {1, "GPUMMU", "CORE_CCI", 0x7F, 0}, + {36, "GPUMMU", "CORE_CCI", 0x7F, 0}, + {71, "GPUMMU", "CORE_CCI", 0x7F, 0}, + {106, "GPUMMU", "CORE_CCI", 0x7F, 0}, + {2, "AUR0", "CORE_CCI", 0x7F, 0}, + {37, "AUR0", "CORE_CCI", 0x7F, 0}, + {72, "AUR0", "CORE_CCI", 0x7F, 0}, + {107, "AUR0", "CORE_CCI", 0x7F, 0}, + {3, "GPU0", "CORE_CCI", 0x7F, 0}, + {38, "GPU0", "CORE_CCI", 0x7F, 0}, + {73, "GPU0", "CORE_CCI", 0x7F, 0}, + {108, "GPU0", "CORE_CCI", 0x7F, 0}, + {4, "GPU1", "CORE_CCI", 0x7F, 0}, + {39, "GPU1", "CORE_CCI", 0x7F, 0}, + {74, "GPU1", "CORE_CCI", 0x7F, 0}, + {109, "GPU1", "CORE_CCI", 0x7F, 0}, + {5, "GPU2", "CORE_CCI", 0x7F, 0}, + {40, "GPU2", "CORE_CCI", 0x7F, 0}, + {75, "GPU2", "CORE_CCI", 0x7F, 0}, + {110, "GPU2", "CORE_CCI", 0x7F, 0}, + {6, "GPU3", "CORE_CCI", 0x7F, 0}, + {41, "GPU3", "CORE_CCI", 0x7F, 0}, + {76, "GPU3", "CORE_CCI", 0x7F, 0}, + {111, "GPU3", "CORE_CCI", 0x7F, 0}, + {7, "TPU", "CORE_CCI", 0x7F, 0}, + {42, "TPU", "CORE_CCI", 0x7F, 0}, + {77, "TPU", "CORE_CCI", 0x7F, 0}, + {112, "TPU", "CORE_CCI", 0x7F, 0}, + {9, "DPU0", "CORE_CCI", 0x7F, 0}, + {44, "DPU0", "CORE_CCI", 0x7F, 0}, + {79, "DPU0", "CORE_CCI", 0x7F, 0}, + {114, "DPU0", "CORE_CCI", 0x7F, 0}, + {9, "DPU1", "CORE_CCI", 0x7F, 0}, + {44, "DPU1", "CORE_CCI", 0x7F, 0}, + {79, "DPU1", "CORE_CCI", 0x7F, 0}, + {114, "DPU1", "CORE_CCI", 0x7F, 0}, + {10, "DPU2", "CORE_CCI", 0x7F, 0}, + {45, "DPU2", "CORE_CCI", 0x7F, 0}, + {80, "DPU2", "CORE_CCI", 0x7F, 0}, + {115, "DPU2", "CORE_CCI", 0x7F, 0}, + {11, "CSIS0", "CORE_CCI", 0x7F, 0}, + {46, "CSIS0", "CORE_CCI", 0x7F, 0}, + {81, "CSIS0", "CORE_CCI", 0x7F, 0}, + {116, "CSIS0", "CORE_CCI", 0x7F, 0}, + {12, "CSIS1", "CORE_CCI", 0x7F, 0}, + {47, "CSIS1", "CORE_CCI", 0x7F, 0}, + {82, "CSIS1", "CORE_CCI", 0x7F, 0}, + {117, "CSIS1", "CORE_CCI", 0x7F, 0}, + {13, "DNS", "CORE_CCI", 0x7F, 0}, + {48, "DNS", "CORE_CCI", 0x7F, 0}, + {82, "DNS", "CORE_CCI", 0x7F, 0}, + {117, "DNS", "CORE_CCI", 0x7F, 0}, + {14, "GDC0", "CORE_CCI", 0x7F, 0}, + {49, "GDC0", "CORE_CCI", 0x7F, 0}, + {84, "GDC0", "CORE_CCI", 0x7F, 0}, + {119, "GDC0", "CORE_CCI", 0x7F, 0}, + {15, "GDC1", "CORE_CCI", 0x7F, 0}, + {50, "GDC1", "CORE_CCI", 0x7F, 0}, + {85, "GDC1", "CORE_CCI", 0x7F, 0}, + {120, "GDC1", "CORE_CCI", 0x7F, 0}, + {16, "GDC2", "CORE_CCI", 0x7F, 0}, + {51, "GDC2", "CORE_CCI", 0x7F, 0}, + {86, "GDC2", "CORE_CCI", 0x7F, 0}, + {121, "GDC2", "CORE_CCI", 0x7F, 0}, + {17, "G3AA", "CORE_CCI", 0x7F, 0}, + {52, "G3AA", "CORE_CCI", 0x7F, 0}, + {87, "G3AA", "CORE_CCI", 0x7F, 0}, + {122, "G3AA", "CORE_CCI", 0x7F, 0}, + {17, "IPP", "CORE_CCI", 0x7F, 0}, + {52, "IPP", "CORE_CCI", 0x7F, 0}, + {88, "IPP", "CORE_CCI", 0x7F, 0}, + {113, "IPP", "CORE_CCI", 0x7F, 0}, + {19, "MCSC0", "CORE_CCI", 0x7F, 0}, + {54, "MCSC0", "CORE_CCI", 0x7F, 0}, + {89, "MCSC0", "CORE_CCI", 0x7F, 0}, + {124, "MCSC0", "CORE_CCI", 0x7F, 0}, + {20, "MCSC1", "CORE_CCI", 0x7F, 0}, + {55, "MCSC1", "CORE_CCI", 0x7F, 0}, + {90, "MCSC1", "CORE_CCI", 0x7F, 0}, + {125, "MCSC1", "CORE_CCI", 0x7F, 0}, + {21, "MCSC2", "CORE_CCI", 0x7F, 0}, + {56, "MCSC2", "CORE_CCI", 0x7F, 0}, + {91, "MCSC2", "CORE_CCI", 0x7F, 0}, + {126, "MCSC2", "CORE_CCI", 0x7F, 0}, + {22, "TNR0", "CORE_CCI", 0x7F, 0}, + {57, "TNR0", "CORE_CCI", 0x7F, 0}, + {92, "TNR0", "CORE_CCI", 0x7F, 0}, + {127, "TNR0", "CORE_CCI", 0x7F, 0}, + {23, "TNR1", "CORE_CCI", 0x7F, 0}, + {58, "TNR1", "CORE_CCI", 0x7F, 0}, + {93, "TNR1", "CORE_CCI", 0x7F, 0}, + {128, "TNR1", "CORE_CCI", 0x7F, 0}, + {24, "TNR2", "CORE_CCI", 0x7F, 0}, + {59, "TNR2", "CORE_CCI", 0x7F, 0}, + {94, "TNR2", "CORE_CCI", 0x7F, 0}, + {129, "TNR2", "CORE_CCI", 0x7F, 0}, + {25, "TNR3", "CORE_CCI", 0x7F, 0}, + {60, "TNR3", "CORE_CCI", 0x7F, 0}, + {95, "TNR3", "CORE_CCI", 0x7F, 0}, + {130, "TNR3", "CORE_CCI", 0x7F, 0}, + {26, "TNR4", "CORE_CCI", 0x7F, 0}, + {61, "TNR4", "CORE_CCI", 0x7F, 0}, + {96, "TNR4", "CORE_CCI", 0x7F, 0}, + {131, "TNR4", "CORE_CCI", 0x7F, 0}, + {27, "BO", "CORE_CCI", 0x7F, 0}, + {62, "BO", "CORE_CCI", 0x7F, 0}, + {97, "BO", "CORE_CCI", 0x7F, 0}, + {132, "BO", "CORE_CCI", 0x7F, 0}, + {28, "G2D0", "CORE_CCI", 0x7F, 0}, + {63, "G2D0", "CORE_CCI", 0x7F, 0}, + {98, "G2D0", "CORE_CCI", 0x7F, 0}, + {133, "G2D0", "CORE_CCI", 0x7F, 0}, + {29, "G2D1", "CORE_CCI", 0x7F, 0}, + {64, "G2D1", "CORE_CCI", 0x7F, 0}, + {99, "G2D1", "CORE_CCI", 0x7F, 0}, + {134, "G2D1", "CORE_CCI", 0x7F, 0}, + {30, "G2D2", "CORE_CCI", 0x7F, 0}, + {65, "G2D2", "CORE_CCI", 0x7F, 0}, + {100, "G2D2", "CORE_CCI", 0x7F, 0}, + {135, "G2D2", "CORE_CCI", 0x7F, 0}, + {31, "HSI2", "CORE_CCI", 0x7F, 0}, + {66, "HSI2", "CORE_CCI", 0x7F, 0}, + {101, "HSI2", "CORE_CCI", 0x7F, 0}, + {136, "HSI2", "CORE_CCI", 0x7F, 0}, + {32, "MFC0", "CORE_CCI", 0x7F, 0}, + {67, "MFC0", "CORE_CCI", 0x7F, 0}, + {102, "MFC0", "CORE_CCI", 0x7F, 0}, + {137, "MFC0", "CORE_CCI", 0x7F, 0}, + {33, "MFC1", "CORE_CCI", 0x7F, 0}, + {68, "MFC1", "CORE_CCI", 0x7F, 0}, + {103, "MFC1", "CORE_CCI", 0x7F, 0}, + {138, "MFC1", "CORE_CCI", 0x7F, 0}, + {34, "MISC", "CORE_CCI", 0x7F, 0}, + {69, "MISC", "CORE_CCI", 0x7F, 0}, + {104, "MISC", "CORE_CCI", 0x7F, 0}, + {139, "MISC", "CORE_CCI", 0x7F, 0}, + {140, "ALIVE", "CORE_CCI", 0x7F, 0}, + {141, "AOC", "CORE_CCI", 0x7F, 0}, + {142, "CSSYS", "CORE_CCI", 0x7F, 0}, + {143, "GSA", "CORE_CCI", 0x7F, 0}, + {144, "HSI0", "CORE_CCI", 0x7F, 0}, + {145, "HSI1", "CORE_CCI", 0x7F, 0}, +}; + +const static struct itmon_clientinfo clientinfo[] = { + {"GSA", 0x1, /*XXXX01*/ "SYSMMU_S2_GSA", 0x3}, + {"GSA", 0x2, /*XXXX10*/ "SYSMMU_S1_GSA", 0x3}, + {"GSA", 0x4, /*XXX100*/ "GME", 0x7}, + {"GSA", 0x0, /*000000*/ "CA32", 0x3F}, + {"GSA", 0x10,/*010000*/ "SSS_GSACORE", 0x3F}, + {"GSA", 0x20,/*100000*/ "DMA_GSACORE", 0x3F}, + {"GSA", 0x30,/*110000*/ "DAP", 0x3F}, + + {"ALIVE", 0x1, /*XXXXX1*/ "SYSMMU_S2_APM", 0x1}, + {"ALIVE", 0x0, /*XX0000*/ "APM", 0xF}, + + {"HSI0", 0x1, /*XXXX01*/ "SYSMMU_S2_HSI0", 0x3}, + {"HSI0", 0x2, /*XXXX10*/ "SYSMMU_S1_HSI0", 0x3}, + {"HSI0", 0x0, /*XXX000*/ "USB31DRD_LINK", 0x7}, + {"HSI0", 0x4, /*XXX100*/ "USB PCS", 0x7}, + + {"HSI1", 0x1, /*XXXX01*/ "SYSMMU_S2_HSI1", 0x3}, + {"HSI1", 0x2, /*XXXX10*/ "SYSMMU_S1_HSI1", 0x3}, + {"HSI1", 0x0, /*XXX000*/ "PCIE_GEN4A", 0x7}, + {"HSI1", 0x2, /*XXX100*/ "PCIE_GEN4B", 0x7}, + + {"CSSYS", 0x4, /*XXX100*/ "SYSMMU_S2_CPUCL0", 0x7}, + {"CSSYS", 0x0, /*XXX000*/ "CORESIGHT(ETR)", 0x7}, + {"CSSYS", 0x1, /*XXXX01*/ "CORESIGHT(AXI-AP)", 0x3}, + {"CSSYS", 0x2, /*XXXX10*/ "DBGC", 0x3}, + + {"AOC", 0x1, /*XXXX01*/ "SYSMMU_S2_AOC", 0x3}, + {"AOC", 0x2, /*XXXX10*/ "SYSMMU_S1_AOC", 0x3}, + {"AOC", 0x0, /*XXXX00*/ "A32", 0x1F}, + {"AOC", 0x4, /*X00100*/ "HF0", 0x1F}, + {"AOC", 0x8, /*X01000*/ "HF1", 0x1F}, + {"AOC", 0xc, /*X01100*/ "F1", 0x1F}, + + {"DPU0", 0x1, /*XXXX01*/ "SYSMMU_S2_DPU0", 0x3}, + {"DPU0", 0x2, /*XXXX10*/ "SYSMMU_S1_DPU0", 0x3}, + {"DPU0", 0x0, /*XXXX00*/ "DPU(M0)", 0x3}, + + {"DPU1", 0x1, /*XXXX01*/ "SYSMMU_S2_DPU1", 0x3}, + {"DPU1", 0x2, /*XXXX10*/ "SYSMMU_S1_DPU1", 0x3}, + {"DPU1", 0x0, /*XXXX00*/ "DPU(M1)", 0x3}, + + {"DPU2", 0x1, /*XXXX01*/ "SYSMMU_S2_DPU1", 0x3}, + {"DPU2", 0x2, /*XXXX10*/ "SYSMMU_S1_DPU1", 0x3}, + {"DPU2", 0x0, /*XXXX00*/ "DPU(M2)", 0x3}, + + {"CSIS0", 0x1, /*XXXX01*/ "SYSMMU_S2_CSIS0", 0x3}, + {"CSIS0", 0x2, /*XXXX10*/ "SYSMMU_S1_CSIS0", 0x3}, + {"CSIS0", 0x0, /*X00000*/ "CSIC(DMA2)", 0x1F}, + {"CSIS0", 0x4, /*X00100*/ "CSIC(DMA3)", 0x1F}, + {"CSIS0", 0x8, /*X01000*/ "CSIC(ZSL0)", 0x1F}, + {"CSIS0", 0xC, /*X01100*/ "CSIC(ZSL1)", 0x1F}, + {"CSIS0", 0x10,/*X10000*/ "CSIC(ZSL2)", 0x1F}, + + {"CSIS1", 0x1, /*XXXX01*/ "SYSMMU_S2_CSIS1", 0x3}, + {"CSIS1", 0x2, /*XXXX10*/ "SYSMMU_S1_CSIS1", 0x3}, + {"CSIS1", 0x0, /*000000*/ "CSIC(DMA0)", 0x3F}, + {"CSIS1", 0x8, /*001000*/ "CSIC(DMA1)", 0x3F}, + {"CSIS1", 0x10,/*010000*/ "CSIC(STRP0)", 0x3F}, + {"CSIS1", 0x18,/*011000*/ "CSIC(STRP1)", 0x3F}, + {"CSIS1", 0x20,/*100000*/ "CSIC(STRP2)", 0x3F}, + {"CSIS1", 0x4, /*X00100*/ "CSIC(PDP_STAT0)", 0x1F}, + {"CSIS1", 0xC, /*X01100*/ "CSIC(PDP_STAT1)", 0x1F}, + {"CSIS1", 0x14,/*X10100*/ "CSIC(PDP_AF0)", 0x1F}, + {"CSIS1", 0x1C,/*X11100*/ "CSIC(PDP_AF1)", 0x1F}, + + {"G3AA", 0x1, /*XXXX01*/ "SYSMMU_S2_G3AA", 0x3}, + {"G3AA", 0x2, /*XXXX10*/ "SYSMMU_S1_G3AA", 0x3}, + {"G3AA", 0x0, /*XXXX00*/ "G3AA", 0x3}, + + {"IPP", 0x1, /*XXXX01*/ "SYSMMU_S2_IPP", 0x3}, + {"IPP", 0x2, /*XXXX10*/ "SYSMMU_S1_IPP", 0x3}, + {"IPP", 0x0, /*000000*/ "IPP(THSTAT)", 0x3F}, + {"IPP", 0x8, /*001000*/ "IPP(FDPIG)", 0x3F}, + {"IPP", 0x10,/*010000*/ "IPP(RBGH0)", 0x3F}, + {"IPP", 0x18,/*011000*/ "IPP(RBGH1)", 0x3F}, + {"IPP", 0x20,/*100000*/ "IPP(RBGH2)", 0x3F}, + {"IPP", 0x04,/*000100*/ "IPP(ALIGN0)", 0x3F}, + {"IPP", 0x0C,/*001100*/ "IPP(ALIGN1)", 0x3F}, + {"IPP", 0x14,/*010100*/ "IPP(ALIGN2)", 0x3F}, + {"IPP", 0x1C,/*011100*/ "IPP(ALIGN3)", 0x3F}, + {"IPP", 0x24,/*100100*/ "IPP(ALIGN_STAT)", 0x3F}, + {"IPP", 0x2C,/*101100*/ "TNR_ALIGN(TNR_MSA0)", 0x3F}, + + {"DNS", 0x1, /*XXXX01*/ "SYSMMU_S2_DNS", 0x3}, + {"DNS", 0x2, /*XXXX10*/ "SYSMMU_S1_DNS", 0x3}, + {"DNS", 0x0, /*X00000*/ "DNS0", 0x1F}, + {"DNS", 0x10,/*X10000*/ "DNS1", 0x1F}, + {"DNS", 0x4, /*X00100*/ "VRA", 0x1F}, + {"DNS", 0x8, /*X01000*/ "TNR_ALIGN(TNR_MSA1)", 0x1F}, + {"DNS", 0xC, /*001100*/ "ITSC(M0/M2)", 0x3F}, + {"DNS", 0x2C,/*101100*/ "ITSC(M1)", 0x3F}, + {"DNS", 0x1C,/*X11100*/ "ITP", 0x1F}, + + {"MCSC0", 0x1, /*XXXX01*/ "SYSMMU_S2_MCSC0", 0x3}, + {"MCSC0", 0x2, /*XXXX10*/ "SYSMMU_S1_MCSC0", 0x3}, + {"MCSC0", 0x0, /*XXXX00*/ "ITSC(M0)", 0x3}, + + {"MCSC1", 0x1, /*XXXX01*/ "SYSMMU_S2_MCSC1", 0x3}, + {"MCSC1", 0x2, /*XXXX10*/ "SYSMMU_S1_MCSC1", 0x3}, + {"MCSC1", 0x0, /*XX0000*/ "MCSC(M0)", 0xF}, + {"MCSC1", 0x4, /*XX0100*/ "MCSC(M2)", 0xF}, + {"MCSC1", 0x8, /*XX1000*/ "MCSC(M3)", 0xF}, + + {"MCSC2", 0x1, /*XXXX01*/ "SYSMMU_S2_MCSC2", 0x3}, + {"MCSC2", 0x2, /*XXXX10*/ "SYSMMU_S1_MCSC2", 0x3}, + {"MCSC2", 0x0, /*XX0000*/ "MCSC(M1)", 0xF}, + {"MCSC2", 0x4, /*XX0100*/ "MCSC(M4)", 0xF}, + {"MCSC2", 0x8, /*XX1000*/ "MCSC(M5)", 0xF}, + + {"TNR0", 0x1, /*XXXX01*/ "SYSMMU_S2_TNR0", 0x3}, + {"TNR0", 0x2, /*XXXX10*/ "SYSMMU_S1_TNR0", 0x3}, + {"TNR0", 0x0, /*XX0000*/ "TNR(M0)", 0xF}, + {"TNR0", 0x4, /*XX0100*/ "TNR(M1)", 0xF}, + {"TNR0", 0x8, /*XX1000*/ "TNR(M8)", 0xF}, + + {"TNR1", 0x1, /*XXXX01*/ "SYSMMU_S2_TNR1", 0x3}, + {"TNR1", 0x2, /*XXXX10*/ "SYSMMU_S1_TNR1", 0x3}, + {"TNR1", 0x0, /*XXXX00*/ "TNR(M2)", 0x3}, + + {"TNR2", 0x1, /*XXXX01*/ "SYSMMU_S2_TNR2", 0x3}, + {"TNR2", 0x2, /*XXXX10*/ "SYSMMU_S1_TNR2", 0x3}, + {"TNR2", 0x0, /*XXXX00*/ "TNR(M3)", 0x3}, + + {"TNR3", 0x1, /*XXXX01*/ "SYSMMU_S2_TNR3", 0x3}, + {"TNR3", 0x2, /*XXXX10*/ "SYSMMU_S1_TNR3", 0x3}, + {"TNR3", 0x0, /*XXXX00*/ "TNR(M4)", 0x3}, + + {"TNR4", 0x1, /*XXXX01*/ "SYSMMU_S2_TNR4", 0x3}, + {"TNR4", 0x2, /*XXXX10*/ "SYSMMU_S1_TNR4", 0x3}, + {"TNR4", 0x0, /*XX0000*/ "TNR(M5)", 0xF}, + {"TNR4", 0x4, /*XX0100*/ "TNR(M6)", 0xF}, + {"TNR4", 0x8, /*XX1000*/ "TNR(M7)", 0xF}, + + {"BO", 0x1, /*XXXX01*/ "SYSMMU_S2_BO", 0x3}, + {"BO", 0x2, /*XXXX10*/ "SYSMMU_S1_BO", 0x3}, + {"BO", 0x0, /*XXXX00*/ "BO", 0x3}, + + {"MFC0", 0x1, /*XXXX01*/ "SYSMMU_S2_MFC0", 0x3}, + {"MFC0", 0x2, /*XXXX10*/ "SYSMMU_S1_MFC0", 0x3}, + {"MFC0", 0x0, /*XXXX00*/ "MFC0", 0x3}, + + {"MFC1", 0x1, /*XXXX01*/ "SYSMMU_S2_MFC1", 0x3}, + {"MFC1", 0x2, /*XXXX10*/ "SYSMMU_S1_MFC1", 0x3}, + {"MFC1", 0x0, /*XXXX00*/ "MFC1", 0x3}, + + {"G2D0", 0x1, /*XXXX01*/ "SYSMMU_S2_G2D0", 0x3}, + {"G2D0", 0x2, /*XXXX10*/ "SYSMMU_S1_G2D0", 0x3}, + {"G2D0", 0x0, /*XXXX00*/ "G2D0", 0x3}, + + {"G2D1", 0x1, /*XXXX01*/ "SYSMMU_S2_G2D1", 0x3}, + {"G2D1", 0x2, /*XXXX10*/ "SYSMMU_S1_G2D1", 0x3}, + {"G2D1", 0x0, /*XXXX00*/ "G2D1", 0x3}, + + {"G2D2", 0x1, /*XXXX01*/ "SYSMMU_S2_G2D2", 0x3}, + {"G2D2", 0x2, /*XXXX10*/ "SYSMMU_S1_G2D2", 0x3}, + {"G2D2", 0x0, /*XXXX00*/ "G2D2", 0x3}, + + {"HSI2", 0x1, /*XXXX01*/ "SYSMMU_S2_HSI2", 0x3}, + {"HSI2", 0x2, /*XXXX10*/ "SYSMMU_S1_HSI2", 0x3}, + {"HSI2", 0x0, /*XX0000*/ "PCIE_GEN4A", 0xF}, + {"HSI2", 0x4, /*XX0100*/ "PCIE_GEN4B", 0xF}, + {"HSI2", 0x8, /*XX1000*/ "UFS_EMBD", 0xF}, + {"HSI2", 0xC, /*XX1100*/ "MMC_CARD", 0xF}, + + {"MISC", 0x1, /*XXXXX1*/ "SYSMMU_S2_MISC", 0x1}, + {"MISC", 0x10,/*X10000*/ "SYSMMU_S2_SSS", 0x1F}, + {"MISC", 0x0, /*X00000*/ "SSS", 0x1F}, + {"MISC", 0x2, /*XX0010*/ "RTIC", 0xF}, + {"MISC", 0x4, /*XX0100*/ "SPDMA0", 0xF}, + {"MISC", 0x6, /*XX0110*/ "PDMA0", 0xF}, + {"MISC", 0x8, /*XX1000*/ "DIT", 0xF}, + {"MISC", 0xA, /*XX1010*/ "SPDMA1", 0xF}, + {"MISC", 0xC, /*XX1100*/ "PDMA1", 0xF}, + + {"GDC0", 0x1, /*XXXX01*/ "SYSMMU_S2_GDC0", 0x3}, + {"GDC0", 0x2, /*XXXX10*/ "SYSMMU_S1_GDC0", 0x3}, + {"GDC0", 0x0, /*XXX000*/ "GDC0(M0)", 0x7}, + {"GDC0", 0x4, /*XXX100*/ "GDC0(M1)", 0x7}, + + {"GDC1", 0x1, /*XXXX01*/ "SYSMMU_S2_GDC1", 0x3}, + {"GDC1", 0x2, /*XXXX10*/ "SYSMMU_S1_GDC1", 0x3}, + {"GDC1", 0x0, /*XX0000*/ "GDC1(M0)", 0xF}, + {"GDC1", 0x4, /*XX0100*/ "GDC1(M1)", 0xF}, + {"GDC1", 0x8, /*XX1000*/ "SCSC(M2)", 0xF}, + + {"GDC2", 0x1, /*XXXX01*/ "SYSMMU_S2_GDC2", 0x3}, + {"GDC2", 0x2, /*XXXX10*/ "SYSMMU_S1_GDC2", 0x3}, + {"GDC2", 0x0, /*XXX000*/ "SCSC(M0)", 0x7}, + {"GDC2", 0x4, /*XXX100*/ "SCSC(M1)", 0x7}, + + {"GPU0", 0x1, /*XXXXX1*/ "SYSMMU_S2_GPU0", 0x1}, + {"GPU0", 0x0, /*XXXXX0*/ "GPU(M0)", 0x1}, + + {"GPU1", 0x1, /*XXXXX1*/ "SYSMMU_S2_GPU1", 0x1}, + {"GPU1", 0x0, /*XXXXX0*/ "GPU(M1)", 0x1}, + + {"GPU2", 0x1, /*XXXXX1*/ "SYSMMU_S2_GPU2", 0x1}, + {"GPU2", 0x0, /*XXXXX0*/ "GPU(M2)", 0x1}, + + {"GPU3", 0x1, /*XXXXX1*/ "SYSMMU_S2_GPU3", 0x1}, + {"GPU3", 0x0, /*XXXXX0*/ "GPU(M3)", 0x1}, + + {"TPU", 0x1, /*XXXX01*/ "SYSMMU_S2_TPU", 0x3}, + {"TPU", 0x2, /*XXXX10*/ "SYSMMU_S1_TPU", 0x3}, + {"TPU", 0x0, /*XXXX00*/ "TPU", 0x3}, + + {"AUR0", 0x1, /*XXXX01*/ "SYSMMU_D0_S2_AUR1", 0x3}, + {"AUR0", 0x2, /*XXXX10*/ "SYSMMU_D0_S1_AUR1", 0x3}, + {"AUR0", 0x0, /*XXXX00*/ "AUR_M0", 0x3}, + + {"AUR1", 0x1, /*XXXX01*/ "SYSMMU_D1_S2_AUR1", 0x3}, + {"AUR1", 0x2, /*XXXX10*/ "SYSMMU_D1_S1_AUR1", 0x3}, + {"AUR1", 0x0, /*XXXX00*/ "AUR_M1", 0x3}, + + /* Cannot differentiate which cpu */ + {"CPU0", 0x40, /*bit 25*/ "CPU", 0x40}, + {"CPU1", 0x40, /*bit 25*/ "CPU", 0x40}, + {"CPU2", 0x40, /*bit 25*/ "CPU", 0x40}, + {"CPU3", 0x40, /*bit 25*/ "CPU", 0x40}, + /* Cannot differentiate others */ + {"CPU0", 0x0, /*bit 25*/ "NOT CPU", 0x40}, + {"CPU1", 0x0, /*bit 25*/ "NOT CPU", 0x40}, + {"CPU2", 0x0, /*bit 25*/ "NOT CPU", 0x40}, + {"CPU3", 0x0, /*bit 25*/ "NOT CPU", 0x40}, + +}; + +static struct itmon_nodeinfo vec_d0[] = { + {M_NODE, "ALIVE", 0x1EA03000, 1, 1, 0, 0}, + {M_NODE, "AOC", 0x1EA13000, 1, 1, 0, 0}, + {M_NODE, "CSSYS", 0x1EA23000, 1, 1, 0, 0}, + {M_NODE, "GSA", 0x1EA33000, 1, 1, 0, 0}, + {M_NODE, "HSI0", 0x1EA43000, 1, 1, 0, 0}, + {M_NODE, "HSI1", 0x1EA53000, 1, 1, 0, 0}, + {T_S_NODE, "BUS0_M0", 0x1EA63000, 1, 1, 0, 0}, +}; + +static struct itmon_nodeinfo vec_d1[] = { + {M_NODE, "BO", 0x1F403000, 1, 1, 0, 0}, + {M_NODE, "CSIS0", 0x1F413000, 1, 1, 0, 0}, + {M_NODE, "CSIS1", 0x1F423000, 1, 1, 0, 0}, + {M_NODE, "DNS", 0x1F433000, 1, 1, 0, 0}, + {M_NODE, "DPU0", 0x1F443000, 1, 1, 0, 0}, + {M_NODE, "DPU1", 0x1F453000, 1, 1, 0, 0}, + {M_NODE, "DPU2", 0x1F463000, 1, 1, 0, 0}, + {M_NODE, "G2D0", 0x1F4A3000, 1, 1, 0, 0}, + {M_NODE, "G2D1", 0x1F4B3000, 1, 1, 0, 0}, + {M_NODE, "G2D2", 0x1F4C3000, 1, 1, 0, 0}, + {M_NODE, "G3AA", 0x1F4D3000, 1, 1, 0, 0}, + {M_NODE, "GDC0", 0x1F473000, 1, 1, 0, 0}, + {M_NODE, "GDC1", 0x1F483000, 1, 1, 0, 0}, + {M_NODE, "GDC2", 0x1F493000, 1, 1, 0, 0}, + {M_NODE, "HSI2", 0x1F4E3000, 1, 1, 0, 0}, + {M_NODE, "IPP", 0x1F4F3000, 1, 1, 0, 0}, + {M_NODE, "MCSC0", 0x1F503000, 1, 1, 0, 0}, + {M_NODE, "MCSC1", 0x1F513000, 1, 1, 0, 0}, + {M_NODE, "MCSC2", 0x1F523000, 1, 1, 0, 0}, + {M_NODE, "MFC0", 0x1F533000, 1, 1, 0, 0}, + {M_NODE, "MFC1", 0x1F543000, 1, 1, 0, 0}, + {M_NODE, "MISC", 0x1F553000, 1, 1, 0, 0}, + {M_NODE, "TNR0", 0x1F563000, 1, 1, 0, 0}, + {M_NODE, "TNR1", 0x1F573000, 1, 1, 0, 0}, + {M_NODE, "TNR2", 0x1F583000, 1, 1, 0, 0}, + {M_NODE, "TNR3", 0x1F593000, 1, 1, 0, 0}, + {M_NODE, "TNR4", 0x1F5A3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL2A_M0", 0x1F5B3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL2A_M1", 0x1F5C3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL2A_M2", 0x1F5D3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL2A_M3", 0x1F5E3000, 1, 1, 0, 0}, +}; + +static struct itmon_nodeinfo vec_d2[] = { + {M_NODE, "AUR0", 0x20403000, 1, 1, 0, 0}, + {M_NODE, "AUR1", 0x20413000, 1, 1, 0, 0}, + {M_NODE, "GPU0", 0x20433000, 1, 1, 0, 0}, + {M_NODE, "GPU1", 0x20443000, 1, 1, 0, 0}, + {M_NODE, "GPU2", 0x20453000, 1, 1, 0, 0}, + {M_NODE, "GPU3", 0x20463000, 1, 1, 0, 0}, + {M_NODE, "GPUMMU", 0x20423000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL1A_S0", 0x20483000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL1A_S1", 0x20493000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL1A_S2", 0x204A3000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL1A_S3", 0x204B3000, 1, 1, 0, 0}, + {M_NODE, "TPU", 0x20473000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL1A_M0", 0x204C3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL1A_M1", 0x204D3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL1A_M2", 0x204E3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL1A_M3", 0x204F3000, 1, 1, 0, 0}, +}; + +static struct itmon_nodeinfo vec_d3[] = { + {M_NODE, "CPU0", 0x1E403000, 1, 1, 0, 0}, + {M_NODE, "CPU1", 0x1E413000, 1, 1, 0, 0}, + {M_NODE, "CPU2", 0x1E423000, 1, 1, 0, 0}, + {M_NODE, "CPU3", 0x1E433000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL0_S0", 0x1E443000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL0_S1", 0x1E453000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL0_S2", 0x1E463000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL0_S3", 0x1E473000, 1, 1, 0, 0}, + {T_M_NODE, "NOCL0_S4", 0x1E483000, 1, 1, 0, 0}, + {S_NODE, "NOCL0_CCI", 0x1E493000, 1, 1, 0, 0}, + {S_NODE, "NOCL0_DP", 0x1E4A3000, 1, 1, 0, 0, TMOUT, 1}, + {T_S_NODE, "NOCL0_M0", 0x1E4B3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL0_M1", 0x1E4C3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL0_M2", 0x1E4D3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL0_M3", 0x1E4E3000, 1, 1, 0, 0}, +}; + +static struct itmon_nodeinfo vec_p0[] = { + {M_NODE, "CCI", 0x1E603000, 1, 1, 0, 0}, + {M_NODE, "CSSYS", 0x1E613000, 1, 1, 0, 0}, + {M_NODE, "NOCL0_DP", 0x1E623000, 1, 1, 0, 0}, + {S_NODE, "ALIVE", 0x1E633000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "CPUCL0", 0x1E643000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "EH", 0x1E653000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "GIC", 0x1E663000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MIF0", 0x1E673000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MIF1", 0x1E683000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MIF2", 0x1E693000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MIF3", 0x1E6A3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MISC", 0x1E6B3000, 1, 1, 0, 0, TMOUT, 1}, + {T_S_NODE, "NOCL0_M0", 0x1E6E3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL1_M1", 0x1E6F3000, 1, 1, 0, 0}, + {T_S_NODE, "NOCL2_M2", 0x1E703000, 1, 1, 0, 0}, + {S_NODE, "P0_NOCL0", 0x1E713000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P1_NOCL0", 0x1E723000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P2_NOCL0", 0x1E733000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "PERIC0", 0x1E6C3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "PERIC1", 0x1E6D3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "SLC", 0x1E743000, 1, 1, 0, 0, TMOUT, 1}, +}; + +static struct itmon_nodeinfo vec_p1[] = { + {T_M_NODE, "NOCL1B_S0", 0x1EC03000, 1, 1, 0, 0}, + {S_NODE, "AOC", 0x1EC13000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "GSA", 0x1EC23000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "HSI0", 0x1EC33000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "HSI1", 0x1EC43000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P0_NOCL1B", 0x1EC53000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P1_NOCL1B", 0x1EC63000, 1, 1, 0, 0, TMOUT, 1}, +}; + +static struct itmon_nodeinfo vec_p2[] = { + {T_M_NODE, "NOCL2A_S0", 0x1F203000, 1, 1, 0, 0}, + {S_NODE, "BO", 0x1F213000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "CSIS", 0x1F223000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "DISP", 0x1F233000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "DNS", 0x1F243000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "DPU", 0x1F253000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "G2D", 0x1F273000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "G3AA", 0x1F283000, 1, 1, 0, 0, TMOUT, 0}, + {S_NODE, "GDC", 0x1F263000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "HSI2", 0x1F293000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "IPP", 0x1F2A3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "ITP", 0x1F2B3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MCSC", 0x1F2C3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "MFC", 0x1F2D3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P0_NOCL2A", 0x1F303000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P1_NOCL2A", 0x1F313000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "PDP", 0x1F2E3000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "TNR", 0x1F2F3000, 1, 1, 0, 0, TMOUT, 1}, +}; + +static struct itmon_nodeinfo vec_p3[] = { + {T_M_NODE, "NOCL1A_S0", 0x20603000, 1, 1, 0}, + {S_NODE, "AUR", 0x20613000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "G3D", 0x20623000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P0_NOCL1A", 0x20643000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "P1_NOCL1A", 0x20653000, 1, 1, 0, 0, TMOUT, 1}, + {S_NODE, "TPU", 0x20633000, 1, 1, 0, 0, TMOUT, 1}, +}; + +static struct itmon_nodegroup nodegroup[] = { + {"BUS_DATA0", 0x1EA83000, 0, vec_d0, ARRAY_SIZE(vec_d0), DATA}, /* 637 */ + {"BUS_DATA1", 0x1F603000, 0, vec_d1, ARRAY_SIZE(vec_d1), DATA}, /* 640 */ + {"BUS_DATA2", 0x20513000, 0, vec_d2, ARRAY_SIZE(vec_d2), DATA}, /* 625 */ + {"BUS_DATA3", 0x1E503000, 0, vec_d3, ARRAY_SIZE(vec_d3), DATA}, /* 596 */ + {"BUS_PERI0", 0x1E773000, 0, vec_p0, ARRAY_SIZE(vec_p0), PERI}, /* 607 */ + {"BUS_PERI1", 0x1EC83000, 0, vec_p1, ARRAY_SIZE(vec_p1), PERI}, /* 638 */ + {"BUS_PERI2", 0x1F333000, 0, vec_p2, ARRAY_SIZE(vec_p2), PERI}, /* 641 */ + {"BUS_PERI3", 0x20673000, 0, vec_p3, ARRAY_SIZE(vec_p3), PERI}, /* 626 */ +}; + +const static char *itmon_pathtype[] = { + "DATA Path transaction", + "Configuration(SFR) Path transaction", +}; + +/* Error Code Description */ +const static char *itmon_errcode[] = { + "Error Detect by the Slave(SLVERR)", + "Decode error(DECERR)", + "Unsupported transaction error", + "Power Down access error", + "Unsupported transaction", + "Unsupported transaction", + "Timeout error - response timeout in timeout value", + "Invalid errorcode", +}; + +const static char *itmon_node_string[] = { + "M_NODE", + "TAXI_S_NODE", + "TAXI_M_NODE", + "S_NODE", +}; + +const static char *itmon_cpu_node_string[] = { + "M_CPU", + "SCI_IRPM", + "SCI_CCM", + "CCI", +}; + +const static char *itmon_drex_node_string[] = { + "DREX_IRPS", + "CORE_CCI", + "CORE_M", +}; + +const static unsigned int itmon_invalid_addr[] = { + 0x03000000, + 0x04000000, +}; + +static struct itmon_dev *g_itmon; + +/* declare notifier_list */ +ATOMIC_NOTIFIER_HEAD(itmon_notifier_list); + +static void itmon_pattern_reset(struct itmon_dev *itmon) +{ + atomic_set(&itmon->itmon_pattern_cnt, 0); +} + +static void itmon_pattern_set(struct itmon_dev *itmon, const char *fmt, ...) +{ + va_list args; + + /* only take the first pattern even there could be multiple paths */ + if (atomic_inc_return(&itmon->itmon_pattern_cnt) > 1) + return; + + va_start(args, fmt); + vsnprintf(itmon->itmon_pattern, sizeof(itmon->itmon_pattern), fmt, args); + va_end(args); +} + +static const struct itmon_rpathinfo *itmon_get_rpathinfo(struct itmon_dev *itmon, + unsigned int id, + char *dest_name) +{ + struct itmon_platdata *pdata = itmon->pdata; + const struct itmon_rpathinfo *rpath = NULL; + int i; + + if (!dest_name) + return NULL; + + for (i = 0; i < (int)ARRAY_SIZE(rpathinfo); i++) { + if (pdata->rpathinfo[i].id == (id & pdata->rpathinfo[i].bits)) { + if (dest_name && !strncmp(pdata->rpathinfo[i].dest_name, dest_name, + strlen(pdata->rpathinfo[i].dest_name))) { + rpath = &pdata->rpathinfo[i]; + break; + } + } + } + return rpath; +} + +static const struct itmon_clientinfo *itmon_get_clientinfo(struct itmon_dev *itmon, + char *port_name, + unsigned int user) +{ + struct itmon_platdata *pdata = itmon->pdata; + const struct itmon_clientinfo *client = NULL; + unsigned int val; + int i; + + if (!port_name) + return NULL; + + /* shift directly to SID bits */ + user >>= 19; + + for (i = 0; i < (int)ARRAY_SIZE(clientinfo); i++) { + if (!strcmp(pdata->clientinfo[i].port_name, port_name)) { + val = user & pdata->clientinfo[i].bits; + if (val == pdata->clientinfo[i].user) { + client = &pdata->clientinfo[i]; + break; + } + } + } + return client; +} + +static void itmon_enable_addr_detect(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, bool enabled) +{ + /* This feature is only for M_NODE */ + unsigned int tmp, val; + unsigned int offset = OFFSET_PROT_CHK; + + val = __raw_readl(node->regs + offset + REG_PROT_CHK_CTL); + val |= INTEND_ACCESS_INT_ENABLE; + __raw_writel(val, node->regs + offset + REG_PROT_CHK_CTL); + + val = ((unsigned int)INTEND_ADDR_START & U32_MAX); + __raw_writel(val, node->regs + offset + REG_PROT_CHK_START_ADDR_LOW); + + val = (unsigned int)(((unsigned long)INTEND_ADDR_START >> 32) & U16_MAX); + __raw_writel(val, node->regs + offset + + REG_PROT_CHK_START_END_ADDR_UPPER); + + val = ((unsigned int)INTEND_ADDR_END & 0xFFFFFFFF); + __raw_writel(val, node->regs + offset + + REG_PROT_CHK_END_ADDR_LOW); + val = ((unsigned int)(((unsigned long)INTEND_ADDR_END >> 32) + & 0XFFFF0000) << 16); + tmp = readl(node->regs + offset + REG_PROT_CHK_START_END_ADDR_UPPER); + __raw_writel(tmp | val, node->regs + offset + + REG_PROT_CHK_START_END_ADDR_UPPER); + + dev_dbg(itmon->dev, "ITMON - %s addr detect enabled\n", node->name); +} + +static void itmon_enable_prot_chk(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + bool enabled) +{ + unsigned int offset = OFFSET_PROT_CHK; + unsigned int val = 0; + + if (enabled) + val = RD_RESP_INT_ENABLE | WR_RESP_INT_ENABLE | + ARLEN_RLAST_INT_ENABLE | AWLEN_WLAST_INT_ENABLE; + + __raw_writel(val, node->regs + offset + REG_PROT_CHK_CTL); + + dev_dbg(itmon->dev, "ITMON - %s hw_assert enabled\n", node->name); +} + +static void itmon_enable_err_report(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + bool enabled) +{ + struct itmon_platdata *pdata = itmon->pdata; + unsigned int offset = OFFSET_REQ_R; + + if (!pdata->probed || !node->retention) + __raw_writel(1, node->regs + offset + REG_INT_CLR); + + /* enable interrupt */ + __raw_writel(enabled, node->regs + offset + REG_INT_MASK); + + /* clear previous interrupt of req_write */ + offset = OFFSET_REQ_W; + if (pdata->probed || !node->retention) + __raw_writel(1, node->regs + offset + REG_INT_CLR); + /* enable interrupt */ + __raw_writel(enabled, node->regs + offset + REG_INT_MASK); + + /* clear previous interrupt of response_read */ + offset = OFFSET_RESP_R; + if (!pdata->probed || !node->retention) + __raw_writel(1, node->regs + offset + REG_INT_CLR); + /* enable interrupt */ + __raw_writel(enabled, node->regs + offset + REG_INT_MASK); + + /* clear previous interrupt of response_write */ + offset = OFFSET_RESP_W; + if (!pdata->probed || !node->retention) + __raw_writel(1, node->regs + offset + REG_INT_CLR); + /* enable interrupt */ + __raw_writel(enabled, node->regs + offset + REG_INT_MASK); + + dev_dbg(itmon->dev, + "ITMON - %s error reporting enabled\n", node->name); +} + +static void itmon_enable_timeout(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + bool enabled) +{ + unsigned int offset = OFFSET_TMOUT_REG; + + /* Enable Timeout setting */ + __raw_writel(enabled, node->regs + offset + REG_DBG_CTL); + + /* set tmout interval value */ + __raw_writel(node->time_val, + node->regs + offset + REG_TMOUT_INIT_VAL); + + if (node->tmout_frz_enabled) { + /* Enable freezing */ + __raw_writel(enabled, + node->regs + offset + REG_TMOUT_FRZ_EN); + } + dev_dbg(itmon->dev, "ITMON - %s timeout enabled\n", node->name); +} + +static void itmon_init(struct itmon_dev *itmon, bool enabled) +{ + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_nodeinfo *node; + int i, j; + + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + node = pdata->nodegroup[i].nodeinfo; + for (j = 0; j < pdata->nodegroup[i].nodesize; j++) { + if (node[j].type == S_NODE && node[j].tmout_enabled) + itmon_enable_timeout(itmon, &node[j], true); + + if (node[j].err_enabled) + itmon_enable_err_report(itmon, &node[j], true); + + if (node[j].prot_chk_enabled) + itmon_enable_prot_chk(itmon, &node[j], true); + + if (node[j].addr_detect_enabled) + itmon_enable_addr_detect(itmon, &node[j], true); + + dev_dbg(itmon->dev, "ITMON - %s init -\n", node[j].name); + } + } +} + +void itmon_enable(bool enabled) +{ + if (g_itmon) + itmon_init(g_itmon, enabled); +} + +static void itmon_post_handler_apply_policy(struct itmon_dev *itmon, + int ret_value) +{ + struct itmon_platdata *pdata = itmon->pdata; + + switch (ret_value) { + case NOTIFY_STOP: + log_dev_err(itmon->dev, "notify calls response NOTIFY_STOP, refer to notifier log\n"); + pdata->policy[IP].error = true; + break; + case NOTIFY_BAD: + log_dev_err(itmon->dev, "notify calls response NOTIFY_BAD, refer to notifier log\n"); + pdata->policy[FATAL].error = true; + break; + case NOTIFY_OK: + case NOTIFY_DONE: + default: + log_dev_err(itmon->dev, "notify calls response NOTIFY_OK/DONE\n"); + pdata->policy[UNHANDLED].error = true; + break; + } +} + +static void itmon_post_handler_to_notifier(struct itmon_dev *itmon, + struct itmon_traceinfo *info, + unsigned int trans_type) +{ + int ret = 0; + + /* After treatment by port */ + if (!info->port || strlen(info->port) < 1) + return; + + itmon->notifier_info.port = info->port; + itmon->notifier_info.client = info->client; + itmon->notifier_info.dest = info->dest; + itmon->notifier_info.read = info->read; + itmon->notifier_info.target_addr = info->target_addr; + itmon->notifier_info.errcode = info->errcode; + itmon->notifier_info.onoff = info->onoff; + + log_dev_err(itmon->dev, " +ITMON Notifier Call Information\n\n"); + + /* call notifier_call_chain of itmon */ + ret = atomic_notifier_call_chain(&itmon_notifier_list, + 0, &itmon->notifier_info); + itmon_post_handler_apply_policy(itmon, ret); + + log_dev_err(itmon->dev, " -ITMON Notifier Call Information\n" + "-----------------------------------------------------------\n"); +} + +static void itmon_post_handler_by_dest(struct itmon_dev *itmon, + struct itmon_traceinfo *info, + unsigned int trans_type) +{ + struct itmon_platdata *pdata = itmon->pdata; + + if (!info->dest || strlen(info->dest) < 1) + return; + + if (info->errcode == ERRCODE_TMOUT) { + int i; + + for (i = 0; i < (int)ARRAY_SIZE(itmon_drex_node_string); i++) { + if (!strcmp(info->dest, itmon_drex_node_string[i])) { + pdata->policy[DREX_TMOUT].error = true; + break; + } + + } + } +} + +static void itmon_post_handler_by_client(struct itmon_dev *itmon, + struct itmon_traceinfo *info, + unsigned int trans_type) +{ + struct itmon_platdata *pdata = itmon->pdata; + + /* After treatment by port */ + if (!info->port || strlen(info->port) < 1) + return; + + if (test_bit(FROM_CPU, &info->from)) { + ktime_t now, interval; + + now = ktime_get(); + interval = ktime_sub(now, pdata->last_time); + pdata->last_time = now; + pdata->err_cnt_by_cpu++; + if (pdata->err_cnt_by_cpu > pdata->panic_threshold) + pdata->policy[CPU].error = true; + + if (info->errcode == ERRCODE_TMOUT) { + pdata->policy[FATAL].error = true; + log_dev_err(itmon->dev, + "Try to handle error, even CPU transaction detected - %s\n", + itmon_errcode[info->errcode]); + } else { + log_dev_err(itmon->dev, "Skips CPU transaction detected - err_cnt_by_cpu: %u, interval: %lldns\n", + pdata->err_cnt_by_cpu, ktime_to_ns(interval)); + + /* Ignore unhandled cpu errors */ + pdata->policy[UNHANDLED].error = false; + } + } else { + if (info->errcode == ERRCODE_UNSUPPORTED) + pdata->policy[FATAL].error = true; + } +} + +static void itmon_report_timeout(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + unsigned int trans_type) +{ + unsigned int id, payload0, payload1 = 0, payload2, payload3, payload4; + unsigned int axid, user, valid, timeout, info; + unsigned long addr; + char *client_name, *port_name; + const struct itmon_rpathinfo *port; + const struct itmon_clientinfo *client; + struct itmon_nodegroup *group = NULL; + int i, num = (trans_type == TRANS_TYPE_READ ? SZ_128 : SZ_64); + int rw_offset = (trans_type == TRANS_TYPE_READ ? 0 : REG_TMOUT_BUF_WR_OFFSET); + int path_offset = 0; + + if (!node) + return; + + group = node->group; + if (group->path_type == DATA) + path_offset = SZ_4; + + log_dev_err(itmon->dev, + "\n-----------------------------------------------------------\n" + " ITMON Report (%s)\n" + "-----------------------------------------------------------\n" + " Timeout Error Occurred : Client --> %s\n\n", + trans_type == TRANS_TYPE_READ ? "READ" : "WRITE", node->name); + log_dev_err(itmon->dev, + " TIMEOUT_BUFFER Information(NODE: %s)\n" + " > NUM| BLOCK| CLIENT|VALID|TIMEOUT| ID| PAYLOAD0| ADDRESS| PAYLOAD4|\n", + node->name); + + for (i = 0; i < num; i++) { + writel(i, node->regs + OFFSET_TMOUT_REG + REG_TMOUT_BUF_POINT_ADDR + rw_offset); + id = readl(node->regs + OFFSET_TMOUT_REG + REG_TMOUT_BUF_ID + rw_offset); + payload0 = readl(node->regs + OFFSET_TMOUT_REG + REG_TMOUT_BUF_PAYLOAD_0); + if (path_offset == SZ_4) + payload1 = readl(node->regs + OFFSET_TMOUT_REG + REG_TMOUT_BUF_PAYLOAD_1 + rw_offset); + payload2 = readl(node->regs + OFFSET_TMOUT_REG + + REG_TMOUT_BUF_PAYLOAD_2 + rw_offset); + payload3 = readl(node->regs + OFFSET_TMOUT_REG + + REG_TMOUT_BUF_PAYLOAD_3 + rw_offset); + payload4 = readl(node->regs + OFFSET_TMOUT_REG + + REG_TMOUT_BUF_PAYLOAD_4 + rw_offset); + + if (path_offset == SZ_4) { + timeout = (payload0 & (unsigned int)(GENMASK(7, 4))) >> 4; + user = payload1; + } else { + timeout = (payload0 & (unsigned int)(GENMASK(19, 16))) >> 16; + user = (payload0 & (unsigned int)(GENMASK(15, 8))) >> 8; + } + + addr = (((unsigned long)payload2 & GENMASK(15, 0)) << 32ULL); + addr |= payload3; + + info = readl(node->regs + OFFSET_TMOUT_REG + + REG_TMOUT_BUF_PAYLOAD_3 + rw_offset + path_offset); + + /* ID[5:0] 6bit : R-PATH */ + axid = id & GENMASK(5, 0); + /* PAYLOAD[0] : Valid or Not valid */ + valid = payload0 & BIT(0); + + port = itmon_get_rpathinfo(itmon, axid, node->name); + + port_name = NOT_AVAILABLE_STR; + client_name = NOT_AVAILABLE_STR; + if (port) { + port_name = port->port_name; + if (user) { + client = itmon_get_clientinfo(itmon, port_name, user); + if (client) + client_name = client->client_name; + } + } + + log_dev_err(itmon->dev, + " > %03d|%8s|%8s|%5u|%7x|%08x|%08x|%pa[p]|%08x\n", + i, port_name, client_name, valid, timeout, + id, payload0, &addr, payload4); + } + log_dev_err(itmon->dev, + "-----------------------------------------------------------\n"); +} + +static unsigned int power(unsigned int param, unsigned int num) +{ + if (num == 0) + return 1; + return param * (power(param, num - 1)); +} + +static void itmon_report_prot_chk_rawdata(struct itmon_dev *itmon, + struct itmon_nodeinfo *node) +{ + unsigned int dbg_mo_cnt, prot_chk_ctl, prot_chk_info, prot_chk_int_id; + + dbg_mo_cnt = __raw_readl(node->regs + OFFSET_PROT_CHK); + prot_chk_ctl = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_CTL); + prot_chk_info = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_INT); + prot_chk_int_id = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_INT_ID); + + /* Output Raw register information */ + log_dev_err(itmon->dev, + "\n-----------------------------------------------------------\n" + " Protocol Checker Raw Register Information (ITMON information)\n\n"); + log_dev_err(itmon->dev, + " > %s(%s, 0x%08X)\n" + " > REG(0x100~0x10C) : 0x%08X, 0x%08X, 0x%08X, 0x%08X\n", + node->name, itmon_node_string[node->type], + node->phy_regs, + dbg_mo_cnt, + prot_chk_ctl, + prot_chk_info, + prot_chk_int_id); + itmon_pattern_set(itmon, "from %s", node->name); +} + +static void itmon_report_rawdata(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + unsigned int trans_type) +{ + struct itmon_tracedata *data = &node->tracedata; + + /* Output Raw register information */ + log_dev_err(itmon->dev, + "Raw Register Information ----------------------------------\n" + " > %s(%s, 0x%08X)\n" + " > REG(0x08~0x18) : 0x%08X, 0x%08X, 0x%08X, 0x%08X\n" + " > REG(0x80) : 0x%08X\n" + " > REG(0x100~0x10C) : 0x%08X, 0x%08X, 0x%08X, 0x%08X\n", + node->name, itmon_node_string[node->type], + node->phy_regs + data->offset, + data->int_info, + data->ext_info_0, + data->ext_info_1, + data->ext_info_2, + data->ext_user, + data->dbg_mo_cnt, + data->prot_chk_ctl, + data->prot_chk_info, + data->prot_chk_int_id); +} + +static void itmon_report_traceinfo(struct itmon_dev *itmon, + struct itmon_traceinfo *info, + unsigned int trans_type) +{ + if (!info->dirty) + return; + + log_dev_err(itmon->dev, + "\n-----------------------------------------------------------\n" + " Transaction Information\n\n" + " > Client (User) : %s %s (0x%X)\n" + " > Target : %s\n" + " > Target Address : 0x%lX %s\n" + " > Type : %s\n" + " > Error code : %s\n\n", + info->port, info->client ? info->client : "", info->user, + info->dest ? info->dest : NOT_AVAILABLE_STR, + info->target_addr, + info->baaw_prot ? "(BAAW Remapped address)" : "", + trans_type == TRANS_TYPE_READ ? "READ" : "WRITE", + itmon_errcode[info->errcode]); + + itmon_pattern_set(itmon, "from %s %s to %s", + info->port, info->client ? info->client : "", + info->dest ? info->dest : NOT_AVAILABLE_STR); + + log_dev_err(itmon->dev, + "\n------------------------------------------------------------\n" + " > Size : %u bytes x %u burst => %u bytes\n" + " > Burst Type : %u (0:FIXED, 1:INCR, 2:WRAP)\n" + " > Level : %s\n" + " > Protection : %s\n" + " > Path Type : %s\n\n", + power(2, info->axsize), info->axlen + 1, + power(2, info->axsize) * (info->axlen + 1), + info->axburst, + info->axprot & BIT(0) ? "Privileged" : "Unprivileged", + info->axprot & BIT(1) ? "Non-secure" : "Secure", + itmon_pathtype[info->path_type]); +} + +static void itmon_report_pathinfo(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + struct itmon_traceinfo *info, + unsigned int trans_type) + +{ + struct itmon_tracedata *data = &node->tracedata; + + if (!info->path_dirty) { + log_dev_err(itmon->dev, + "\n-----------------------------------------------------------\n" + " ITMON Report (%s)\n" + "-----------------------------------------------------------\n" + " PATH Information\n\n", + trans_type == TRANS_TYPE_READ ? "READ" : "WRITE"); + info->path_dirty = true; + } + switch (node->type) { + case M_NODE: + log_dev_info(itmon->dev, + " > %14s, %8s(0x%08X)\n", + node->name, "M_NODE", + node->phy_regs + data->offset); + break; + case T_S_NODE: + log_dev_info(itmon->dev, + " > %14s, %8s(0x%08X)\n", + node->name, "T_S_NODE", + node->phy_regs + data->offset); + break; + case T_M_NODE: + log_dev_info(itmon->dev, + " > %14s, %8s(0x%08X)\n", + node->name, "T_M_NODE", + node->phy_regs + data->offset); + break; + case S_NODE: + log_dev_info(itmon->dev, + " > %14s, %8s(0x%08X)\n", + node->name, "S_NODE", + node->phy_regs + data->offset); + break; + } +} + +static int itmon_parse_cpuinfo(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + struct itmon_traceinfo *info, + unsigned int userbit) +{ + struct itmon_tracedata *find_data = NULL; + int cluster_num, core_num, i; + int ret = -1; + + for (i = 0; i < (int)ARRAY_SIZE(itmon_cpu_node_string); i++) { + if (!strcmp(node->name, itmon_cpu_node_string[i])) { + core_num = ((userbit & GENMASK(4, 2)) >> 2); + cluster_num = 0; + scnprintf(info->buf, SZ_32 - 1, "CPU%d Cluster%d", + core_num, cluster_num); + find_data = &node->tracedata; + find_data->ref_info = info; + info->port = info->buf; + set_bit(FROM_CPU, &info->from); + ret = 0; + break; + } + }; + + return ret; +} + +static void itmon_parse_traceinfo(struct itmon_dev *itmon, + struct itmon_nodeinfo *node, + unsigned int trans_type) +{ + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_tracedata *data = &node->tracedata; + struct itmon_traceinfo *new_info = NULL; + const struct itmon_clientinfo *client = NULL; + const struct itmon_rpathinfo *port = NULL; + struct itmon_nodeinfo *find_node = NULL; + struct itmon_tracedata *find_data = NULL; + struct itmon_nodegroup *group = node->group; + unsigned int errcode, axid; + unsigned int userbit; + int i; + + errcode = BIT_ERR_CODE(data->int_info); + if (!BIT_ERR_VALID(data->int_info)) + return; + + if (node->type == M_NODE && !(errcode == ERRCODE_DECERR || errcode == ERRCODE_UNSUPPORTED)) + return; + + new_info = kmalloc(sizeof(struct itmon_traceinfo), GFP_ATOMIC); + if (!new_info) + return; + + axid = (unsigned int)BIT_AXID(data->int_info); + if (group->path_type == DATA) + userbit = BIT_AXUSER(data->ext_user); + else + userbit = BIT_AXUSER_PERI(data->ext_info_2); + + new_info->port = NULL; + new_info->client = NULL; + new_info->user = userbit; + + switch (node->type) { + case S_NODE: + case T_S_NODE: + new_info->dest = node->name; + port = itmon_get_rpathinfo(itmon, axid, node->name); + list_for_each_entry(find_node, &pdata->datalist[trans_type], list) { + if (find_node->type != M_NODE) + continue; + + if (!itmon_parse_cpuinfo(itmon, find_node, new_info, userbit)) { + break; + } else if (port && !strcmp(find_node->name, port->port_name)) { + new_info->port = port->port_name; + client = itmon_get_clientinfo(itmon, new_info->port, userbit); + if (client) { + new_info->client = client->client_name; + if (!strcmp(client->client_name, "CPU")) + set_bit(FROM_CPU, &new_info->from); + } + + find_data = &find_node->tracedata; + find_data->ref_info = new_info; + break; + } + if (port) + continue; + + for (i = 0; i < (int)ARRAY_SIZE(rpathinfo); i++) { + if (strcmp(find_node->name, pdata->rpathinfo[i].port_name)) { + new_info->port = find_node->name; + new_info->client = " "; + find_data = &find_node->tracedata; + find_data->ref_info = new_info; + break; + } + } + } + if (!new_info->port) { + new_info->port = "Failed to parsing"; + new_info->client = "Refer to Raw Node information"; + } + break; + case M_NODE: + new_info->dest = "Refer to address"; + + if (!itmon_parse_cpuinfo(itmon, node, new_info, userbit)) + break; + + new_info->port = node->name; + client = itmon_get_clientinfo(itmon, node->name, userbit); + new_info->client = client ? client->client_name : " "; + break; + default: + log_dev_err(itmon->dev, + "Unknown Error - offset:%u\n", data->offset); + return; + } + + /* Last Information */ + new_info->path_type = group->path_type; + new_info->target_addr = + (((unsigned long)node->tracedata.ext_info_1 + & GENMASK(15, 0)) << 32ULL); + new_info->target_addr |= node->tracedata.ext_info_0; + new_info->errcode = errcode; + new_info->dirty = true; + new_info->axsize = BIT_AXSIZE(data->ext_info_1); + new_info->axlen = BIT_AXLEN(data->ext_info_1); + new_info->axburst = BIT_AXBURST(data->ext_info_2); + new_info->axprot = BIT_AXPROT(data->ext_info_2); + new_info->baaw_prot = false; + + for (i = 0; i < (int)ARRAY_SIZE(itmon_invalid_addr); i++) { + if (new_info->target_addr == itmon_invalid_addr[i]) { + new_info->baaw_prot = true; + break; + } + } + data->ref_info = new_info; + list_add(&new_info->list, &pdata->infolist[trans_type]); +} + +static void itmon_analyze_errnode(struct itmon_dev *itmon) +{ + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_traceinfo *info, *next_info; + struct itmon_tracedata *data; + struct itmon_nodeinfo *node, *next_node; + unsigned int trans_type; + int i; + + /* Parse */ + for (trans_type = 0; trans_type < TRANS_TYPE_NUM; trans_type++) { + list_for_each_entry(node, &pdata->datalist[trans_type], list) { + if (node->type == S_NODE || node->type == M_NODE || node->type == T_S_NODE) + itmon_parse_traceinfo(itmon, node, trans_type); + } + } + + /* Report */ + for (trans_type = 0; trans_type < TRANS_TYPE_NUM; trans_type++) { + list_for_each_entry(info, &pdata->infolist[trans_type], list) { + info->path_dirty = false; + list_for_each_entry(node, &pdata->datalist[trans_type], list) { + if (!node) + continue; + + data = &node->tracedata; + if (data->ref_info == info) + itmon_report_pathinfo(itmon, node, info, trans_type); + } + itmon_report_traceinfo(itmon, info, trans_type); + } + } + + /* Report Raw all tracedata and Clean-up tracedata and node */ + for (trans_type = 0; trans_type < TRANS_TYPE_NUM; trans_type++) { + for (i = M_NODE; i < NODE_TYPE; i++) { + list_for_each_entry_safe(node, next_node, + &pdata->datalist[trans_type], list) { + if (i == node->type) { + itmon_report_rawdata(itmon, node, trans_type); + list_del(&node->list); + kfree(node); + } + } + } + } + + /* Rest works and Clean-up traceinfo */ + for (trans_type = 0; trans_type < TRANS_TYPE_NUM; trans_type++) { + list_for_each_entry_safe(info, next_info, &pdata->infolist[trans_type], list) { + itmon_post_handler_to_notifier(itmon, info, trans_type); + itmon_post_handler_by_dest(itmon, info, trans_type); + itmon_post_handler_by_client(itmon, info, trans_type); + list_del(&info->list); + kfree(info); + } + } +} + +static void itmon_collect_errnode(struct itmon_dev *itmon, + struct itmon_nodegroup *group, + struct itmon_nodeinfo *node, + unsigned int offset) +{ + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_nodeinfo *new_node = NULL; + unsigned int int_info, info0, info1, info2, user; + unsigned int prot_chk_ctl, prot_chk_info, prot_chk_int_id, dbg_mo_cnt; + bool read = TRANS_TYPE_WRITE; + bool req = false; + + int_info = __raw_readl(node->regs + offset + REG_INT_INFO); + info0 = __raw_readl(node->regs + offset + REG_EXT_INFO_0); + info1 = __raw_readl(node->regs + offset + REG_EXT_INFO_1); + info2 = __raw_readl(node->regs + offset + REG_EXT_INFO_2); + if (group->path_type == DATA) + user = __raw_readl(node->regs + offset + REG_EXT_USER); + + dbg_mo_cnt = __raw_readl(node->regs + OFFSET_PROT_CHK); + prot_chk_ctl = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_CTL); + prot_chk_info = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_INT); + prot_chk_int_id = __raw_readl(node->regs + + OFFSET_PROT_CHK + REG_PROT_CHK_INT_ID); + switch (offset) { + case OFFSET_REQ_R: + read = TRANS_TYPE_READ; + /* fall down */ + case OFFSET_REQ_W: + req = true; + /* Only S-Node is able to make log to registers */ + break; + case OFFSET_RESP_R: + read = TRANS_TYPE_READ; + /* fall down */ + case OFFSET_RESP_W: + req = false; + /* Only NOT S-Node is able to make log to registers */ + break; + default: + log_dev_err(itmon->dev, "Unknown Error - node:%s offset:%u\n", + node->name, offset); + break; + } + + new_node = kmalloc(sizeof(struct itmon_nodeinfo), GFP_ATOMIC); + + if (!new_node) { + log_dev_err(itmon->dev, "failed to kmalloc for %s node %x offset\n", + node->name, offset); + return; + } + + /* Fill detected node information to tracedata's list */ + memcpy(new_node, node, sizeof(*new_node)); + new_node->tracedata.int_info = int_info; + new_node->tracedata.ext_info_0 = info0; + new_node->tracedata.ext_info_1 = info1; + new_node->tracedata.ext_info_2 = info2; + new_node->tracedata.ext_user = user; + new_node->tracedata.dbg_mo_cnt = dbg_mo_cnt; + new_node->tracedata.prot_chk_ctl = prot_chk_ctl; + new_node->tracedata.prot_chk_info = prot_chk_info; + new_node->tracedata.prot_chk_int_id = prot_chk_int_id; + + new_node->tracedata.offset = offset; + new_node->tracedata.read = read; + new_node->tracedata.ref_info = NULL; + new_node->group = group; + node->tracedata.logging = BIT_ERR_VALID(int_info); + + list_add(&new_node->list, &pdata->datalist[read]); +} + +static int __itmon_search_node(struct itmon_dev *itmon, + struct itmon_nodegroup *group, + bool clear) +{ + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_nodeinfo *node = NULL; + unsigned int val, offset, freeze; + unsigned long vec, bit = 0; + int i, ret = 0; + + if (group->phy_regs) { + if (group->ex_table) + vec = (unsigned long)__raw_readq(group->regs); + else + vec = (unsigned long)__raw_readl(group->regs); + } else { + vec = GENMASK(group->nodesize, 0); + } + + if (!vec) + goto exit; + + node = group->nodeinfo; + + for_each_set_bit(bit, &vec, group->nodesize) { + /* exist array */ + for (i = 0; i < OFFSET_NUM; i++) { + offset = i * OFFSET_ERR_REPT; + /* Check Request information */ + val = __raw_readl(node[bit].regs + offset + REG_INT_INFO); + if (BIT_ERR_OCCURRED(val)) { + /* This node occurs the error */ + itmon_collect_errnode(itmon, group, &node[bit], offset); + if (clear) + __raw_writel(1, node[bit].regs + + offset + REG_INT_CLR); + ret = true; + } + } + /* Check H/W assertion */ + if (node[bit].prot_chk_enabled) { + val = __raw_readl(node[bit].regs + OFFSET_PROT_CHK + + REG_PROT_CHK_INT); + /* + * if timeout_freeze is enable, + * PROT_CHK interrupt is able to assert without any information + */ + if (BIT_PROT_CHK_ERR_OCCURRED(val) && (val & GENMASK(8, 1))) { + itmon_report_prot_chk_rawdata(itmon, &node[bit]); + pdata->policy[FATAL].error = true; + ret = true; + } + } + /* Check freeze enable node */ + if (node[bit].type == S_NODE && node[bit].tmout_frz_enabled) { + val = __raw_readl(node[bit].regs + OFFSET_TMOUT_REG + + REG_TMOUT_FRZ_STATUS); + freeze = val & (unsigned int)GENMASK(1, 0); + if (freeze) { + if (freeze & BIT(0)) + itmon_report_timeout(itmon, &node[bit], TRANS_TYPE_WRITE); + if (freeze & BIT(1)) + itmon_report_timeout(itmon, &node[bit], TRANS_TYPE_READ); + pdata->policy[FATAL].error = true; + ret = true; + } + } + } +exit: + return ret; +} + +static int itmon_search_node(struct itmon_dev *itmon, + struct itmon_nodegroup *group, + bool clear) +{ + int i, ret = 0; + unsigned long flags; + + spin_lock_irqsave(&itmon->ctrl_lock, flags); + + if (group) { + ret = __itmon_search_node(itmon, group, clear); + } else { + /* Processing all group & nodes */ + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + group = &nodegroup[i]; + ret |= __itmon_search_node(itmon, group, clear); + } + } + itmon_analyze_errnode(itmon); + + spin_unlock_irqrestore(&itmon->ctrl_lock, flags); + return ret; +} + +static void itmon_do_dpm_policy(struct itmon_dev *itmon) +{ + struct itmon_platdata *pdata = itmon->pdata; + int i; + + /* This will stop recursive panic when dpm action is panic */ + pdata->in_do_policy = true; + + + for (i = 0; i < TYPE_MAX; i++) { + char buf[SZ_64]; + + if (!pdata->policy[i].error) + continue; + + scnprintf(buf, sizeof(buf), "itmon triggering %s %s", + pdata->policy[i].name, itmon->itmon_pattern); + dbg_snapshot_do_dpm_policy(pdata->policy[i].policy, buf); + pdata->policy[i].error = false; + } + + pdata->in_do_policy = false; +} + +static irqreturn_t itmon_irq_handler(int irq, void *data) +{ + struct itmon_dev *itmon = (struct itmon_dev *)data; + struct itmon_platdata *pdata = itmon->pdata; + struct itmon_nodegroup *group = NULL; + bool ret; + int i; + +#if IS_ENABLED(CONFIG_EXYNOS_CPUPM) + system_is_in_itmon = true; +#endif + + itmon_pattern_reset(itmon); + dbg_snapshot_itmon_irq_received(); + + /* Search itmon group */ + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + group = &pdata->nodegroup[i]; + log_dev_info(itmon->dev, + "%d irq, %s group, 0x%x\n", + irq, group->name, + group->phy_regs == 0 ? 0 : __raw_readl(group->regs)); + } + + ret = itmon_search_node(itmon, NULL, true); + if (!ret) { + log_dev_info(itmon->dev, "No errors found\n"); + } else { + log_dev_err(itmon->dev, "\nError detected: err_cnt_by_cpu:%u\n", + pdata->err_cnt_by_cpu); + + /* This will stop recursive panic when dpm action is panic */ + if (!pdata->in_do_policy) + itmon_do_dpm_policy(itmon); + } + +#if IS_ENABLED(CONFIG_EXYNOS_CPUPM) + system_is_in_itmon = false; +#endif + + return IRQ_HANDLED; +} + +void itmon_notifier_chain_register(struct notifier_block *block) +{ + atomic_notifier_chain_register(&itmon_notifier_list, block); +} +EXPORT_SYMBOL(itmon_notifier_chain_register); + +void itmon_notifier_chain_unregister(struct notifier_block *block) +{ + atomic_notifier_chain_unregister(&itmon_notifier_list, block); +} +EXPORT_SYMBOL(itmon_notifier_chain_unregister); + +static struct bus_type itmon_subsys = { + .name = "itmon", + .dev_name = "itmon", +}; + +static ssize_t itmon_timeout_fix_val_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "set timeout val: 0x%x\n", + g_itmon->pdata->sysfs_tmout_val); +} + +static ssize_t itmon_timeout_fix_val_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned long val = 0; + struct itmon_platdata *pdata = g_itmon->pdata; + int ret; + + ret = kstrtoul(buf, 16, &val); + if (!ret) { + if (val > 0 && val <= 0xFFFFF) + pdata->sysfs_tmout_val = val; + } else { + log_dev_err(g_itmon->dev, "kstrtoul return value is %d\n", ret); + } + + return count; +} + +static ssize_t itmon_timeout_val_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + unsigned long i, offset; + ssize_t n = 0; + unsigned long vec, bit = 0; + struct itmon_nodegroup *group = NULL; + struct itmon_nodeinfo *node; + + /* Processing all group & nodes */ + offset = OFFSET_TMOUT_REG; + for (i = 0; i < ARRAY_SIZE(nodegroup); i++) { + group = &nodegroup[i]; + node = group->nodeinfo; + vec = GENMASK(group->nodesize, 0); + bit = 0; + for_each_set_bit(bit, &vec, group->nodesize) { + if (node[bit].type == S_NODE) { + n += scnprintf(buf + n, PAGE_SIZE - n, + "%-12s : 0x%08X, timeout : 0x%x\n", + node[bit].name, node[bit].phy_regs, + __raw_readl(node[bit].regs + + offset + REG_TMOUT_INIT_VAL)); + } + } + } + return n; +} + +static ssize_t itmon_timeout_freeze_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + unsigned long i, offset; + ssize_t n = 0; + unsigned long vec, bit = 0; + struct itmon_nodegroup *group = NULL; + struct itmon_nodeinfo *node; + + /* Processing all group & nodes */ + offset = OFFSET_TMOUT_REG; + for (i = 0; i < ARRAY_SIZE(nodegroup); i++) { + group = &nodegroup[i]; + node = group->nodeinfo; + vec = GENMASK(group->nodesize, 0); + bit = 0; + for_each_set_bit(bit, &vec, group->nodesize) { + if (node[bit].type == S_NODE) { + n += scnprintf(buf + n, PAGE_SIZE - n, + "%-12s : 0x%08X, timeout_freeze : %x\n", + node[bit].name, node[bit].phy_regs, + __raw_readl(node[bit].regs + + offset + REG_TMOUT_FRZ_EN)); + } + } + } + return n; +} + +static ssize_t itmon_timeout_val_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + char *name; + unsigned int offset, i; + unsigned long vec, bit = 0; + struct itmon_nodegroup *group = NULL; + struct itmon_nodeinfo *node; + struct itmon_platdata *pdata = g_itmon->pdata; + + name = (char *)kstrndup(buf, count, GFP_KERNEL); + if (!name) + return count; + + offset = OFFSET_TMOUT_REG; + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + group = &nodegroup[i]; + node = group->nodeinfo; + vec = GENMASK(group->nodesize, 0); + bit = 0; + for_each_set_bit(bit, &vec, group->nodesize) { + if (node[bit].type == S_NODE && + !strcmp(name, node[bit].name)) { + __raw_writel(pdata->sysfs_tmout_val, + node[bit].regs + offset + + REG_TMOUT_INIT_VAL); + node[bit].time_val = pdata->sysfs_tmout_val; + } + } + } + kfree(name); + return count; +} + +static ssize_t itmon_timeout_freeze_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + char *name; + unsigned int val, offset, i; + unsigned long vec, bit = 0; + struct itmon_nodegroup *group = NULL; + struct itmon_nodeinfo *node; + + name = (char *)kstrndup(buf, count, GFP_KERNEL); + if (!name) + return count; + + offset = OFFSET_TMOUT_REG; + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + group = &nodegroup[i]; + node = group->nodeinfo; + vec = GENMASK(group->nodesize, 0); + bit = 0; + for_each_set_bit(bit, &vec, group->nodesize) { + if (node[bit].type == S_NODE && + !strcmp(name, node[bit].name)) { + val = __raw_readl(node[bit].regs + + offset + REG_TMOUT_FRZ_EN); + val = !val; + __raw_writel(val, node[bit].regs + + offset + REG_TMOUT_FRZ_EN); + node[bit].tmout_frz_enabled = val; + } + } + } + kfree(name); + return count; +} + +static struct kobj_attribute itmon_timeout_fix_attr = + __ATTR(set_val, 0644, itmon_timeout_fix_val_show, + itmon_timeout_fix_val_store); +static struct kobj_attribute itmon_timeout_val_attr = + __ATTR(timeout_val, 0644, itmon_timeout_val_show, + itmon_timeout_val_store); +static struct kobj_attribute itmon_timeout_freeze_attr = + __ATTR(timeout_freeze, 0644, itmon_timeout_freeze_show, + itmon_timeout_freeze_store); + +static struct attribute *itmon_sysfs_attrs[] = { + &itmon_timeout_fix_attr.attr, + &itmon_timeout_val_attr.attr, + &itmon_timeout_freeze_attr.attr, + NULL, +}; + +static struct attribute_group itmon_sysfs_group = { + .attrs = itmon_sysfs_attrs, +}; + +static const struct attribute_group *itmon_sysfs_groups[] = { + &itmon_sysfs_group, + NULL, +}; + +static int itmon_logging_panic_handler(struct notifier_block *nb, + unsigned long l, void *buf) +{ + struct itmon_panic_block *itmon_panic = (struct itmon_panic_block *)nb; + struct itmon_dev *itmon = itmon_panic->pdev; + struct itmon_platdata *pdata = itmon->pdata; + int ret; + + if (!IS_ERR_OR_NULL(itmon)) { + /* Check error has been logged */ + ret = itmon_search_node(itmon, NULL, false); + if (!ret) { + log_dev_info(itmon->dev, "No errors found\n"); + } else { + log_dev_err(itmon->dev, + "Error detected, err_cnt_by_cpu:%u\n", + pdata->err_cnt_by_cpu); + + itmon_do_dpm_policy(itmon); + } + } + return 0; +} + +static void itmon_parse_dt(struct itmon_dev *itmon) +{ + struct device_node *np = itmon->dev->of_node; + struct itmon_platdata *pdata = itmon->pdata; + unsigned int val; + int i; + + if (!of_property_read_u32(np, "panic_count", &val)) + pdata->panic_threshold = val; + else + pdata->panic_threshold = PANIC_THRESHOLD; + + log_dev_info(itmon->dev, "panic threshold: %d\n", pdata->panic_threshold); + for (i = 0; i < TYPE_MAX; i++) { + if (!of_property_read_u32(np, pdata->policy[i].name, &val)) + pdata->policy[i].policy = val; + + log_dev_info(itmon->dev, "policy: %s: [%d]\n", + pdata->policy[i].name, pdata->policy[i].policy); + } +} + + +static int itmon_probe(struct platform_device *pdev) +{ + struct itmon_dev *itmon; + struct itmon_panic_block *itmon_panic = NULL; + struct itmon_platdata *pdata; + struct itmon_nodeinfo *node; + unsigned int irq_option = 0, irq; + char *dev_name; + int ret, i, j; + + itmon = devm_kzalloc(&pdev->dev, + sizeof(struct itmon_dev), GFP_KERNEL); + if (!itmon) + return -ENOMEM; + + itmon->dev = &pdev->dev; + + spin_lock_init(&itmon->ctrl_lock); + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct itmon_platdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + pdata->cp_crash_in_progress = false; + for (i = 0; i < TRANS_TYPE_NUM; i++) { + INIT_LIST_HEAD(&pdata->datalist[i]); + INIT_LIST_HEAD(&pdata->infolist[i]); + } + + itmon->pdata = pdata; + itmon->pdata->clientinfo = clientinfo; + itmon->pdata->rpathinfo = rpathinfo; + itmon->pdata->nodegroup = nodegroup; + itmon->pdata->policy = err_policy; + + itmon_parse_dt(itmon); + + for (i = 0; i < (int)ARRAY_SIZE(nodegroup); i++) { + dev_name = nodegroup[i].name; + node = nodegroup[i].nodeinfo; + + if (nodegroup[i].phy_regs) { + nodegroup[i].regs = devm_ioremap(&pdev->dev, nodegroup[i].phy_regs, SZ_16K); + if (nodegroup[i].regs == NULL) { + log_dev_err(&pdev->dev, + "failed to claim register region - %s\n", + dev_name); + return -ENOENT; + } + } + irq = irq_of_parse_and_map(pdev->dev.of_node, i); + nodegroup[i].irq = irq; + + ret = devm_request_irq(&pdev->dev, irq, + itmon_irq_handler, irq_option, dev_name, itmon); + if (ret == 0) { + log_dev_info(&pdev->dev, + "success to register request irq%u - %s\n", + irq, dev_name); + } else { + log_dev_err(&pdev->dev, "failed to request irq - %s\n", + dev_name); + return -ENOENT; + } + + for (j = 0; j < nodegroup[i].nodesize; j++) { + node[j].regs = devm_ioremap(&pdev->dev, node[j].phy_regs, SZ_16K); + if (node[j].regs == NULL) { + log_dev_err(&pdev->dev, + "failed to claim register region - %s\n", + dev_name); + return -ENOENT; + } + } + } + + itmon_panic = devm_kzalloc(&pdev->dev, sizeof(struct itmon_panic_block), + GFP_KERNEL); + if (itmon_panic) { + itmon_panic->nb_panic_block.notifier_call = itmon_logging_panic_handler; + itmon_panic->pdev = itmon; + atomic_notifier_chain_register(&panic_notifier_list, + &itmon_panic->nb_panic_block); + } + + platform_set_drvdata(pdev, itmon); + itmon_init(itmon, true); + itmon_pattern_reset(itmon); + g_itmon = itmon; + + ret = subsys_system_register(&itmon_subsys, itmon_sysfs_groups); + if (ret) + log_dev_err(g_itmon->dev, "fail to register itmon subsys\n"); + + pdata->probed = true; + log_dev_info(&pdev->dev, "success to probe gs201 ITMON driver\n"); + + return 0; +} + +static int itmon_remove(struct platform_device *pdev) +{ + platform_set_drvdata(pdev, NULL); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int itmon_suspend(struct device *dev) +{ + return 0; +} + +static int itmon_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct itmon_dev *itmon = platform_get_drvdata(pdev); + struct itmon_platdata *pdata = itmon->pdata; + + /* re-enable ITMON if cp-crash progress is not starting */ + if (!pdata->cp_crash_in_progress) + itmon_init(itmon, true); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(itmon_pm_ops, itmon_suspend, itmon_resume); +#define ITMON_PM (&itmon_pm_ops) +#else +#define ITMON_PM NULL +#endif + +static const struct of_device_id itmon_dt_match[] = { + {.compatible = "google,gs201-itmon", }, + {}, +}; +MODULE_DEVICE_TABLE(of, itmon_dt_match); + +static struct platform_driver gs201_itmon_driver = { + .probe = itmon_probe, + .remove = itmon_remove, + .driver = { + .name = "gs201-itmon", + .of_match_table = itmon_dt_match, + .pm = ITMON_PM, + }, +}; +module_platform_driver(gs201_itmon_driver); + +MODULE_DESCRIPTION("Google GS201 ITMON DRIVER"); +MODULE_AUTHOR("Hosung Kim #include #include +#include #include +void __noreturn __cold nvhe_hyp_panic_handler(u64 esr, u64 spsr, + u64 elr_virt, u64 elr_phys, + u64 par, uintptr_t vcpu, + u64 far, u64 hpfar); + /* * Utility functions */ @@ -146,12 +152,10 @@ static void simulate_warn(char *arg) static void simulate_null(char *arg) { - char *pointer = NULL; - pr_crit("called!\n"); /* Intentional null pointer dereference */ - *pointer = 'a'; + writeb('a', NULL); /* Should not reach here */ pr_crit("failed!"); @@ -231,7 +235,7 @@ static void simulate_low_memory(char *arg) static void simulate_softlockup(char *arg) { - pr_crit("called!\n"); + pr_crit("called on CPU %u!\n", smp_processor_id()); local_irq_disable(); preempt_disable(); @@ -444,7 +448,9 @@ void debug_trigger_register(struct debug_trigger *soc_trigger, char *arch_name) { pr_info("DEBUG TEST: [%s] test triggers are registered!", arch_name); soc_test_trigger.hard_lockup = soc_trigger->hard_lockup; +#if IS_ENABLED(CONFIG_SOC_GS101) soc_test_trigger.cold_reset = soc_trigger->cold_reset; +#endif soc_test_trigger.watchdog_emergency_reset = soc_trigger->watchdog_emergency_reset; soc_test_trigger.halt = soc_trigger->halt; @@ -471,6 +477,7 @@ static void simulate_hardlockup(char *arg) } +#if IS_ENABLED(CONFIG_SOC_GS101) static void simulate_cold_reset(char *arg) { pr_crit("called!\n"); @@ -484,6 +491,7 @@ static void simulate_cold_reset(char *arg) /* Should not reach here */ pr_crit("failed!\n"); } +#endif static void simulate_watchdog_emergency_reset(char *arg) { @@ -534,6 +542,50 @@ static void simulate_scandump(char *arg) (*soc_test_trigger.scandump)(arg); } + +static int suspend_valid(suspend_state_t state) +{ + return 1; +} + +static int suspend_begin(suspend_state_t state) +{ + pr_crit("called!\n"); + schedule_timeout_interruptible(msecs_to_jiffies(9000000)); + return -EINVAL; +} + +static int suspend_enter(suspend_state_t state) +{ + return -EINVAL; +} + +static const struct platform_suspend_ops suspend_ops = { + .valid = suspend_valid, + .begin = suspend_begin, + .enter = suspend_enter, +}; + +static void simulate_suspend_hang(char *arg) +{ + suspend_set_ops(&suspend_ops); +} + +static void simulate_hyp_panic(char *arg) +{ + u64 esr, spsr; + + pr_crit("called!\n"); + + /* Fake the EL2 exception with the following values + * exception class: 0x3F, instruction specific syndrome : 0x1ffffff + */ + spsr = PSR_MODE_EL2t; + esr = (ESR_ELx_EC_MAX << ESR_ELx_EC_SHIFT) | ESR_ELx_ISS_MASK; + + nvhe_hyp_panic_handler(esr, spsr, -1, 0, 0, 0, 0, 0); +} + /* * Error trigger definitions */ @@ -567,11 +619,15 @@ static const struct force_error_item force_error_vector[] = { { "pcabort", &simulate_pc_abort }, { "spabort", &simulate_sp_abort }, { "jumpzero", &simulate_jump_zero }, +#if IS_ENABLED(CONFIG_SOC_GS101) { "cold_reset", &simulate_cold_reset }, +#endif { "emerg_reset", &simulate_watchdog_emergency_reset }, { "halt", &simulate_halt }, { "arraydump", &simulate_arraydump }, { "scandump", &simulate_scandump }, + { "suspend_hang", &simulate_suspend_hang }, + { "hyp_panic", &simulate_hyp_panic }, }; static void parse_and_trigger(const char *buf) diff --git a/drivers/soc/google/eh/eh_internal.h b/drivers/soc/google/eh/eh_internal.h index 3c8f418fb428..7d64a3fe5f2d 100644 --- a/drivers/soc/google/eh/eh_internal.h +++ b/drivers/soc/google/eh/eh_internal.h @@ -91,6 +91,9 @@ struct eh_device { /* EH clock */ struct clk *clk; + /* EH S2MPU device */ + struct device *s2mpu; + int error_irq; /* diff --git a/drivers/soc/google/eh/eh_main.c b/drivers/soc/google/eh/eh_main.c index f66b477bebe3..1030b7556803 100644 --- a/drivers/soc/google/eh/eh_main.c +++ b/drivers/soc/google/eh/eh_main.c @@ -57,6 +57,9 @@ #include #include #include +#include + +#include /* These are the possible values for the status field from the specification */ enum eh_cdesc_status { @@ -108,9 +111,9 @@ static LIST_HEAD(eh_dev_list); static DEFINE_SPINLOCK(eh_dev_list_lock); static DECLARE_WAIT_QUEUE_HEAD(eh_compress_wait); -static unsigned int eh_default_fifo_size = 256; +static unsigned int eh_default_fifo_size = 512; -#define EH_SW_FIFO_SIZE (1 << 14) +#define EH_SW_FIFO_SIZE (1 << 16) #define first_to_eh_request(head) (list_entry((head)->prev, \ struct eh_request, list)) @@ -490,6 +493,7 @@ static void flush_sw_fifo(struct eh_device *eh_dev) list_splice(&list, &fifo->head); fifo->count -= nr_processed; spin_unlock(&fifo->lock); + clear_eh_congested(); } static void refill_hw_fifo(struct eh_device *eh_dev) @@ -508,6 +512,7 @@ static void refill_hw_fifo(struct eh_device *eh_dev) } } spin_unlock(&fifo->lock); + clear_eh_congested(); } static irqreturn_t eh_error_irq(int irq, void *data) @@ -622,7 +627,6 @@ static int eh_process_completed_descriptor(struct eh_device *eh_dev, /* set the descriptor back to IDLE */ desc->status = EH_CDESC_IDLE; atomic_dec(&eh_dev->nr_request); - clear_eh_congested(); update_fifo_complete_index(eh_dev); return ret; @@ -677,7 +681,12 @@ static int eh_comp_thread(void *data) struct eh_device *eh_dev = data; DEFINE_WAIT(wait); int nr_processed = 0; + struct sched_attr attr = { + .sched_policy = SCHED_NORMAL, + .sched_nice = -10, + }; + WARN_ON_ONCE(sched_setattr_nocheck(current, &attr) != 0); current->flags |= PF_MEMALLOC; while (!kthread_should_stop()) { @@ -989,7 +998,7 @@ static ssize_t nr_stall_show(struct kobject *kobj, struct kobj_attribute *attr, { struct eh_device *eh_dev = container_of(kobj, struct eh_device, kobj); - return sysfs_emit(buf, "%l\n", atomic64_read(&eh_dev->nr_stall)); + return sysfs_emit(buf, "%llu\n", atomic64_read(&eh_dev->nr_stall)); } EH_ATTR_RO(nr_stall); @@ -1242,6 +1251,18 @@ void eh_destroy(struct eh_device *eh_dev) } EXPORT_SYMBOL(eh_destroy); +static int eh_s2mpu_suspend(struct eh_device *eh_dev) +{ + return (IS_ENABLED(CONFIG_PKVM_S2MPU) && eh_dev->s2mpu) + ? pkvm_s2mpu_suspend(eh_dev->s2mpu) : 0; +} + +static int eh_s2mpu_resume(struct eh_device *eh_dev) +{ + return (IS_ENABLED(CONFIG_PKVM_S2MPU) && eh_dev->s2mpu) + ? pkvm_s2mpu_resume(eh_dev->s2mpu) : 0; +} + #ifdef CONFIG_OF static int eh_of_probe(struct platform_device *pdev) { @@ -1251,8 +1272,21 @@ static int eh_of_probe(struct platform_device *pdev) int error_irq = 0; unsigned short quirks = 0; struct clk *clk; + struct device *s2mpu = NULL; int sw_fifo_size = EH_SW_FIFO_SIZE; + if (IS_ENABLED(CONFIG_PKVM_S2MPU)) { + s2mpu = pkvm_s2mpu_of_parse(&pdev->dev); + if (IS_ERR(s2mpu)) { + dev_err(&pdev->dev, "pkvm_s2mpu_of_parse returned: %ld\n", + PTR_ERR(s2mpu)); + return PTR_ERR(s2mpu); + } + if (s2mpu && !pkvm_s2mpu_ready(s2mpu)) { + return -EPROBE_DEFER; + } + } + pr_info("starting probing\n"); pm_runtime_enable(&pdev->dev); @@ -1294,6 +1328,11 @@ static int eh_of_probe(struct platform_device *pdev) if (ret) goto free_ehdev; + eh_dev->s2mpu = s2mpu; + ret = eh_s2mpu_resume(eh_dev); + if (ret) + dev_err(&pdev->dev, "could not resume s2mpu: %d", ret); + eh_dev->clk = clk; platform_set_drvdata(pdev, eh_dev); @@ -1332,6 +1371,7 @@ static int eh_suspend(struct device *dev) { unsigned long data; struct eh_device *eh_dev = dev_get_drvdata(dev); + int ret; /* check pending work */ if (atomic_read(&eh_dev->nr_request) > 0) { @@ -1351,6 +1391,11 @@ static int eh_suspend(struct device *dev) /* disable EH clock */ clk_disable_unprepare(eh_dev->clk); + + ret = eh_s2mpu_suspend(eh_dev); + if (ret) + dev_err(dev, "could not suspend s2mpu: %d", ret); + dev_dbg(dev, "EH suspended\n"); return 0; @@ -1359,6 +1404,11 @@ static int eh_suspend(struct device *dev) static int eh_resume(struct device *dev) { struct eh_device *eh_dev = dev_get_drvdata(dev); + int ret; + + ret = eh_s2mpu_resume(eh_dev); + if (ret) + dev_err(dev, "could not resume s2mpu: %d", ret); /* re-enable EH clock */ clk_prepare_enable(eh_dev->clk); diff --git a/drivers/soc/google/exynos-bcm_dbg.c b/drivers/soc/google/exynos-bcm_dbg.c index 554b90602c83..ffd2e0cf47d6 100644 --- a/drivers/soc/google/exynos-bcm_dbg.c +++ b/drivers/soc/google/exynos-bcm_dbg.c @@ -1739,57 +1739,6 @@ static ssize_t show_event_ctrl(struct file *fp, char __user *ubuf, size_t size, return ret; } -static ssize_t show_event_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - struct exynos_bcm_dbg_data *data = fp->private_data; - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_event_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= event_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat event_ctrl\n" - "bcm[ip_index]: def(define_index), [ev0], [ev1], [ev2], [ev3], [ev4], [ev5], [ev6], [ev7]\n"); - - /* help store_event_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= event_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [ip_range] [ip_index] [define_index] " - "[ev0] [ev1] [ev2] [ev3] [ev4] [ev5] [ev6] [ev7] > " - "event_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nip_range: BCM_EACH(%d), BCM_ALL(%d)\n", - BCM_EACH, BCM_ALL); - count += scnprintf(buf + count, size - count, - "ip_index: number of bcm ip (0 ~ %u)\n" - " (if ip_range is all, set to 0)\n", - data->bcm_ip_nr - 1); - count += scnprintf(buf + count, size - count, - "define_index: index of pre-defined event (0 ~ %u)\n" - " 0 means no pre-defined event\n", - data->define_event_max - 1); - count += scnprintf(buf + count, size - count, - "evX: event value of counter (if define_index is not 0, set to 0\n" - " event value should be in hex\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_event_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { struct exynos_bcm_dbg_data *data = fp->private_data; @@ -1966,64 +1915,6 @@ static ssize_t show_filter_id_active(struct file *fp, char __user *ubuf, size_t return ret; } -static ssize_t show_filter_id_ctrl_help(struct file *fp, char __user *ubuf, size_t size, - loff_t *ppos) -{ - struct exynos_bcm_dbg_data *data = fp->private_data; - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_filter_id_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= filter_id_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat filter_id_ctrl\n" - "bcm[ip_index]: [mask], [value]\n"); - - /* help store_filter_id_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= filter_id_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [ip_range] [ip_index] [define_index] [mask] " - "[value] [ev0] [ev1] [ev2] [ev3] [ev4] [ev5] [ev6] " - "[ev7] > filter_id_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nip_range: BCM_EACH(%d), BCM_ALL(%d)\n", - BCM_EACH, BCM_ALL); - count += scnprintf(buf + count, size - count, - "ip_index: number of bcm ip (0 ~ %u)\n" - " (if ip_range is all, set to 0)\n", - data->bcm_ip_nr - 1); - count += scnprintf(buf + count, size - count, - "define_index: index of pre-defined event (0 ~ %u)\n" - " 0 means no pre-defined event\n", - data->define_event_max - 1); - count += scnprintf(buf + count, size - count, - "mask: masking for filter id (if define_index is not 0, set to 0)\n" - " mask value should be in hex\n"); - count += scnprintf(buf + count, size - count, - "value: value of filter id (if define_index is not 0, set to 0)\n" - " value should be in hex\n"); - count += scnprintf(buf + count, size - count, - "evX: event counter alloc for filter id (if define_index is not 0, set to 0)\n" - " value should be 0 or 1\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_filter_id_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { @@ -2212,78 +2103,6 @@ static ssize_t show_filter_others_active(struct file *fp, char __user *ubuf, siz return ret; } -static ssize_t show_filter_others_ctrl_help(struct file *fp, char __user *ubuf, size_t size, - loff_t *ppos) -{ - struct exynos_bcm_dbg_data *data = fp->private_data; - char *buf; - ssize_t ret; - ssize_t count = 0; - int othr_cnt; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_filter_others_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= filter_others_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat filter_other_ctrl\n" - "bcm[ip_index]: [type0], [mask0], [value0], [type1], [mask1], [value1]\n"); - - /* help store_filter_others_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= filter_others_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [ip_range] [ip_index] [define_index] " - "[type0] [mask0] [value0] [type1] [mask1] [value1] " - "[ev0] [ev1] [ev2] [ev3] [ev4] [ev5] [ev6] [ev7] > " - "filter_others_ctrl\n"); - count += scnprintf(buf + count, size - count, - " ip_range: BCM_EACH(%d), BCM_ALL(%d)\n", - BCM_EACH, BCM_ALL); - count += scnprintf(buf + count, size - count, - " ip_index: number of bcm ip (0 ~ %u)\n" - " (if ip_range is all, set to 0)\n", - data->bcm_ip_nr - 1); - count += scnprintf(buf + count, size - count, - " define_index: index of pre-defined event (0 ~ %u)\n" - " 0 means no pre-defined event\n", - data->define_event_max - 1); - for (othr_cnt = 0; othr_cnt < BCM_EVT_FLT_OTHR_MAX; othr_cnt++) { - count += scnprintf(buf + count, size - count, - " type%d: type%d for filter others" - " (if define_index is not 0, set to 0)\n" - " type%d value should be in hex\n", - othr_cnt, othr_cnt, othr_cnt); - count += scnprintf(buf + count, size - count, - " mask%d: mask%d for filter others" - " (if define_index is not 0, set to 0)\n" - " mask%d value should be in hex\n", - othr_cnt, othr_cnt, othr_cnt); - count += scnprintf(buf + count, size - count, - " value%d: value%d of filter others" - " (if define_index is not 0, set to 0)\n" - " value%d should be in hex\n", - othr_cnt, othr_cnt, othr_cnt); - } - count += scnprintf(buf + count, size - count, - " evX: event counter alloc for filter others" - " (if define_index is not 0, set to 0)\n" - " value should be 0 or 1\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_filter_others_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { @@ -2481,64 +2300,6 @@ static ssize_t show_sample_id_active(struct file *fp, char __user *ubuf, size_t return ret; } -static ssize_t show_sample_id_ctrl_help(struct file *fp, char __user *ubuf, size_t size, - loff_t *ppos) -{ - struct exynos_bcm_dbg_data *data = fp->private_data; - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_sample_id_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= sample_id_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat sample_id_ctrl\n" - "bcm[ip_index]: [mask], [value]\n"); - - /* help store_sample_id_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= sample_id_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [ip_range] [ip_index] [define_index] [mask] " - "[id] [ev0] [ev1] [ev2] [ev3] [ev4] [ev5] [ev6] " - "[ev7] > sample_id_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nip_range: BCM_EACH(%d), BCM_ALL(%d)\n", - BCM_EACH, BCM_ALL); - count += scnprintf(buf + count, size - count, - "ip_index: number of bcm ip (0 ~ %u)\n" - " (if ip_range is all, set to 0)\n", - data->bcm_ip_nr - 1); - count += scnprintf(buf + count, size - count, - "define_index: index of pre-defined event (0 ~ %u)\n" - " 0 means no pre-defined event\n", - data->define_event_max - 1); - count += scnprintf(buf + count, size - count, - "mask: masking for sample id (if define_index is not 0, set to 0)\n" - " mask value should be in hex\n"); - count += scnprintf(buf + count, size - count, - "id: id of sample id (if define_index is not 0, set to 0)\n" - " id should be in hex\n"); - count += scnprintf(buf + count, size - count, - "evX: event counter enable for sample id (if define_index is not 0, set to 0)\n" - " value should be 0 or 1\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_sample_id_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { @@ -2654,43 +2415,6 @@ static ssize_t show_run_ctrl(struct file *fp, char __user *ubuf, size_t size, lo return ret; } -static ssize_t show_run_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_run_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= run_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat run_ctrl\n" - "run state: raw state([run_state]), sw state([run_state])\n"); - - /* help store_run_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= run_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [run_state] > run_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nrun_state: BCM_RUN(%d), BCM_STOP(%d)\n", - BCM_RUN, BCM_STOP); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_run_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { struct exynos_bcm_dbg_data *data = fp->private_data; @@ -2762,44 +2486,6 @@ static ssize_t show_period_ctrl(struct file *fp, char __user *ubuf, size_t size, return ret; } -static ssize_t show_period_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_period_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= period_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat period_ctrl\n" - "monitor period: [period] usec\n"); - - /* help store_period_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= period_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [period] > period_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nperiod: monitor period (unit: usec),\n" - " min(%d usec) ~ max(%d usec)\n", - BCM_TIMER_PERIOD_MIN, BCM_TIMER_PERIOD_MAX); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_period_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { @@ -2871,46 +2557,6 @@ static ssize_t show_mode_ctrl(struct file *fp, char __user *ubuf, size_t size, l return ret; } -static ssize_t show_mode_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_mode_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= mode_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat mode_ctrl\n" - "mode: [mode] (%d:Interval, %d:Once, %d:User_ctrl, %d:Accumulator)\n", - BCM_MODE_INTERVAL, BCM_MODE_ONCE, BCM_MODE_USERCTRL, - BCM_MODE_ACCUMULATOR); - - /* help store_mode_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= mode_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [mode] > mode_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nmode: %d:Interval, %d:Once, %d:User_ctrl, %d:Accumulator\n", - BCM_MODE_INTERVAL, BCM_MODE_ONCE, BCM_MODE_USERCTRL, - BCM_MODE_ACCUMULATOR); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_mode_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { struct exynos_bcm_dbg_data *data = fp->private_data; @@ -2979,42 +2625,6 @@ static ssize_t show_str_ctrl(struct file *fp, char __user *ubuf, size_t size, lo return ret; } -static ssize_t show_str_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_str_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= str_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat str_ctrl\n" - "str state: [str_state]\n"); - - /* help store_str_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= str_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [str_state] > str_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nstr_state: suspend(1), resume(0)\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_str_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { struct exynos_bcm_dbg_data *data = fp->private_data; @@ -3097,46 +2707,6 @@ static ssize_t show_ip_ctrl(struct file *fp, char __user *ubuf, size_t size, lof return ret; } -static ssize_t show_ip_ctrl_help(struct file *fp, char __user *ubuf, size_t size, loff_t *ppos) -{ - struct exynos_bcm_dbg_data *data = fp->private_data; - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_ip_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= ip_ctrl get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "cat ip_ctrl\n" - "bcm[ip_index]: enabled ([enable])\n"); - - /* help store_ip_ctrl */ - count += scnprintf(buf + count, size - count, - "\n= ip_ctrl set help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, - "echo [ip_index] [enable] > ip_ctrl\n"); - count += scnprintf(buf + count, size - count, - "\nip_index: number of bcm ip (0 ~ %u)\n", - data->bcm_ip_nr - 1); - count += scnprintf(buf + count, size - count, - "enable: ip enable state (1:enable, 0:disable)\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - static ssize_t store_ip_ctrl(struct file *fp, const char __user *ubuf, size_t size, loff_t *ppos) { struct exynos_bcm_dbg_data *data = fp->private_data; @@ -3515,36 +3085,6 @@ static ssize_t show_dump_accumulators(struct file *fp, char __user *ubuf, size_t return ret; } -static ssize_t show_dump_accumulators_help(struct file *fp, char __user *ubuf, size_t size, - loff_t *ppos) -{ - char *buf; - ssize_t ret; - ssize_t count = 0; - - if (*ppos > 0) - return 0; - - buf = kmalloc(size, GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - /* help show_dump_accumulators_help */ - count += scnprintf(buf + count, size - count, - "\n= dump_accumulators get help =\n"); - count += scnprintf(buf + count, size - count, "Usage:\n"); - count += scnprintf(buf + count, size - count, "cat dump_accumulators\n"); - count += scnprintf(buf + count, size - count, - "[seq_no], [ip_index], [define_event], [time], [ccnt], [pmcnt0], "); - count += scnprintf(buf + count, size - count, - "[pmcnt1], [pmcnt2], [pmcnt3], [pmcnt4], [pmcnt5], [pmcnt6], [pmcnt7]\n"); - - ret = simple_read_from_buffer(ubuf, size, ppos, buf, count); - kfree(buf); - - return ret; -} - #if IS_ENABLED(CONFIG_DEBUG_SNAPSHOT) static int exynos_bcm_dbg_dump_config(struct exynos_bcm_dbg_data *data) { @@ -3623,7 +3163,6 @@ static struct bcm_file_entry bcm_dbg_file_entries[] = { #endif BCM_FILE_ENTRY_RO(boot_config), BCM_FILE_ENTRY_RO(dump_accumulators), - BCM_FILE_ENTRY_RO(dump_accumulators_help), #if IS_ENABLED(CONFIG_DEBUG_SNAPSHOT) BCM_FILE_ENTRY_WR(dump_addr_info), #endif @@ -3633,31 +3172,22 @@ static struct bcm_file_entry bcm_dbg_file_entries[] = { BCM_FILE_ENTRY_WR(enable_dump_klog), BCM_FILE_ENTRY_WR(enable_stop_owner), BCM_FILE_ENTRY_WR(event_ctrl), - BCM_FILE_ENTRY_RO(event_ctrl_help), BCM_FILE_ENTRY_RO(filter_id_active), BCM_FILE_ENTRY_WR(filter_id_ctrl), - BCM_FILE_ENTRY_RO(filter_id_ctrl_help), BCM_FILE_ENTRY_RO(filter_others_active), BCM_FILE_ENTRY_WR(filter_others_ctrl), - BCM_FILE_ENTRY_RO(filter_others_ctrl_help), BCM_FILE_ENTRY_WR(ip_ctrl), - BCM_FILE_ENTRY_RO(ip_ctrl_help), BCM_FILE_ENTRY_RO(ip_power_domains), BCM_FILE_ENTRY_WR(mode_ctrl), - BCM_FILE_ENTRY_RO(mode_ctrl_help), BCM_FILE_ENTRY_WR(period_ctrl), - BCM_FILE_ENTRY_RO(period_ctrl_help), BCM_FILE_ENTRY_RO(ppmu_ver), BCM_FILE_ENTRY_RO(predefined_events), BCM_FILE_ENTRY_RO(predefined_filters), BCM_FILE_ENTRY_RO(predefined_sample_mask), BCM_FILE_ENTRY_WR(run_ctrl), - BCM_FILE_ENTRY_RO(run_ctrl_help), BCM_FILE_ENTRY_RO(sample_id_active), BCM_FILE_ENTRY_WR(sample_id_ctrl), - BCM_FILE_ENTRY_RO(sample_id_ctrl_help), BCM_FILE_ENTRY_WR(str_ctrl), - BCM_FILE_ENTRY_RO(str_ctrl_help), }; static void exynos_bcm_dbg_init_debugfs(struct exynos_bcm_dbg_data *data) diff --git a/drivers/soc/google/exynos-pd.c b/drivers/soc/google/exynos-pd.c index e9dc56ecebcb..9f2eee802670 100644 --- a/drivers/soc/google/exynos-pd.c +++ b/drivers/soc/google/exynos-pd.c @@ -45,6 +45,31 @@ struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name) } EXPORT_SYMBOL(exynos_pd_lookup_name); +void *exynos_pd_lookup_cmu_id(u32 cmu_id) +{ + struct exynos_pm_domain *exypd = NULL; + struct device_node *np; + + for_each_compatible_node(np, NULL, "samsung,exynos-pd") { + struct platform_device *pdev; + struct exynos_pm_domain *pd; + + if (!of_device_is_available(np)) + continue; + + pdev = of_find_device_by_node(np); + if (!pdev) + continue; + pd = platform_get_drvdata(pdev); + if (pd->cmu_id == cmu_id) { + exypd = pd; + break; + } + } + return exypd; +} +EXPORT_SYMBOL(exynos_pd_lookup_cmu_id); + int exynos_pd_status(struct exynos_pm_domain *pd) { int status; @@ -104,6 +129,18 @@ static void exynos_pd_power_on_pre(struct exynos_pm_domain *pd) } } +static void exynos_pd_power_on_post(struct exynos_pm_domain *pd) +{ + if (pd->cal_pdid == HSI0_CAL_PDID) + exynos_usbdrd_s2mpu_manual_control(1); +} + +static void exynos_pd_power_off_pre(struct exynos_pm_domain *pd) +{ + if (pd->cal_pdid == HSI0_CAL_PDID) + exynos_usbdrd_s2mpu_manual_control(0); +} + static void exynos_pd_power_off_post(struct exynos_pm_domain *pd) { if (!pd->skip_idle_ip) @@ -160,6 +197,8 @@ static int __exynos_pd_power_on(struct exynos_pm_domain *pd) goto acc_unlock; } + exynos_pd_power_on_post(pd); + pd->pd_stat.on_count++; pd->pd_stat.last_on_time = ktime_get_boottime(); @@ -230,6 +269,8 @@ static int __exynos_pd_power_off(struct exynos_pm_domain *pd) goto acc_unlock; } + exynos_pd_power_off_pre(pd); + ret = pd->pd_control(pd->cal_pdid, 0); exynos_pd_power_off_post(pd); @@ -424,6 +465,14 @@ static int exynos_pd_probe(struct platform_device *pdev) dev_dbg(dev, "read need_smc 0x%x successfully.!\n", pd->need_smc); } + + ret = of_property_read_u32(np, "cmu_id", (u32 *)&pd->cmu_id); + if (ret) { + pd->cmu_id = 0x0; + } else { + dev_dbg(dev, "%s read cmu_id 0x%x successfully.!\n", + pd->name, pd->cmu_id); + } initial_state = cal_pd_status(pd->cal_pdid); if (initial_state == -1) { dev_err(dev, "%s is in unknown state\n", pd->name); @@ -490,6 +539,7 @@ static int exynos_pd_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); + cal_register_pd_lookup_cmu_id(exynos_pd_lookup_cmu_id); dev_dbg(dev, "PM Domain Initialized\n"); return ret; } diff --git a/drivers/soc/google/exynos-pm.c b/drivers/soc/google/exynos-pm.c index 9701df897fc5..f49dab91e2db 100644 --- a/drivers/soc/google/exynos-pm.c +++ b/drivers/soc/google/exynos-pm.c @@ -24,6 +24,8 @@ #define EXYNOS_EINT_PEND(b, x) ((b) + 0xA00 + (((x) >> 3) * 4)) #define SHARED_SR0 0x80 +#define WS_BIT_MAILBOX_AOC2AP (7) +#define WS2_BIT_MAILBOX_AOCA322AP (5) static struct exynos_pm_info *pm_info; static struct exynos_pm_dbg *pm_dbg; @@ -106,7 +108,8 @@ static void exynos_show_wakeup_registers(unsigned int wakeup_stat) } static void exynos_show_wakeup_reason_sysint(unsigned int stat, - struct wakeup_stat_name *ws_names) + struct wakeup_stat_name *ws_names, + int wakeup_stat_id) { int bit; unsigned long lstat = stat; @@ -123,7 +126,8 @@ static void exynos_show_wakeup_reason_sysint(unsigned int stat, } str_idx += strscpy(wake_reason + str_idx, ws_names->name[bit], MAX_SUSPEND_ABORT_LEN - str_idx); - if (bit == 7) { /* MAILBOX_AOC2AP */ + if ((wakeup_stat_id == 0 && bit == WS_BIT_MAILBOX_AOC2AP) || + (wakeup_stat_id == 1 && bit == WS2_BIT_MAILBOX_AOCA322AP)) { aoc_id = __raw_readl(pm_info->mbox_aoc + SHARED_SR0); str_idx += scnprintf(wake_reason + str_idx, MAX_SUSPEND_ABORT_LEN - str_idx, @@ -155,7 +159,7 @@ static void exynos_show_wakeup_reason_detail(unsigned int wakeup_stat) if (!wss) continue; - exynos_show_wakeup_reason_sysint(wss, &pm_info->ws_names[i]); + exynos_show_wakeup_reason_sysint(wss, &pm_info->ws_names[i], i); } } @@ -307,14 +311,18 @@ static void exynos_pm_syscore_resume(void) if (pm_dbg->mifdn_early_wakeup_cnt != pm_dbg->mifdn_early_wakeup_prev) pr_debug("%s: Sequence early wakeup\n", EXYNOS_PM_PREFIX); - if (pm_dbg->mifdn_cnt == pm_dbg->mifdn_cnt_prev) + if (pm_dbg->mifdn_cnt == pm_dbg->mifdn_cnt_prev) { pr_info("%s: MIF blocked. MIF request Mster was 0x%x\n", EXYNOS_PM_PREFIX, pm_dbg->mif_req); - else +#ifdef CONFIG_SUSPEND + log_abnormal_wakeup_reason("MIF request 0x%x", pm_dbg->mif_req); +#endif + } else { pr_info("%s: MIF down. cur_count: %d, acc_count: %d\n", EXYNOS_PM_PREFIX, pm_dbg->mifdn_cnt - pm_dbg->mifdn_cnt_prev, pm_dbg->mifdn_cnt); + } if (pm_info->is_pcieon_suspend || pm_dbg->test_pcieon_suspend) exynos_wakeup_sys_powerdown(pm_info->pcieon_suspend_mode_idx, diff --git a/drivers/soc/google/gs-chipid.c b/drivers/soc/google/gs-chipid.c index 8fe09202aee8..24e6788f0a77 100644 --- a/drivers/soc/google/gs-chipid.c +++ b/drivers/soc/google/gs-chipid.c @@ -22,13 +22,16 @@ struct gs_chipid_variant { int rev_reg; int main_rev_bit; int sub_rev_bit; + int dvfs_version_reg; }; -#define RAW_HEX_STR_SIZE 116 +#define RAW_HEX_STR_SIZE 132 #define AP_HW_TUNE_HEX_STR_SIZE 64 #define AP_HW_TUNE_HEX_ARRAY_SIZE 32 #define ASV_TBL_HEX_STR_SIZE 128 #define HPM_ASV_HEX_STR_SIZE 128 +#define GS101_HPM_ASV_END_ADDR 0xA024 +#define GS201_HPM_ASV_END_ADDR 0xA02C static void gs_chipid_get_asv_tbl_str(void __iomem *reg); static void gs_chipid_get_hpm_asv_str(void __iomem *reg); @@ -47,6 +50,7 @@ struct gs_chipid_info { u32 sub_rev; u32 lot_id; char *lot_id2; + u32 dvfs_version; u64 unique_id; char ap_hw_tune_str[AP_HW_TUNE_HEX_STR_SIZE+1]; u8 ap_hw_tune_arr[AP_HW_TUNE_HEX_ARRAY_SIZE]; @@ -59,9 +63,12 @@ struct gs_chipid_info { }; #define GS101_SOC_ID 0x09845000 +#define GS201_SOC_ID 0x09855000 #define SOC_MASK 0xFFFFF000 #define SOC_MASK_V2 0x00FFFFFF -#define SOC_TYPE_MASK 0x0000000F +#define SOC_TYPE_MASK 0x000000FF +#define GS201_TYPE_MASK 0x00F00000 +#define GS201_TYPE_SHIFT 20 #define LOTID_MASK 0x001FFFFF #define REV_MASK 0xF @@ -81,6 +88,9 @@ static const char *product_id_to_name(unsigned int product_id) case GS101_SOC_ID: soc_name = "GS101"; break; + case GS201_SOC_ID: + soc_name = "GS201"; + break; default: soc_name = "UNKNOWN"; } @@ -93,6 +103,16 @@ static const struct gs_chipid_variant drv_data_gs101 = { .rev_reg = 0x10, .main_rev_bit = 0, .sub_rev_bit = 16, + .dvfs_version_reg = 0x900C, +}; + +static const struct gs_chipid_variant drv_data_gs201 = { + .product_ver = 1, + .unique_id_reg = 0x04, + .rev_reg = 0x10, + .main_rev_bit = 0, + .sub_rev_bit = 16, + .dvfs_version_reg = 0x900C, }; static char lot_id[6]; @@ -163,6 +183,12 @@ static ssize_t lot_id2_show(struct device *dev, return scnprintf(buf, PAGE_SIZE, "%s\n", gs_soc_info.lot_id2); } +static ssize_t dvfs_version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%u\n", gs_soc_info.dvfs_version); +} + static ssize_t revision_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -216,6 +242,7 @@ static DEVICE_ATTR_RO(product_id); static DEVICE_ATTR_RO(unique_id); static DEVICE_ATTR_RO(lot_id); static DEVICE_ATTR_RO(lot_id2); +static DEVICE_ATTR_RO(dvfs_version); static DEVICE_ATTR_RO(revision); static DEVICE_ATTR_RO(evt_ver); static DEVICE_ATTR_RO(raw_str); @@ -228,6 +255,7 @@ static struct attribute *chipid_sysfs_attrs[] = { &dev_attr_unique_id.attr, &dev_attr_lot_id.attr, &dev_attr_lot_id2.attr, + &dev_attr_dvfs_version.attr, &dev_attr_revision.attr, &dev_attr_evt_ver.attr, &dev_attr_raw_str.attr, @@ -267,6 +295,15 @@ u32 gs_chipid_get_type(void) } EXPORT_SYMBOL_GPL(gs_chipid_get_type); +s32 gs_chipid_get_dvfs_version(void) +{ + if (!gs_soc_info.initialized) + return -EPROBE_DEFER; + + return gs_soc_info.dvfs_version; +} +EXPORT_SYMBOL_GPL(gs_chipid_get_dvfs_version); + u32 gs_chipid_get_revision(void) { if (!gs_soc_info.initialized) @@ -292,6 +329,9 @@ static void gs_chipid_get_chipid_info(void __iomem *reg) case 1: default: gs_soc_info.product_id = val & SOC_MASK; + if (gs_soc_info.product_id == GS201_SOC_ID) + val |= (readl_relaxed(reg + data->rev_reg) + & GS201_TYPE_MASK) >> GS201_TYPE_SHIFT; gs_soc_info.type = val & SOC_TYPE_MASK; break; } @@ -313,30 +353,42 @@ static void gs_chipid_get_chipid_info(void __iomem *reg) temp = (temp >> 11) & LOTID_MASK; chipid_dec_to_36(temp, uniq_id1, lot_id); gs_soc_info.lot_id2 = lot_id; + + val = readb_relaxed(reg + data->dvfs_version_reg); + gs_soc_info.dvfs_version = val; } static void gs_chipid_get_raw_str(void __iomem *reg) { u32 addr; + u32 addr_end; u8 val; int str_pos = 0; + size_t str_buf_size = sizeof(gs_soc_info.raw_str); for (addr = 0x4; addr < 0xA; addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.raw_str + str_pos, - RAW_HEX_STR_SIZE - str_pos, + str_buf_size - str_pos, "%02x", val); } - for (addr = 0xA000; addr < 0xA024; addr++) { + + if (gs_soc_info.product_id == GS201_SOC_ID) { + addr_end = GS201_HPM_ASV_END_ADDR; + } else { + addr_end = GS101_HPM_ASV_END_ADDR; + } + + for (addr = 0xA000; addr < addr_end; addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.raw_str + str_pos, - RAW_HEX_STR_SIZE - str_pos, + str_buf_size - str_pos, "%02x", val); } for (addr = 0x9000; addr < 0x9010; addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.raw_str + str_pos, - RAW_HEX_STR_SIZE - str_pos, + str_buf_size - str_pos, "%02x", val); } } @@ -347,11 +399,12 @@ static void gs_chipid_get_ap_hw_tune_str(void __iomem *reg) u8 val; int str_pos = 0; int arr_pos = 0; + size_t str_buf_size = sizeof(gs_soc_info.ap_hw_tune_str); for (addr = 0xC300; addr < (0xC300 + AP_HW_TUNE_HEX_STR_SIZE/2); addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.ap_hw_tune_str + str_pos, - AP_HW_TUNE_HEX_STR_SIZE - str_pos, "%02x", + str_buf_size - str_pos, "%02x", val); if (arr_pos < ARRAY_SIZE(gs_soc_info.ap_hw_tune_arr)) gs_soc_info.ap_hw_tune_arr[arr_pos++] = val; @@ -373,11 +426,12 @@ static void gs_chipid_get_asv_tbl_str(void __iomem *reg) u32 addr; u8 val; int str_pos = 0; + size_t str_buf_size = sizeof(gs_soc_info.asv_tbl_str); for (addr = 0x9000; addr < (0x9000 + ASV_TBL_HEX_STR_SIZE/2); addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.asv_tbl_str + str_pos, - ASV_TBL_HEX_STR_SIZE - str_pos, "%02x", + str_buf_size - str_pos, "%02x", val); } } @@ -387,11 +441,12 @@ static void gs_chipid_get_hpm_asv_str(void __iomem *reg) u32 addr; u8 val; int str_pos = 0; + size_t str_buf_size = sizeof(gs_soc_info.hpm_asv_str); for (addr = 0xA000; addr < (0xA000 + HPM_ASV_HEX_STR_SIZE/2); addr++) { val = readb_relaxed(reg + addr); str_pos += scnprintf(gs_soc_info.hpm_asv_str + str_pos, - HPM_ASV_HEX_STR_SIZE - str_pos, "%02x", + str_buf_size - str_pos, "%02x", val); } } @@ -401,6 +456,10 @@ static const struct of_device_id of_gs_chipid_ids[] = { .compatible = "google,gs101-chipid", .data = &drv_data_gs101, }, + { + .compatible = "google,gs201-chipid", + .data = &drv_data_gs201, + }, {}, }; diff --git a/drivers/soc/google/gsa/Kconfig b/drivers/soc/google/gsa/Kconfig index 5a54524b2101..2a57f07025a3 100644 --- a/drivers/soc/google/gsa/Kconfig +++ b/drivers/soc/google/gsa/Kconfig @@ -2,6 +2,12 @@ config GSA tristate "GSA driver" default n +config GSA_PKVM + bool "Support pKVM" + depends on GSA + depends on PKVM_S2MPU + default n + config GSA_GSC tristate "GSC Proxy" depends on GSA diff --git a/drivers/soc/google/gsa/gsa_core.c b/drivers/soc/google/gsa/gsa_core.c index 302638523cb3..64d56cbde28a 100644 --- a/drivers/soc/google/gsa/gsa_core.c +++ b/drivers/soc/google/gsa/gsa_core.c @@ -565,6 +565,15 @@ int gsa_sjtag_end_session(struct device *gsa, u32 *status) } EXPORT_SYMBOL_GPL(gsa_sjtag_end_session); +/* + * External image authentication interface + */ +int gsa_authenticate_image(struct device *gsa, dma_addr_t img_meta, phys_addr_t img_body) +{ + return gsa_send_load_img_cmd(gsa, GSA_MB_CMD_AUTH_IMG, img_meta, img_body); +} +EXPORT_SYMBOL_GPL(gsa_authenticate_image); + /********************************************************************/ static int gsa_probe(struct platform_device *pdev) @@ -593,7 +602,7 @@ static int gsa_probe(struct platform_device *pdev) /* initialize mailbox */ s->mb = gsa_mbox_init(pdev); if (IS_ERR(s->mb)) - return -ENOMEM; + return (int)PTR_ERR(s->mb); /* add children */ err = devm_of_platform_populate(dev); @@ -653,6 +662,11 @@ static void __exit gsa_driver_exit(void) platform_driver_unregister(&gsa_driver); } +/* XXX - EPROBE_DEFER would be better. */ +#ifdef CONFIG_GSA_PKVM +MODULE_SOFTDEP("pre: pkvm-s2mpu"); +#endif + MODULE_DESCRIPTION("Google GSA core platform driver"); MODULE_LICENSE("GPL v2"); module_init(gsa_driver_init); diff --git a/drivers/soc/google/gsa/gsa_mbox.c b/drivers/soc/google/gsa/gsa_mbox.c index dd0c848ce89b..423c86cf503f 100644 --- a/drivers/soc/google/gsa/gsa_mbox.c +++ b/drivers/soc/google/gsa/gsa_mbox.c @@ -12,6 +12,11 @@ #include #include +#if IS_ENABLED(CONFIG_GSA_PKVM) +#include +#include +#endif + #include "gsa_mbox.h" /* Mailbox control Register */ @@ -82,6 +87,8 @@ struct gsa_mbox { struct mutex mbox_lock; /* protects access to SRs */ struct completion mbox_cmd_completion; u32 exp_intmr0; + u32 wake_ref_cnt; + struct device *s2mpu; }; static void gsa_mbox_mask_irq0(struct gsa_mbox *mb, u32 mask) @@ -150,6 +157,44 @@ static irqreturn_t gsa_mb_irq_handler(int irq, void *data) return IRQ_HANDLED; } +#if IS_ENABLED(CONFIG_GSA_PKVM) + +static void gsa_unlink_s2mpu(void *ctx) +{ + struct gsa_mbox *mb = ctx; + + put_device(mb->s2mpu); + mb->s2mpu = NULL; +} + +static int gsa_link_s2mpu(struct device *dev, struct gsa_mbox *mb) +{ + /* We expect "s2mpu" entry in device node to point to gsa s2mpu driver + * This entry is absolutely required for normal operation on most + * devices. + */ + mb->s2mpu = pkvm_s2mpu_of_parse(dev); + if (!mb->s2mpu) { + dev_err(dev, "no 's2mpu' entry found\n"); + return -ENODEV; + } else if (IS_ERR(mb->s2mpu)) { + dev_err(dev, "error parsing 's2mpu' phandle: %ld\n", + PTR_ERR(mb->s2mpu)); + return -ENODEV; + } + + dev_info(dev, "linked to %s\n", dev_name(mb->s2mpu)); + + /* register unlink hook for s2mpu device */ + return devm_add_action_or_reset(dev, gsa_unlink_s2mpu, mb); +} +#else /* CONFIG_GSA_PKVM */ +static int gsa_link_s2mpu(struct device *dev, struct gsa_mbox *mb) +{ + return 0; +} +#endif /* CONFIG_GSA_PKVM */ + struct gsa_mbox *gsa_mbox_init(struct platform_device *pdev) { int err; @@ -161,6 +206,10 @@ struct gsa_mbox *gsa_mbox_init(struct platform_device *pdev) if (!mb) return ERR_PTR(-ENOMEM); + err = gsa_link_s2mpu(dev, mb); + if (err) + return ERR_PTR(err); + mb->dev = dev; spin_lock_init(&mb->slock); mutex_init(&mb->mbox_lock); @@ -195,9 +244,9 @@ struct gsa_mbox *gsa_mbox_init(struct platform_device *pdev) return mb; } -static int exec_mbox_cmd_sync(struct gsa_mbox *mb, - struct gsa_mbox_req *req, - struct gsa_mbox_rsp *rsp) +static int exec_mbox_cmd_sync_locked(struct gsa_mbox *mb, + struct gsa_mbox_req *req, + struct gsa_mbox_rsp *rsp) { u32 i; int ret; @@ -227,8 +276,6 @@ static int exec_mbox_cmd_sync(struct gsa_mbox *mb, /* save max response arg count */ max_rsp_argc = rsp->argc; - mutex_lock(&mb->mbox_lock); - /* write command */ writel(req->cmd, mb->base + MBOX_SR_REG(0)); writel(req->argc, mb->base + MBOX_SR_REG(1)); @@ -276,7 +323,6 @@ static int exec_mbox_cmd_sync(struct gsa_mbox *mb, gsa_mbox_clr_irq0(mb, (0x1u << MBOX_CLIENT_RSP_IRQ)); gsa_mbox_mask_irq0(mb, (0x1u << MBOX_CLIENT_RSP_IRQ)); - mutex_unlock(&mb->mbox_lock); return ret; } @@ -346,9 +392,9 @@ static int check_mbox_cmd_rsp(struct device *dev, return 0; } -int gsa_send_mbox_cmd(struct gsa_mbox *mb, u32 cmd, - u32 *req_args, u32 req_argc, - u32 *rsp_args, u32 rsp_max_argc) +static int gsa_send_mbox_cmd_locked(struct gsa_mbox *mb, u32 cmd, + u32 *req_args, u32 req_argc, + u32 *rsp_args, u32 rsp_max_argc) { int ret; struct gsa_mbox_req mb_req; @@ -366,7 +412,7 @@ int gsa_send_mbox_cmd(struct gsa_mbox *mb, u32 cmd, mb_rsp.args = rsp_args; /* execute command */ - ret = exec_mbox_cmd_sync(mb, &mb_req, &mb_rsp); + ret = exec_mbox_cmd_sync_locked(mb, &mb_req, &mb_rsp); if (ret < 0) return ret; @@ -378,4 +424,165 @@ int gsa_send_mbox_cmd(struct gsa_mbox *mb, u32 cmd, return mb_rsp.argc; } +static bool is_data_xfer(uint32_t cmd) +{ + switch (cmd) { + case GSA_MB_CMD_AUTH_IMG: + case GSA_MB_CMD_LOAD_FW_IMG: + case GSA_MB_TEST_CMD_START_UNITTEST: + case GSA_MB_TEST_CMD_RUN_UNITTEST: + case GSA_MB_CMD_LOAD_TPU_FW_IMG: + case GSA_MB_CMD_UNLOAD_TPU_FW_IMG: + case GSA_MB_CMD_GSC_TPM_DATAGRAM: + case GSA_MB_CMD_KDN_GENERATE_KEY: + case GSA_MB_CMD_KDN_EPHEMERAL_WRAP_KEY: + case GSA_MB_CMD_KDN_DERIVE_RAW_SECRET: + case GSA_MB_CMD_KDN_PROGRAM_KEY: + case GSA_MB_CMD_LOAD_AOC_FW_IMG: + case GSA_MB_CMD_SJTAG_GET_PUB_KEY_HASH: + case GSA_MB_CMD_SJTAG_SET_PUB_KEY: + case GSA_MB_CMD_SJTAG_GET_CHALLENGE: + case GSA_MB_CMD_SJTAG_ENABLE: + return true; + + default: + return false; + } +} + +#if IS_ENABLED(CONFIG_GSA_PKVM) + +#define MAX_GSA_WAKELOCK_CNT 100 + +static int gsa_data_xfer_prepare_locked(struct gsa_mbox *mb) +{ + int rc; + int ret; + + if (WARN_ON(mb->wake_ref_cnt >= MAX_GSA_WAKELOCK_CNT)) + return -EINVAL; + + if (mb->wake_ref_cnt) { + /* just bump wake ref count */ + ++mb->wake_ref_cnt; + return 0; + } + + /* + * If we are running under Hypervisor DATA XFER command requires + * proper SYSMMU_S2 configuration. Since GSA SYSMMU_S2 is in GSACORE + * power domain, we need grab wakelock in order to make sure it is + * powered + */ + ret = gsa_send_mbox_cmd_locked(mb, GSA_MB_CMD_WAKELOCK_ACQUIRE, + NULL, 0, NULL, 0); + if (ret < 0) { + dev_err(mb->dev, "gsa wakelock acquire failed (%d)\n", + ret); + return ret; + } + ++mb->wake_ref_cnt; + + /* resume gsa s2mpu */ + ret = pkvm_s2mpu_resume(mb->s2mpu); + if (ret < 0) { + dev_err(mb->s2mpu, "failed to resume s2mpu (%d)\n", ret); + goto err_s2mpu_resume; + } + + return 0; + +err_s2mpu_resume: + /* release wakelock */ + rc = gsa_send_mbox_cmd_locked(mb, GSA_MB_CMD_WAKELOCK_RELEASE, + NULL, 0, NULL, 0); + if (WARN_ON(rc < 0)) { + dev_err(mb->dev, "gsa wakelock release failed (%d): leaking wakelock\n", rc); + } else { + /* undo ref count obtained after acquiring lock */ + --mb->wake_ref_cnt; + } + return ret; +} + +static void gsa_data_xfer_finish_locked(struct gsa_mbox *mb) +{ + int rc; + + if (WARN_ON(!mb->wake_ref_cnt)) + return; + + if (mb->wake_ref_cnt > 1) { + /* Just decrement wake ref count */ + --mb->wake_ref_cnt; + return; + } + + /* suspend gsa s2mpu */ + rc = pkvm_s2mpu_suspend(mb->s2mpu); + if (rc < 0) { + dev_err(mb->s2mpu, "failed to suspend s2mpu (%d), leaking wakelock\n", rc); + return; + } + + /* the following call can only fail if acquire/release + * are imbalanced, in this case we cannot really continue. + */ + rc = gsa_send_mbox_cmd_locked(mb, GSA_MB_CMD_WAKELOCK_RELEASE, + NULL, 0, NULL, 0); + if (WARN_ON(rc < 0)) { + dev_err(mb->dev, "gsa wakelock release failed (%d)\n", rc); + goto err_wakelock_release; + } + + /* decrement wake ref */ + --mb->wake_ref_cnt; + return; + +err_wakelock_release: + /* at least try to get into consistent state */ + rc = pm_runtime_get_sync(mb->s2mpu); + if (WARN_ON(rc < 0)) + dev_err(mb->s2mpu, "failed to resume s2mpu (%d), leaking wakelock\n", rc); + return; +} + +#else /* CONFIG_GSA_PKVM */ + +static int gsa_data_xfer_prepare_locked(struct gsa_mbox *mb) +{ + return 0; +} + +static void gsa_data_xfer_finish_locked(struct gsa_mbox *mb) {} + +#endif /* CONFIG_GSA_PKVM */ + +int gsa_send_mbox_cmd(struct gsa_mbox *mb, u32 cmd, + u32 *req_args, u32 req_argc, + u32 *rsp_args, u32 rsp_max_argc) +{ + int ret; + bool data_xfer = is_data_xfer(cmd); + + mutex_lock(&mb->mbox_lock); + + if (data_xfer) { + ret = gsa_data_xfer_prepare_locked(mb); + if (ret < 0) + goto err_data_prepare; + } + + /* send command */ + ret = gsa_send_mbox_cmd_locked(mb, cmd, req_args, req_argc, + rsp_args, rsp_max_argc); + + if (data_xfer) + gsa_data_xfer_finish_locked(mb); + +err_data_prepare: + mutex_unlock(&mb->mbox_lock); + return ret; +} + MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/google/gsa/gsa_mbox.h b/drivers/soc/google/gsa/gsa_mbox.h index 96c842fb2570..9a8d91b4e0e1 100644 --- a/drivers/soc/google/gsa/gsa_mbox.h +++ b/drivers/soc/google/gsa/gsa_mbox.h @@ -58,6 +58,10 @@ enum gsa_mbox_cmd { GSA_MB_CMD_SJTAG_GET_CHALLENGE = 104, GSA_MB_CMD_SJTAG_ENABLE = 105, GSA_MB_CMD_SJTAG_FINISH = 106, + + /* PM commands */ + GSA_MB_CMD_WAKELOCK_ACQUIRE = 150, + GSA_MB_CMD_WAKELOCK_RELEASE = 151, }; /** diff --git a/drivers/soc/google/hardlockup-debug.c b/drivers/soc/google/hardlockup-debug.c index e0941a3ae0f2..02c9f5e6c0b7 100644 --- a/drivers/soc/google/hardlockup-debug.c +++ b/drivers/soc/google/hardlockup-debug.c @@ -39,7 +39,10 @@ #endif #include -#define HARDLOCKUP_DEBUG_MAGIC (0xDEADBEEF) +#define HARDLOCKUP_DEBUG_EL1_FIQ_MAGIC (0xDEADBEEF) +#define HARDLOCKUP_DEBUG_EL1_SGI_MAGIC (HARDLOCKUP_DEBUG_EL1_FIQ_MAGIC + 1) +#define HARDLOCKUP_DEBUG_EL2_FIQ_MAGIC (HARDLOCKUP_DEBUG_EL1_FIQ_MAGIC - 4) +#define HARDLOCKUP_DEBUG_EL2_SGI_MAGIC (HARDLOCKUP_DEBUG_EL1_FIQ_MAGIC - 3) #define BUG_BRK_IMM_HARDLOCKUP (0x801) #define FIQ_PENDING_INST_INDEX (ARRAY_SIZE(hardlockup_debug_cpu_resume_insts) - 1) @@ -173,12 +176,6 @@ static void pm_dev_end(void *data, struct device *dev, int error) spin_unlock_irqrestore(&pm_trace_lock, flags); } -static void vh_bug_on_wdt_fiq_pending(void *data, int state, struct cpuidle_device *dev) -{ - if (get_pending_fiq_cpu_id() == raw_smp_processor_id()) - hardlockup_debug_bug_func(); -} - static void hardlockup_debug_disable_fiq(void) { asm volatile (__stringify(msr daifset, #0x1)); @@ -205,6 +202,23 @@ static inline int hardlockup_debug_try_lock_timeout(raw_spinlock_t *lock, return ret; } +static bool is_valid_hardlockup_magic(int val) +{ + return val == HARDLOCKUP_DEBUG_EL1_FIQ_MAGIC || + val == HARDLOCKUP_DEBUG_EL1_SGI_MAGIC || + val == HARDLOCKUP_DEBUG_EL2_FIQ_MAGIC || + val == HARDLOCKUP_DEBUG_EL2_SGI_MAGIC; +} + +static void vh_bug_on_wdt_fiq_pending(void *data, int state, struct cpuidle_device *dev) +{ + int cpu = raw_smp_processor_id(); + + if (get_pending_fiq_cpu_id() == cpu || + is_valid_hardlockup_magic(dbg_snapshot_get_hardlockup_magic(cpu))) + hardlockup_debug_bug_func(); +} + static unsigned long hardlockup_debug_get_locked_cpu_mask(void) { unsigned long mask = 0; @@ -213,8 +227,7 @@ static unsigned long hardlockup_debug_get_locked_cpu_mask(void) for_each_online_cpu(cpu) { val = dbg_snapshot_get_hardlockup_magic(cpu); - if (val == HARDLOCKUP_DEBUG_MAGIC || - val == (HARDLOCKUP_DEBUG_MAGIC + 1)) + if (is_valid_hardlockup_magic(val)) mask |= (1 << cpu); } @@ -239,8 +252,7 @@ static int hardlockup_debug_bug_handler(struct pt_regs *regs, unsigned int esr) if (watchdog_fiq && !allcorelockup_detected) { /* 1st WDT FIQ trigger */ val = dbg_snapshot_get_hardlockup_magic(cpu); - if (val == HARDLOCKUP_DEBUG_MAGIC || - val == (HARDLOCKUP_DEBUG_MAGIC + 1)) { + if (is_valid_hardlockup_magic(val)) { allcorelockup_detected = 1; hardlockup_core_mask = hardlockup_debug_get_locked_cpu_mask(); diff --git a/drivers/input/keydebug-func.c b/drivers/soc/google/kernel-top.c similarity index 82% rename from drivers/input/keydebug-func.c rename to drivers/soc/google/kernel-top.c index 5645c39173fd..114e9692d373 100644 --- a/drivers/input/keydebug-func.c +++ b/drivers/soc/google/kernel-top.c @@ -1,35 +1,31 @@ -/* drivers/input/keydebug-func.c +// SPDX-License-Identifier: GPL-2.0-only +/* drivers/soc/google/kernel-top.c * * Copyright (C) 2018 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * */ -#include -#include +#define dev_fmt(fmt) "TOP: " fmt + #include -#include -#include +#include +#include +#include #include +#include +#include #include -#include +#include +#include #include -#include -#include +#include #include #include +#include #define NUM_BUSY_TASK_CHECK 5 struct kernel_top_context { + struct device *owner; u64 *prev_tasktics_array; u64 *frame_tasktics_array; pid_t *curr_task_pid_array; @@ -41,12 +37,10 @@ struct kernel_top_context { bool kernel_top_alloc_done; }; -static struct kernel_top_context ktop_cxt; -static DEFINE_MUTEX(kernel_top_mutex); - +/* Clone from fs/proc/stat.c. */ #ifdef arch_idle_time -static u64 keydebug_get_idle_time(int cpu) +static u64 ktop_get_idle_time(int cpu) { u64 idle; @@ -68,7 +62,7 @@ static u64 get_iowait_time(int cpu) #else -static u64 keydebug_get_idle_time(int cpu) +static u64 ktop_get_idle_time(int cpu) { u64 idle, idle_usecs = -1ULL; @@ -120,7 +114,7 @@ static void get_all_cpustat(struct kernel_cpustat *cpu_stat) cpu_stat->cpustat[CPUTIME_SYSTEM] += kcpustat_cpu(cpu).cpustat[CPUTIME_SYSTEM]; cpu_stat->cpustat[CPUTIME_IDLE] += - keydebug_get_idle_time(cpu); + ktop_get_idle_time(cpu); cpu_stat->cpustat[CPUTIME_IOWAIT] += get_iowait_time(cpu); cpu_stat->cpustat[CPUTIME_IRQ] += @@ -206,11 +200,10 @@ static u64 cal_frame_cpustat_total(struct kernel_cpustat curr_all_cpustat, return (user_time + system_time + io_time + irq_time + idle_time); } -static void kernel_top_cal(void) +static void kernel_top_cal(struct kernel_top_context *cxt) { int task_count = 0; struct task_struct *tsk; - struct kernel_top_context *cxt = &ktop_cxt; /* Calculate each tasks tics in this time frame*/ rcu_read_lock(); @@ -248,21 +241,19 @@ static void kernel_top_cal(void) } -static void kernel_top_show(void) +static void kernel_top_show(struct kernel_top_context *cxt) { pid_t top_n_pid = 0; int i; - struct kernel_top_context *cxt = &ktop_cxt; - pr_info("%s: CPU Usage PID Name\n", __func__); + dev_info(cxt->owner, "CPU Usage PID Name\n"); for (i = 0; i < NUM_BUSY_TASK_CHECK; i++) { if (cxt->frame_cpustat_total > 0) { top_n_pid = cxt->top_task_pid_array[i]; - pr_info("%s: %8llu%%%8d %s%10llu\n", __func__, + dev_info(cxt->owner, "%8llu%%%8d %s%10llu\n", cxt->frame_tasktics_array[top_n_pid] * 100 / cxt->frame_cpustat_total, - top_n_pid, - cxt->task_ptr_array[top_n_pid]->comm, + top_n_pid, cxt->task_ptr_array[top_n_pid]->comm, nsec_to_clock_t(cxt->frame_tasktics_array[top_n_pid])); } } @@ -273,38 +264,32 @@ static void kernel_top_show(void) memset(cxt->curr_task_pid_array, 0, sizeof(pid_t) * PID_MAX_DEFAULT); } -void kernel_top_monitor(void) +void kernel_top_print(struct kernel_top_context *cxt) { struct timespec64 ts; struct rtc_time tm; - struct kernel_top_context *cxt = &ktop_cxt; - mutex_lock(&kernel_top_mutex); if (cxt->kernel_top_alloc_done == false) - goto done; + return; - kernel_top_cal(); - kernel_top_show(); + kernel_top_cal(cxt); + kernel_top_show(cxt); ktime_get_real_ts64(&ts); rtc_time64_to_tm(ts.tv_sec - (sys_tz.tz_minuteswest * 60), &tm); - pr_info("%s: Kernel Top Statistic done" - "(%02d-%02d %02d:%02d:%02d)\n", __func__, + dev_info(cxt->owner, "Kernel Top Statistic done (%02d-%02d %02d:%02d:%02d)\n", tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - -done: - mutex_unlock(&kernel_top_mutex); } -EXPORT_SYMBOL_GPL(kernel_top_monitor); +EXPORT_SYMBOL_GPL(kernel_top_print); -void kernel_top_init(void) +int kernel_top_init(struct device *dev, struct kernel_top_context **pcxt) { - struct task_struct *tsk; - struct timespec64 ts; - struct rtc_time tm; - struct kernel_top_context *cxt = &ktop_cxt; + struct kernel_top_context *cxt; + + cxt = devm_kzalloc(dev, sizeof(*cxt), GFP_KERNEL); + if (!cxt) + return -ENOMEM; - mutex_lock(&kernel_top_mutex); if (cxt->kernel_top_alloc_done == false) { cxt->prev_tasktics_array = @@ -327,6 +312,30 @@ void kernel_top_init(void) cxt->kernel_top_alloc_done = true; } + *pcxt = cxt; + cxt->owner = dev; + kernel_top_reset(cxt); + return 0; + +err_alloc_curr_task_pid: + vfree(cxt->curr_task_pid_array); +err_alloc_task_ptr: + vfree(cxt->task_ptr_array); +err_alloc_frame_tasktics: + vfree(cxt->frame_tasktics_array); +err_alloc_prev_tasktics: + vfree(cxt->prev_tasktics_array); + + return -ENOMEM; +} +EXPORT_SYMBOL_GPL(kernel_top_init); + +void kernel_top_reset(struct kernel_top_context *cxt) +{ + struct task_struct *tsk; + struct timespec64 ts; + struct rtc_time tm; + memset(cxt->prev_tasktics_array, 0, sizeof(u64) * PID_MAX_DEFAULT); memset(cxt->frame_tasktics_array, 0, sizeof(u64) * PID_MAX_DEFAULT); memset(cxt->task_ptr_array, 0, @@ -335,8 +344,7 @@ void kernel_top_init(void) ktime_get_real_ts64(&ts); rtc_time64_to_tm(ts.tv_sec - (sys_tz.tz_minuteswest * 60), &tm); - pr_info("%s: Kernel Top Statistic start" - "(%02d-%02d %02d:%02d:%02d)\n", __func__, + dev_info(cxt->owner, "Kernel Top Statistic start (%02d-%02d %02d:%02d:%02d)\n", tm.tm_mon + 1, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); get_all_cpustat(&cxt->curr_all_cpustat); @@ -354,34 +362,22 @@ void kernel_top_init(void) } } rcu_read_unlock(); - goto done; - -err_alloc_curr_task_pid: - vfree(cxt->curr_task_pid_array); -err_alloc_task_ptr: - vfree(cxt->task_ptr_array); -err_alloc_frame_tasktics: - vfree(cxt->frame_tasktics_array); -err_alloc_prev_tasktics: - vfree(cxt->prev_tasktics_array); - - cxt->kernel_top_alloc_done = false; - pr_info("%s: memory allocate failed", __func__); -done: - mutex_unlock(&kernel_top_mutex); } +EXPORT_SYMBOL_GPL(kernel_top_reset); -void kernel_top_exit(void) +void kernel_top_destroy(struct kernel_top_context *cxt) { - struct kernel_top_context *cxt = &ktop_cxt; - - mutex_lock(&kernel_top_mutex); if (cxt->kernel_top_alloc_done) { vfree(cxt->curr_task_pid_array); vfree(cxt->task_ptr_array); vfree(cxt->frame_tasktics_array); vfree(cxt->prev_tasktics_array); - memset(cxt, 0, sizeof(*cxt)); + + devm_kfree(cxt->owner, cxt); + cxt->kernel_top_alloc_done = false; } - mutex_unlock(&kernel_top_mutex); } +EXPORT_SYMBOL_GPL(kernel_top_destroy); + +MODULE_DESCRIPTION("Kernel-Top utils"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/google/pixel_em/pixel_em.c b/drivers/soc/google/pixel_em/pixel_em.c deleted file mode 100644 index 95f4b7011ea7..000000000000 --- a/drivers/soc/google/pixel_em/pixel_em.c +++ /dev/null @@ -1,493 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* pixel_em.c - * - * Support for runtime-customizable table-based Energy Model - * - * Copyright 2022 Google LLC - */ - -#define pr_fmt(fmt) "pixel-em: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if IS_ENABLED(CONFIG_VH_SCHED) -extern struct em_perf_domain **vendor_sched_cpu_to_em_pd; -#endif - -#if IS_ENABLED(CONFIG_EXYNOS_CPU_THERMAL) -extern struct em_perf_domain **exynos_cpu_cooling_cpu_to_em_pd; -#endif - -static int pixel_em_max_cpu; -static int pixel_em_num_cpu_pds; - -static struct em_perf_domain **em_pds; -static struct em_perf_domain **em_pds_backup; -static struct em_perf_domain **cpu_to_em_pd; -static int *em_pd_to_cpu; // Map em_pd indice to the first CPU of a PD. - -static struct mutex sysfs_em_pd_lock; // Synchronize sysfs EM table accesses. -static struct kobject *primary_sysfs_folder; - -static struct platform_device *platform_dev; - -static int pixel_em_count_cpu_pds(void) -{ - int res = 0; - - cpumask_t unmatched_cpus; - - cpumask_copy(&unmatched_cpus, cpu_possible_mask); - - while (!cpumask_empty(&unmatched_cpus)) { - int first_cpu = cpumask_first(&unmatched_cpus); - struct em_perf_domain *pd = em_cpu_get(first_cpu); - - if (!pd) - return -EPROBE_DEFER; - - cpumask_xor(&unmatched_cpus, &unmatched_cpus, em_span_cpus(pd)); - res++; - } - - return res; -} - -static struct em_perf_domain *clone_pd(const struct em_perf_domain *original_pd) -{ - struct em_perf_domain *pd; - - pd = kzalloc(sizeof(*pd) + cpumask_size(), GFP_KERNEL); - if (!pd) - return NULL; - - cpumask_copy(em_span_cpus(pd), em_span_cpus(original_pd)); - - pd->nr_perf_states = original_pd->nr_perf_states; - pd->milliwatts = original_pd->milliwatts; - - pd->table = kcalloc(original_pd->nr_perf_states, sizeof(struct em_perf_state), GFP_KERNEL); - if (!pd->table) { - kfree(pd); - return NULL; - } - - memcpy(pd->table, original_pd->table, - sizeof(struct em_perf_state) * original_pd->nr_perf_states); - - return pd; -} - -static void copy_pd_table(struct em_perf_domain *dest_pd, const struct em_perf_domain *orig_pd) -{ - int perf_state_id; - - if (dest_pd->nr_perf_states != orig_pd->nr_perf_states) { - pr_err("Trying to copy PDs of different sizes %d and %d!\n", - dest_pd->nr_perf_states, - orig_pd->nr_perf_states); - return; - } - - for (perf_state_id = 0; perf_state_id < orig_pd->nr_perf_states; perf_state_id++) { - dest_pd->table[perf_state_id].power = orig_pd->table[perf_state_id].power; - dest_pd->table[perf_state_id].cost = orig_pd->table[perf_state_id].cost; - } -} - -static void free_pd(const struct em_perf_domain *pd) -{ - if (!pd) - return; - - kfree(pd->table); - kfree(pd); -} - -static int pixel_em_init_cpu_layout(void) -{ - cpumask_t unmatched_cpus; - int current_pd_id = 0; - int num_cpu_pds; - - num_cpu_pds = pixel_em_count_cpu_pds(); - if (num_cpu_pds <= 0) - return num_cpu_pds; - pixel_em_num_cpu_pds = num_cpu_pds; - - pixel_em_max_cpu = cpumask_last(cpu_possible_mask); - - cpu_to_em_pd = kcalloc(pixel_em_max_cpu + 1, sizeof(*cpu_to_em_pd), GFP_KERNEL); - if (!cpu_to_em_pd) - return -ENOMEM; - - em_pd_to_cpu = kcalloc(num_cpu_pds, sizeof(*em_pd_to_cpu), GFP_KERNEL); - if (!em_pd_to_cpu) - return -ENOMEM; - - em_pds = kcalloc(num_cpu_pds, sizeof(*em_pds), GFP_KERNEL); - if (!em_pds) - return -ENOMEM; - - em_pds_backup = kcalloc(num_cpu_pds, sizeof(*em_pds_backup), GFP_KERNEL); - if (!em_pds_backup) - return -ENOMEM; - - cpumask_copy(&unmatched_cpus, cpu_possible_mask); - - while (!cpumask_empty(&unmatched_cpus)) { - int first_cpu = cpumask_first(&unmatched_cpus); - int pd_cpu; - struct em_perf_domain *pd = em_cpu_get(first_cpu); - // pd is guaranteed not to be NULL, as pixel_em_count_cpu_pds completed earlier. - - em_pd_to_cpu[current_pd_id] = first_cpu; - - em_pds[current_pd_id] = clone_pd(pd); - if (!em_pds[current_pd_id]) - return -ENOMEM; - - em_pds_backup[current_pd_id] = clone_pd(em_pds[current_pd_id]); - if (!em_pds_backup[current_pd_id]) - return -ENOMEM; - - for_each_cpu(pd_cpu, em_span_cpus(pd)) { - pr_debug("For CPU %d's domain, seeing CPU %d.\n", first_cpu, pd_cpu); - cpu_to_em_pd[pd_cpu] = em_pds[current_pd_id]; - } - - cpumask_xor(&unmatched_cpus, &unmatched_cpus, em_span_cpus(pd)); - current_pd_id++; - } - - return 0; -} - -static ssize_t sysfs_profile_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) -{ - ssize_t res = 0; - int pd_id; - - mutex_lock(&sysfs_em_pd_lock); - for (pd_id = 0; pd_id < pixel_em_num_cpu_pds; pd_id++) { - int perf_state_id; - - res += sysfs_emit_at(buf, res, "cpu%d {\n", em_pd_to_cpu[pd_id]); - - for (perf_state_id = 0; - perf_state_id < em_pds[pd_id]->nr_perf_states; - perf_state_id++) - res += sysfs_emit_at(buf, - res, - "%lu %lu\n", - em_pds[pd_id]->table[perf_state_id].frequency, - em_pds[pd_id]->table[perf_state_id].power); - - res += sysfs_emit_at(buf, res, "}\n"); - } - mutex_unlock(&sysfs_em_pd_lock); - return res; -} - -static void update_em_entry(int cpu_id, unsigned long freq, unsigned long power) -{ - int target_opp_index = 0; - int max_freq_index; - unsigned long max_freq; - - while (target_opp_index < cpu_to_em_pd[cpu_id]->nr_perf_states) { - if (cpu_to_em_pd[cpu_id]->table[target_opp_index].frequency >= freq) - break; - target_opp_index++; - } - - max_freq_index = cpu_to_em_pd[cpu_id]->nr_perf_states - 1; - max_freq = cpu_to_em_pd[cpu_id]->table[max_freq_index].frequency; - - cpu_to_em_pd[cpu_id]->table[target_opp_index].power = power; - cpu_to_em_pd[cpu_id]->table[target_opp_index].cost = div64_u64(max_freq * power, freq); - pr_info("Updating cpu_em[%d][%luKHz] to {%lu mW, %lu cost}.\n", - cpu_id, - freq, - power, - cpu_to_em_pd[cpu_id]->table[target_opp_index].cost); -} - -static int parse_profile(const char *profile, int profile_length) -{ - char *profile_dup = kstrndup(profile, profile_length, GFP_KERNEL); - char *cur_line; - char *sep_iterator = profile_dup; - - int current_cpu_id = -1; - - int res = 0; - - if (!profile_dup) - return -ENOMEM; - - while ((cur_line = strsep(&sep_iterator, "\n"))) { - char *skipped_blanks = skip_spaces(cur_line); - - if (skipped_blanks[0] == '\0' || skipped_blanks[0] == '}') { - continue; - } else if (strncasecmp(skipped_blanks, "cpu", 3) == 0) { - // Expecting a CPU line here... - if (sscanf(skipped_blanks + 3, "%d", ¤t_cpu_id) != 1) { - pr_err("Error when parsing '%s'!\n", skipped_blanks); - res = -EINVAL; - break; - } - if (current_cpu_id < 0 || current_cpu_id > pixel_em_max_cpu) { - pr_err("Invalid CPU specified on line '%s'!\n", skipped_blanks); - res = -EINVAL; - break; - } - pr_debug("Setting active CPU to %d...\n", current_cpu_id); - } else if (skipped_blanks[0] != '\0' && skipped_blanks[0] != '}') { - unsigned long freq = 0; - unsigned long power = 0; - - if (current_cpu_id == -1) { - pr_err("Error: no CPU id specified before parsing '%s'!\n", - skipped_blanks); - res = -EINVAL; - break; - } - if (sscanf(skipped_blanks, "%lu %lu", &freq, &power) != 2) { - pr_err("Error when parsing '%s'!\n", skipped_blanks); - res = -EINVAL; - break; - } - pr_info("Scanned freq %luKHz, power %lumW for CPU%d.\n", - freq, - power, - current_cpu_id); - if (freq == 0 || power == 0) { - pr_err("Illegal freq/power combination specified: %lu, %lu.\n", - freq, - power); - res = -EINVAL; - break; - } - - update_em_entry(current_cpu_id, freq, power); - } - } - - kfree(profile_dup); - return res; -} - -static ssize_t sysfs_profile_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, - size_t count) -{ - bool parse_successful; - - if (strncasecmp(buf, "default", sizeof("default") - 1) == 0) { - int pd_id; - - mutex_lock(&sysfs_em_pd_lock); - pr_info("Restoring default profile.\n"); - for (pd_id = 0; pd_id < pixel_em_num_cpu_pds; pd_id++) - copy_pd_table(em_pds[pd_id], em_pds_backup[pd_id]); - mutex_unlock(&sysfs_em_pd_lock); - return count; - } - - mutex_lock(&sysfs_em_pd_lock); - parse_successful = parse_profile(buf, count); - mutex_unlock(&sysfs_em_pd_lock); - - return parse_successful ? count : -EINVAL; -} - -static struct kobj_attribute profile_attr = __ATTR(profile, - 0660, - sysfs_profile_show, - sysfs_profile_store); - -static void pixel_em_clean_up_sysfs_nodes(void) -{ - if (!primary_sysfs_folder) - return; - - sysfs_remove_file(primary_sysfs_folder, &profile_attr.attr); - - kobject_put(primary_sysfs_folder); - primary_sysfs_folder = NULL; -} - -static int pixel_em_initialize_sysfs_nodes(void) -{ - if (primary_sysfs_folder) { - pr_err("Sysfs nodes already initialized!"); - return -EINVAL; - } - - primary_sysfs_folder = kobject_create_and_add("pixel_em", kernel_kobj); - if (!primary_sysfs_folder) { - pr_err("Failed to create primary sysfs folder!"); - return -EINVAL; - } - - if (sysfs_create_file(primary_sysfs_folder, &profile_attr.attr)) { - pr_err("Failed to create profile file!\n"); - return -EINVAL; - } - - return 0; -} - -static void pixel_em_drv_undo_probe(void) -{ - // Note: removing/unloading this driver after a successful probe is not expected to ever - // happen (other than debugging). - - pixel_em_clean_up_sysfs_nodes(); - - if (!platform_dev) { - // 'platform_dev' gets set when probing is successful. When that point is reached, - // there is no way to know whether freeing cpu_to_em_pd or em_pds is safe (as - // the pointers may have been shared with other drivers without reference tracking). - // => If platform_dev is NULL, free these pointers (if they're not NULL themselves). - // Otherwise, set them to NULL without freeing. - kfree(cpu_to_em_pd); - - if (em_pds) { - int i; - - for (i = 0; i < pixel_em_num_cpu_pds; i++) { - if (em_pds[i]) - free_pd(em_pds[i]); - } - kfree(em_pds); - } - } - - kfree(em_pd_to_cpu); - em_pd_to_cpu = NULL; - - if (em_pds_backup) { - int i; - - for (i = 0; i < pixel_em_num_cpu_pds; i++) { - if (em_pds_backup[i]) - free_pd(em_pds_backup[i]); - } - kfree(em_pds_backup); - em_pds_backup = NULL; - } - - cpu_to_em_pd = NULL; - em_pds = NULL; - platform_dev = NULL; -} - -static int pixel_em_drv_probe(struct platform_device *dev) -{ - int res; - const char *dt_profile; - - res = pixel_em_init_cpu_layout(); - if (res < 0) { - pixel_em_drv_undo_probe(); - return res; - } - - if (of_property_read_string(dev->dev.of_node, "profile", &dt_profile)) { - pr_info("Could not find EM profile in device tree.\n"); - } else { - int pd_id; - - pr_info("Loading profile from DT.\n"); - parse_profile(dt_profile, strlen(dt_profile)); - - // Override backup values with DT profile. - for (pd_id = 0; pd_id < pixel_em_num_cpu_pds; pd_id++) - copy_pd_table(em_pds_backup[pd_id], em_pds[pd_id]); - } - - res = pixel_em_initialize_sysfs_nodes(); - if (res < 0) { - pixel_em_drv_undo_probe(); - return res; - } - - // Probe is successful => do not attempt to free pixel_em_max_cpu or cpu_to_em_pd. - platform_dev = dev; - - // Register EM table to all needed drivers here. -#if IS_ENABLED(CONFIG_VH_SCHED) - pr_info("Publishing PDs to vh_sched!\n"); - WRITE_ONCE(vendor_sched_cpu_to_em_pd, cpu_to_em_pd); -#endif - -#if IS_ENABLED(CONFIG_EXYNOS_CPU_THERMAL) - pr_info("Publishing PDs to exynos_cpu_cooling!\n"); - WRITE_ONCE(exynos_cpu_cooling_cpu_to_em_pd, cpu_to_em_pd); -#endif - - return res; -} - -static int pixel_em_drv_remove(struct platform_device *dev) -{ - pixel_em_drv_undo_probe(); - - return 0; -} - -static const struct of_device_id pixel_em_of_match[] = { - { - .compatible = "google,pixel-em", - }, - {} -}; - -static struct platform_driver pixel_em_platform_driver = { - .probe = pixel_em_drv_probe, - .remove = pixel_em_drv_remove, - .driver = { - .name = "pixel-em", - .owner = THIS_MODULE, - .of_match_table = pixel_em_of_match, - }, -}; - -static int __init pixel_em_init(void) -{ - mutex_init(&sysfs_em_pd_lock); - if (platform_driver_register(&pixel_em_platform_driver)) - pr_err("Error when registering driver!\n"); - - pr_info("Registered! :D\n"); - - return 0; -} - -static void __exit pixel_em_exit(void) -{ - pixel_em_drv_undo_probe(); - pr_info("Unregistered! :(\n"); -} - -module_init(pixel_em_init); -module_exit(pixel_em_exit); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Vincent Palomares"); -MODULE_DESCRIPTION("Pixel Energy Model Driver"); -MODULE_DEVICE_TABLE(of, pixel_em_of_match); diff --git a/drivers/soc/google/pixel_stat/mm/Makefile b/drivers/soc/google/pixel_stat/mm/Makefile index 3117afeaf8ea..79c23ee63160 100644 --- a/drivers/soc/google/pixel_stat/mm/Makefile +++ b/drivers/soc/google/pixel_stat/mm/Makefile @@ -2,4 +2,4 @@ # vendor hook for mm obj-$(CONFIG_PIXEL_STAT) += pixel_stat_mm.o -pixel_stat_mm-y += init.o page_alloc.o sysfs_node.o filemap.o cma.o meminfo.o vmscan.o +pixel_stat_mm-y += init.o page_alloc.o sysfs_node.o filemap.o cma.o meminfo.o vmscan.o compaction.o diff --git a/drivers/soc/google/pixel_stat/mm/compaction.c b/drivers/soc/google/pixel_stat/mm/compaction.c new file mode 100644 index 000000000000..71176b703f47 --- /dev/null +++ b/drivers/soc/google/pixel_stat/mm/compaction.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* compaction.c + * + * Android Vendor Hook Support + * + * Copyright 2021 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../../vh/include/sched.h" +#include "compaction.h" + +#define COMPACTION_ATTR_RW(_name) \ + static struct kobj_attribute _name##_attr = __ATTR_RW(_name) +#define COMPACTION_ATTR_RO(_name) \ + static struct kobj_attribute _name##_attr = __ATTR_RO(_name) +#define ATTR_ATTR(_name) (&_name##_attr.attr) + +#define COMPACTION_BUCKETS 5 /* at least 2 */ +#define THRESHOLD_CNT (COMPACTION_BUCKETS - 1) + +#ifdef CONFIG_COMPACTION +struct compaction_pixel_stat { + spinlock_t lock; + unsigned long thresholds[THRESHOLD_CNT]; + unsigned long count[COMPACTION_BUCKETS]; + unsigned long total_count; + unsigned long total_time; + struct kobject kobj; +}; +static struct compaction_pixel_stat stat = { + .thresholds = {5, 50, 100, 500} +}; + +/********** vendor hooks *****************************/ +void vh_compaction_begin(__always_unused void *data, + __always_unused struct compact_control *cc, long *ts) +{ + *ts = (long)jiffies; +} + +void vh_compaction_end(__always_unused void *data, + __always_unused struct compact_control *cc, long ts) +{ + int delta; + int i; + + delta = jiffies_to_msecs(jiffies - ts); + WARN_ON_ONCE(delta < 0); + if (delta < 0) + return; + + spin_lock(&stat.lock); + stat.total_count++; + stat.total_time += delta; + for (i = 0; i < THRESHOLD_CNT; i++) { + if (delta < stat.thresholds[i]) + break; + } + stat.count[i]++; + spin_unlock(&stat.lock); +} + +/********** sysfs *****************************/ +static ssize_t mm_compaction_duration_threshold_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + int n; + + spin_lock(&stat.lock); + n = sysfs_emit(buf, "%lu %lu %lu %lu\n", + stat.thresholds[0], + stat.thresholds[1], + stat.thresholds[2], + stat.thresholds[3]); + spin_unlock(&stat.lock); + return n; +} + +static ssize_t mm_compaction_duration_threshold_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t len) +{ + int n; + unsigned long th[THRESHOLD_CNT]; + + n = sscanf(buf, "%lu %lu %lu %lu", + &th[0], &th[1], &th[2], &th[3]); + if (n != THRESHOLD_CNT) { + pr_info("Error: Input expect %d args but got %d.\n", THRESHOLD_CNT, n); + return -EINVAL; + } + for (n = 1; n < THRESHOLD_CNT; n++) { + if (th[n-1] >= th[n]) { + pr_info("Error: Input numbers must be ascending.\n"); + return -EINVAL; + } + } + + spin_lock(&stat.lock); + memcpy(stat.thresholds, th, sizeof(th)); + spin_unlock(&stat.lock); + + return len; +} +COMPACTION_ATTR_RW(mm_compaction_duration_threshold); + +static ssize_t mm_compaction_duration_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + int n; + + spin_lock(&stat.lock); + n = sysfs_emit(buf, "%ld %ld %lu %lu %lu %lu %lu\n", + stat.total_count, + stat.total_time, + stat.count[0], + stat.count[1], + stat.count[2], + stat.count[3], + stat.count[4]); + spin_unlock(&stat.lock); + return n; +} +COMPACTION_ATTR_RO(mm_compaction_duration); + +static struct attribute *mm_compaction_attrs[] = { + ATTR_ATTR(mm_compaction_duration_threshold), + ATTR_ATTR(mm_compaction_duration), + NULL, +}; +ATTRIBUTE_GROUPS(mm_compaction); + +static struct kobj_type compaction_ktype = { + .release = NULL, + .sysfs_ops = &kobj_sysfs_ops, + .default_groups = mm_compaction_groups, +}; + +void remove_compaction_sysfs(void) +{ + kobject_put(&stat.kobj); +} + +int compaction_sysfs(struct kobject *parent) +{ + int ret; + + ret = kobject_init_and_add(&stat.kobj, &compaction_ktype, parent, "compaction"); + if (ret) { + remove_compaction_sysfs(); + return ret; + } + return ret; +} + +#endif /* CONFIG_COMPACTION */ diff --git a/drivers/soc/google/pixel_stat/mm/compaction.h b/drivers/soc/google/pixel_stat/mm/compaction.h new file mode 100644 index 000000000000..5e3e44ddd0c3 --- /dev/null +++ b/drivers/soc/google/pixel_stat/mm/compaction.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __MM_PIXEL_COMPACTION_H_ +#define __MM_PIXEL_COMPACTION_H_ + +struct compact_control; + +int compaction_sysfs(struct kobject *parent); +void remove_compaction_sysfs(void); + +void vh_compaction_begin(void *, struct compact_control *, long *ts); +void vh_compaction_end(void *, struct compact_control *, long ts); + +#endif diff --git a/drivers/soc/google/pixel_stat/mm/init.c b/drivers/soc/google/pixel_stat/mm/init.c index 3afcd09b667c..037200a86250 100644 --- a/drivers/soc/google/pixel_stat/mm/init.c +++ b/drivers/soc/google/pixel_stat/mm/init.c @@ -11,6 +11,7 @@ #include "cma.h" #include "meminfo.h" #include "vmscan.h" +#include "compaction.h" extern void vh_rmqueue_mod(void *data, struct zone *preferred_zone, struct zone *zone, unsigned int order, gfp_t gfp_flags, @@ -24,6 +25,10 @@ static int pixel_stat_mm_init(void) { int ret; + ret = pixel_mm_sysfs(); + if (ret) + return ret; + ret = register_trace_android_vh_rmqueue(vh_rmqueue_mod, NULL); if (ret) return ret; @@ -51,7 +56,12 @@ static int pixel_stat_mm_init(void) if (ret) return ret; - ret = pixel_mm_sysfs(); + ret = register_trace_android_vh_mm_compaction_begin(vh_compaction_begin, + NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_mm_compaction_end(vh_compaction_end, NULL); if (ret) return ret; diff --git a/drivers/soc/google/pixel_stat/mm/sysfs_node.c b/drivers/soc/google/pixel_stat/mm/sysfs_node.c index a50e79c4db82..d6698687dc92 100644 --- a/drivers/soc/google/pixel_stat/mm/sysfs_node.c +++ b/drivers/soc/google/pixel_stat/mm/sysfs_node.c @@ -11,6 +11,7 @@ #include #include "cma.h" #include "vmscan.h" +#include "compaction.h" DEFINE_PER_CPU(unsigned long, pgalloc_costly_order); DEFINE_PER_CPU(unsigned long, pgcache_miss); @@ -72,7 +73,16 @@ int pixel_mm_sysfs(void) if (ret) goto remove_vmscan_sysfs; +#ifdef CONFIG_COMPACTION + ret = compaction_sysfs(pixel_stat_mm_kobj); + if (ret) + goto remove_cma_sysfs; +#endif + return ret; + +remove_cma_sysfs: + remove_cma_sysfs(); remove_vmscan_sysfs: remove_vmscan_sysfs(); remove_stat_sysfs: diff --git a/drivers/soc/google/pkvm-s2mpu.c b/drivers/soc/google/pkvm-s2mpu.c new file mode 100644 index 000000000000..4d1f5237f306 --- /dev/null +++ b/drivers/soc/google/pkvm-s2mpu.c @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 - Google LLC + * Author: David Brazdil + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#define S2MPU_NR_WAYS 4 + +struct s2mpu_data { + struct device *dev; + void __iomem *base; + bool pkvm_registered; + bool always_on; +}; + +struct s2mpu_mptc_entry { + bool valid; + u32 vid; + u32 ppn; + u32 others; + u32 data; +}; + +static const struct of_device_id sysmmu_sync_of_match[]; + +static int nr_devs_total; +static atomic_t nr_devs_registered = ATOMIC_INIT(0); + +static struct platform_device *__of_get_phandle_pdev(struct device *parent, + const char *prop, int index) +{ + struct device_node *np; + struct platform_device *pdev; + + np = of_parse_phandle(parent->of_node, prop, index); + if (!np) + return NULL; + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return ERR_PTR(-EINVAL); + + return pdev; +} + +int pkvm_s2mpu_of_link(struct device *parent) +{ + struct platform_device *pdev; + struct device_link *link; + int i; + + /* Check that all S2MPUs have been initialized. */ + for (i = 0; (pdev = __of_get_phandle_pdev(parent, "s2mpus", i)); i++) { + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + if (!pkvm_s2mpu_ready(&pdev->dev)) + return -EAGAIN; + } + + /* Link all S2MPUs as suppliers to the parent. */ + for (i = 0; (pdev = __of_get_phandle_pdev(parent, "s2mpus", i)); i++) { + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + link = device_link_add(/*consumer=*/parent, /*supplier=*/&pdev->dev, + DL_FLAG_AUTOREMOVE_CONSUMER | DL_FLAG_PM_RUNTIME); + if (!link) + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(pkvm_s2mpu_of_link); + +struct device *pkvm_s2mpu_of_parse(struct device *parent) +{ + struct platform_device *pdev; + + pdev = __of_get_phandle_pdev(parent, "s2mpu", 0); + if (IS_ERR_OR_NULL(pdev)) + return ERR_PTR(PTR_ERR(pdev)); + + return &pdev->dev; +} +EXPORT_SYMBOL_GPL(pkvm_s2mpu_of_parse); + +static const char *str_fault_direction(u32 fault_info) +{ + return (fault_info & FAULT_INFO_RW_BIT) ? "write" : "read"; +} + +static const char *str_fault_type(u32 fault_info) +{ + switch (FIELD_GET(FAULT_INFO_TYPE_MASK, fault_info)) { + case FAULT_INFO_TYPE_MPTW: + return "MPTW fault"; + case FAULT_INFO_TYPE_AP: + return "access permission fault"; + case FAULT_INFO_TYPE_CONTEXT: + return "context fault"; + default: + return "unknown fault"; + } +} + +static const char *str_l1entry_gran(u32 l1attr) +{ + if (!(l1attr & L1ENTRY_ATTR_L2TABLE_EN)) + return "1G"; + + switch (FIELD_GET(L1ENTRY_ATTR_GRAN_MASK, l1attr)) { + case L1ENTRY_ATTR_GRAN_4K: + return "4K"; + case L1ENTRY_ATTR_GRAN_64K: + return "64K"; + case L1ENTRY_ATTR_GRAN_2M: + return "2M"; + default: + return "invalid"; + } +} + +static const char *str_l1entry_prot(u32 l1attr) +{ + if (l1attr & L1ENTRY_ATTR_L2TABLE_EN) + return "??"; + + switch (FIELD_GET(L1ENTRY_ATTR_PROT_MASK, l1attr)) { + case MPT_PROT_NONE: + return "0"; + case MPT_PROT_R: + return "R"; + case MPT_PROT_W: + return "W"; + case MPT_PROT_RW: + return "RW"; + default: + return "invalid"; + } +} + +static struct s2mpu_mptc_entry read_mptc(void __iomem *base, u32 set, u32 way) +{ + struct s2mpu_mptc_entry entry; + + writel_relaxed(READ_MPTC(set, way), base + REG_NS_READ_MPTC); + + entry.ppn = readl_relaxed(base + REG_NS_READ_MPTC_TAG_PPN), + entry.others = readl_relaxed(base + REG_NS_READ_MPTC_TAG_OTHERS), + entry.data = readl_relaxed(base + REG_NS_READ_MPTC_DATA), + + entry.valid = FIELD_GET(READ_MPTC_TAG_OTHERS_VALID_BIT, entry.others); + entry.vid = FIELD_GET(READ_MPTC_TAG_OTHERS_VID_MASK, entry.others); + return entry; +} + +static irqreturn_t s2mpu_irq_handler(int irq, void *ptr) +{ + struct s2mpu_data *data = ptr; + struct device *dev = data->dev; + unsigned int vid, gb; + u32 vid_bmap, fault_info, fmpt, smpt, nr_sets, set, way, invalid; + phys_addr_t fault_pa; + struct s2mpu_mptc_entry mptc; + irqreturn_t ret = IRQ_NONE; + + while ((vid_bmap = readl_relaxed(data->base + REG_NS_FAULT_STATUS))) { + WARN_ON_ONCE(vid_bmap & (~ALL_VIDS_BITMAP)); + vid = __ffs(vid_bmap); + + fault_pa = hi_lo_readq_relaxed(data->base + REG_NS_FAULT_PA_HIGH_LOW(vid)); + fault_info = readl_relaxed(data->base + REG_NS_FAULT_INFO(vid)); + WARN_ON(FIELD_GET(FAULT_INFO_VID_MASK, fault_info) != vid); + + dev_err(dev, "============== S2MPU FAULT DETECTED ==============\n"); + dev_err(dev, " PA=%pap, FAULT_INFO=0x%08x\n", + &fault_pa, fault_info); + dev_err(dev, " DIRECTION: %s, TYPE: %s\n", + str_fault_direction(fault_info), + str_fault_type(fault_info)); + dev_err(dev, " VID=%u, REQ_LENGTH=%lu, REQ_AXI_ID=%lu\n", + vid, + FIELD_GET(FAULT_INFO_LEN_MASK, fault_info), + FIELD_GET(FAULT_INFO_ID_MASK, fault_info)); + + for_each_gb(gb) { + fmpt = readl_relaxed(data->base + REG_NS_L1ENTRY_ATTR(vid, gb)); + smpt = readl_relaxed(data->base + REG_NS_L1ENTRY_L2TABLE_ADDR(vid, gb)); + dev_err(dev, " %uG: FMPT=%#x (%s, %s), SMPT=%#x\n", + gb, fmpt, str_l1entry_gran(fmpt), + str_l1entry_prot(fmpt), smpt); + } + + dev_err(dev, "==================================================\n"); + + writel_relaxed(BIT(vid), data->base + REG_NS_INTERRUPT_CLEAR); + ret = IRQ_HANDLED; + } + + dev_err(dev, "================== MPTC ENTRIES ==================\n"); + nr_sets = FIELD_GET(INFO_NUM_SET_MASK, readl_relaxed(data->base + REG_NS_INFO)); + for (invalid = 0, set = 0; set < nr_sets; set++) { + for (way = 0; way < S2MPU_NR_WAYS; way++) { + mptc = read_mptc(data->base, set, way); + if (!mptc.valid) { + invalid++; + continue; + } + + dev_err(dev, + " MPTC[set=%u, way=%u]={VID=%u, PPN=%#x, OTHERS=%#x, DATA=%#x}\n", + set, way, mptc.vid, mptc.ppn, mptc.others, mptc.data); + } + } + dev_err(dev, " invalid entries: %u\n", invalid); + dev_err(dev, "==================================================\n"); + + return ret; +} + +/* + * Parse interrupt information from DT and if found, register IRQ handler. + * This is considered optional and will not fail even if the initialization is + * unsuccessful. In that case the IRQ will remain masked. + */ +static void s2mpu_probe_irq(struct platform_device *pdev, struct s2mpu_data *data) +{ + int ret, irq; + + irq = platform_get_irq_optional(pdev, 0); + + if (irq == -ENXIO) + return; /* No IRQ specified. */ + + if (irq < 0) { + /* IRQ specified but failed to parse. */ + dev_err(data->dev, "failed to parse IRQ, IRQ not enabled"); + return; + } + + ret = devm_request_irq(data->dev, irq, s2mpu_irq_handler, 0, + dev_name(data->dev), data); + if (ret) { + dev_err(&pdev->dev, "failed to register IRQ, IRQ not enabled"); + return; + } +} + +static struct s2mpu_data *s2mpu_dev_data(struct device *dev) +{ + return platform_get_drvdata(to_platform_device(dev)); +} + +int pkvm_s2mpu_suspend(struct device *dev) +{ + struct s2mpu_data *data = s2mpu_dev_data(dev); + + if (data->pkvm_registered && !data->always_on) + return pkvm_iommu_suspend(dev); + + return 0; +} +EXPORT_SYMBOL_GPL(pkvm_s2mpu_suspend); + +int pkvm_s2mpu_resume(struct device *dev) +{ + struct s2mpu_data *data = s2mpu_dev_data(dev); + + if (data->pkvm_registered) + return pkvm_iommu_resume(dev); + + writel_relaxed(0, data->base + REG_NS_CTRL0); + return 0; +} +EXPORT_SYMBOL_GPL(pkvm_s2mpu_resume); + +static int s2mpu_late_suspend(struct device *dev) +{ + struct s2mpu_data *data = s2mpu_dev_data(dev); + + /* + * Some always-on S2MPUs need to allow traffic while the CPU is asleep. + * Do not call pkvm_iommu_suspend() here because that would put them + * in a blocking state. + */ + if (data->always_on || pm_runtime_status_suspended(dev)) + return 0; + + dev->power.must_resume = true; + return pkvm_s2mpu_suspend(dev); +} + +static int s2mpu_late_resume(struct device *dev) +{ + /* + * Some always-on S2MPUs reset while the CPU is asleep. Call + * pkvm_iommu_resume() here regardless of always-on to reconfigure them. + */ + + if (pm_runtime_status_suspended(dev)) + return 0; + + return pkvm_s2mpu_resume(dev); +} + +static int sysmmu_sync_probe(struct device *parent) +{ + struct platform_device *pdev; + struct resource *res; + int i, ret; + + for (i = 0; (pdev = __of_get_phandle_pdev(parent, "sysmmu_syncs", i)); i++) { + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + if (!of_match_device(sysmmu_sync_of_match, &pdev->dev)) { + dev_err(parent, "%s is not sysmmu_sync compatible", + dev_name(&pdev->dev)); + return -EINVAL; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to parse 'reg'"); + return -EINVAL; + } + + if (!devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), + dev_name(&pdev->dev))) { + dev_err(&pdev->dev, "failed to request mmio region"); + return -EINVAL; + } + + ret = pkvm_iommu_sysmmu_sync_register(&pdev->dev, res->start, + parent); + if (ret) { + dev_err(&pdev->dev, "could not register: %d\n", ret); + return ret; + } + } + + return 0; +} + +static int s2mpu_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + struct resource *res; + struct s2mpu_data *data; + bool off_at_boot, has_pd; + int ret, nr_devs; + + data = devm_kmalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + data->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "failed to parse 'reg'"); + return -EINVAL; + } + + /* devm_ioremap_resource internally calls devm_request_mem_region. */ + data->base = devm_ioremap_resource(dev, res); + if (IS_ERR(data->base)) { + dev_err(dev, "could not ioremap resource: %ld", PTR_ERR(data->base)); + return PTR_ERR(data->base); + } + + data->always_on = !!of_get_property(np, "always-on", NULL); + off_at_boot = !!of_get_property(np, "off-at-boot", NULL); + has_pd = !!of_get_property(np, "power-domains", NULL); + + /* + * Try to parse IRQ information. This is optional as it only affects + * runtime fault reporting, and therefore errors do not fail the whole + * driver initialization. + */ + s2mpu_probe_irq(pdev, data); + + ret = pkvm_iommu_s2mpu_register(dev, res->start); + if (ret && ret != -ENODEV) { + dev_err(dev, "could not register: %d\n", ret); + return ret; + } + + data->pkvm_registered = ret != -ENODEV; + + if (data->pkvm_registered) { + ret = sysmmu_sync_probe(dev); + if (ret) + return ret; + } + + platform_set_drvdata(pdev, data); + nr_devs = atomic_inc_return(&nr_devs_registered); + + if (data->pkvm_registered) + dev_info(dev, "registered with hypervisor [%d/%d]\n", nr_devs, nr_devs_total); + else + dev_warn(dev, "hypervisor disabled, control from kernel\n"); + + if (data->pkvm_registered && nr_devs == nr_devs_total) { + ret = pkvm_iommu_finalize(); + if (!ret) + pr_info("list of devices successfully finalized\n"); + else + pr_err("could not finalize: %d\n", ret); + } + + /* + * Most S2MPUs are in an allow-all state at boot. Call the hypervisor + * to initialize the S2MPU to a blocking state. This corresponds to + * the state the hypervisor sets on suspend. + */ + if (!off_at_boot) + WARN_ON(pkvm_s2mpu_suspend(dev)); + + if (has_pd || data->always_on) + pm_runtime_enable(dev); + if (data->always_on) + pm_runtime_get_sync(dev); + + return 0; +} + +static const struct dev_pm_ops s2mpu_pm_ops = { + SET_RUNTIME_PM_OPS(pkvm_s2mpu_suspend, pkvm_s2mpu_resume, NULL) + SET_LATE_SYSTEM_SLEEP_PM_OPS(s2mpu_late_suspend, s2mpu_late_resume) +}; + +static const struct of_device_id sysmmu_sync_of_match[] = { + { .compatible = "google,sysmmu_sync" }, + {}, +}; + +static const struct of_device_id s2mpu_of_match[] = { + { .compatible = "google,s2mpu" }, + {}, +}; + +static struct platform_driver s2mpu_driver = { + .probe = s2mpu_probe, + .driver = { + .name = "pkvm-s2mpu", + .of_match_table = s2mpu_of_match, + .pm = &s2mpu_pm_ops, + }, +}; + +static int s2mpu_driver_register(struct platform_driver *driver) +{ + struct device_node *np; + + for_each_matching_node(np, driver->driver.of_match_table) + if (of_device_is_available(np)) + nr_devs_total++; + pr_info("%d devices to be initialized\n", nr_devs_total); + + return platform_driver_register(driver); +} + +module_driver(s2mpu_driver, s2mpu_driver_register, platform_driver_unregister); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("David Brazdil "); diff --git a/drivers/soc/google/s2mpu/Kconfig b/drivers/soc/google/s2mpu/Kconfig index e3392e66f447..972b41a02791 100644 --- a/drivers/soc/google/s2mpu/Kconfig +++ b/drivers/soc/google/s2mpu/Kconfig @@ -1,4 +1,4 @@ config GS_S2MPU tristate "S2MPU driver" depends on ARM64 - depends on SOC_GS101 + depends on SOC_GS101 || SOC_GS201 diff --git a/drivers/soc/google/vh/include/buffer.h b/drivers/soc/google/vh/include/buffer.h new file mode 100644 index 000000000000..97ba458007ea --- /dev/null +++ b/drivers/soc/google/vh/include/buffer.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _VH_BUFFER_H +#define _VH_BUFFER_H +#include + +void vh_bh_lru_install(void *data, struct page *page, bool *skip); + +#endif diff --git a/drivers/soc/google/vh/include/mm.h b/drivers/soc/google/vh/include/mm.h new file mode 100644 index 000000000000..8a7ef68dda98 --- /dev/null +++ b/drivers/soc/google/vh/include/mm.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _VH_MM_H +#define _VH_MM_H +#include + +void vh_do_madvise_blk_plug(void *data, int behavior, bool *do_plug); +void vh_shrink_inactive_list_blk_plug(void *data, bool *do_plug); +void vh_shrink_lruvec_blk_plug(void *data, bool *do_plug); +void vh_reclaim_pages_plug(void *data, bool *do_plug); +void vh_pagevec_drain(void *data, struct page *page, bool *ret); +void vh_zap_pte_range_tlb_start(void *data, void *preempt_off); +void vh_zap_pte_range_tlb_force_flush(void *data, struct page *page, bool *flush); +void vh_zap_pte_range_tlb_end(void *data, void *preempt_off); +void vh_skip_lru_disable(void *data, bool *skip); + +#endif diff --git a/drivers/soc/google/vh/include/pixel_em.h b/drivers/soc/google/vh/include/pixel_em.h new file mode 100644 index 000000000000..516408ec0288 --- /dev/null +++ b/drivers/soc/google/vh/include/pixel_em.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Pixel Energy Model (EM). + * + * Copyright (C) 2022 Google, Inc. + */ + +#ifndef __PIXEL_EM_H__ +#define __PIXEL_EM_H__ + +#if IS_ENABLED(CONFIG_PIXEL_EM) + +struct pixel_em_opp { + unsigned int freq; + unsigned int capacity; + unsigned int power; + unsigned long cost; +}; + +struct pixel_em_cluster { + cpumask_t cpus; + int num_opps; + struct pixel_em_opp *opps; +}; + +struct pixel_em_profile { + struct list_head list; + struct profile_sysfs_helper *sysfs_helper; + const char *name; + int num_clusters; + struct pixel_em_cluster *clusters; + int num_cpus; + struct pixel_em_cluster **cpu_to_cluster; // Maps CPU index to a cluster pointer +}; + +#endif /* CONFIG_PIXEL_EM */ + +#endif /* __PIXEL_EM_H__ */ diff --git a/drivers/soc/google/vh/kernel/Kconfig b/drivers/soc/google/vh/kernel/Kconfig index b01d59e3d0b0..ce7a9bedb468 100644 --- a/drivers/soc/google/vh/kernel/Kconfig +++ b/drivers/soc/google/vh/kernel/Kconfig @@ -45,6 +45,18 @@ config VH_SYSTRACE If in doubt, say N. +config PIXEL_EM + tristate "Enable Pixel Energy Model driver" + depends on VH_KERNEL + default m + help + Support Pixel Energy Model. + +config PERF_METRICS + tristate "Enable PERF METRICS driver" + depends on VH_KERNEL + default m + config VH_THERMAL tristate "Vendor hooks for kernel thermal" depends on VH_KERNEL diff --git a/drivers/soc/google/vh/kernel/Makefile b/drivers/soc/google/vh/kernel/Makefile index fda3b36fc718..0b1b80528831 100644 --- a/drivers/soc/google/vh/kernel/Makefile +++ b/drivers/soc/google/vh/kernel/Makefile @@ -20,3 +20,9 @@ obj-$(CONFIG_VH_CGROUP) += cgroup/ # vh/kernel/i2c obj-$(CONFIG_VH_I2C) += i2c/ + +# vh/kernel/pixel_em +obj-$(CONFIG_PIXEL_EM) += pixel_em/ + +# metrics +obj-$(CONFIG_PERF_METRICS) += metrics.o diff --git a/drivers/soc/google/vh/kernel/metrics.c b/drivers/soc/google/vh/kernel/metrics.c new file mode 100644 index 000000000000..5bae61f5c5ad --- /dev/null +++ b/drivers/soc/google/vh/kernel/metrics.c @@ -0,0 +1,412 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* metrics.c + * + * Support for Perf metrics + * + * Copyright 2022 Google LLC + */ +#define pr_fmt(fmt) KBUILD_MODNAME": " fmt +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + + +#include +#include +#include "metrics.h" + +static struct resume_latency resume_latency_stats; +static struct long_irq long_irq_stat; +static struct kobject *primary_sysfs_folder; + +/********************************************************************* + * SYSTEM TRACE + *********************************************************************/ + +static void vendor_hook_resume_begin(void *data, void *unused) +{ + resume_latency_stats.resume_start = ktime_get(); +} + +static void vendor_hook_resume_end(void *data, void *unused) +{ + int resume_latency_index; + s64 resume_latency_msec; + /* Exit function when partial resumes */ + if (resume_latency_stats.resume_start == resume_latency_stats.resume_end) + return; + resume_latency_stats.resume_end = ktime_get(); + resume_latency_msec = ktime_ms_delta(resume_latency_stats.resume_end, + resume_latency_stats.resume_start); + pr_info("resume latency: %lld\n", resume_latency_msec); + /* Exit function when partial resumes */ + if (resume_latency_msec <= 0) + return; + spin_lock(&resume_latency_stats.resume_latency_stat_lock); + if (resume_latency_msec < RESUME_LATENCY_BOUND_SMALL) { + resume_latency_index = resume_latency_msec / RESUME_LATENCY_STEP_SMALL; + } else if (resume_latency_msec < RESUME_LATENCY_BOUND_MID) { + resume_latency_index = (resume_latency_msec - RESUME_LATENCY_BOUND_SMALL) / + RESUME_LATENCY_STEP_MID + LATENCY_CNT_SMALL; + } else if (resume_latency_msec < RESUME_LATENCY_BOUND_MAX) { + resume_latency_index = (resume_latency_msec - RESUME_LATENCY_BOUND_MID) / + RESUME_LATENCY_STEP_LARGE + LATENCY_CNT_SMALL + + LATENCY_CNT_MID; + } else { + resume_latency_index = LATENCY_CNT_SMALL + LATENCY_CNT_MID + LATENCY_CNT_LARGE; + } + resume_latency_stats.resume_count[resume_latency_index]++; + resume_latency_stats.resume_latency_sum_ms += resume_latency_msec; + resume_latency_stats.resume_latency_max_ms = max(resume_latency_stats.resume_latency_max_ms, + resume_latency_msec); + spin_unlock(&resume_latency_stats.resume_latency_stat_lock); + resume_latency_stats.resume_start = resume_latency_stats.resume_end; +} + +static void hook_softirq_begin(void *data, unsigned int vec_nr) +{ + int cpu_num; + cpu_num = raw_smp_processor_id(); + long_irq_stat.softirq_start[cpu_num][vec_nr] = ktime_get(); +} + +static void hook_softirq_end(void *data, unsigned int vec_nr) +{ + s64 irq_usec; + int cpu_num; + s64 curr_max_irq; + if (vec_nr >= NR_SOFTIRQS) + return; + cpu_num = raw_smp_processor_id(); + long_irq_stat.softirq_end = ktime_get(); + irq_usec = ktime_to_us(ktime_sub(long_irq_stat.softirq_end, + long_irq_stat.softirq_start[cpu_num][vec_nr])); + if (irq_usec >= long_irq_stat.long_softirq_threshold) { + if (long_irq_stat.display_warning) + WARN("%s","Got a long running irq: softirq\n"); + atomic64_inc(&(long_irq_stat.long_softirq_count)); + } + do { + curr_max_irq = long_irq_stat.long_softirq_arr[vec_nr]; + if (irq_usec < curr_max_irq) + return; + } while (cmpxchg64(&long_irq_stat.long_softirq_arr[vec_nr], + curr_max_irq, irq_usec) != curr_max_irq); +} + +static void hook_irq_begin(void *data, int irq, struct irqaction *action) +{ + int cpu_num; + cpu_num = raw_smp_processor_id(); + long_irq_stat.irq_start[cpu_num][irq] = ktime_get(); +} + +static void hook_irq_end(void *data, int irq, struct irqaction *action, int ret) +{ + s64 irq_usec; + int cpu_num; + s64 curr_max_irq; + if (irq >= MAX_IRQ_NUM) + return; + cpu_num = raw_smp_processor_id(); + long_irq_stat.irq_end = ktime_get(); + irq_usec = ktime_to_us(ktime_sub(long_irq_stat.irq_end, + long_irq_stat.irq_start[cpu_num][irq])); + if (irq_usec >= long_irq_stat.long_irq_threshold) { + if (long_irq_stat.display_warning) + WARN("%s","Got a long running irq: irq_handler\n"); + atomic64_inc(&(long_irq_stat.long_irq_count)); + } + do { + curr_max_irq = long_irq_stat.long_irq_arr[irq]; + if (irq_usec < curr_max_irq) + break; + } while (cmpxchg64(&long_irq_stat.long_irq_arr[irq], + curr_max_irq, irq_usec) != curr_max_irq); +} +/******************************************************************* + * SYSFS * + *******************************************************************/ + +static ssize_t resume_latency_metrics_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + s64 lower_bound; + s64 upper_bound; + int index; + ssize_t count = 0; + count += sysfs_emit_at(buf, count, "Resume Latency Bucket Count: %d\n", + RESUME_LATENCY_ARR_SIZE); + count += sysfs_emit_at(buf, count, "Max Resume Latency: %lld\n", + resume_latency_stats.resume_latency_max_ms); + count += sysfs_emit_at(buf, count, "Sum Resume Latency: %llu\n", + resume_latency_stats.resume_latency_sum_ms); + for (index = 0; index < RESUME_LATENCY_ARR_SIZE; index++) { + if (index < LATENCY_CNT_SMALL) { + lower_bound = index * RESUME_LATENCY_STEP_SMALL; + upper_bound = lower_bound + RESUME_LATENCY_STEP_SMALL; + count += sysfs_emit_at(buf, count, "%lld - %lldms ====> %lld\n", + lower_bound, upper_bound, + resume_latency_stats.resume_count[index]); + } else if (index < LATENCY_CNT_SMALL + LATENCY_CNT_MID) { + lower_bound = RESUME_LATENCY_BOUND_SMALL + RESUME_LATENCY_STEP_MID * + (index - LATENCY_CNT_SMALL); + upper_bound = lower_bound + RESUME_LATENCY_STEP_MID; + count += sysfs_emit_at(buf, count, "%lld - %lldms ====> %lld\n", + lower_bound, upper_bound, + resume_latency_stats.resume_count[index]); + } else if (index < LATENCY_CNT_SMALL + LATENCY_CNT_MID + LATENCY_CNT_LARGE) { + lower_bound = RESUME_LATENCY_BOUND_MID + RESUME_LATENCY_STEP_LARGE * + (index - (LATENCY_CNT_SMALL + LATENCY_CNT_MID)); + upper_bound = lower_bound + RESUME_LATENCY_STEP_LARGE; + count += sysfs_emit_at(buf, count, "%lld - %lldms ====> %lld\n", + lower_bound, upper_bound, + resume_latency_stats.resume_count[index]); + } else { + lower_bound = RESUME_LATENCY_BOUND_MAX; + count += sysfs_emit_at(buf, count, "%lld - infms ====> %lld\n", + lower_bound, + resume_latency_stats.resume_count[index]); + } + } + return count; +} + +static ssize_t resume_latency_metrics_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + spin_lock(&resume_latency_stats.resume_latency_stat_lock); + resume_latency_stats.resume_latency_max_ms = 0; + resume_latency_stats.resume_latency_sum_ms = 0; + memset(resume_latency_stats.resume_count, 0, RESUME_LATENCY_ARR_SIZE * + sizeof(resume_latency_stats.resume_count[0])); + spin_unlock(&resume_latency_stats.resume_latency_stat_lock); + return count; +} +static ssize_t long_irq_metrics_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + ssize_t count = 0; + int index; + s64 latency; + int irq_num; + count += sysfs_emit_at(buf, count, "Long running SOFTIRQ count: %lld\n", + atomic64_read(&(long_irq_stat.long_softirq_count))); + for (index = 0; index < NR_SOFTIRQS; index++) { + latency = long_irq_stat.long_softirq_arr[index]; + irq_num = index; + count += sysfs_emit_at(buf, count, + "long SOFTIRQ latency: %lld, long SOFTIRQ num: %d\n", latency, irq_num); + } + count += sysfs_emit_at(buf, count, "Long running IRQ count: %lld\n", + atomic64_read(&(long_irq_stat.long_irq_count))); + for (index = 0; index < MAX_IRQ_NUM; index++) { + latency = long_irq_stat.long_irq_arr[index]; + irq_num = index; + count += sysfs_emit_at(buf, count, + "long IRQ latency: %lld, long IRQ num: %d\n", latency, irq_num); + } + return count; +} + +static ssize_t modify_softirq_threshold_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + ssize_t count = 0; + count += sysfs_emit_at(buf, count,"%lld\n", long_irq_stat.long_softirq_threshold); + return count; +} + +static ssize_t modify_softirq_threshold_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + s64 new_threshold_us; + int err = sscanf (buf, "%lld", &new_threshold_us); + if (!err || new_threshold_us < 0) { + return count; + } + long_irq_stat.long_softirq_threshold = new_threshold_us; + atomic64_set(&(long_irq_stat.long_softirq_count), 0); + return count; +} + +static ssize_t modify_irq_threshold_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + ssize_t count = 0; + count += sysfs_emit_at(buf, count,"%lld\n", long_irq_stat.long_irq_threshold); + return count; +} + +static ssize_t modify_irq_threshold_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + s64 new_threshold_us; + int err = sscanf (buf, "%lld", &new_threshold_us); + if (!err || new_threshold_us < 0) { + return count; + } + long_irq_stat.long_irq_threshold = new_threshold_us; + atomic64_set(&(long_irq_stat.long_irq_count), 0); + return count; +} + +static ssize_t display_warning_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + ssize_t count = 0; + if (long_irq_stat.display_warning) { + count += sysfs_emit_at(buf, count,"%s", + "WARN is turned on\n"); + } else { + count += sysfs_emit_at(buf, count,"%s", + "WARN is turned off\n"); + } + return count; +} + +static ssize_t display_warning_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + int display_warn; + int err = sscanf (buf, "%d", &display_warn); + if (!err) { + return count; + } + if (display_warn == 0) { + long_irq_stat.display_warning = false; + } + if (display_warn == 1) { + long_irq_stat.display_warning = true; + } + return count; +} + +static struct kobj_attribute resume_latency_metrics_attr = __ATTR(resume_latency_metrics, + 0664, + resume_latency_metrics_show, + resume_latency_metrics_store); +static struct kobj_attribute long_irq_metrics_attr = __ATTR(long_irq_metrics, + 0444, + long_irq_metrics_show, + NULL); +static struct kobj_attribute modify_softirq_threshold_attr = __ATTR(modify_softirq_threshold, + 0664, + modify_softirq_threshold_show, + modify_softirq_threshold_store); +static struct kobj_attribute modify_irq_threshold_attr = __ATTR(modify_irq_threshold, + 0664, + modify_irq_threshold_show, + modify_irq_threshold_store); +static struct kobj_attribute display_warning_attr = __ATTR(display_warning, + 0664, + display_warning_show, + display_warning_store); + +static struct attribute *irq_attrs[] = { + &long_irq_metrics_attr.attr, + &modify_softirq_threshold_attr.attr, + &modify_irq_threshold_attr.attr, + &display_warning_attr.attr, + NULL +}; + +static const struct attribute_group irq_attr_group = { + .attrs = irq_attrs, + .name = "irq" +}; + +static struct attribute *resume_latency_attrs[] = { + &resume_latency_metrics_attr.attr, + NULL +}; + +static const struct attribute_group resume_latency_attr_group = { + .attrs = resume_latency_attrs, + .name = "resume_latency" +}; + +/********************************************************************* + * INITIALIZE DRIVER * + *********************************************************************/ + +static int __init perf_metrics_init(void) +{ + int ret = 0; + primary_sysfs_folder = kobject_create_and_add("metrics", kernel_kobj); + if (!primary_sysfs_folder) { + pr_err("Failed to create primary sysfs folder!\n"); + return -EINVAL; + } + if (sysfs_create_group(primary_sysfs_folder, &resume_latency_attr_group)) { + pr_err("failed to create resume_latency folder\n"); + return ret; + } + if (sysfs_create_group(primary_sysfs_folder, &irq_attr_group)) { + pr_err("failed to create irq folder\n"); + return ret; + } + spin_lock_init(&resume_latency_stats.resume_latency_stat_lock); + ret = register_trace_android_vh_early_resume_begin( + vendor_hook_resume_begin, NULL); + if (ret) { + pr_err("Register resume begin vendor hook fail %d\n", ret); + return ret; + } + ret = register_trace_android_vh_resume_end( + vendor_hook_resume_end, NULL); + if (ret) { + pr_err("Register resume end vendor hook fail %d\n", ret); + return ret; + } + long_irq_stat.long_softirq_threshold = 10000; + long_irq_stat.long_irq_threshold = 500; + ret = register_trace_softirq_entry(hook_softirq_begin, NULL); + if (ret) { + pr_err("Register soft irq handler hook fail %d\n", ret); + return ret; + } + ret = register_trace_softirq_exit(hook_softirq_end, NULL); + if (ret) { + pr_err("Register soft irq exit hook fail %d\n", ret); + return ret; + } + ret = register_trace_irq_handler_entry(hook_irq_begin, NULL); + if (ret) { + pr_err("Register irq handler hook fail %d\n", ret); + return ret; + } + ret = register_trace_irq_handler_exit(hook_irq_end, NULL); + if (ret) { + pr_err("Register irq exit hook fail %d\n", ret); + return ret; + } + pr_info("perf_metrics driver initialized! :D\n"); + return ret; +} + +module_init(perf_metrics_init); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ziyi Cui "); diff --git a/drivers/soc/google/vh/kernel/metrics.h b/drivers/soc/google/vh/kernel/metrics.h new file mode 100644 index 000000000000..059dbfa157df --- /dev/null +++ b/drivers/soc/google/vh/kernel/metrics.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Support for Perf metrics + * + * Copyright 2022 Google LLC + */ + +#include + +#define RESUME_LATENCY_STEP_SMALL 10 +#define RESUME_LATENCY_STEP_MID 50 +#define RESUME_LATENCY_STEP_LARGE 100 + +#define RESUME_LATENCY_BOUND_SMALL 250 +#define RESUME_LATENCY_BOUND_MID 500 +#define RESUME_LATENCY_BOUND_MAX 1000 + +#define MAX_IRQ_NUM 1024 + +#define LATENCY_CNT_SMALL (RESUME_LATENCY_BOUND_SMALL / RESUME_LATENCY_STEP_SMALL) +#define LATENCY_CNT_MID ((RESUME_LATENCY_BOUND_MID - RESUME_LATENCY_BOUND_SMALL) / \ + RESUME_LATENCY_STEP_MID) +#define LATENCY_CNT_LARGE ((RESUME_LATENCY_BOUND_MAX - RESUME_LATENCY_BOUND_MID) / \ + RESUME_LATENCY_STEP_LARGE) +#define RESUME_LATENCY_ARR_SIZE (LATENCY_CNT_SMALL + LATENCY_CNT_MID + LATENCY_CNT_LARGE + 1) + +struct resume_latency { + ktime_t resume_start; + ktime_t resume_end; + spinlock_t resume_latency_stat_lock; + s64 resume_count[RESUME_LATENCY_ARR_SIZE]; + s64 resume_latency_max_ms; + u64 resume_latency_sum_ms; +}; + +struct long_irq { + ktime_t softirq_start[CONFIG_VH_SCHED_CPU_NR][NR_SOFTIRQS]; + ktime_t softirq_end; + ktime_t irq_start[CONFIG_VH_SCHED_CPU_NR][MAX_IRQ_NUM]; + ktime_t irq_end; + atomic64_t long_softirq_count; + atomic64_t long_irq_count; + s64 long_softirq_arr[NR_SOFTIRQS]; + s64 long_irq_arr[MAX_IRQ_NUM]; + s64 long_softirq_threshold; + s64 long_irq_threshold; + bool display_warning; +}; diff --git a/drivers/soc/google/vh/kernel/mm/Makefile b/drivers/soc/google/vh/kernel/mm/Makefile index fa707127a65c..4f0526fdfb59 100644 --- a/drivers/soc/google/vh/kernel/mm/Makefile +++ b/drivers/soc/google/vh/kernel/mm/Makefile @@ -2,4 +2,4 @@ # vendor mm module obj-$(CONFIG_VH_MM) += vh_mm.o -vh_mm-y += vh_mm_init.o cma.o gup.o +vh_mm-y += vh_mm_init.o cma.o gup.o swap.o memory.o buffer.o madvise.o vmscan.o diff --git a/drivers/soc/google/vh/kernel/mm/buffer.c b/drivers/soc/google/vh/kernel/mm/buffer.c new file mode 100644 index 000000000000..4c9916dd6ac7 --- /dev/null +++ b/drivers/soc/google/vh/kernel/mm/buffer.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* buffer.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include + +void vh_bh_lru_install(void *data, struct page *page, bool *skip) +{ + if (is_migrate_cma_page(page)) + *skip = true; +} diff --git a/drivers/soc/google/vh/kernel/mm/madvise.c b/drivers/soc/google/vh/kernel/mm/madvise.c new file mode 100644 index 000000000000..b8f5985d63c6 --- /dev/null +++ b/drivers/soc/google/vh/kernel/mm/madvise.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* madvise.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include +#include + +void vh_do_madvise_blk_plug(void *data, int behavior, bool *do_plug) +{ + if (behavior == MADV_PAGEOUT) + *do_plug = false; +} diff --git a/drivers/soc/google/vh/kernel/mm/memory.c b/drivers/soc/google/vh/kernel/mm/memory.c new file mode 100644 index 000000000000..3f026e42f0b9 --- /dev/null +++ b/drivers/soc/google/vh/kernel/mm/memory.c @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* memory.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include + +void vh_zap_pte_range_tlb_start(void *data, void *preempt_off) +{ + preempt_disable(); + *(int *)preempt_off = 1; +} + +void vh_zap_pte_range_tlb_force_flush(void *data, struct page *page, bool *flush) +{ + if (is_migrate_cma_page(page)) + *flush = true; +} + +void vh_zap_pte_range_tlb_end(void *data, void *preempt_off) +{ + if (likely(*(int *)preempt_off == 1)) { + preempt_enable(); + *(int *)preempt_off = 0; + } +} + +void vh_skip_lru_disable(void *data, bool *skip) +{ + *skip = true; +} diff --git a/drivers/soc/google/vh/kernel/mm/swap.c b/drivers/soc/google/vh/kernel/mm/swap.c new file mode 100644 index 000000000000..34a222dcfb0f --- /dev/null +++ b/drivers/soc/google/vh/kernel/mm/swap.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* swap.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include + +void vh_pagevec_drain(void *data, struct page *page, bool *ret) +{ + if (is_migrate_cma_page(page)) + *ret = true; +} diff --git a/drivers/soc/google/vh/kernel/mm/vh_mm_init.c b/drivers/soc/google/vh/kernel/mm/vh_mm_init.c index bf1c860935a1..a307cb3c256d 100644 --- a/drivers/soc/google/vh/kernel/mm/vh_mm_init.c +++ b/drivers/soc/google/vh/kernel/mm/vh_mm_init.c @@ -9,7 +9,11 @@ #include #include #include +#include +#include #include "../../include/gup.h" +#include "../../include/mm.h" +#include "../../include/buffer.h" struct kobject *vendor_mm_kobj; EXPORT_SYMBOL_GPL(vendor_mm_kobj); @@ -52,6 +56,55 @@ static int vh_mm_init(void) return ret; ret = register_trace_android_vh_pin_user_pages( vh_pin_user_pages, NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_pagevec_drain( + vh_pagevec_drain, NULL); + if (ret) + return ret; + + /* + * Do not reorder pte_range_tlb_end and pte_range_tlb_start + * Otherwise, depending on module load timing, the pair can + * be broken. + */ + ret = register_trace_android_vh_zap_pte_range_tlb_end( + vh_zap_pte_range_tlb_end, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_zap_pte_range_tlb_force_flush( + vh_zap_pte_range_tlb_force_flush, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_zap_pte_range_tlb_start( + vh_zap_pte_range_tlb_start, NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_skip_lru_disable( + vh_skip_lru_disable, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_bh_lru_install( + vh_bh_lru_install, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_do_madvise_blk_plug( + vh_do_madvise_blk_plug, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_shrink_inactive_list_blk_plug( + vh_shrink_inactive_list_blk_plug, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_shrink_lruvec_blk_plug( + vh_shrink_lruvec_blk_plug, NULL); + if (ret) + return ret; + ret = register_trace_android_vh_reclaim_pages_plug( + vh_reclaim_pages_plug, NULL); + return ret; } module_init(vh_mm_init); diff --git a/drivers/soc/google/vh/kernel/mm/vmscan.c b/drivers/soc/google/vh/kernel/mm/vmscan.c new file mode 100644 index 000000000000..0fd0e846a7ba --- /dev/null +++ b/drivers/soc/google/vh/kernel/mm/vmscan.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* vmscan.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include + +void vh_shrink_inactive_list_blk_plug(void *data, bool *do_plug) +{ + *do_plug = true; +} + +void vh_shrink_lruvec_blk_plug(void *data, bool *do_plug) +{ + *do_plug = false; +} + +void vh_reclaim_pages_plug(void *data, bool *do_plug) +{ + *do_plug = true; +} diff --git a/drivers/soc/google/pixel_em/Makefile b/drivers/soc/google/vh/kernel/pixel_em/Makefile similarity index 100% rename from drivers/soc/google/pixel_em/Makefile rename to drivers/soc/google/vh/kernel/pixel_em/Makefile diff --git a/drivers/soc/google/vh/kernel/pixel_em/pixel_em.c b/drivers/soc/google/vh/kernel/pixel_em/pixel_em.c new file mode 100644 index 000000000000..0864b70a75c3 --- /dev/null +++ b/drivers/soc/google/vh/kernel/pixel_em/pixel_em.c @@ -0,0 +1,912 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* pixel_em.c + * + * Support for runtime-customizable table-based Energy Model + * + * Copyright 2022 Google LLC + */ + +#define pr_fmt(fmt) "pixel-em: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../include/pixel_em.h" + +#if IS_ENABLED(CONFIG_VH_SCHED) +extern struct pixel_em_profile **vendor_sched_pixel_em_profile; +extern void vh_arch_set_freq_scale_pixel_mod(void *data, + const struct cpumask *cpus, + unsigned long freq, + unsigned long max, + unsigned long *scale); +#endif + +#if IS_ENABLED(CONFIG_EXYNOS_CPU_THERMAL) +extern struct pixel_em_profile **exynos_cpu_cooling_pixel_em_profile; +#endif + +#if IS_ENABLED(CONFIG_ARM_EXYNOS_ACME) +extern struct pixel_em_profile **exynos_acme_pixel_em_profile; +#endif + +static int pixel_em_max_cpu; +static int pixel_em_num_clusters; + +static struct mutex profile_list_lock; +static LIST_HEAD(profile_list); +static struct pixel_em_profile *active_profile; + +static struct mutex sysfs_lock; // Synchronize sysfs calls. +static struct kobject *primary_sysfs_folder; +static struct kobject *profiles_sysfs_folder; + +static struct platform_device *platform_dev; + +static struct pixel_em_profile *generate_default_em_profile(const char *); +static void pixel_em_free_profile(struct pixel_em_profile *); +static int pixel_em_publish_profile(struct pixel_em_profile *); +static void pixel_em_unpublish_profile(struct pixel_em_profile *); + + +static int pixel_em_count_clusters(void) +{ + int res = 0; + + cpumask_t unmatched_cpus; + + cpumask_copy(&unmatched_cpus, cpu_possible_mask); + + while (!cpumask_empty(&unmatched_cpus)) { + int first_cpu = cpumask_first(&unmatched_cpus); + struct em_perf_domain *pd = em_cpu_get(first_cpu); + + if (!pd) + return -EPROBE_DEFER; + + cpumask_xor(&unmatched_cpus, &unmatched_cpus, em_span_cpus(pd)); + res++; + } + + return res; +} + +static int pixel_em_init_cpu_layout(void) +{ + int num_clusters; + + num_clusters = pixel_em_count_clusters(); + if (num_clusters <= 0) + return num_clusters; + pixel_em_num_clusters = num_clusters; + + pixel_em_max_cpu = cpumask_last(cpu_possible_mask); + + return 0; +} + +static bool verify_profile_name(char *name) +{ + char *iter = name; + + if (*name == '\0') { + pr_err("Empty profile name!\n"); + return false; + } + + while (*iter) { + if ((*iter >= 'a' && *iter <= 'z') || + (*iter >= 'A' && *iter <= 'Z') || + (*iter >= '0' && *iter <= '9') || + (*iter == '-' || *iter == '_') ) { + iter++; + } else { + pr_err("Invalid character '%c' in profile name!\n", *iter); + return false; + } + } + + return true; +} + +static struct pixel_em_profile *find_profile(const char *name) +{ + struct pixel_em_profile *profile; + struct list_head *pos; + + mutex_lock(&profile_list_lock); + list_for_each(pos, &profile_list) { + profile = list_entry(pos, struct pixel_em_profile, list); + if (strcmp(name, profile->name) == 0) { + mutex_unlock(&profile_list_lock); + return profile; + } + } + mutex_unlock(&profile_list_lock); + + return NULL; +} + + +static void apply_profile(struct pixel_em_profile *profile) +{ + int cluster_id; + + pr_info("Switching to profile %s...\n", profile->name); + + WRITE_ONCE(active_profile, profile); + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + struct pixel_em_cluster *cluster = &profile->clusters[cluster_id]; + int cluster_cap = cluster->opps[cluster->num_opps - 1].capacity; + int cpu; + struct cpufreq_policy *policy; + + cpu = cpumask_first(&cluster->cpus); + policy = cpufreq_cpu_get(cpu); + if (policy) { + unsigned int cur_freq; + + spin_lock(&policy->transition_lock); + + cur_freq = policy->cur; + + for_each_cpu(cpu, &cluster->cpus) { + WRITE_ONCE(per_cpu(cpu_scale, cpu), cluster_cap); + } + +#if IS_ENABLED(CONFIG_VH_SCHED) + { + unsigned int max_freq = cluster->opps[cluster->num_opps - 1].freq; + unsigned long new_freq_scale; + vh_arch_set_freq_scale_pixel_mod(NULL, + &cluster->cpus, + cur_freq, + max_freq, + &new_freq_scale); + for_each_cpu(cpu, &cluster->cpus) { + WRITE_ONCE(per_cpu(freq_scale, cpu), new_freq_scale); + } + } +#endif + spin_unlock(&policy->transition_lock); + + schedule_work(&policy->update); + cpufreq_cpu_put(policy); + } else { + pr_err("Could not find cpufreq policy for CPU %d!\n", cpu); + } + } +} + +static bool update_em_entry(struct pixel_em_profile *profile, + int cpu, + unsigned int freq, + unsigned int cap, + unsigned int power) +{ + int cluster_id; + int opp_id; + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + struct pixel_em_cluster *cluster = &profile->clusters[cluster_id]; + unsigned long max_freq = cluster->opps[cluster->num_opps - 1].freq; + + if (!cpumask_test_cpu(cpu, &cluster->cpus)) + continue; + + for (opp_id = 0; opp_id < cluster->num_opps; opp_id++) { + if (cluster->opps[opp_id].freq == freq) { + cluster->opps[opp_id].capacity = cap; + cluster->opps[opp_id].power = power; + cluster->opps[opp_id].cost = (max_freq * power) / freq; + return true; + } + } + } + + pr_err("Could not find OPP for CPU %d, freq %u in profile '%s'!\n", + cpu, + freq, + profile->name); + + return false; +} + +static void update_profile(struct pixel_em_profile *dst, const struct pixel_em_profile *src) +{ + int cluster_id; + int opp_id; + + if (dst->num_clusters != src->num_clusters) { + pr_err("Cannot update incompatible profiles (different num_clusters)!\n"); + return; + } + + for (cluster_id = 0; cluster_id < dst->num_clusters; cluster_id++) { + struct pixel_em_cluster *dst_cluster = &dst->clusters[cluster_id]; + struct pixel_em_cluster *src_cluster = &src->clusters[cluster_id]; + + if (dst_cluster->num_opps != src_cluster->num_opps) { + pr_err("Cannot update incompatible profiles (different num_opps)!\n"); + return; + } + + if (!cpumask_equal(&dst_cluster->cpus, &src_cluster->cpus)) { + pr_err("Cannot update incompatible profiles (different CPU masks)!\n"); + return; + } + + for (opp_id = 0; opp_id < src_cluster->num_opps; opp_id++) { + if (dst_cluster->opps[opp_id].freq != src_cluster->opps[opp_id].freq) { + pr_err("Cannot update incompatible profiles (different CPU freqs)!\n"); + return; + } + dst_cluster->opps[opp_id].capacity = src_cluster->opps[opp_id].capacity; + dst_cluster->opps[opp_id].power = src_cluster->opps[opp_id].power; + dst_cluster->opps[opp_id].cost = src_cluster->opps[opp_id].cost; + } + } +} + +// Checks that frequencies, capacities and powers are ascending on every cluster. +static bool check_profile_consistency(const struct pixel_em_profile *profile) +{ + int cluster_id; + int opp_id; + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + struct pixel_em_cluster *cluster = &profile->clusters[cluster_id]; + for (opp_id = 1; opp_id < cluster->num_opps; opp_id++) { + if (cluster->opps[opp_id].freq <= cluster->opps[opp_id -1].freq) { + pr_err("Non-ascending frequency in profile (freq: %u KHz)!\n", + cluster->opps[opp_id].freq); + return false; + } + if (cluster->opps[opp_id].capacity <= cluster->opps[opp_id -1].capacity) { + pr_err("Non-ascending capacity in profile (capacity: %u)!\n", + cluster->opps[opp_id].capacity); + return false; + } + if (cluster->opps[opp_id].power <= cluster->opps[opp_id -1].power) { + pr_err("Non-ascending power in profile (power: %u mW)!\n", + cluster->opps[opp_id].power); + return false; + } + } + } + + return true; +} + +static void scale_profile_capacities(struct pixel_em_profile *profile) +{ + int cluster_id; + int opp_id; + unsigned int orig_max_cap = 0; + const unsigned int scaling_target = 1024; + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + struct pixel_em_cluster *cluster = &profile->clusters[cluster_id]; + orig_max_cap = max(orig_max_cap, cluster->opps[cluster->num_opps - 1].capacity); + } + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + struct pixel_em_cluster *cluster = &profile->clusters[cluster_id]; + for (opp_id = 0; opp_id < cluster->num_opps; opp_id++) { + cluster->opps[opp_id].capacity *= scaling_target; + cluster->opps[opp_id].capacity /= orig_max_cap; + } + } +} + +static int parse_profile(const char *profile_input, int profile_input_length) +{ + char *profile_input_dup = kstrndup(profile_input, profile_input_length, GFP_KERNEL); + char *cur_line; + char *sep_iterator = profile_input_dup; + char *profile_name; + struct pixel_em_profile *profile; + struct pixel_em_profile *pre_existing_profile; + int current_cpu_id = -1; + int res = profile_input_length; + + if (!profile_input_dup) { + res = -ENOMEM; + goto early_return; + } + + profile_name = strsep(&sep_iterator, "\n"); + if (!profile_name || !verify_profile_name(profile_name)) { + res = -EINVAL; + goto early_return; + } + + profile = generate_default_em_profile(profile_name); + if (!profile) { + res = -EINVAL; + goto early_return; + } + + pre_existing_profile = find_profile(profile->name); + if (pre_existing_profile) { + pr_info("Updating profile %s...\n", profile->name); + } + + while ((cur_line = strsep(&sep_iterator, "\n"))) { + char *skipped_blanks = skip_spaces(cur_line); + + if (skipped_blanks[0] == '\0' || skipped_blanks[0] == '}') { + continue; + } else if (strncasecmp(skipped_blanks, "cpu", 3) == 0) { + // Expecting a CPU line here... + if (sscanf(skipped_blanks + 3, "%d", ¤t_cpu_id) != 1) { + pr_err("Error when parsing '%s'!\n", skipped_blanks); + res = -EINVAL; + goto early_return; + } + if (current_cpu_id < 0 || current_cpu_id > pixel_em_max_cpu) { + pr_err("Invalid CPU specified on line '%s'!\n", skipped_blanks); + res = -EINVAL; + goto early_return; + } + pr_debug("Setting active CPU to %d...\n", current_cpu_id); + } else if (skipped_blanks[0] != '\0' && skipped_blanks[0] != '}') { + unsigned int freq = 0; + unsigned int cap = 0; + unsigned int power = 0; + + if (current_cpu_id == -1) { + pr_err("Error: no CPU id specified before parsing '%s'!\n", + skipped_blanks); + res = -EINVAL; + goto early_return; + } + if (sscanf(skipped_blanks, "%u %u %u", &freq, &cap, &power) != 3) { + pr_err("Error when parsing '%s'!\n", skipped_blanks); + res = -EINVAL; + goto early_return; + } + if (freq == 0 || cap == 0 || power == 0) { + pr_err("Illegal freq/cap/power combination specified: %u, %u, %u.\n", + freq, + cap, + power); + res = -EINVAL; + goto early_return; + } + + update_em_entry(profile, current_cpu_id, freq, cap, power); + } + } + + if (!check_profile_consistency(profile)) { + res = -EINVAL; + goto early_return; + } + + scale_profile_capacities(profile); + + if (!pre_existing_profile) { + int file_res = pixel_em_publish_profile(profile); + if (file_res) { + pixel_em_free_profile(profile); + res = file_res; + goto early_return; + } + } else { + update_profile(pre_existing_profile, profile); + pixel_em_free_profile(profile); + profile = pre_existing_profile; + if (profile == active_profile) + apply_profile(profile); + } + +early_return: + kfree(profile_input_dup); + if (res < 0) { + pixel_em_free_profile(profile); + } else { + pr_info("Successfully created/updated profile '%s'!\n", profile->name); + } + + return res; +} + +static bool generate_em_cluster(struct pixel_em_cluster *dst, struct em_perf_domain *pd) +{ + int first_cpu = cpumask_first(em_span_cpus(pd)); + int cpu_scale = topology_get_cpu_scale(first_cpu); + int max_freq_index = pd->nr_perf_states - 1; + unsigned long max_freq = pd->table[max_freq_index].frequency; + int opp_id; + + cpumask_copy(&dst->cpus, em_span_cpus(pd)); + + dst->num_opps = pd->nr_perf_states; + + dst->opps = kcalloc(dst->num_opps, sizeof(*dst->opps), GFP_KERNEL); + if (!dst->opps) + return false; + + for (opp_id = 0; opp_id < pd->nr_perf_states; opp_id++) { + dst->opps[opp_id].freq = pd->table[opp_id].frequency; + dst->opps[opp_id].power = pd->table[opp_id].power; + dst->opps[opp_id].cost = pd->table[opp_id].cost; + dst->opps[opp_id].capacity = (dst->opps[opp_id].freq * cpu_scale) / max_freq; + } + + return true; +} + +static void deallocate_em_cluster(struct pixel_em_cluster *dst) +{ + kfree(dst->opps); + dst->opps = NULL; +} + +// Returns a valid pixel_em_profile based on default system parameters. This +// profile is NOT yet registered in the profile list, nor associated to sysfs. +static struct pixel_em_profile *generate_default_em_profile(const char *name) +{ + struct pixel_em_profile *res; + cpumask_t unmatched_cpus; + int current_cluster_id = 0; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + goto failed_res_allocation; + + res->name = kstrdup(name, GFP_KERNEL); + if (!res->name) + goto failed_name_allocation; + + res->num_clusters = pixel_em_num_clusters; + + res->clusters = kcalloc(res->num_clusters, sizeof(*res->clusters), GFP_KERNEL); + if (!res->clusters) + goto failed_clusters_allocation; + + res->cpu_to_cluster = kcalloc(pixel_em_max_cpu, sizeof(*res->cpu_to_cluster), GFP_KERNEL); + if (!res->cpu_to_cluster) + goto failed_cpu_to_cluster_allocation; + + + cpumask_copy(&unmatched_cpus, cpu_possible_mask); + + while (!cpumask_empty(&unmatched_cpus)) { + int first_cpu = cpumask_first(&unmatched_cpus); + struct em_perf_domain *pd = em_cpu_get(first_cpu); + // pd is guaranteed not to be NULL, as pixel_em_count_clusters completed earlier. + int pd_cpu; + + if (!generate_em_cluster(&res->clusters[current_cluster_id], pd)) { + do { + deallocate_em_cluster(&res->clusters[current_cluster_id]); + } while (--current_cluster_id >= 0); + goto failed_cluster_generation; + } + + for_each_cpu(pd_cpu, em_span_cpus(pd)) { + res->cpu_to_cluster[pd_cpu] = &res->clusters[current_cluster_id]; + } + + cpumask_xor(&unmatched_cpus, &unmatched_cpus, em_span_cpus(pd)); + current_cluster_id++; + } + + INIT_LIST_HEAD(&res->list); + + return res; + +failed_cluster_generation: + kfree(res->cpu_to_cluster); + +failed_cpu_to_cluster_allocation: + kfree(res->clusters); + +failed_clusters_allocation: + kfree(res->name); + +failed_name_allocation: + kfree(res); + +failed_res_allocation: + return NULL; +} + +static ssize_t sysfs_write_profile_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + int parse_result; + + mutex_lock(&sysfs_lock); + parse_result = parse_profile(buf, count); + mutex_unlock(&sysfs_lock); + + return parse_result; +} + +static struct kobj_attribute write_profile_attr = __ATTR(write_profile, + 0220, + NULL, + sysfs_write_profile_store); + +static ssize_t sysfs_active_profile_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + ssize_t res = 0; + struct pixel_em_profile *profile_snapshot; + + mutex_lock(&sysfs_lock); + + profile_snapshot = READ_ONCE(active_profile); + + res = profile_snapshot + ? sysfs_emit(buf, "%s\n", profile_snapshot->name) + : -EINVAL; + + mutex_unlock(&sysfs_lock); + return res; +} + +static ssize_t sysfs_active_profile_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t count) +{ + int res = count; + char *profile_name = kstrndup(buf, count, GFP_KERNEL); + char *iter = profile_name; + struct pixel_em_profile *profile; + + if (!profile_name) + return -ENOMEM; + + while (*iter) { + if (*iter == '\n') { + *iter = '\0'; + break; + } + iter++; + } + + mutex_lock(&sysfs_lock); + profile = find_profile(profile_name); + if (profile) + apply_profile(profile); + else + res = -EINVAL; + mutex_unlock(&sysfs_lock); + + kfree(profile_name); + return res; +} + +static struct kobj_attribute active_profile_attr = __ATTR(active_profile, + 0664, + sysfs_active_profile_show, + sysfs_active_profile_store); + +struct profile_sysfs_helper { + struct kobj_attribute kobj_attr; + struct pixel_em_profile *profile; +}; + +static ssize_t sysfs_profile_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + ssize_t res = 0; + int cluster_id; + struct pixel_em_profile *profile = ((struct profile_sysfs_helper *) attr)->profile; + + mutex_lock(&sysfs_lock); + + res += sysfs_emit_at(buf, res, "%s\n", profile->name); + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + int opp_id; + int first_cpu = cpumask_first(&profile->clusters[cluster_id].cpus); + + res += sysfs_emit_at(buf, res, "cpu%d {\n", first_cpu); + + for (opp_id = 0; + opp_id < profile->clusters[cluster_id].num_opps; + opp_id++) + res += sysfs_emit_at(buf, + res, + "%u %d %d\n", + profile->clusters[cluster_id].opps[opp_id].freq, + profile->clusters[cluster_id].opps[opp_id].capacity, + profile->clusters[cluster_id].opps[opp_id].power); + + res += sysfs_emit_at(buf, res, "}\n"); + } + mutex_unlock(&sysfs_lock); + return res; +} + +// Creates a sysfs file for the target profile (in the profiles/ folder), and also adds the +// profile to the profiles list. +static int pixel_em_publish_profile(struct pixel_em_profile *profile) +{ + profile->sysfs_helper = kzalloc(sizeof(*profile->sysfs_helper), GFP_KERNEL); + if (!profile->sysfs_helper) + return -ENOMEM; + + profile->sysfs_helper->profile = profile; + sysfs_attr_init(&profile->sysfs_helper->kobj_attr.attr); + profile->sysfs_helper->kobj_attr.attr.name = profile->name; + profile->sysfs_helper->kobj_attr.attr.mode = 0664; + profile->sysfs_helper->kobj_attr.show = sysfs_profile_show; + + if (sysfs_create_file(profiles_sysfs_folder, &profile->sysfs_helper->kobj_attr.attr)) { + pr_err("Failed to create profile file for '%s'!\n", profile->name); + kfree(profile->sysfs_helper); + profile->sysfs_helper = NULL; + return -EINVAL; + } + + mutex_lock(&profile_list_lock); + list_add(&profile->list, &profile_list); + mutex_unlock(&profile_list_lock); + return 0; +} + +static void pixel_em_unpublish_profile(struct pixel_em_profile *profile) +{ + if (!profile->sysfs_helper) + return; + + mutex_lock(&profile_list_lock); + list_del(&profile->list); + mutex_unlock(&profile_list_lock); + + sysfs_remove_file(profiles_sysfs_folder, &profile->sysfs_helper->kobj_attr.attr); + kfree(profile->sysfs_helper); + profile->sysfs_helper = NULL; +} + +static void pixel_em_free_profile(struct pixel_em_profile *profile) +{ + int cluster_id; + + if (!profile) + return; + + if (profile->sysfs_helper) { + // When a profile was published (i.e. got sysfs files / was inserted in + // the profiles list), we cannot guarantee that no driver client retains + // a reference to it: the sysfs file can be removed, but the rest of the + // profile cannot be deallocated. + pixel_em_unpublish_profile(profile); + return; + } + + kfree(profile->name); + + for (cluster_id = 0; cluster_id < profile->num_clusters; cluster_id++) { + deallocate_em_cluster(&profile->clusters[cluster_id]); + } + kfree(profile->clusters); + kfree(profile); +} + +static void pixel_em_clean_up_sysfs_nodes(void) +{ + if (!primary_sysfs_folder) + return; + + sysfs_remove_file(primary_sysfs_folder, &active_profile_attr.attr); + sysfs_remove_file(primary_sysfs_folder, &write_profile_attr.attr); + + if (profiles_sysfs_folder) { + struct pixel_em_profile *profile; + struct list_head *pos, *tmp; + + list_for_each_safe(pos, tmp, &profile_list) { + profile = list_entry(pos, struct pixel_em_profile, list); + pixel_em_free_profile(profile); + } + kobject_put(profiles_sysfs_folder); + profiles_sysfs_folder = NULL; + } + + kobject_put(primary_sysfs_folder); + primary_sysfs_folder = NULL; +} + +static int pixel_em_initialize_sysfs_nodes(void) +{ + if (primary_sysfs_folder) { + pr_err("Sysfs nodes already initialized!\n"); + return -EINVAL; + } + + primary_sysfs_folder = kobject_create_and_add("pixel_em", kernel_kobj); + if (!primary_sysfs_folder) { + pr_err("Failed to create primary sysfs folder!\n"); + return -EINVAL; + } + + profiles_sysfs_folder = kobject_create_and_add("profiles", primary_sysfs_folder); + if (!profiles_sysfs_folder) { + pr_err("Failed to create profiles sysfs folder!\n"); + return -EINVAL; + } + + + if (sysfs_create_file(primary_sysfs_folder, &write_profile_attr.attr)) { + pr_err("Failed to create write_profile file!\n"); + return -EINVAL; + } + + if (sysfs_create_file(primary_sysfs_folder, &active_profile_attr.attr)) { + pr_err("Failed to create active_profile file!\n"); + return -EINVAL; + } + + return 0; +} + +static void pixel_em_drv_undo_probe(void) +{ + // Note: removing/unloading this driver after a successful probe is not expected to ever + // happen (other than debugging). + + pixel_em_clean_up_sysfs_nodes(); + + if (!platform_dev) { + // 'platform_dev' gets set when probing is successful. When that point is reached, + // there is no way to know whether freeing cpu_to_em_pd or em_pds is safe (as + // the pointers may have been shared with other drivers without reference tracking). + // => If platform_dev is NULL, free these pointers (if they're not NULL themselves). + // Otherwise, set them to NULL without freeing. + } + + platform_dev = NULL; +} + +static int pixel_em_drv_probe(struct platform_device *dev) +{ + int res; + struct pixel_em_profile *default_profile; + int num_dt_profiles; + int i; + + mutex_init(&sysfs_lock); + mutex_init(&profile_list_lock); + INIT_LIST_HEAD(&profile_list); + + res = pixel_em_init_cpu_layout(); + if (res < 0) { + pixel_em_drv_undo_probe(); + return res; + } + + default_profile = generate_default_em_profile("default"); + if (default_profile == NULL) { + pixel_em_drv_undo_probe(); + return -ENOMEM; + } + + res = pixel_em_initialize_sysfs_nodes(); + if (res < 0) { + pixel_em_drv_undo_probe(); + return res; + } + + res = pixel_em_publish_profile(default_profile); + if (res) { + pixel_em_drv_undo_probe(); + return res; + } + + num_dt_profiles = of_property_count_strings(dev->dev.of_node, "profiles"); + if (num_dt_profiles >= 0) + pr_info("Loading %d profile(s).\n", num_dt_profiles); + + for (i = 0; i < num_dt_profiles; i++) { + const char *profile_body; + int res = of_property_read_string_index(dev->dev.of_node, + "profiles", + i, + &profile_body); + if (!res) { + res = parse_profile(profile_body, strlen(profile_body)); + if (res <= 0) { + pr_err("Error parsing profile #%d.\n", i); + pixel_em_drv_undo_probe(); + return res; + } + } else { + pr_err("Error retrieving profile #%d.\n", i); + pixel_em_drv_undo_probe(); + return res; + } + } + + active_profile = default_profile; + + // Probe is successful => do not attempt to free pixel_em_max_cpu or cpu_to_em_pd. + platform_dev = dev; + + // Register EM table to all needed drivers here. +#if IS_ENABLED(CONFIG_VH_SCHED) + pr_info("Publishing EM profile to vh_sched!\n"); + WRITE_ONCE(vendor_sched_pixel_em_profile, &active_profile); +#endif + +#if IS_ENABLED(CONFIG_EXYNOS_CPU_THERMAL) + pr_info("Publishing EM profile to exynos_cpu_cooling!\n"); + WRITE_ONCE(exynos_cpu_cooling_pixel_em_profile, &active_profile); +#endif + +#if IS_ENABLED(CONFIG_ARM_EXYNOS_ACME) + pr_info("Publishing EM profile to exynos acme!\n"); + WRITE_ONCE(exynos_acme_pixel_em_profile, &active_profile); +#endif + + return 0; +} + +static int pixel_em_drv_remove(struct platform_device *dev) +{ + pixel_em_drv_undo_probe(); + + return 0; +} + +static const struct of_device_id pixel_em_of_match[] = { + { + .compatible = "google,pixel-em", + }, + {} +}; + +static struct platform_driver pixel_em_platform_driver = { + .probe = pixel_em_drv_probe, + .remove = pixel_em_drv_remove, + .driver = { + .name = "pixel-em", + .owner = THIS_MODULE, + .of_match_table = pixel_em_of_match, + }, +}; + +static int __init pixel_em_init(void) +{ + if (platform_driver_register(&pixel_em_platform_driver)) + pr_err("Error when registering driver!\n"); + + pr_info("Registered! :D\n"); + + return 0; +} + +static void __exit pixel_em_exit(void) +{ + pixel_em_drv_undo_probe(); + pr_info("Unregistered! :(\n"); +} + +module_init(pixel_em_init); +module_exit(pixel_em_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Vincent Palomares"); +MODULE_DESCRIPTION("Pixel Energy Model Driver"); +MODULE_DEVICE_TABLE(of, pixel_em_of_match); diff --git a/drivers/soc/google/vh/kernel/sched/Makefile b/drivers/soc/google/vh/kernel/sched/Makefile index 3672e39bf40e..438eaed9994c 100644 --- a/drivers/soc/google/vh/kernel/sched/Makefile +++ b/drivers/soc/google/vh/kernel/sched/Makefile @@ -4,7 +4,7 @@ EXTRA_CFLAGS += -I$(srctree) # vendor sched module obj-$(CONFIG_VH_SCHED) += vh_sched.o -vh_sched-y += core.o fair.o init.o procfs_node.o rt.o cpufreq_gov.o acpu.o +vh_sched-y += core.o fair.o init.o procfs_node.o rt.o cpufreq_gov.o acpu.o sched_lib.o freeze.o # vendor sched tracing module obj-$(CONFIG_VH_SCHED) += sched_tp.o diff --git a/drivers/soc/google/vh/kernel/sched/cpufreq_gov.c b/drivers/soc/google/vh/kernel/sched/cpufreq_gov.c index 7a5dcec1fa7f..46bb60febd23 100644 --- a/drivers/soc/google/vh/kernel/sched/cpufreq_gov.c +++ b/drivers/soc/google/vh/kernel/sched/cpufreq_gov.c @@ -145,16 +145,13 @@ static inline bool update_pmu_throttle_on_ignored_cpus(struct sugov_policy *sg_p return true; } -static inline void trace_pmu_limit(struct sugov_policy *sg_policy) +static inline void trace_pmu_limit(struct sugov_policy *sg_policy, unsigned int freq) { if (trace_clock_set_rate_enabled()) { char trace_name[32] = {0}; scnprintf(trace_name, sizeof(trace_name), "pmu_limit_cpu%d", sg_policy->policy->cpu); - trace_clock_set_rate(trace_name, sg_policy->under_pmu_throttle ? - sg_policy->tunables->limit_frequency : - sg_policy->policy->cpuinfo.max_freq, - raw_smp_processor_id()); + trace_clock_set_rate(trace_name, freq, raw_smp_processor_id()); } } @@ -869,10 +866,10 @@ static void sugov_work(struct kthread_work *work) freq_qos_update_request(&sg_policy->pmu_max_freq_req, sg_policy->policy->cpuinfo.max_freq); + trace_pmu_limit(sg_policy, sg_policy->policy->cpuinfo.max_freq); + sg_policy->under_pmu_throttle = false; sg_policy->relax_pmu_throttle = false; - - trace_pmu_limit(sg_policy); } mutex_lock(&sg_policy->work_lock); @@ -903,6 +900,7 @@ void pmu_poll_enable(void) if (!pmu_poll_enabled) { pmu_poll_enabled = true; + trace_clock_set_rate("PMU_POLL", 1, raw_smp_processor_id()); kthread_mod_delayed_work(&pmu_worker, &pmu_work, msecs_to_jiffies(0)); } @@ -919,6 +917,7 @@ void pmu_poll_disable(void) if (pmu_poll_enabled) { pmu_poll_enabled = false; + trace_clock_set_rate("PMU_POLL", 0, raw_smp_processor_id()); kthread_cancel_delayed_work_sync(&pmu_work); @@ -926,9 +925,11 @@ void pmu_poll_disable(void) policy = cpufreq_cpu_get(cpu); sg_policy = policy->governor_data; - if (sg_policy) + if (sg_policy) { freq_qos_update_request(&sg_policy->pmu_max_freq_req, policy->cpuinfo.max_freq); + trace_pmu_limit(sg_policy, policy->cpuinfo.max_freq); + } else pr_err("no sugov policy for cpu %d\n", cpu); @@ -1025,13 +1026,13 @@ static void pmu_limit_work(struct kthread_work *work) update_next_max_freq: freq_qos_update_request(&sg_policy->pmu_max_freq_req, next_max_freq); + trace_pmu_limit(sg_policy, next_max_freq); raw_spin_lock_irqsave(&sg_policy->update_lock, flags); sg_policy->under_pmu_throttle = pmu_throttle; cpumask_copy(&sg_policy->pmu_ignored_mask, &local_pmu_ignored_mask); raw_spin_unlock_irqrestore(&sg_policy->update_lock, flags); - trace_pmu_limit(sg_policy); cpu = cpumask_last(policy->related_cpus) + 1; cpufreq_cpu_put(policy); } diff --git a/drivers/soc/google/vh/kernel/sched/fair.c b/drivers/soc/google/vh/kernel/sched/fair.c index ab1da74a1ccd..7c699ceb15e2 100644 --- a/drivers/soc/google/vh/kernel/sched/fair.c +++ b/drivers/soc/google/vh/kernel/sched/fair.c @@ -14,8 +14,9 @@ #include "../systrace.h" #if IS_ENABLED(CONFIG_PIXEL_EM) -struct em_perf_domain **vendor_sched_cpu_to_em_pd; -EXPORT_SYMBOL_GPL(vendor_sched_cpu_to_em_pd); +#include "../../include/pixel_em.h" +struct pixel_em_profile **vendor_sched_pixel_em_profile; +EXPORT_SYMBOL_GPL(vendor_sched_pixel_em_profile); #endif extern unsigned int vendor_sched_uclamp_threshold; @@ -27,8 +28,8 @@ static struct vendor_group_property vg[VG_MAX]; unsigned int sched_capacity_margin[CPU_NUM] = { [0 ... CPU_NUM-1] = DEF_UTIL_THRESHOLD }; -static unsigned long scale_freq[CPU_NUM] = { - [0 ... CPU_NUM-1] = SCHED_CAPACITY_SCALE }; + +extern struct vendor_group_list vendor_group_list[VG_MAX]; extern struct vendor_group_list vendor_group_list[VG_MAX]; @@ -132,7 +133,7 @@ static unsigned long capacity_curr_of(int cpu) { unsigned long max_cap = cpu_rq(cpu)->cpu_capacity_orig; - return cap_scale(max_cap, scale_freq[cpu]); + return cap_scale(max_cap, per_cpu(freq_scale, cpu)); } /* Runqueue only has SCHED_IDLE tasks enqueued */ @@ -579,9 +580,32 @@ static inline unsigned long em_cpu_energy_pixel_mod(struct em_perf_domain *pd, #if IS_ENABLED(CONFIG_PIXEL_EM) { - struct em_perf_domain **cpu_to_em_pd = READ_ONCE(vendor_sched_cpu_to_em_pd); - if (cpu_to_em_pd) - pd = cpu_to_em_pd[cpu]; + struct pixel_em_profile **profile_ptr_snapshot; + profile_ptr_snapshot = READ_ONCE(vendor_sched_pixel_em_profile); + if (profile_ptr_snapshot) { + struct pixel_em_profile *profile = READ_ONCE(*profile_ptr_snapshot); + if (profile) { + struct pixel_em_cluster *cluster = profile->cpu_to_cluster[cpu]; + struct pixel_em_opp *max_opp; + struct pixel_em_opp *opp; + + max_opp = &cluster->opps[cluster->num_opps - 1]; + + freq = map_util_freq_pixel_mod(max_util, + max_opp->freq, + max_opp->capacity, + cpu); + freq = map_scaling_freq(cpu, freq); + + for (i = 0; i < cluster->num_opps; i++) { + opp = &cluster->opps[i]; + if (opp->freq >= freq) + break; + } + + return opp->cost * sum_util / max_opp->capacity; + } + } } #endif @@ -1022,15 +1046,37 @@ static int find_energy_efficient_cpu(struct task_struct *p, int prev_cpu, bool s return best_energy_cpu; } +#if IS_ENABLED(CONFIG_PIXEL_EM) void vh_arch_set_freq_scale_pixel_mod(void *data, const struct cpumask *cpus, unsigned long freq, unsigned long max, unsigned long *scale) { int i; + struct pixel_em_profile **profile_ptr_snapshot; + profile_ptr_snapshot = READ_ONCE(vendor_sched_pixel_em_profile); + if (profile_ptr_snapshot) { + struct pixel_em_profile *profile = READ_ONCE(*profile_ptr_snapshot); + if (profile) { + struct pixel_em_cluster *cluster; + struct pixel_em_opp *max_opp; + struct pixel_em_opp *opp; + + cluster = profile->cpu_to_cluster[cpumask_first(cpus)]; + max_opp = &cluster->opps[cluster->num_opps - 1]; + + for (i = 0; i < cluster->num_opps; i++) { + opp = &cluster->opps[i]; + if (opp->freq >= freq) + break; + } - for_each_cpu(i, cpus) - scale_freq[i] = *scale; + *scale = (opp->capacity << SCHED_CAPACITY_SHIFT) / + max_opp->capacity; + } + } } +EXPORT_SYMBOL_GPL(vh_arch_set_freq_scale_pixel_mod); +#endif void rvh_set_iowait_pixel_mod(void *data, struct task_struct *p, int *should_iowait_boost) { diff --git a/drivers/soc/google/vh/kernel/sched/freeze.c b/drivers/soc/google/vh/kernel/sched/freeze.c new file mode 100644 index 000000000000..d1fe29909463 --- /dev/null +++ b/drivers/soc/google/vh/kernel/sched/freeze.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* freeze.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ + +#include + +/* + * Freezing of user space tasks may be failed due to process being in + * uninterruptible sleep state. Currently,the logging of unfrozen tasks + * is disabled by default. Although it can be enabled for debugging via + * an adb command, it's usually hard to reproduce the issue. This hook + * is used to enable logging to record unfrozen tasks. + */ +void vh_try_to_freeze_todo_logging_pixel_mod(void *data, bool *logging_on) +{ + *logging_on = true; +} diff --git a/drivers/soc/google/vh/kernel/sched/init.c b/drivers/soc/google/vh/kernel/sched/init.c index 5819ef3867b7..ed42fa4859f4 100644 --- a/drivers/soc/google/vh/kernel/sched/init.c +++ b/drivers/soc/google/vh/kernel/sched/init.c @@ -9,18 +9,22 @@ #include #include #include +#include #include #include +#include #include "sched_priv.h" extern void init_uclamp_stats(void); extern int create_procfs_node(void); +#if IS_ENABLED(CONFIG_PIXEL_EM) extern void vh_arch_set_freq_scale_pixel_mod(void *data, const struct cpumask *cpus, unsigned long freq, unsigned long max, unsigned long *scale); +#endif extern void vh_set_sugov_sched_attr_pixel_mod(void *data, struct sched_attr *attr); extern void rvh_set_iowait_pixel_mod(void *data, struct task_struct *p, int *should_iowait_boost); extern void rvh_select_task_rq_rt_pixel_mod(void *data, struct task_struct *p, int prev_cpu, @@ -52,6 +56,16 @@ extern void rvh_set_task_cpu_pixel_mod(void *data, struct task_struct *p, unsign extern void rvh_enqueue_task_pixel_mod(void *data, struct rq *rq, struct task_struct *p, int flags); extern void rvh_dequeue_task_pixel_mod(void *data, struct rq *rq, struct task_struct *p, int flags); +extern void vh_dump_throttled_rt_tasks_mod(void *data, int cpu, u64 clock, ktime_t rt_period, + u64 rt_runtime, s64 rt_period_timer_expires); + +extern void android_vh_show_max_freq(void *unused, struct cpufreq_policy *policy, + unsigned int *max_freq); + +extern void vh_sched_setaffinity_mod(void *data, struct task_struct *task, + const struct cpumask *in_mask, int *skip); + +extern void vh_try_to_freeze_todo_logging_pixel_mod(void *data, bool *logging_on); extern void rvh_cpumask_any_and_distribute(void *data, struct task_struct *p, const struct cpumask *cpu_valid_mask, const struct cpumask *new_mask, int *dest_cpu); @@ -142,9 +156,11 @@ static int vh_sched_init(void) if (ret) return ret; +#if IS_ENABLED(CONFIG_PIXEL_EM) ret = register_trace_android_vh_arch_set_freq_scale(vh_arch_set_freq_scale_pixel_mod, NULL); if (ret) return ret; +#endif ret = register_trace_android_vh_setscheduler_uclamp( vh_sched_setscheduler_uclamp_pixel_mod, NULL); @@ -163,6 +179,24 @@ static int vh_sched_init(void) if (ret) return ret; + ret = register_trace_android_vh_dump_throttled_rt_tasks(vh_dump_throttled_rt_tasks_mod, + NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_show_max_freq(android_vh_show_max_freq, NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_sched_setaffinity_early(vh_sched_setaffinity_mod, NULL); + if (ret) + return ret; + + ret = register_trace_android_vh_try_to_freeze_todo_logging( + vh_try_to_freeze_todo_logging_pixel_mod, NULL); + if (ret) + return ret; + ret = register_trace_android_rvh_cpumask_any_and_distribute( rvh_cpumask_any_and_distribute, NULL); if (ret) diff --git a/drivers/soc/google/vh/kernel/sched/procfs_node.c b/drivers/soc/google/vh/kernel/sched/procfs_node.c index 39f34998cf6e..4dba9c5da7e9 100644 --- a/drivers/soc/google/vh/kernel/sched/procfs_node.c +++ b/drivers/soc/google/vh/kernel/sched/procfs_node.c @@ -1288,6 +1288,112 @@ static ssize_t pmu_poll_enable_store(struct file *filp, PROC_OPS_RW(pmu_poll_enable); + +extern unsigned int sched_lib_cpu_freq_cached_val; + +static sched_lib_cpu_freq_cached_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%u\n", sched_lib_cpu_freq_cached_val); + return 0; +} + +static ssize_t sched_lib_cpu_freq_cached_store(struct file *filp, + const char __user *ubuf, + size_t count, loff_t *pos) +{ + int dup_sched_lib_cpu_freq_cached_val = 0; + char buf[MAX_PROC_SIZE]; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + + buf[count] = '\0'; + + if (kstrtoint(buf, 10, &dup_sched_lib_cpu_freq_cached_val)) + return -EINVAL; + + sched_lib_cpu_freq_cached_val = dup_sched_lib_cpu_freq_cached_val; + return count; + +} + +PROC_OPS_RW(sched_lib_cpu_freq_cached); + +extern unsigned int sched_lib_freq_cpumask; +static sched_lib_freq_cpumask_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%d\n", sched_lib_freq_cpumask); + return 0; +} + +static ssize_t sched_lib_freq_cpumask_store(struct file *filp, + const char __user *ubuf, + size_t count, loff_t *pos) +{ + int dup_sched_lib_freq_cpumask = 0; + char buf[MAX_PROC_SIZE]; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + + buf[count] = '\0'; + + if (kstrtoint(buf, 10, &dup_sched_lib_freq_cpumask)) + return -EINVAL; + + sched_lib_freq_cpumask = dup_sched_lib_freq_cpumask; + return count; +} + +PROC_OPS_RW(sched_lib_freq_cpumask); + +extern unsigned int sched_lib_affinity_val; +static sched_lib_affinity_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%d\n", sched_lib_affinity_val); + return 0; +} + +static ssize_t sched_lib_affinity_store(struct file *filp, + const char __user *ubuf, + size_t count, loff_t *pos) +{ + int dup_sched_lib_affinity_val = 0; + char buf[MAX_PROC_SIZE]; + + if (count >= sizeof(buf)) + return -EINVAL; + + if (copy_from_user(buf, ubuf, count)) + return -EFAULT; + + buf[count] = '\0'; + + if (kstrtoint(buf, 10, &dup_sched_lib_affinity_val)) + return -EINVAL; + + sched_lib_affinity_val = dup_sched_lib_affinity_val; + return count; +} + +PROC_OPS_RW(sched_lib_affinity); + +extern ssize_t sched_lib_name_store(struct file *filp, + const char __user *ubuffer, size_t count, + loff_t *ppos); +extern sched_lib_name_show(struct seq_file *m, void *v); + + +PROC_OPS_RW(sched_lib_name); + + + struct pentry { const char *name; const struct proc_ops *fops; @@ -1423,6 +1529,11 @@ static struct pentry entries[] = { PROC_ENTRY(prefer_idle_clear), PROC_ENTRY(uclamp_fork_reset_set), PROC_ENTRY(uclamp_fork_reset_clear), + // sched lib + PROC_ENTRY(sched_lib_cpu_freq_cached), + PROC_ENTRY(sched_lib_freq_cpumask), + PROC_ENTRY(sched_lib_affinity), + PROC_ENTRY(sched_lib_name), }; diff --git a/drivers/soc/google/vh/kernel/sched/rt.c b/drivers/soc/google/vh/kernel/sched/rt.c index 1bd5b165e14c..bfeef4c6e3ef 100644 --- a/drivers/soc/google/vh/kernel/sched/rt.c +++ b/drivers/soc/google/vh/kernel/sched/rt.c @@ -476,3 +476,19 @@ void rvh_set_task_cpu_pixel_mod(void *data, struct task_struct *p, unsigned int p->se.avg.last_update_time = 0; } + +void vh_dump_throttled_rt_tasks_mod(void *data, int cpu, u64 clock, ktime_t rt_period, + u64 rt_runtime, s64 rt_period_timer_expires) +{ +#ifdef CONFIG_SCHED_INFO + printk_deferred("RT %s (%d) run %llu ns over rt throttled threshold %llu ns on cpu %d", + current->comm, + current->pid, + clock - current->sched_info.last_arrival, + rt_runtime, + cpu); +#else + printk_deferred("RT %s (%d) run over rt throttled threshold %llu ns on cpu %d", + current->comm, current->pid, rt_runtime, cpu); +#endif +} diff --git a/drivers/soc/google/vh/kernel/sched/sched_lib.c b/drivers/soc/google/vh/kernel/sched/sched_lib.c new file mode 100644 index 000000000000..967c1ea5b6fe --- /dev/null +++ b/drivers/soc/google/vh/kernel/sched/sched_lib.c @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* core.c + * + * Android Vendor Hook Support + * + * Copyright 2021 Google LLC + */ +#include +#include + +#define LIB_PATH_LENGTH 512 +static char sched_lib_name[LIB_PATH_LENGTH]; +unsigned int sched_lib_cpu_freq_cached_val; +unsigned int sched_lib_freq_cpumask; +unsigned int sched_lib_affinity_val; + +static DEFINE_SPINLOCK(__sched_lib_name_lock); + +ssize_t sched_lib_name_store(struct file *filp, + const char __user *ubuffer, size_t count, + loff_t *ppos) +{ + size_t null_idx = count > 0 ? count - 1 : 0; + if (null_idx >= sizeof(sched_lib_name)) + return -EINVAL; + + spin_lock(&__sched_lib_name_lock); + + if (copy_from_user(sched_lib_name, ubuffer, count)) { + spin_unlock(&__sched_lib_name_lock); + return -EFAULT; + } + + sched_lib_name[null_idx] = '\0'; + spin_unlock(&__sched_lib_name_lock); + return count; +} + +sched_lib_name_show(struct seq_file *m, void *v) +{ + spin_lock(&__sched_lib_name_lock); + seq_printf(m, "%s\n", sched_lib_name); + spin_unlock(&__sched_lib_name_lock); + return 0; +} + +static bool is_sched_lib_based_task_name(char const *sched_lib_name_list, char const *name) +{ + int length_name; + int length_sched_lib_name_list; + + length_name = strnlen(name, LIB_PATH_LENGTH); + if (!length_name) + return false; + + length_sched_lib_name_list = strnlen(sched_lib_name_list, LIB_PATH_LENGTH); + if (!length_sched_lib_name_list) + return false; + + if (!strnstr(sched_lib_name_list, name, length_sched_lib_name_list)) + return false; + return true; +} + + +static inline bool is_sched_lib_based_task(struct task_struct *task) +{ + bool found = false; + char *tmp_lib_name; + struct task_struct *list_entry_task; + + /* Copy lib name list into place */ + spin_lock(&__sched_lib_name_lock); + if (strnlen(sched_lib_name, LIB_PATH_LENGTH) == 0) { + spin_unlock(&__sched_lib_name_lock); + return false; + } + + tmp_lib_name = kstrdup(sched_lib_name, GFP_KERNEL); + spin_unlock(&__sched_lib_name_lock); + if (!tmp_lib_name) { + return false; + } + + /* Check task name equal to any of the sched_lib_name list. */ + found = is_sched_lib_based_task_name(tmp_lib_name, task->comm); + if (found) + goto free_up_tmp_lib_name; + + /* Check task name of every thread in group */ + rcu_read_lock(); + for_each_thread(task, list_entry_task) { + if (is_sched_lib_based_task_name(tmp_lib_name, list_entry_task->comm)) { + found = true; + break; + } + } + rcu_read_unlock(); +free_up_tmp_lib_name: + kfree(tmp_lib_name); + return found; +} + +static bool is_sched_lib_based_app(pid_t pid) +{ + bool found; + struct task_struct *p; + + if (strnlen(sched_lib_name, LIB_PATH_LENGTH) == 0) + return false; + + rcu_read_lock(); + p = pid ? get_pid_task(find_vpid(pid), PIDTYPE_PID) : get_task_struct(current); + rcu_read_unlock(); + if (!p) + return false; + + found = is_sched_lib_based_task(p); + + put_task_struct(p); + return found; +} + +void android_vh_show_max_freq(void *unused, struct cpufreq_policy *policy, + unsigned int *max_freq) +{ + bool is_app; + unsigned int the_bit; + if ((!sched_lib_freq_cpumask) || (!sched_lib_cpu_freq_cached_val)) + return; + the_bit = BIT(policy->cpu); + if (!(the_bit & sched_lib_freq_cpumask)) + return; + + is_app = is_sched_lib_based_app(current->pid); + if (is_app) + *max_freq = sched_lib_cpu_freq_cached_val << 1; + + pr_debug("sched_lib show_max_freq returning %u, pid %d, is_app %s, cpu %d, bit %d\n", + (*max_freq), current->pid, is_app ? "true" : "false", policy->cpu, the_bit); +} + +void vh_sched_setaffinity_mod(void *data, struct task_struct *task, + const struct cpumask *in_mask, int *skip) +{ + bool is_sched; + if (!sched_lib_affinity_val) + return; + + is_sched = is_sched_lib_based_task(task); + if (is_sched) + *skip = 1; + + pr_debug("sched_lib setaffinity task %5d, cpumask %*pb, skip %s, is_sched %s\n", + task_pid_nr(task), cpumask_pr_args(in_mask), (*skip)?"True":"False", + is_sched?"True":"False"); +} + diff --git a/drivers/thermal/google/Makefile b/drivers/thermal/google/Makefile index 9cf9a499fd82..67e9d547a127 100644 --- a/drivers/thermal/google/Makefile +++ b/drivers/thermal/google/Makefile @@ -1,2 +1,9 @@ obj-$(CONFIG_GOOGLE_BCL) += google_bcl.o + +ifneq ($(CONFIG_MFD_S2MPG13),) +obj-$(CONFIG_GSOC_PMIC_THERMAL) += s2mpg13_spmic_thermal.o +endif + +ifneq ($(CONFIG_MFD_S2MPG11),) obj-$(CONFIG_GSOC_PMIC_THERMAL) += gs101_spmic_thermal.o +endif diff --git a/drivers/thermal/google/google_bcl.c b/drivers/thermal/google/google_bcl.c index 3253b4d90b8e..efccd7005729 100644 --- a/drivers/thermal/google/google_bcl.c +++ b/drivers/thermal/google/google_bcl.c @@ -25,12 +25,21 @@ #include #include #include +#if IS_ENABLED(CONFIG_SOC_GS201) +#include +#include +#include +#include +#include +#else #include #include #include #include +#endif #include #include +#include #include #include #if IS_ENABLED(CONFIG_DEBUG_FS) @@ -61,7 +70,11 @@ #define CPUCL0_BASE (0x20c00000) #define CPUCL1_BASE (0x20c10000) #define CPUCL2_BASE (0x20c20000) +#if IS_ENABLED(CONFIG_SOC_GS201) +#define G3D_BASE (0x27F00000) +#else #define G3D_BASE (0x1c400000) +#endif #define TPU_BASE (0x1cc00000) #define SYSREG_CPUCL0_BASE (0x20c40000) #define CLUSTER0_GENERAL_CTRL_64 (0x1404) @@ -72,6 +85,7 @@ #define CPUCL12_CLKDIVSTEP_STAT (0x848) #define CPUCL12_CLKDIVSTEP_CON_HEAVY (0x840) #define CPUCL12_CLKDIVSTEP_CON_LIGHT (0x844) +#define CLKOUT (0x810) #define G3D_CLKDIVSTEP_STAT (0x854) #define TPU_CLKDIVSTEP_STAT (0x850) #define CLUSTER0_MPMM (0x1408) @@ -81,6 +95,7 @@ #define PPMCTL_MASK (0xFF) #define OCP_WARN_MASK (0x1F) #define SMPL_WARN_MASK (0xE0) +#if IS_ENABLED(CONFIG_SOC_GS101) #define B3M_UPPER_LIMIT (9600) #define B3M_LOWER_LIMIT (3400) #define B3M_STEP (200) @@ -93,6 +108,21 @@ #define B2S_UPPER_LIMIT (14400) #define B2S_LOWER_LIMIT (5100) #define B2S_STEP (300) +#endif +#if IS_ENABLED(CONFIG_SOC_GS201) +#define B3M_UPPER_LIMIT (8000) +#define B3M_LOWER_LIMIT (2688) +#define B3M_STEP (166) +#define B2M_UPPER_LIMIT (12000) +#define B2M_LOWER_LIMIT (4000) +#define B2M_STEP (250) +#define B10M_UPPER_LIMIT (12000) +#define B10M_LOWER_LIMIT (4000) +#define B10M_STEP (250) +#define B2S_UPPER_LIMIT (12000) +#define B2S_LOWER_LIMIT (4000) +#define B2S_STEP (250) +#endif #define SMPL_BATTERY_VOLTAGE (4200) #define SMPL_UPPER_LIMIT (3300) #define SMPL_LOWER_LIMIT (2600) @@ -109,8 +139,52 @@ #define PMU_ALIVE_CPU2_OUT (0x1DA0) #define PMU_ALIVE_TPU_OUT (0x2920) #define PMU_ALIVE_GPU_OUT (0x1E20) +#define PMU_CLK_OUT (0x3E80) #define THRESHOLD_DELAY_MS 50 +#if IS_ENABLED(CONFIG_SOC_GS201) +#define MAIN S2MPG12 +#define SUB S2MPG13 +#define SMPL_WARN_CTRL S2MPG12_PM_SMPL_WARN_CTRL +#define SMPL_WARN_SHIFT S2MPG12_SMPL_WARN_LVL_SHIFT +#define OCP_WARN_LVL_SHIFT S2MPG12_OCP_WARN_LVL_SHIFT +#define B3M_OCP_WARN S2MPG12_PM_B3M_OCP_WARN +#define B3M_SOFT_OCP_WARN S2MPG12_PM_B3M_SOFT_OCP_WARN +#define B2M_OCP_WARN S2MPG12_PM_B2M_OCP_WARN +#define B2M_SOFT_OCP_WARN S2MPG12_PM_B2M_SOFT_OCP_WARN +#define B10M_OCP_WARN S2MPG12_PM_B10M_OCP_WARN +#define B10M_SOFT_OCP_WARN S2MPG12_PM_B10M_SOFT_OCP_WARN +#define B2S_OCP_WARN S2MPG13_PM_B2S_OCP_WARN +#define B2S_SOFT_OCP_WARN S2MPG13_PM_B2S_SOFT_OCP_WARN +#define MAIN_CHIPID S2MPG12_COMMON_CHIPID +#define SUB_CHIPID S2MPG13_COMMON_CHIPID +#define INT3_120C S2MPG12_IRQ_120C_INT3; +#define INT3_140C S2MPG12_IRQ_140C_INT3; +#define INT3_TSD S2MPG12_IRQ_TSD_INT3; +#define S2MPG1X_WRITE(pmic, bcl_dev, ret, args...) \ + do { \ + switch (pmic) { \ + case SUB: \ + ret = s2mpg13_write_reg(bcl_dev->sub_pmic_i2c, args); \ + break; \ + case MAIN: \ + ret = s2mpg12_write_reg(bcl_dev->main_pmic_i2c, args); \ + break; \ + } \ + } while (0) + +#define S2MPG1X_READ(pmic, bcl_dev, ret, args...) \ + do { \ + switch (pmic) { \ + case SUB: \ + ret = s2mpg13_read_reg(bcl_dev->sub_pmic_i2c, args); \ + break; \ + case MAIN: \ + ret = s2mpg12_read_reg(bcl_dev->main_pmic_i2c, args); \ + break; \ + } \ + } while (0) +#else #define MAIN S2MPG10 #define SUB S2MPG11 #define SMPL_WARN_CTRL S2MPG10_PM_SMPL_WARN_CTRL @@ -153,6 +227,8 @@ } \ } while (0) +#endif + static const char * const triggered_source[] = { [SMPL_WARN] = "smpl_warn", [PMIC_120C] = "pmic_120c", @@ -231,9 +307,47 @@ static bool is_subsystem_on(unsigned int addr) return true; } +static int bcl_odpm_map(int id) +{ +#if IS_ENABLED(CONFIG_SOC_GS201) + switch (id) { + case OCP_WARN_GPU: + case SOFT_OCP_WARN_GPU: + return BUCK4; + case OCP_WARN_TPU: + case SOFT_OCP_WARN_TPU: + return BUCK10; + case OCP_WARN_CPUCL1: + case SOFT_OCP_WARN_CPUCL1: + return BUCK3; + case OCP_WARN_CPUCL2: + case SOFT_OCP_WARN_CPUCL2: + default: + return BUCK2; + } +#endif +#if IS_ENABLED(CONFIG_SOC_GS101) + switch (id) { + case OCP_WARN_GPU: + case SOFT_OCP_WARN_GPU: + return 6; + case OCP_WARN_CPUCL1: + case SOFT_OCP_WARN_CPUCL1: + return 4; + case OCP_WARN_CPUCL2: + case SOFT_OCP_WARN_CPUCL2: + default: + return 3; + } +#endif + return BUCK2; +} + static int triggered_read_level(void *data, int *val, int id) { struct bcl_device *bcl_dev = data; + u64 micro_unit[ODPM_CHANNEL_MAX]; + u64 odpm_current = 0; bool state = true; int polarity = (id == SMPL_WARN) ? 0 : 1; int gpio_pin = bcl_dev->vdroop1_pin; @@ -271,8 +385,23 @@ static int triggered_read_level(void *data, int *val, int id) return 0; } + /* If IRQ not asserted, check ODPM */ + if ((id == OCP_WARN_GPU) || (id == SOFT_OCP_WARN_GPU)) { + mutex_lock(&bcl_dev->sub_odpm->lock); + odpm_get_lpf_values(bcl_dev->sub_odpm, S2MPG1X_METER_CURRENT, micro_unit); + odpm_current = micro_unit[bcl_odpm_map(id)] / 1000; + mutex_unlock(&bcl_dev->sub_odpm->lock); + } else if ((id > SMPL_WARN) && (id < OCP_WARN_TPU)) { + mutex_lock(&bcl_dev->main_odpm->lock); + odpm_get_lpf_values(bcl_dev->main_odpm, S2MPG1X_METER_CURRENT, micro_unit); + odpm_current = micro_unit[bcl_odpm_map(id)] / 1000; + mutex_unlock(&bcl_dev->main_odpm->lock); + } + *val = 0; bcl_dev->bcl_tz_cnt[id] = 0; + if (odpm_current > (bcl_dev->bcl_lvl[id] / bcl_dev->odpm_ratio)) + *val = bcl_dev->bcl_lvl[id] + THERMAL_HYST_LEVEL; if (bcl_dev->bcl_prev_lvl[id] != *val) { mod_delayed_work(system_unbound_wq, &bcl_dev->bcl_irq_work[id], msecs_to_jiffies(THRESHOLD_DELAY_MS)); @@ -599,15 +728,11 @@ static int battery_supply_callback(struct notifier_block *nb, static int google_bcl_remove_thermal(struct bcl_device *bcl_dev) { int i = 0; - struct device *dev; power_supply_unreg_notifier(&bcl_dev->psy_nb); - dev = bcl_dev->main_dev; for (i = 0; i < TRIGGERED_SOURCE_MAX; i++) { - if (i > SOFT_OCP_WARN_TPU) - dev = bcl_dev->sub_dev; if (bcl_dev->bcl_tz[i]) - thermal_zone_of_sensor_unregister(dev, bcl_dev->bcl_tz[i]); + thermal_zone_of_sensor_unregister(bcl_dev->device, bcl_dev->bcl_tz[i]); } return 0; @@ -1210,6 +1335,8 @@ static ssize_t clk_div_show(struct bcl_device *bcl_dev, int idx, char *buf) unsigned int reg; void __iomem *addr; + if (!bcl_dev) + return -EIO; if (idx == TPU) return sysfs_emit(buf, "0x%x\n", bcl_dev->tpu_clkdivstep); else if (idx == GPU) @@ -1228,6 +1355,8 @@ static ssize_t clk_stats_show(struct bcl_device *bcl_dev, int idx, char *buf) unsigned int reg; void __iomem *addr; + if (!bcl_dev) + return -EIO; if (idx == TPU) return sysfs_emit(buf, "0x%x\n", bcl_dev->tpu_clk_stats); else if (idx == GPU) @@ -1245,6 +1374,8 @@ static int google_bcl_init_clk_div(struct bcl_device *bcl_dev, int idx, unsigned { void __iomem *addr; + if (!bcl_dev) + return -EIO; addr = get_addr_by_subsystem(bcl_dev, clk_stats_source[idx]); if (addr == NULL) return -EINVAL; @@ -1267,6 +1398,8 @@ static ssize_t clk_div_store(struct bcl_device *bcl_dev, int idx, if (ret != 1) return -EINVAL; + if (!bcl_dev) + return -EIO; if (idx == TPU) bcl_dev->tpu_clkdivstep = value; else if (idx == GPU) @@ -1406,6 +1539,8 @@ static ssize_t vdroop_flt_show(struct bcl_device *bcl_dev, int idx, char *buf) unsigned int reg; void __iomem *addr; + if (!bcl_dev) + return -EIO; if (idx == TPU) return sysfs_emit(buf, "0x%x\n", bcl_dev->tpu_vdroop_flt); else if (idx == GPU) @@ -1428,6 +1563,8 @@ static ssize_t vdroop_flt_store(struct bcl_device *bcl_dev, int idx, if (sscanf(buf, "0x%x", &value) != 1) return -EINVAL; + if (!bcl_dev) + return -EIO; if (idx == TPU) bcl_dev->tpu_vdroop_flt = value; else if (idx == GPU) @@ -1625,6 +1762,8 @@ static ssize_t clk_ratio_show(struct bcl_device *bcl_dev, int idx, char *buf) unsigned int reg; void __iomem *addr; + if (!bcl_dev) + return -EIO; if (idx == TPU_HEAVY) return sysfs_emit(buf, "0x%x\n", bcl_dev->tpu_con_heavy); else if (idx == TPU_LIGHT) @@ -1653,6 +1792,8 @@ static ssize_t clk_ratio_store(struct bcl_device *bcl_dev, int idx, if (ret != 1) return -EINVAL; + if (!bcl_dev) + return -EIO; if (idx == TPU_HEAVY) bcl_dev->tpu_con_heavy = value; else if (idx == GPU_HEAVY) @@ -1878,6 +2019,8 @@ static ssize_t uvlo1_lvl_show(struct device *dev, struct device_attribute *attr, struct bcl_device *bcl_dev = platform_get_drvdata(pdev); unsigned int uvlo1_lvl; + if (!bcl_dev) + return -EIO; if (!bcl_dev->intf_pmic_i2c) return -EBUSY; if (bcl_cb_uvlo1_read(bcl_dev, &uvlo1_lvl) < 0) @@ -1898,6 +2041,8 @@ static ssize_t uvlo1_lvl_store(struct device *dev, if (ret) return ret; + if (!bcl_dev) + return -EIO; if (value < VD_LOWER_LIMIT || value > VD_UPPER_LIMIT) { dev_err(bcl_dev->device, "UVLO1 %d outside of range %d - %d mV.", value, VD_LOWER_LIMIT, VD_UPPER_LIMIT); @@ -1926,6 +2071,8 @@ static ssize_t uvlo2_lvl_show(struct device *dev, struct device_attribute *attr, struct bcl_device *bcl_dev = platform_get_drvdata(pdev); unsigned int uvlo2_lvl; + if (!bcl_dev) + return -EIO; if (!bcl_dev->intf_pmic_i2c) return -EBUSY; if (bcl_cb_uvlo2_read(bcl_dev, &uvlo2_lvl) < 0) @@ -1946,6 +2093,8 @@ static ssize_t uvlo2_lvl_store(struct device *dev, if (ret) return ret; + if (!bcl_dev) + return -EIO; if (value < VD_LOWER_LIMIT || value > VD_UPPER_LIMIT) { dev_err(bcl_dev->device, "UVLO2 %d outside of range %d - %d mV.", value, VD_LOWER_LIMIT, VD_UPPER_LIMIT); @@ -1973,6 +2122,8 @@ static ssize_t batoilo_lvl_show(struct device *dev, struct device_attribute *att struct bcl_device *bcl_dev = platform_get_drvdata(pdev); unsigned int batoilo_lvl; + if (!bcl_dev) + return -EIO; if (!bcl_dev->intf_pmic_i2c) return -EBUSY; if (bcl_cb_batoilo_read(bcl_dev, &batoilo_lvl) < 0) @@ -1993,6 +2144,8 @@ static ssize_t batoilo_lvl_store(struct device *dev, if (ret) return ret; + if (!bcl_dev) + return -EIO; if (value < BO_LOWER_LIMIT || value > BO_UPPER_LIMIT) { dev_err(bcl_dev->device, "BATOILO %d outside of range %d - %d mA.", value, BO_LOWER_LIMIT, BO_UPPER_LIMIT); @@ -2019,6 +2172,8 @@ static ssize_t smpl_lvl_show(struct device *dev, struct device_attribute *attr, int ret; unsigned int smpl_warn_lvl; + if (!bcl_dev) + return -EIO; if (!bcl_dev->main_pmic_i2c) { return -EBUSY; } @@ -2044,6 +2199,8 @@ static ssize_t smpl_lvl_store(struct device *dev, if (ret) return ret; + if (!bcl_dev) + return -EIO; if (val < SMPL_LOWER_LIMIT || val > SMPL_UPPER_LIMIT) { dev_err(bcl_dev->device, "SMPL_WARN LEVEL %d outside of range %d - %d mV.", val, SMPL_LOWER_LIMIT, SMPL_UPPER_LIMIT); @@ -2087,6 +2244,8 @@ static int get_ocp_lvl(struct bcl_device *bcl_dev, u64 *val, u8 addr, u8 pmic, u int ret; unsigned int ocp_warn_lvl; + if (!bcl_dev) + return -EIO; S2MPG1X_READ(pmic, bcl_dev, ret, addr, &value); if (ret) { dev_err(bcl_dev->device, "S2MPG1X read 0x%x failed.", addr); @@ -2104,6 +2263,8 @@ static int set_ocp_lvl(struct bcl_device *bcl_dev, u64 val, u8 addr, u8 pmic, u8 u8 value; int ret; + if (!bcl_dev) + return -EIO; if (val < llimit || val > ulimit) { dev_err(bcl_dev->device, "OCP_WARN LEVEL %llu outside of range %d - %d mA.", val, llimit, ulimit); @@ -2437,6 +2598,15 @@ static ssize_t pwronsrc_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RO(pwronsrc); +static ssize_t ready_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, dev); + struct bcl_device *bcl_dev = platform_get_drvdata(pdev); + + return sysfs_emit(buf, "%d\n", bcl_dev->ready); +} +static DEVICE_ATTR_RO(ready); + static ssize_t enable_mitigation_show(struct device *dev, struct device_attribute *attr, char *buf) { struct platform_device *pdev = container_of(dev, struct platform_device, dev); @@ -2548,6 +2718,8 @@ int google_init_tpu_ratio(struct bcl_device *data) __raw_writel(data->tpu_clkdivstep, addr); addr = data->base_mem[TPU] + VDROOP_FLT; __raw_writel(data->tpu_vdroop_flt, addr); + addr = data->base_mem[TPU] + CLKOUT; + __raw_writel(data->tpu_clk_out, addr); data->tpu_clk_stats = __raw_readl(data->base_mem[TPU] + clk_stats_offset[TPU]); mutex_unlock(&data->ratio_lock); @@ -2577,6 +2749,8 @@ int google_init_gpu_ratio(struct bcl_device *data) __raw_writel(data->gpu_clkdivstep, addr); addr = data->base_mem[GPU] + VDROOP_FLT; __raw_writel(data->gpu_vdroop_flt, addr); + addr = data->base_mem[GPU] + CLKOUT; + __raw_writel(data->gpu_clk_out, addr); data->gpu_clk_stats = __raw_readl(data->base_mem[GPU] + clk_stats_offset[GPU]); mutex_unlock(&data->ratio_lock); @@ -2752,6 +2926,7 @@ static struct attribute *instr_attrs[] = { &dev_attr_enable_mitigation.attr, &dev_attr_offsrc.attr, &dev_attr_pwronsrc.attr, + &dev_attr_ready.attr, NULL, }; @@ -2760,22 +2935,23 @@ static const struct attribute_group instr_group = { .name = "instruction", }; -static int google_bcl_register_irq(struct bcl_device *bcl_dev, int id, int tz_id, - struct device *dev, const char *devname, u32 intr_flag) +static int google_bcl_register_irq(struct bcl_device *bcl_dev, int id, const char *devname, + u32 intr_flag) { int ret = 0; - ret = devm_request_threaded_irq(dev, bcl_dev->bcl_irq[id], NULL, irq_handler, + ret = devm_request_threaded_irq(bcl_dev->device, bcl_dev->bcl_irq[id], NULL, irq_handler, intr_flag | IRQF_ONESHOT, devname, bcl_dev); if (ret < 0) { - dev_err(dev, "Failed to request IRQ: %d: %d\n", bcl_dev->bcl_irq[id], ret); + dev_err(bcl_dev->device, "Failed to request IRQ: %d: %d\n", bcl_dev->bcl_irq[id], + ret); return ret; } - bcl_dev->bcl_tz[id] = thermal_zone_of_sensor_register(dev, tz_id, bcl_dev, + bcl_dev->bcl_tz[id] = thermal_zone_of_sensor_register(bcl_dev->device, id, bcl_dev, &bcl_dev->bcl_ops[id]); if (IS_ERR(bcl_dev->bcl_tz[id])) { - dev_err(bcl_dev->device, "TZ register failed. %d, err:%ld\n", tz_id, + dev_err(bcl_dev->device, "TZ register failed. %d, err:%ld\n", id, PTR_ERR(bcl_dev->bcl_tz[id])); } else { thermal_zone_device_enable(bcl_dev->bcl_tz[id]); @@ -2784,6 +2960,149 @@ static int google_bcl_register_irq(struct bcl_device *bcl_dev, int id, int tz_id return ret; } +static int get_cpu0clk(void *data, u64 *val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + unsigned int value; + + addr = bcl_dev->base_mem[CPU0] + CLKOUT; + *val = __raw_readl(addr); + exynos_pmu_read(PMU_CLK_OUT, &value); + pr_info("PMU CLK OUT: 0x%x\n", value); + return 0; +} + +static int set_cpu0clk(void *data, u64 val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + + addr = bcl_dev->base_mem[CPU0] + CLKOUT; + __raw_writel(val, addr); + if (val != 0) + exynos_pmu_write(PMU_CLK_OUT, 0x3001); + else + exynos_pmu_write(PMU_CLK_OUT, 0x0); + return 0; +} + +static int get_cpu1clk(void *data, u64 *val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + unsigned int value; + + addr = bcl_dev->base_mem[CPU1] + CLKOUT; + *val = __raw_readl(addr); + exynos_pmu_read(PMU_CLK_OUT, &value); + pr_info("PMU CLK OUT: 0x%x\n", value); + return 0; +} + +static int set_cpu1clk(void *data, u64 val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + + addr = bcl_dev->base_mem[CPU1] + CLKOUT; + __raw_writel(val, addr); + if (val != 0) + exynos_pmu_write(PMU_CLK_OUT, 0x1101); + else + exynos_pmu_write(PMU_CLK_OUT, 0x0); + return 0; +} + +static int get_cpu2clk(void *data, u64 *val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + unsigned int value; + + addr = bcl_dev->base_mem[CPU2] + CLKOUT; + *val = __raw_readl(addr); + exynos_pmu_read(PMU_CLK_OUT, &value); + pr_info("PMU CLK OUT: 0x%x\n", value); + return 0; +} + +static int set_cpu2clk(void *data, u64 val) +{ + struct bcl_device *bcl_dev = data; + void __iomem *addr; + + addr = bcl_dev->base_mem[CPU2] + CLKOUT; + __raw_writel(val, addr); + if (val != 0) + exynos_pmu_write(PMU_CLK_OUT, 0x1201); + else + exynos_pmu_write(PMU_CLK_OUT, 0x0); + return 0; +} + +static int get_gpuclk(void *data, u64 *val) +{ + struct bcl_device *bcl_dev = data; + unsigned int value; + + *val = bcl_dev->gpu_clk_out; + exynos_pmu_read(PMU_CLK_OUT, &value); + pr_info("PMU CLK OUT: 0x%x\n", value); + return 0; +} + +static int set_gpuclk(void *data, u64 val) +{ + struct bcl_device *bcl_dev = data; + + bcl_dev->gpu_clk_out = val; + if (val != 0) + exynos_pmu_write(PMU_CLK_OUT, 0x1a01); + else + exynos_pmu_write(PMU_CLK_OUT, 0x0); + return 0; +} + +static int get_tpuclk(void *data, u64 *val) +{ + struct bcl_device *bcl_dev = data; + unsigned int value; + + *val = bcl_dev->tpu_clk_out; + exynos_pmu_read(PMU_CLK_OUT, &value); + pr_info("PMU CLK OUT: 0x%x\n", value); + return 0; +} + +static int set_tpuclk(void *data, u64 val) +{ + struct bcl_device *bcl_dev = data; + + bcl_dev->tpu_clk_out = val; + if (val != 0) + exynos_pmu_write(PMU_CLK_OUT, 0x2E01); + else + exynos_pmu_write(PMU_CLK_OUT, 0x0); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(cpu0_clkout_fops, get_cpu0clk, set_cpu0clk, "0x%llx\n"); +DEFINE_SIMPLE_ATTRIBUTE(cpu1_clkout_fops, get_cpu1clk, set_cpu1clk, "0x%llx\n"); +DEFINE_SIMPLE_ATTRIBUTE(cpu2_clkout_fops, get_cpu2clk, set_cpu2clk, "0x%llx\n"); +DEFINE_SIMPLE_ATTRIBUTE(gpu_clkout_fops, get_gpuclk, set_gpuclk, "0x%llx\n"); +DEFINE_SIMPLE_ATTRIBUTE(tpu_clkout_fops, get_tpuclk, set_tpuclk, "0x%llx\n"); + +static void google_init_debugfs(struct bcl_device *bcl_dev) +{ + bcl_dev->debug_entry = debugfs_create_dir("google_bcl", 0); + debugfs_create_file("cpu0_clk_out", 0644, bcl_dev->debug_entry, bcl_dev, &cpu0_clkout_fops); + debugfs_create_file("cpu1_clk_out", 0644, bcl_dev->debug_entry, bcl_dev, &cpu1_clkout_fops); + debugfs_create_file("cpu2_clk_out", 0644, bcl_dev->debug_entry, bcl_dev, &cpu2_clkout_fops); + debugfs_create_file("gpu_clk_out", 0644, bcl_dev->debug_entry, bcl_dev, &gpu_clkout_fops); + debugfs_create_file("tpu_clk_out", 0644, bcl_dev->debug_entry, bcl_dev, &tpu_clkout_fops); +} + static void google_set_throttling(struct bcl_device *bcl_dev) { struct device_node *np = bcl_dev->device->of_node; @@ -2812,8 +3131,13 @@ static void google_set_throttling(struct bcl_device *bcl_dev) static int google_set_sub_pmic(struct bcl_device *bcl_dev) { +#if IS_ENABLED(CONFIG_SOC_GS201) + struct s2mpg13_platform_data *pdata_sub; + struct s2mpg13_dev *sub_dev = NULL; +#else struct s2mpg11_platform_data *pdata_sub; struct s2mpg11_dev *sub_dev = NULL; +#endif struct device_node *p_np; struct device_node *np = bcl_dev->device->of_node; struct i2c_client *i2c; @@ -2835,6 +3159,7 @@ static int google_set_sub_pmic(struct bcl_device *bcl_dev) return -ENODEV; } pdata_sub = dev_get_platdata(sub_dev->dev); + bcl_dev->sub_odpm = pdata_sub->meter; bcl_dev->sub_pmic_i2c = sub_dev->pmic; bcl_dev->sub_dev = sub_dev->dev; bcl_dev->bcl_lvl[OCP_WARN_GPU] = B2S_UPPER_LIMIT - THERMAL_HYST_LEVEL - @@ -2853,14 +3178,13 @@ static int google_set_sub_pmic(struct bcl_device *bcl_dev) return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, OCP_WARN_GPU, TS_OCP_WARN_GPU, - sub_dev->dev, "GPU_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, OCP_WARN_GPU, "GPU_OCP_IRQ", IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: GPU\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_GPU, TS_SOFT_OCP_WARN_GPU, - sub_dev->dev, "SOFT_GPU_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_GPU, "SOFT_GPU_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: SOFT_GPU\n"); return -ENODEV; @@ -2916,7 +3240,7 @@ static void google_set_intf_pmic_work(struct work_struct *work) bcl_dev->batt_psy = google_get_power_supply(bcl_dev); bcl_dev->bcl_tz[PMIC_SOC] = thermal_zone_of_sensor_register(bcl_dev->device, - TS_PMIC_SOC, bcl_dev, + PMIC_SOC, bcl_dev, &bcl_dev->bcl_ops[PMIC_SOC]); bcl_dev->bcl_ops[PMIC_SOC].get_temp = google_bcl_read_soc; bcl_dev->bcl_ops[PMIC_SOC].set_trips = google_bcl_set_soc; @@ -2942,7 +3266,7 @@ static void google_set_intf_pmic_work(struct work_struct *work) bcl_dev->bcl_ops[UVLO2].get_temp = google_bcl_uvlo2_read_temp; bcl_dev->bcl_ops[BATOILO].get_temp = google_bcl_batoilo_read_temp; - bcl_dev->bcl_tz[UVLO1] = thermal_zone_of_sensor_register(bcl_dev->device, TS_UVLO1, + bcl_dev->bcl_tz[UVLO1] = thermal_zone_of_sensor_register(bcl_dev->device, UVLO1, bcl_dev, &bcl_dev->bcl_ops[UVLO1]); if (IS_ERR(bcl_dev->bcl_tz[UVLO1])) { @@ -2952,7 +3276,7 @@ static void google_set_intf_pmic_work(struct work_struct *work) thermal_zone_device_enable(bcl_dev->bcl_tz[UVLO1]); thermal_zone_device_update(bcl_dev->bcl_tz[UVLO1], THERMAL_DEVICE_UP); } - bcl_dev->bcl_tz[UVLO2] = thermal_zone_of_sensor_register(bcl_dev->device, TS_UVLO2, + bcl_dev->bcl_tz[UVLO2] = thermal_zone_of_sensor_register(bcl_dev->device, UVLO2, bcl_dev, &bcl_dev->bcl_ops[UVLO2]); if (IS_ERR(bcl_dev->bcl_tz[UVLO2])) { @@ -2962,7 +3286,7 @@ static void google_set_intf_pmic_work(struct work_struct *work) thermal_zone_device_enable(bcl_dev->bcl_tz[UVLO2]); thermal_zone_device_update(bcl_dev->bcl_tz[UVLO2], THERMAL_DEVICE_UP); } - bcl_dev->bcl_tz[BATOILO] = thermal_zone_of_sensor_register(bcl_dev->device, TS_BATOILO, + bcl_dev->bcl_tz[BATOILO] = thermal_zone_of_sensor_register(bcl_dev->device, BATOILO, bcl_dev, &bcl_dev->bcl_ops[BATOILO]); if (IS_ERR(bcl_dev->bcl_tz[BATOILO])) { @@ -2973,6 +3297,7 @@ static void google_set_intf_pmic_work(struct work_struct *work) thermal_zone_device_update(bcl_dev->bcl_tz[BATOILO], THERMAL_DEVICE_UP); } + bcl_dev->ready = true; return; retry_init_work: @@ -2986,7 +3311,11 @@ static int google_set_intf_pmic(struct bcl_device *bcl_dev) struct device_node *p_np; struct device_node *np = bcl_dev->device->of_node; struct i2c_client *i2c; +#if IS_ENABLED(CONFIG_SOC_GS201) + struct s2mpg12_platform_data *pdata_main; +#else struct s2mpg10_platform_data *pdata_main; +#endif p_np = of_parse_phandle(np, "google,charger", 0); if (p_np) { i2c = of_find_i2c_device_by_node(p_np); @@ -3025,20 +3354,18 @@ static int google_set_intf_pmic(struct bcl_device *bcl_dev) bcl_dev->bcl_lvl[PMIC_140C] = PMIC_140C_UPPER_LIMIT - THERMAL_HYST_LEVEL; bcl_dev->bcl_lvl[PMIC_OVERHEAT] = PMIC_OVERHEAT_UPPER_LIMIT - THERMAL_HYST_LEVEL; - ret = google_bcl_register_irq(bcl_dev, PMIC_120C, TS_PMIC_120C, bcl_dev->main_dev, - "PMIC_120C", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, PMIC_120C, "PMIC_120C", IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: PMIC_120C\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, PMIC_140C, TS_PMIC_140C, bcl_dev->main_dev, - "PMIC_140C", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, PMIC_140C, "PMIC_140C", IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: PMIC_140C\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, PMIC_OVERHEAT, TS_PMIC_OVERHEAT, bcl_dev->main_dev, - "PMIC_OVERHEAT", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, PMIC_OVERHEAT, "PMIC_OVERHEAT", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: PMIC_OVERHEAT\n"); return -ENODEV; @@ -3049,8 +3376,13 @@ static int google_set_intf_pmic(struct bcl_device *bcl_dev) static int google_set_main_pmic(struct bcl_device *bcl_dev) { +#if IS_ENABLED(CONFIG_SOC_GS201) + struct s2mpg12_platform_data *pdata_main; + struct s2mpg12_dev *main_dev = NULL; +#else struct s2mpg10_platform_data *pdata_main; struct s2mpg10_dev *main_dev = NULL; +#endif u8 val; struct device_node *p_np; struct device_node *np = bcl_dev->device->of_node; @@ -3089,6 +3421,7 @@ static int google_set_main_pmic(struct bcl_device *bcl_dev) return -ENODEV; } pdata_main = dev_get_platdata(main_dev->dev); + bcl_dev->main_odpm = pdata_main->meter; /* request smpl_warn interrupt */ if (!gpio_is_valid(pdata_main->smpl_warn_pin)) { dev_err(bcl_dev->device, "smpl_warn GPIO NOT VALID\n"); @@ -3097,6 +3430,21 @@ static int google_set_main_pmic(struct bcl_device *bcl_dev) } bcl_dev->main_pmic_i2c = main_dev->pmic; bcl_dev->main_dev = main_dev->dev; +#if IS_ENABLED(CONFIG_SOC_GS201) + /* clear S2MPG_12 information every boot */ + /* see b/215371539 */ + S2MPG1X_READ(MAIN, bcl_dev, ret, S2MPG12_PM_OFFSRC1, &val); + pr_info("S2MPG12 OFFSRC1 : %#x\n", val); + bcl_dev->offsrc = val; + S2MPG1X_READ(MAIN, bcl_dev, ret, S2MPG12_PM_OFFSRC2, &val); + pr_info("S2MPG12 OFFSRC2 : %#x\n", val); + S2MPG1X_READ(MAIN, bcl_dev, ret, S2MPG12_PM_PWRONSRC, &val); + pr_info("S2MPG12 PWRONSRC: %#x\n", val); + bcl_dev->pwronsrc = val; + S2MPG1X_WRITE(MAIN, bcl_dev, ret, S2MPG12_PM_OFFSRC1, 0); + S2MPG1X_WRITE(MAIN, bcl_dev, ret, S2MPG12_PM_OFFSRC2, 0); + S2MPG1X_WRITE(MAIN, bcl_dev, ret, S2MPG12_PM_PWRONSRC, 0); +#else bcl_dev->main_pmic_i2c = main_dev->pmic; /* clear S2MPG_10 information every boot */ /* see b/166671802#comment34 and b/195455000 */ @@ -3108,6 +3456,7 @@ static int google_set_main_pmic(struct bcl_device *bcl_dev) bcl_dev->pwronsrc = val; S2MPG1X_WRITE(MAIN, bcl_dev, ret, S2MPG10_PM_OFFSRC, 0); S2MPG1X_WRITE(MAIN, bcl_dev, ret, S2MPG10_PM_PWRONSRC, 0); +#endif bcl_dev->bcl_irq[SMPL_WARN] = gpio_to_irq(pdata_main->smpl_warn_pin); irq_set_status_flags(bcl_dev->bcl_irq[SMPL_WARN], IRQ_DISABLE_UNLAZY); bcl_dev->bcl_pin[SMPL_WARN] = pdata_main->smpl_warn_pin; @@ -3145,45 +3494,44 @@ static int google_set_main_pmic(struct bcl_device *bcl_dev) bcl_dev->bcl_ops[OCP_WARN_TPU].get_temp = ocp_tpu_read_current; bcl_dev->bcl_ops[SOFT_OCP_WARN_TPU].get_temp = soft_ocp_tpu_read_current; if (!bypass_smpl_warn) { - ret = google_bcl_register_irq(bcl_dev, SMPL_WARN, TS_SMPL_WARN, main_dev->dev, - "SMPL_WARN_IRQ", IRQF_TRIGGER_FALLING); + ret = google_bcl_register_irq(bcl_dev, SMPL_WARN, "SMPL_WARN_IRQ", + IRQF_TRIGGER_FALLING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: SMPL_WARN\n"); return -ENODEV; } } - ret = google_bcl_register_irq(bcl_dev, OCP_WARN_CPUCL1, TS_OCP_WARN_CPUCL1, main_dev->dev, - "CPU1_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, OCP_WARN_CPUCL1, "CPU1_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: CPUCL1\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, OCP_WARN_CPUCL2, TS_OCP_WARN_CPUCL2, main_dev->dev, - "CPU2_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, OCP_WARN_CPUCL2, "CPU2_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: CPUCL2\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_CPUCL1, TS_SOFT_OCP_WARN_CPUCL1, - main_dev->dev, "SOFT_CPU1_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_CPUCL1, "SOFT_CPU1_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: SOFT_CPUCL1\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_CPUCL2, TS_SOFT_OCP_WARN_CPUCL2, - main_dev->dev, "SOFT_CPU2_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_CPUCL2, "SOFT_CPU2_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: SOFT_CPUCL2\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, OCP_WARN_TPU, TS_OCP_WARN_TPU, main_dev->dev, - "TPU_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, OCP_WARN_TPU, "TPU_OCP_IRQ", IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: TPU\n"); return -ENODEV; } - ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_TPU, TS_SOFT_OCP_WARN_TPU, - main_dev->dev, "SOFT_TPU_OCP_IRQ", IRQF_TRIGGER_RISING); + ret = google_bcl_register_irq(bcl_dev, SOFT_OCP_WARN_TPU, "SOFT_TPU_OCP_IRQ", + IRQF_TRIGGER_RISING); if (ret < 0) { dev_err(bcl_dev->device, "bcl_register fail: SOFT_TPU\n"); return -ENODEV; @@ -3298,6 +3646,8 @@ static void google_bcl_parse_dtree(struct bcl_device *bcl_dev) bcl_dev->cpu1_clkdivstep = ret ? 0 : val; ret = of_property_read_u32(np, "cpu0_clkdivstep", &val); bcl_dev->cpu0_clkdivstep = ret ? 0 : val; + ret = of_property_read_u32(np, "odpm_ratio", &val); + bcl_dev->odpm_ratio = (ret || !val) ? 2 : val; bcl_dev->vdroop1_pin = of_get_gpio(np, 0); bcl_dev->vdroop2_pin = of_get_gpio(np, 1); if (google_bcl_init_clk_div(bcl_dev, CPU2, bcl_dev->cpu2_clkdivstep) != 0) @@ -3321,6 +3671,7 @@ static int google_bcl_probe(struct platform_device *pdev) INIT_DELAYED_WORK(&bcl_dev->init_work, google_set_intf_pmic_work); platform_set_drvdata(pdev, bcl_dev); + bcl_dev->ready = false; ret = google_bcl_init_instruction(bcl_dev); if (ret < 0) goto bcl_soc_probe_exit; @@ -3336,6 +3687,7 @@ static int google_bcl_probe(struct platform_device *pdev) goto bcl_soc_probe_exit; schedule_delayed_work(&bcl_dev->init_work, msecs_to_jiffies(THERMAL_DELAY_INIT_MS)); bcl_dev->enabled = true; + google_init_debugfs(bcl_dev); return 0; @@ -3349,6 +3701,7 @@ static int google_bcl_remove(struct platform_device *pdev) struct bcl_device *bcl_dev = platform_get_drvdata(pdev); pmic_device_destroy(bcl_dev->mitigation_dev->devt); + debugfs_remove_recursive(bcl_dev->debug_entry); google_bcl_remove_thermal(bcl_dev); return 0; diff --git a/drivers/thermal/google/s2mpg13_spmic_thermal.c b/drivers/thermal/google/s2mpg13_spmic_thermal.c new file mode 100644 index 000000000000..cdd6a43637d3 --- /dev/null +++ b/drivers/thermal/google/s2mpg13_spmic_thermal.c @@ -0,0 +1,819 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * s2mpg13_spmic_thermal.c S2MPG13 Sub-PMIC thermistor driver + * + * Copyright (c) 2021, Google LLC. All rights reserved. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_core.h" + +#define GTHERM_CHAN_NUM 8 +#define SENSOR_WAIT_SLEEP_MS 50 +#define NTC_UPDATE_MIN_DELAY_US 100 +#define NTC_UPDATE_MAX_DELAY_US 10000 + +struct s2mpg13_spmic_thermal_sensor { + struct s2mpg13_spmic_thermal_chip *chip; + struct thermal_zone_device *tzd; + unsigned int adc_chan; + bool thr_triggered; + int emul_temperature; + int ot_irq; + int ut_irq; +}; + +struct s2mpg13_spmic_thermal_chip { + struct device *dev; + struct i2c_client *meter_i2c; + struct i2c_client *mt_trim_i2c; + struct mutex adc_chan_lock; + struct s2mpg13_dev *iodev; + struct s2mpg13_spmic_thermal_sensor sensor[GTHERM_CHAN_NUM]; + u8 adc_chan_en; + struct kobject *kobjs[GTHERM_CHAN_NUM]; + struct kthread_worker *wq; + struct kthread_delayed_work wait_sensor_work; + bool sensors_ready; +}; + +/** + * struct s2mpg13_spmic_thermal_map_pt - Map data representation for ADC + * @volt: Represent the ADC voltage data. + * @temp: Represent the temperature for given volt. + */ +struct adc_map_pt { + int volt; + int temp; +}; + +/* + * voltage to temperature table organized descending in voltage, + * ascending in temperature. + */ +static const struct adc_map_pt s2mpg13_adc_map[] = { + { 0xF8D, -26428 }, { 0xF6A, -21922 }, { 0xF29, -15958 }, + { 0xEE4, -11060 }, { 0xE9D, -6890 }, { 0xE3F, -2264 }, + { 0xDBF, 2961 }, { 0xD33, 7818 }, { 0xC97, 12525 }, + { 0xBF5, 16945 }, { 0xB3A, 21623 }, { 0xA42, 27431 }, + { 0x7F1, 40631 }, { 0x734, 44960 }, { 0x66B, 49757 }, + { 0x5A3, 54854 }, { 0x4EE, 59898 }, { 0x446, 65076 }, + { 0x43A, 65779 }, { 0x430, 65856 }, { 0x3C3, 69654 }, + { 0x3BD, 69873 }, { 0x33B, 74910 }, { 0x2BB, 80691 }, + { 0x259, 85844 }, { 0x206, 90915 }, { 0x1CE, 94873 }, + { 0x191, 99720 }, { 0x160, 104216 }, { 0x12E, 109531 }, + { 0xF9, 116445 }, { 0xD7, 121600 }, { 0x9F, 131839 }, +}; + +/* + * Convert the input voltage to a temperature using linear interpretation + * from the lookup table. + */ +static int s2mpg13_map_volt_temp(int input) +{ + int low = 0; + int high = ARRAY_SIZE(s2mpg13_adc_map) - 1; + int mid = 0; + + if (s2mpg13_adc_map[low].volt <= input) + return s2mpg13_adc_map[low].temp; + else if (s2mpg13_adc_map[high].volt >= input) + return s2mpg13_adc_map[high].temp; + + /* Binary search, value will be between index low and low - 1 */ + while (low <= high) { + mid = (low + high) / 2; + if (s2mpg13_adc_map[mid].volt < input) + high = mid - 1; + else if (s2mpg13_adc_map[mid].volt > input) + low = mid + 1; + else + return s2mpg13_adc_map[mid].temp; + } + + return s2mpg13_adc_map[low].temp + + mult_frac(s2mpg13_adc_map[low - 1].temp - s2mpg13_adc_map[low].temp, + input - s2mpg13_adc_map[low].volt, + s2mpg13_adc_map[low - 1].volt - s2mpg13_adc_map[low].volt); +} + +/* + * Convert the temperature to voltage to a temperature using linear interpretation + * from the lookup table. + */ +static int s2mpg13_map_temp_volt(int input) +{ + int low = 0; + int high = ARRAY_SIZE(s2mpg13_adc_map) - 1; + int mid = 0; + + if (s2mpg13_adc_map[low].temp >= input) + return s2mpg13_adc_map[low].volt; + else if (s2mpg13_adc_map[high].temp <= input) + return s2mpg13_adc_map[high].volt; + + /* Binary search, value will between index low and low - 1 */ + while (low <= high) { + mid = (low + high) / 2; + if (s2mpg13_adc_map[mid].temp < input) + low = mid + 1; + else if (s2mpg13_adc_map[mid].temp > input) + high = mid - 1; + else + return s2mpg13_adc_map[mid].volt; + } + return s2mpg13_adc_map[low].volt + + mult_frac(s2mpg13_adc_map[low - 1].volt - s2mpg13_adc_map[low].volt, + input - s2mpg13_adc_map[low].temp, + s2mpg13_adc_map[low - 1].temp - s2mpg13_adc_map[low].temp); +} + +static int s2mpg13_spmic_thermal_read_raw(struct s2mpg13_spmic_thermal_sensor *s, int *raw) +{ + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal = s->chip; + u8 data_buf[S2MPG13_METER_NTC_BUF]; + u8 reg = S2MPG13_METER_LPF_DATA_NTC0_1 + S2MPG13_METER_NTC_BUF * s->adc_chan; + + int ret = s2mpg13_bulk_read(s2mpg13_spmic_thermal->meter_i2c, reg, S2MPG13_METER_NTC_BUF, + data_buf); + if (ret) + return ret; + + *raw = data_buf[0] + ((data_buf[1] & 0xf) << 8); + + // All 0 usually means not ready + if (*raw == 0) + return -EBUSY; + + return ret; +} + +/* + * Configure NTC channels in thermistor engine. + */ +static int s2mpg13_spmic_set_ntc_channels( + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal, u8 adc_ch_en) +{ + int ret = 0; + struct device *dev = s2mpg13_spmic_thermal->dev; + struct i2c_client *meter_i2c = s2mpg13_spmic_thermal->meter_i2c; + struct i2c_client *mt_trim_i2c = s2mpg13_spmic_thermal->mt_trim_i2c; + + dev_info(dev, "Applying NTC... disabling odpm [s2mpg13]\n"); + + /* workaround suggested in b/200582715 for NTC channel update */ + ret = s2mpg13_write_reg(mt_trim_i2c, S2MPG13_MT_TRIM_COMMON2, 0x00); + if (ret) + goto err; + + usleep_range(NTC_UPDATE_MIN_DELAY_US, NTC_UPDATE_MAX_DELAY_US); + ret = s2mpg13_write_reg(mt_trim_i2c, S2MPG13_MT_TRIM_COMMON2, 0x80); + if (ret) + goto err; + + usleep_range(NTC_UPDATE_MIN_DELAY_US, NTC_UPDATE_MAX_DELAY_US); + ret = s2mpg13_write_reg(meter_i2c, S2MPG13_METER_CTRL3, 0x00); + if (ret) + goto err; + + usleep_range(NTC_UPDATE_MIN_DELAY_US, NTC_UPDATE_MAX_DELAY_US); + ret = s2mpg13_write_reg(mt_trim_i2c, S2MPG13_MT_TRIM_COMMON2, 0x00); + if (ret) + goto err; + + usleep_range(NTC_UPDATE_MIN_DELAY_US, NTC_UPDATE_MAX_DELAY_US); + ret = s2mpg13_write_reg(mt_trim_i2c, S2MPG13_MT_TRIM_COMMON2, 0x80); + if (ret) + goto err; + + usleep_range(NTC_UPDATE_MIN_DELAY_US, NTC_UPDATE_MAX_DELAY_US); + ret = s2mpg13_write_reg(meter_i2c, S2MPG13_METER_CTRL3, adc_ch_en); + if (ret) + goto err; + + msleep(SENSOR_WAIT_SLEEP_MS); + + dev_info(dev, "Set NTC channels (adc_ch_en : 0x%x\n)", adc_ch_en); + + /* b/228112807, we need to re-enable the meter for the odpm. */ + ret = s2mpg13_update_reg(meter_i2c, S2MPG13_METER_CTRL1, + METER_EN_MASK, METER_EN_MASK); + if (ret) + dev_info(dev, "Failed to re-enable odpm [s2mpg13] :(\n"); + else + dev_info(dev, "Re-enabled odpm [s2mpg13] :)\n"); + + return ret; + +err: + s2mpg13_write_reg(meter_i2c, S2MPG13_METER_CTRL3, 0x00); + dev_err(dev, "Failed to set NTC channels (adc_ch_en : 0x%x\n)", adc_ch_en); + return ret; +} + +/* + * Get temperature for given tz. + */ +static int s2mpg13_spmic_thermal_get_temp(void *data, int *temp) +{ + struct s2mpg13_spmic_thermal_sensor *s = data; + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal = s->chip; + int raw, ret = 0; + u8 mask = 0x1; + u8 data_buf[S2MPG13_METER_NTC_BUF]; + u8 reg = S2MPG13_METER_LPF_DATA_NTC0_1 + + S2MPG13_METER_NTC_BUF * s->adc_chan; + + if (!s2mpg13_spmic_thermal->sensors_ready) + return -EAGAIN; + + mutex_lock(&s2mpg13_spmic_thermal->adc_chan_lock); + if (s->emul_temperature) + goto emul_temp_exit; + + if (!(s2mpg13_spmic_thermal->adc_chan_en & (mask << s->adc_chan))) { + ret = -EIO; + goto err_exit; + } + + ret = s2mpg13_bulk_read(s2mpg13_spmic_thermal->meter_i2c, reg, + S2MPG13_METER_NTC_BUF, data_buf); + raw = data_buf[0] + ((data_buf[1] & 0xf) << 8); + *temp = s2mpg13_map_volt_temp(raw); + + mutex_unlock(&s2mpg13_spmic_thermal->adc_chan_lock); + return ret; + +emul_temp_exit: + *temp = s->emul_temperature; + +err_exit: + mutex_unlock(&s2mpg13_spmic_thermal->adc_chan_lock); + return ret; +} + +/* + * Set monitor window for given tz. + */ +static int s2mpg13_spmic_thermal_set_trips(void *data, int low_temp, + int high_temp) +{ + struct s2mpg13_spmic_thermal_sensor *s = data; + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal = s->chip; + struct device *dev = s2mpg13_spmic_thermal->dev; + int emul_temp, low_volt, high_volt, ret = 0; + u8 low_raw, high_raw; + + if (!s2mpg13_spmic_thermal->sensors_ready) + return -EAGAIN; + + /* Set threshold to extreme value when emul_temp set */ + emul_temp = s->emul_temperature; + if (emul_temp) { + high_temp = INT_MAX; + low_temp = INT_MIN; + } + + low_volt = s2mpg13_map_temp_volt(low_temp); + low_raw = low_volt >> 4 & 0xFF; + ret = s2mpg13_write_reg(s2mpg13_spmic_thermal->meter_i2c, + S2MPG13_METER_NTC_UT_WARN0 + s->adc_chan, low_raw); + if (ret) + return ret; + + high_volt = s2mpg13_map_temp_volt(high_temp); + high_raw = high_volt >> 4 & 0xFF; + ret = s2mpg13_write_reg(s2mpg13_spmic_thermal->meter_i2c, + S2MPG13_METER_NTC_OT_WARN0 + s->adc_chan, high_raw); + if (ret) + return ret; + + dev_dbg_ratelimited(dev, + "low_temp(mdegC):%d, high_temp(mdegC):%d low_adc:%d high_adc:%d\n", + low_temp, high_temp, low_raw, high_raw); + + return 0; +} + +static int +s2mpg13_spmic_thermal_set_hot_trip(struct s2mpg13_spmic_thermal_sensor *s, int temp) +{ + int ret = 0; + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal = s->chip; + u8 raw = s2mpg13_map_temp_volt(temp) >> 4 & 0xFF; + struct device *dev = s2mpg13_spmic_thermal->dev; + + if (temp == THERMAL_TEMP_INVALID) + return -EINVAL; + + ret = s2mpg13_write_reg(s2mpg13_spmic_thermal->meter_i2c, + S2MPG13_METER_NTC_OT_FAULT0 + s->adc_chan, raw); + dev_info(dev, "Set sensor %d hot trip(mdegC):%d, ret:%d\n", s->adc_chan, temp, ret); + + return ret; +} + +/* + * Set temperature threshold for given tz, only critical threshold will be + * programmed as shutdown threshold. + */ +static int s2mpg13_spmic_thermal_set_trip_temp(void *data, int trip, int temp) +{ + struct s2mpg13_spmic_thermal_sensor *s = data; + const struct thermal_trip *trip_points; + int ret = 0; + + if (!s->chip->sensors_ready) + return -EAGAIN; + + trip_points = of_thermal_get_trip_points(s->tzd); + if (!trip_points) + return -EINVAL; + + if (trip_points[trip].type != THERMAL_TRIP_HOT) + return ret; + + /* Use THERMAL_TRIP_HOT for HW thermal shutdown */ + ret = s2mpg13_spmic_thermal_set_hot_trip(s, temp); + + return ret; +} + +/* + * Set emulation temperture for given tz. + */ +static int s2mpg13_spmic_thermal_set_emul_temp(void *data, int temp) +{ + struct s2mpg13_spmic_thermal_sensor *sensor = data; + int ret = 0; + u8 value, mask = 0x1; + + if (!sensor->chip->sensors_ready) + return -EAGAIN; + + mutex_lock(&sensor->chip->adc_chan_lock); + if (sensor->chip->adc_chan_en & (mask << sensor->adc_chan)) { + ret = s2mpg13_read_reg(sensor->chip->meter_i2c, S2MPG13_METER_CTRL3, &value); + if (ret) + goto err; + + if (temp) + value &= ~(mask << sensor->adc_chan); + else + value |= mask << sensor->adc_chan; + + ret = s2mpg13_spmic_set_ntc_channels(sensor->chip, value); + if (ret) + goto err; + } + sensor->emul_temperature = temp; + +err: + mutex_unlock(&sensor->chip->adc_chan_lock); + return ret; +} + +static void +s2mpg13_spmic_thermal_init(struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal) +{ + int i; + + mutex_init(&s2mpg13_spmic_thermal->adc_chan_lock); + + for (i = 0; i < GTHERM_CHAN_NUM; i++) { + s2mpg13_spmic_thermal->sensor[i].chip = s2mpg13_spmic_thermal; + s2mpg13_spmic_thermal->sensor[i].adc_chan = i; + } +} + +static struct thermal_zone_of_device_ops s2mpg13_spmic_thermal_ops = { + .get_temp = s2mpg13_spmic_thermal_get_temp, + .set_trips = s2mpg13_spmic_thermal_set_trips, + .set_trip_temp = s2mpg13_spmic_thermal_set_trip_temp, + .set_emul_temp = s2mpg13_spmic_thermal_set_emul_temp, +}; + +static ssize_t +tz_temp_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct thermal_zone_device *tzd = to_thermal_zone(dev); + + thermal_zone_device_update(tzd, THERMAL_EVENT_UNSPECIFIED); + + return sysfs_emit(buf, "%d\n", tzd->temperature); +} + +static DEVICE_ATTR_RO(tz_temp); + +static int s2mpg13_spmic_thermal_get_hot_temp(struct thermal_zone_device *tzd) +{ + int ntrips; + const struct thermal_trip *trips; + int i; + + ntrips = of_thermal_get_ntrips(tzd); + if (ntrips <= 0) + return THERMAL_TEMP_INVALID; + + trips = of_thermal_get_trip_points(tzd); + if (!trips) + return THERMAL_TEMP_INVALID; + + for (i = 0; i < ntrips; i++) { + if (of_thermal_is_trip_valid(tzd, i) && trips[i].type == THERMAL_TRIP_HOT) + return trips[i].temperature; + } + + return THERMAL_TEMP_INVALID; +} + +/* + * IRQ handler. + */ +static irqreturn_t s2mpg13_spmic_thermal_irq(int irq, void *data) +{ + struct s2mpg13_spmic_thermal_chip *chip = data; + struct device *dev = chip->dev; + int i; + + for (i = 0; i < GTHERM_CHAN_NUM; i++) { + if ((chip->sensor[i].ot_irq == irq) || (chip->sensor[i].ut_irq == irq)) { + dev_info_ratelimited(dev, "PMIC_THERM[%d] IRQ, %d ot_irq:%d\n", i, + irq, (chip->sensor[i].ot_irq == irq)); + thermal_zone_device_update(chip->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + return IRQ_HANDLED; + } + } + WARN(1, "Bad IRQ in thermal %d", irq); + return IRQ_NONE; +} + +/* + * Wait for sensors to be ready. + */ +static void s2mpg13_spmic_thermal_wait_sensor(struct kthread_work *work) +{ + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal = + container_of(work, struct s2mpg13_spmic_thermal_chip, wait_sensor_work.work); + struct device *dev = s2mpg13_spmic_thermal->dev; + u8 mask = 0x1; + u8 adc_chan_en = s2mpg13_spmic_thermal->adc_chan_en; + int raw, ret, i, j = 64000 / SENSOR_WAIT_SLEEP_MS; + + mutex_lock(&s2mpg13_spmic_thermal->adc_chan_lock); + ret = s2mpg13_spmic_set_ntc_channels(s2mpg13_spmic_thermal, adc_chan_en); + if (ret) + goto err; + mutex_unlock(&s2mpg13_spmic_thermal->adc_chan_lock); + + for (i = 0; i < GTHERM_CHAN_NUM; i++, mask <<= 1) { + if (!(s2mpg13_spmic_thermal->adc_chan_en & mask)) + continue; + /* Wait for longest refresh period */ + while (j--) { + ret = s2mpg13_spmic_thermal_read_raw(&s2mpg13_spmic_thermal->sensor[i], + &raw); + dev_info(dev, "Sensor %d raw:0x%x\n", i, raw); + if (ret != -EBUSY) + break; + dev_info(dev, "Sensor %d not ready, retry...\n", i); + msleep(SENSOR_WAIT_SLEEP_MS); + } + if (j < 0) + dev_warn(dev, "Sensor %d timeout, give up...\n", i); + + thermal_zone_device_update(s2mpg13_spmic_thermal->sensor[i].tzd, + THERMAL_EVENT_UNSPECIFIED); + } + + s2mpg13_spmic_thermal->sensors_ready = true; + return; + +err: + dev_err(dev, "Failed to set NTC channels during initialization\n"); + s2mpg13_spmic_thermal->adc_chan_en = 0x00; + mutex_unlock(&s2mpg13_spmic_thermal->adc_chan_lock); +} + +/* + * Unregister thermal zones. + */ +static void +s2mpg13_spmic_thermal_unregister_tzd(struct s2mpg13_spmic_thermal_chip *chip) +{ + int i; + struct device *dev = chip->dev; + + for (i = 0; i < GTHERM_CHAN_NUM; i++) { + dev_info(dev, "Unregistering %d sensor\n", i); + devm_thermal_zone_of_sensor_unregister(chip->dev, + chip->sensor[i].tzd); + } +} + +/* + * Register thermal zones. + */ +static int +s2mpg13_spmic_thermal_register_tzd(struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal) +{ + unsigned int i; + struct thermal_zone_device *tzd; + struct device *dev = s2mpg13_spmic_thermal->dev; + u8 mask = 0x1; + int temp, ret = 0; + + for (i = 0; i < GTHERM_CHAN_NUM; i++, mask <<= 1) { + dev_info(dev, "Registering %d sensor\n", i); + tzd = devm_thermal_zone_of_sensor_register(s2mpg13_spmic_thermal->dev, i, + &s2mpg13_spmic_thermal->sensor[i], + &s2mpg13_spmic_thermal_ops); + + if (IS_ERR(tzd)) { + dev_err(dev, + "Error registering thermal zone:%ld for channel:%d\n", + PTR_ERR(tzd), i); + return -EINVAL; + } + s2mpg13_spmic_thermal->sensor[i].tzd = tzd; + if (s2mpg13_spmic_thermal->adc_chan_en & mask) + thermal_zone_device_enable(tzd); + else + thermal_zone_device_disable(tzd); + + ret = device_create_file(&tzd->device, &dev_attr_tz_temp); + if (ret) { + dev_err(dev, + "Error creating tz_temp node for thermal zone:%ld for channel:%d\n", + PTR_ERR(tzd), i); + return ret; + } + + temp = s2mpg13_spmic_thermal_get_hot_temp(tzd); + s2mpg13_spmic_thermal_set_hot_trip(&s2mpg13_spmic_thermal->sensor[i], temp); + } + + return ret; +} + +static const struct of_device_id s2mpg13_spmic_thermal_match_table[] = { + { .compatible = "google,s2mpg13-spmic-thermal" }, + {} +}; + +static int s2mpg13_spmic_thermal_get_dt_data(struct platform_device *pdev, + struct s2mpg13_spmic_thermal_chip *s2mpg13_spmic_thermal) +{ + struct device_node *node = pdev->dev.of_node; + struct device *dev = &pdev->dev; + const struct of_device_id *id; + + if (!node) + return -EINVAL; + + id = of_match_node(s2mpg13_spmic_thermal_match_table, node); + if (!id) + return -EINVAL; + + if (of_property_read_u8(node, "adc_chan_en", + &s2mpg13_spmic_thermal->adc_chan_en)) { + dev_err(dev, "Cannot read adc_chan_en\n"); + return -EINVAL; + } + + return 0; +} + +static ssize_t +adc_chan_en_show(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg13_spmic_thermal_chip *chip = platform_get_drvdata(pdev); + int ret; + u8 value; + + if (!chip->sensors_ready) + return -EAGAIN; + + mutex_lock(&chip->adc_chan_lock); + ret = s2mpg13_read_reg(chip->meter_i2c, S2MPG13_METER_CTRL3, &value); + mutex_unlock(&chip->adc_chan_lock); + + return ret ? ret : sysfs_emit(buf, "0x%02X\n", value); +} + +static ssize_t +adc_chan_en_store(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + int i, ret; + struct platform_device *pdev = to_platform_device(dev); + struct s2mpg13_spmic_thermal_chip *chip = platform_get_drvdata(pdev); + u8 value, mask = 0x1; + + if (!chip->sensors_ready) + return -EAGAIN; + + ret = sscanf(buf, "%hhx", &value); + if (ret != 1) + return -EINVAL; + + mutex_lock(&chip->adc_chan_lock); + ret = s2mpg13_spmic_set_ntc_channels(chip, value); + if (ret) + goto err; + + chip->adc_chan_en = value; + mutex_unlock(&chip->adc_chan_lock); + + for (i = 0; i < GTHERM_CHAN_NUM; i++, mask <<= 1) { + if (chip->adc_chan_en & mask) + thermal_zone_device_enable(chip->sensor[i].tzd); + else + thermal_zone_device_disable(chip->sensor[i].tzd); + } + + return count; + +err: + chip->adc_chan_en = 0x00; + mutex_unlock(&chip->adc_chan_lock); + return ret; +} + +static DEVICE_ATTR_RW(adc_chan_en); + +static struct attribute *s2mpg13_spmic_dev_attrs[] = { + &dev_attr_adc_chan_en.attr, + NULL +}; + +ATTRIBUTE_GROUPS(s2mpg13_spmic_dev); + +static int s2mpg13_spmic_thermal_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct s2mpg13_spmic_thermal_chip *chip; + int ret = 0; + struct s2mpg13_dev *iodev = dev_get_drvdata(pdev->dev.parent); + struct s2mpg13_platform_data *pdata; + int irq_base, i; + int irq_count = 0; + + chip = devm_kzalloc(&pdev->dev, sizeof(struct s2mpg13_spmic_thermal_chip), + GFP_KERNEL); + if (!chip) + return -ENOMEM; + + if (!iodev) { + dev_err(dev, "Failed to get parent s2mpg13_dev\n"); + return -EINVAL; + } + pdata = iodev->pdata; + if (!pdata) { + dev_err(dev, "Failed to get s2mpg13_platform_data\n"); + return -EINVAL; + } + + chip->dev = dev; + chip->meter_i2c = iodev->meter; + chip->mt_trim_i2c = iodev->mt_trim; + chip->iodev = iodev; + chip->sensors_ready = false; + ret = s2mpg13_spmic_thermal_get_dt_data(pdev, chip); + if (ret) { + dev_err(dev, "s2mpg13_spmic_thermal get dt data failed\n"); + return ret; + } + + irq_base = pdata->irq_base; + if (irq_base <= 0) { + dev_err(dev, "Failed to get irq base %d\n", irq_base); + ret = -ENODEV; + goto fail; + } + + s2mpg13_spmic_thermal_init(chip); + + /* Set sampling rate */ + s2mpg13_update_reg(chip->meter_i2c, S2MPG13_METER_CTRL1, + NTC_0P15625HZ << NTC_SAMP_RATE_SHIFT, + NTC_SAMP_RATE_MASK); + + ret = s2mpg13_spmic_thermal_register_tzd(chip); + if (ret) { + dev_err(dev, "Failed to register with of thermal\n"); + goto disable_ntc; + } + + /* Setup IRQ */ + for (i = 0; i < GTHERM_CHAN_NUM; i++) { + chip->sensor[i].ot_irq = + irq_base + S2MPG13_IRQ_NTC_WARN_OT_CH1_INT7 + i; + + chip->sensor[i].ut_irq = + irq_base + S2MPG13_IRQ_NTC_WARN_UT_CH1_INT8 + i; + + ret = devm_request_threaded_irq(&pdev->dev, chip->sensor[i].ot_irq, + NULL, s2mpg13_spmic_thermal_irq, + 0, "PMIC_THERM_IRQ", chip); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to request NTC[%d] IRQ: %d: %d\n", i, + chip->sensor[i].ot_irq, ret); + goto free_irq_tz; + } + irq_count++; + + ret = devm_request_threaded_irq(&pdev->dev, chip->sensor[i].ut_irq, + NULL, s2mpg13_spmic_thermal_irq, + 0, "PMIC_THERM_IRQ", chip); + if (ret < 0) { + dev_err(&pdev->dev, + "Failed to request NTC[%d] IRQ: %d: %d\n", i, + chip->sensor[i].ut_irq, ret); + goto free_irq_tz; + } + irq_count++; + } + + chip->wq = kthread_create_worker(0, "spmic-init"); + if (IS_ERR_OR_NULL(chip->wq)) { + ret = PTR_ERR(chip->wq); + goto free_irq_tz; + } + + kthread_init_delayed_work(&chip->wait_sensor_work, s2mpg13_spmic_thermal_wait_sensor); + + platform_set_drvdata(pdev, chip); + + dev_info(dev, "probe done, now wait for sensors\n"); + kthread_mod_delayed_work(chip->wq, &chip->wait_sensor_work, 0); + + return ret; + +free_irq_tz: + if (irq_count & 0x01) + devm_free_irq(&pdev->dev, chip->sensor[i].ot_irq, chip); + + while (--i >= 0) { + devm_free_irq(&pdev->dev, chip->sensor[i].ot_irq, chip); + devm_free_irq(&pdev->dev, chip->sensor[i].ut_irq, chip); + } +disable_ntc: + s2mpg13_spmic_set_ntc_channels(chip, 0x00); +fail: + return ret; +} + +static int s2mpg13_spmic_thermal_remove(struct platform_device *pdev) +{ + int i; + struct s2mpg13_spmic_thermal_chip *chip = platform_get_drvdata(pdev); + + mutex_lock(&chip->adc_chan_lock); + s2mpg13_spmic_set_ntc_channels(chip, 0x00); + chip->adc_chan_en = 0x00; + mutex_unlock(&chip->adc_chan_lock); + + kthread_cancel_delayed_work_sync(&chip->wait_sensor_work); + kthread_destroy_worker(chip->wq); + for (i = 0; i < GTHERM_CHAN_NUM; i++) { + devm_free_irq(&pdev->dev, chip->sensor[i].ot_irq, chip); + devm_free_irq(&pdev->dev, chip->sensor[i].ut_irq, chip); + } + s2mpg13_spmic_thermal_unregister_tzd(chip); + + return 0; +} + +static struct platform_driver s2mpg13_spmic_thermal_driver = { + .driver = { + .name = "s2mpg13-spmic-thermal", + .dev_groups = s2mpg13_spmic_dev_groups, + .owner = THIS_MODULE, + }, + .probe = s2mpg13_spmic_thermal_probe, + .remove = s2mpg13_spmic_thermal_remove, +}; +module_platform_driver(s2mpg13_spmic_thermal_driver); + +MODULE_DESCRIPTION("Google LLC GS201 SPMIC Thermal Driver"); +MODULE_AUTHOR("Sayanna Chandula "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:google,s2mpg13_thermal"); diff --git a/drivers/thermal/samsung/Makefile b/drivers/thermal/samsung/Makefile index 60e8d1db54a8..0369dc71d528 100644 --- a/drivers/thermal/samsung/Makefile +++ b/drivers/thermal/samsung/Makefile @@ -5,10 +5,10 @@ obj-$(CONFIG_EXYNOS_THERMAL) += exynos_thermal.o exynos_thermal-y := exynos_tmu.o -obj-$(CONFIG_GS101_THERMAL_V2) += gs101_thermal.o -gs101_thermal-y += gs101_tmu_v2.o -gs101_thermal-y += exynos_acpm_tmu.o -gs101_thermal-$(CONFIG_EXYNOS_CPU_THERMAL) += exynos_cpu_cooling.o -gs101_thermal-$(CONFIG_ISP_THERMAL) += isp_cooling.o +obj-$(CONFIG_GS101_THERMAL_V2) += gs_thermal.o +gs_thermal-y += gs_tmu_v2.o +gs_thermal-y += exynos_acpm_tmu.o +gs_thermal-$(CONFIG_EXYNOS_CPU_THERMAL) += exynos_cpu_cooling.o +gs_thermal-$(CONFIG_ISP_THERMAL) += isp_cooling.o obj-$(CONFIG_GPU_THERMAL) += gpu_cooling.o diff --git a/drivers/thermal/samsung/exynos_cpu_cooling.c b/drivers/thermal/samsung/exynos_cpu_cooling.c index bcd196ef72ce..5bdb58baaccc 100644 --- a/drivers/thermal/samsung/exynos_cpu_cooling.c +++ b/drivers/thermal/samsung/exynos_cpu_cooling.c @@ -30,8 +30,9 @@ #include #if IS_ENABLED(CONFIG_PIXEL_EM) -struct em_perf_domain **exynos_cpu_cooling_cpu_to_em_pd; -EXPORT_SYMBOL_GPL(exynos_cpu_cooling_cpu_to_em_pd); +#include "../../soc/google/vh/include/pixel_em.h" +struct pixel_em_profile **exynos_cpu_cooling_pixel_em_profile; +EXPORT_SYMBOL_GPL(exynos_cpu_cooling_pixel_em_profile); #endif /* @@ -381,16 +382,20 @@ static u32 cpu_freq_to_power(struct exynos_cpu_cooling_device *cpufreq_cdev, #if IS_ENABLED(CONFIG_PIXEL_EM) { - struct em_perf_domain **cpu_to_em_pd = READ_ONCE(exynos_cpu_cooling_cpu_to_em_pd); - if (cpu_to_em_pd) { - int first_cpu = cpumask_first(cpufreq_cdev->policy->related_cpus); - struct em_perf_domain *pd = cpu_to_em_pd[first_cpu]; - - for (i = 0; i < (pd->nr_perf_states - 1); i++) - if (freq <= pd->table[i].frequency) - break; - - return pd->table[i].power; + struct pixel_em_profile **profile_ptr_snapshot; + profile_ptr_snapshot = READ_ONCE(exynos_cpu_cooling_pixel_em_profile); + if (profile_ptr_snapshot) { + struct pixel_em_profile *profile = READ_ONCE(*profile_ptr_snapshot); + if (profile) { + int cpu = cpumask_first(cpufreq_cdev->policy->related_cpus); + struct pixel_em_cluster *cluster = profile->cpu_to_cluster[cpu]; + int opp_id; + for (opp_id = 0; opp_id < (cluster->num_opps - 1); opp_id++) { + if (freq <= cluster->opps[opp_id].freq) + break; + } + return cluster->opps[opp_id].power; + } } } #endif @@ -412,16 +417,20 @@ static u32 cpu_power_to_freq(struct exynos_cpu_cooling_device *cpufreq_cdev, #if IS_ENABLED(CONFIG_PIXEL_EM) { - struct em_perf_domain **cpu_to_em_pd = READ_ONCE(exynos_cpu_cooling_cpu_to_em_pd); - if (cpu_to_em_pd) { - int first_cpu = cpumask_first(cpufreq_cdev->policy->related_cpus); - struct em_perf_domain *pd = cpu_to_em_pd[first_cpu]; - - for (i = 0; i < (pd->nr_perf_states - 1); i++) - if (power <= pd->table[i].power) - break; - - return pd->table[i].frequency; + struct pixel_em_profile **profile_ptr_snapshot; + profile_ptr_snapshot = READ_ONCE(exynos_cpu_cooling_pixel_em_profile); + if (profile_ptr_snapshot) { + struct pixel_em_profile *profile = READ_ONCE(*profile_ptr_snapshot); + if (profile) { + int cpu = cpumask_first(cpufreq_cdev->policy->related_cpus); + struct pixel_em_cluster *cluster = profile->cpu_to_cluster[cpu]; + int opp_id; + for (opp_id = 0; opp_id < (cluster->num_opps - 1); opp_id++) { + if (power <= cluster->opps[opp_id].power) + break; + } + return cluster->opps[opp_id].freq; + } } } #endif diff --git a/drivers/thermal/samsung/gs_tmu.h b/drivers/thermal/samsung/gs_tmu.h new file mode 100644 index 000000000000..a040422299af --- /dev/null +++ b/drivers/thermal/samsung/gs_tmu.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * gs_tmu.h - Samsung GS TMU (Thermal Management Unit) + * + * Copyright (C) 2019 Samsung Electronics + * Hyeonseong Gil + */ + +#ifndef _GS_TMU_H +#define _GS_TMU_H +#include +#include +#include + +#define MCELSIUS 1000 + +struct gs_pi_param { + s64 err_integral; + int trip_switch_on; + int trip_control_temp; + + u32 sustainable_power; + s32 k_po; + s32 k_pu; + s32 k_i; + s32 i_max; + s32 integral_cutoff; + + int polling_delay_on; + int polling_delay_off; + + bool switched_on; +}; + +/** + * struct gs_tmu_data : A structure to hold the private data of the TMU + driver + * @id: identifier of the one instance of the TMU controller. + * @base: base address of the single instance of the TMU controller. + * @irq: irq number of the TMU controller. + * @soc: id of the SOC type. + * @irq_work: pointer to the irq work structure. + * @lock: lock to implement synchronization. + * @regulator: pointer to the TMU regulator structure. + * @reg_conf: pointer to structure to register with core thermal. + * @ntrip: number of supported trip points. + * @tmu_initialize: SoC specific TMU initialization method + * @tmu_control: SoC specific TMU control method + * @tmu_read: SoC specific TMU temperature read method + * @tmu_set_emulation: SoC specific TMU emulation setting method + * @tmu_clear_irqs: SoC specific TMU interrupts clearing method + */ +struct gs_tmu_data { + int id; + /* Throttle hotplug related variables */ + bool pause_enable; + unsigned int tmu_type; + int pause_threshold; + int resume_threshold; + bool hardlimit_enable; + int hardlimit_threshold; + int hardlimit_clr_threshold; + unsigned int hardlimit_cooling_state; + unsigned long max_cdev; + bool hotplug_enable; + int hotplug_in_threshold; + int hotplug_out_threshold; + bool cpu_hw_throttling_enable; + int cpu_hw_throttling_trigger_threshold; + int cpu_hw_throttling_clr_threshold; + int ppm_clr_throttle_level; + int ppm_throttle_level; + int mpmm_clr_throttle_level; + int mpmm_throttle_level; + int limited_frequency; + int limited_threshold; + int limited_threshold_release; + struct exynos_pm_qos_request thermal_limit_request; + bool limited; + void __iomem *base; + int irq; + struct kthread_worker hardlimit_worker; + struct kthread_worker thermal_worker; + struct kthread_worker pause_worker; + struct kthread_worker cpu_hw_throttle_worker; + struct kthread_work irq_work; + struct kthread_work pause_work; + struct kthread_work hardlimit_work; + struct kthread_work hotplug_work; + struct kthread_work cpu_hw_throttle_work; + struct kthread_delayed_work cpu_hw_throttle_init_work; + struct mutex lock; /* lock to protect gs tmu */ + struct thermal_zone_device *tzd; + struct bcl_device *bcl_dev; + unsigned int ntrip; + bool enabled; + struct thermal_cooling_device *cool_dev; + struct list_head node; + char tmu_name[THERMAL_NAME_LENGTH + 1]; + struct device_node *np; + bool is_paused; + bool is_hardlimited; + bool is_cpu_hotplugged_out; + bool is_cpu_hw_throttled; + int temperature; + bool use_pi_thermal; + struct kthread_delayed_work pi_work; + struct gs_pi_param *pi_param; + struct cpumask pause_cpus; + struct cpumask hotplug_cpus; + struct cpumask tmu_work_affinity; + struct cpumask hotplug_work_affinity; + char cpuhp_name[CPUHP_USER_NAME_LEN + 1]; + void *disable_stats; + void *hardlimit_stats; +}; + +enum throttling_stats_type { + DISABLE_STATS = 0, + HARDLIMIT_STATS, +}; + +struct throttling_stats { + spinlock_t lock; + int stats_type; + unsigned int disable_total_count; + unsigned int disable_state; + unsigned int hardlimit_total_count; + unsigned int hardlimit_state; + ktime_t last_time; + ktime_t *disable_time_in_state; + ktime_t *hardlimit_time_in_state; +}; + +#define TMU_INTPEND_P0 0x00F8 +#define TMU_INTPEND_REG(i) (TMU_INTPEND_P0 + 0x50 * (i)) + +#define TMU_SENSOR_PROBE_NUM 16 + +enum tmu_zone_t { + TMU_TOP = 0, + TMU_SUB = 1, + TMU_END = 2, +}; + +enum tmu_sensor_t { + TMU_P0_SENSOR = 0, + TMU_P1_SENSOR = 1, + TMU_P2_SENSOR = 2, + TMU_P3_SENSOR = 3, + TMU_P4_SENSOR = 4, + TMU_P5_SENSOR = 5, + TMU_P6_SENSOR = 6, + TMU_P7_SENSOR = 7, + TMU_P8_SENSOR = 8, + TMU_P9_SENSOR = 9, + TMU_P10_SENSOR = 10, + TMU_P11_SENSOR = 11, + TMU_P12_SENSOR = 12, + TMU_P13_SENSOR = 13, + TMU_P14_SENSOR = 14, + TMU_P15_SENSOR = 15, +}; + +#define TMU_P0_SENSOR_MASK (1 << TMU_P0_SENSOR) +#define TMU_P1_SENSOR_MASK (1 << TMU_P1_SENSOR) +#define TMU_P2_SENSOR_MASK (1 << TMU_P2_SENSOR) +#define TMU_P3_SENSOR_MASK (1 << TMU_P3_SENSOR) +#define TMU_P4_SENSOR_MASK (1 << TMU_P4_SENSOR) +#define TMU_P5_SENSOR_MASK (1 << TMU_P5_SENSOR) +#define TMU_P6_SENSOR_MASK (1 << TMU_P6_SENSOR) +#define TMU_P7_SENSOR_MASK (1 << TMU_P7_SENSOR) +#define TMU_P8_SENSOR_MASK (1 << TMU_P8_SENSOR) +#define TMU_P9_SENSOR_MASK (1 << TMU_P9_SENSOR) +#define TMU_P10_SENSOR_MASK (1 << TMU_P10_SENSOR) +#define TMU_P11_SENSOR_MASK (1 << TMU_P11_SENSOR) +#define TMU_P12_SENSOR_MASK (1 << TMU_P12_SENSOR) +#define TMU_P13_SENSOR_MASK (1 << TMU_P13_SENSOR) +#define TMU_P14_SENSOR_MASK (1 << TMU_P14_SENSOR) +#define TMU_P15_SENSOR_MASK (1 << TMU_P15_SENSOR) + +struct sensor_data { + enum tmu_sensor_t probe_id; +}; + +struct thermal_zone_data { + enum tmu_zone_t tmu_zone_id; + u16 sensors_mask; + struct sensor_data sensors[TMU_SENSOR_PROBE_NUM]; + u16 sensor_cnt; +}; + +enum thermal_pause_state { + THERMAL_RESUME = 0, + THERMAL_SUSPEND, +}; + +typedef int (*tpu_pause_cb)(enum thermal_pause_state action, void *data); + +void register_tpu_thermal_pause_cb(tpu_pause_cb tpu_cb, void *data); + +#endif /* _GS101_TMU_H */ diff --git a/drivers/thermal/samsung/gs101_tmu_v2.c b/drivers/thermal/samsung/gs_tmu_v2.c similarity index 86% rename from drivers/thermal/samsung/gs101_tmu_v2.c rename to drivers/thermal/samsung/gs_tmu_v2.c index 6c3def2f5073..816184526c60 100644 --- a/drivers/thermal/samsung/gs101_tmu_v2.c +++ b/drivers/thermal/samsung/gs_tmu_v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * gs101_tmu_v2.c - Samsung GS101 TMU (Thermal Management Unit) + * gs_tmu_v2.c - Samsung GS TMU (Thermal Management Unit) * * Copyright (C) 2019 Samsung Electronics * Hyeonseong Gil @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include @@ -58,13 +58,17 @@ #define frac_to_int(x) ((x) >> FRAC_BITS) #define INVALID_TRIP -1 +#define INVALID_CONTROL_TEMP -1 enum tmu_type_t { TMU_TYPE_CPU = 0, TMU_TYPE_GPU = 1, TMU_TYPE_ISP = 2, TMU_TYPE_TPU = 3, - TMU_TYPE_END = 4, +#if defined(CONFIG_SOC_GS201) + TMU_TYPE_AUR, +#endif + TMU_TYPE_END, }; enum tmu_grp_idx_t { @@ -74,9 +78,13 @@ enum tmu_grp_idx_t { TZ_GPU = 3, TZ_ISP = 4, TZ_TPU = 5, - TZ_END = 6, +#if defined(CONFIG_SOC_GS201) + TZ_AUR, +#endif + TZ_END, }; +#if defined(CONFIG_SOC_GS101) #define TZ_BIG_SENSOR_MASK (TMU_P0_SENSOR_MASK | \ TMU_P6_SENSOR_MASK | \ TMU_P7_SENSOR_MASK | \ @@ -125,7 +133,64 @@ static struct thermal_zone_data tz_config[] = { .sensors_mask = TZ_TPU_SENSOR_MASK, }, }; +#elif defined(CONFIG_SOC_GS201) +#define TZ_BIG_SENSOR_MASK (TMU_P0_SENSOR_MASK | \ + TMU_P7_SENSOR_MASK | \ + TMU_P9_SENSOR_MASK | \ + TMU_P10_SENSOR_MASK | \ + TMU_P11_SENSOR_MASK) +#define TZ_MID_SENSOR_MASK (TMU_P4_SENSOR_MASK | \ + TMU_P6_SENSOR_MASK) +#define TZ_LIT_SENSOR_MASK (TMU_P1_SENSOR_MASK | \ + TMU_P3_SENSOR_MASK) +#define TZ_GPU_SENSOR_MASK (TMU_P0_SENSOR_MASK | \ + TMU_P8_SENSOR_MASK | \ + TMU_P9_SENSOR_MASK | \ + TMU_P10_SENSOR_MASK | \ + TMU_P11_SENSOR_MASK | \ + TMU_P12_SENSOR_MASK | \ + TMU_P13_SENSOR_MASK) +#define TZ_ISP_SENSOR_MASK (TMU_P13_SENSOR_MASK | \ + TMU_P14_SENSOR_MASK | \ + TMU_P15_SENSOR_MASK) +#define TZ_TPU_SENSOR_MASK (TMU_P2_SENSOR_MASK | \ + TMU_P3_SENSOR_MASK | \ + TMU_P4_SENSOR_MASK | \ + TMU_P5_SENSOR_MASK) +#define TZ_AUR_SENSOR_MASK (TMU_P14_SENSOR_MASK | \ + TMU_P15_SENSOR_MASK) +static struct thermal_zone_data tz_config[] = { + [TZ_BIG] = { + .tmu_zone_id = TMU_TOP, + .sensors_mask = TZ_BIG_SENSOR_MASK, + }, + [TZ_MID] = { + .tmu_zone_id = TMU_TOP, + .sensors_mask = TZ_MID_SENSOR_MASK, + }, + [TZ_LIT] = { + .tmu_zone_id = TMU_TOP, + .sensors_mask = TZ_LIT_SENSOR_MASK, + }, + [TZ_GPU] = { + .tmu_zone_id = TMU_SUB, + .sensors_mask = TZ_GPU_SENSOR_MASK, + }, + [TZ_ISP] = { + .tmu_zone_id = TMU_TOP, + .sensors_mask = TZ_ISP_SENSOR_MASK, + }, + [TZ_TPU] = { + .tmu_zone_id = TMU_SUB, + .sensors_mask = TZ_TPU_SENSOR_MASK, + }, + [TZ_AUR] = { + .tmu_zone_id = TMU_SUB, + .sensors_mask = TZ_AUR_SENSOR_MASK, + }, +}; +#endif /** * mul_frac() - multiply two fixed-point numbers * @x: first multiplicand @@ -152,7 +217,7 @@ static inline s64 div_frac(s64 x, s64 y) return div_s64(x << FRAC_BITS, y); } -static atomic_t gs101_tmu_in_suspend; +static atomic_t gs_tmu_in_suspend; static struct acpm_tmu_cap cap; static unsigned int num_of_devices, suspended_count; @@ -219,7 +284,7 @@ static void disable_stats_update(struct throttling_stats *stats, spin_unlock(&stats->lock); } -static int gs101_tmu_tz_config_init(struct platform_device *pdev) +static int gs_tmu_tz_config_init(struct platform_device *pdev) { struct thermal_zone_data *tz_config_p; u16 cnt; @@ -253,6 +318,7 @@ static const char * const trace_suffix[] = { [HARD_LIMIT] = "hard_limit", [HOTPLUG] = "hotplug", [PAUSE] = "pause", + [DFS] = "dfs", }; #define MAX_TRACE_SUFFIX_STR_LEN (13) @@ -262,8 +328,8 @@ static const char * const trace_suffix[] = { update_thermal_trace_internal(pdata, feature, value); \ } while (0); -static void update_thermal_trace_internal(struct gs101_tmu_data *pdata, - enum thermal_feature feature, int value) +static void update_thermal_trace_internal(struct gs_tmu_data *pdata, enum thermal_feature feature, + int value) { char clock_name[THERMAL_NAME_LENGTH + MAX_TRACE_SUFFIX_STR_LEN + 1]; scnprintf(clock_name, (THERMAL_NAME_LENGTH + 1 + strlen(trace_suffix[feature])), @@ -271,7 +337,24 @@ static void update_thermal_trace_internal(struct gs101_tmu_data *pdata, trace_clock_set_rate(clock_name, value, raw_smp_processor_id()); } -static bool has_tz_pending_irq(struct gs101_tmu_data *pdata) +static dfs_throttle_cb thermal_dfs_throttle_cb; +void register_dfs_throttle_cb(dfs_throttle_cb dfs_cb) +{ + if (WARN_ON(!dfs_cb)) { + pr_err("Failed to register in %s\n",__func__); + return; + } + + if (WARN_ON(thermal_dfs_throttle_cb)) { + pr_err("thermal_dfs_throttle_cb is already set"); + return; + } + + thermal_dfs_throttle_cb = dfs_cb; +} +EXPORT_SYMBOL(register_dfs_throttle_cb); + +static bool has_tz_pending_irq(struct gs_tmu_data *pdata) { struct thermal_zone_data *tz_config_p = &tz_config[pdata->id]; u32 val, counter = 0; @@ -290,14 +373,20 @@ static bool has_tz_pending_irq(struct gs101_tmu_data *pdata) } for (i = 0; i < TRIP_LEVEL_NUM; i++) { - if (counter & TMU_REG_INTPEND_RISE_MASK(i)) + if (counter & TMU_REG_INTPEND_RISE_MASK(i)) { atomic64_inc(&(pdata->trip_counter[i])); + if ((i == DFS_IRQ_BIT) && (pdata->has_dfs_support)) + update_thermal_trace(pdata, DFS, 1); + } + if ((counter & TMU_REG_INTPEND_FALL_MASK(i)) && (i == DFS_IRQ_BIT) && + (pdata->has_dfs_support)) + update_thermal_trace(pdata, DFS, 0); } return ret; } -static void gs101_report_trigger(struct gs101_tmu_data *p) +static void gs_report_trigger(struct gs_tmu_data *p) { struct thermal_zone_device *tz = p->tzd; @@ -309,9 +398,9 @@ static void gs101_report_trigger(struct gs101_tmu_data *p) thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); } -static int gs101_tmu_initialize(struct platform_device *pdev) +static int gs_tmu_initialize(struct platform_device *pdev) { - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct thermal_zone_device *tz = data->tzd; enum thermal_trip_type type; int i, temp, ret = 0; @@ -349,7 +438,7 @@ static int gs101_tmu_initialize(struct platform_device *pdev) hysteresis[i] = (unsigned char)(temp / MCELSIUS); } - ret = gs101_tmu_tz_config_init(pdev); + ret = gs_tmu_tz_config_init(pdev); if (ret) { dev_err(&pdev->dev, "Failed to initialize tmu tz config\n"); goto out; @@ -359,15 +448,21 @@ static int gs101_tmu_initialize(struct platform_device *pdev) exynos_acpm_tmu_set_hysteresis(data->id, hysteresis); exynos_acpm_tmu_set_interrupt_enable(data->id, inten); + /* Initialize dfs thresholds */ + if (data->has_dfs_support) { + data->dfs_trig_threshold = threshold[DFS_IRQ_BIT]; + data->dfs_clr_threshold = threshold[DFS_IRQ_BIT] - hysteresis[DFS_IRQ_BIT]; + } + out: mutex_unlock(&data->lock); return ret; } -static void gs101_tmu_control(struct platform_device *pdev, bool on) +static void gs_tmu_control(struct platform_device *pdev, bool on) { - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); mutex_lock(&data->lock); exynos_acpm_tmu_tz_control(data->id, on); @@ -377,9 +472,9 @@ static void gs101_tmu_control(struct platform_device *pdev, bool on) #define MCINFO_LOG_THRESHOLD (4) -static int gs101_get_temp(void *p, int *temp) +static int gs_get_temp(void *p, int *temp) { - struct gs101_tmu_data *data = p; + struct gs_tmu_data *data = p; #if IS_ENABLED(CONFIG_EXYNOS_MCINFO) unsigned int mcinfo_count; unsigned int mcinfo_result[4] = {0, 0, 0, 0}; @@ -416,6 +511,16 @@ static int gs101_get_temp(void *p, int *temp) data->temperature = *temp / 1000; + if (data->has_dfs_support && + thermal_dfs_throttle_cb && + ((data->is_dfs_throttled && (data->temperature < data->dfs_clr_threshold)) || + (!data->is_dfs_throttled && (data->temperature >= data->dfs_trig_threshold)))) { + data->is_dfs_throttled = !data->is_dfs_throttled; + thermal_dfs_throttle_cb(&data->dfs_throttled_cpus, data->is_dfs_throttled); + pr_info_ratelimited("%s: dfs throttling status: %d \n", data->tmu_name, + data->is_dfs_throttled); + } + if (data->hotplug_enable && ((data->is_cpu_hotplugged_out && data->temperature < data->hotplug_in_threshold) || @@ -465,9 +570,9 @@ static int gs101_get_temp(void *p, int *temp) return 0; } -static int gs101_get_trend(void *p, int trip, enum thermal_trend *trend) +static int gs_get_trend(void *p, int trip, enum thermal_trend *trend) { - struct gs101_tmu_data *data = p; + struct gs_tmu_data *data = p; struct thermal_zone_device *tz = data->tzd; int trip_temp, ret = 0; @@ -490,9 +595,9 @@ static int gs101_get_trend(void *p, int trip, enum thermal_trend *trend) return 0; } -static int gs1010_tmu_set_trip_temp(void *drv_data, int trip, int temp) +static int gs_tmu_set_trip_temp(void *drv_data, int trip, int temp) { - struct gs101_tmu_data *data = drv_data; + struct gs_tmu_data *data = drv_data; struct thermal_zone_device *tz = data->tzd; enum thermal_trip_type type; int i, trip_temp, ret = 0; @@ -541,9 +646,9 @@ static int gs1010_tmu_set_trip_temp(void *drv_data, int trip, int temp) } #if IS_ENABLED(CONFIG_THERMAL_EMULATION) -static int gs101_tmu_set_emulation(void *drv_data, int temp) +static int gs_tmu_set_emulation(void *drv_data, int temp) { - struct gs101_tmu_data *data = drv_data; + struct gs_tmu_data *data = drv_data; int ret = -EINVAL; unsigned char emul_temp; @@ -559,22 +664,22 @@ static int gs101_tmu_set_emulation(void *drv_data, int temp) return ret; } #else -static int gs101_tmu_set_emulation(void *drv_data, int temp) +static int gs_tmu_set_emulation(void *drv_data, int temp) { return -EINVAL; } #endif /* CONFIG_THERMAL_EMULATION */ -static void start_pi_polling(struct gs101_tmu_data *data, int delay) +static void start_pi_polling(struct gs_tmu_data *data, int delay) { kthread_mod_delayed_work(&data->thermal_worker, &data->pi_work, msecs_to_jiffies(delay)); } -static void reset_pi_trips(struct gs101_tmu_data *data) +static void reset_pi_trips(struct gs_tmu_data *data) { struct thermal_zone_device *tz = data->tzd; - struct gs101_pi_param *params = data->pi_param; + struct gs_pi_param *params = data->pi_param; int i, last_active, last_passive; bool found_first_passive; @@ -620,14 +725,15 @@ static void reset_pi_trips(struct gs101_tmu_data *data) } } -static void reset_pi_params(struct gs101_tmu_data *data) +static void reset_pi_params(struct gs_tmu_data *data) { s64 i = int_to_frac(data->pi_param->i_max); data->pi_param->err_integral = div_frac(i, data->pi_param->k_i); + data->pi_param->prev_control_temp = INVALID_CONTROL_TEMP; } -static void allow_maximum_power(struct gs101_tmu_data *data) +static void allow_maximum_power(struct gs_tmu_data *data) { struct thermal_instance *instance; struct thermal_zone_device *tz = data->tzd; @@ -657,11 +763,11 @@ static void allow_maximum_power(struct gs101_tmu_data *data) mutex_lock(&data->lock); } -static u32 pi_calculate(struct gs101_tmu_data *data, int control_temp, +static u32 pi_calculate(struct gs_tmu_data *data, int control_temp, u32 max_allocatable_power) { struct thermal_zone_device *tz = data->tzd; - struct gs101_pi_param *params = data->pi_param; + struct gs_pi_param *params = data->pi_param; s64 p, i, power_range; s32 err, max_power_frac; @@ -711,10 +817,24 @@ static u32 pi_calculate(struct gs101_tmu_data *data, int control_temp, return power_range; } -static int gs101_pi_controller(struct gs101_tmu_data *data, int control_temp) +static int gs_pi_calculate_control_temp(struct gs_pi_param *params, int control_temp) +{ + /* Smooth transition is applied only for decreasing control temperatures. For increasing + temperatures and non-positive control step sizes, the transition will be immediate */ + if ((params->prev_control_temp <= control_temp) || (params->control_temp_step <= 0)) { + params->prev_control_temp = control_temp; + return control_temp; + } + + params->prev_control_temp -= params->control_temp_step; + params->prev_control_temp = max(params->prev_control_temp, control_temp); + return params->prev_control_temp; +} + +static int gs_pi_controller(struct gs_tmu_data *data, int control_temp) { struct thermal_zone_device *tz = data->tzd; - struct gs101_pi_param *params = data->pi_param; + struct gs_pi_param *params = data->pi_param; struct thermal_instance *instance; struct thermal_cooling_device *cdev; int ret = 0; @@ -741,6 +861,9 @@ static int gs101_pi_controller(struct gs101_tmu_data *data, int control_temp) cdev->ops->state2power(cdev, 0, &max_power); + if (params->prev_control_temp != control_temp) + control_temp = gs_pi_calculate_control_temp(params, control_temp); + power_range = pi_calculate(data, control_temp, max_power); ret = cdev->ops->power2state(cdev, power_range, &state); @@ -770,14 +893,14 @@ static int gs101_pi_controller(struct gs101_tmu_data *data, int control_temp) return ret; } -static void gs101_pi_thermal(struct gs101_tmu_data *data) +static void gs_pi_thermal(struct gs_tmu_data *data) { struct thermal_zone_device *tz = data->tzd; - struct gs101_pi_param *params = data->pi_param; + struct gs_pi_param *params = data->pi_param; int ret = 0; int switch_on_temp, control_temp, delay; - if (atomic_read(&gs101_tmu_in_suspend)) + if (atomic_read(&gs_tmu_in_suspend)) return; if (tz) { @@ -813,7 +936,7 @@ static void gs101_pi_thermal(struct gs101_tmu_data *data) goto polling; } - ret = gs101_pi_controller(data, control_temp); + ret = gs_pi_controller(data, control_temp); if (ret) { pr_debug("Failed to calculate pi controller: %d\n", @@ -833,20 +956,20 @@ static void gs101_pi_thermal(struct gs101_tmu_data *data) mutex_unlock(&data->lock); } -static void gs101_pi_polling(struct kthread_work *work) +static void gs_pi_polling(struct kthread_work *work) { - struct gs101_tmu_data *data = - container_of(work, struct gs101_tmu_data, pi_work.work); + struct gs_tmu_data *data = + container_of(work, struct gs_tmu_data, pi_work.work); - gs101_pi_thermal(data); + gs_pi_thermal(data); } -static void gs101_tmu_work(struct kthread_work *work) +static void gs_tmu_work(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, irq_work); + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, irq_work); - gs101_report_trigger(data); + gs_report_trigger(data); mutex_lock(&data->lock); exynos_acpm_tmu_clear_tz_irq(data->id); @@ -854,14 +977,14 @@ static void gs101_tmu_work(struct kthread_work *work) mutex_unlock(&data->lock); if (data->use_pi_thermal) - gs101_pi_thermal(data); + gs_pi_thermal(data); enable_irq(data->irq); } -static irqreturn_t gs101_tmu_irq(int irq, void *id) +static irqreturn_t gs_tmu_irq(int irq, void *id) { - struct gs101_tmu_data *data = id; + struct gs_tmu_data *data = id; disable_irq_nosync(irq); if (has_tz_pending_irq(data)) { @@ -876,8 +999,8 @@ static irqreturn_t gs101_tmu_irq(int irq, void *id) static void init_bcl_dev(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, cpu_hw_throttle_init_work.work); int ret = 0; @@ -919,10 +1042,10 @@ static void init_bcl_dev(struct kthread_work *work) mutex_unlock(&data->lock); } -static void gs101_throttle_arm(struct kthread_work *work) +static void gs_throttle_arm(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, cpu_hw_throttle_work); + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, cpu_hw_throttle_work); int ret = 0; @@ -988,10 +1111,10 @@ static void gs101_throttle_arm(struct kthread_work *work) mutex_unlock(&data->lock); } -static void gs101_throttle_cpu_hotplug(struct kthread_work *work) +static void gs_throttle_cpu_hotplug(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, hotplug_work); + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, hotplug_work); struct cpumask mask; mutex_lock(&data->lock); @@ -1005,7 +1128,7 @@ static void gs101_throttle_cpu_hotplug(struct kthread_work *work) if (exynos_cpuhp_request(data->cpuhp_name, *cpu_possible_mask)) { // queue the work again in case failure // also do not queue again when prepare to suspend - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->hotplug_work); } else { @@ -1022,7 +1145,7 @@ static void gs101_throttle_cpu_hotplug(struct kthread_work *work) if (exynos_cpuhp_request(data->cpuhp_name, mask)) { // queue the work again in case of failure // also do not queue again when prepare to suspend - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->hotplug_work); } else { @@ -1054,8 +1177,8 @@ EXPORT_SYMBOL(register_tpu_thermal_pause_cb); static void gs101_throttle_pause(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, pause_work); + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, pause_work); struct cpumask mask; int cpu_pause_mask, ret; @@ -1090,7 +1213,7 @@ static void gs101_throttle_pause(struct kthread_work *work) if (resume_cpus(&mask)) { // queue the work again in case failure // also do not queue again when prepare to suspend - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->pause_work); } else { @@ -1104,7 +1227,7 @@ static void gs101_throttle_pause(struct kthread_work *work) data->is_paused = false; pr_info_ratelimited("%s thermal resumed\n", data->tmu_name); } else { - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->pause_work); } @@ -1116,7 +1239,7 @@ static void gs101_throttle_pause(struct kthread_work *work) if (pause_cpus(&mask)) { // queue the work again in case of failure // also do not queue again when prepare to suspend - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->pause_work); } else { @@ -1130,7 +1253,7 @@ static void gs101_throttle_pause(struct kthread_work *work) data->is_paused = true; pr_info_ratelimited("%s thermal paused\n", data->tmu_name); } else { - if (!atomic_read(&gs101_tmu_in_suspend)) + if (!atomic_read(&gs_tmu_in_suspend)) kthread_queue_work(&data->pause_worker, &data->pause_work); } @@ -1145,10 +1268,10 @@ static void gs101_throttle_pause(struct kthread_work *work) mutex_unlock(&data->lock); } -static void gs101_throttle_hard_limit(struct kthread_work *work) +static void gs_throttle_hard_limit(struct kthread_work *work) { - struct gs101_tmu_data *data = container_of(work, - struct gs101_tmu_data, hardlimit_work); + struct gs_tmu_data *data = container_of(work, + struct gs_tmu_data, hardlimit_work); struct thermal_zone_device *tz = data->tzd; struct thermal_instance *instance; struct thermal_cooling_device *cdev = NULL; @@ -1195,7 +1318,7 @@ static void gs101_throttle_hard_limit(struct kthread_work *work) data->is_hardlimited = false; pr_info_ratelimited("%s: clear hard limit, is_hardlimited = %d, pid swithed_on = %d\n", data->tmu_name, data->is_hardlimited, - data->pi_param->switched_on); + data->use_pi_thermal ? data->pi_param->switched_on : 0); } } else { if (data->temperature >= data->hardlimit_threshold) { @@ -1229,7 +1352,7 @@ static void gs101_throttle_hard_limit(struct kthread_work *work) pr_info_ratelimited("%s: %s set cur_state to hardlimit cooling state %d, is_hardlimited = %d, pid swithed_on = %d\n", data->tmu_name, cdev->type, data->hardlimit_cooling_state, data->is_hardlimited, - data->pi_param->switched_on); + data->use_pi_thermal ? data->pi_param->switched_on : 0); } } update_thermal_trace(data, HARD_LIMIT, data->is_hardlimited); @@ -1239,16 +1362,16 @@ static void gs101_throttle_hard_limit(struct kthread_work *work) mutex_unlock(&data->lock); } -static int gs101_tmu_pm_notify(struct notifier_block *nb, - unsigned long mode, void *_unused) +static int gs_tmu_pm_notify(struct notifier_block *nb, + unsigned long mode, void *_unused) { - struct gs101_tmu_data *data; + struct gs_tmu_data *data; switch (mode) { case PM_HIBERNATION_PREPARE: case PM_RESTORE_PREPARE: case PM_SUSPEND_PREPARE: - atomic_set(&gs101_tmu_in_suspend, 1); + atomic_set(&gs_tmu_in_suspend, 1); list_for_each_entry(data, &dtm_dev_list, node) { if (data->use_pi_thermal) kthread_cancel_delayed_work_sync(&data->pi_work); @@ -1257,7 +1380,7 @@ static int gs101_tmu_pm_notify(struct notifier_block *nb, case PM_POST_HIBERNATION: case PM_POST_RESTORE: case PM_POST_SUSPEND: - atomic_set(&gs101_tmu_in_suspend, 0); + atomic_set(&gs_tmu_in_suspend, 0); list_for_each_entry(data, &dtm_dev_list, node) { if (data->use_pi_thermal) start_pi_polling(data, 0); @@ -1269,19 +1392,20 @@ static int gs101_tmu_pm_notify(struct notifier_block *nb, return 0; } -static struct notifier_block gs101_tmu_pm_nb = { - .notifier_call = gs101_tmu_pm_notify, +static struct notifier_block gs_tmu_pm_nb = { + .notifier_call = gs_tmu_pm_notify, }; -static const struct of_device_id gs101_tmu_match[] = { +static const struct of_device_id gs_tmu_match[] = { { .compatible = "samsung,gs101-tmu-v2", }, + { .compatible = "samsung,gs201-tmu-v2", }, { /* sentinel */ }, }; -MODULE_DEVICE_TABLE(of, gs101_tmu_match); +MODULE_DEVICE_TABLE(of, gs_tmu_match); -static int gs101_tmu_irq_work_init(struct platform_device *pdev) +static int gs_tmu_irq_work_init(struct platform_device *pdev) { - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct cpumask mask; struct sched_param param = { .sched_priority = MAX_RT_PRIO / 4 - 1 }; struct task_struct *thread; @@ -1307,7 +1431,7 @@ static int gs101_tmu_irq_work_init(struct platform_device *pdev) return ret; } - kthread_init_work(&data->irq_work, gs101_tmu_work); + kthread_init_work(&data->irq_work, gs_tmu_work); wake_up_process(thread); @@ -1315,7 +1439,7 @@ static int gs101_tmu_irq_work_init(struct platform_device *pdev) if (data->hotplug_enable) { scnprintf(data->cpuhp_name, CPUHP_USER_NAME_LEN, "DTM_%s", data->tmu_name); exynos_cpuhp_register(data->cpuhp_name, *cpu_online_mask); - kthread_init_work(&data->hotplug_work, gs101_throttle_cpu_hotplug); + kthread_init_work(&data->hotplug_work, gs_throttle_cpu_hotplug); } if (data->pause_enable) { @@ -1340,7 +1464,7 @@ static int gs101_tmu_irq_work_init(struct platform_device *pdev) } if (data->cpu_hw_throttling_enable) { - kthread_init_work(&data->cpu_hw_throttle_work, gs101_throttle_arm); + kthread_init_work(&data->cpu_hw_throttle_work, gs_throttle_arm); kthread_init_worker(&data->cpu_hw_throttle_worker); scnprintf(kworker_name, CPUHP_USER_NAME_LEN, "%s_hw_throttle", data->tmu_name); @@ -1365,7 +1489,7 @@ static int gs101_tmu_irq_work_init(struct platform_device *pdev) } if (data->hardlimit_enable) { - kthread_init_work(&data->hardlimit_work, gs101_throttle_hard_limit); + kthread_init_work(&data->hardlimit_work, gs_throttle_hard_limit); kthread_init_worker(&data->hardlimit_worker); scnprintf(kworker_name, CPUHP_USER_NAME_LEN, "%s_hardlimit", data->tmu_name); @@ -1386,9 +1510,9 @@ static int gs101_tmu_irq_work_init(struct platform_device *pdev) return ret; } -static int gs101_map_dt_data(struct platform_device *pdev) +static int gs_map_dt_data(struct platform_device *pdev) { - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct resource res; const char *tmu_name, *buf; int ret; @@ -1535,12 +1659,16 @@ static int gs101_map_dt_data(struct platform_device *pdev) } #endif + ret = of_property_read_string(pdev->dev.of_node, "dfs_throttled_cpus", &buf); + if (!ret) + cpulist_parse(buf, &data->dfs_throttled_cpus); + ret = of_property_read_string(pdev->dev.of_node, "tmu_work_affinity", &buf); if (!ret) cpulist_parse(buf, &data->tmu_work_affinity); if (of_property_read_bool(pdev->dev.of_node, "use-pi-thermal")) { - struct gs101_pi_param *params; + struct gs_pi_param *params; u32 value; data->use_pi_thermal = true; @@ -1592,6 +1720,13 @@ static int gs101_map_dt_data(struct platform_device *pdev) else params->integral_cutoff = value; + ret = of_property_read_u32(pdev->dev.of_node, "control_temp_step", + &value); + if (ret < 0) + dev_err(&pdev->dev, "No input control_temp_step\n"); + else + params->control_temp_step = value; + ret = of_property_read_u32(pdev->dev.of_node, "sustainable_power", &value); if (ret < 0) @@ -1604,14 +1739,16 @@ static int gs101_map_dt_data(struct platform_device *pdev) data->use_pi_thermal = false; } + data->has_dfs_support = of_property_read_bool(pdev->dev.of_node, "has-dfs-support"); + return 0; } -static const struct thermal_zone_of_device_ops gs101_sensor_ops = { - .get_temp = gs101_get_temp, - .set_emul_temp = gs101_tmu_set_emulation, - .get_trend = gs101_get_trend, - .set_trip_temp = gs1010_tmu_set_trip_temp, +static const struct thermal_zone_of_device_ops gs_sensor_ops = { + .get_temp = gs_get_temp, + .set_emul_temp = gs_tmu_set_emulation, + .get_trend = gs_get_trend, + .set_trip_temp = gs_tmu_set_trip_temp, }; static ssize_t @@ -1619,7 +1756,7 @@ cpu_hw_throttling_trigger_temp_show(struct device *dev, struct device_attribute char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->cpu_hw_throttling_trigger_threshold); } @@ -1629,7 +1766,7 @@ cpu_hw_throttling_trigger_temp_store(struct device *dev, struct device_attribute const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int cpu_hw_throttling_trigger = 0; mutex_lock(&data->lock); @@ -1651,7 +1788,7 @@ cpu_hw_throttling_clr_temp_show(struct device *dev, struct device_attribute *dev char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->cpu_hw_throttling_clr_threshold); } @@ -1661,7 +1798,7 @@ cpu_hw_throttling_clr_temp_store(struct device *dev, struct device_attribute *de const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int cpu_hw_throttling_clear = 0; mutex_lock(&data->lock); @@ -1683,7 +1820,7 @@ hotplug_out_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return scnprintf(buf, PAGE_SIZE, "%d\n", data->hotplug_out_threshold); } @@ -1693,7 +1830,7 @@ hotplug_out_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int hotplug_out = 0; mutex_lock(&data->lock); @@ -1715,7 +1852,7 @@ hotplug_in_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return scnprintf(buf, PAGE_SIZE, "%d\n", data->hotplug_in_threshold); } @@ -1725,7 +1862,7 @@ hotplug_in_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int hotplug_in = 0; mutex_lock(&data->lock); @@ -1747,7 +1884,7 @@ hardlimit_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->hardlimit_threshold); } @@ -1757,7 +1894,7 @@ hardlimit_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int hardlimit_throttling_trigger = 0; mutex_lock(&data->lock); @@ -1779,7 +1916,7 @@ hardlimit_clr_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->hardlimit_clr_threshold); } @@ -1789,7 +1926,7 @@ hardlimit_clr_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int hardlimit_clr_threshold = 0; mutex_lock(&data->lock); @@ -1811,7 +1948,7 @@ pause_cpus_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->pause_threshold); } @@ -1821,7 +1958,7 @@ pause_cpus_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int pause_throttling_trigger = 0; mutex_lock(&data->lock); @@ -1843,7 +1980,7 @@ resume_cpus_temp_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); return sysfs_emit(buf, "%d\n", data->resume_threshold); } @@ -1853,7 +1990,7 @@ resume_cpus_temp_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int resume_threshold = 0; mutex_lock(&data->lock); @@ -1875,7 +2012,7 @@ sustainable_power_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); if (data->pi_param) return sprintf(buf, "%u\n", data->pi_param->sustainable_power); @@ -1888,7 +2025,7 @@ sustainable_power_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); u32 sustainable_power; if (!data->pi_param) @@ -1907,7 +2044,7 @@ polling_delay_on_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); if (data->pi_param) return sprintf(buf, "%u\n", data->pi_param->polling_delay_on); @@ -1920,7 +2057,7 @@ polling_delay_on_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); u32 polling_delay_on; if (!data->pi_param) @@ -1951,7 +2088,7 @@ polling_delay_off_show(struct device *dev, struct device_attribute *devattr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); if (data->pi_param) return sprintf(buf, "%u\n", data->pi_param->polling_delay_off); @@ -1964,7 +2101,7 @@ polling_delay_off_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); u32 polling_delay_off; if (!data->pi_param) @@ -1995,7 +2132,7 @@ hardlimit_total_count_show(struct device *dev, struct device_attribute *attr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->hardlimit_stats; int ret = 0; @@ -2016,7 +2153,7 @@ hardlimit_time_in_state_ms_show(struct device *dev, struct device_attribute *att char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->hardlimit_stats; ssize_t len = 0; int i; @@ -2041,7 +2178,7 @@ hardlimit_reset_store(struct device *dev, struct device_attribute *attr, const c size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->hardlimit_stats; int i; @@ -2067,7 +2204,7 @@ pause_total_count_show(struct device *dev, struct device_attribute *attr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->disable_stats; int ret = 0; @@ -2086,7 +2223,7 @@ pause_time_in_state_ms_show(struct device *dev, struct device_attribute *attr, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->disable_stats; ssize_t len = 0; int i; @@ -2111,7 +2248,7 @@ pause_reset_store(struct device *dev, struct device_attribute *attr, const char size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct throttling_stats *stats = data->disable_stats; int i; @@ -2135,7 +2272,7 @@ static ssize_t trip_counter_show(struct device *dev, char *buf) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int i; int len = 0; @@ -2154,7 +2291,7 @@ static ssize_t trip_counter_reset_store(struct device *dev, size_t count) { struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); int i; for (i = 0; i < TRIP_LEVEL_NUM; i++) @@ -2199,7 +2336,7 @@ static ssize_t ipc_dump2_show(struct device *dev, struct device_attribute *attr, char *buf) \ { \ struct platform_device *pdev = to_platform_device(dev); \ - struct gs101_tmu_data *data = platform_get_drvdata(pdev); \ + struct gs_tmu_data *data = platform_get_drvdata(pdev); \ \ if (data->pi_param) \ return sprintf(buf, "%d\n", data->pi_param->name); \ @@ -2212,7 +2349,7 @@ static ssize_t ipc_dump2_show(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \ { \ struct platform_device *pdev = to_platform_device(dev); \ - struct gs101_tmu_data *data = platform_get_drvdata(pdev); \ + struct gs_tmu_data *data = platform_get_drvdata(pdev); \ s32 value; \ \ if (!data->pi_param) \ @@ -2253,8 +2390,9 @@ create_s32_param_attr(k_pu); create_s32_param_attr(k_i); create_s32_param_attr(i_max); create_s32_param_attr(integral_cutoff); +create_s32_param_attr(control_temp_step); -static struct attribute *gs101_tmu_attrs[] = { +static struct attribute *gs_tmu_attrs[] = { &dev_attr_pause_cpus_temp.attr, &dev_attr_resume_cpus_temp.attr, &dev_attr_hardlimit_temp.attr, @@ -2271,6 +2409,7 @@ static struct attribute *gs101_tmu_attrs[] = { &dev_attr_k_i.attr, &dev_attr_i_max.attr, &dev_attr_integral_cutoff.attr, + &dev_attr_control_temp_step.attr, &dev_attr_pause_time_in_state_ms.attr, &dev_attr_pause_total_count.attr, &dev_attr_pause_reset.attr, @@ -2284,9 +2423,9 @@ static struct attribute *gs101_tmu_attrs[] = { NULL, }; -ATTRIBUTE_GROUPS(gs101_tmu); +ATTRIBUTE_GROUPS(gs_tmu); -static void hard_limit_stats_setup(struct gs101_tmu_data *data) +static void hard_limit_stats_setup(struct gs_tmu_data *data) { struct throttling_stats *stats; int var; @@ -2307,7 +2446,7 @@ static void hard_limit_stats_setup(struct gs101_tmu_data *data) spin_lock_init(&stats->lock); } -static void pause_stats_setup(struct gs101_tmu_data *data) +static void pause_stats_setup(struct gs_tmu_data *data) { struct throttling_stats *stats; int var; @@ -2455,7 +2594,7 @@ static int param_tmu_reg_dump_state(char *buf, const struct kernel_param *kp) u32 val; int len = 0; - if (suspended_count || atomic_read(&gs101_tmu_in_suspend)) + if (suspended_count || atomic_read(&gs_tmu_in_suspend)) return sysfs_emit(buf, "in tmu suspending..try again\n"); for (i = 0; i < TMU_END; i++) { @@ -2846,7 +2985,7 @@ MODULE_PARM_DESC(tmu_sub_reg_dump_fall_thres, static void exynos_acpm_tmu_test_cp_call(bool mode) { - struct gs101_tmu_data *devnode; + struct gs_tmu_data *devnode; if (mode) { list_for_each_entry(devnode, &dtm_dev_list, node) { @@ -2910,7 +3049,7 @@ module_param_call(log_print, log_print_store, log_print_show, NULL, 0600); #define PARAM_NAME_LENGTH 25 #if IS_ENABLED(CONFIG_ECT) -static int gs101_tmu_ect_get_param(struct ect_pidtm_block *pidtm_block, char *name) +static int gs_tmu_ect_get_param(struct ect_pidtm_block *pidtm_block, char *name) { int i; int param_value = -1; @@ -2925,7 +3064,7 @@ static int gs101_tmu_ect_get_param(struct ect_pidtm_block *pidtm_block, char *na return param_value; } -static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) +static int gs_tmu_parse_ect(struct gs_tmu_data *data) { struct thermal_zone_device *tz = data->tzd; int ntrips = 0; @@ -3001,7 +3140,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) } else { void *block; struct ect_pidtm_block *pidtm_block; - struct gs101_pi_param *params; + struct gs_pi_param *params; int i, temperature, value; int hotplug_out_threshold = 0, hotplug_in_threshold = 0, limited_frequency = 0; int limited_threshold = 0, limited_threshold_release = 0; @@ -3034,7 +3173,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) params = data->pi_param; - value = gs101_tmu_ect_get_param(pidtm_block, "k_po"); + value = gs_tmu_ect_get_param(pidtm_block, "k_po"); if (value != -1) { pr_info("Parse from ECT k_po: %d\n", value); params->k_po = int_to_frac(value); @@ -3042,7 +3181,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse k_po parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "k_pu"); + value = gs_tmu_ect_get_param(pidtm_block, "k_pu"); if (value != -1) { pr_info("Parse from ECT k_pu: %d\n", value); params->k_pu = int_to_frac(value); @@ -3050,7 +3189,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse k_pu parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "k_i"); + value = gs_tmu_ect_get_param(pidtm_block, "k_i"); if (value != -1) { pr_info("Parse from ECT k_i: %d\n", value); params->k_i = int_to_frac(value); @@ -3058,7 +3197,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse k_i parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "i_max"); + value = gs_tmu_ect_get_param(pidtm_block, "i_max"); if (value != -1) { pr_info("Parse from ECT i_max: %d\n", value); params->i_max = value; @@ -3066,7 +3205,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse i_max parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "integral_cutoff"); + value = gs_tmu_ect_get_param(pidtm_block, "integral_cutoff"); if (value != -1) { pr_info("Parse from ECT integral_cutoff: %d\n", value); params->integral_cutoff = value; @@ -3074,7 +3213,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse integral_cutoff parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "p_control_t"); + value = gs_tmu_ect_get_param(pidtm_block, "p_control_t"); if (value != -1) { pr_info("Parse from ECT p_control_t: %d\n", value); params->sustainable_power = value; @@ -3082,25 +3221,25 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) pr_err("Fail to parse p_control_t parameter\n"); } - value = gs101_tmu_ect_get_param(pidtm_block, "hotplug_out_threshold"); + value = gs_tmu_ect_get_param(pidtm_block, "hotplug_out_threshold"); if (value != -1) { pr_info("Parse from ECT hotplug_out_threshold: %d\n", value); hotplug_out_threshold = value; } - value = gs101_tmu_ect_get_param(pidtm_block, "hotplug_in_threshold"); + value = gs_tmu_ect_get_param(pidtm_block, "hotplug_in_threshold"); if (value != -1) { pr_info("Parse from ECT hotplug_in_threshold: %d\n", value); hotplug_in_threshold = value; } - value = gs101_tmu_ect_get_param(pidtm_block, "limited_frequency"); + value = gs_tmu_ect_get_param(pidtm_block, "limited_frequency"); if (value != -1) { pr_info("Parse from ECT limited_frequency: %d\n", value); limited_frequency = value; } - value = gs101_tmu_ect_get_param(pidtm_block, "limited_threshold"); + value = gs_tmu_ect_get_param(pidtm_block, "limited_threshold"); if (value != -1) { pr_info("Parse from ECT limited_threshold: %d\n", value); limited_threshold = value * MCELSIUS; @@ -3108,7 +3247,7 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) data->limited_threshold = value; } - value = gs101_tmu_ect_get_param(pidtm_block, "limited_threshold_release"); + value = gs_tmu_ect_get_param(pidtm_block, "limited_threshold_release"); if (value != -1) { pr_info("Parse from ECT limited_threshold_release: %d\n", value); limited_threshold_release = value * MCELSIUS; @@ -3133,24 +3272,24 @@ static int gs101_tmu_parse_ect(struct gs101_tmu_data *data) #endif #if IS_ENABLED(CONFIG_MALI_DEBUG_KERNEL_SYSFS) -struct gs101_tmu_data *gpu_thermal_data; +struct gs_tmu_data *gpu_thermal_data; #endif extern void register_tz_id_ignore_genl(int tz_id); -static int gs101_tmu_probe(struct platform_device *pdev) +static int gs_tmu_probe(struct platform_device *pdev) { - struct gs101_tmu_data *data; + struct gs_tmu_data *data; int ret; - data = devm_kzalloc(&pdev->dev, sizeof(struct gs101_tmu_data), GFP_KERNEL); + data = devm_kzalloc(&pdev->dev, sizeof(struct gs_tmu_data), GFP_KERNEL); if (!data) return -ENOMEM; platform_set_drvdata(pdev, data); mutex_init(&data->lock); - ret = gs101_map_dt_data(pdev); + ret = gs_map_dt_data(pdev); if (ret) goto err_sensor; @@ -3161,7 +3300,7 @@ static int gs101_tmu_probe(struct platform_device *pdev) #endif } - data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, &gs101_sensor_ops); + data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, &gs_sensor_ops); if (IS_ERR(data->tzd)) { ret = PTR_ERR(data->tzd); dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); @@ -3172,7 +3311,7 @@ static int gs101_tmu_probe(struct platform_device *pdev) #if IS_ENABLED(CONFIG_ECT) if (!of_property_read_bool(pdev->dev.of_node, "ect_nouse")) - gs101_tmu_parse_ect(data); + gs_tmu_parse_ect(data); if (data->limited_frequency) { exynos_pm_qos_add_request(&data->thermal_limit_request, @@ -3181,29 +3320,29 @@ static int gs101_tmu_probe(struct platform_device *pdev) } #endif - ret = gs101_tmu_initialize(pdev); + ret = gs_tmu_initialize(pdev); if (ret) { dev_err(&pdev->dev, "Failed to initialize TMU\n"); goto err_thermal; } - ret = devm_request_irq(&pdev->dev, data->irq, gs101_tmu_irq, + ret = devm_request_irq(&pdev->dev, data->irq, gs_tmu_irq, IRQF_SHARED, dev_name(&pdev->dev), data); if (ret) { dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); goto err_thermal; } - ret = gs101_tmu_irq_work_init(pdev); + ret = gs_tmu_irq_work_init(pdev); if (ret) { - dev_err(&pdev->dev, "cannot gs101 interrupt work initialize\n"); + dev_err(&pdev->dev, "cannot gs interrupt work initialize\n"); goto err_thermal; } if (data->use_pi_thermal) - kthread_init_delayed_work(&data->pi_work, gs101_pi_polling); + kthread_init_delayed_work(&data->pi_work, gs_pi_polling); - gs101_tmu_control(pdev, true); + gs_tmu_control(pdev, true); if (data->hotplug_enable || data->pause_enable) pause_stats_setup(data); @@ -3225,7 +3364,7 @@ static int gs101_tmu_probe(struct platform_device *pdev) thermal_zone_device_enable(data->tzd); if (list_is_singular(&dtm_dev_list)) { - register_pm_notifier(&gs101_tmu_pm_nb); + register_pm_notifier(&gs_tmu_pm_nb); } #if IS_ENABLED(CONFIG_MALI_DEBUG_KERNEL_SYSFS) @@ -3247,14 +3386,14 @@ static int gs101_tmu_probe(struct platform_device *pdev) return ret; } -static int gs101_tmu_remove(struct platform_device *pdev) +static int gs_tmu_remove(struct platform_device *pdev) { - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct thermal_zone_device *tzd = data->tzd; - struct gs101_tmu_data *devnode; + struct gs_tmu_data *devnode; thermal_zone_of_sensor_unregister(&pdev->dev, tzd); - gs101_tmu_control(pdev, false); + gs_tmu_control(pdev, false); mutex_lock(&data->lock); list_for_each_entry(devnode, &dtm_dev_list, node) { @@ -3270,11 +3409,11 @@ static int gs101_tmu_remove(struct platform_device *pdev) } #if IS_ENABLED(CONFIG_PM_SLEEP) -static int gs101_tmu_suspend(struct device *dev) +static int gs_tmu_suspend(struct device *dev) { #if IS_ENABLED(CONFIG_EXYNOS_ACPM_THERMAL) struct platform_device *pdev = to_platform_device(dev); - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); suspended_count++; disable_irq(data->irq); @@ -3285,7 +3424,7 @@ static int gs101_tmu_suspend(struct device *dev) kthread_flush_work(&data->pause_work); kthread_flush_work(&data->irq_work); - gs101_tmu_control(pdev, false); + gs_tmu_control(pdev, false); if (suspended_count == num_of_devices) { exynos_acpm_tmu_set_suspend(false); pr_info("%s: TMU suspend\n", __func__); @@ -3294,18 +3433,18 @@ static int gs101_tmu_suspend(struct device *dev) return 0; } -static int gs101_tmu_resume(struct device *dev) +static int gs_tmu_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); #if IS_ENABLED(CONFIG_EXYNOS_ACPM_THERMAL) - struct gs101_tmu_data *data = platform_get_drvdata(pdev); + struct gs_tmu_data *data = platform_get_drvdata(pdev); struct cpumask mask; int temp, stat; if (suspended_count == num_of_devices) exynos_acpm_tmu_set_resume(); - gs101_tmu_control(pdev, true); + gs_tmu_control(pdev, true); exynos_acpm_tmu_set_read_temp(data->id, &temp, &stat); @@ -3325,28 +3464,28 @@ static int gs101_tmu_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(gs101_tmu_pm, - gs101_tmu_suspend, gs101_tmu_resume); -#define EXYNOS_TMU_PM (&gs101_tmu_pm) +static SIMPLE_DEV_PM_OPS(gs_tmu_pm, + gs_tmu_suspend, gs_tmu_resume); +#define EXYNOS_TMU_PM (&gs_tmu_pm) #else #define EXYNOS_TMU_PM NULL #endif -static struct platform_driver gs101_tmu_driver = { +static struct platform_driver gs_tmu_driver = { .driver = { - .name = "gs101-tmu", - .dev_groups = gs101_tmu_groups, + .name = "gs-tmu", + .dev_groups = gs_tmu_groups, .pm = EXYNOS_TMU_PM, - .of_match_table = gs101_tmu_match, + .of_match_table = gs_tmu_match, .suppress_bind_attrs = true, }, - .probe = gs101_tmu_probe, - .remove = gs101_tmu_remove, + .probe = gs_tmu_probe, + .remove = gs_tmu_remove, }; -module_platform_driver(gs101_tmu_driver); +module_platform_driver(gs_tmu_driver); -MODULE_DESCRIPTION("GS101 TMU Driver"); +MODULE_DESCRIPTION("GS TMU Driver"); MODULE_AUTHOR("Hyeonseong Gil "); MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:gs101-tmu"); +MODULE_ALIAS("platform:gs-tmu"); diff --git a/drivers/tty/serial/exynos_tty.c b/drivers/tty/serial/exynos_tty.c index 090208a49b60..cba8b3fa37bd 100644 --- a/drivers/tty/serial/exynos_tty.c +++ b/drivers/tty/serial/exynos_tty.c @@ -1901,7 +1901,7 @@ static void exynos_serial_set_termios(struct uart_port *port, port->status &= ~UPSTAT_AUTOCTS; umcon = rd_regl(port, S3C2410_UMCON); - if (termios->c_cflag & CRTSCTS) { + if ((termios->c_cflag & CRTSCTS) && (!ourport->dbg_uart_ch)) { umcon |= S3C2410_UMCOM_AFC; port->status = UPSTAT_AUTOCTS; if (ourport->uart_logging && !IS_ERR_OR_NULL(ourport->log)) @@ -2476,10 +2476,12 @@ static int exynos_serial_notifier(struct notifier_block *self, spin_lock_irqsave(&port->lock, flags); - /* enable auto flow control */ - umcon = rd_regl(port, S3C2410_UMCON); - umcon |= S3C2410_UMCOM_AFC; - wr_regl(port, S3C2410_UMCON, umcon); + if (!ourport->dbg_uart_ch) { + /* enable auto flow control */ + umcon = rd_regl(port, S3C2410_UMCON); + umcon |= S3C2410_UMCOM_AFC; + wr_regl(port, S3C2410_UMCON, umcon); + } spin_unlock_irqrestore(&port->lock, flags); diff --git a/drivers/usb/dwc3/dwc3-exynos-ldo.h b/drivers/usb/dwc3/dwc3-exynos-ldo.h index a1e172348149..8445a4c2f8ca 100644 --- a/drivers/usb/dwc3/dwc3-exynos-ldo.h +++ b/drivers/usb/dwc3/dwc3-exynos-ldo.h @@ -12,6 +12,7 @@ int exynos_usbdrd_ldo_manual_control(bool on); int exynos_usbdrd_vdd_hsi_manual_control(bool on); +int exynos_usbdrd_s2mpu_manual_control(bool on); bool exynos_usbdrd_get_ldo_status(void); #endif /* __LINUX_USB_DWC3_EXYNOS_LDO_H */ diff --git a/drivers/usb/dwc3/dwc3-exynos-otg.c b/drivers/usb/dwc3/dwc3-exynos-otg.c index 06cac914984c..2aa0e6e4be88 100644 --- a/drivers/usb/dwc3/dwc3-exynos-otg.c +++ b/drivers/usb/dwc3/dwc3-exynos-otg.c @@ -523,7 +523,6 @@ static int dwc3_otg_start_gadget(struct otg_fsm *fsm, int on) if (!dwc3_otg_check_usb_suspend(exynos)) dev_err(dev, "too long to wait for dwc3 suspended\n"); - exynos->vbus_state = true; while (dwc->gadget_driver == NULL) { wait_counter++; usleep_range(100, 200); @@ -554,6 +553,7 @@ static int dwc3_otg_start_gadget(struct otg_fsm *fsm, int on) timer_setup(&exynos->usb_connect_timer, dwc3_otg_retry_configuration, 0); mod_timer(&exynos->usb_connect_timer, jiffies + CHG_CONNECTED_DELAY_TIME); + exynos->vbus_state = true; } else { exynos->vbus_state = false; del_timer_sync(&exynos->usb_connect_timer); @@ -884,7 +884,8 @@ static int dwc3_otg_reboot_notify(struct notifier_block *nb, unsigned long event case SYS_POWER_OFF: exynos->dwc->current_dr_role = DWC3_EXYNOS_IGNORE_CORE_OPS; dotg->in_shutdown = true; - del_timer_sync(&exynos->usb_connect_timer); + if (exynos->vbus_state) + del_timer_sync(&exynos->usb_connect_timer); break; } diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index 8cdf45c0adce..e80f59cd679d 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -42,6 +42,7 @@ #include #include +#include static const struct of_device_id exynos_dwc3_match[] = { { @@ -777,8 +778,12 @@ static int dwc3_exynos_vbus_notifier(struct notifier_block *nb, { struct dwc3_exynos *exynos = container_of(nb, struct dwc3_exynos, vbus_nb); - if (!exynos->usb_data_enabled) + dev_info(exynos->dev, "turn %s USB gadget\n", action ? "on" : "off"); + + if (!exynos->usb_data_enabled) { + dev_info(exynos->dev, "skip the notification due to USB enumeration disabled\n"); return NOTIFY_OK; + } dwc3_exynos_vbus_event(exynos->dev, action); @@ -790,8 +795,12 @@ static int dwc3_exynos_id_notifier(struct notifier_block *nb, { struct dwc3_exynos *exynos = container_of(nb, struct dwc3_exynos, id_nb); - if (!exynos->usb_data_enabled) + dev_info(exynos->dev, "turn %s USB host\n", action ? "on" : "off"); + + if (!exynos->usb_data_enabled) { + dev_info(exynos->dev, "skip the notification due to USB enumeration disabled\n"); return NOTIFY_OK; + } dwc3_exynos_id_event(exynos->dev, !action); @@ -1026,6 +1035,8 @@ static ssize_t force_speed_store(struct device *dev, struct device_attribute *at force_speed = USB_SPEED_SUPER; } else if (sysfs_streq(buf, "high-speed")) { force_speed = USB_SPEED_HIGH; + } else if (sysfs_streq(buf, "full-speed")) { + force_speed = USB_SPEED_FULL; } else { return -EINVAL; } @@ -1073,6 +1084,14 @@ static int dwc3_exynos_probe(struct platform_device *pdev) return -EPROBE_DEFER; } + if (IS_ENABLED(CONFIG_PKVM_S2MPU)) { + ret = pkvm_s2mpu_of_link(dev); + if (ret == -EAGAIN) + return -EPROBE_DEFER; + else if (ret) + return ret; + } + exynos = devm_kzalloc(dev, sizeof(*exynos), GFP_KERNEL); if (!exynos) return -ENOMEM; @@ -1139,6 +1158,7 @@ static int dwc3_exynos_probe(struct platform_device *pdev) exynos_usbdrd_vdd_hsi_manual_control(1); exynos_usbdrd_ldo_manual_control(1); + exynos_usbdrd_s2mpu_manual_control(1); if (node) { ret = of_platform_populate(node, NULL, NULL, dev); @@ -1154,7 +1174,7 @@ static int dwc3_exynos_probe(struct platform_device *pdev) dwc3_pdev = of_find_device_by_node(dwc3_np); exynos->dwc = platform_get_drvdata(dwc3_pdev); - if (exynos->dwc == NULL) + if (exynos->dwc == NULL || exynos->dwc->dev == NULL || exynos->dwc->gadget == NULL) goto populate_err; /* dwc3 core configurations */ diff --git a/drivers/usb/host/xhci-exynos.c b/drivers/usb/host/xhci-exynos.c index 06940ffaa84c..2231cee9710b 100644 --- a/drivers/usb/host/xhci-exynos.c +++ b/drivers/usb/host/xhci-exynos.c @@ -673,7 +673,9 @@ int xhci_exynos_wake_lock(struct xhci_hcd_exynos *xhci_exynos, int is_main_hcd, int is_lock) { struct usb_hcd *hcd = xhci_exynos->hcd; +#if IS_ENABLED(CONFIG_EXYNOS_CPUPM) int idle_ip_index; +#endif struct xhci_hcd *xhci = hcd_to_xhci(hcd); dev_dbg(xhci_exynos->dev, "%s\n", __func__); @@ -698,8 +700,10 @@ int xhci_exynos_wake_lock(struct xhci_hcd_exynos *xhci_exynos, } /* Add a routine for disable IDLEIP (IP idle) */ dev_info(xhci_exynos->dev, "IDLEIP(SICD) disable.\n"); +#if IS_ENABLED(CONFIG_EXYNOS_CPUPM) idle_ip_index = dwc3_otg_get_idle_ip_index(); exynos_update_ip_idle_status(idle_ip_index, 0); +#endif } else { if (xhci_exynos->ap_suspend_enabled) { dev_info(xhci_exynos->dev, "%s: audio device, skip WAKE UNLOCK\n", @@ -716,8 +720,10 @@ int xhci_exynos_wake_lock(struct xhci_hcd_exynos *xhci_exynos, } dev_info(xhci_exynos->dev, "IDLEIP(SICD) enable.\n"); /* Add a routine for enable IDLEIP (IP idle) */ +#if IS_ENABLED(CONFIG_EXYNOS_CPUPM) idle_ip_index = dwc3_otg_get_idle_ip_index(); exynos_update_ip_idle_status(idle_ip_index, 1); +#endif } return 0; diff --git a/drivers/usb/typec/tcpm/google/max77759_contaminant.c b/drivers/usb/typec/tcpm/google/max77759_contaminant.c index ee00c96ee678..f0e523b9deb5 100644 --- a/drivers/usb/typec/tcpm/google/max77759_contaminant.c +++ b/drivers/usb/typec/tcpm/google/max77759_contaminant.c @@ -537,6 +537,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb return ret; } *cc_update_handled = false; + return 0; } if (contaminant->state == NOT_DETECTED || contaminant->state == SINK || @@ -562,6 +563,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb if (ret == -EIO) return ret; *cc_update_handled = true; + return 0; } /* Sink or Not detected */ @@ -570,6 +572,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb if (ret == -EIO) return ret; *cc_update_handled = true; + return 0; } else { /* Need to check again after tCCDebounce */ if (((cc_status & TCPC_CC_STATUS_TOGGLING) == 0) && @@ -621,6 +624,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb if (ret == -EIO) return ret; *cc_update_handled = true; + return 0; } /* Sink or Not detected */ ret = enable_contaminant_detection(contaminant->chip, @@ -639,6 +643,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb return ret; } *cc_update_handled = false; + return 0; } else if (contaminant->state == DETECTED) { if (status_check(cc_status, TCPC_CC_STATUS_TOGGLING, 0)) { logbuffer_log(chip->log, "Contaminant: Check if dry"); @@ -652,6 +657,7 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb if (ret == -EIO) return ret; *cc_update_handled = true; + return 0; } /* @@ -664,9 +670,11 @@ int process_contaminant_alert(struct max77759_contaminant *contaminant, bool deb if (ret == -EIO) return ret; *cc_update_handled = true; + return 0; } /* TCPM does not manage ports in dry detection phase. */ *cc_update_handled = true; + return 0; } *cc_update_handled = false; diff --git a/drivers/usb/typec/tcpm/google/tcpci_max77759.c b/drivers/usb/typec/tcpm/google/tcpci_max77759.c index a06ab515308b..a40aa0002f94 100644 --- a/drivers/usb/typec/tcpm/google/tcpci_max77759.c +++ b/drivers/usb/typec/tcpm/google/tcpci_max77759.c @@ -824,6 +824,7 @@ static void enable_vbus_work(struct kthread_work *work) enum gbms_charger_modes vote = 0xff; int ret; + logbuffer_log(chip->log, "%s", __func__); if (IS_ERR_OR_NULL(chip->charger_mode_votable)) { chip->charger_mode_votable = gvotable_election_get_handle(GBMS_MODE_VOTABLE); if (IS_ERR_OR_NULL(chip->charger_mode_votable)) { @@ -1331,8 +1332,10 @@ static irqreturn_t _max77759_irq_locked(struct max77759_plat *chip, u16 status, if (chip->contaminant_detection && tcpm_is_toggling(tcpci->port)) { ret = process_contaminant_alert(chip->contaminant, false, true, &contaminant_cc_update_handled); - if (ret < 0) + if (ret < 0) { + mutex_unlock(&chip->rc_lock); goto reschedule; + } /* * Invoke TCPM when CC update not related to contaminant * detection. @@ -2360,7 +2363,7 @@ static int max77759_probe(struct i2c_client *client, { int ret, i; struct max77759_plat *chip; - char *usb_psy_name; + char *usb_psy_name, *chg_psy_name; struct device_node *dn, *ovp_dn, *conn; u8 power_status; u16 device_id; @@ -2385,13 +2388,6 @@ static int max77759_probe(struct i2c_client *client, return PTR_ERR(chip->data.regmap); } - chip->charger_mode_votable = gvotable_election_get_handle(GBMS_MODE_VOTABLE); - if (IS_ERR_OR_NULL(chip->charger_mode_votable)) { - dev_err(&client->dev, "TCPCI: GBMS_MODE_VOTABLE get failed: %ld", - PTR_ERR(chip->charger_mode_votable)); - return -EPROBE_DEFER; - } - kthread_init_work(&chip->reenable_auto_ultra_low_power_mode_work, reenable_auto_ultra_low_power_mode_work_item); alarm_init(&chip->reenable_auto_ultra_low_power_mode_alarm, ALARM_BOOTTIME, @@ -2402,6 +2398,18 @@ static int max77759_probe(struct i2c_client *client, return -EINVAL; } + chip->charger_mode_votable = gvotable_election_get_handle(GBMS_MODE_VOTABLE); + if (IS_ERR_OR_NULL(chip->charger_mode_votable)) { + dev_err(&client->dev, "TCPCI: GBMS_MODE_VOTABLE get failed: %ld\n", + PTR_ERR(chip->charger_mode_votable)); + chg_psy_name = (char *)of_get_property(dn, "chg-psy-name", NULL); + /* + * Defer when chg psy is set. This implies mode votable should be present as well. + */ + if (chg_psy_name) + return -EPROBE_DEFER; + } + chip->in_switch_gpio = -EINVAL; if (of_property_read_bool(dn, "ovp-present")) { chip->in_switch_gpio = of_get_named_gpio_flags(dn, "in-switch-gpio", 0, &flags); diff --git a/drivers/video/fbdev/core/fbcon.c b/drivers/video/fbdev/core/fbcon.c index f102519ccefb..b4260a830e78 100644 --- a/drivers/video/fbdev/core/fbcon.c +++ b/drivers/video/fbdev/core/fbcon.c @@ -2510,6 +2510,11 @@ static int fbcon_set_font(struct vc_data *vc, struct console_font *font, if (charcount != 256 && charcount != 512) return -EINVAL; + /* font bigger than screen resolution ? */ + if (w > FBCON_SWAP(info->var.rotate, info->var.xres, info->var.yres) || + h > FBCON_SWAP(info->var.rotate, info->var.yres, info->var.xres)) + return -EINVAL; + /* Make sure drawing engine can handle the font */ if (!(info->pixmap.blit_x & (1 << (font->width - 1))) || !(info->pixmap.blit_y & (1 << (font->height - 1)))) @@ -2771,6 +2776,34 @@ void fbcon_update_vcs(struct fb_info *info, bool all) } EXPORT_SYMBOL(fbcon_update_vcs); +/* let fbcon check if it supports a new screen resolution */ +int fbcon_modechange_possible(struct fb_info *info, struct fb_var_screeninfo *var) +{ + struct fbcon_ops *ops = info->fbcon_par; + struct vc_data *vc; + unsigned int i; + + WARN_CONSOLE_UNLOCKED(); + + if (!ops) + return 0; + + /* prevent setting a screen size which is smaller than font size */ + for (i = first_fb_vc; i <= last_fb_vc; i++) { + vc = vc_cons[i].d; + if (!vc || vc->vc_mode != KD_TEXT || + registered_fb[con2fb_map[i]] != info) + continue; + + if (vc->vc_font.width > FBCON_SWAP(var->rotate, var->xres, var->yres) || + vc->vc_font.height > FBCON_SWAP(var->rotate, var->yres, var->xres)) + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(fbcon_modechange_possible); + int fbcon_mode_deleted(struct fb_info *info, struct fb_videomode *mode) { diff --git a/drivers/video/fbdev/core/fbmem.c b/drivers/video/fbdev/core/fbmem.c index 00939ca2065a..3b3ccb235522 100644 --- a/drivers/video/fbdev/core/fbmem.c +++ b/drivers/video/fbdev/core/fbmem.c @@ -1019,6 +1019,16 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var) if (ret) return ret; + /* verify that virtual resolution >= physical resolution */ + if (var->xres_virtual < var->xres || + var->yres_virtual < var->yres) { + pr_warn("WARNING: fbcon: Driver '%s' missed to adjust virtual screen size (%ux%u vs. %ux%u)\n", + info->fix.id, + var->xres_virtual, var->yres_virtual, + var->xres, var->yres); + return -EINVAL; + } + if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_NOW) return 0; @@ -1109,7 +1119,9 @@ static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, return -EFAULT; console_lock(); lock_fb_info(info); - ret = fb_set_var(info, &var); + ret = fbcon_modechange_possible(info, &var); + if (!ret) + ret = fb_set_var(info, &var); if (!ret) fbcon_update_vcs(info, var.activate & FB_ACTIVATE_ALL); unlock_fb_info(info); diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 2a1dc4d0e0a3..6791f81dcc19 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -336,6 +336,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = { QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, }; +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = { + .noncpu_int_en = EXYNOS_CLUSTER0_NONCPU_INT_EN, + .noncpu_out = EXYNOS_CLUSTER0_NONCPU_OUT, + .mask_bit = 2, + .cnt_en_bit = 8, + .rst_stat_reg = EXYNOS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 0, /* CLUSTER0 WDTRESET */ + .pmu_reset_func = s3c2410wdt_noncpu_int_en, + .pmu_count_en_func = s3c2410wdt_noncpu_out, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT | QUIRK_HAS_WTCLRINT_REG | + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, +}; + +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = { + .noncpu_int_en = EXYNOS_CLUSTER1_NONCPU_INT_EN, + .noncpu_out = EXYNOS_CLUSTER1_NONCPU_OUT, + .mask_bit = 2, + .cnt_en_bit = 7, + .rst_stat_reg = EXYNOS_RST_STAT_REG_OFFSET, + .rst_stat_bit = 1, /* CLUSTER1 WDTRESET */ + .pmu_reset_func = s3c2410wdt_noncpu_int_en, + .pmu_count_en_func = s3c2410wdt_noncpu_out, + .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT | QUIRK_HAS_WTCLRINT_REG | + QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG, +}; + static const struct of_device_id s3c2410_wdt_match[] = { { .compatible = "samsung,s3c2410-wdt", .data = &drv_data_s3c2410 }, @@ -361,6 +387,10 @@ static const struct of_device_id s3c2410_wdt_match[] = { .data = &drv_data_gs101_cl0 }, { .compatible = "google,gs101-cl1-wdt", .data = &drv_data_gs101_cl1 }, + { .compatible = "google,gs201-cl0-wdt", + .data = &drv_data_gs201_cl0 }, + { .compatible = "google,gs201-cl1-wdt", + .data = &drv_data_gs201_cl1 }, {}, }; MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); diff --git a/fs/buffer.c b/fs/buffer.c index 13dd0f71f762..029e806a85bd 100644 --- a/fs/buffer.c +++ b/fs/buffer.c @@ -51,6 +51,8 @@ #include "internal.h" +#include + static int fsync_buffers_list(spinlock_t *lock, struct list_head *list); static int submit_bh_wbc(int op, int op_flags, struct buffer_head *bh, enum rw_hint hint, struct writeback_control *wbc); @@ -1262,6 +1264,7 @@ static void bh_lru_install(struct buffer_head *bh) struct buffer_head *evictee = bh; struct bh_lru *b; int i; + bool skip = false; check_irqs_on(); /* @@ -1273,6 +1276,10 @@ static void bh_lru_install(struct buffer_head *bh) if (lru_cache_disabled()) return; + trace_android_vh_bh_lru_install(bh->b_page, &skip); + if (skip) + return; + bh_lru_lock(); b = this_cpu_ptr(&bh_lrus); diff --git a/fs/erofs/zdata.c b/fs/erofs/zdata.c index 03a3dafc82f3..bff7bf2f7586 100644 --- a/fs/erofs/zdata.c +++ b/fs/erofs/zdata.c @@ -770,12 +770,9 @@ static void z_erofs_decompress_kickoff(struct z_erofs_decompressqueue *io, /* wake up the caller thread for sync decompression */ if (sync) { - unsigned long flags; - - spin_lock_irqsave(&io->u.wait.lock, flags); if (!atomic_add_return(bios, &io->pending_bios)) - wake_up_locked(&io->u.wait); - spin_unlock_irqrestore(&io->u.wait.lock, flags); + complete(&io->u.done); + return; } @@ -1186,7 +1183,7 @@ jobqueue_init(struct super_block *sb, } else { fg_out: q = fgq; - init_waitqueue_head(&fgq->u.wait); + init_completion(&fgq->u.done); atomic_set(&fgq->pending_bios, 0); } q->sb = sb; @@ -1360,8 +1357,7 @@ static void z_erofs_runqueue(struct super_block *sb, return; /* wait until all bios are completed */ - io_wait_event(io[JQ_SUBMIT].u.wait, - !atomic_read(&io[JQ_SUBMIT].pending_bios)); + wait_for_completion_io(&io[JQ_SUBMIT].u.done); /* handle synchronous decompress queue in the caller context */ z_erofs_decompress_queue(&io[JQ_SUBMIT], pagepool); diff --git a/fs/erofs/zdata.h b/fs/erofs/zdata.h index 4a69515dea75..5e9a0eb54c89 100644 --- a/fs/erofs/zdata.h +++ b/fs/erofs/zdata.h @@ -89,7 +89,7 @@ struct z_erofs_decompressqueue { z_erofs_next_pcluster_t head; union { - wait_queue_head_t wait; + struct completion done; struct work_struct work; } u; }; diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index 9aae2e6cc981..bf8059060766 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -26,12 +26,16 @@ static struct kmem_cache *ino_entry_slab; struct kmem_cache *f2fs_inode_entry_slab; -void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io) +void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io, + unsigned char reason) { f2fs_build_fault_attr(sbi, 0, 0); set_ckpt_flags(sbi, CP_ERROR_FLAG); - if (!end_io) + if (!end_io) { f2fs_flush_merged_writes(sbi); + + f2fs_handle_stop(sbi, reason); + } } /* @@ -122,7 +126,7 @@ struct page *f2fs_get_meta_page_retry(struct f2fs_sb_info *sbi, pgoff_t index) if (PTR_ERR(page) == -EIO && ++count <= DEFAULT_RETRY_IO_COUNT) goto retry; - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_META_PAGE); } return page; } diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 103e7038356f..0b2196e997b8 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -336,7 +336,8 @@ static void f2fs_write_end_io(struct bio *bio) mempool_free(page, sbi->write_io_dummy); if (unlikely(bio->bi_status)) - f2fs_stop_checkpoint(sbi, true); + f2fs_stop_checkpoint(sbi, true, + STOP_CP_REASON_WRITE_FAIL); continue; } @@ -352,7 +353,8 @@ static void f2fs_write_end_io(struct bio *bio) if (unlikely(bio->bi_status)) { mapping_set_error(page->mapping, -EIO); if (type == F2FS_WB_CP_DATA) - f2fs_stop_checkpoint(sbi, true); + f2fs_stop_checkpoint(sbi, true, + STOP_CP_REASON_WRITE_FAIL); } f2fs_bug_on(sbi, page->mapping == NODE_MAPPING(sbi) && @@ -2549,7 +2551,7 @@ bool f2fs_should_update_inplace(struct inode *inode, struct f2fs_io_info *fio) return true; /* if this is cold file, we should overwrite to avoid fragmentation */ - if (file_is_cold(inode)) + if (file_is_cold(inode) && !is_inode_flag_set(inode, FI_OPU_WRITE)) return true; return check_inplace_update_policy(inode, fio); diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index c5e7a34693b8..c09650fea4ef 100644 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -3516,6 +3516,7 @@ int f2fs_enable_quota_files(struct f2fs_sb_info *sbi, bool rdonly); int f2fs_quota_sync(struct super_block *sb, int type); loff_t max_file_blocks(struct inode *inode); void f2fs_quota_off_umount(struct super_block *sb); +void f2fs_handle_stop(struct f2fs_sb_info *sbi, unsigned char reason); int f2fs_commit_super(struct f2fs_sb_info *sbi, bool recover); int f2fs_sync_fs(struct super_block *sb, int sync); int f2fs_sanity_check_ckpt(struct f2fs_sb_info *sbi); @@ -3680,7 +3681,8 @@ static inline bool f2fs_need_rand_seg(struct f2fs_sb_info *sbi) /* * checkpoint.c */ -void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io); +void f2fs_stop_checkpoint(struct f2fs_sb_info *sbi, bool end_io, + unsigned char reason); void f2fs_flush_ckpt_thread(struct f2fs_sb_info *sbi); struct page *f2fs_grab_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); struct page *f2fs_get_meta_page(struct f2fs_sb_info *sbi, pgoff_t index); diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index ea2a5260758c..10612740060d 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -2273,7 +2273,8 @@ static int f2fs_ioc_shutdown(struct file *filp, unsigned long arg) if (ret) { if (ret == -EROFS) { ret = 0; - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, + STOP_CP_REASON_SHUTDOWN); set_sbi_flag(sbi, SBI_IS_SHUTDOWN); trace_f2fs_shutdown(sbi, in, ret); } @@ -2286,7 +2287,7 @@ static int f2fs_ioc_shutdown(struct file *filp, unsigned long arg) ret = freeze_bdev(sb->s_bdev); if (ret) goto out; - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_SHUTDOWN); set_sbi_flag(sbi, SBI_IS_SHUTDOWN); thaw_bdev(sb->s_bdev); break; @@ -2295,16 +2296,16 @@ static int f2fs_ioc_shutdown(struct file *filp, unsigned long arg) ret = f2fs_sync_fs(sb, 1); if (ret) goto out; - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_SHUTDOWN); set_sbi_flag(sbi, SBI_IS_SHUTDOWN); break; case F2FS_GOING_DOWN_NOSYNC: - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_SHUTDOWN); set_sbi_flag(sbi, SBI_IS_SHUTDOWN); break; case F2FS_GOING_DOWN_METAFLUSH: f2fs_sync_meta_pages(sbi, META, LONG_MAX, FS_META_IO); - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_SHUTDOWN); set_sbi_flag(sbi, SBI_IS_SHUTDOWN); break; case F2FS_GOING_DOWN_NEED_FSCK: diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index 3da5583f9dbb..f48b60553630 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -70,7 +70,8 @@ static int gc_thread_func(void *data) if (time_to_inject(sbi, FAULT_CHECKPOINT)) { f2fs_show_injection_info(sbi, FAULT_CHECKPOINT); - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, + STOP_CP_REASON_FAULT_INJECT); } if (!sb_start_write_trylock(sbi->sb)) { @@ -1651,7 +1652,8 @@ static int do_garbage_collect(struct f2fs_sb_info *sbi, f2fs_err(sbi, "Inconsistent segment (%u) type [%d, %d] in SSA and SIT", segno, type, GET_SUM_TYPE((&sum->footer))); set_sbi_flag(sbi, SBI_NEED_FSCK); - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, + STOP_CP_REASON_CORRUPTED_SUMMARY); goto skip; } diff --git a/fs/f2fs/inode.c b/fs/f2fs/inode.c index 5fffc2268964..d9757673f45e 100644 --- a/fs/f2fs/inode.c +++ b/fs/f2fs/inode.c @@ -700,7 +700,8 @@ void f2fs_update_inode_page(struct inode *inode) cond_resched(); goto retry; } else if (err != -ENOENT) { - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, + STOP_CP_REASON_UPDATE_INODE); } return; } diff --git a/fs/f2fs/namei.c b/fs/f2fs/namei.c index 0de98abd7282..b93695d28e43 100644 --- a/fs/f2fs/namei.c +++ b/fs/f2fs/namei.c @@ -623,6 +623,8 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry) goto fail; } f2fs_delete_entry(de, page, dir, inode); + f2fs_unlock_op(sbi); + #ifdef CONFIG_UNICODE /* VFS negative dentries are incompatible with Encoding and * Case-insensitiveness. Eventually we'll want avoid @@ -633,8 +635,6 @@ static int f2fs_unlink(struct inode *dir, struct dentry *dentry) if (IS_CASEFOLDED(dir)) d_invalidate(dentry); #endif - f2fs_unlock_op(sbi); - if (IS_DIRSYNC(dir)) f2fs_sync_fs(sbi->sb, 1); fail: diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index de1f4ac8191a..af6b14191076 100644 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -498,7 +498,7 @@ void f2fs_balance_fs(struct f2fs_sb_info *sbi, bool need) { if (time_to_inject(sbi, FAULT_CHECKPOINT)) { f2fs_show_injection_info(sbi, FAULT_CHECKPOINT); - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, STOP_CP_REASON_FAULT_INJECT); } /* balance_fs_bg is able to be pending */ @@ -809,7 +809,8 @@ int f2fs_flush_device_cache(struct f2fs_sb_info *sbi) } while (ret && --count); if (ret) { - f2fs_stop_checkpoint(sbi, false); + f2fs_stop_checkpoint(sbi, false, + STOP_CP_REASON_FLUSH_FAIL); break; } diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index bdea4ec6cebe..28541a527c64 100644 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -3861,6 +3861,26 @@ int f2fs_commit_super(struct f2fs_sb_info *sbi, bool recover) return err; } +void f2fs_handle_stop(struct f2fs_sb_info *sbi, unsigned char reason) +{ + struct f2fs_super_block *raw_super = F2FS_RAW_SUPER(sbi); + int err; + + f2fs_bug_on(sbi, reason >= MAX_STOP_REASON); + + f2fs_down_write(&sbi->sb_lock); + + if (raw_super->s_stop_reason[reason] < ((1 << BITS_PER_BYTE) - 1)) + raw_super->s_stop_reason[reason]++; + + err = f2fs_commit_super(sbi, false); + if (err) + f2fs_err(sbi, "f2fs_commit_super fails to record reason:%u err:%d", + reason, err); + + f2fs_up_write(&sbi->sb_lock); +} + static int f2fs_scan_devices(struct f2fs_sb_info *sbi) { struct f2fs_super_block *raw_super = F2FS_RAW_SUPER(sbi); diff --git a/fs/fuse/backing.c b/fs/fuse/backing.c index b536fd9e99b7..9f78384b021f 100644 --- a/fs/fuse/backing.c +++ b/fs/fuse/backing.c @@ -23,6 +23,9 @@ struct fuse_bpf_aio_req { static struct kmem_cache *fuse_bpf_aio_request_cachep; +static void fuse_stat_to_attr(struct fuse_conn *fc, struct inode *inode, + struct kstat *stat, struct fuse_attr *attr); + static void fuse_file_accessed(struct file *dst_file, struct file *src_file) { struct inode *dst_inode; @@ -181,8 +184,10 @@ void *fuse_open_finalize(struct fuse_bpf_args *fa, struct fuse_file *ff = file->private_data; struct fuse_open_out *foo = fa->out_args[0].value; - if (ff) + if (ff) { ff->fh = foo->fh; + ff->nodeid = get_fuse_inode(inode)->nodeid; + } return 0; } @@ -1153,6 +1158,9 @@ int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, struct dentry *dir_backing_entry = dir_fuse_entry->backing_path.dentry; struct inode *dir_backing_inode = dir_backing_entry->d_inode; struct dentry *backing_entry; + struct fuse_entry_out *feo = (void *)fa->out_args[0].value; + struct kstat stat; + int err; /* TODO this will not handle lookups over mount points */ inode_lock_nested(dir_backing_inode, I_MUTEX_PARENT); @@ -1165,10 +1173,23 @@ int fuse_lookup_backing(struct fuse_bpf_args *fa, struct inode *dir, fuse_entry->backing_path = (struct path) { .dentry = backing_entry, - .mnt = dir_fuse_entry->backing_path.mnt, + .mnt = mntget(dir_fuse_entry->backing_path.mnt), }; - mntget(fuse_entry->backing_path.mnt); + if (d_is_negative(backing_entry)) { + fa->error_in = -ENOENT; + return 0; + } + + err = vfs_getattr(&fuse_entry->backing_path, &stat, + STATX_BASIC_STATS, 0); + if (err) { + path_put_init(&fuse_entry->backing_path); + return err; + } + + fuse_stat_to_attr(get_fuse_conn(dir), + backing_entry->d_inode, &stat, &feo->attr); return 0; } diff --git a/fs/incfs/vfs.c b/fs/incfs/vfs.c index e97b843a4da5..7d349ee73bc3 100644 --- a/fs/incfs/vfs.c +++ b/fs/incfs/vfs.c @@ -1592,6 +1592,10 @@ static int incfs_setattr(struct dentry *dentry, struct iattr *ia) if (ia->ia_valid & ATTR_SIZE) return -EINVAL; + if ((ia->ia_valid & (ATTR_KILL_SUID|ATTR_KILL_SGID)) && + (ia->ia_valid & ATTR_MODE)) + return -EINVAL; + if (!di) return -EINVAL; backing_dentry = di->backing_path.dentry; diff --git a/include/OWNERS b/include/OWNERS index ca220f368163..19ecb0b3062c 100644 --- a/include/OWNERS +++ b/include/OWNERS @@ -14,9 +14,9 @@ per-file linux/keycombo.h=* per-file linux/keydebug-func.h=* per-file linux/keydebug.h=* per-file linux/mcu_ipc.h=* -per-file linux/mfd/samsung/rtc-s2mpg10.h=* -per-file linux/mfd/samsung/s2mpg1*=* +per-file linux/mfd/samsung/*=* per-file linux/mfd/slg51000.h=* +per-file linux/mfd/slg51002.h=* per-file linux/modem_notifier.h=* per-file linux/platform_data/lp855x.h=* per-file linux/platform_data/spi-s3c64xx.h=* @@ -26,6 +26,7 @@ per-file linux/shm_ipc.h=* per-file linux/samsung-secure-iova.h=* per-file linux/samsung-dma-heap.h=* per-file linux/samsung-dma-mapping.h=* +per-file linux/s2mpg12-key.h=* per-file linux/soc/**=* per-file linux/trusty/*=* per-file linux/usb/f_mtp.h=* diff --git a/include/dt-bindings/clock/gs201.h b/include/dt-bindings/clock/gs201.h new file mode 100644 index 000000000000..5287e446a374 --- /dev/null +++ b/include/dt-bindings/clock/gs201.h @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree binding constants for GS201 clock controller. + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_GS201_H +#define _DT_BINDINGS_CLOCK_GS201_H + +#define NONE (0 + 0) +#define OSCCLK (0 + 1) + + +#define CLK_APM_BASE (10) +#define MUX_APM_FUNCSRC (CLK_APM_BASE + 0) +#define MUX_APM_FUNC (CLK_APM_BASE + 1) +#define DOUT_CLK_APM_BOOST (CLK_APM_BASE + 2) +#define DOUT_CLK_APM_USI0_UART (CLK_APM_BASE + 3) +#define DOUT_CLK_APM_USI1_UART (CLK_APM_BASE + 4) +#define DOUT_CLK_APM_USI0_USI (CLK_APM_BASE + 5) + + +#define CLK_AUR_BASE (20) +#define UMUX_CLKCMU_AUR_AURCTL (CLK_AUR_BASE + 0) +#define UMUX_CLKCMU_AUR_NOC (CLK_AUR_BASE + 1) +#define DOUT_CLK_AUR_NOCP (CLK_AUR_BASE + 2) + + +#define CLK_TOP_BASE (50) +#define GATE_DFTMUX_CMU_CIS_CLK0 (CLK_TOP_BASE + 0) +#define GATE_DFTMUX_CMU_CIS_CLK1 (CLK_TOP_BASE + 1) +#define GATE_DFTMUX_CMU_CIS_CLK2 (CLK_TOP_BASE + 2) +#define GATE_DFTMUX_CMU_CIS_CLK3 (CLK_TOP_BASE + 3) +#define GATE_DFTMUX_CMU_CIS_CLK4 (CLK_TOP_BASE + 4) +#define GATE_DFTMUX_CMU_CIS_CLK5 (CLK_TOP_BASE + 5) +#define GATE_DFTMUX_CMU_CIS_CLK6 (CLK_TOP_BASE + 6) +#define GATE_DFTMUX_CMU_CIS_CLK7 (CLK_TOP_BASE + 7) +#define VDOUT_CLK_TOP_HSI0_NOC (CLK_TOP_BASE + 8) +#define CIS_CLK0 (CLK_TOP_BASE + 9) +#define CIS_CLK1 (CLK_TOP_BASE + 10) +#define CIS_CLK2 (CLK_TOP_BASE + 11) +#define CIS_CLK3 (CLK_TOP_BASE + 12) +#define CIS_CLK4 (CLK_TOP_BASE + 13) +#define CIS_CLK5 (CLK_TOP_BASE + 14) +#define CIS_CLK6 (CLK_TOP_BASE + 15) +#define CIS_CLK7 (CLK_TOP_BASE + 16) + + +#define CLK_NOCL0_BASE (100) +#define UMUX_CLKCMU_NOCL0_NOC (CLK_NOCL0_BASE + 0) +#define MUX_NOCL0_NOC_OPTION1 (CLK_NOCL0_BASE + 1) +#define DOUT_CLK_NOCL0_NOCP (CLK_NOCL0_BASE + 2) + + +#define CLK_NOCL1A_BASE (150) +#define UMUX_CLKCMU_NOCL1A_NOC (CLK_NOCL1A_BASE + 0) +#define DOUT_CLK_NOCL1A_NOCP (CLK_NOCL1A_BASE + 1) + + +#define CLK_NOCL1B_BASE (200) +#define UMUX_CLKCMU_NOCL1B_NOC (CLK_NOCL1B_BASE + 0) +#define DOUT_CLK_NOCL1B_NOCP (CLK_NOCL1B_BASE + 1) + + +#define CLK_NOCL2A_BASE (250) +#define UMUX_CLKCMU_NOCL2A_NOC (CLK_NOCL2A_BASE + 0) +#define DOUT_CLK_NOCL2A_NOCP (CLK_NOCL2A_BASE + 1) + + +#define CLK_EH_BASE (300) +#define UMUX_CLKCMU_EH_NOC (CLK_EH_BASE + 0) +#define UMUX_CLKCMU_EH_PLL_NOCL0 (CLK_EH_BASE + 1) +#define MUX_EH_NOC (CLK_EH_BASE + 2) +#define DOUT_CLK_EH_NOCP (CLK_EH_BASE + 3) + + +#define CLK_G3D_BASE (350) +#define GATE_GPU (CLK_G3D_BASE + 0) + + +#define CLK_DPU_BASE (400) +#define UMUX_CLKCMU_DPU_NOC (CLK_DPU_BASE + 0) +#define GATE_DPUF_DMA (CLK_DPU_BASE + 1) +#define GATE_DPUF_DPP (CLK_DPU_BASE + 2) +#define DOUT_CLK_DPU_NOCP (CLK_DPU_BASE + 3) + + +#define CLK_DISP_BASE (450) +#define UMUX_CLKCMU_DISP_NOC (CLK_DISP_BASE + 0) +#define GATE_DPUB (CLK_DISP_BASE + 1) +#define DOUT_CLK_DISP_NOCP (CLK_DISP_BASE + 2) + + +#define CLK_G2D_BASE (500) +#define UMUX_CLKCMU_G2D_G2D (CLK_G2D_BASE + 0) +#define UMUX_CLKCMU_G2D_MSCL (CLK_G2D_BASE + 1) +#define GATE_G2D (CLK_G2D_BASE + 2) +#define GATE_JPEG (CLK_G2D_BASE + 3) +#define DOUT_CLK_G2D_NOCP (CLK_G2D_BASE + 4) + + +#define CLK_HSI0_BASE (550) +#define UMUX_CLKCMU_HSI0_TCXO (CLK_HSI0_BASE + 0) +#define MUX_HSI0_USB20_REF (CLK_HSI0_BASE + 1) +#define UMUX_CLKCMU_HSI0_USB31DRD (CLK_HSI0_BASE + 2) +#define UMUX_CLKCMU_HSI0_USB20 (CLK_HSI0_BASE + 3) +#define MUX_HSI0_USB31DRD (CLK_HSI0_BASE + 4) +#define UMUX_CLKCMU_HSI0_NOC (CLK_HSI0_BASE + 5) +#define UMUX_CLKCMU_HSI0_ALT (CLK_HSI0_BASE + 6) +#define MUX_HSI0_NOC (CLK_HSI0_BASE + 7) +#define UMUX_CLKCMU_HSI0_DPGTC (CLK_HSI0_BASE + 8) +#define GATE_USB31DRD_SLV_LINK (CLK_HSI0_BASE + 9) +#define DOUT_CLK_HSI0_USB31DRD (CLK_HSI0_BASE + 10) + + +#define CLK_HSI1_BASE (600) +#define UMUX_CLKCMU_HSI1_NOC (CLK_HSI1_BASE + 0) +#define UMUX_CLKCMU_HSI1_PCIE (CLK_HSI1_BASE + 1) +#define GATE_PCIE_GEN4_0_DBG_1 (CLK_HSI1_BASE + 2) +#define GATE_PCIE_GEN4_0_AXI_1 (CLK_HSI1_BASE + 3) +#define GATE_PCIE_GEN4_0_APB_1 (CLK_HSI1_BASE + 4) +#define GATE_PCIE_GEN4_0_SCLK_1 (CLK_HSI1_BASE + 5) +#define GATE_PCIE_GEN4_0_PCS_APB (CLK_HSI1_BASE + 6) +#define GATE_PCIE_GEN4_0_PMA_APB (CLK_HSI1_BASE + 7) +#define GATE_PCIE_GEN4_0_DBG_2 (CLK_HSI1_BASE + 8) +#define GATE_PCIE_GEN4_0_AXI_2 (CLK_HSI1_BASE + 9) +#define GATE_PCIE_GEN4_0_APB_2 (CLK_HSI1_BASE + 10) +#define GATE_PCIE_GEN4_0_UDBG (CLK_HSI1_BASE + 11) + + +#define CLK_HSI2_BASE (650) +#define UMUX_CLKCMU_HSI2_NOC (CLK_HSI2_BASE + 0) +#define UMUX_CLKCMU_HSI2_PCIE (CLK_HSI2_BASE + 1) +#define UMUX_CLKCMU_HSI2_UFS_EMBD (CLK_HSI2_BASE + 2) +#define UMUX_CLKCMU_HSI2_MMC_CARD (CLK_HSI2_BASE + 3) +#define GATE_MMC_CARD (CLK_HSI2_BASE + 4) +#define GATE_PCIE_GEN4_1_AXI_1 (CLK_HSI2_BASE + 5) +#define GATE_PCIE_GEN4_1_APB_1 (CLK_HSI2_BASE + 6) +#define GATE_PCIE_GEN4_1_DBG_1 (CLK_HSI2_BASE + 7) +#define GATE_PCIE_GEN4_1_PCS_APB (CLK_HSI2_BASE + 8) +#define GATE_PCIE_GEN4_1_SCLK_1 (CLK_HSI2_BASE + 9) +#define GATE_PCIE_GEN4_1_PMA_APB (CLK_HSI2_BASE + 10) +#define GATE_PCIE_GEN4_1_AXI_2 (CLK_HSI2_BASE + 11) +#define GATE_PCIE_GEN4_1_DBG_2 (CLK_HSI2_BASE + 12) +#define GATE_PCIE_GEN4_1_APB_2 (CLK_HSI2_BASE + 13) +#define GATE_PCIE_GEN4_1_UDBG (CLK_HSI2_BASE + 14) +#define GATE_UFS_EMBD (CLK_HSI2_BASE + 15) +#define GATE_UFS_EMBD_FMP (CLK_HSI2_BASE + 16) +#define DOUT_CLKCMU_HSI2_MMC_CARD (CLK_HSI2_BASE + 17) +#define UFS_EMBD (CLK_HSI2_BASE + 18) + + +#define CLK_CSIS_BASE (700) +#define UMUX_CLKCMU_CSIS_NOC (CLK_CSIS_BASE + 0) +#define DOUT_CLK_CSIS_NOCP (CLK_CSIS_BASE + 1) + + +#define CLK_PDP_BASE (750) +#define UMUX_CLKCMU_PDP_NOC (CLK_PDP_BASE + 0) +#define UMUX_CLKCMU_PDP_VRA (CLK_PDP_BASE + 1) +#define DOUT_CLK_PDP_NOCP (CLK_PDP_BASE + 2) + + +#define CLK_IPP_BASE (800) +#define UMUX_CLKCMU_IPP_NOC (CLK_IPP_BASE + 0) +#define DOUT_CLK_IPP_NOCP (CLK_IPP_BASE + 1) + + +#define CLK_G3AA_BASE (850) +#define UMUX_CLKCMU_G3AA_G3AA (CLK_G3AA_BASE + 0) +#define DOUT_CLK_G3AA_NOCP (CLK_G3AA_BASE + 1) + + +#define CLK_ITP_BASE (900) +#define UMUX_CLKCMU_ITP_NOC (CLK_ITP_BASE + 0) +#define DOUT_CLK_ITP_NOCP (CLK_ITP_BASE + 1) + + +#define CLK_DNS_BASE (950) +#define UMUX_CLKCMU_DNS_NOC (CLK_DNS_BASE + 0) +#define DOUT_CLK_DNS_NOCP (CLK_DNS_BASE + 1) + + +#define CLK_TNR_BASE (1000) +#define UMUX_CLKCMU_TNR_NOC (CLK_TNR_BASE + 0) +#define DOUT_CLK_TNR_NOCP (CLK_TNR_BASE + 1) + + +#define CLK_MCSC_BASE (1050) +#define UMUX_CLKCMU_MCSC_ITSC (CLK_MCSC_BASE + 0) +#define UMUX_CLKCMU_MCSC_MCSC (CLK_MCSC_BASE + 1) +#define DOUT_CLK_MCSC_NOCP (CLK_MCSC_BASE + 2) + + +#define CLK_GDC_BASE (1100) +#define UMUX_CLKCMU_GDC_SCSC (CLK_GDC_BASE + 0) +#define UMUX_CLKCMU_GDC_GDC0 (CLK_GDC_BASE + 1) +#define UMUX_CLKCMU_GDC_GDC1 (CLK_GDC_BASE + 2) +#define DOUT_CLK_GDC_NOCP (CLK_GDC_BASE + 3) + + +#define CLK_MFC_BASE (1150) +#define UMUX_CLKCMU_MFC_MFC (CLK_MFC_BASE + 0) +#define DOUT_CLK_MFC_NOCP (CLK_MFC_BASE + 1) +#define GATE_MFC (CLK_MFC_BASE + 2) + + +#define CLK_MIF_BASE (1200) +#define UMUX_MIF_DDRPHY2X (CLK_MIF_BASE + 0) + + +#define CLK_MISC_BASE (1250) +#define UMUX_CLKCMU_MISC_NOC (CLK_MISC_BASE + 0) +#define UMUX_CLKCMU_MISC_SSS (CLK_MISC_BASE + 1) +#define GATE_MCT (CLK_MISC_BASE + 2) +#define DOUT_CLK_MISC_NOCP (CLK_MISC_BASE + 3) +#define GATE_WDT_CL0 (CLK_MISC_BASE + 4) +#define GATE_WDT_CL1 (CLK_MISC_BASE + 5) +#define GATE_PDMA0 (CLK_MISC_BASE + 6) +#define GATE_PDMA1 (CLK_MISC_BASE + 7) +#define ATCLK (CLK_MISC_BASE + 8) + + +#define CLK_PERIC0_BASE (1300) +#define UMUX_CLKCMU_PERIC0_NOC (CLK_PERIC0_BASE + 0) +#define UMUX_CLKCMU_PERIC0_USI0_UART (CLK_PERIC0_BASE + 1) +#define GATE_PERIC0_TOP0_USI1_USI (CLK_PERIC0_BASE + 2) +#define GATE_PERIC0_TOP0_USI2_USI (CLK_PERIC0_BASE + 3) +#define GATE_PERIC0_TOP0_USI3_USI (CLK_PERIC0_BASE + 4) +#define GATE_PERIC0_TOP0_USI4_USI (CLK_PERIC0_BASE + 5) +#define GATE_PERIC0_TOP0_USI5_USI (CLK_PERIC0_BASE + 6) +#define GATE_PERIC0_TOP0_USI6_USI (CLK_PERIC0_BASE + 7) +#define GATE_PERIC0_TOP0_USI7_USI (CLK_PERIC0_BASE + 8) +#define GATE_PERIC0_TOP0_USI8_USI (CLK_PERIC0_BASE + 9) +#define GATE_PERIC0_TOP0_I3C1 (CLK_PERIC0_BASE + 10) +#define GATE_PERIC0_TOP0_I3C2 (CLK_PERIC0_BASE + 11) +#define GATE_PERIC0_TOP0_I3C3 (CLK_PERIC0_BASE + 12) +#define GATE_PERIC0_TOP0_I3C4 (CLK_PERIC0_BASE + 13) +#define GATE_PERIC0_TOP0_I3C5 (CLK_PERIC0_BASE + 14) +#define GATE_PERIC0_TOP0_I3C6 (CLK_PERIC0_BASE + 15) +#define GATE_PERIC0_TOP0_I3C7 (CLK_PERIC0_BASE + 16) +#define GATE_PERIC0_TOP0_I3C8 (CLK_PERIC0_BASE + 17) +#define GATE_PERIC0_TOP0_S1 (CLK_PERIC0_BASE + 18) +#define GATE_PERIC0_TOP0_S2 (CLK_PERIC0_BASE + 19) +#define GATE_PERIC0_TOP0_S3 (CLK_PERIC0_BASE + 20) +#define GATE_PERIC0_TOP0_S4 (CLK_PERIC0_BASE + 21) +#define GATE_PERIC0_TOP0_S5 (CLK_PERIC0_BASE + 22) +#define GATE_PERIC0_TOP0_S6 (CLK_PERIC0_BASE + 23) +#define GATE_PERIC0_TOP0_S7 (CLK_PERIC0_BASE + 24) +#define GATE_PERIC0_TOP0_S8 (CLK_PERIC0_BASE + 25) +#define GATE_PERIC0_TOP1_USI0_UART (CLK_PERIC0_BASE + 26) +#define GATE_PERIC0_TOP1_USI14_USI (CLK_PERIC0_BASE + 27) +#define VDOUT_CLK_PERIC0_USI0_UART (CLK_PERIC0_BASE + 28) +#define VDOUT_CLK_PERIC0_USI1_USI (CLK_PERIC0_BASE + 29) +#define VDOUT_CLK_PERIC0_USI2_USI (CLK_PERIC0_BASE + 30) +#define VDOUT_CLK_PERIC0_USI3_USI (CLK_PERIC0_BASE + 31) +#define VDOUT_CLK_PERIC0_USI4_USI (CLK_PERIC0_BASE + 32) +#define VDOUT_CLK_PERIC0_USI5_USI (CLK_PERIC0_BASE + 33) +#define VDOUT_CLK_PERIC0_USI6_USI (CLK_PERIC0_BASE + 34) +#define VDOUT_CLK_PERIC0_USI7_USI (CLK_PERIC0_BASE + 35) +#define VDOUT_CLK_PERIC0_USI8_USI (CLK_PERIC0_BASE + 36) +#define VDOUT_CLK_PERIC0_USI14_USI (CLK_PERIC0_BASE + 37) +#define VDOUT_CLK_PERIC0_I3C (CLK_PERIC0_BASE + 38) + + +#define CLK_PERIC1_BASE (1400) +#define UMUX_CLKCMU_PERIC1_NOC (CLK_PERIC1_BASE + 0) +#define GATE_PERIC1_TOP0_USI0_USI (CLK_PERIC1_BASE + 1) +#define GATE_PERIC1_TOP0_USI9_USI (CLK_PERIC1_BASE + 2) +#define GATE_PERIC1_TOP0_USI10_USI (CLK_PERIC1_BASE + 3) +#define GATE_PERIC1_TOP0_USI11_USI (CLK_PERIC1_BASE + 4) +#define GATE_PERIC1_TOP0_USI12_USI (CLK_PERIC1_BASE + 5) +#define GATE_PERIC1_TOP0_USI13_USI (CLK_PERIC1_BASE + 6) +#define GATE_PERIC1_TOP0_USI15_USI (CLK_PERIC1_BASE + 7) +#define GATE_PERIC1_TOP0_USI16_USI (CLK_PERIC1_BASE + 8) +#define GATE_PERIC1_TOP0_I3C0 (CLK_PERIC1_BASE + 9) +#define GATE_PERIC1_TOP0_PWM (CLK_PERIC1_BASE + 10) +#define GATE_PERIC1_TOP0_S (CLK_PERIC1_BASE + 11) +#define VDOUT_CLK_PERIC1_USI0_USI (CLK_PERIC1_BASE + 12) +#define VDOUT_CLK_PERIC1_USI9_USI (CLK_PERIC1_BASE + 13) +#define VDOUT_CLK_PERIC1_USI10_USI (CLK_PERIC1_BASE + 14) +#define VDOUT_CLK_PERIC1_USI11_USI (CLK_PERIC1_BASE + 15) +#define VDOUT_CLK_PERIC1_USI12_USI (CLK_PERIC1_BASE + 16) +#define VDOUT_CLK_PERIC1_USI13_USI (CLK_PERIC1_BASE + 17) +#define VDOUT_CLK_PERIC1_USI15_USI (CLK_PERIC1_BASE + 18) +#define VDOUT_CLK_PERIC1_USI16_USI (CLK_PERIC1_BASE + 19) +#define VDOUT_CLK_PERIC1_I3C (CLK_PERIC1_BASE + 20) + + +#define CLK_TPU_BASE (1450) +#define UMUX_CLKCMU_TPU_TPU (CLK_TPU_BASE + 0) +#define UMUX_CLKCMU_TPU_TPUCTL (CLK_TPU_BASE + 1) +#define UMUX_CLKCMU_TPU_NOC (CLK_TPU_BASE + 2) +#define UMUX_CLKCMU_TPU_UART (CLK_TPU_BASE + 3) +#define MUX_TPU_TPU (CLK_TPU_BASE + 4) +#define MUX_TPU_TPUCTL (CLK_TPU_BASE + 5) +#define DOUT_CLK_TPU_TPU (CLK_TPU_BASE + 6) +#define DOUT_CLK_TPU_TPUCTL (CLK_TPU_BASE + 7) +#define DOUT_CLK_TPU_NOCP (CLK_TPU_BASE + 8) + + +#define CLK_BO_BASE (1500) +#define UMUX_CLKCMU_BO_NOC (CLK_BO_BASE + 0) +#define DOUT_CLK_BO_NOCP (CLK_BO_BASE + 1) + + +#define CLK_CLKOUT_BASE (1550) +#define CLKOUT1 (CLK_CLKOUT_BASE + 0) +#define CLKOUT0 (CLK_CLKOUT_BASE + 1) + +#define CLK_NR_CLKS (1700) + +#define ACPM_DVFS_MIF (0x0B040000) +#define ACPM_DVFS_INT (0x0B040001) +#define ACPM_DVFS_CPUCL0 (0x0B040002) +#define ACPM_DVFS_CPUCL1 (0x0B040003) +#define ACPM_DVFS_CPUCL2 (0x0B040004) +#define ACPM_DVFS_G3D (0x0B040005) +#define ACPM_DVFS_G3DL2 (0x0B040006) +#define ACPM_DVFS_TPU (0x0B040007) +#define ACPM_DVFS_INTCAM (0x0B040008) +#define ACPM_DVFS_TNR (0x0B040009) +#define ACPM_DVFS_CAM (0x0B04000A) +#define ACPM_DVFS_MFC (0x0B04000B) +#define ACPM_DVFS_DISP (0x0B04000C) +#define ACPM_DVFS_BO (0x0B04000D) + +#define CAMERA_CLOCK_FAMILY_CAM 0 +#define CAMERA_CLOCK_FAMILY_INTCAM 1 +#define CAMERA_CLOCK_FAMILY_TNR 2 + +#endif /* _DT_BINDINGS_CLOCK_GS201_H */ diff --git a/include/dt-bindings/interrupt-controller/gs201.h b/include/dt-bindings/interrupt-controller/gs201.h new file mode 100644 index 000000000000..1d91b64ce098 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/gs201.h @@ -0,0 +1,815 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * This header provides constants for gs201 interrupt controller. + * + * Copyright 2020 Google LLC. + * + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_GS201_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_GS201_H + +#include + +#define ITNO IRQ_TYPE_NONE +#define ITER IRQ_TYPE_EDGE_RISING +#define ITEF IRQ_TYPE_EDGE_FALLING +#define ITEB IRQ_TYPE_EDGE_BOTH +#define ITLH IRQ_TYPE_LEVEL_HIGH +#define ITLL IRQ_TYPE_LEVEL_LOW + +#define IRQ_ALIVE_EINT0 0 +#define IRQ_ALIVE_EINT1 1 +#define IRQ_ALIVE_EINT2 2 +#define IRQ_ALIVE_EINT3 3 +#define IRQ_ALIVE_EINT4 4 +#define IRQ_ALIVE_EINT5 5 +#define IRQ_ALIVE_EINT6 6 +#define IRQ_ALIVE_EINT7 7 +#define IRQ_ALIVE_EINT8 8 +#define IRQ_ALIVE_EINT9 9 +#define IRQ_ALIVE_EINT10 10 +#define IRQ_ALIVE_EINT11 11 +#define IRQ_ALIVE_EINT12 12 +#define IRQ_ALIVE_EINT13 13 +#define IRQ_ALIVE_EINT14 14 +#define IRQ_ALIVE_EINT15 15 +#define IRQ_ALIVE_EINT16 16 +#define IRQ_ALIVE_EINT17 17 +#define IRQ_ALIVE_EINT18 18 +#define IRQ_ALIVE_EINT20 19 +#define IRQ_ALIVE_EINT21 20 +#define IRQ_ALIVE_EINT22 21 +#define IRQ_ALIVE_EINT23 22 +#define IRQ_ALIVE_EINT24 23 +#define IRQ_ALIVE_EINT25 24 +#define IRQ_ALIVE_EINT26 25 +#define IRQ_ALIVE_EINT27 26 +#define IRQ_ALIVE_EINT28 27 +#define IRQ_ALIVE_EINT29 28 +#define IRQ_ALIVE_EINT30 29 +#define IRQ_ALIVE_EINT31 30 +#define IRQ_ALIVE_EINT32 31 +#define IRQ_ALIVE_EINT33 32 +#define IRQ_ALIVE_EINT34 33 +#define IRQ_ALIVE_EINT35 34 +#define IRQ_ALIVE_EINT36 35 +#define IRQ_ALIVE_EINT37 36 +#define IRQ_ALIVE_EINT38 37 +#define IRQ_ALIVE_EINT39 38 +#define IRQ_ALIVE_EINT40 39 +#define IRQ_ALIVE_EINT41 40 +#define IRQ_ALIVE_EINT42 41 +#define IRQ_ALIVE_EINT43 42 +#define IRQ_ALIVE_EINT44 43 +#define IRQ_ALIVE_EINT45 44 +#define IRQ_ALIVE_EINT46 45 +#define IRQ_ALIVE_EINT47 46 +#define IRQ_ALIVE_EINT48 47 +#define IRQ_ALIVE_EINT49 48 +#define IRQ_ALIVE_EINT50 49 +#define IRQ_ALIVE_EINT51 50 +#define IRQ_ALIVE_EINT52 51 +#define IRQ_ALIVE_EINT53 52 +#define IRQ_ALIVE_EINT54 53 +#define IRQ_ALIVE_EINT55 54 +#define IRQ_ALIVE_EINT56 55 +#define IRQ_ALIVE_EINT57 56 +#define IRQ_ALIVE_EINT58 57 +#define IRQ_ALIVE_EINT59 58 +#define IRQ_ALIVE_EINT60 59 +#define IRQ_ALIVE_EINT61 60 +#define IRQ_ALIVE_EINT62 61 +#define IRQ_ALIVE_EINT63 62 +#define IRQ_ALIVE_EINT64 63 +#define IRQ_ALIVE_EINT65 64 +#define IRQ_ALIVE_EINT66 65 +#define IRQ_APM_I3C_PMIC_ALIVE 66 +#define IRQ_APM_USI0_UART_ALIVE 67 +#define IRQ_APM_USI0_USI_ALIVE 68 +#define IRQ_APM_USI1_UART_ALIVE 69 +#define IRQ_COMB_SFI_CE_NONSECURE_SYSREG_APM_ALIVE 70 +#define IRQ_COMB_SFI_UCE_NONSECURE_SYSREG_APM_ALIVE 71 +#define IRQ_INTCOMB_VGPIO2AP_ALIVE 72 +#define IRQ_IRQB_M_ALIVE 73 +#define IRQ_IRQB_S_ALIVE 74 +#define IRQ_MAILBOX_AOCA322AP_ALIVE 75 +#define IRQ_MAILBOX_AOCF12AP_ALIVE 76 +#define IRQ_MAILBOX_AOCP62AP_ALIVE 77 +#define IRQ_MAILBOX_APM2AP_ALIVE 78 +#define IRQ_MAILBOX_AUR02AP_ALIVE 79 +#define IRQ_MAILBOX_AUR12AP_ALIVE 80 +#define IRQ_MAILBOX_AUR22AP_ALIVE 81 +#define IRQ_MAILBOX_AUR32AP_ALIVE 82 +#define IRQ_MAILBOX_DBGCORE2AP_ALIVE 83 +#define IRQ_OCP_WARN_CPUCL1_ALIVE 84 +#define IRQ_OCP_WARN_CPUCL2_ALIVE 85 +#define IRQ_OCP_WARN_GPU_ALIVE 86 +#define IRQ_OCP_WARN_TPU_ALIVE 87 +#define IRQ_ONOB_ALIVE 88 +#define IRQ_RTC_ALARM_INT_ALIVE 89 +#define IRQ_RTC_TIC_INT_0_ALIVE 90 +#define IRQ_SMPL_WARN_ALIVE 91 +#define IRQ_SOFT_OCP_WARN_CPUCL1_ALIVE 92 +#define IRQ_SOFT_OCP_WARN_CPUCL2_ALIVE 93 +#define IRQ_SOFT_OCP_WARN_GPU_ALIVE 94 +#define IRQ_SOFT_OCP_WARN_TPU_ALIVE 95 +#define IRQ_TRTC_ALARM_INT_ALIVE 96 +#define IRQ_TRTC_TIC_INT_0_ALIVE 97 +#define IRQ_VDROOP1_ALIVE 98 +#define IRQ_VDROOP2_ALIVE 99 +#define IRQ_WDT_APM_ALIVE 100 +#define IRQ_WDT_DBGCORE_ALIVE 101 +#define NONSEQINT__UASC_APM_ALIVE 102 +#define NONSEQINT__UASC_DBGCORE_ALIVE 103 +#define NONSEQINT__UASC_IG_SWD_ALIVE 104 +#define NONSEQINT__UASC_LP0_AOC_ALIVE 105 +#define NONSEQINT__UASC_P_ALIVE_ALIVE 106 +#define O_INTERRUPT_S2__SYSMMU_D_APM_ALIVE 107 +#define TZINT__UASC_APM_ALIVE 108 +#define TZINT__UASC_DBGCORE_ALIVE 109 +#define TZINT__UASC_IG_SWD_ALIVE 110 +#define TZINT__UASC_LP0_AOC_ALIVE 111 +#define TZINT__UASC_P_ALIVE_ALIVE 112 +#define INTR_AOC_PPMU_AOC 113 +#define INTR_AOCUSB_PPMU_AOC 114 +#define IRQ_AOC_TIMER0_AOC 115 +#define IRQ_AOC_Watchdog_CPU_AOC 116 +#define INTREQ_AOCPLL_LOCK_STATUS_AOC 117 +#define IRQ_SYSMMU_AOC_S1_NS_AOC 118 +#define IRQ_SYSMMU_AOC_S1_S_AOC 119 +#define IRQ_SYSMMU_AOC_S2_AOC 120 +#define IRQ_UASC_NS_AOC_AOC 121 +#define IRQ_UASC_S_AOC_AOC 122 +#define IRQ_ADD_APBIF_AUR_AUR 123 +#define IRQ_AUR_AP_REQ_AUR 124 +#define IRQ_AUR_IDMA_IRQ_0_AUR 125 +#define IRQ_AUR_IDMA_IRQ_1_AUR 126 +#define IRQ_AUR_IDMA_IRQ_2_AUR 127 +#define IRQ_AUR_IDMA_IRQ_3_AUR 128 +#define IRQ_AUR_PG_REQ_AUR 129 +#define IRQ_AUR_WDOG_APM_IRQ_AUR 130 +#define IRQ_AUR_WDOG_CPU_IRQ_AUR 131 +#define IRQ_PPMU_AUR0_UPPER_OR_NORMAL_AUR 132 +#define IRQ_PPMU_AUR1_UPPER_OR_NORMAL_AUR 133 +#define IRQ_SSMT_AUR0_AUR 134 +#define IRQ_SSMT_AUR1_AUR 135 +#define IRQ_SYSMMU_S1_NS_AUR0_AUR 136 +#define IRQ_SYSMMU_S1_NS_AUR1_AUR 137 +#define IRQ_SYSMMU_S1_S_AUR0_AUR 138 +#define IRQ_SYSMMU_S1_S_AUR1_AUR 139 +#define IRQ_SYSMMU_S2_AUR0_AUR 140 +#define IRQ_SYSMMU_S2_AUR1_AUR 141 +#define IRQ_UASC_NS_AUR_AUR 142 +#define IRQ_UASC_S_AUR_AUR 143 +#define IRQ_BO_XINT_BO 144 +#define IRQ_PPMU_UPPER_OR_NORMAL_BO 145 +#define IRQ_SSMT_BO_BO 146 +#define IRQ_SYSMMU_S1_NS_BO_BO 147 +#define IRQ_SYSMMU_S1_S_BO_BO 148 +#define IRQ_SYSMMU_S2_BO_BO 149 +#define IRQ_UASC_NS_BO_BO 150 +#define IRQ_UASC_S_BO_BO 151 +#define IRQ_CPUCL0_CLUSTERPMUIRQ_CPUCL0 152 +#define IRQ_CPUCL0_DDD_APBIF0_FAST_PEND_CPUCL0 153 +#define IRQ_CPUCL0_DDD_APBIF0_HIGH_PEND_CPUCL0 154 +#define IRQ_CPUCL0_DDD_APBIF0_LOW_PEND_CPUCL0 155 +#define IRQ_CPUCL0_DDD_APBIF0_SLOW_PEND_CPUCL0 156 +#define IRQ_CPUCL0_DDD_APBIF1_FAST_PEND_CPUCL0 157 +#define IRQ_CPUCL0_DDD_APBIF1_HIGH_PEND_CPUCL0 158 +#define IRQ_CPUCL0_DDD_APBIF1_LOW_PEND_CPUCL0 159 +#define IRQ_CPUCL0_DDD_APBIF1_SLOW_PEND_CPUCL0 160 +#define IRQ_CPUCL0_DDD_APBIF2_FAST_PEND_CPUCL0 161 +#define IRQ_CPUCL0_DDD_APBIF2_HIGH_PEND_CPUCL0 162 +#define IRQ_CPUCL0_DDD_APBIF2_LOW_PEND_CPUCL0 163 +#define IRQ_CPUCL0_DDD_APBIF2_SLOW_PEND_CPUCL0 164 +#define IRQ_CPUCL0_DDD_APBIF3_FAST_PEND_CPUCL0 165 +#define IRQ_CPUCL0_DDD_APBIF3_HIGH_PEND_CPUCL0 166 +#define IRQ_CPUCL0_DDD_APBIF3_LOW_PEND_CPUCL0 167 +#define IRQ_CPUCL0_DDD_APBIF3_SLOW_PEND_CPUCL0 168 +#define IRQ_CPUCL0_ERRIRQ_0_CPUCL0 169 +#define IRQ_CPUCL0_ERRIRQ_1_CPUCL0 170 +#define IRQ_CPUCL0_ERRIRQ_2_CPUCL0 171 +#define IRQ_CPUCL0_ERRIRQ_3_CPUCL0 172 +#define IRQ_CPUCL0_ERRIRQ_4_CPUCL0 173 +#define IRQ_CPUCL0_ERRIRQ_5_CPUCL0 174 +#define IRQ_CPUCL0_ERRIRQ_6_CPUCL0 175 +#define IRQ_CPUCL0_ERRIRQ_7_CPUCL0 176 +#define IRQ_CPUCL0_ERRIRQ_8_CPUCL0 177 +#define IRQ_CPUCL0_FAULTIRQ_0_CPUCL0 178 +#define IRQ_CPUCL0_FAULTIRQ_1_CPUCL0 179 +#define IRQ_CPUCL0_FAULTIRQ_2_CPUCL0 180 +#define IRQ_CPUCL0_FAULTIRQ_3_CPUCL0 181 +#define IRQ_CPUCL0_FAULTIRQ_4_CPUCL0 182 +#define IRQ_CPUCL0_FAULTIRQ_5_CPUCL0 183 +#define IRQ_CPUCL0_FAULTIRQ_6_CPUCL0 184 +#define IRQ_CPUCL0_FAULTIRQ_7_CPUCL0 185 +#define IRQ_CPUCL0_FAULTIRQ_8_CPUCL0 186 +#define O_HPM_IRQ_CPUCL0_CPUCL0 187 +#define INTREQ_SYSMMU_S2_CPUCL0_CPUCL0 188 +#define IRQ_CSIS0_CSIS 189 +#define IRQ_CSIS1_CSIS 190 +#define IRQ_CSIS2_CSIS 191 +#define IRQ_CSIS3_CSIS 192 +#define IRQ_CSIS4_CSIS 193 +#define IRQ_CSIS5_CSIS 194 +#define IRQ_CSIS6_CSIS 195 +#define IRQ_CSIS7_CSIS 196 +#define IRQ_CSIS_DMA0_CSIS 197 +#define IRQ_CSIS_DMA1_CSIS 198 +#define IRQ_CSIS_DMA2_CSIS 199 +#define IRQ_CSIS_DMA3_CSIS 200 +#define IRQ_EBUF_OVERFLOW0_CSIS 201 +#define IRQ_EBUF_OVERFLOW1_CSIS 202 +#define IRQ_EBUF_OVERFLOW2_CSIS 203 +#define IRQ_EBUF_OVERFLOW3_CSIS 204 +#define IRQ_MUTE_CSIS0_CSIS 205 +#define IRQ_MUTE_CSIS1_CSIS 206 +#define IRQ_MUTE_CSIS2_CSIS 207 +#define IRQ_MUTE_CSIS3_CSIS 208 +#define IRQ_MUTE_STRP0_CSIS 209 +#define IRQ_MUTE_STRP1_CSIS 210 +#define IRQ_MUTE_STRP2_CSIS 211 +#define IRQ_MUTE_ZSL0_CSIS 212 +#define IRQ_MUTE_ZSL1_CSIS 213 +#define IRQ_MUTE_ZSL2_CSIS 214 +#define IRQ_PPMU_D0_CSIS_UPPER_OR_NORMAL_CSIS 215 +#define IRQ_PPMU_D1_CSIS_UPPER_OR_NORMAL_CSIS 216 +#define IRQ_STRP_DMA0_CSIS 217 +#define IRQ_STRP_DMA1_CSIS 218 +#define IRQ_STRP_DMA2_CSIS 219 +#define IRQ_SYSMMU_D0_CSIS_S1_NS_CSIS 220 +#define IRQ_SYSMMU_D0_CSIS_S1_S_CSIS 221 +#define INTREQ__SECURE_LOG 224 +#define IRQ_SYSMMU_D0_CSIS_S2_CSIS 230 +#define IRQ_SYSMMU_D1_CSIS_S1_NS_CSIS 231 +#define IRQ_SYSMMU_D1_CSIS_S1_S_CSIS 232 +#define IRQ_SYSMMU_D1_CSIS_S2_CSIS 233 +#define IRQ_ZSL_DMA0_CSIS 234 +#define IRQ_ZSL_DMA1_CSIS 235 +#define IRQ_ZSL_DMA2_CSIS 236 +#define IRQ_DISP_DECON0_DQE_DIMMING_END_DISP 237 +#define IRQ_DISP_DECON0_DQE_DIMMING_START_DISP 238 +#define IRQ_DISP_DECON0_EXTRA_DISP 239 +#define IRQ_DISP_DECON0_FRAME_DONE_DISP 240 +#define IRQ_DISP_DECON0_FRAME_START_DISP 241 +#define IRQ_DISP_DECON1_DQE_DIMMING_END_DISP 242 +#define IRQ_DISP_DECON1_DQE_DIMMING_START_DISP 243 +#define IRQ_DISP_DECON1_EXTRA_DISP 244 +#define IRQ_DISP_DECON1_FRAME_DONE_DISP 245 +#define IRQ_DISP_DECON1_FRAME_START_DISP 246 +#define IRQ_DISP_DECON2_EXTRA_DISP 247 +#define IRQ_DISP_DECON2_FRAME_DONE_DISP 248 +#define IRQ_DISP_DECON2_FRAME_START_DISP 249 +#define IRQ_DISP_DSIM0_DISP 250 +#define IRQ_DISP_DSIM1_DISP 251 +#define IRQ_DNS_0_DNS 252 +#define IRQ_DNS_1_DNS 253 +#define IRQ_DNS_MUTE_DNS 254 +#define IRQ_PPMU_D0_DNS_UPPER_OR_NORMAL_DNS 255 +#define IRQ_PPMU_D1_DNS_UPPER_OR_NORMAL_DNS 256 +#define IRQ_SYSMMU_DNS_S1_NS_DNS 257 +#define IRQ_SYSMMU_DNS_S1_S_DNS 258 +#define IRQ_SYSMMU_DNS_S2_DNS 259 +#define IRQ_DPU_DMA_CGC0_DPU 260 +#define IRQ_DPU_DMA_CGC1_DPU 261 +#define IRQ_DPU_DMA_L0_DPU 262 +#define IRQ_DPU_DMA_L1_DPU 263 +#define IRQ_DPU_DMA_L2_DPU 264 +#define IRQ_DPU_DMA_L3_DPU 265 +#define IRQ_DPU_DMA_L4_DPU 266 +#define IRQ_DPU_DMA_L5_DPU 267 +#define IRQ_DPU_DMA_RCD0_DPU 268 +#define IRQ_DPU_DMA_RCD1_DPU 269 +#define IRQ_DPU_DMA_WB_DPU 270 +#define IRQ_DPU_DPP_L0_DPU 271 +#define IRQ_DPU_DPP_L1_DPU 272 +#define IRQ_DPU_DPP_L2_DPU 273 +#define IRQ_DPU_DPP_L3_DPU 274 +#define IRQ_DPU_DPP_L4_DPU 275 +#define IRQ_DPU_DPP_L5_DPU 276 +#define IRQ_PPMU_DPUD0_UPPER_OR_NORMAL_DPU 277 +#define IRQ_PPMU_DPUD1_UPPER_OR_NORMAL_DPU 278 +#define IRQ_PPMU_DPUD2_UPPER_OR_NORMAL_DPU 279 +#define IRQ_SYSMMU_DPUD0_S1_NS_DPU 280 +#define IRQ_SYSMMU_DPUD0_S1_S_DPU 281 +#define IRQ_SYSMMU_DPUD0_S2_DPU 282 +#define IRQ_SYSMMU_DPUD1_S1_NS_DPU 283 +#define IRQ_SYSMMU_DPUD1_S1_S_DPU 284 +#define IRQ_SYSMMU_DPUD1_S2_DPU 285 +#define IRQ_SYSMMU_DPUD2_S1_NS_DPU 286 +#define IRQ_SYSMMU_DPUD2_S1_S_DPU 287 +#define IRQ_SYSMMU_DPUD2_S2_DPU 288 +#define IRQ_EH_0_EH 289 +#define IRQ_EH_1_EH 290 +#define IRQ_EH_2_EH 291 +#define IRQ_EH_3_EH 292 +#define IRQ_EH_4_EH 293 +#define IRQ_EH_5_EH 294 +#define IRQ_EH_6_EH 295 +#define IRQ_EH_7_EH 296 +#define IRQ_EH_8_EH 297 +#define IRQ_EH_9_EH 298 +#define IRQ_PPMU_UPPER_OR_NORMAL_EH 299 +#define IRQ_SSMT_EH_EH 300 +#define IRQ_SYSMMU_S2_EH_EH 301 +#define IRQ_UASC_GSA_EH_EH 302 +#define IRQ_UASC_NS_EH_EH 303 +#define IRQ_UASC_S_EH_EH 304 +#define IRQ_G2D_G2D 305 +#define IRQ_JPEG_G2D 306 +#define IRQ_PPMU_D0_G2D_IUON_G2D 307 +#define IRQ_PPMU_D1_G2D_IUON_G2D 308 +#define IRQ_PPMU_D2_G2D_IUON_G2D 309 +#define IRQ_SSMT_D0_G2D_intreq_G2D 310 +#define IRQ_SSMT_D1_G2D_intreq_G2D 311 +#define IRQ_SSMT_D2_G2D_intreq_G2D 312 +#define IRQ_SYSMMU_D0_G2D_interrupt_s1_ns_G2D 313 +#define IRQ_SYSMMU_D0_G2D_interrupt_s2_G2D 314 +#define IRQ_SYSMMU_D0_G2D_interrupt_s1_s_G2D 315 +#define IRQ_SYSMMU_D1_G2D_interrupt_s1_ns_G2D 316 +#define IRQ_SYSMMU_D1_G2D_interrupt_s2_G2D 317 +#define IRQ_SYSMMU_D1_G2D_interrupt_s1_s_G2D 318 +#define IRQ_SYSMMU_D2_G2D_interrupt_s1_ns_G2D 319 +#define IRQ_SYSMMU_D2_G2D_interrupt_s2_G2D 320 +#define IRQ_SYSMMU_D2_G2D_interrupt_s1_s_G2D 321 +#define IRQ_G3AA_G3AA 322 +#define IRQ_PPMU_G3AA_UPPER_OR_NORMAL_G3AA 323 +#define IRQ_SSMT_G3AA_G3AA 324 +#define IRQ_SYSMMU_G3AA_S1_NS_G3AA 325 +#define IRQ_SYSMMU_G3AA_S1_S_G3AA 326 +#define IRQ_SYSMMU_G3AA_S2_G3AA 327 +#define IRQ_G3D_IRQGPU_G3D 328 +#define IRQ_G3D_IRQJOB_G3D 329 +#define IRQ_G3D_IRQMMU_G3D 330 +#define IRQ_UASC_GSA_G3D_G3D 331 +#define IRQ_UASC_NS_G3D_G3D 332 +#define IRQ_UASC_S_G3D_G3D 333 +#define O_ADD_APBIF_G3D_FLAG_IRQ_PEND_G3D 334 +#define O_DDD_APBIF_G3D_DD_ERR_IRQ_FAST_PEND_G3D 335 +#define O_DDD_APBIF_G3D_DD_ERR_IRQ_SLOW_PEND_G3D 336 +#define O_HPM_IRQ_G3D 337 +#define IRQ_GDC0_IRQ_0_GDC 338 +#define IRQ_GDC0_IRQ_1_GDC 339 +#define IRQ_GDC0_Mute_IRQ_GDC 340 +#define IRQ_GDC1_IRQ_0_GDC 341 +#define IRQ_GDC1_IRQ_1_GDC 342 +#define IRQ_GDC1_Mute_IRQ_GDC 343 +#define IRQ_PPMU_D0_GDC_UPPER_OR_NORMAL_GDC 344 +#define IRQ_PPMU_D0_SCSC_UPPER_OR_NORMAL_GDC 345 +#define IRQ_PPMU_D1_GDC_UPPER_OR_NORMAL_GDC 346 +#define IRQ_PPMU_D1_SCSC_UPPER_OR_NORMAL_GDC 347 +#define IRQ_PPMU_D2_GDC_UPPER_OR_NORMAL_GDC 348 +#define IRQ_PPMU_D2_SCSC_UPPER_OR_NORMAL_GDC 349 +#define IRQ_PPMU_D3_GDC_UPPER_OR_NORMAL_GDC 350 +#define IRQ_SCSC_IRQ_0_GDC 351 +#define IRQ_SCSC_IRQ_1_GDC 352 +#define IRQ_SCSC_NonSecu_Mute_IRQ_GDC 353 +#define IRQ_SYSMMU_D0_GDC_S1_NS_GDC 354 +#define IRQ_SYSMMU_D0_GDC_S1_S_GDC 355 +#define IRQ_SYSMMU_D0_GDC_S2_GDC 356 +#define IRQ_SYSMMU_D1_GDC_S1_NS_GDC 357 +#define IRQ_SYSMMU_D1_GDC_S1_S_GDC 358 +#define IRQ_SYSMMU_D1_GDC_S2_GDC 359 +#define IRQ_SYSMMU_D2_GDC_S1_NS_GDC 360 +#define IRQ_SYSMMU_D2_GDC_S1_S_GDC 361 +#define IRQ_SYSMMU_D2_GDC_S2_GDC 362 +#define IRQ_MAILBOX_GSA2NONTZ_GSA 363 +#define IRQ_MAILBOX_GSA2TZ_GSA 364 +#define SYSMMU_NS__INTERRUPT_GSA 365 +#define SYSMMU_S2MPU__INTERRUPT_GSA 366 +#define SYSMMU_S__INTERRUPT_GSA 367 +#define IRQ_DP_LINK_HSI0 368 +#define IRQ_PPMU_HSI0_AOC_UPPER_OR_NORMAL_HSI0 369 +#define IRQ_PPMU_HSI0_NOCL1B_UPPER_OR_NORMAL_HSI0 370 +#define IRQ_SYSMMU_USB_S1_NS_HSI0 371 +#define IRQ_SYSMMU_USB_S1_S_HSI0 372 +#define IRQ_SYSMMU_USB_S2_HSI0 373 +#define IRQ_USB2_REMOTE_CONNECT_GIC_HSI0 374 +#define IRQ_USB2_REMOTE_TIMER_GIC_HSI0 375 +#define IRQ_USB2_REMOTE_WAKEUP_GIC_HSI0 376 +#define IRQ_USB31DRD_FSVMINUS_GIC_HSI0 377 +#define IRQ_USB31DRD_FSVPLUS_GIC_HSI0 378 +#define IRQ_USB31DRD_GIC_0_HSI0 379 +#define IRQ_USB31DRD_GIC_1_HSI0 380 +#define IRQ_USB_UDBG_HSI0 381 +#define IRQ_USB_WAKEUP_HSI0 382 +#define NONSEQINT__UASC_HSI0_CTRL_HSI0 383 +#define NONSEQINT__UASC_HSI0_LINK_HSI0 384 +#define TZINT__UASC_HSI0_CTRL_HSI0 385 +#define TZINT__UASC_HSI0_LINK_HSI0 386 +#define IRQ_GPIO_HSI1_HSI1 387 +#define IRQ_PCIE_GEN4A_0_HSI1 388 +#define IRQ_PCIE_GEN4A_MSI_0_HSI1 389 +#define IRQ_PCIE_GEN4A_MSI_1_HSI1 390 +#define IRQ_PCIE_GEN4A_MSI_2_HSI1 391 +#define IRQ_PCIE_GEN4A_MSI_3_HSI1 392 +#define IRQ_PCIE_GEN4A_MSI_4_HSI1 393 +#define IRQ_PCIE_GEN4B_0_HSI1 394 +#define IRQ_PCIE_GEN4B_MSI_0_HSI1 395 +#define IRQ_PCIE_GEN4B_MSI_1_HSI1 396 +#define IRQ_PCIE_GEN4B_MSI_2_HSI1 397 +#define IRQ_PCIE_GEN4B_MSI_3_HSI1 398 +#define IRQ_PCIE_GEN4B_MSI_4_HSI1 399 +#define IRQ_PCIE_IA_GEN4A_0_HSI1 400 +#define IRQ_PCIE_IA_GEN4B_0_HSI1 401 +#define IRQ_PCIE_PCS_GEN4A_0_HSI1 402 +#define IRQ_PCIE_PCS_GEN4B_0_HSI1 403 +#define IRQ_PPMU_HSI1_UPPER_OR_NORMAL_HSI1 404 +#define IRQ_SSMT_HSI1_HSI1 405 +#define IRQ_SYSMMU_HSI1_S1_NS_HSI1 406 +#define IRQ_SYSMMU_HSI1_S1_S_HSI1 407 +#define IRQ_SYSMMU_HSI1_S2_HSI1 408 +#define IRQ_UASC_GSA_PCIE_GEN4A_DBI_0_HSI1 409 +#define IRQ_UASC_GSA_PCIE_GEN4A_SLV_0_HSI1 410 +#define IRQ_UASC_GSA_PCIE_GEN4B_DBI_0_HSI1 411 +#define IRQ_UASC_GSA_PCIE_GEN4B_SLV_0_HSI1 412 +#define IRQ_UASC_NS_PCIE_GEN4A_DBI_0_HSI1 413 +#define IRQ_UASC_NS_PCIE_GEN4A_SLV_0_HSI1 414 +#define IRQ_UASC_NS_PCIE_GEN4B_DBI_0_HSI1 415 +#define IRQ_UASC_NS_PCIE_GEN4B_SLV_0_HSI1 416 +#define IRQ_UASC_S_PCIE_GEN4A_DBI_0_HSI1 417 +#define IRQ_UASC_S_PCIE_GEN4A_SLV_0_HSI1 418 +#define IRQ_UASC_S_PCIE_GEN4B_DBI_0_HSI1 419 +#define IRQ_UASC_S_PCIE_GEN4B_SLV_0_HSI1 420 +#define IRQ_GPIO_HSI2_HSI2 421 +#define IRQ_GPIO_HSI2UFS_HSI2 422 +#define IRQ_MMC_CARD_HSI2 423 +#define IRQ_NONSEQINT_PCIE_GEN4A_DBI_1_HSI2 424 +#define IRQ_NONSEQINT_PCIE_GEN4A_SLV_1_HSI2 425 +#define IRQ_NONSEQINT_PCIE_GEN4B_DBI_1_HSI2 426 +#define IRQ_NONSEQINT_PCIE_GEN4B_SLV_1_HSI2 427 +#define IRQ_PCIE_GEN4A_1_HSI2 428 +#define IRQ_PCIE_GEN4A_1_MSI_0_HSI2 429 +#define IRQ_PCIE_GEN4A_1_MSI_1_HSI2 430 +#define IRQ_PCIE_GEN4A_1_MSI_2_HSI2 431 +#define IRQ_PCIE_GEN4A_1_MSI_3_HSI2 432 +#define IRQ_PCIE_GEN4A_1_MSI_4_HSI2 433 +#define IRQ_PCIE_GEN4B_1_HSI2 434 +#define IRQ_PCIE_GEN4B_1_MSI_0_HSI2 435 +#define IRQ_PCIE_GEN4B_1_MSI_1_HSI2 436 +#define IRQ_PCIE_GEN4B_1_MSI_2_HSI2 437 +#define IRQ_PCIE_GEN4B_1_MSI_3_HSI2 438 +#define IRQ_PCIE_GEN4B_1_MSI_4_HSI2 439 +#define IRQ_PCIE_IA_GEN4A_1_HSI2 440 +#define IRQ_PCIE_IA_GEN4B_1_HSI2 441 +#define IRQ_PCIE_PCS_GEN4A_1_HSI2 442 +#define IRQ_PCIE_PCS_GEN4B_1_HSI2 443 +#define IRQ_PPMU_HSI2_UPPER_OR_NORMAL_HSI2 444 +#define IRQ_SSMT_HSI2_HSI2 445 +#define IRQ_SYSMMU_HSI2_S1_NS_HSI2 446 +#define IRQ_SYSMMU_HSI2_S1_S_HSI2 447 +#define IRQ_SYSMMU_HSI2_S2_HSI2 448 +#define IRQ_TZINT_PCIE_GEN4A_DBI_1_HSI2 449 +#define IRQ_TZINT_PCIE_GEN4A_SLV_1_HSI2 450 +#define IRQ_TZINT_PCIE_GEN4B_DBI_1_HSI2 451 +#define IRQ_TZINT_PCIE_GEN4B_SLV_1_HSI2 452 +#define IRQ_UFS_EMBD_HSI2 453 +#define IRQ_IPP_CH0_0_IPP 454 +#define IRQ_IPP_CH0_1_IPP 455 +#define IRQ_IPP_CH1_0_IPP 456 +#define IRQ_IPP_CH1_1_IPP 457 +#define IRQ_IPP_CH2_0_IPP 458 +#define IRQ_IPP_CH2_1_IPP 459 +#define IRQ_MUTE_GTNR_ALIGN_IPP 460 +#define IRQ_MUTE_IPP0_IPP 461 +#define IRQ_MUTE_IPP1_IPP 462 +#define IRQ_MUTE_IPP2_IPP 463 +#define IRQ_PPMU_IPP_UPPER_OR_NORMAL_IPP 464 +#define IRQ_PPMU_MSA_UPPER_OR_NORMAL_IPP 465 +#define IRQ_SECU_GTNR_ALIGN_IPP 466 +#define IRQ_SECU_IPP0_IPP 467 +#define IRQ_SECU_IPP1_IPP 468 +#define IRQ_SECU_IPP2_IPP 469 +#define IRQ_SYSMMU_IPP_S1_NS_IPP 470 +#define IRQ_SYSMMU_IPP_S1_S_IPP 471 +#define IRQ_SYSMMU_IPP_S2_IPP 472 +#define IRQ_TNR_A_IPP 473 +#define INTREQ_ITP_0_ITP 474 +#define INTREQ_ITP_1_ITP 475 +#define IRQ_PPMU_ITP_UPPER_OR_NORMAL_ITP 476 +#define INTREQ_SECU_ITP_ITP 477 +#define INTREQ_SECU_MUTE_ITP 478 +#define IRQ_C2COM_MCSC_0_MCSC 479 +#define IRQ_C2COM_MCSC_1_MCSC 480 +#define IRQ_C2R_MCSC_0_MCSC 481 +#define IRQ_C2R_MCSC_1_MCSC 482 +#define IRQ_ITSC_0_MCSC 483 +#define IRQ_ITSC_1_MCSC 484 +#define IRQ_ITSC_NonSecu_Mute_MCSC 485 +#define IRQ_ITSC_Secu_MCSC 486 +#define IRQ_MCSC_0_MCSC 487 +#define IRQ_MCSC_1_MCSC 488 +#define IRQ_MCSC_NonSecu_Mute_MCSC 489 +#define IRQ_MCSC_Secu_MCSC 490 +#define IRQ_PPMU_D0_ITSC_UPPER_OR_NORMAL_MCSC 491 +#define IRQ_PPMU_D0_MCSC_UPPER_OR_NORMAL_MCSC 492 +#define IRQ_PPMU_D1_ITSC_UPPER_OR_NORMAL_MCSC 493 +#define IRQ_PPMU_D1_MCSC_UPPER_OR_NORMAL_MCSC 494 +#define IRQ_SYSMMU_D0_MCSC_S1_NS_MCSC 495 +#define IRQ_SYSMMU_D0_MCSC_S1_S_MCSC 496 +#define IRQ_SYSMMU_D0_MCSC_S2_MCSC 497 +#define IRQ_SYSMMU_D1_MCSC_S1_NS_MCSC 498 +#define IRQ_SYSMMU_D1_MCSC_S1_S_MCSC 499 +#define IRQ_SYSMMU_D1_MCSC_S2_MCSC 500 +#define IRQ_SYSMMU_D2_MCSC_S1_NS_MCSC 501 +#define IRQ_SYSMMU_D2_MCSC_S1_S_MCSC 502 +#define IRQ_SYSMMU_D2_MCSC_S2_MCSC 503 +#define IRQ_MFC_MFC 504 +#define IRQ_PPMU_D0_MFC_IUON_MFC 505 +#define IRQ_PPMU_D1_MFC_IUON_MFC 506 +#define IRQ_SYSMMU_D0_MFC_interrupt_s1_ns_MFC 507 +#define IRQ_SYSMMU_D0_MFC_interrupt_s1_s_MFC 508 +#define IRQ_SYSMMU_D0_MFC_interrupt_s2_MFC 509 +#define IRQ_SYSMMU_D1_MFC_interrupt_s1_ns_MFC 510 +#define IRQ_SYSMMU_D1_MFC_interrupt_s1_s_MFC 511 +#define IRQ_SYSMMU_D1_MFC_interrupt_s2_MFC 512 +#define IRQ_DMC_APBACCESSINT_MIF0 513 +#define IRQ_DMC_ECC_CORERR_MIF0 514 +#define IRQ_DMC_ECC_UNCORERR_MIF0 515 +#define IRQ_DMC_PPMPINT_MIF0 516 +#define IRQ_DMC_TEMPERR_MIF0 517 +#define IRQ_DMC_TEMPHOT_MIF0 518 +#define IRQ_DMC_TZCINT_MIF0 519 +#define IRQ_DMC_APBACCESSINT_MIF1 520 +#define IRQ_DMC_ECC_CORERR_MIF1 521 +#define IRQ_DMC_ECC_UNCORERR_MIF1 522 +#define IRQ_DMC_PPMPINT_MIF1 523 +#define IRQ_DMC_TEMPERR_MIF1 524 +#define IRQ_DMC_TEMPHOT_MIF1 525 +#define IRQ_DMC_TZCINT_MIF1 526 +#define IRQ_DMC_APBACCESSINT_MIF2 527 +#define IRQ_DMC_ECC_CORERR_MIF2 528 +#define IRQ_DMC_ECC_UNCORERR_MIF2 529 +#define IRQ_DMC_PPMPINT_MIF2 530 +#define IRQ_DMC_TEMPERR_MIF2 531 +#define IRQ_DMC_TEMPHOT_MIF2 532 +#define IRQ_DMC_TZCINT_MIF2 533 +#define IRQ_DMC_APBACCESSINT_MIF3 534 +#define IRQ_DMC_ECC_CORERR_MIF3 535 +#define IRQ_DMC_ECC_UNCORERR_MIF3 536 +#define IRQ_DMC_PPMPINT_MIF3 537 +#define IRQ_DMC_TEMPERR_MIF3 538 +#define IRQ_DMC_TEMPHOT_MIF3 539 +#define IRQ_DMC_TZCINT_MIF3 540 +#define IRQ_BDU_O_INT_NOCL0 541 +#define IRQ_CCI_nERRIRQ_NOCL0 542 +#define IRQ_CCI_nEVNTCNTOVERFLOW_0_NOCL0 543 +#define IRQ_CCI_nEVNTCNTOVERFLOW_1_NOCL0 544 +#define IRQ_CCI_nEVNTCNTOVERFLOW_2_NOCL0 545 +#define IRQ_CCI_nEVNTCNTOVERFLOW_3_NOCL0 546 +#define IRQ_CCI_nEVNTCNTOVERFLOW_4_NOCL0 547 +#define IRQ_CCI_nEVNTCNTOVERFLOW_5_NOCL0 548 +#define IRQ_CCI_nEVNTCNTOVERFLOW_6_NOCL0 549 +#define IRQ_CCI_nEVNTCNTOVERFLOW_7_NOCL0 550 +#define IRQ_LD_SLC_CH0_O_APC_NS_IRQ_NOCL0 551 +#define IRQ_LD_SLC_CH0_O_APC_S_IRQ_NOCL0 552 +#define IRQ_LD_SLC_CH0_O_PPMPU_IRQ_NOCL0 553 +#define IRQ_LD_SLC_CH0_O_UASC_GSA_IRQ_NOCL0 554 +#define IRQ_LD_SLC_CH0_O_UASC_NS_IRQ_NOCL0 555 +#define IRQ_LD_SLC_CH0_O_UASC_TZ_IRQ_NOCL0 556 +#define IRQ_LD_SLC_CH1_O_APC_NS_IRQ_NOCL0 557 +#define IRQ_LD_SLC_CH1_O_APC_S_IRQ_NOCL0 558 +#define IRQ_LD_SLC_CH1_O_PPMPU_IRQ_NOCL0 559 +#define IRQ_LD_SLC_CH1_O_UASC_GSA_IRQ_NOCL0 560 +#define IRQ_LD_SLC_CH1_O_UASC_NS_IRQ_NOCL0 561 +#define IRQ_LD_SLC_CH1_O_UASC_TZ_IRQ_NOCL0 562 +#define IRQ_LD_SLC_CH2_O_APC_NS_IRQ_NOCL0 563 +#define IRQ_LD_SLC_CH2_O_APC_S_IRQ_NOCL0 564 +#define IRQ_LD_SLC_CH2_O_PPMPU_IRQ_NOCL0 565 +#define IRQ_LD_SLC_CH2_O_UASC_GSA_IRQ_NOCL0 566 +#define IRQ_LD_SLC_CH2_O_UASC_NS_IRQ_NOCL0 567 +#define IRQ_LD_SLC_CH2_O_UASC_TZ_IRQ_NOCL0 568 +#define IRQ_LD_SLC_CH3_O_APC_NS_IRQ_NOCL0 569 +#define IRQ_LD_SLC_CH3_O_APC_S_IRQ_NOCL0 570 +#define IRQ_LD_SLC_CH3_O_PPMPU_IRQ_NOCL0 571 +#define IRQ_LD_SLC_CH3_O_UASC_GSA_IRQ_NOCL0 572 +#define IRQ_LD_SLC_CH3_O_UASC_NS_IRQ_NOCL0 573 +#define IRQ_LD_SLC_CH3_O_UASC_TZ_IRQ_NOCL0 574 +#define IRQ_NOCL0_PPC_CON_O_IUON_AND_PPC_CCI_EVENT_NOCL0 575 +#define IRQ_NOCL0_PPC_CON_O_IUON_AND_PPC_CPUCL0_EVENT_NOCL0 576 +#define IRQ_NOCL0_PPC_CON_O_IUON_AND_PPC_NOCL1A_EVENT_NOCL0 577 +#define IRQ_NOCL0_PPC_CON_O_IUON_OR_PPC_CCI_EVENT_NOCL0 578 +#define IRQ_NOCL0_PPC_CON_O_IUON_OR_PPC_CPUCL0_EVENT_NOCL0 579 +#define IRQ_NOCL0_PPC_CON_O_IUON_OR_PPC_NOCL1A_EVENT_NOCL0 580 +#define IRQ_PPC_CCI_M1_CYCLE_O_IUON_NOCL0 581 +#define IRQ_PPC_CPUCL0_D0_CYCLE_O_IUON_NOCL0 582 +#define IRQ_PPC_DEBUG_O_IL_NOCL0 583 +#define IRQ_PPC_DEBUG_O_IUON_NOCL0 584 +#define IRQ_PPC_EH_CYCLE_O_IUON_NOCL0 585 +#define IRQ_PPC_EH_EVENT_O_IUON_NOCL0 586 +#define IRQ_PPC_IO_CYCLE_O_IUON_NOCL0 587 +#define IRQ_PPC_IO_EVENT_O_IUON_NOCL0 588 +#define IRQ_PPC_NOCL1A_M0_CYCLE_O_IUON_NOCL0 589 +#define IRQ_PPC_NOCL1B_M0_CYCLE_O_IUON_NOCL0 590 +#define IRQ_PPC_NOCL1B_M0_EVENT_O_IUON_NOCL0 591 +#define IRQ_PPMU_ACE_CPUCL0_D0_O_IL_NOCL0 592 +#define IRQ_PPMU_ACE_CPUCL0_D0_O_IUON_NOCL0 593 +#define IRQ_PPMU_ACE_CPUCL0_D1_O_IL_NOCL0 594 +#define IRQ_PPMU_ACE_CPUCL0_D1_O_IUON_NOCL0 595 +#define IRQ_TREX_D_NOCL0_debugInterrupt_NOCL0 596 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_CCI_NOCL0 597 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_CPU0_NOCL0 598 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_CPU1_NOCL0 599 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_CPU2_NOCL0 600 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_CPU3_NOCL0 601 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_NOCL0_DP_NOCL0 602 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_NOCL0_M0_NOCL0 603 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_NOCL0_M1_NOCL0 604 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_NOCL0_M2_NOCL0 605 +#define IRQ_TREX_D_NOCL0_ppcInterrupt_NOCL0_M3_NOCL0 606 +#define IRQ_TREX_P_NOCL0_debugInterrupt_NOCL0 607 +#define IRQ_TREX_P_NOCL0_ppcInterrupt_CCI_NOCL0 608 +#define IRQ_TREX_P_NOCL0_ppcInterrupt_CSSYS_NOCL0 609 +#define IRQ_TREX_P_NOCL0_ppcInterrupt_NOCL0_DP_NOCL0 610 +#define IRQ_PPC_CYCLE_AUR_UON_NOCL1A 611 +#define IRQ_PPC_CYCLE_G3D_UON_NOCL1A 612 +#define IRQ_PPC_CYCLE_NOCL1A_UON_NOCL1A 613 +#define IRQ_PPC_EVENT_AUR_UON_AND_NOCL1A 614 +#define IRQ_PPC_EVENT_AUR_UON_OR_NOCL1A 615 +#define IRQ_PPC_EVENT_G3D_UON_AND_NOCL1A 616 +#define IRQ_PPC_EVENT_G3D_UON_OR_NOCL1A 617 +#define IRQ_PPC_EVENT_NOCL1A_UON_AND_NOCL1A 618 +#define IRQ_PPC_EVENT_NOCL1A_UON_OR_NOCL1A 619 +#define IRQ_PPC_TPU_CYCLE_UON_NOCL1A 620 +#define IRQ_PPC_TPU_EVENT_UON_NOCL1A 621 +#define IRQ_PPCFW_G3D_NOCL1A 622 +#define IRQ_SYSMMU_G3D_NONSECURE_NOCL1A 623 +#define IRQ_SYSMMU_G3D_SECURE_NOCL1A 624 +#define IRQ_TREX_D_NOCL1A_debugInterrupt_NOCL1A 625 +#define IRQ_TREX_P_NOCL1A_debugInterrupt_NOCL1A 626 +#define IRQ_TREX_PPMU_GPU0_NOCL1A 627 +#define IRQ_TREX_PPMU_GPU1_NOCL1A 628 +#define IRQ_TREX_PPMU_GPU2_NOCL1A 629 +#define IRQ_TREX_PPMU_GPU3_NOCL1A 630 +#define IRQ_TREX_PPMU_NOCL1AM0_NOCL1A 631 +#define IRQ_TREX_PPMU_NOCL1AM1_NOCL1A 632 +#define IRQ_TREX_PPMU_NOCL1AM2_NOCL1A 633 +#define IRQ_TREX_PPMU_NOCL1AM3_NOCL1A 634 +#define IRQ_PPC_AOC_CYCLE_UON_NOCL1B 635 +#define IRQ_PPC_AOC_EVENT_UON_NOCL1B 636 +#define IRQ_TREX_D_NOCL1B_debugInterrupt_NOCL1B 637 +#define IRQ_TREX_P_NOCL1B_debugInterrupt_NOCL1B 638 +#define IRQ_TREX_PPMU_NOCL1BM0_NOCL1B 639 +#define IRQ_TREX_D_NOCL2A_debugInterrupt_NOCL2A 640 +#define IRQ_TREX_P_NOCL2A_debugInterrupt_NOCL2A 641 +#define IRQ_TREX_PPMU_NOCL2AM0_NOCL2A 642 +#define IRQ_TREX_PPMU_NOCL2AM1_NOCL2A 643 +#define IRQ_TREX_PPMU_NOCL2AM2_NOCL2A 644 +#define IRQ_TREX_PPMU_NOCL2AM3_NOCL2A 645 +#define IRQ_PDP_MUTE0_PDP 646 +#define IRQ_PDP_MUTE1_PDP 647 +#define IRQ_PDP_MUTE2_PDP 648 +#define IRQ_PDP_TOP0_PDP 649 +#define IRQ_PDP_TOP1_PDP 650 +#define IRQ_PDP_TOP2_PDP 651 +#define IRQ_PDP_TOP3_PDP 652 +#define IRQ_PDP_TOP4_PDP 653 +#define IRQ_PDP_TOP5_PDP 654 +#define IRQ_PPMU_VRA_UPPER_OR_NORMAL_PDP 655 +#define IRQ_SECU_PDP0_PDP 656 +#define IRQ_SECU_PDP1_PDP 657 +#define IRQ_SECU_PDP2_PDP 658 +#define IRQ_SSMT_PDP_STAT_PDP 659 +#define IRQ_SSMT_VRA_PDP 660 +#define IRQ_VRA_PDP 661 +#define IRQ_VRA_NonSecu_Mute_IRQ_PDP 662 +#define IRQ_VRA_Secu_FROM_PDP_TO_GSA_PDP 663 +#define IRQ_GPIO_PERIC0_PERIC0 664 +#define IRQ_I3C1_PERIC0 665 +#define IRQ_I3C2_PERIC0 666 +#define IRQ_I3C3_PERIC0 667 +#define IRQ_I3C4_PERIC0 668 +#define IRQ_I3C5_PERIC0 669 +#define IRQ_I3C6_PERIC0 670 +#define IRQ_I3C7_PERIC0 671 +#define IRQ_I3C8_PERIC0 672 +#define IRQ_USI0_UART_PERIC0 673 +#define IRQ_USI1_USI_PERIC0 674 +#define IRQ_USI2_USI_PERIC0 675 +#define IRQ_USI3_USI_PERIC0 676 +#define IRQ_USI4_USI_PERIC0 677 +#define IRQ_USI5_USI_PERIC0 678 +#define IRQ_USI6_USI_PERIC0 679 +#define IRQ_USI7_USI_PERIC0 680 +#define IRQ_USI8_USI_PERIC0 681 +#define IRQ_USI14_USI_PERIC0 682 +#define IRQ_GPIO_PERIC1_PERIC1 683 +#define IRQ_I3C0_PERIC1 684 +#define IRQ_PWM0_PERIC1 685 +#define IRQ_PWM1_PERIC1 686 +#define IRQ_PWM2_PERIC1 687 +#define IRQ_PWM3_PERIC1 688 +#define IRQ_PWM4_PERIC1 689 +#define IRQ_USI0_USI_PERIC1 690 +#define IRQ_USI9_USI_PERIC1 691 +#define IRQ_USI10_USI_PERIC1 692 +#define IRQ_USI11_USI_PERIC1 693 +#define IRQ_USI12_USI_PERIC1 694 +#define IRQ_USI13_USI_PERIC1 695 +#define IRQ_USI15_USI_PERIC1 696 +#define IRQ_USI16_USI_PERIC1 697 +#define IRQ_PPMU_D0_TNR_UPPER_OR_NORMAL_TNR 698 +#define IRQ_PPMU_D1_TNR_UPPER_OR_NORMAL_TNR 699 +#define IRQ_PPMU_D2_TNR_UPPER_OR_NORMAL_TNR 700 +#define IRQ_PPMU_D3_TNR_UPPER_OR_NORMAL_TNR 701 +#define IRQ_PPMU_D4_TNR_UPPER_OR_NORMAL_TNR 702 +#define IRQ_PPMU_D5_TNR_UPPER_OR_NORMAL_TNR 703 +#define IRQ_PPMU_D6_TNR_UPPER_OR_NORMAL_TNR 704 +#define IRQ_PPMU_D7_TNR_UPPER_OR_NORMAL_TNR 705 +#define IRQ_PPMU_D8_TNR_UPPER_OR_NORMAL_TNR 706 +#define IRQ_SYSMMU_D0_TNR_S1_NS_TNR 707 +#define IRQ_SYSMMU_D0_TNR_S1_S_TNR 708 +#define IRQ_SYSMMU_D0_TNR_S2_TNR 709 +#define IRQ_SYSMMU_D1_TNR_S1_NS_TNR 710 +#define IRQ_SYSMMU_D1_TNR_S1_S_TNR 711 +#define IRQ_SYSMMU_D1_TNR_S2_TNR 712 +#define IRQ_SYSMMU_D2_TNR_S1_NS_TNR 713 +#define IRQ_SYSMMU_D2_TNR_S1_S_TNR 714 +#define IRQ_SYSMMU_D2_TNR_S2_TNR 715 +#define IRQ_SYSMMU_D3_TNR_S1_NS_TNR 716 +#define IRQ_SYSMMU_D3_TNR_S1_S_TNR 717 +#define IRQ_SYSMMU_D3_TNR_S2_TNR 718 +#define IRQ_SYSMMU_D4_TNR_S1_NS_TNR 719 +#define IRQ_SYSMMU_D4_TNR_S1_S_TNR 720 +#define IRQ_SYSMMU_D4_TNR_S2_TNR 721 +#define IRQ_TNR_0_TNR 722 +#define IRQ_TNR_1_TNR 723 +#define IRQ_TNR_MUTE_TNR 724 +#define IRQ_DDD_IRQ_0_TPU 725 +#define IRQ_DDD_IRQ_1_TPU 726 +#define IRQ_DDD_IRQ_2_TPU 727 +#define IRQ_DDD_IRQ_3_TPU 728 +#define IRQ_HPM_IRQ_TPU 729 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_0_TPU 730 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_1_TPU 731 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_2_TPU 732 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_3_TPU 733 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_4_TPU 734 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_5_TPU 735 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_6_TPU 736 +#define IRQ_MAILBOX_TPU2AP_NS_TPU_7_TPU 737 +#define IRQ_MAILBOX_TPU2AP_S_TPU_TPU 738 +#define IRQ_PPMU_UPPER_OR_NORMAL_TPU 739 +#define IRQ_SSMT_TPU_TPU 740 +#define IRQ_SYSMMU_S1_NS_TPU_TPU 741 +#define IRQ_SYSMMU_S1_S_TPU_TPU 742 +#define IRQ_SYSMMU_S2_TPU_TPU 743 +#define IRQ_OTP_CON_TOP_MISC 784 +#define IRQ_MCT_G0_MISC 785 +#define IRQ_MCT_G1_MISC 786 +#define IRQ_MCT_G2_MISC 787 +#define IRQ_MCT_G3_MISC 788 +#define IRQ_MCT_L0_MISC 789 +#define IRQ_MCT_L1_MISC 790 +#define IRQ_MCT_L2_MISC 791 +#define IRQ_MCT_L3_MISC 792 +#define IRQ_MCT_L4_MISC 793 +#define IRQ_MCT_L5_MISC 794 +#define IRQ_MCT_L6_MISC 795 +#define IRQ_MCT_L7_MISC 796 +#define IRQ_WDT_CLUSTER0_MISC 797 +#define IRQ_WDT_CLUSTER1_MISC 798 +#define IRQ_OTP_CON_BISR_MISC 799 +#define IRQ_OTP_CON_BIRA_MISC 800 +#define IRQ_TMU_TMU_TOP_MISC 801 +#define IRQ_TMU_TMU_SUB_MISC 802 +#define IRQ_SPDMA1_MISC 803 +#define IRQ_PDMA1_MISC 804 +#define IRQ_SPDMA0_MISC 805 +#define IRQ_PDMA0_MISC 806 +#define IRQ_SSS_AXI_ERR_RESP_DETECT_MISC 807 +#define IRQ_SSS_MISC 808 +#define IRQ_SSS_NS_MB_MISC 809 +#define IRQ_SSS_S_MB_MISC 810 +#define IRQ_SSS_KM_MISC 811 +#define IRQ_SSS_DMAINT_MISC 812 +#define IRQ_SSS_SWDT1_MISC 813 +#define IRQ_SSS_SWDT2_MISC 814 +#define IRQ_PUF_SEC_MISC 815 +#define IRQ_PUF_UNCOREECT_MISC 816 +#define IRQ_RTIC_MISC 817 +#define IRQ_DIT_TxDst2_MISC 818 +#define IRQ_DIT_TxDst1_MISC 819 +#define IRQ_DIT_TxDst0_MISC 820 +#define IRQ_DIT_TxSrc2_MISC 821 +#define IRQ_DIT_TxSrc1_MISC 822 +#define IRQ_DIT_TxSrc0_MISC 823 +#define IRQ_DIT_RxDst2_MISC 824 +#define IRQ_DIT_RxDst1_MISC 825 +#define IRQ_DIT_RxDst03_MISC 826 +#define IRQ_DIT_RxDst02_MISC 827 +#define IRQ_DIT_RxDst01_MISC 828 +#define IRQ_DIT_RxDst00_MISC 829 +#define IRQ_DIT_RxSrc2_MISC 830 +#define IRQ_DIT_RxSrc1_MISC 831 +#define IRQ_DIT_RxSrc0_MISC 832 +#define IRQ_PPMU_MISC_UPPER_OR_NORMAL_MISC 833 +#define IRQ_SYSMMU_NS_SSS_MISC 834 +#define IRQ_SYSMMU_S_SSS_MISC 835 +#define IRQ_SYSMMU_S2_MISC_MISC 836 +#define IRQ_GIC_FAULT_MISC 837 +#define IRQ_GIC_ERR_MISC 838 +#define IRQ_GIC_PMU_MISC 839 + +#endif/*_DT_BINDINGS_INTERRUPT_CONTROLLER_GS201_H*/ diff --git a/include/dt-bindings/lwis/platform/gs201/csi.h b/include/dt-bindings/lwis/platform/gs201/csi.h new file mode 100644 index 000000000000..b9027afa0b0d --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/csi.h @@ -0,0 +1,4333 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 CSI Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_CSI_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_CSI_H_ + +#include + +/* clang-format off */ + + +#define CSI_CSIS_INT0_CTX0_BASE (HW_EVENT_MASK + 0) + +#define CSI_CSIS_INT0_CTX0_ERR_ID 0 +#define CSI_CSIS_INT0_CTX0_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX0_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX0_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX0_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX0_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX0_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX1_BASE (HW_EVENT_MASK + 32) + +#define CSI_CSIS_INT0_CTX1_ERR_ID 0 +#define CSI_CSIS_INT0_CTX1_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX1_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX1_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX1_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX1_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX1_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX2_BASE (HW_EVENT_MASK + 64) + +#define CSI_CSIS_INT0_CTX2_ERR_ID 0 +#define CSI_CSIS_INT0_CTX2_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX2_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX2_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX2_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX2_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX2_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX3_BASE (HW_EVENT_MASK + 96) + +#define CSI_CSIS_INT0_CTX3_ERR_ID 0 +#define CSI_CSIS_INT0_CTX3_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX3_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX3_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX3_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX3_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX3_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX4_BASE (HW_EVENT_MASK + 128) + +#define CSI_CSIS_INT0_CTX4_ERR_ID 0 +#define CSI_CSIS_INT0_CTX4_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX4_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX4_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX4_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX4_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX4_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX5_BASE (HW_EVENT_MASK + 160) + +#define CSI_CSIS_INT0_CTX5_ERR_ID 0 +#define CSI_CSIS_INT0_CTX5_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX5_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX5_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX5_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX5_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX5_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX6_BASE (HW_EVENT_MASK + 192) + +#define CSI_CSIS_INT0_CTX6_ERR_ID 0 +#define CSI_CSIS_INT0_CTX6_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX6_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX6_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX6_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX6_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX6_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3 23 + +#define CSI_CSIS_INT0_CTX7_BASE (HW_EVENT_MASK + 224) + +#define CSI_CSIS_INT0_CTX7_ERR_ID 0 +#define CSI_CSIS_INT0_CTX7_ERR_CRC 1 +#define CSI_CSIS_INT0_CTX7_ERR_ECC 2 +#define CSI_CSIS_INT0_CTX7_ERR_WRONG_CONFIG 3 +#define CSI_CSIS_INT0_CTX7_ERR_OVER 4 +#define CSI_CSIS_INT0_CTX7_ERR_CRC_PH 5 +#define CSI_CSIS_INT0_CTX7_MAL_CRC 6 +#define CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0 12 +#define CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1 13 +#define CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2 14 +#define CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE3 15 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE0 16 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE1 17 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE2 18 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE3 19 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE0 20 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1 21 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2 22 +#define CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3 23 + + + +#define CSI_CSIS_INT1_CTX0_BASE (HW_EVENT_MASK + 256) + +#define CSI_CSIS_INT1_CTX0_LINE_END 0 +#define CSI_CSIS_INT1_CTX0_FRAME_END 1 +#define CSI_CSIS_INT1_CTX0_FRAME_START 2 +#define CSI_CSIS_INT1_CTX0_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX0_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX0_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX0_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX1_BASE (HW_EVENT_MASK + 288) + +#define CSI_CSIS_INT1_CTX1_LINE_END 0 +#define CSI_CSIS_INT1_CTX1_FRAME_END 1 +#define CSI_CSIS_INT1_CTX1_FRAME_START 2 +#define CSI_CSIS_INT1_CTX1_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX1_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX1_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX1_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX2_BASE (HW_EVENT_MASK + 320) + +#define CSI_CSIS_INT1_CTX2_LINE_END 0 +#define CSI_CSIS_INT1_CTX2_FRAME_END 1 +#define CSI_CSIS_INT1_CTX2_FRAME_START 2 +#define CSI_CSIS_INT1_CTX2_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX2_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX2_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX2_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX3_BASE (HW_EVENT_MASK + 352) + +#define CSI_CSIS_INT1_CTX3_LINE_END 0 +#define CSI_CSIS_INT1_CTX3_FRAME_END 1 +#define CSI_CSIS_INT1_CTX3_FRAME_START 2 +#define CSI_CSIS_INT1_CTX3_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX3_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX3_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX3_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX4_BASE (HW_EVENT_MASK + 384) + +#define CSI_CSIS_INT1_CTX4_LINE_END 0 +#define CSI_CSIS_INT1_CTX4_FRAME_END 1 +#define CSI_CSIS_INT1_CTX4_FRAME_START 2 +#define CSI_CSIS_INT1_CTX4_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX4_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX4_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX4_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX5_BASE (HW_EVENT_MASK + 416) + +#define CSI_CSIS_INT1_CTX5_LINE_END 0 +#define CSI_CSIS_INT1_CTX5_FRAME_END 1 +#define CSI_CSIS_INT1_CTX5_FRAME_START 2 +#define CSI_CSIS_INT1_CTX5_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX5_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX5_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX5_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX6_BASE (HW_EVENT_MASK + 448) + +#define CSI_CSIS_INT1_CTX6_LINE_END 0 +#define CSI_CSIS_INT1_CTX6_FRAME_END 1 +#define CSI_CSIS_INT1_CTX6_FRAME_START 2 +#define CSI_CSIS_INT1_CTX6_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX6_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX6_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX6_VRESOL_MISMATCH 6 + +#define CSI_CSIS_INT1_CTX7_BASE (HW_EVENT_MASK + 480) + +#define CSI_CSIS_INT1_CTX7_LINE_END 0 +#define CSI_CSIS_INT1_CTX7_FRAME_END 1 +#define CSI_CSIS_INT1_CTX7_FRAME_START 2 +#define CSI_CSIS_INT1_CTX7_ERR_LOST_FE 3 +#define CSI_CSIS_INT1_CTX7_ERR_LOST_FS 4 +#define CSI_CSIS_INT1_CTX7_HRESOL_MISMATCH 5 +#define CSI_CSIS_INT1_CTX7_VRESOL_MISMATCH 6 + + + +#define CSI_FS_INT_CTX0_BASE (HW_EVENT_MASK + 512) + +#define CSI_FS_INT_CTX0_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX0_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX0_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX0_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX0_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX0_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX0_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX0_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX0_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX0_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX0_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX0_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX0_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX0_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX0_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX0_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX0_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX0_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX0_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX0_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX0_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX0_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX0_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX0_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX0_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX0_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX0_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX0_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX0_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX0_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX0_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX0_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX1_BASE (HW_EVENT_MASK + 544) + +#define CSI_FS_INT_CTX1_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX1_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX1_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX1_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX1_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX1_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX1_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX1_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX1_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX1_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX1_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX1_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX1_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX1_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX1_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX1_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX1_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX1_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX1_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX1_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX1_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX1_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX1_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX1_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX1_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX1_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX1_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX1_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX1_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX1_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX1_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX1_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX2_BASE (HW_EVENT_MASK + 576) + +#define CSI_FS_INT_CTX2_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX2_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX2_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX2_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX2_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX2_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX2_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX2_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX2_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX2_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX2_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX2_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX2_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX2_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX2_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX2_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX2_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX2_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX2_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX2_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX2_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX2_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX2_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX2_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX2_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX2_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX2_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX2_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX2_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX2_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX2_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX2_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX3_BASE (HW_EVENT_MASK + 608) + +#define CSI_FS_INT_CTX3_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX3_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX3_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX3_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX3_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX3_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX3_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX3_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX3_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX3_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX3_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX3_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX3_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX3_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX3_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX3_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX3_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX3_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX3_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX3_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX3_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX3_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX3_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX3_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX3_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX3_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX3_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX3_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX3_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX3_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX3_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX3_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX4_BASE (HW_EVENT_MASK + 640) + +#define CSI_FS_INT_CTX4_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX4_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX4_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX4_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX4_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX4_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX4_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX4_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX4_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX4_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX4_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX4_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX4_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX4_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX4_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX4_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX4_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX4_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX4_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX4_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX4_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX4_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX4_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX4_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX4_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX4_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX4_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX4_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX4_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX4_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX4_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX4_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX5_BASE (HW_EVENT_MASK + 672) + +#define CSI_FS_INT_CTX5_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX5_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX5_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX5_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX5_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX5_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX5_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX5_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX5_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX5_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX5_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX5_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX5_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX5_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX5_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX5_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX5_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX5_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX5_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX5_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX5_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX5_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX5_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX5_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX5_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX5_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX5_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX5_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX5_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX5_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX5_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX5_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX6_BASE (HW_EVENT_MASK + 704) + +#define CSI_FS_INT_CTX6_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX6_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX6_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX6_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX6_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX6_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX6_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX6_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX6_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX6_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX6_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX6_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX6_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX6_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX6_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX6_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX6_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX6_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX6_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX6_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX6_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX6_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX6_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX6_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX6_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX6_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX6_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX6_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX6_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX6_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX6_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX6_FRAME_START_CH31 31 + +#define CSI_FS_INT_CTX7_BASE (HW_EVENT_MASK + 736) + +#define CSI_FS_INT_CTX7_FRAME_START_CH0 0 +#define CSI_FS_INT_CTX7_FRAME_START_CH1 1 +#define CSI_FS_INT_CTX7_FRAME_START_CH2 2 +#define CSI_FS_INT_CTX7_FRAME_START_CH3 3 +#define CSI_FS_INT_CTX7_FRAME_START_CH4 4 +#define CSI_FS_INT_CTX7_FRAME_START_CH5 5 +#define CSI_FS_INT_CTX7_FRAME_START_CH6 6 +#define CSI_FS_INT_CTX7_FRAME_START_CH7 7 +#define CSI_FS_INT_CTX7_FRAME_START_CH8 8 +#define CSI_FS_INT_CTX7_FRAME_START_CH9 9 +#define CSI_FS_INT_CTX7_FRAME_START_CH10 10 +#define CSI_FS_INT_CTX7_FRAME_START_CH11 11 +#define CSI_FS_INT_CTX7_FRAME_START_CH12 12 +#define CSI_FS_INT_CTX7_FRAME_START_CH13 13 +#define CSI_FS_INT_CTX7_FRAME_START_CH14 14 +#define CSI_FS_INT_CTX7_FRAME_START_CH15 15 +#define CSI_FS_INT_CTX7_FRAME_START_CH16 16 +#define CSI_FS_INT_CTX7_FRAME_START_CH17 17 +#define CSI_FS_INT_CTX7_FRAME_START_CH18 18 +#define CSI_FS_INT_CTX7_FRAME_START_CH19 19 +#define CSI_FS_INT_CTX7_FRAME_START_CH20 20 +#define CSI_FS_INT_CTX7_FRAME_START_CH21 21 +#define CSI_FS_INT_CTX7_FRAME_START_CH22 22 +#define CSI_FS_INT_CTX7_FRAME_START_CH23 23 +#define CSI_FS_INT_CTX7_FRAME_START_CH24 24 +#define CSI_FS_INT_CTX7_FRAME_START_CH25 25 +#define CSI_FS_INT_CTX7_FRAME_START_CH26 26 +#define CSI_FS_INT_CTX7_FRAME_START_CH27 27 +#define CSI_FS_INT_CTX7_FRAME_START_CH28 28 +#define CSI_FS_INT_CTX7_FRAME_START_CH29 29 +#define CSI_FS_INT_CTX7_FRAME_START_CH30 30 +#define CSI_FS_INT_CTX7_FRAME_START_CH31 31 + + + +#define CSI_FE_INT_CTX0_BASE (HW_EVENT_MASK + 768) + +#define CSI_FE_INT_CTX0_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX0_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX0_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX0_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX0_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX0_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX0_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX0_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX0_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX0_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX0_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX0_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX0_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX0_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX0_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX0_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX0_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX0_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX0_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX0_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX0_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX0_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX0_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX0_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX0_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX0_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX0_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX0_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX0_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX0_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX0_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX0_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX1_BASE (HW_EVENT_MASK + 800) + +#define CSI_FE_INT_CTX1_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX1_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX1_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX1_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX1_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX1_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX1_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX1_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX1_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX1_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX1_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX1_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX1_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX1_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX1_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX1_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX1_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX1_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX1_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX1_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX1_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX1_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX1_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX1_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX1_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX1_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX1_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX1_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX1_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX1_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX1_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX1_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX2_BASE (HW_EVENT_MASK + 832) + +#define CSI_FE_INT_CTX2_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX2_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX2_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX2_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX2_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX2_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX2_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX2_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX2_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX2_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX2_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX2_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX2_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX2_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX2_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX2_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX2_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX2_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX2_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX2_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX2_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX2_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX2_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX2_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX2_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX2_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX2_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX2_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX2_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX2_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX2_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX2_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX3_BASE (HW_EVENT_MASK + 864) + +#define CSI_FE_INT_CTX3_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX3_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX3_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX3_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX3_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX3_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX3_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX3_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX3_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX3_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX3_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX3_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX3_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX3_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX3_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX3_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX3_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX3_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX3_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX3_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX3_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX3_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX3_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX3_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX3_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX3_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX3_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX3_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX3_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX3_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX3_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX3_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX4_BASE (HW_EVENT_MASK + 896) + +#define CSI_FE_INT_CTX4_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX4_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX4_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX4_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX4_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX4_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX4_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX4_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX4_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX4_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX4_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX4_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX4_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX4_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX4_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX4_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX4_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX4_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX4_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX4_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX4_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX4_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX4_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX4_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX4_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX4_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX4_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX4_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX4_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX4_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX4_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX4_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX5_BASE (HW_EVENT_MASK + 928) + +#define CSI_FE_INT_CTX5_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX5_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX5_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX5_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX5_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX5_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX5_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX5_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX5_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX5_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX5_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX5_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX5_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX5_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX5_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX5_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX5_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX5_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX5_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX5_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX5_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX5_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX5_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX5_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX5_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX5_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX5_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX5_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX5_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX5_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX5_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX5_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX6_BASE (HW_EVENT_MASK + 960) + +#define CSI_FE_INT_CTX6_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX6_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX6_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX6_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX6_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX6_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX6_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX6_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX6_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX6_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX6_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX6_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX6_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX6_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX6_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX6_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX6_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX6_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX6_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX6_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX6_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX6_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX6_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX6_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX6_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX6_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX6_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX6_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX6_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX6_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX6_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX6_FRAME_END_CH31 31 + +#define CSI_FE_INT_CTX7_BASE (HW_EVENT_MASK + 992) + +#define CSI_FE_INT_CTX7_FRAME_END_CH0 0 +#define CSI_FE_INT_CTX7_FRAME_END_CH1 1 +#define CSI_FE_INT_CTX7_FRAME_END_CH2 2 +#define CSI_FE_INT_CTX7_FRAME_END_CH3 3 +#define CSI_FE_INT_CTX7_FRAME_END_CH4 4 +#define CSI_FE_INT_CTX7_FRAME_END_CH5 5 +#define CSI_FE_INT_CTX7_FRAME_END_CH6 6 +#define CSI_FE_INT_CTX7_FRAME_END_CH7 7 +#define CSI_FE_INT_CTX7_FRAME_END_CH8 8 +#define CSI_FE_INT_CTX7_FRAME_END_CH9 9 +#define CSI_FE_INT_CTX7_FRAME_END_CH10 10 +#define CSI_FE_INT_CTX7_FRAME_END_CH11 11 +#define CSI_FE_INT_CTX7_FRAME_END_CH12 12 +#define CSI_FE_INT_CTX7_FRAME_END_CH13 13 +#define CSI_FE_INT_CTX7_FRAME_END_CH14 14 +#define CSI_FE_INT_CTX7_FRAME_END_CH15 15 +#define CSI_FE_INT_CTX7_FRAME_END_CH16 16 +#define CSI_FE_INT_CTX7_FRAME_END_CH17 17 +#define CSI_FE_INT_CTX7_FRAME_END_CH18 18 +#define CSI_FE_INT_CTX7_FRAME_END_CH19 19 +#define CSI_FE_INT_CTX7_FRAME_END_CH20 20 +#define CSI_FE_INT_CTX7_FRAME_END_CH21 21 +#define CSI_FE_INT_CTX7_FRAME_END_CH22 22 +#define CSI_FE_INT_CTX7_FRAME_END_CH23 23 +#define CSI_FE_INT_CTX7_FRAME_END_CH24 24 +#define CSI_FE_INT_CTX7_FRAME_END_CH25 25 +#define CSI_FE_INT_CTX7_FRAME_END_CH26 26 +#define CSI_FE_INT_CTX7_FRAME_END_CH27 27 +#define CSI_FE_INT_CTX7_FRAME_END_CH28 28 +#define CSI_FE_INT_CTX7_FRAME_END_CH29 29 +#define CSI_FE_INT_CTX7_FRAME_END_CH30 30 +#define CSI_FE_INT_CTX7_FRAME_END_CH31 31 + + + + +#define CSI_ZSL_DMA_INT_CTX0_BASE (HW_EVENT_MASK + 1024) + +#define CSI_ZSL_DMA_INT_CTX0_LINE_END0 0 +#define CSI_ZSL_DMA_INT_CTX0_LINE_END1 1 +#define CSI_ZSL_DMA_INT_CTX0_LINE_END2 2 +#define CSI_ZSL_DMA_INT_CTX0_LINE_END3 3 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_START0 4 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_START1 5 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_START2 6 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_START3 7 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_END0 8 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_END1 9 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_END2 10 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_END3 11 +#define CSI_ZSL_DMA_INT_CTX0_FIFO_FULL 12 +#define CSI_ZSL_DMA_INT_CTX0_QREQN_P 13 +#define CSI_ZSL_DMA_INT_CTX0_LASTDATA_ERROR 14 +#define CSI_ZSL_DMA_INT_CTX0_LASTADDR_ERROR 15 +#define CSI_ZSL_DMA_INT_CTX0_ABORT_DONE 16 +#define CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0 17 +#define CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1 18 +#define CSI_ZSL_DMA_INT_CTX0_OVERLAP0 20 +#define CSI_ZSL_DMA_INT_CTX0_OVERLAP1 21 +#define CSI_ZSL_DMA_INT_CTX0_OVERLAP2 22 +#define CSI_ZSL_DMA_INT_CTX0_OVERLAP3 23 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_DROP0 24 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_DROP1 25 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_DROP2 26 +#define CSI_ZSL_DMA_INT_CTX0_FRAME_DROP3 27 +#define CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0 28 +#define CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1 29 +#define CSI_ZSL_DMA_INT_CTX0_C2COM_SLOW_RING 30 + +#define CSI_ZSL_DMA_INT_CTX1_BASE (HW_EVENT_MASK + 1056) + +#define CSI_ZSL_DMA_INT_CTX1_LINE_END0 0 +#define CSI_ZSL_DMA_INT_CTX1_LINE_END1 1 +#define CSI_ZSL_DMA_INT_CTX1_LINE_END2 2 +#define CSI_ZSL_DMA_INT_CTX1_LINE_END3 3 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_START0 4 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_START1 5 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_START2 6 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_START3 7 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_END0 8 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_END1 9 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_END2 10 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_END3 11 +#define CSI_ZSL_DMA_INT_CTX1_FIFO_FULL 12 +#define CSI_ZSL_DMA_INT_CTX1_QREQN_P 13 +#define CSI_ZSL_DMA_INT_CTX1_LASTDATA_ERROR 14 +#define CSI_ZSL_DMA_INT_CTX1_LASTADDR_ERROR 15 +#define CSI_ZSL_DMA_INT_CTX1_ABORT_DONE 16 +#define CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0 17 +#define CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1 18 +#define CSI_ZSL_DMA_INT_CTX1_OVERLAP0 20 +#define CSI_ZSL_DMA_INT_CTX1_OVERLAP1 21 +#define CSI_ZSL_DMA_INT_CTX1_OVERLAP2 22 +#define CSI_ZSL_DMA_INT_CTX1_OVERLAP3 23 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_DROP0 24 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_DROP1 25 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_DROP2 26 +#define CSI_ZSL_DMA_INT_CTX1_FRAME_DROP3 27 +#define CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0 28 +#define CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1 29 +#define CSI_ZSL_DMA_INT_CTX1_C2COM_SLOW_RING 30 + +#define CSI_ZSL_DMA_INT_CTX2_BASE (HW_EVENT_MASK + 1088) + +#define CSI_ZSL_DMA_INT_CTX2_LINE_END0 0 +#define CSI_ZSL_DMA_INT_CTX2_LINE_END1 1 +#define CSI_ZSL_DMA_INT_CTX2_LINE_END2 2 +#define CSI_ZSL_DMA_INT_CTX2_LINE_END3 3 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_START0 4 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_START1 5 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_START2 6 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_START3 7 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_END0 8 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_END1 9 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_END2 10 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_END3 11 +#define CSI_ZSL_DMA_INT_CTX2_FIFO_FULL 12 +#define CSI_ZSL_DMA_INT_CTX2_QREQN_P 13 +#define CSI_ZSL_DMA_INT_CTX2_LASTDATA_ERROR 14 +#define CSI_ZSL_DMA_INT_CTX2_LASTADDR_ERROR 15 +#define CSI_ZSL_DMA_INT_CTX2_ABORT_DONE 16 +#define CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0 17 +#define CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1 18 +#define CSI_ZSL_DMA_INT_CTX2_OVERLAP0 20 +#define CSI_ZSL_DMA_INT_CTX2_OVERLAP1 21 +#define CSI_ZSL_DMA_INT_CTX2_OVERLAP2 22 +#define CSI_ZSL_DMA_INT_CTX2_OVERLAP3 23 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_DROP0 24 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_DROP1 25 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_DROP2 26 +#define CSI_ZSL_DMA_INT_CTX2_FRAME_DROP3 27 +#define CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0 28 +#define CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1 29 +#define CSI_ZSL_DMA_INT_CTX2_C2COM_SLOW_RING 30 + + + + +#define CSI_STRP_DMA_INT_CTX0_BASE (HW_EVENT_MASK + 1120) + +#define CSI_STRP_DMA_INT_CTX0_LINE_END0 0 +#define CSI_STRP_DMA_INT_CTX0_LINE_END1 1 +#define CSI_STRP_DMA_INT_CTX0_LINE_END2 2 +#define CSI_STRP_DMA_INT_CTX0_LINE_END3 3 +#define CSI_STRP_DMA_INT_CTX0_FRAME_START0 4 +#define CSI_STRP_DMA_INT_CTX0_FRAME_START1 5 +#define CSI_STRP_DMA_INT_CTX0_FRAME_START2 6 +#define CSI_STRP_DMA_INT_CTX0_FRAME_START3 7 +#define CSI_STRP_DMA_INT_CTX0_FRAME_END0 8 +#define CSI_STRP_DMA_INT_CTX0_FRAME_END1 9 +#define CSI_STRP_DMA_INT_CTX0_FRAME_END2 10 +#define CSI_STRP_DMA_INT_CTX0_FRAME_END3 11 +#define CSI_STRP_DMA_INT_CTX0_FIFO_FULL 12 +#define CSI_STRP_DMA_INT_CTX0_QREQN_P 13 +#define CSI_STRP_DMA_INT_CTX0_LASTDATA_ERROR 14 +#define CSI_STRP_DMA_INT_CTX0_LASTADDR_ERROR 15 +#define CSI_STRP_DMA_INT_CTX0_ABORT_DONE 16 +#define CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0 17 +#define CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1 18 +#define CSI_STRP_DMA_INT_CTX0_OVERLAP0 20 +#define CSI_STRP_DMA_INT_CTX0_OVERLAP1 21 +#define CSI_STRP_DMA_INT_CTX0_OVERLAP2 22 +#define CSI_STRP_DMA_INT_CTX0_OVERLAP3 23 +#define CSI_STRP_DMA_INT_CTX0_FRAME_DROP0 24 +#define CSI_STRP_DMA_INT_CTX0_FRAME_DROP1 25 +#define CSI_STRP_DMA_INT_CTX0_FRAME_DROP2 26 +#define CSI_STRP_DMA_INT_CTX0_FRAME_DROP3 27 +#define CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0 28 +#define CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1 29 +#define CSI_STRP_DMA_INT_CTX0_C2COM_SLOW_RING 30 + +#define CSI_STRP_DMA_INT_CTX1_BASE (HW_EVENT_MASK + 1152) + +#define CSI_STRP_DMA_INT_CTX1_LINE_END0 0 +#define CSI_STRP_DMA_INT_CTX1_LINE_END1 1 +#define CSI_STRP_DMA_INT_CTX1_LINE_END2 2 +#define CSI_STRP_DMA_INT_CTX1_LINE_END3 3 +#define CSI_STRP_DMA_INT_CTX1_FRAME_START0 4 +#define CSI_STRP_DMA_INT_CTX1_FRAME_START1 5 +#define CSI_STRP_DMA_INT_CTX1_FRAME_START2 6 +#define CSI_STRP_DMA_INT_CTX1_FRAME_START3 7 +#define CSI_STRP_DMA_INT_CTX1_FRAME_END0 8 +#define CSI_STRP_DMA_INT_CTX1_FRAME_END1 9 +#define CSI_STRP_DMA_INT_CTX1_FRAME_END2 10 +#define CSI_STRP_DMA_INT_CTX1_FRAME_END3 11 +#define CSI_STRP_DMA_INT_CTX1_FIFO_FULL 12 +#define CSI_STRP_DMA_INT_CTX1_QREQN_P 13 +#define CSI_STRP_DMA_INT_CTX1_LASTDATA_ERROR 14 +#define CSI_STRP_DMA_INT_CTX1_LASTADDR_ERROR 15 +#define CSI_STRP_DMA_INT_CTX1_ABORT_DONE 16 +#define CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0 17 +#define CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1 18 +#define CSI_STRP_DMA_INT_CTX1_OVERLAP0 20 +#define CSI_STRP_DMA_INT_CTX1_OVERLAP1 21 +#define CSI_STRP_DMA_INT_CTX1_OVERLAP2 22 +#define CSI_STRP_DMA_INT_CTX1_OVERLAP3 23 +#define CSI_STRP_DMA_INT_CTX1_FRAME_DROP0 24 +#define CSI_STRP_DMA_INT_CTX1_FRAME_DROP1 25 +#define CSI_STRP_DMA_INT_CTX1_FRAME_DROP2 26 +#define CSI_STRP_DMA_INT_CTX1_FRAME_DROP3 27 +#define CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0 28 +#define CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1 29 +#define CSI_STRP_DMA_INT_CTX1_C2COM_SLOW_RING 30 + +#define CSI_STRP_DMA_INT_CTX2_BASE (HW_EVENT_MASK + 1184) + +#define CSI_STRP_DMA_INT_CTX2_LINE_END0 0 +#define CSI_STRP_DMA_INT_CTX2_LINE_END1 1 +#define CSI_STRP_DMA_INT_CTX2_LINE_END2 2 +#define CSI_STRP_DMA_INT_CTX2_LINE_END3 3 +#define CSI_STRP_DMA_INT_CTX2_FRAME_START0 4 +#define CSI_STRP_DMA_INT_CTX2_FRAME_START1 5 +#define CSI_STRP_DMA_INT_CTX2_FRAME_START2 6 +#define CSI_STRP_DMA_INT_CTX2_FRAME_START3 7 +#define CSI_STRP_DMA_INT_CTX2_FRAME_END0 8 +#define CSI_STRP_DMA_INT_CTX2_FRAME_END1 9 +#define CSI_STRP_DMA_INT_CTX2_FRAME_END2 10 +#define CSI_STRP_DMA_INT_CTX2_FRAME_END3 11 +#define CSI_STRP_DMA_INT_CTX2_FIFO_FULL 12 +#define CSI_STRP_DMA_INT_CTX2_QREQN_P 13 +#define CSI_STRP_DMA_INT_CTX2_LASTDATA_ERROR 14 +#define CSI_STRP_DMA_INT_CTX2_LASTADDR_ERROR 15 +#define CSI_STRP_DMA_INT_CTX2_ABORT_DONE 16 +#define CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0 17 +#define CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1 18 +#define CSI_STRP_DMA_INT_CTX2_OVERLAP0 20 +#define CSI_STRP_DMA_INT_CTX2_OVERLAP1 21 +#define CSI_STRP_DMA_INT_CTX2_OVERLAP2 22 +#define CSI_STRP_DMA_INT_CTX2_OVERLAP3 23 +#define CSI_STRP_DMA_INT_CTX2_FRAME_DROP0 24 +#define CSI_STRP_DMA_INT_CTX2_FRAME_DROP1 25 +#define CSI_STRP_DMA_INT_CTX2_FRAME_DROP2 26 +#define CSI_STRP_DMA_INT_CTX2_FRAME_DROP3 27 +#define CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0 28 +#define CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1 29 +#define CSI_STRP_DMA_INT_CTX2_C2COM_SLOW_RING 30 + + + + +#define CSI_CSIS_DMA_INT_CTX0_BASE (HW_EVENT_MASK + 1216) + +#define CSI_CSIS_DMA_INT_CTX0_LINE_END0 0 +#define CSI_CSIS_DMA_INT_CTX0_LINE_END1 1 +#define CSI_CSIS_DMA_INT_CTX0_LINE_END2 2 +#define CSI_CSIS_DMA_INT_CTX0_LINE_END3 3 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_START0 4 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_START1 5 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_START2 6 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_START3 7 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_END0 8 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_END1 9 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_END2 10 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_END3 11 +#define CSI_CSIS_DMA_INT_CTX0_FIFO_FULL 12 +#define CSI_CSIS_DMA_INT_CTX0_QREQN_P 13 +#define CSI_CSIS_DMA_INT_CTX0_LASTDATA_ERROR 14 +#define CSI_CSIS_DMA_INT_CTX0_LASTADDR_ERROR 15 +#define CSI_CSIS_DMA_INT_CTX0_ABORT_DONE 16 +#define CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0 17 +#define CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1 18 +#define CSI_CSIS_DMA_INT_CTX0_OVERLAP0 20 +#define CSI_CSIS_DMA_INT_CTX0_OVERLAP1 21 +#define CSI_CSIS_DMA_INT_CTX0_OVERLAP2 22 +#define CSI_CSIS_DMA_INT_CTX0_OVERLAP3 23 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_DROP0 24 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_DROP1 25 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_DROP2 26 +#define CSI_CSIS_DMA_INT_CTX0_FRAME_DROP3 27 +#define CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0 28 +#define CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1 29 +#define CSI_CSIS_DMA_INT_CTX0_C2COM_SLOW_RING 30 + +#define CSI_CSIS_DMA_INT_CTX1_BASE (HW_EVENT_MASK + 1248) + +#define CSI_CSIS_DMA_INT_CTX1_LINE_END0 0 +#define CSI_CSIS_DMA_INT_CTX1_LINE_END1 1 +#define CSI_CSIS_DMA_INT_CTX1_LINE_END2 2 +#define CSI_CSIS_DMA_INT_CTX1_LINE_END3 3 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_START0 4 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_START1 5 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_START2 6 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_START3 7 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_END0 8 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_END1 9 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_END2 10 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_END3 11 +#define CSI_CSIS_DMA_INT_CTX1_FIFO_FULL 12 +#define CSI_CSIS_DMA_INT_CTX1_QREQN_P 13 +#define CSI_CSIS_DMA_INT_CTX1_LASTDATA_ERROR 14 +#define CSI_CSIS_DMA_INT_CTX1_LASTADDR_ERROR 15 +#define CSI_CSIS_DMA_INT_CTX1_ABORT_DONE 16 +#define CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0 17 +#define CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1 18 +#define CSI_CSIS_DMA_INT_CTX1_OVERLAP0 20 +#define CSI_CSIS_DMA_INT_CTX1_OVERLAP1 21 +#define CSI_CSIS_DMA_INT_CTX1_OVERLAP2 22 +#define CSI_CSIS_DMA_INT_CTX1_OVERLAP3 23 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_DROP0 24 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_DROP1 25 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_DROP2 26 +#define CSI_CSIS_DMA_INT_CTX1_FRAME_DROP3 27 +#define CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0 28 +#define CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1 29 +#define CSI_CSIS_DMA_INT_CTX1_C2COM_SLOW_RING 30 + +#define CSI_CSIS_DMA_INT_CTX2_BASE (HW_EVENT_MASK + 1280) + +#define CSI_CSIS_DMA_INT_CTX2_LINE_END0 0 +#define CSI_CSIS_DMA_INT_CTX2_LINE_END1 1 +#define CSI_CSIS_DMA_INT_CTX2_LINE_END2 2 +#define CSI_CSIS_DMA_INT_CTX2_LINE_END3 3 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_START0 4 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_START1 5 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_START2 6 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_START3 7 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_END0 8 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_END1 9 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_END2 10 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_END3 11 +#define CSI_CSIS_DMA_INT_CTX2_FIFO_FULL 12 +#define CSI_CSIS_DMA_INT_CTX2_QREQN_P 13 +#define CSI_CSIS_DMA_INT_CTX2_LASTDATA_ERROR 14 +#define CSI_CSIS_DMA_INT_CTX2_LASTADDR_ERROR 15 +#define CSI_CSIS_DMA_INT_CTX2_ABORT_DONE 16 +#define CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0 17 +#define CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1 18 +#define CSI_CSIS_DMA_INT_CTX2_OVERLAP0 20 +#define CSI_CSIS_DMA_INT_CTX2_OVERLAP1 21 +#define CSI_CSIS_DMA_INT_CTX2_OVERLAP2 22 +#define CSI_CSIS_DMA_INT_CTX2_OVERLAP3 23 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_DROP0 24 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_DROP1 25 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_DROP2 26 +#define CSI_CSIS_DMA_INT_CTX2_FRAME_DROP3 27 +#define CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0 28 +#define CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1 29 +#define CSI_CSIS_DMA_INT_CTX2_C2COM_SLOW_RING 30 + +#define CSI_CSIS_DMA_INT_CTX3_BASE (HW_EVENT_MASK + 1312) + +#define CSI_CSIS_DMA_INT_CTX3_LINE_END0 0 +#define CSI_CSIS_DMA_INT_CTX3_LINE_END1 1 +#define CSI_CSIS_DMA_INT_CTX3_LINE_END2 2 +#define CSI_CSIS_DMA_INT_CTX3_LINE_END3 3 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_START0 4 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_START1 5 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_START2 6 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_START3 7 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_END0 8 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_END1 9 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_END2 10 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_END3 11 +#define CSI_CSIS_DMA_INT_CTX3_FIFO_FULL 12 +#define CSI_CSIS_DMA_INT_CTX3_QREQN_P 13 +#define CSI_CSIS_DMA_INT_CTX3_LASTDATA_ERROR 14 +#define CSI_CSIS_DMA_INT_CTX3_LASTADDR_ERROR 15 +#define CSI_CSIS_DMA_INT_CTX3_ABORT_DONE 16 +#define CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH0 17 +#define CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH1 18 +#define CSI_CSIS_DMA_INT_CTX3_OVERLAP0 20 +#define CSI_CSIS_DMA_INT_CTX3_OVERLAP1 21 +#define CSI_CSIS_DMA_INT_CTX3_OVERLAP2 22 +#define CSI_CSIS_DMA_INT_CTX3_OVERLAP3 23 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_DROP0 24 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_DROP1 25 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_DROP2 26 +#define CSI_CSIS_DMA_INT_CTX3_FRAME_DROP3 27 +#define CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH0 28 +#define CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH1 29 +#define CSI_CSIS_DMA_INT_CTX3_C2COM_SLOW_RING 30 + +#define CSI_EBUF_INT_BASE (HW_EVENT_MASK + 1344) + +#define CSI_EBUF_INT_EBUF0_FULL 0 +#define CSI_EBUF_INT_EBUF1_FULL 1 +#define CSI_EBUF_INT_EBUF2_FULL 2 +#define CSI_EBUF_INT_EBUF3_FULL 3 +#define CSI_EBUF_INT_EBUF0_FAKE_FRAME_DONE 4 +#define CSI_EBUF_INT_EBUF1_FAKE_FRAME_DONE 5 +#define CSI_EBUF_INT_EBUF2_FAKE_FRAME_DONE 6 +#define CSI_EBUF_INT_EBUF3_FAKE_FRAME_DONE 7 + +/* clang-format on */ + + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX0_BASE, \ + CSI_CSIS_INT0_CTX0_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX1_BASE, \ + CSI_CSIS_INT0_CTX1_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX2_BASE, \ + CSI_CSIS_INT0_CTX2_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX3_BASE, \ + CSI_CSIS_INT0_CTX3_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX4_BASE, \ + CSI_CSIS_INT0_CTX4_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX5_BASE, \ + CSI_CSIS_INT0_CTX5_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX6_BASE, \ + CSI_CSIS_INT0_CTX6_ERR_SOT_SYNC_HS_LANE3) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_ID \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_ID) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_ECC \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_ECC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_WRONG_CONFIG \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_WRONG_CONFIG) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_OVER \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_OVER) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_CRC_PH \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_CRC_PH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_MAL_CRC \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_MAL_CRC) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_RX_INVALID_CODE_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_RX_INVALID_CODE_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_HS_LANE3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE0 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE1 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE2 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_SOT_SYNC_HS_LANE3 \ + EVENT_ID(CSI_CSIS_INT0_CTX7_BASE, \ + CSI_CSIS_INT0_CTX7_ERR_SOT_SYNC_HS_LANE3) + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX0_BASE, \ + CSI_CSIS_INT1_CTX0_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX1_BASE, \ + CSI_CSIS_INT1_CTX1_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX2_BASE, \ + CSI_CSIS_INT1_CTX2_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX3_BASE, \ + CSI_CSIS_INT1_CTX3_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX4_BASE, \ + CSI_CSIS_INT1_CTX4_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX5_BASE, \ + CSI_CSIS_INT1_CTX5_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX6_BASE, \ + CSI_CSIS_INT1_CTX6_VRESOL_MISMATCH) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_LINE_END \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_LINE_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_LOST_FE \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_ERR_LOST_FE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_ERR_LOST_FS \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_ERR_LOST_FS) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_HRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_HRESOL_MISMATCH) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_VRESOL_MISMATCH \ + EVENT_ID(CSI_CSIS_INT1_CTX7_BASE, \ + CSI_CSIS_INT1_CTX7_VRESOL_MISMATCH) + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX0_BASE, \ + CSI_FS_INT_CTX0_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX1_BASE, \ + CSI_FS_INT_CTX1_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX2_BASE, \ + CSI_FS_INT_CTX2_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX3_BASE, \ + CSI_FS_INT_CTX3_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX4_BASE, \ + CSI_FS_INT_CTX4_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX5_BASE, \ + CSI_FS_INT_CTX5_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX6_BASE, \ + CSI_FS_INT_CTX6_FRAME_START_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH0 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH1 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH2 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH3 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH4 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH5 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH6 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH7 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH8 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH9 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH10 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH11 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH12 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH13 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH14 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH15 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH16 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH17 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH18 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH19 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH20 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH21 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH22 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH23 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH24 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH25 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH26 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH27 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH28 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH29 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH30 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_START_CH31 \ + EVENT_ID(CSI_FS_INT_CTX7_BASE, \ + CSI_FS_INT_CTX7_FRAME_START_CH31) + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX0_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX0_BASE, \ + CSI_FE_INT_CTX0_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX1_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX1_BASE, \ + CSI_FE_INT_CTX1_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX2_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX2_BASE, \ + CSI_FE_INT_CTX2_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX3_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX3_BASE, \ + CSI_FE_INT_CTX3_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX4_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX4_BASE, \ + CSI_FE_INT_CTX4_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX5_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX5_BASE, \ + CSI_FE_INT_CTX5_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX6_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX6_BASE, \ + CSI_FE_INT_CTX6_FRAME_END_CH31) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH0 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH1 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH2 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH3 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH4 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH4) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH5 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH5) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH6 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH6) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH7 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH7) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH8 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH8) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH9 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH9) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH10 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH10) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH11 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH11) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH12 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH12) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH13 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH13) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH14 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH14) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH15 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH15) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH16 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH16) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH17 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH17) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH18 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH18) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH19 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH19) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH20 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH20) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH21 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH21) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH22 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH22) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH23 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH23) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH24 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH24) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH25 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH25) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH26 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH26) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH27 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH27) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH28 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH28) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH29 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH29) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH30 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH30) +#define LWIS_PLATFORM_EVENT_ID_CSI_CTX7_FRAME_END_CH31 \ + EVENT_ID(CSI_FE_INT_CTX7_BASE, \ + CSI_FE_INT_CTX7_FRAME_END_CH31) + + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LINE_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_START3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FIFO_FULL \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_QREQN_P \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LASTDATA_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_LASTADDR_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_ABORT_DONE \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_OVERLAP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_FRAME_DROP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX0_C2COM_SLOW_RING \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX0_BASE, \ + CSI_ZSL_DMA_INT_CTX0_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LINE_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_START3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FIFO_FULL \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_QREQN_P \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LASTDATA_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_LASTADDR_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_ABORT_DONE \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_OVERLAP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_FRAME_DROP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX1_C2COM_SLOW_RING \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX1_BASE, \ + CSI_ZSL_DMA_INT_CTX1_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LINE_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_START3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_END3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FIFO_FULL \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_QREQN_P \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LASTDATA_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_LASTADDR_ERROR \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_ABORT_DONE \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_OVERLAP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP2 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_FRAME_DROP3 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_ZSL_DMA_CTX2_C2COM_SLOW_RING \ + EVENT_ID(CSI_ZSL_DMA_INT_CTX2_BASE, \ + CSI_ZSL_DMA_INT_CTX2_C2COM_SLOW_RING) + + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LINE_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_START3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FIFO_FULL \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_QREQN_P \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LASTDATA_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_LASTADDR_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_ABORT_DONE \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_OVERLAP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_FRAME_DROP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX0_C2COM_SLOW_RING \ + EVENT_ID(CSI_STRP_DMA_INT_CTX0_BASE, \ + CSI_STRP_DMA_INT_CTX0_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LINE_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_START3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FIFO_FULL \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_QREQN_P \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LASTDATA_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_LASTADDR_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_ABORT_DONE \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_OVERLAP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_FRAME_DROP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX1_C2COM_SLOW_RING \ + EVENT_ID(CSI_STRP_DMA_INT_CTX1_BASE, \ + CSI_STRP_DMA_INT_CTX1_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LINE_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_START3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_END3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FIFO_FULL \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_QREQN_P \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LASTDATA_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_LASTADDR_ERROR \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_ABORT_DONE \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_OVERLAP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP2 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_FRAME_DROP3 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_STRP_DMA_CTX2_C2COM_SLOW_RING \ + EVENT_ID(CSI_STRP_DMA_INT_CTX2_BASE, \ + CSI_STRP_DMA_INT_CTX2_C2COM_SLOW_RING) + + + + +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LINE_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_START3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FIFO_FULL \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_QREQN_P \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LASTDATA_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_LASTADDR_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_ABORT_DONE \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_OVERLAP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_FRAME_DROP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX0_C2COM_SLOW_RING \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX0_BASE, \ + CSI_CSIS_DMA_INT_CTX0_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LINE_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_START3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FIFO_FULL \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_QREQN_P \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LASTDATA_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_LASTADDR_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_ABORT_DONE \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_OVERLAP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_FRAME_DROP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX1_C2COM_SLOW_RING \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX1_BASE, \ + CSI_CSIS_DMA_INT_CTX1_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LINE_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_START3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FIFO_FULL \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_QREQN_P \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LASTDATA_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_LASTADDR_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_ABORT_DONE \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_OVERLAP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_FRAME_DROP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX2_C2COM_SLOW_RING \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX2_BASE, \ + CSI_CSIS_DMA_INT_CTX2_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LINE_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LINE_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LINE_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LINE_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LINE_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_START0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_START1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_START2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_START3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_START3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_END0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_END1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_END2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_END3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_END3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FIFO_FULL \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FIFO_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_QREQN_P \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_QREQN_P) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LASTDATA_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LASTDATA_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_LASTADDR_ERROR \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_LASTADDR_ERROR) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_ABORT_DONE \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_ABORT_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FSTART_IN_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FSTART_IN_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FSTART_IN_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_OVERLAP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_OVERLAP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_OVERLAP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_OVERLAP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_OVERLAP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_DROP0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_DROP1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP2 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_DROP2) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_FRAME_DROP3 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_FRAME_DROP3) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_LOST_FLUSH_CH0 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH0) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_LOST_FLUSH_CH1 \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_C2COM_LOST_FLUSH_CH1) +#define LWIS_PLATFORM_EVENT_ID_CSI_CSIS_DMA_CTX3_C2COM_SLOW_RING \ + EVENT_ID(CSI_CSIS_DMA_INT_CTX3_BASE, \ + CSI_CSIS_DMA_INT_CTX3_C2COM_SLOW_RING) + +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF0_FULL \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF0_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF1_FULL \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF1_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF2_FULL \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF2_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF3_FULL \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF3_FULL) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF0_FAKE_FRAME_DONE \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF0_FAKE_FRAME_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF1_FAKE_FRAME_DONE \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF1_FAKE_FRAME_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF2_FAKE_FRAME_DONE \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF2_FAKE_FRAME_DONE) +#define LWIS_PLATFORM_EVENT_ID_CSI_EBUF_EBUF3_FAKE_FRAME_DONE \ + EVENT_ID(CSI_EBUF_INT_BASE, \ + CSI_EBUF_INT_EBUF3_FAKE_FRAME_DONE) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_CSI_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/g3aa.h b/include/dt-bindings/lwis/platform/gs201/g3aa.h new file mode 100644 index 000000000000..0d8577666d19 --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/g3aa.h @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 G3AA Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_G3AA_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_G3AA_H_ + +#include + +/* clang-format off */ + + +#define G3AA_INTERRUPTS_CTX0_BASE (HW_EVENT_MASK + 0) + +#define G3AA_INTERRUPTS_CTX0_BAYER_START_OF_FRAME 0 +#define G3AA_INTERRUPTS_CTX0_BAYER_END_OF_FRAME 1 +#define G3AA_INTERRUPTS_CTX0_BAYER_CDAF_PRIMARY 2 +#define G3AA_INTERRUPTS_CTX0_BAYER_CDAF_WINDOWS 3 +#define G3AA_INTERRUPTS_CTX0_BAYER_AE_STATS 4 +#define G3AA_INTERRUPTS_CTX0_BAYER_AWB_STATS 5 +#define G3AA_INTERRUPTS_CTX0_BAYER_LSC_STATS 6 +#define G3AA_INTERRUPTS_CTX0_BAYER_FLICKER_STATS 7 +#define G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM0 8 +#define G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM1 9 +#define G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM2 10 +#define G3AA_INTERRUPTS_CTX0_BAYER_UAE_STATS 11 +#define G3AA_INTERRUPTS_CTX0_BAYER_MOTION_METERING 12 +#define G3AA_INTERRUPTS_CTX0_PDAF_START_OF_FRAME 13 +#define G3AA_INTERRUPTS_CTX0_PDAF_EARLY 14 +#define G3AA_INTERRUPTS_CTX0_PDAF_END_OF_FRAME 15 + +#define G3AA_INTERRUPTS_CTX1_BASE (HW_EVENT_MASK + 32) + +#define G3AA_INTERRUPTS_CTX1_BAYER_START_OF_FRAME 0 +#define G3AA_INTERRUPTS_CTX1_BAYER_END_OF_FRAME 1 +#define G3AA_INTERRUPTS_CTX1_BAYER_CDAF_PRIMARY 2 +#define G3AA_INTERRUPTS_CTX1_BAYER_CDAF_WINDOWS 3 +#define G3AA_INTERRUPTS_CTX1_BAYER_AE_STATS 4 +#define G3AA_INTERRUPTS_CTX1_BAYER_AWB_STATS 5 +#define G3AA_INTERRUPTS_CTX1_BAYER_LSC_STATS 6 +#define G3AA_INTERRUPTS_CTX1_BAYER_FLICKER_STATS 7 +#define G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM0 8 +#define G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM1 9 +#define G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM2 10 +#define G3AA_INTERRUPTS_CTX1_BAYER_UAE_STATS 11 +#define G3AA_INTERRUPTS_CTX1_BAYER_MOTION_METERING 12 +#define G3AA_INTERRUPTS_CTX1_PDAF_START_OF_FRAME 13 +#define G3AA_INTERRUPTS_CTX1_PDAF_EARLY 14 +#define G3AA_INTERRUPTS_CTX1_PDAF_END_OF_FRAME 15 + +#define G3AA_INTERRUPTS_CTX2_BASE (HW_EVENT_MASK + 64) + +#define G3AA_INTERRUPTS_CTX2_BAYER_START_OF_FRAME 0 +#define G3AA_INTERRUPTS_CTX2_BAYER_END_OF_FRAME 1 +#define G3AA_INTERRUPTS_CTX2_BAYER_CDAF_PRIMARY 2 +#define G3AA_INTERRUPTS_CTX2_BAYER_CDAF_WINDOWS 3 +#define G3AA_INTERRUPTS_CTX2_BAYER_AE_STATS 4 +#define G3AA_INTERRUPTS_CTX2_BAYER_AWB_STATS 5 +#define G3AA_INTERRUPTS_CTX2_BAYER_LSC_STATS 6 +#define G3AA_INTERRUPTS_CTX2_BAYER_FLICKER_STATS 7 +#define G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM0 8 +#define G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM1 9 +#define G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM2 10 +#define G3AA_INTERRUPTS_CTX2_BAYER_UAE_STATS 11 +#define G3AA_INTERRUPTS_CTX2_BAYER_MOTION_METERING 12 +#define G3AA_INTERRUPTS_CTX2_PDAF_START_OF_FRAME 13 +#define G3AA_INTERRUPTS_CTX2_PDAF_EARLY 14 +#define G3AA_INTERRUPTS_CTX2_PDAF_END_OF_FRAME 15 + +#define G3AA_ERROR_INTERRUPTS_BASE (HW_EVENT_MASK + 96) + +#define G3AA_ERROR_INTERRUPTS_HW_TIMEOUT 0 +#define G3AA_ERROR_INTERRUPTS_BUS_ERROR 1 +#define G3AA_ERROR_INTERRUPTS_AXI_READ_DATA_OVERFLOW 2 +#define G3AA_ERROR_INTERRUPTS_AXI_WRITE_DATA_OVERFLOW 3 + +/* clang-format on */ + + +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_END_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_CDAF_PRIMARY \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_CDAF_PRIMARY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_CDAF_WINDOWS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_CDAF_WINDOWS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_AE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_AE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_AWB_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_AWB_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_LSC_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_LSC_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_FLICKER_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_FLICKER_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM0 \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM0) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM1 \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM1) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_HISTOGRAM2 \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_HISTOGRAM2) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_UAE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_UAE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_BAYER_MOTION_METERING \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_BAYER_MOTION_METERING) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_PDAF_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_EARLY \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_PDAF_EARLY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX0_PDAF_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX0_BASE, \ + G3AA_INTERRUPTS_CTX0_PDAF_END_OF_FRAME) + +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_END_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_CDAF_PRIMARY \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_CDAF_PRIMARY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_CDAF_WINDOWS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_CDAF_WINDOWS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_AE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_AE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_AWB_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_AWB_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_LSC_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_LSC_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_FLICKER_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_FLICKER_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM0 \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM0) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM1 \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM1) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_HISTOGRAM2 \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_HISTOGRAM2) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_UAE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_UAE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_BAYER_MOTION_METERING \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_BAYER_MOTION_METERING) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_PDAF_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_EARLY \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_PDAF_EARLY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX1_PDAF_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX1_BASE, \ + G3AA_INTERRUPTS_CTX1_PDAF_END_OF_FRAME) + +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_END_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_CDAF_PRIMARY \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_CDAF_PRIMARY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_CDAF_WINDOWS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_CDAF_WINDOWS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_AE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_AE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_AWB_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_AWB_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_LSC_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_LSC_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_FLICKER_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_FLICKER_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM0 \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM0) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM1 \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM1) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_HISTOGRAM2 \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_HISTOGRAM2) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_UAE_STATS \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_UAE_STATS) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_BAYER_MOTION_METERING \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_BAYER_MOTION_METERING) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_START_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_PDAF_START_OF_FRAME) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_EARLY \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_PDAF_EARLY) +#define LWIS_PLATFORM_EVENT_ID_G3AA_CTX2_PDAF_END_OF_FRAME \ + EVENT_ID(G3AA_INTERRUPTS_CTX2_BASE, \ + G3AA_INTERRUPTS_CTX2_PDAF_END_OF_FRAME) + + +#define LWIS_PLATFORM_EVENT_ID_G3AA_HW_TIMEOUT \ + EVENT_ID(G3AA_ERROR_INTERRUPTS_BASE, \ + G3AA_ERROR_INTERRUPTS_HW_TIMEOUT) +#define LWIS_PLATFORM_EVENT_ID_G3AA_BUS_ERROR \ + EVENT_ID(G3AA_ERROR_INTERRUPTS_BASE, \ + G3AA_ERROR_INTERRUPTS_BUS_ERROR) +#define LWIS_PLATFORM_EVENT_ID_G3AA_AXI_READ_DATA_OVERFLOW \ + EVENT_ID(G3AA_ERROR_INTERRUPTS_BASE, \ + G3AA_ERROR_INTERRUPTS_AXI_READ_DATA_OVERFLOW) +#define LWIS_PLATFORM_EVENT_ID_G3AA_AXI_WRITE_DATA_OVERFLOW \ + EVENT_ID(G3AA_ERROR_INTERRUPTS_BASE, \ + G3AA_ERROR_INTERRUPTS_AXI_WRITE_DATA_OVERFLOW) +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_G3AA_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/gdc.h b/include/dt-bindings/lwis/platform/gs201/gdc.h new file mode 100644 index 000000000000..e08bdba3b1c8 --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/gdc.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 GDC Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_GDC_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_GDC_H_ + +#include + +/* clang-format off */ + +#define GDC_INT0_BASE (HW_EVENT_MASK + 0) + +#define GDC_INT0_FRAME_START 0 +#define GDC_INT0_FRAME_END 1 +#define GDC_INT0_CMDQ_HOLD 2 +#define GDC_INT0_SETTING_DONE 3 +#define GDC_INT0_C_LOADER_END 4 +#define GDC_INT0_COREX_END0 5 +#define GDC_INT0_COREX_END1 6 +#define GDC_INT0_ROW_COL 7 +#define GDC_INT0_FREEZE_ON_ROW_COL 8 +#define GDC_INT0_TRANS_STOP_DONE 9 +#define GDC_INT0_CMDQ_ERROR 10 +#define GDC_INT0_C_LOADER_ERROR 11 +#define GDC_INT0_COREX_ERROR 12 +#define GDC_INT0_CINFIFO0_OVERFLOW_ERROR 13 +#define GDC_INT0_CINFIFO0_OVERLAP_ERROR 14 +#define GDC_INT0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define GDC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define GDC_INT0_CINFIFO1_OVERFLOW_ERROR 17 +#define GDC_INT0_CINFIFO1_OVERLAP_ERROR 18 +#define GDC_INT0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define GDC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define GDC_INT0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define GDC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define GDC_INT0_COUTFIFO0_OVERFLOW_ERROR 23 +#define GDC_INT0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define GDC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define GDC_INT0_COUTFIFO1_OVERFLOW_ERROR 26 +#define GDC_INT0_VOTF_GLOBAL_ERROR 27 +#define GDC_INT0_VOTF_LOST_CONNECTION 28 +#define GDC_INT0_OTF_SEQ_ID_ERROR 29 + +#define GDC_INT1_BASE (HW_EVENT_MASK + 32) + +#define GDC_INT1_VOTF_LOST_FLUSH 0 +#define GDC_INT1_COMP_ERR 1 + +#define GDC_CMDQ_INT_BASE (HW_EVENT_MASK + 64) + +#define GDC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN 0 +#define GDC_CMDQ_INT_PRELOAD_FLUSH 1 +#define GDC_CMDQ_INT_QUE0_OVERFLOW 2 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_GDC_FRAME_START \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_GDC_FRAME_END \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_GDC_CMDQ_HOLD \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_GDC_SETTING_DONE \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_GDC_C_LOADER_END \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_GDC_COREX_END0 \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_GDC_COREX_END1 \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_GDC_ROW_COL \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_GDC_FREEZE_ON_ROW_COL \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_GDC_TRANS_STOP_DONE \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_GDC_CMDQ_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_C_LOADER_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COREX_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_VOTF_GLOBAL_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_VOTF_GLOBAL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GDC_VOTF_LOST_CONNECTION \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_GDC_OTF_SEQ_ID_ERROR \ + EVENT_ID(GDC_INT0_BASE, \ + GDC_INT0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_GDC_VOTF_LOST_FLUSH \ + EVENT_ID(GDC_INT1_BASE, \ + GDC_INT1_VOTF_LOST_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_GDC_COMP_ERR \ + EVENT_ID(GDC_INT1_BASE, \ + GDC_INT1_COMP_ERR) + +#define LWIS_PLATFORM_EVENT_ID_GDC_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(GDC_CMDQ_INT_BASE, \ + GDC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_GDC_PRELOAD_FLUSH \ + EVENT_ID(GDC_CMDQ_INT_BASE, \ + GDC_CMDQ_INT_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_GDC_QUE0_OVERFLOW \ + EVENT_ID(GDC_CMDQ_INT_BASE, \ + GDC_CMDQ_INT_QUE0_OVERFLOW) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_GDC_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/gtnr_align.h b/include/dt-bindings/lwis/platform/gs201/gtnr_align.h new file mode 100644 index 000000000000..49b176497276 --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/gtnr_align.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 GTNR_ALIGN Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_ALIGN_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_ALIGN_H_ + +#include + +/* clang-format off */ +#define GTNR_ALIGN_INT_BASE (HW_EVENT_MASK + 0) + +#define GTNR_ALIGN_INT_MSA_FRAME_DONE 0 +#define GTNR_ALIGN_INT_NM_FRAME_DONE 1 +#define GTNR_ALIGN_INT_FRO_DONE 2 + +#define GTNR_ALIGN_SECU_INT_MUTE_BASE (HW_EVENT_MASK + 32) + +#define GTNR_ALIGN_SECU_INT_MUTE_MUTE 0 +#define GTNR_ALIGN_SECU_INT_MUTE_UNMUTE 1 + +#define GTNR_ALIGN_SECU_INT_SECU_FLG_BASE (HW_EVENT_MASK + 64) + +#define GTNR_ALIGN_SECU_INT_SECU_FLG_SECURITY_FILTER_VIOLATION_WDMA 0 +#define GTNR_ALIGN_SECU_INT_SECU_FLG_SECURITY_FILTER_VIOLATION_RDMA 1 + + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_MSA_FRAME_DONE \ + EVENT_ID(GTNR_ALIGN_INT_BASE, \ + GTNR_ALIGN_INT_MSA_FRAME_DONE) +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_NM_FRAME_DONE \ + EVENT_ID(GTNR_ALIGN_INT_BASE, \ + GTNR_ALIGN_INT_NM_FRAME_DONE) +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_FRO_DONE \ + EVENT_ID(GTNR_ALIGN_INT_BASE, \ + GTNR_ALIGN_INT_FRO_DONE) + +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_MUTE \ + EVENT_ID(GTNR_ALIGN_SECU_INT_MUTE_BASE, \ + GTNR_ALIGN_SECU_INT_MUTE_MUTE) +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_UNMUTE \ + EVENT_ID(GTNR_ALIGN_SECU_INT_MUTE_BASE, \ + GTNR_ALIGN_SECU_INT_MUTE_UNMUTE) + +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_SECURITY_FILTER_VIOLATION_WDMA \ + EVENT_ID(GTNR_ALIGN_SECU_INT_SECU_FLG_BASE, \ + GTNR_ALIGN_SECU_INT_SECU_FLG_SECURITY_FILTER_VIOLATION_WDMA) +#define LWIS_PLATFORM_EVENT_ID_GTNR_ALIGN_SECURITY_FILTER_VIOLATION_RDMA \ + EVENT_ID(GTNR_ALIGN_SECU_INT_SECU_FLG_BASE, \ + GTNR_ALIGN_SECU_INT_SECU_FLG_SECURITY_FILTER_VIOLATION_RDMA) + + + + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_ALIGN_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/gtnr_merge.h b/include/dt-bindings/lwis/platform/gs201/gtnr_merge.h new file mode 100644 index 000000000000..94041bc630d9 --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/gtnr_merge.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 GTNR_MERGE Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_MERGE_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_MERGE_H_ + +#include + +/* clang-format off */ +#define GTNR_MERGE_INT0_BASE (HW_EVENT_MASK + 0) + +#define GTNR_MERGE_INT0_FRAME_START 0 +#define GTNR_MERGE_INT0_FRAME_END 1 +#define GTNR_MERGE_INT0_CMDQ_HOLD 2 +#define GTNR_MERGE_INT0_SETTING_DONE 3 +#define GTNR_MERGE_INT0_C_LOADER_END_INT 4 +#define GTNR_MERGE_INT0_COREX_END0 5 +#define GTNR_MERGE_INT0_COREX_END1 6 +#define GTNR_MERGE_INT0_ROW_COL 7 +#define GTNR_MERGE_INT0_FREEZE_ON_ROW_COL 8 +#define GTNR_MERGE_INT0_TRANS_STOP_DONE 9 +#define GTNR_MERGE_INT0_CMDQ_ERROR 10 +#define GTNR_MERGE_INT0_C_CLOADER_ERROR 11 +#define GTNR_MERGE_INT0_COREX_ERROR 12 +#define GTNR_MERGE_INT0_CINFIFO0_OVERFLOW_ERROR 13 +#define GTNR_MERGE_INT0_CINFIFO0_OVERLAP_ERROR 14 +#define GTNR_MERGE_INT0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define GTNR_MERGE_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define GTNR_MERGE_INT0_CINFIFO1_OVERFLOW_ERROR 17 +#define GTNR_MERGE_INT0_CINFIFO1_OVERLAP_ERROR 18 +#define GTNR_MERGE_INT0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define GTNR_MERGE_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define GTNR_MERGE_INT0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define GTNR_MERGE_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define GTNR_MERGE_INT0_COUTFIFO0_OVERFLOW_ERROR 23 +#define GTNR_MERGE_INT0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define GTNR_MERGE_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define GTNR_MERGE_INT0_COUTFIFO1_OVERFLOW_ERROR 26 +#define GTNR_MERGE_INT0_VOTF_SLOW_RING 27 +#define GTNR_MERGE_INT0_VOTF_LOST_CONNECTION 28 +#define GTNR_MERGE_INT0_OTF_SEQ_ID_ERROR 29 + +#define GTNR_MERGE_INT1_BASE (HW_EVENT_MASK + 32) + +#define GTNR_MERGE_INT1_VOTF_LOST_FLUSH 0 +#define GTNR_MERGE_INT1_SBWC_ERR_CUR0 1 +#define GTNR_MERGE_INT1_SBWC_ERR_CUR1 2 +#define GTNR_MERGE_INT1_SBWC_ERR_PRE0 3 +#define GTNR_MERGE_INT1_SBWC_ERR_PRE1 4 + +#define GTNR_MERGE_CMDQ_INT_BASE (HW_EVENT_MASK + 64) + +#define GTNR_MERGE_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN 0 +#define GTNR_MERGE_CMDQ_INT_PRELOAD_FLUSH 1 +#define GTNR_MERGE_CMDQ_INT_QUE0_OVERFLOW 2 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FRAME_START \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FRAME_END \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CMDQ_HOLD \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SETTING_DONE \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_C_LOADER_END_INT \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_C_LOADER_END_INT) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_END0 \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_END1 \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_ROW_COL \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_FREEZE_ON_ROW_COL \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_TRANS_STOP_DONE \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CMDQ_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_C_CLOADER_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_C_CLOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COREX_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_SLOW_RING \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_VOTF_SLOW_RING) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_LOST_CONNECTION \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_OTF_SEQ_ID_ERROR \ + EVENT_ID(GTNR_MERGE_INT0_BASE, \ + GTNR_MERGE_INT0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_VOTF_LOST_FLUSH \ + EVENT_ID(GTNR_MERGE_INT1_BASE, \ + GTNR_MERGE_INT1_VOTF_LOST_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_CUR0 \ + EVENT_ID(GTNR_MERGE_INT1_BASE, \ + GTNR_MERGE_INT1_SBWC_ERR_CUR0) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_CUR1 \ + EVENT_ID(GTNR_MERGE_INT1_BASE, \ + GTNR_MERGE_INT1_SBWC_ERR_CUR1) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_PRE0 \ + EVENT_ID(GTNR_MERGE_INT1_BASE, \ + GTNR_MERGE_INT1_SBWC_ERR_PRE0) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_SBWC_ERR_PRE1 \ + EVENT_ID(GTNR_MERGE_INT1_BASE, \ + GTNR_MERGE_INT1_SBWC_ERR_PRE1) + +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(GTNR_MERGE_CMDQ_INT_BASE, \ + GTNR_MERGE_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_PRELOAD_FLUSH \ + EVENT_ID(GTNR_MERGE_CMDQ_INT_BASE, \ + GTNR_MERGE_CMDQ_INT_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_GTNR_MERGE_QUE0_OVERFLOW \ + EVENT_ID(GTNR_MERGE_CMDQ_INT_BASE, \ + GTNR_MERGE_CMDQ_INT_QUE0_OVERFLOW) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_GTNR_MERGE_H_ */ \ No newline at end of file diff --git a/include/dt-bindings/lwis/platform/gs201/ipp.h b/include/dt-bindings/lwis/platform/gs201/ipp.h new file mode 100644 index 000000000000..98b5cb3da26f --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/ipp.h @@ -0,0 +1,775 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 IPP Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_IPP_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_IPP_H_ + +#include + +/* clang-format off */ + + +#define IPP_INT1_CTX0_BASE (HW_EVENT_MASK + 0) + +#define IPP_INT1_CTX0_FRAME_START 0 +#define IPP_INT1_CTX0_FRAME_END_INTERRUPT 1 +#define IPP_INT1_CTX0_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_INT1_CTX0_IRQ_CORRUPTED 3 +#define IPP_INT1_CTX0_COREX_ERROR_INT 4 +#define IPP_INT1_CTX0_P_SLVERR 5 +#define IPP_INT1_CTX0_PRE_FRAME_END_INTERRUPT 6 +#define IPP_INT1_CTX0_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_INT1_CTX0_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_INT1_CTX0_STRP_OUT_DMA_IN_LAST 9 +#define IPP_INT1_CTX0_BDS_DATA_OUT_LAST 10 +#define IPP_INT1_CTX0_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_INT1_CTX0_BCROP1_DATA_IN_LAST 12 +#define IPP_INT1_CTX0_BCROP0_DATA_IN_LAST 13 +#define IPP_INT1_CTX0_RGBY_HIST2_DMA_DONE 14 +#define IPP_INT1_CTX0_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_INT1_CTX0_THSTAT_DATA_IN_LAST 16 +#define IPP_INT1_CTX0_GP_DATA_IN_LAST 17 +#define IPP_INT1_CTX0_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_INT1_CTX0_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_INT1_CTX0_COREX_END_INT0 20 +#define IPP_INT1_CTX0_COREX_END_INT1 21 +#define IPP_INT1_CTX0_COUTFIFO_SIZE_ERROR 22 +#define IPP_INT1_CTX0_COUTFIFO_LINE_ERROR 23 +#define IPP_INT1_CTX0_COUTFIFO_COL_ERROR 24 +#define IPP_INT1_CTX0_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_INT1_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_INT1_CTX0_CINFIFO_LINES_ERROR_INT 27 +#define IPP_INT1_CTX0_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_INT1_CTX0_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_INT1_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + +#define IPP_INT1_CTX1_BASE (HW_EVENT_MASK + 32) + +#define IPP_INT1_CTX1_FRAME_START 0 +#define IPP_INT1_CTX1_FRAME_END_INTERRUPT 1 +#define IPP_INT1_CTX1_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_INT1_CTX1_IRQ_CORRUPTED 3 +#define IPP_INT1_CTX1_COREX_ERROR_INT 4 +#define IPP_INT1_CTX1_P_SLVERR 5 +#define IPP_INT1_CTX1_PRE_FRAME_END_INTERRUPT 6 +#define IPP_INT1_CTX1_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_INT1_CTX1_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_INT1_CTX1_STRP_OUT_DMA_IN_LAST 9 +#define IPP_INT1_CTX1_BDS_DATA_OUT_LAST 10 +#define IPP_INT1_CTX1_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_INT1_CTX1_BCROP1_DATA_IN_LAST 12 +#define IPP_INT1_CTX1_BCROP0_DATA_IN_LAST 13 +#define IPP_INT1_CTX1_RGBY_HIST2_DMA_DONE 14 +#define IPP_INT1_CTX1_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_INT1_CTX1_THSTAT_DATA_IN_LAST 16 +#define IPP_INT1_CTX1_GP_DATA_IN_LAST 17 +#define IPP_INT1_CTX1_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_INT1_CTX1_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_INT1_CTX1_COREX_END_INT0 20 +#define IPP_INT1_CTX1_COREX_END_INT1 21 +#define IPP_INT1_CTX1_COUTFIFO_SIZE_ERROR 22 +#define IPP_INT1_CTX1_COUTFIFO_LINE_ERROR 23 +#define IPP_INT1_CTX1_COUTFIFO_COL_ERROR 24 +#define IPP_INT1_CTX1_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_INT1_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_INT1_CTX1_CINFIFO_LINES_ERROR_INT 27 +#define IPP_INT1_CTX1_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_INT1_CTX1_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_INT1_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + +#define IPP_INT1_CTX2_BASE (HW_EVENT_MASK + 64) + +#define IPP_INT1_CTX2_FRAME_START 0 +#define IPP_INT1_CTX2_FRAME_END_INTERRUPT 1 +#define IPP_INT1_CTX2_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_INT1_CTX2_IRQ_CORRUPTED 3 +#define IPP_INT1_CTX2_COREX_ERROR_INT 4 +#define IPP_INT1_CTX2_P_SLVERR 5 +#define IPP_INT1_CTX2_PRE_FRAME_END_INTERRUPT 6 +#define IPP_INT1_CTX2_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_INT1_CTX2_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_INT1_CTX2_STRP_OUT_DMA_IN_LAST 9 +#define IPP_INT1_CTX2_BDS_DATA_OUT_LAST 10 +#define IPP_INT1_CTX2_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_INT1_CTX2_BCROP1_DATA_IN_LAST 12 +#define IPP_INT1_CTX2_BCROP0_DATA_IN_LAST 13 +#define IPP_INT1_CTX2_RGBY_HIST2_DMA_DONE 14 +#define IPP_INT1_CTX2_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_INT1_CTX2_THSTAT_DATA_IN_LAST 16 +#define IPP_INT1_CTX2_GP_DATA_IN_LAST 17 +#define IPP_INT1_CTX2_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_INT1_CTX2_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_INT1_CTX2_COREX_END_INT0 20 +#define IPP_INT1_CTX2_COREX_END_INT1 21 +#define IPP_INT1_CTX2_COUTFIFO_SIZE_ERROR 22 +#define IPP_INT1_CTX2_COUTFIFO_LINE_ERROR 23 +#define IPP_INT1_CTX2_COUTFIFO_COL_ERROR 24 +#define IPP_INT1_CTX2_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_INT1_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_INT1_CTX2_CINFIFO_LINES_ERROR_INT 27 +#define IPP_INT1_CTX2_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_INT1_CTX2_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_INT1_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + + + +#define IPP_INT2_CTX0_BASE (HW_EVENT_MASK + 96) + +#define IPP_INT2_CTX0_CDAF_INT 0 +#define IPP_INT2_CTX0_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_INT2_CTX0_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_INT2_CTX0_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_INT2_CTX0_THSTAT_STATISTICS_DONE 4 +#define IPP_INT2_CTX0_FRO_GROUP2 5 +#define IPP_INT2_CTX0_FRO_GROUP4 6 +#define IPP_INT2_CTX0_FRO_GROUP5 7 + +#define IPP_INT2_CTX1_BASE (HW_EVENT_MASK + 128) + +#define IPP_INT2_CTX1_CDAF_INT 0 +#define IPP_INT2_CTX1_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_INT2_CTX1_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_INT2_CTX1_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_INT2_CTX1_THSTAT_STATISTICS_DONE 4 +#define IPP_INT2_CTX1_FRO_GROUP2 5 +#define IPP_INT2_CTX1_FRO_GROUP4 6 +#define IPP_INT2_CTX1_FRO_GROUP5 7 + +#define IPP_INT2_CTX2_BASE (HW_EVENT_MASK + 160) + +#define IPP_INT2_CTX2_CDAF_INT 0 +#define IPP_INT2_CTX2_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_INT2_CTX2_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_INT2_CTX2_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_INT2_CTX2_THSTAT_STATISTICS_DONE 4 +#define IPP_INT2_CTX2_FRO_GROUP2 5 +#define IPP_INT2_CTX2_FRO_GROUP4 6 +#define IPP_INT2_CTX2_FRO_GROUP5 7 + + + + +#define IPP_FRO_INT0_CTX0_BASE (HW_EVENT_MASK + 192) + +#define IPP_FRO_INT0_CTX0_FRAME_START 0 +#define IPP_FRO_INT0_CTX0_FRAME_END_INTERRUPT 1 +#define IPP_FRO_INT0_CTX0_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_FRO_INT0_CTX0_IRQ_CORRUPTED 3 +#define IPP_FRO_INT0_CTX0_COREX_ERROR_INT 4 +#define IPP_FRO_INT0_CTX0_P_SLVERR 5 +#define IPP_FRO_INT0_CTX0_PRE_FRAME_END_INTERRUPT 6 +#define IPP_FRO_INT0_CTX0_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_FRO_INT0_CTX0_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_FRO_INT0_CTX0_STRP_OUT_DMA_IN_LAST 9 +#define IPP_FRO_INT0_CTX0_BDS_DATA_OUT_LAST 10 +#define IPP_FRO_INT0_CTX0_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_FRO_INT0_CTX0_BCROP1_DATA_IN_LAST 12 +#define IPP_FRO_INT0_CTX0_BCROP0_DATA_IN_LAST 13 +#define IPP_FRO_INT0_CTX0_RGBYHIST2DMA_DONE 14 +#define IPP_FRO_INT0_CTX0_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_FRO_INT0_CTX0_THSTAT_DATA_IN_LAST 16 +#define IPP_FRO_INT0_CTX0_GP_DATA_IN_LAST 17 +#define IPP_FRO_INT0_CTX0_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_FRO_INT0_CTX0_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_FRO_INT0_CTX0_COREX_END_INT0 20 +#define IPP_FRO_INT0_CTX0_COREX_END_INT1 21 +#define IPP_FRO_INT0_CTX0_COUTFIFO_SIZE_ERROR 22 +#define IPP_FRO_INT0_CTX0_COUTFIFO_LINE_ERROR 23 +#define IPP_FRO_INT0_CTX0_COUTFIFO_COL_ERROR 24 +#define IPP_FRO_INT0_CTX0_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_FRO_INT0_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_FRO_INT0_CTX0_CINFIFO_LINES_ERROR_INT 27 +#define IPP_FRO_INT0_CTX0_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_FRO_INT0_CTX0_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_FRO_INT0_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + +#define IPP_FRO_INT0_CTX1_BASE (HW_EVENT_MASK + 224) + +#define IPP_FRO_INT0_CTX1_FRAME_START 0 +#define IPP_FRO_INT0_CTX1_FRAME_END_INTERRUPT 1 +#define IPP_FRO_INT0_CTX1_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_FRO_INT0_CTX1_IRQ_CORRUPTED 3 +#define IPP_FRO_INT0_CTX1_COREX_ERROR_INT 4 +#define IPP_FRO_INT0_CTX1_P_SLVERR 5 +#define IPP_FRO_INT0_CTX1_PRE_FRAME_END_INTERRUPT 6 +#define IPP_FRO_INT0_CTX1_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_FRO_INT0_CTX1_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_FRO_INT0_CTX1_STRP_OUT_DMA_IN_LAST 9 +#define IPP_FRO_INT0_CTX1_BDS_DATA_OUT_LAST 10 +#define IPP_FRO_INT0_CTX1_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_FRO_INT0_CTX1_BCROP1_DATA_IN_LAST 12 +#define IPP_FRO_INT0_CTX1_BCROP0_DATA_IN_LAST 13 +#define IPP_FRO_INT0_CTX1_RGBYHIST2DMA_DONE 14 +#define IPP_FRO_INT0_CTX1_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_FRO_INT0_CTX1_THSTAT_DATA_IN_LAST 16 +#define IPP_FRO_INT0_CTX1_GP_DATA_IN_LAST 17 +#define IPP_FRO_INT0_CTX1_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_FRO_INT0_CTX1_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_FRO_INT0_CTX1_COREX_END_INT0 20 +#define IPP_FRO_INT0_CTX1_COREX_END_INT1 21 +#define IPP_FRO_INT0_CTX1_COUTFIFO_SIZE_ERROR 22 +#define IPP_FRO_INT0_CTX1_COUTFIFO_LINE_ERROR 23 +#define IPP_FRO_INT0_CTX1_COUTFIFO_COL_ERROR 24 +#define IPP_FRO_INT0_CTX1_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_FRO_INT0_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_FRO_INT0_CTX1_CINFIFO_LINES_ERROR_INT 27 +#define IPP_FRO_INT0_CTX1_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_FRO_INT0_CTX1_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_FRO_INT0_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + +#define IPP_FRO_INT0_CTX2_BASE (HW_EVENT_MASK + 256) + +#define IPP_FRO_INT0_CTX2_FRAME_START 0 +#define IPP_FRO_INT0_CTX2_FRAME_END_INTERRUPT 1 +#define IPP_FRO_INT0_CTX2_FRAME_INT_ON_ROW_COL_INFO 2 +#define IPP_FRO_INT0_CTX2_IRQ_CORRUPTED 3 +#define IPP_FRO_INT0_CTX2_COREX_ERROR_INT 4 +#define IPP_FRO_INT0_CTX2_P_SLVERR 5 +#define IPP_FRO_INT0_CTX2_PRE_FRAME_END_INTERRUPT 6 +#define IPP_FRO_INT0_CTX2_COUTFIFO_DATA_OUT_END_INT 7 +#define IPP_FRO_INT0_CTX2_COUTFIFO_FRAME_OUT_END_INT 8 +#define IPP_FRO_INT0_CTX2_STRP_OUT_DMA_IN_LAST 9 +#define IPP_FRO_INT0_CTX2_BDS_DATA_OUT_LAST 10 +#define IPP_FRO_INT0_CTX2_ZSL_OUT_DMA_IN_LAST 11 +#define IPP_FRO_INT0_CTX2_BCROP1_DATA_IN_LAST 12 +#define IPP_FRO_INT0_CTX2_BCROP0_DATA_IN_LAST 13 +#define IPP_FRO_INT0_CTX2_RGBYHIST2DMA_DONE 14 +#define IPP_FRO_INT0_CTX2_RGBYHIST_DATA_OUT_LAST 15 +#define IPP_FRO_INT0_CTX2_THSTAT_DATA_IN_LAST 16 +#define IPP_FRO_INT0_CTX2_GP_DATA_IN_LAST 17 +#define IPP_FRO_INT0_CTX2_CINFIFO_DATA_OUT_END_INT 18 +#define IPP_FRO_INT0_CTX2_CINFIFO_FRAME_OUT_END_INT 19 +#define IPP_FRO_INT0_CTX2_COREX_END_INT0 20 +#define IPP_FRO_INT0_CTX2_COREX_END_INT1 21 +#define IPP_FRO_INT0_CTX2_COUTFIFO_SIZE_ERROR 22 +#define IPP_FRO_INT0_CTX2_COUTFIFO_LINE_ERROR 23 +#define IPP_FRO_INT0_CTX2_COUTFIFO_COL_ERROR 24 +#define IPP_FRO_INT0_CTX2_COUTFIFO_OVERFLOW_ERROR 25 +#define IPP_FRO_INT0_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT 26 +#define IPP_FRO_INT0_CTX2_CINFIFO_LINES_ERROR_INT 27 +#define IPP_FRO_INT0_CTX2_CINFIFO_COLUMNS_ERROR_INT 28 +#define IPP_FRO_INT0_CTX2_CINFIFO_STREAM_OVERFLOW_SIG 29 +#define IPP_FRO_INT0_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED 30 + + + +#define IPP_FRO_INT1_CTX0_BASE (HW_EVENT_MASK + 288) + +#define IPP_FRO_INT1_CTX0_CDAF_INT 0 +#define IPP_FRO_INT1_CTX0_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_FRO_INT1_CTX0_THSTAT_STATISTICS_DONE 4 +#define IPP_FRO_INT1_CTX0_FRO_GROUP2_INT 5 +#define IPP_FRO_INT1_CTX0_FRO_GROUP4_INT 6 +#define IPP_FRO_INT1_CTX0_FRO_GROUP5_INT 7 + +#define IPP_FRO_INT1_CTX1_BASE (HW_EVENT_MASK + 320) + +#define IPP_FRO_INT1_CTX1_CDAF_INT 0 +#define IPP_FRO_INT1_CTX1_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_FRO_INT1_CTX1_THSTAT_STATISTICS_DONE 4 +#define IPP_FRO_INT1_CTX1_FRO_GROUP2_INT 5 +#define IPP_FRO_INT1_CTX1_FRO_GROUP4_INT 6 +#define IPP_FRO_INT1_CTX1_FRO_GROUP5_INT 7 + +#define IPP_FRO_INT1_CTX2_BASE (HW_EVENT_MASK + 352) + +#define IPP_FRO_INT1_CTX2_CDAF_INT 0 +#define IPP_FRO_INT1_CTX2_COUTFIFO_FRAME_OUT_START_INFO 1 +#define IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_END_INFO 2 +#define IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_START_INFO 3 +#define IPP_FRO_INT1_CTX2_THSTAT_STATISTICS_DONE 4 +#define IPP_FRO_INT1_CTX2_FRO_GROUP2_INT 5 +#define IPP_FRO_INT1_CTX2_FRO_GROUP4_INT 6 +#define IPP_FRO_INT1_CTX2_FRO_GROUP5_INT 7 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_START \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_IRQ_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_P_SLVERR \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_RGBY_HIST2_DMA_DONE \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_RGBY_HIST2_DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_GP_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_END_INT0 \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COREX_END_INT1 \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX0_BASE, IPP_INT1_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_START \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_IRQ_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_P_SLVERR \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_RGBY_HIST2_DMA_DONE \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_RGBY_HIST2_DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_GP_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_END_INT0 \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COREX_END_INT1 \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX1_BASE, IPP_INT1_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_START \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_IRQ_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_P_SLVERR \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_RGBY_HIST2_DMA_DONE \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_RGBY_HIST2_DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_GP_DATA_IN_LAST \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_END_INT0 \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COREX_END_INT1 \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED \ + EVENT_ID(IPP_INT1_CTX2_BASE, IPP_INT1_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CDAF_INT \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP2 \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_FRO_GROUP2) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP4 \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_FRO_GROUP4) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX0_FRO_GROUP5 \ + EVENT_ID(IPP_INT2_CTX0_BASE, IPP_INT2_CTX0_FRO_GROUP5) + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CDAF_INT \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP2 \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_FRO_GROUP2) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP4 \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_FRO_GROUP4) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX1_FRO_GROUP5 \ + EVENT_ID(IPP_INT2_CTX1_BASE, IPP_INT2_CTX1_FRO_GROUP5) + +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CDAF_INT \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP2 \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_FRO_GROUP2) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP4 \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_FRO_GROUP4) +#define LWIS_PLATFORM_EVENT_ID_IPP_CTX2_FRO_GROUP5 \ + EVENT_ID(IPP_INT2_CTX2_BASE, IPP_INT2_CTX2_FRO_GROUP5) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_START \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_IRQ_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_P_SLVERR \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_RGBYHIST2DMA_DONE \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_RGBYHIST2DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_GP_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_END_INT0 \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COREX_END_INT1 \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRM_START_BEFORE_END_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX0_BASE, IPP_FRO_INT0_CTX0_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_START \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_IRQ_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_P_SLVERR \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_RGBYHIST2DMA_DONE \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_RGBYHIST2DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_GP_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_END_INT0 \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COREX_END_INT1 \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRM_START_BEFORE_END_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX1_BASE, IPP_FRO_INT0_CTX1_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_START \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_IRQ_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_P_SLVERR \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_P_SLVERR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_STRP_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_STRP_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BDS_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_BDS_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_ZSL_OUT_DMA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_ZSL_OUT_DMA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BCROP1_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_BCROP1_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_BCROP0_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_BCROP0_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_RGBYHIST2DMA_DONE \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_RGBYHIST2DMA_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_RGBYHIST_DATA_OUT_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_RGBYHIST_DATA_OUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_THSTAT_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_THSTAT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_GP_DATA_IN_LAST \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_GP_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_DATA_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_OUT_END_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_END_INT0 \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COREX_END_INT1 \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_SIZE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_LINE_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_COL_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRM_START_BEFORE_END_CORRUPTED \ + EVENT_ID(IPP_FRO_INT0_CTX2_BASE, IPP_FRO_INT0_CTX2_FRAME_START_BEFORE_FRAME_END_CORRUPTED) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CDAF_INT \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP2_INT \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_FRO_GROUP2_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP4_INT \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_FRO_GROUP4_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX0_FRO_GROUP5_INT \ + EVENT_ID(IPP_FRO_INT1_CTX0_BASE, IPP_FRO_INT1_CTX0_FRO_GROUP5_INT) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CDAF_INT \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP2_INT \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_FRO_GROUP2_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP4_INT \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_FRO_GROUP4_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX1_FRO_GROUP5_INT \ + EVENT_ID(IPP_FRO_INT1_CTX1_BASE, IPP_FRO_INT1_CTX1_FRO_GROUP5_INT) + +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CDAF_INT \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_CDAF_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_COUTFIFO_FRAME_OUT_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_COUTFIFO_FRAME_OUT_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_IN_END_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_END_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_CINFIFO_FRAME_IN_START_INFO \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_CINFIFO_FRAME_IN_START_INFO) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_THSTAT_STATISTICS_DONE \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_THSTAT_STATISTICS_DONE) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP2_INT \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_FRO_GROUP2_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP4_INT \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_FRO_GROUP4_INT) +#define LWIS_PLATFORM_EVENT_ID_IPP_FRO_CTX2_FRO_GROUP5_INT \ + EVENT_ID(IPP_FRO_INT1_CTX2_BASE, IPP_FRO_INT1_CTX2_FRO_GROUP5_INT) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_IPP_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/itp.h b/include/dt-bindings/lwis/platform/gs201/itp.h new file mode 100644 index 000000000000..404c4e1130db --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/itp.h @@ -0,0 +1,437 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 ITP Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_ITP_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_ITP_H_ + +#include + +/* clang-format off */ + +#define ITP_ITP_INT0_BASE (HW_EVENT_MASK + 0) + +#define ITP_ITP_INT0_FRAME_START 0 +#define ITP_ITP_INT0_FRAME_END 1 +#define ITP_ITP_INT0_CMDQ_HOLD 2 +#define ITP_ITP_INT0_SETTING_DONE 3 +#define ITP_ITP_INT0_C_LOADER_END 4 +#define ITP_ITP_INT0_COREX_END0 5 +#define ITP_ITP_INT0_COREX_END1 6 +#define ITP_ITP_INT0_ROW_COL 7 +#define ITP_ITP_INT0_FREEZE_ON_ROW_COL 8 +#define ITP_ITP_INT0_TRANS_STOP_DONE 9 +#define ITP_ITP_INT0_CMDQ_ERROR 10 +#define ITP_ITP_INT0_C_LOADER_ERROR 11 +#define ITP_ITP_INT0_COREX_ERROR 12 +#define ITP_ITP_INT0_CINFIFO0_OVERFLOW_ERROR 13 +#define ITP_ITP_INT0_CINFIFO0_OVERLAP_ERROR 14 +#define ITP_ITP_INT0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define ITP_ITP_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define ITP_ITP_INT0_CINFIFO1_OVERFLOW_ERROR 17 +#define ITP_ITP_INT0_CINFIFO1_OVERLAP_ERROR 18 +#define ITP_ITP_INT0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define ITP_ITP_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define ITP_ITP_INT0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define ITP_ITP_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define ITP_ITP_INT0_COUTFIFO0_OVERFLOW_ERROR 23 + +#define ITP_ITP_CMDQ_INT_BASE (HW_EVENT_MASK + 32) + +#define ITP_ITP_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN 0 +#define ITP_ITP_CMDQ_INT_PRELOAD_FLUSH 1 +#define ITP_ITP_CMDQ_INT_QUE0_OVERFLOW 2 + +#define ITP_DNS_INT0_BASE (HW_EVENT_MASK + 64) + +#define ITP_DNS_INT0_DNS0_FRAME_START 0 +#define ITP_DNS_INT0_DNS0_FRAME_END 1 +#define ITP_DNS_INT0_DNS0_CMDQ_HOLD 2 +#define ITP_DNS_INT0_DNS0_SETTING_DONE 3 +#define ITP_DNS_INT0_DNS0_C_LOADER_END 4 +#define ITP_DNS_INT0_DNS0_COREX_END0 5 +#define ITP_DNS_INT0_DNS0_COREX_END1 6 +#define ITP_DNS_INT0_DNS0_ROW_COL 7 +#define ITP_DNS_INT0_DNS0_FREEZE_ON_ROW_COL 8 +#define ITP_DNS_INT0_DNS0_TRANS_STOP_DONE 9 +#define ITP_DNS_INT0_DNS0_CMDQ_ERROR 10 +#define ITP_DNS_INT0_DNS0_C_LOADER_ERROR 11 +#define ITP_DNS_INT0_DNS0_COREX_ERROR 12 +#define ITP_DNS_INT0_DNS0_CINFIFO0_OVERFLOW_ERROR 13 +#define ITP_DNS_INT0_DNS0_CINFIFO0_OVERLAP_ERROR 14 +#define ITP_DNS_INT0_DNS0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define ITP_DNS_INT0_DNS0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define ITP_DNS_INT0_DNS0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define ITP_DNS_INT0_DNS0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define ITP_DNS_INT0_DNS0_COUTFIFO0_OVERFLOW_ERROR 23 +#define ITP_DNS_INT0_DNS0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define ITP_DNS_INT0_DNS0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define ITP_DNS_INT0_DNS0_COUTFIFO1_OVERFLOW_ERROR 26 +#define ITP_DNS_INT0_DNS0_VOTF_GLOBAL_ERROR 27 +#define ITP_DNS_INT0_DNS0_VOTF_LOST_CONNECTION 28 +#define ITP_DNS_INT0_DNS0_OTF_SEQ_ID_ERROR 29 + +#define ITP_DNS_INT1_BASE (HW_EVENT_MASK + 96) + +#define ITP_DNS_INT1_DNS1_SBWC_ERR 0 +#define ITP_DNS_INT1_DNS1_VOTF_SLOW_RING 1 +#define ITP_DNS_INT1_DNS1_VOTF_LOST_CONNECTION 2 +#define ITP_DNS_INT1_DNS1_VOTF_LOST_FLUSH 3 +#define ITP_DNS_INT1_DNS1_COUTFIFO2_PIXEL_CNT_ERROR 4 +#define ITP_DNS_INT1_DNS1_COUTFIFO2_INPUT_PROTOCOL_ERROR 5 +#define ITP_DNS_INT1_DNS1_COUTFIFO2_OVERFLOW_ERROR 6 + +#define ITP_DNS_CMDQ_INT_BASE (HW_EVENT_MASK + 128) + +#define ITP_DNS_CMDQ_INT_DNS_STOP_CRPT_OFF_CMDQ_EN 0 +#define ITP_DNS_CMDQ_INT_DNS_PRELOAD_FLUSH 1 +#define ITP_DNS_CMDQ_INT_DNS_QUE0_OVERFLOW 2 + +#define ITP_ITSC_INT0_BASE (HW_EVENT_MASK + 160) + +#define ITP_ITSC_INT0_ITSC0_FRAME_START 0 +#define ITP_ITSC_INT0_ITSC0_FRAME_END 1 +#define ITP_ITSC_INT0_ITSC0_CMDQ_HOLD 2 +#define ITP_ITSC_INT0_ITSC0_SETTING_DONE 3 +#define ITP_ITSC_INT0_ITSC0_C_LOADER_END 4 +#define ITP_ITSC_INT0_ITSC0_COREX_END0 5 +#define ITP_ITSC_INT0_ITSC0_COREX_END1 6 +#define ITP_ITSC_INT0_ITSC0_ROW_COL 7 +#define ITP_ITSC_INT0_ITSC0_FREEZE_ON_ROW_COL 8 +#define ITP_ITSC_INT0_ITSC0_TRANS_STOP_DONE 9 +#define ITP_ITSC_INT0_ITSC0_CMDQ_ERROR 10 +#define ITP_ITSC_INT0_ITSC0_C_LOADER_ERROR 11 +#define ITP_ITSC_INT0_ITSC0_COREX_ERROR 12 +#define ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERFLOW_ERROR 13 +#define ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERLAP_ERROR 14 +#define ITP_ITSC_INT0_ITSC0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define ITP_ITSC_INT0_ITSC0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERFLOW_ERROR 17 +#define ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERLAP_ERROR 18 +#define ITP_ITSC_INT0_ITSC0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define ITP_ITSC_INT0_ITSC0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO0_OVERFLOW_ERROR 23 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define ITP_ITSC_INT0_ITSC0_COUTFIFO1_OVERFLOW_ERROR 26 +#define ITP_ITSC_INT0_ITSC0_VOTF_GLOBAL_ERROR 27 +#define ITP_ITSC_INT0_ITSC0_VOTF_LOST_CONNECTION 28 +#define ITP_ITSC_INT0_ITSC0_OTF_SEQ_ID_ERROR 29 + +#define ITP_ITSC_INT1_BASE (HW_EVENT_MASK + 192) + +#define ITP_ITSC_INT1_ITSC1_VOTF_LOST_FLUSH 0 + +#define ITP_ITSC_CMDQ_INT_BASE (HW_EVENT_MASK + 224) + +#define ITP_ITSC_CMDQ_INT_ITSC_STOP_CRPT_OFF_CMDQ_EN 0 +#define ITP_ITSC_CMDQ_INT_ITSC_PRELOAD_FLUSH 1 +#define ITP_ITSC_CMDQ_INT_ITSC_QUE0_OVERFLOW 2 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_ITP_FRAME_START \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_ITP_FRAME_END \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_CMDQ_HOLD \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_ITP_SETTING_DONE \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_C_LOADER_END \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_COREX_END0 \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_ITP_COREX_END1 \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_ITP_ROW_COL \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_FREEZE_ON_ROW_COL \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_TRANS_STOP_DONE \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_CMDQ_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_C_LOADER_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_COREX_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITP_INT0_BASE, \ + ITP_ITP_INT0_COUTFIFO0_OVERFLOW_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_ITP_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(ITP_ITP_CMDQ_INT_BASE, \ + ITP_ITP_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_ITP_PRELOAD_FLUSH \ + EVENT_ID(ITP_ITP_CMDQ_INT_BASE, \ + ITP_ITP_CMDQ_INT_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_ITP_QUE0_OVERFLOW \ + EVENT_ID(ITP_ITP_CMDQ_INT_BASE, \ + ITP_ITP_CMDQ_INT_QUE0_OVERFLOW) + +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FRAME_START \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FRAME_END \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CMDQ_HOLD \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_SETTING_DONE \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_C_LOADER_END \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_END0 \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_END1 \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_ROW_COL \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_FREEZE_ON_ROW_COL \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_TRANS_STOP_DONE \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CMDQ_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_C_LOADER_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COREX_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_VOTF_GLOBAL_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_VOTF_GLOBAL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_VOTF_LOST_CONNECTION \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS0_OTF_SEQ_ID_ERROR \ + EVENT_ID(ITP_DNS_INT0_BASE, \ + ITP_DNS_INT0_DNS0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_SBWC_ERR \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_SBWC_ERR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_SLOW_RING \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_VOTF_SLOW_RING) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_LOST_CONNECTION \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_VOTF_LOST_FLUSH \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_VOTF_LOST_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_COUTFIFO2_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_COUTFIFO2_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS1_COUTFIFO2_OVERFLOW_ERROR \ + EVENT_ID(ITP_DNS_INT1_BASE, \ + ITP_DNS_INT1_DNS1_COUTFIFO2_OVERFLOW_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(ITP_DNS_CMDQ_INT_BASE, \ + ITP_DNS_CMDQ_INT_DNS_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS_PRELOAD_FLUSH \ + EVENT_ID(ITP_DNS_CMDQ_INT_BASE, \ + ITP_DNS_CMDQ_INT_DNS_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_ITP_DNS_QUE0_OVERFLOW \ + EVENT_ID(ITP_DNS_CMDQ_INT_BASE, \ + ITP_DNS_CMDQ_INT_DNS_QUE0_OVERFLOW) + +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FRAME_START \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FRAME_END \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CMDQ_HOLD \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_SETTING_DONE \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_C_LOADER_END \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_END0 \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_END1 \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_ROW_COL \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_FREEZE_ON_ROW_COL \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_TRANS_STOP_DONE \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CMDQ_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_C_LOADER_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COREX_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_VOTF_GLOBAL_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_VOTF_GLOBAL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_VOTF_LOST_CONNECTION \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC0_OTF_SEQ_ID_ERROR \ + EVENT_ID(ITP_ITSC_INT0_BASE, \ + ITP_ITSC_INT0_ITSC0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC1_VOTF_LOST_FLUSH \ + EVENT_ID(ITP_ITSC_INT1_BASE, \ + ITP_ITSC_INT1_ITSC1_VOTF_LOST_FLUSH) + +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(ITP_ITSC_CMDQ_INT_BASE, \ + ITP_ITSC_CMDQ_INT_ITSC_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC_PRELOAD_FLUSH \ + EVENT_ID(ITP_ITSC_CMDQ_INT_BASE, \ + ITP_ITSC_CMDQ_INT_ITSC_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_ITP_ITSC_QUE0_OVERFLOW \ + EVENT_ID(ITP_ITSC_CMDQ_INT_BASE, \ + ITP_ITSC_CMDQ_INT_ITSC_QUE0_OVERFLOW) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_ITP_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/mcsc.h b/include/dt-bindings/lwis/platform/gs201/mcsc.h new file mode 100644 index 000000000000..55698725ec7c --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/mcsc.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 MCSC Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_MCSC_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_MCSC_H_ + +#include + +/* clang-format off */ + +#define MCSC_INT0_BASE (HW_EVENT_MASK + 0) + +#define MCSC_INT0_FRAME_START 0 +#define MCSC_INT0_FRAME_END 1 +#define MCSC_INT0_CMDQ_HOLD 2 +#define MCSC_INT0_SETTING_DONE 3 +#define MCSC_INT0_C_LOADER_END 4 +#define MCSC_INT0_COREX_END0 5 +#define MCSC_INT0_COREX_END1 6 +#define MCSC_INT0_ROW_COL 7 +#define MCSC_INT0_FREEZE_ON_ROW_COL 8 +#define MCSC_INT0_TRANS_STOP_DONE 9 +#define MCSC_INT0_CMDQ_ERROR 10 +#define MCSC_INT0_C_LOADER_ERROR 11 +#define MCSC_INT0_COREX_ERROR 12 +#define MCSC_INT0_CINFIFO0_OVERFLOW_ERROR 13 +#define MCSC_INT0_CINFIFO0_OVERLAP_ERROR 14 +#define MCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define MCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define MCSC_INT0_CINFIFO1_OVERFLOW_ERROR 17 +#define MCSC_INT0_CINFIFO1_OVERLAP_ERROR 18 +#define MCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define MCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define MCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define MCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define MCSC_INT0_COUTFIFO0_OVERFLOW_ERROR 23 +#define MCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define MCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define MCSC_INT0_COUTFIFO1_OVERFLOW_ERROR 26 +#define MCSC_INT0_VOTF_GLOBAL_ERROR 27 +#define MCSC_INT0_VOTF_LOST_CONNECTION 28 +#define MCSC_INT0_OTF_SEQ_ID_ERROR 29 + +#define MCSC_INT1_BASE (HW_EVENT_MASK + 32) + +#define MCSC_INT1_RDMA_M0_FINISH 0 +#define MCSC_INT1_WDMA_M0_FINISH 1 +#define MCSC_INT1_WDMA_M1_FINISH 2 +#define MCSC_INT1_WDMA_M2_FINISH 3 +#define MCSC_INT1_WDMA_M3_FINISH 4 +#define MCSC_INT1_WDMA_M4_FINISH 5 +#define MCSC_INT1_RDMA_VOTF_LOST_CONNECTION 6 +#define MCSC_INT1_COMP_DEC_ERROR 8 +#define MCSC_INT1_DJAG_FINISH 9 +#define MCSC_INT1_SC0_FINISH 10 +#define MCSC_INT1_SC1_FINISH 11 +#define MCSC_INT1_SC2_FINISH 12 +#define MCSC_INT1_SC3_FINISH 13 +#define MCSC_INT1_SC4_FINISH 14 +#define MCSC_INT1_PC0_FINISH 15 +#define MCSC_INT1_PC1_FINISH 16 +#define MCSC_INT1_PC2_FINISH 17 +#define MCSC_INT1_PC3_FINISH 18 +#define MCSC_INT1_PC4_FINISH 19 +#define MCSC_INT1_CONV4200_FINISH 20 +#define MCSC_INT1_CONV4201_FINISH 21 +#define MCSC_INT1_CONV4202_FINISH 22 +#define MCSC_INT1_CONV4203_FINISH 23 +#define MCSC_INT1_CONV4204_FINISH 24 +#define MCSC_INT1_BCHS0_FINISH 25 +#define MCSC_INT1_BCHS1_FINISH 26 +#define MCSC_INT1_BCHS2_FINISH 27 +#define MCSC_INT1_BCHS3_FINISH 28 +#define MCSC_INT1_BCHS4_FINISH 29 + +#define MCSC_CMDQ_INT_BASE (HW_EVENT_MASK + 64) + +#define MCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN 0 +#define MCSC_CMDQ_INT_PRELOAD_FLUSH 1 +#define MCSC_CMDQ_INT_QUE0_OVERFLOW 2 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_MCSC_FRAME_START \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_MCSC_FRAME_END \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CMDQ_HOLD \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SETTING_DONE \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_MCSC_C_LOADER_END \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COREX_END0 \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COREX_END1 \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_MCSC_ROW_COL \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_MCSC_FREEZE_ON_ROW_COL \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_MCSC_TRANS_STOP_DONE \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CMDQ_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_C_LOADER_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COREX_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_VOTF_GLOBAL_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_VOTF_GLOBAL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_VOTF_LOST_CONNECTION \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_MCSC_OTF_SEQ_ID_ERROR \ + EVENT_ID(MCSC_INT0_BASE, \ + MCSC_INT0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_MCSC_RDMA_M0_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_RDMA_M0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M0_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_WDMA_M0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M1_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_WDMA_M1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M2_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_WDMA_M2_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M3_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_WDMA_M3_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_WDMA_M4_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_WDMA_M4_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_RDMA_VOTF_LOST_CONNECTION \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_RDMA_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_MCSC_COMP_DEC_ERROR \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_COMP_DEC_ERROR) +#define LWIS_PLATFORM_EVENT_ID_MCSC_DJAG_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_DJAG_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SC0_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_SC0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SC1_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_SC1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SC2_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_SC2_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SC3_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_SC3_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_SC4_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_SC4_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PC0_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_PC0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PC1_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_PC1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PC2_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_PC2_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PC3_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_PC3_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PC4_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_PC4_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CONV4200_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_CONV4200_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CONV4201_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_CONV4201_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CONV4202_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_CONV4202_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CONV4203_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_CONV4203_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_CONV4204_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_CONV4204_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_BCHS0_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_BCHS0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_BCHS1_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_BCHS1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_BCHS2_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_BCHS2_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_BCHS3_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_BCHS3_FINISH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_BCHS4_FINISH \ + EVENT_ID(MCSC_INT1_BASE, \ + MCSC_INT1_BCHS4_FINISH) + +#define LWIS_PLATFORM_EVENT_ID_MCSC_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(MCSC_CMDQ_INT_BASE, \ + MCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_MCSC_PRELOAD_FLUSH \ + EVENT_ID(MCSC_CMDQ_INT_BASE, \ + MCSC_CMDQ_INT_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_MCSC_QUE0_OVERFLOW \ + EVENT_ID(MCSC_CMDQ_INT_BASE, \ + MCSC_CMDQ_INT_QUE0_OVERFLOW) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_MCSC_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/pdp.h b/include/dt-bindings/lwis/platform/gs201/pdp.h new file mode 100644 index 000000000000..ac9bf82340e3 --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/pdp.h @@ -0,0 +1,503 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 PDP Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_PDP_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_PDP_H_ + +#include + +/* clang-format off */ + + +#define PDP_INT_SRC1_CTX0_BASE (HW_EVENT_MASK + 0) + +#define PDP_INT_SRC1_CTX0_FRAME_START 0 +#define PDP_INT_SRC1_CTX0_FRAME_END_INTERRUPT 1 +#define PDP_INT_SRC1_CTX0_FRAME_INT_ON_ROW_COL_INFO 2 +#define PDP_INT_SRC1_CTX0_IRQ_CORRUPTED 3 +#define PDP_INT_SRC1_CTX0_COREX_ERROR_INT 4 +#define PDP_INT_SRC1_CTX0_PRE_FRAME_END_INTERRUPT 6 +#define PDP_INT_SRC1_CTX0_LIC_INPUT_FRAME_END 7 +#define PDP_INT_SRC1_CTX0_LIC_OUTPUT_FRAME_END 8 +#define PDP_INT_SRC1_CTX0_AFIDENT_DATA_IN_LAST 9 +#define PDP_INT_SRC1_CTX0_COUTFIFO_DATA_OUT_END_INT 10 +#define PDP_INT_SRC1_CTX0_COUTFIFO_FRAME_OUT_END_INT 11 +#define PDP_INT_SRC1_CTX0_RCB_OUTPUT_LAST 12 +#define PDP_INT_SRC1_CTX0_MPD_IR_OUTPUT_LAST 13 +#define PDP_INT_SRC1_CTX0_YEXT_OUTPUT_LAST 14 +#define PDP_INT_SRC1_CTX0_BPC_IR_OUTPUT_LAST 15 +#define PDP_INT_SRC1_CTX0_REORDER_IR_OUTPUT_LAST 16 +#define PDP_INT_SRC1_CTX0_GAMMA0_OUTPUT_LAST 17 +#define PDP_INT_SRC1_CTX0_GAMMA1_IR_OUTPUT_LAST 18 +#define PDP_INT_SRC1_CTX0_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT 19 +#define PDP_INT_SRC1_CTX0_COREX_END_INT0 20 +#define PDP_INT_SRC1_CTX0_COREX_END_INT1 21 +#define PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_DATA_OUT_END_INT 22 +#define PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_FRAME_OUT_END_INT 23 +#define PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_DATA_OUT_END_INT 24 +#define PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_FRAME_OUT_END_INT 25 + +#define PDP_INT_SRC1_CTX1_BASE (HW_EVENT_MASK + 32) + +#define PDP_INT_SRC1_CTX1_FRAME_START 0 +#define PDP_INT_SRC1_CTX1_FRAME_END_INTERRUPT 1 +#define PDP_INT_SRC1_CTX1_FRAME_INT_ON_ROW_COL_INFO 2 +#define PDP_INT_SRC1_CTX1_IRQ_CORRUPTED 3 +#define PDP_INT_SRC1_CTX1_COREX_ERROR_INT 4 +#define PDP_INT_SRC1_CTX1_PRE_FRAME_END_INTERRUPT 6 +#define PDP_INT_SRC1_CTX1_LIC_INPUT_FRAME_END 7 +#define PDP_INT_SRC1_CTX1_LIC_OUTPUT_FRAME_END 8 +#define PDP_INT_SRC1_CTX1_AFIDENT_DATA_IN_LAST 9 +#define PDP_INT_SRC1_CTX1_COUTFIFO_DATA_OUT_END_INT 10 +#define PDP_INT_SRC1_CTX1_COUTFIFO_FRAME_OUT_END_INT 11 +#define PDP_INT_SRC1_CTX1_RCB_OUTPUT_LAST 12 +#define PDP_INT_SRC1_CTX1_MPD_IR_OUTPUT_LAST 13 +#define PDP_INT_SRC1_CTX1_YEXT_OUTPUT_LAST 14 +#define PDP_INT_SRC1_CTX1_BPC_IR_OUTPUT_LAST 15 +#define PDP_INT_SRC1_CTX1_REORDER_IR_OUTPUT_LAST 16 +#define PDP_INT_SRC1_CTX1_GAMMA0_OUTPUT_LAST 17 +#define PDP_INT_SRC1_CTX1_GAMMA1_IR_OUTPUT_LAST 18 +#define PDP_INT_SRC1_CTX1_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT 19 +#define PDP_INT_SRC1_CTX1_COREX_END_INT0 20 +#define PDP_INT_SRC1_CTX1_COREX_END_INT1 21 +#define PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_DATA_OUT_END_INT 22 +#define PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_FRAME_OUT_END_INT 23 +#define PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_DATA_OUT_END_INT 24 +#define PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_FRAME_OUT_END_INT 25 + +#define PDP_INT_SRC1_CTX2_BASE (HW_EVENT_MASK + 64) + +#define PDP_INT_SRC1_CTX2_FRAME_START 0 +#define PDP_INT_SRC1_CTX2_FRAME_END_INTERRUPT 1 +#define PDP_INT_SRC1_CTX2_FRAME_INT_ON_ROW_COL_INFO 2 +#define PDP_INT_SRC1_CTX2_IRQ_CORRUPTED 3 +#define PDP_INT_SRC1_CTX2_COREX_ERROR_INT 4 +#define PDP_INT_SRC1_CTX2_PRE_FRAME_END_INTERRUPT 6 +#define PDP_INT_SRC1_CTX2_LIC_INPUT_FRAME_END 7 +#define PDP_INT_SRC1_CTX2_LIC_OUTPUT_FRAME_END 8 +#define PDP_INT_SRC1_CTX2_AFIDENT_DATA_IN_LAST 9 +#define PDP_INT_SRC1_CTX2_COUTFIFO_DATA_OUT_END_INT 10 +#define PDP_INT_SRC1_CTX2_COUTFIFO_FRAME_OUT_END_INT 11 +#define PDP_INT_SRC1_CTX2_RCB_OUTPUT_LAST 12 +#define PDP_INT_SRC1_CTX2_MPD_IR_OUTPUT_LAST 13 +#define PDP_INT_SRC1_CTX2_YEXT_OUTPUT_LAST 14 +#define PDP_INT_SRC1_CTX2_BPC_IR_OUTPUT_LAST 15 +#define PDP_INT_SRC1_CTX2_REORDER_IR_OUTPUT_LAST 16 +#define PDP_INT_SRC1_CTX2_GAMMA0_OUTPUT_LAST 17 +#define PDP_INT_SRC1_CTX2_GAMMA1_IR_OUTPUT_LAST 18 +#define PDP_INT_SRC1_CTX2_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT 19 +#define PDP_INT_SRC1_CTX2_COREX_END_INT0 20 +#define PDP_INT_SRC1_CTX2_COREX_END_INT1 21 +#define PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_DATA_OUT_END_INT 22 +#define PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_FRAME_OUT_END_INT 23 +#define PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_DATA_OUT_END_INT 24 +#define PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_FRAME_OUT_END_INT 25 + + + +#define PDP_INT_SRC2_CTX0_BASE (HW_EVENT_MASK + 96) + +#define PDP_INT_SRC2_CTX0_COUTFIFO_FRAME_OUT_START_INT 1 +#define PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_IMG 5 +#define PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_AF 6 +#define PDP_INT_SRC2_CTX0_C2SER_SLOW_RING 7 +#define PDP_INT_SRC2_CTX0_PDAF_STAT_INT 8 +#define PDP_INT_SRC2_CTX0_SBWC_ERR 9 +#define PDP_INT_SRC2_CTX0_VOTF_LOSTCON_IMG 10 +#define PDP_INT_SRC2_CTX0_VOTF_LOSTCON_AF 11 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_BFRAME_OUT_START_INT 12 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_YFRAME_OUT_START_INT 13 +#define PDP_INT_SRC2_CTX0_COUTFIFO_SIZE_ERROR 14 +#define PDP_INT_SRC2_CTX0_COUTFIFO_LINE_ERROR 15 +#define PDP_INT_SRC2_CTX0_COUTFIFO_COL_ERROR 16 +#define PDP_INT_SRC2_CTX0_COUTFIFO_OVERFLOW_ERROR 17 +#define PDP_INT_SRC2_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT 18 +#define PDP_INT_SRC2_CTX0_CINFIFO_LINES_ERROR_INT 19 +#define PDP_INT_SRC2_CTX0_CINFIFO_COLUMNS_ERROR_INT 20 +#define PDP_INT_SRC2_CTX0_CINFIFO_STREAM_OVERFLOW_SIG 21 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_SIZE_ERROR 24 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_LINE_ERROR 25 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_COL_ERROR 26 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_OVERFLOW_ERROR 27 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_SIZE_ERROR 28 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_LINE_ERROR 29 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_COL_ERROR 30 +#define PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_OVERFLOW_ERROR 31 + +#define PDP_INT_SRC2_CTX1_BASE (HW_EVENT_MASK + 128) + +#define PDP_INT_SRC2_CTX1_COUTFIFO_FRAME_OUT_START_INT 1 +#define PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_IMG 5 +#define PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_AF 6 +#define PDP_INT_SRC2_CTX1_C2SER_SLOW_RING 7 +#define PDP_INT_SRC2_CTX1_PDAF_STAT_INT 8 +#define PDP_INT_SRC2_CTX1_SBWC_ERR 9 +#define PDP_INT_SRC2_CTX1_VOTF_LOSTCON_IMG 10 +#define PDP_INT_SRC2_CTX1_VOTF_LOSTCON_AF 11 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_BFRAME_OUT_START_INT 12 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_YFRAME_OUT_START_INT 13 +#define PDP_INT_SRC2_CTX1_COUTFIFO_SIZE_ERROR 14 +#define PDP_INT_SRC2_CTX1_COUTFIFO_LINE_ERROR 15 +#define PDP_INT_SRC2_CTX1_COUTFIFO_COL_ERROR 16 +#define PDP_INT_SRC2_CTX1_COUTFIFO_OVERFLOW_ERROR 17 +#define PDP_INT_SRC2_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT 18 +#define PDP_INT_SRC2_CTX1_CINFIFO_LINES_ERROR_INT 19 +#define PDP_INT_SRC2_CTX1_CINFIFO_COLUMNS_ERROR_INT 20 +#define PDP_INT_SRC2_CTX1_CINFIFO_STREAM_OVERFLOW_SIG 21 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_SIZE_ERROR 24 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_LINE_ERROR 25 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_COL_ERROR 26 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_OVERFLOW_ERROR 27 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_SIZE_ERROR 28 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_LINE_ERROR 29 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_COL_ERROR 30 +#define PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_OVERFLOW_ERROR 31 + +#define PDP_INT_SRC2_CTX2_BASE (HW_EVENT_MASK + 160) + +#define PDP_INT_SRC2_CTX2_COUTFIFO_FRAME_OUT_START_INT 1 +#define PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_IMG 5 +#define PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_AF 6 +#define PDP_INT_SRC2_CTX2_C2SER_SLOW_RING 7 +#define PDP_INT_SRC2_CTX2_PDAF_STAT_INT 8 +#define PDP_INT_SRC2_CTX2_SBWC_ERR 9 +#define PDP_INT_SRC2_CTX2_VOTF_LOSTCON_IMG 10 +#define PDP_INT_SRC2_CTX2_VOTF_LOSTCON_AF 11 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_BFRAME_OUT_START_INT 12 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_YFRAME_OUT_START_INT 13 +#define PDP_INT_SRC2_CTX2_COUTFIFO_SIZE_ERROR 14 +#define PDP_INT_SRC2_CTX2_COUTFIFO_LINE_ERROR 15 +#define PDP_INT_SRC2_CTX2_COUTFIFO_COL_ERROR 16 +#define PDP_INT_SRC2_CTX2_COUTFIFO_OVERFLOW_ERROR 17 +#define PDP_INT_SRC2_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT 18 +#define PDP_INT_SRC2_CTX2_CINFIFO_LINES_ERROR_INT 19 +#define PDP_INT_SRC2_CTX2_CINFIFO_COLUMNS_ERROR_INT 20 +#define PDP_INT_SRC2_CTX2_CINFIFO_STREAM_OVERFLOW_SIG 21 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_SIZE_ERROR 24 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_LINE_ERROR 25 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_COL_ERROR 26 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_OVERFLOW_ERROR 27 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_SIZE_ERROR 28 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_LINE_ERROR 29 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_COL_ERROR 30 +#define PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_OVERFLOW_ERROR 31 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_START \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_IRQ_CORRUPTED \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_ERROR_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_LIC_INPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_LIC_INPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_LIC_OUTPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_LIC_OUTPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_AFIDENT_DATA_IN_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_AFIDENT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_RCB_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_RCB_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_MPD_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_MPD_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_YEXT_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_YEXT_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_BPC_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_BPC_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_REORDER_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_REORDER_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_GAMMA0_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_GAMMA0_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_GAMMA1_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_GAMMA1_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_END_INT0 \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COREX_END_INT1 \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_G3AAB_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX0_BASE, PDP_INT_SRC1_CTX0_COUTFIFO_G3AAY_FRAME_OUT_END_INT) + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_START \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_IRQ_CORRUPTED \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_ERROR_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_LIC_INPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_LIC_INPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_LIC_OUTPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_LIC_OUTPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_AFIDENT_DATA_IN_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_AFIDENT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_RCB_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_RCB_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_MPD_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_MPD_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_YEXT_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_YEXT_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_BPC_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_BPC_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_REORDER_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_REORDER_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_GAMMA0_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_GAMMA0_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_GAMMA1_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_GAMMA1_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_END_INT0 \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COREX_END_INT1 \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_G3AAB_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX1_BASE, PDP_INT_SRC1_CTX1_COUTFIFO_G3AAY_FRAME_OUT_END_INT) + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_START \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_FRAME_INT_ON_ROW_COL_INFO \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_FRAME_INT_ON_ROW_COL_INFO) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_IRQ_CORRUPTED \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_IRQ_CORRUPTED) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_ERROR_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COREX_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_PRE_FRAME_END_INTERRUPT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_PRE_FRAME_END_INTERRUPT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_LIC_INPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_LIC_INPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_LIC_OUTPUT_FRAME_END \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_LIC_OUTPUT_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_AFIDENT_DATA_IN_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_AFIDENT_DATA_IN_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_RCB_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_RCB_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_MPD_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_MPD_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_YEXT_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_YEXT_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_BPC_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_BPC_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_REORDER_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_REORDER_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_GAMMA0_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_GAMMA0_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_GAMMA1_IR_OUTPUT_LAST \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_GAMMA1_IR_OUTPUT_LAST) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_ALC_IR_LAST_G3AAY_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_END_INT0 \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COREX_END_INT0) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COREX_END_INT1 \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COREX_END_INT1) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_G3AAB_FRAME_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_DATA_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_DATA_OUT_END_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_FRAME_OUT_END_INT \ + EVENT_ID(PDP_INT_SRC1_CTX2_BASE, PDP_INT_SRC1_CTX2_COUTFIFO_G3AAY_FRAME_OUT_END_INT) + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_FRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_FRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOST_FLUSH_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOST_FLUSH_AF \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_VOTF_LOST_FLUSH_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_C2SER_SLOW_RING \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_C2SER_SLOW_RING) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_PDAF_STAT_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_PDAF_STAT_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_SBWC_ERR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_SBWC_ERR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOSTCON_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_VOTF_LOSTCON_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_VOTF_LOSTCON_AF \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_VOTF_LOSTCON_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AA_BFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_BFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AA_YFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AA_YFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAB_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAB_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX0_COUTFIFO_G3AAY_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX0_BASE, PDP_INT_SRC2_CTX0_COUTFIFO_G3AAY_OVERFLOW_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_FRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_FRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOST_FLUSH_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOST_FLUSH_AF \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_VOTF_LOST_FLUSH_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_C2SER_SLOW_RING \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_C2SER_SLOW_RING) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_PDAF_STAT_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_PDAF_STAT_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_SBWC_ERR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_SBWC_ERR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOSTCON_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_VOTF_LOSTCON_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_VOTF_LOSTCON_AF \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_VOTF_LOSTCON_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AA_BFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_BFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AA_YFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AA_YFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAB_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAB_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX1_COUTFIFO_G3AAY_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX1_BASE, PDP_INT_SRC2_CTX1_COUTFIFO_G3AAY_OVERFLOW_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_FRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_FRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOST_FLUSH_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOST_FLUSH_AF \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_VOTF_LOST_FLUSH_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_C2SER_SLOW_RING \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_C2SER_SLOW_RING) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_PDAF_STAT_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_PDAF_STAT_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_SBWC_ERR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_SBWC_ERR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOSTCON_IMG \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_VOTF_LOSTCON_IMG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_VOTF_LOSTCON_AF \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_VOTF_LOSTCON_AF) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AA_BFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_BFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AA_YFRAME_OUT_START_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AA_YFRAME_OUT_START_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_CINFIFO_TOTAL_SIZE_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_LINES_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_CINFIFO_LINES_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_COLUMNS_ERROR_INT \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_CINFIFO_COLUMNS_ERROR_INT) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_CINFIFO_STREAM_OVERFLOW_SIG \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_CINFIFO_STREAM_OVERFLOW_SIG) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAB_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAB_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_SIZE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_SIZE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_LINE_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_LINE_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_COL_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_COL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_PDP_CTX2_COUTFIFO_G3AAY_OVERFLOW_ERROR \ + EVENT_ID(PDP_INT_SRC2_CTX2_BASE, PDP_INT_SRC2_CTX2_COUTFIFO_G3AAY_OVERFLOW_ERROR) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_PDP_H_ */ diff --git a/include/dt-bindings/lwis/platform/gs201/scsc.h b/include/dt-bindings/lwis/platform/gs201/scsc.h new file mode 100644 index 000000000000..50591bf4e0eb --- /dev/null +++ b/include/dt-bindings/lwis/platform/gs201/scsc.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Google LWIS GS201 SCSC Interrupt And Event Defines + * + * Copyright (c) 2021 Google, LLC + */ + +#ifndef DT_BINDINGS_LWIS_PLATFORM_GS201_SCSC_H_ +#define DT_BINDINGS_LWIS_PLATFORM_GS201_SCSC_H_ + +#include + +/* clang-format off */ + +#define SCSC_INT0_BASE (HW_EVENT_MASK + 0) + +#define SCSC_INT0_FRAME_START 0 +#define SCSC_INT0_FRAME_END 1 +#define SCSC_INT0_CMDQ_HOLD 2 +#define SCSC_INT0_SETTING_DONE 3 +#define SCSC_INT0_C_LOADER_END 4 +#define SCSC_INT0_COREX_END0 5 +#define SCSC_INT0_COREX_END1 6 +#define SCSC_INT0_ROW_COL 7 +#define SCSC_INT0_FREEZE_ON_ROW_COL 8 +#define SCSC_INT0_TRANS_STOP_DONE 9 +#define SCSC_INT0_CMDQ_ERROR 10 +#define SCSC_INT0_C_LOADER_ERROR 11 +#define SCSC_INT0_COREX_ERROR 12 +#define SCSC_INT0_CINFIFO0_OVERFLOW_ERROR 13 +#define SCSC_INT0_CINFIFO0_OVERLAP_ERROR 14 +#define SCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR 15 +#define SCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR 16 +#define SCSC_INT0_CINFIFO1_OVERFLOW_ERROR 17 +#define SCSC_INT0_CINFIFO1_OVERLAP_ERROR 18 +#define SCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR 19 +#define SCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR 20 +#define SCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR 21 +#define SCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR 22 +#define SCSC_INT0_COUTFIFO0_OVERFLOW_ERROR 23 +#define SCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR 24 +#define SCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR 25 +#define SCSC_INT0_COUTFIFO1_OVERFLOW_ERROR 26 +#define SCSC_INT0_VOTF_GLOBAL_ERROR 27 +#define SCSC_INT0_VOTF_LOST_CONNECTION 28 +#define SCSC_INT0_OTF_SEQ_ID_ERROR 29 + +#define SCSC_INT1_BASE (HW_EVENT_MASK + 32) + +#define SCSC_INT1_RDMA_M0_FINISH 0 +#define SCSC_INT1_WDMA_M0_FINISH 1 +#define SCSC_INT1_WDMA_M1_FINISH 2 +#define SCSC_INT1_RDMA_VOTF_LOST_CONNECTION 3 +#define SCSC_INT1_COMP_DEC_ERROR 5 +#define SCSC_INT1_DJAG_FINISH 6 +#define SCSC_INT1_SC0_FINISH 7 +#define SCSC_INT1_SC1_FINISH 8 +#define SCSC_INT1_PC0_FINISH 9 +#define SCSC_INT1_PC1_FINISH 10 +#define SCSC_INT1_CONV4200_FINISH 11 +#define SCSC_INT1_CONV4201_FINISH 12 +#define SCSC_INT1_BCHS0_FINISH 13 +#define SCSC_INT1_BCHS1_FINISH 14 + +#define SCSC_CMDQ_INT_BASE (HW_EVENT_MASK + 64) + +#define SCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN 0 +#define SCSC_CMDQ_INT_PRELOAD_FLUSH 1 +#define SCSC_CMDQ_INT_QUE0_OVERFLOW 2 + +/* clang-format on */ + +#define LWIS_PLATFORM_EVENT_ID_SCSC_FRAME_START \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_FRAME_START) +#define LWIS_PLATFORM_EVENT_ID_SCSC_FRAME_END \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_FRAME_END) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CMDQ_HOLD \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CMDQ_HOLD) +#define LWIS_PLATFORM_EVENT_ID_SCSC_SETTING_DONE \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_SETTING_DONE) +#define LWIS_PLATFORM_EVENT_ID_SCSC_C_LOADER_END \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_C_LOADER_END) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COREX_END0 \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COREX_END0) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COREX_END1 \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COREX_END1) +#define LWIS_PLATFORM_EVENT_ID_SCSC_ROW_COL \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_SCSC_FREEZE_ON_ROW_COL \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_FREEZE_ON_ROW_COL) +#define LWIS_PLATFORM_EVENT_ID_SCSC_TRANS_STOP_DONE \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_TRANS_STOP_DONE) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CMDQ_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CMDQ_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_C_LOADER_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_C_LOADER_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COREX_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COREX_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_OVERFLOW_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_OVERLAP_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO0_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_OVERFLOW_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_OVERLAP_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO1_OVERLAP_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CINFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_CINFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_PIXEL_CNT_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO0_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_INPUT_PROTOCOL_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO0_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO0_OVERFLOW_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO0_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_PIXEL_CNT_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO1_PIXEL_CNT_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_INPUT_PROTOCOL_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO1_INPUT_PROTOCOL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COUTFIFO1_OVERFLOW_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_COUTFIFO1_OVERFLOW_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_VOTF_GLOBAL_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_VOTF_GLOBAL_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_VOTF_LOST_CONNECTION \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_SCSC_OTF_SEQ_ID_ERROR \ + EVENT_ID(SCSC_INT0_BASE, \ + SCSC_INT0_OTF_SEQ_ID_ERROR) + +#define LWIS_PLATFORM_EVENT_ID_SCSC_RDMA_M0_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_RDMA_M0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_WDMA_M0_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_WDMA_M0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_WDMA_M1_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_WDMA_M1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_RDMA_VOTF_LOST_CONNECTION \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_RDMA_VOTF_LOST_CONNECTION) +#define LWIS_PLATFORM_EVENT_ID_SCSC_COMP_DEC_ERROR \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_COMP_DEC_ERROR) +#define LWIS_PLATFORM_EVENT_ID_SCSC_DJAG_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_DJAG_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_SC0_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_SC0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_SC1_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_SC1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_PC0_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_PC0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_PC1_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_PC1_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CONV4200_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_CONV4200_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_CONV4201_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_CONV4201_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_BCHS0_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_BCHS0_FINISH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_BCHS1_FINISH \ + EVENT_ID(SCSC_INT1_BASE, \ + SCSC_INT1_BCHS1_FINISH) + +#define LWIS_PLATFORM_EVENT_ID_SCSC_STOP_CRPT_OFF_CMDQ_EN \ + EVENT_ID(SCSC_CMDQ_INT_BASE, \ + SCSC_CMDQ_INT_STOP_CRPT_OFF_CMDQ_EN) +#define LWIS_PLATFORM_EVENT_ID_SCSC_PRELOAD_FLUSH \ + EVENT_ID(SCSC_CMDQ_INT_BASE, \ + SCSC_CMDQ_INT_PRELOAD_FLUSH) +#define LWIS_PLATFORM_EVENT_ID_SCSC_QUE0_OVERFLOW \ + EVENT_ID(SCSC_CMDQ_INT_BASE, \ + SCSC_CMDQ_INT_QUE0_OVERFLOW) + +#endif /* DT_BINDINGS_LWIS_PLATFORM_GS201_SCSC_H_ */ diff --git a/include/dt-bindings/pci/pci.h b/include/dt-bindings/pci/pci.h index 30937246d831..c2f053c9dd41 100644 --- a/include/dt-bindings/pci/pci.h +++ b/include/dt-bindings/pci/pci.h @@ -17,6 +17,7 @@ #define EP_SAMSUNG_S359 2 #define EP_QC_MODEM 3 #define EP_SAMSUNG_MODEM 4 +#define EP_QC_WIFI 5 /* * CAUTION - It SHOULD fit Target Link Speed Encoding diff --git a/include/dt-bindings/soc/google/exynos-cpif.h b/include/dt-bindings/soc/google/exynos-cpif.h index 7298b73fc384..f8b5745c0b8e 100644 --- a/include/dt-bindings/soc/google/exynos-cpif.h +++ b/include/dt-bindings/soc/google/exynos-cpif.h @@ -32,8 +32,8 @@ #define IPC_RAW 1 #define IPC_RFS 2 #define IPC_MULTI_RAW 3 -#define IPC_BOOT 4 -#define IPC_DUMP 5 +#define IPC_BOOT 4 +#define IPC_DUMP 5 #define IPC_CMD 6 #define IPC_DEBUG 7 #define MAX_DEV_FORMAT 8 @@ -50,9 +50,10 @@ #define INTERRUPT_MAX 2 /* Control msg type */ +#define CMSG_TYPE_NONE 0 #define MAILBOX_SR 1 -#define DRAM_V1 2 -#define DRAM_V2 3 +#define DRAM_V1 2 +#define DRAM_V2 3 #define GPIO 4 #define MAX_CMSG_TYPE 5 @@ -86,45 +87,46 @@ #define SHMEM_IPC 3 #define SHMEM_VPA 4 #define SHMEM_BTL 5 -#define SHMEM_PKTPROC 6 -#define SHMEM_PKTPROC_UL 7 -#define SHMEM_ZMC 8 -#define SHMEM_C2C 9 -#define SHMEM_MSI 10 -#define MAX_CP_SHMEM 11 +#define SHMEM_BTL_EXT 6 +#define SHMEM_PKTPROC 7 +#define SHMEM_PKTPROC_UL 8 +#define SHMEM_ZMC 9 +#define SHMEM_C2C 10 +#define SHMEM_MSI 11 +#define SHMEM_DDM 12 +#define MAX_CP_SHMEM 13 /* TPMON measure */ -#define TPMON_MEASURE_TP 0 -#define TPMON_MEASURE_NETDEV_Q 1 +#define TPMON_MEASURE_TP 0 +#define TPMON_MEASURE_NETDEV_Q 1 #define TPMON_MEASURE_PKTPROC_DL_Q 2 -#define TPMON_MEASURE_DIT_SRC_Q 3 +#define TPMON_MEASURE_DIT_SRC_Q 3 /* TPMON target */ -#define TPMON_TARGET_RPS 0 -#define TPMON_TARGET_GRO 1 -#define TPMON_TARGET_MIF 2 +#define TPMON_TARGET_RPS 0 +#define TPMON_TARGET_GRO 1 +#define TPMON_TARGET_MIF 2 #define TPMON_TARGET_PCIE_LOW_POWER 3 -#define TPMON_TARGET_IRQ_MBOX 4 -#define TPMON_TARGET_IRQ_PCIE 5 -#define TPMON_TARGET_IRQ_DIT 6 -#define TPMON_TARGET_INT_FREQ 7 -#define TPMON_TARGET_BTS 8 -#define TPMON_TARGET_CPU_CL0 9 -#define TPMON_TARGET_CPU_CL1 10 -#define TPMON_TARGET_CPU_CL2 11 -#define TPMON_TARGET_MIF_MAX 12 +#define TPMON_TARGET_IRQ_MBOX 4 +#define TPMON_TARGET_IRQ_PCIE 5 +#define TPMON_TARGET_IRQ_DIT 6 +#define TPMON_TARGET_INT_FREQ 7 +#define TPMON_TARGET_BTS 8 +#define TPMON_TARGET_CPU_CL0 9 +#define TPMON_TARGET_CPU_CL1 10 +#define TPMON_TARGET_CPU_CL2 11 +#define TPMON_TARGET_MIF_MAX 12 #define TPMON_TARGET_INT_FREQ_MAX 13 #define TPMON_TARGET_CPU_CL0_MAX 14 #define TPMON_TARGET_CPU_CL1_MAX 15 #define TPMON_TARGET_CPU_CL2_MAX 16 -#define MAX_TPMON_TARGET 17 +#define MAX_TPMON_TARGET 17 /* Protocol for TPMON */ -#define TPMON_PROTO_ALL 0 -#define TPMON_PROTO_TCP 1 -#define TPMON_PROTO_UDP 2 +#define TPMON_PROTO_ALL 0 +#define TPMON_PROTO_TCP 1 +#define TPMON_PROTO_UDP 2 #define TPMON_PROTO_OTHERS 3 -#define MAX_TPMON_PROTO 4 /* Link device attr */ #define LINK_ATTR_SBD_IPC (0x1 << 0) /* IPC over SBD (from MIPI-LLI) */ @@ -139,22 +141,25 @@ #define LINK_ATTR_DUMP_ALIGNED (0x1 << 9) /* DUMP with 4-bytes alignment */ #define LINK_ATTR_XMIT_BTDLR (0x1 << 10) /* Used to download CP bootloader */ #define LINK_ATTR_XMIT_BTDLR_SPI (0x1 << 11) /* Download CP bootloader by SPI */ +#define LINK_ATTR_XMIT_BTDLR_PCIE (0x1 << 12) /* CP ROM booting via PCIe */ /* IO device attr */ #define IO_ATTR_SIPC4 (0x1 << 0) #define IO_ATTR_SIPC5 (0x1 << 1) -#define IO_ATTR_CDC_NCM (0x1 << 2) +#define IO_ATTR_CDC_NCM (0x1 << 2) #define IO_ATTR_MULTIFMT (0x1 << 3) #define IO_ATTR_HANDOVER (0x1 << 4) #define IO_ATTR_LEGACY_RFS (0x1 << 5) #define IO_ATTR_RX_FRAGMENT (0x1 << 6) -#define IO_ATTR_SBD_IPC (0x1 << 7) /* IPC using SBD designed from MIPI-LLI */ +#define IO_ATTR_SBD_IPC (0x1 << 7) /* IPC using SBD designed from MIPI-LLI */ #define IO_ATTR_NO_LINK_HEADER (0x1 << 8) /* Link-layer header is not needed */ #define IO_ATTR_NO_CHECK_MAXQ (0x1 << 9) /* no need to check rxq overflow condition */ -#define IO_ATTR_DUALSIM (0x1 << 10) /* support Dual SIM */ +#define IO_ATTR_DUALSIM (0x1 << 10) /* support Dual SIM */ #define IO_ATTR_OPTION_REGION (0x1 << 11) /* region & operator info */ +/* Deprecated */ #define IO_ATTR_ZEROCOPY (0x1 << 12) /* support SW zerocopy on SBD */ #define IO_ATTR_MULTI_CH (0x1 << 13) /* Multi channel IO device */ +#define IO_ATTR_STATE_RESET_NOTI (0x1 << 14) /* Receive CP reset state noti */ /* SIPC channel ID */ #define SIPC_CH_ID_RAW_0 0 @@ -183,20 +188,22 @@ #define SIPC_CH_ID_PDP_12 22 #define SIPC_CH_ID_PDP_13 23 #define SIPC_CH_ID_PDP_14 24 - #define SIPC_CH_ID_BT_DUN 25 #define SIPC_CH_ID_CIQ_DATA 26 - #define SIPC_CH_ID_PDP_17 27 - #define SIPC_CH_ID_CPLOG1 28 #define SIPC_CH_ID_CPLOG2 29 #define SIPC_CH_ID_LOOPBACK1 30 #define SIPC_CH_ID_LOOPBACK2 31 -#define SIPC_CH_ID_SMD4 33 +#define SIPC_CH_ID_SMD4 33 + +#define SIPC_CH_ID_CASS 35 -#define SIPC_CH_ID_CASS 35 +/* 0 ... 30 */ +#define SIPC_CH_EX_ID_PDP_0 181 +#define SIPC_CH_EX_ID_PDP_30 (SIPC_CH_EX_ID_PDP_0 + 30) +#define SIPC_CH_EX_ID_PDP_MAX SIPC_CH_EX_ID_PDP_30 #define SIPC5_CH_ID_BOOT_0 215 #define SIPC5_CH_ID_BOOT_1 216 @@ -242,7 +249,7 @@ #define SIPC5_CH_ID_RFS_8 253 #define SIPC5_CH_ID_RFS_9 254 -#define SIPC5_CH_ID_MAX 255 +#define SIPC5_CH_ID_MAX 255 /* SIT channel ID */ #define EXYNOS_CH_ID_MULTIPDP 0 @@ -299,37 +306,9 @@ #define EXYNOS_CH_ID_OEM_6 135 /* oem_ipc6 */ #define EXYNOS_CH_ID_OEM_7 136 /* oem_ipc7 */ +/* 0 ... 30 */ #define EXYNOS_CH_EX_ID_PDP_0 181 -#define EXYNOS_CH_EX_ID_PDP_1 182 -#define EXYNOS_CH_EX_ID_PDP_2 183 -#define EXYNOS_CH_EX_ID_PDP_3 184 -#define EXYNOS_CH_EX_ID_PDP_4 185 -#define EXYNOS_CH_EX_ID_PDP_5 186 -#define EXYNOS_CH_EX_ID_PDP_6 187 -#define EXYNOS_CH_EX_ID_PDP_7 188 -#define EXYNOS_CH_EX_ID_PDP_8 189 -#define EXYNOS_CH_EX_ID_PDP_9 190 -#define EXYNOS_CH_EX_ID_PDP_10 191 -#define EXYNOS_CH_EX_ID_PDP_11 192 -#define EXYNOS_CH_EX_ID_PDP_12 193 -#define EXYNOS_CH_EX_ID_PDP_13 194 -#define EXYNOS_CH_EX_ID_PDP_14 195 -#define EXYNOS_CH_EX_ID_PDP_15 196 -#define EXYNOS_CH_EX_ID_PDP_16 197 -#define EXYNOS_CH_EX_ID_PDP_17 198 -#define EXYNOS_CH_EX_ID_PDP_18 199 -#define EXYNOS_CH_EX_ID_PDP_19 200 -#define EXYNOS_CH_EX_ID_PDP_20 201 -#define EXYNOS_CH_EX_ID_PDP_21 202 -#define EXYNOS_CH_EX_ID_PDP_22 203 -#define EXYNOS_CH_EX_ID_PDP_23 204 -#define EXYNOS_CH_EX_ID_PDP_24 205 -#define EXYNOS_CH_EX_ID_PDP_25 206 -#define EXYNOS_CH_EX_ID_PDP_26 207 -#define EXYNOS_CH_EX_ID_PDP_27 208 -#define EXYNOS_CH_EX_ID_PDP_28 209 -#define EXYNOS_CH_EX_ID_PDP_29 210 -#define EXYNOS_CH_EX_ID_PDP_30 211 +#define EXYNOS_CH_EX_ID_PDP_30 (EXYNOS_CH_EX_ID_PDP_0 + 30) #define EXYNOS_CH_EX_ID_PDP_MAX EXYNOS_CH_EX_ID_PDP_30 #define EXYNOS_CH_ID_BOOT 241 diff --git a/include/dt-bindings/soc/google/gs101-bts.h b/include/dt-bindings/soc/google/gs-bts.h similarity index 100% rename from include/dt-bindings/soc/google/gs101-bts.h rename to include/dt-bindings/soc/google/gs-bts.h diff --git a/include/dt-bindings/soc/google/gs201-devfreq.h b/include/dt-bindings/soc/google/gs201-devfreq.h new file mode 100644 index 000000000000..4a4cded07051 --- /dev/null +++ b/include/dt-bindings/soc/google/gs201-devfreq.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2021 Google, LLC. + * + * Device Tree binding constants for GS201 devfreq + */ + +#ifndef _DT_BINDINGS_GS_201_DEVFREQ_H +#define _DT_BINDINGS_GS_201_DEVFREQ_H +/* DEVFREQ TYPE LIST */ +#define DEVFREQ_MIF 0 +#define DEVFREQ_INT 1 +#define DEVFREQ_DISP 2 +#define DEVFREQ_CAM 3 +#define DEVFREQ_INTCAM 4 +#define DEVFREQ_TNR 5 +#define DEVFREQ_MFC 6 +#define DEVFREQ_BO 7 +#define DEVFREQ_TYPE_END 9 + +/* ESS FLAG LIST */ +#define ESS_FLAG_INT 3 +#define ESS_FLAG_MIF 4 +#define ESS_FLAG_ISP 5 +#define ESS_FLAG_DISP 6 +#define ESS_FLAG_INTCAM 7 +#define ESS_FLAG_TPU 8 +#define ESS_FLAG_TNR 9 +#define ESS_FLAG_MFC 10 +#define ESS_FLAG_BO 11 + +/* DEVFREQ GOV TYPE */ +#define SIMPLE_INTERACTIVE 0 +#define MEM_LATENCY 1 + +#endif diff --git a/include/dt-bindings/soc/google/gs201-dm.h b/include/dt-bindings/soc/google/gs201-dm.h new file mode 100644 index 000000000000..6ac3f1e1d206 --- /dev/null +++ b/include/dt-bindings/soc/google/gs201-dm.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Google, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for GS201 + */ + +#ifndef _DT_BINDINGS_GS_201_H +#define _DT_BINDINGS_GS_201_H + +/* NUMBER FOR DVFS MANAGER */ +#define DM_CPU_CL0 0 +#define DM_CPU_CL1 1 +#define DM_CPU_CL2 2 +#define DM_MIF 3 +#define DM_INT 4 +#define DM_INTCAM 5 +#define DM_CAM 6 +#define DM_TPU 7 +#define DM_TNR 8 +#define DM_DISP 9 +#define DM_MFC 10 +#define DM_BO 11 + +/* CONSTRAINT TYPE */ +#define CONSTRAINT_MIN 0 +#define CONSTRAINT_MAX 1 + +#endif /* _DT_BINDINGS_GS_201_H */ diff --git a/include/dt-bindings/soc/google/gs201-pm-qos.h b/include/dt-bindings/soc/google/gs201-pm-qos.h new file mode 100644 index 000000000000..a655d9b15e43 --- /dev/null +++ b/include/dt-bindings/soc/google/gs201-pm-qos.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Google, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for GS201 + */ + +#ifndef _DT_BINDINGS_GS201_PM_QOS_H +#define _DT_BINDINGS_GS201_PM_QOS_H + +/* EXYNOS_PM_QOS CLASSES IDS */ +#define PM_QOS_CLUSTER0_FREQ_MIN (1) +#define PM_QOS_CLUSTER0_FREQ_MAX (2) +#define PM_QOS_CLUSTER1_FREQ_MIN (3) +#define PM_QOS_CLUSTER1_FREQ_MAX (4) +#define PM_QOS_CLUSTER2_FREQ_MIN (5) +#define PM_QOS_CLUSTER2_FREQ_MAX (6) +#define PM_QOS_DEVICE_THROUGHPUT (7) +#define PM_QOS_INTCAM_THROUGHPUT (8) +#define PM_QOS_DEVICE_THROUGHPUT_MAX (9) +#define PM_QOS_INTCAM_THROUGHPUT_MAX (10) +#define PM_QOS_BUS_THROUGHPUT (11) +#define PM_QOS_BUS_THROUGHPUT_MAX (12) +#define PM_QOS_DISPLAY_THROUGHPUT (13) +#define PM_QOS_DISPLAY_THROUGHPUT_MAX (14) +#define PM_QOS_CAM_THROUGHPUT (15) +#define PM_QOS_CAM_THROUGHPUT_MAX (16) +#define PM_QOS_MFC_THROUGHPUT (17) +#define PM_QOS_MFC_THROUGHPUT_MAX (18) +#define PM_QOS_TNR_THROUGHPUT (19) +#define PM_QOS_TNR_THROUGHPUT_MAX (20) +#define PM_QOS_BO_THROUGHPUT (21) +#define PM_QOS_BO_THROUGHPUT_MAX (22) +#define PM_QOS_GPU_THROUGHPUT_MIN (23) +#define PM_QOS_GPU_THROUGHPUT_MAX (24) +#define EXYNOS_PM_QOS_NUM_CLASSES (25) +#endif diff --git a/include/dt-bindings/sound/google-aoc.h b/include/dt-bindings/sound/google-aoc.h index b233b0cd40dd..7cf3c9f05d89 100644 --- a/include/dt-bindings/sound/google-aoc.h +++ b/include/dt-bindings/sound/google-aoc.h @@ -40,7 +40,8 @@ #define IDX_HAPTIC_NoHOST_RX 0x20000011 #define IDX_US_RX 0x13 #define IDX_INCALL_PB2_RX 0x14 -#define IDX_IMSV_RX 0x15 +#define IDX_IMSV_RX 0x15 +#define IDX_CAP_INJ_RX 0x16 #define IDX_EP1_TX 0x40000000 #define IDX_EP2_TX 0x40000001 diff --git a/include/linux/exynos-pci-noti.h b/include/linux/exynos-pci-noti.h index e21343506007..b329e0272b66 100644 --- a/include/linux/exynos-pci-noti.h +++ b/include/linux/exynos-pci-noti.h @@ -16,6 +16,7 @@ enum exynos_pcie_event { EXYNOS_PCIE_EVENT_WAKEUP = 0x4, EXYNOS_PCIE_EVENT_WAKE_RECOVERY = 0x8, EXYNOS_PCIE_EVENT_NO_ACCESS = 0x10, + EXYNOS_PCIE_EVENT_CPL_TIMEOUT = 0x20, }; enum exynos_pcie_trigger { diff --git a/include/linux/f2fs_fs.h b/include/linux/f2fs_fs.h index d445150c5350..5dd1e52b8997 100644 --- a/include/linux/f2fs_fs.h +++ b/include/linux/f2fs_fs.h @@ -73,6 +73,20 @@ struct f2fs_device { __le32 total_segments; } __packed; +/* reason of stop_checkpoint */ +enum stop_cp_reason { + STOP_CP_REASON_SHUTDOWN, + STOP_CP_REASON_FAULT_INJECT, + STOP_CP_REASON_META_PAGE, + STOP_CP_REASON_WRITE_FAIL, + STOP_CP_REASON_CORRUPTED_SUMMARY, + STOP_CP_REASON_UPDATE_INODE, + STOP_CP_REASON_FLUSH_FAIL, + STOP_CP_REASON_MAX, +}; + +#define MAX_STOP_REASON 32 + struct f2fs_super_block { __le32 magic; /* Magic Number */ __le16 major_ver; /* Major Version */ @@ -116,7 +130,8 @@ struct f2fs_super_block { __u8 hot_ext_count; /* # of hot file extension */ __le16 s_encoding; /* Filename charset encoding */ __le16 s_encoding_flags; /* Filename charset encoding flags */ - __u8 reserved[306]; /* valid reserved region */ + __u8 s_stop_reason[MAX_STOP_REASON]; /* stop checkpoint reason */ + __u8 reserved[274]; /* valid reserved region */ __le32 crc; /* checksum of superblock */ } __packed; diff --git a/include/linux/fbcon.h b/include/linux/fbcon.h index ff5596dd30f8..2382dec6d6ab 100644 --- a/include/linux/fbcon.h +++ b/include/linux/fbcon.h @@ -15,6 +15,8 @@ void fbcon_new_modelist(struct fb_info *info); void fbcon_get_requirement(struct fb_info *info, struct fb_blit_caps *caps); void fbcon_fb_blanked(struct fb_info *info, int blank); +int fbcon_modechange_possible(struct fb_info *info, + struct fb_var_screeninfo *var); void fbcon_update_vcs(struct fb_info *info, bool all); void fbcon_remap_all(struct fb_info *info); int fbcon_set_con2fb_map_ioctl(void __user *argp); @@ -33,6 +35,8 @@ static inline void fbcon_new_modelist(struct fb_info *info) {} static inline void fbcon_get_requirement(struct fb_info *info, struct fb_blit_caps *caps) {} static inline void fbcon_fb_blanked(struct fb_info *info, int blank) {} +static inline int fbcon_modechange_possible(struct fb_info *info, + struct fb_var_screeninfo *var) { return 0; } static inline void fbcon_update_vcs(struct fb_info *info, bool all) {} static inline void fbcon_remap_all(struct fb_info *info) {} static inline int fbcon_set_con2fb_map_ioctl(void __user *argp) { return 0; } diff --git a/include/linux/freezer.h b/include/linux/freezer.h index f753c307b8b3..181aac4b5187 100644 --- a/include/linux/freezer.h +++ b/include/linux/freezer.h @@ -8,6 +8,9 @@ #include #include #include +#if defined(CONFIG_ARM64) && !defined(__GENKSYMS__) +#include +#endif #ifdef CONFIG_FREEZER extern atomic_t system_freezing_cnt; /* nr of freezing conds in effect */ @@ -108,10 +111,15 @@ static inline bool cgroup_freezing(struct task_struct *task) * The caller shouldn't do anything which isn't allowed for a frozen task * until freezer_cont() is called. Usually, freezer[_do_not]_count() pair * wrap a scheduling operation and nothing much else. + * + * The write to current->flags uses release semantics to prevent a concurrent + * freezer_should_skip() from observing this write before a write to on_rq + * during a prior call to activate_task(), which may cause it to return true + * before deactivate_task() is called. */ static inline void freezer_do_not_count(void) { - current->flags |= PF_FREEZER_SKIP; + smp_store_release(¤t->flags, current->flags | PF_FREEZER_SKIP); } /** @@ -161,7 +169,19 @@ static inline bool freezer_should_skip(struct task_struct *p) * clearing %PF_FREEZER_SKIP. */ smp_mb(); +#ifdef CONFIG_ARM64 + return (p->flags & PF_FREEZER_SKIP) && + (!p->on_rq || task_cpu_possible_mask(p) == cpu_possible_mask); +#else + /* + * On non-aarch64, avoid depending on task_cpu_possible_mask(), which is + * defined in , because including that header from + * here exposes a tricky bug in the tracepoint headers on x86, and that + * macro would end up being defined equal to cpu_possible_mask on other + * architectures anyway. + */ return p->flags & PF_FREEZER_SKIP; +#endif } /* diff --git a/include/linux/gsa/gsa_image_auth.h b/include/linux/gsa/gsa_image_auth.h new file mode 100644 index 000000000000..62a6ead5c0b7 --- /dev/null +++ b/include/linux/gsa/gsa_image_auth.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (C) 2022 Google LLC + */ +#ifndef __LINUX_GSA_IMAGE_AUTH_H +#define __LINUX_GSA_IMAGE_AUTH_H + +#include +#include + +/* + * GSA Image authentication interface + */ + +/** + * gsp_authenticate_image() - authenticate a generic binary image + * @gsa: pointer to GSA &struct device + * @img_hdr: dma address of image meta information + * @img_body: physical address of image body + * + * This routine authenticates the binary image specified by + * @img_hdr/@img_body parameters. + * + * The binary image consists of two parts: a header (always 4K in size) + * containing image meta information (including authentication parameters and + * loading instructions) and image body which contains the image itself. The + * image header must be loaded into memory region allocated by calling + * dma_alloc_coherent() for GSA device. This memory chunk can be discarded + * after gsa_authenticate_image() call is complete. Image body should + * be loaded into physically contiguous memory region. + * + * Return: 0 on success, negative error otherwise + */ +int gsa_authenticate_image(struct device *gsa, dma_addr_t img_meta, phys_addr_t img_body); + +#endif /* __LINUX_GSA_IMAGE_AUTH_H */ diff --git a/include/linux/kernel-top.h b/include/linux/kernel-top.h new file mode 100644 index 000000000000..f4a205bccd9a --- /dev/null +++ b/include/linux/kernel-top.h @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* include/linux/kernel-top.h + * + * Copyright (C) 2022 Google, Inc. + */ + +#ifndef _LINUX_KERNEL_TOP_FUNC_H +#define _LINUX_KERNEL_TOP_FUNC_H + +struct kernel_top_context; + +#if IS_ENABLED(CONFIG_KERNEL_TOP) +extern void kernel_top_print(struct kernel_top_context *cxt); +extern int kernel_top_init(struct device *dev, struct kernel_top_context **pcxt); +extern void kernel_top_reset(struct kernel_top_context *cxt); +extern void kernel_top_destroy(struct kernel_top_context *cxt); +#else +static inline void kernel_top_print(struct kernel_top_context *cxt) +{ +} + +static inline int kernel_top_init(struct device *dev, struct kernel_top_context **pcxt) +{ + return -EINVAL; +} + +static inline void kernel_top_reset(struct kernel_top_context *cxt) +{ +} + +static inline void kernel_top_destroy(struct kernel_top_context *cxt) +{ +} +#endif /* CONFIG_KERNEL_TOP */ + +#endif /* _LINUX_KERNEL_TOP_FUNC_H */ diff --git a/include/linux/keydebug-func.h b/include/linux/keydebug-func.h deleted file mode 100644 index 035ad7d3fa57..000000000000 --- a/include/linux/keydebug-func.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * include/linux/keydebug-func.h - function and structure for debug - * functions used by keydebug driver - * - * Copyright (C) 2018 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _LINUX_KEYDEBUG_FUNC_H -#define _LINUX_KEYDEBUG_FUNC_H - -void kernel_top_monitor(void); -void kernel_top_init(void); -void kernel_top_exit(void); - -#endif /* _LINUX_KEYDEBUG_FUNC_H */ diff --git a/include/linux/keydebug.h b/include/linux/keydebug.h index c16b8ef46b94..47f75510a4a4 100644 --- a/include/linux/keydebug.h +++ b/include/linux/keydebug.h @@ -27,6 +27,7 @@ struct keydebug_platform_data { struct delayed_work delayed_work; bool keydebug_requested; int s2d_state_backup; + struct kernel_top_context *ktop; }; void keydebug_register_s2d_ops(void *get, void *set); diff --git a/include/linux/mfd/samsung/rtc-s2mpg12.h b/include/linux/mfd/samsung/rtc-s2mpg12.h new file mode 100644 index 000000000000..27dc1d7b33c3 --- /dev/null +++ b/include/linux/mfd/samsung/rtc-s2mpg12.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * rtc-s2mpg12.h + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * http://www.samsung.com + */ + +#ifndef __LINUX_MFD_SEC_RTC_H +#define __LINUX_MFD_SEC_RTC_H + +/* RTC(0x2) Registers */ +enum S2MPG12_RTC_REG { + S2MPG12_RTC_CTRL = 0x0, + S2MPG12_RTC_UPDATE = 0x1, + S2MPG12_RTC_SMPL = 0x2, + S2MPG12_RTC_WTSR = 0x3, + S2MPG12_RTC_CAPSEL = 0x4, + S2MPG12_RTC_MSEC = 0x5, + S2MPG12_RTC_SEC = 0x6, + S2MPG12_RTC_MIN = 0x7, + S2MPG12_RTC_HOUR = 0x8, + S2MPG12_RTC_WEEK = 0x9, + S2MPG12_RTC_DAY = 0xA, + S2MPG12_RTC_MON = 0xB, + S2MPG12_RTC_YEAR = 0xC, + S2MPG12_RTC_A0SEC = 0xD, + S2MPG12_RTC_A0MIN = 0xE, + S2MPG12_RTC_A0HOUR = 0xF, + S2MPG12_RTC_A0WEEK = 0x10, + S2MPG12_RTC_A0DAY = 0x11, + S2MPG12_RTC_A0MON = 0x12, + S2MPG12_RTC_A0YEAR = 0x13, + S2MPG12_RTC_A1SEC = 0x14, + S2MPG12_RTC_A1MIN = 0x15, + S2MPG12_RTC_A1HOUR = 0x16, + S2MPG12_RTC_A1WEEK = 0x17, + S2MPG12_RTC_A1DAY = 0x18, + S2MPG12_RTC_A1MON = 0x19, + S2MPG12_RTC_A1YEAR = 0x1A, + S2MPG12_RTC_OSCCTRL = 0x1B, + S2MPG12_RTC_NONCE0_0 = 0x1C, + S2MPG12_RTC_NONCE0_1 = 0x1D, + S2MPG12_RTC_NONCE0_2 = 0x1E, + S2MPG12_RTC_NONCE0_3 = 0x1F, + S2MPG12_RTC_NONCE0_4 = 0x20, + S2MPG12_RTC_NONCE0_5 = 0x21, + S2MPG12_RTC_NONCE0_6 = 0x22, + S2MPG12_RTC_NONCE0_7 = 0x23, + S2MPG12_RTC_NONCE1_0 = 0x24, + S2MPG12_RTC_NONCE1_1 = 0x25, + S2MPG12_RTC_NONCE1_2 = 0x26, + S2MPG12_RTC_NONCE1_3 = 0x27, + S2MPG12_RTC_NONCE1_4 = 0x28, + S2MPG12_RTC_NONCE1_5 = 0x29, + S2MPG12_RTC_NONCE1_6 = 0x2A, + S2MPG12_RTC_NONCE1_7 = 0x2B, + S2MPG12_RTC_SCRATCH0 = 0x2C, + S2MPG12_RTC_SCRATCH1 = 0x2D, + S2MPG12_RTC_SCRATCH2 = 0x2E, + S2MPG12_RTC_SCRATCH3 = 0x2F, + S2MPG12_RTC_SCRATCH4 = 0x30, +}; + +/* RTC Control Register */ +#define BCD_EN_SHIFT 0 +#define MODEL24_SHIFT 1 + +/* RTC Update Register */ +#define RTC_RUDR_SHIFT 0 +#define RTC_WUDR_SHIFT 1 +#define RTC_FREEZE_SHIFT 2 +#define RTC_AUDR_SHIFT 4 + +/* RTC SMPL Register */ +#define SMPLT_SHIFT 1 +#define SMPLT_MASK (0x7 << SMPLT_SHIFT) +#define SMPL_EN_SHIFT 0 +#define SMPL_EN_MASK (0x1 << SMPL_EN_SHIFT) + +/* RTC WTSR Register */ +#define WTSRT_SHIFT 1 +#define WTSRT_MASK (0x7 << WTSRT_SHIFT) +#define WTSR_EN_SHIFT 0 +#define WTSR_EN_MASK (0x1 << WTSR_EN_SHIFT) +#define COLDRST_EN_SHIFT 4 +#define COLDRST_EN_MASK (0x1 << COLDRST_EN_SHIFT) +#define COLDRST_TIMER_SHIFT 5 +#define COLDRST_TIMER_MASK (0x3 << COLDRST_TIMER_SHIFT) + +/* RTC HOUR Register */ +#define HOUR_PM_SHIFT 6 + +/* RTC Alarm Enable */ +#define ALARM_ENABLE_SHIFT 7 + +/* PM STATUS2 Register */ +#define RTCA0E_SHIFT 2 +#define RTCA1E_SHIFT 1 + +#define WTSR_TIMER_BITS(v) (((v) << WTSRT_SHIFT) & WTSRT_MASK) +#define SMPL_TIMER_BITS(v) (((v) << SMPLT_SHIFT) & SMPLT_MASK) + +/* RTC Optimize */ +#define CAP_SEL_SHIFT 0 +#define CAP_SEL_MASK (0x3 << CAP_SEL_SHIFT) +#define OSC_BIAS_UP_SHIFT 2 +#define OSC_XIN_SHIFT 5 +#define OSC_XIN_MASK (0x7 << OSC_XIN_SHIFT) +#define OSC_XOUT_SHIFT 2 +#define OSC_XOUT_MASK (0x7 << OSC_XOUT_SHIFT) + +#define NONCE0_CNT 8 +#define NONCE0_0_SPECIAL_VAL 222 /* Can be anything except 0 */ + +struct s2m_rtc_info { + struct device *dev; + struct i2c_client *i2c; + struct i2c_client *pmic_i2c; + struct s2mpg12_dev *iodev; + struct rtc_device *rtc_dev; + + /* mutex for RTC */ + struct mutex lock; + struct delayed_work irq_work; + int alarm0_irq; + + bool use_irq; + bool wtsr_en; + bool coldrst_en; + bool smpl_en; + bool alarm_enabled; + u8 update_reg; + bool use_alarm_workaround; + bool alarm_check; + u8 wudr_mask; + u8 audr_mask; +}; + +/* RTC Counter Register offsets */ +#ifdef CONFIG_RTC_DRV_S2MP +enum { + RTC_SEC = 0, + RTC_MIN, + RTC_HOUR, + RTC_WEEKDAY, + RTC_DATE, + RTC_MONTH, + RTC_YEAR, + NR_RTC_CNT_REGS, +}; +#else +enum { + /* RTC_MSEC = 0, */ + RTC_SEC = 0, + RTC_MIN, + RTC_HOUR, + RTC_WEEKDAY, + RTC_DATE, + RTC_MONTH, + RTC_YEAR, + NR_RTC_CNT_REGS, +}; +#endif + +enum S2M_RTC_OP { + S2M_RTC_READ, + S2M_RTC_WRITE_TIME, + S2M_RTC_WRITE_ALARM, +}; + +#endif /* __LINUX_MFD_SEC_RTC_H */ diff --git a/include/linux/mfd/samsung/s2mpg10-meter.h b/include/linux/mfd/samsung/s2mpg10-meter.h index 150807221062..d30b4d35cb3e 100644 --- a/include/linux/mfd/samsung/s2mpg10-meter.h +++ b/include/linux/mfd/samsung/s2mpg10-meter.h @@ -25,15 +25,13 @@ struct s2mpg10_meter { }; /* Public s2mpg10 Meter functions */ -int s2mpg10_meter_load_measurement(struct s2mpg10_meter *s2mpg10, - s2mpg1x_meter_mode mode, u64 *data, - u32 *count, u64 *timestamp_capture); int s2mpg10_meter_set_muxsel(struct s2mpg10_meter *s2mpg10, int channel, s2mpg1x_meter_muxsel m); int s2mpg10_meter_onoff(struct s2mpg10_meter *s2mpg10, bool onoff); int s2mpg10_ext_meter_onoff(struct s2mpg10_meter *s2mpg10, bool onoff); u32 s2mpg10_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m); +u32 s2mpg10_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m); void s2mpg10_meter_read_lpf_data_reg(struct s2mpg10_meter *s2mpg10, u32 *data); #endif /* __LINUX_MFD_S2MPG10_METER_H */ diff --git a/include/linux/mfd/samsung/s2mpg10.h b/include/linux/mfd/samsung/s2mpg10.h index 339e7c06ed36..bbd2ebb5b517 100644 --- a/include/linux/mfd/samsung/s2mpg10.h +++ b/include/linux/mfd/samsung/s2mpg10.h @@ -120,6 +120,8 @@ struct s2mpg10_platform_data { int cap_sel; int osc_xin; int osc_xout; + + void *meter; }; struct s2mpg10_dev { diff --git a/include/linux/mfd/samsung/s2mpg11-meter.h b/include/linux/mfd/samsung/s2mpg11-meter.h index 30dc18f99b03..db1bc6433856 100644 --- a/include/linux/mfd/samsung/s2mpg11-meter.h +++ b/include/linux/mfd/samsung/s2mpg11-meter.h @@ -28,15 +28,13 @@ struct s2mpg11_meter { }; /* Public s2mpg11 Meter functions */ -int s2mpg11_meter_load_measurement(struct s2mpg11_meter *s2mpg11, - s2mpg1x_meter_mode mode, u64 *data, - u32 *count, u64 *timestamp_capture); int s2mpg11_meter_set_muxsel(struct s2mpg11_meter *s2mpg11, int channel, s2mpg1x_meter_muxsel m); int s2mpg11_meter_onoff(struct s2mpg11_meter *s2mpg11, bool onoff); int s2mpg11_ext_meter_onoff(struct s2mpg11_meter *s2mpg11, bool onoff); u32 s2mpg11_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m); +u32 s2mpg11_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m); void s2mpg11_meter_read_lpf_data_reg(struct s2mpg11_meter *s2mpg11, u32 *data); #endif /* __LINUX_MFD_S2MPG11_METER_H */ diff --git a/include/linux/mfd/samsung/s2mpg11.h b/include/linux/mfd/samsung/s2mpg11.h index b4c63befbbb6..d6847d99d4d2 100644 --- a/include/linux/mfd/samsung/s2mpg11.h +++ b/include/linux/mfd/samsung/s2mpg11.h @@ -83,6 +83,8 @@ struct s2mpg11_platform_data { unsigned int buck_ocp_ctrl5; unsigned int buck_ocp_ctrl6; unsigned int buck_ocp_ctrl7; + + void *meter; }; struct s2mpg11_dev { diff --git a/include/linux/mfd/samsung/s2mpg12-meter.h b/include/linux/mfd/samsung/s2mpg12-meter.h new file mode 100644 index 000000000000..798ac22326be --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg12-meter.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg12-meter.h + * + * Copyright (C) 2015 Samsung Electronics + * + * header file including meter information of s2mpg12 + */ + +#ifndef __LINUX_MFD_S2MPG12_METER_H +#define __LINUX_MFD_S2MPG12_METER_H + +#include "s2mpg12-register.h" + +struct s2mpg12_meter { + struct s2mpg12_dev *iodev; + struct i2c_client *i2c; + + /* mutex for s2mpg12 meter */ + struct mutex meter_lock; + u8 meter_en; + u8 ext_meter_en; + u8 chg_mux_sel[S2MPG1X_METER_CHANNEL_MAX]; + u32 lpf_data[S2MPG1X_METER_CHANNEL_MAX]; /* 21-bit data */ + struct device *dev; +}; + +/* Public s2mpg12 Meter functions */ +int s2mpg12_meter_set_muxsel(struct s2mpg12_meter *s2mpg12, int channel, + s2mpg1x_meter_muxsel m); + +int s2mpg12_meter_onoff(struct s2mpg12_meter *s2mpg12, bool onoff); +int s2mpg12_ext_meter_onoff(struct s2mpg12_meter *s2mpg12, bool onoff); +u32 s2mpg12_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m); +u32 s2mpg12_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m); +void s2mpg12_meter_read_lpf_data_reg(struct s2mpg12_meter *s2mpg12, + u32 *data); + +#endif /* __LINUX_MFD_S2MPG12_METER_H */ diff --git a/include/linux/mfd/samsung/s2mpg12-register.h b/include/linux/mfd/samsung/s2mpg12-register.h new file mode 100644 index 000000000000..4a306a505f88 --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg12-register.h @@ -0,0 +1,625 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg12-register.h + * + * Copyright (C) 2015 Samsung Electronics + * + * header file including register information of s2mpg12 + */ + +#ifndef __LINUX_MFD_S2MPG12_REGISTER_H +#define __LINUX_MFD_S2MPG12_REGISTER_H + +#include +#include "s2mpg1x-register.h" + +#define S2MPG12_REG_INVALID (0xFF) + +enum S2MPG12_pmic_rev { + S2MPG12_EVT0, + S2MPG12_EVT1, +}; + +/* Common(0x0) Registers */ +enum S2MPG12_COMMON_REG { + S2MPG12_COMMON_VGPIO0 = 0x0, + S2MPG12_COMMON_VGPIO1 = 0x1, + S2MPG12_COMMON_VGPIO2 = 0x2, + S2MPG12_COMMON_VGPIO3 = 0x3, + S2MPG12_COMMON_I3C_DAA = 0x4, + S2MPG12_COMMON_IBI0 = 0x5, + S2MPG12_COMMON_IBI1 = 0x6, + S2MPG12_COMMON_IBI2 = 0x7, + S2MPG12_COMMON_IBI3 = 0x8, + S2MPG12_COMMON_CHIPID = 0xB, + S2MPG12_COMMON_I3C_CFG1 = 0xC, + S2MPG12_COMMON_I3C_CFG2 = 0xD, + S2MPG12_COMMON_I3C_STA = 0xE, + S2MPG12_COMMON_IBIM1 = 0xF, + S2MPG12_COMMON_IBIM2 = 0x10, +}; + +/* PM(0x1) Registers */ +enum S2MPG12_PM_REG { + S2MPG12_PM_INT1 = 0x0, + S2MPG12_PM_INT2 = 0x1, + S2MPG12_PM_INT3 = 0x2, + S2MPG12_PM_INT4 = 0x3, + S2MPG12_PM_INT5 = 0x4, + S2MPG12_PM_INT1M = 0x5, + S2MPG12_PM_INT2M = 0x6, + S2MPG12_PM_INT3M = 0x7, + S2MPG12_PM_INT4M = 0x8, + S2MPG12_PM_INT5M = 0x9, + S2MPG12_PM_STATUS1 = 0xA, + S2MPG12_PM_STATUS2 = 0xB, + S2MPG12_PM_PWRONSRC = 0xC, + S2MPG12_PM_OFFSRC1 = 0xD, + S2MPG12_PM_OFFSRC2 = 0xE, + S2MPG12_PM_BUCHG = 0xF, + S2MPG12_PM_RTCBUF = 0x10, + S2MPG12_PM_CTRL1 = 0x11, + S2MPG12_PM_CTRL2 = 0x12, + S2MPG12_PM_CTRL3 = 0x13, + S2MPG12_PM_CTRL4 = 0x14, + S2MPG12_PM_CTRL5 = 0x15, + S2MPG12_PM_SMPL_WARN_CTRL = 0x16, + S2MPG12_PM_B1M_CTRL = 0x17, + S2MPG12_PM_B1M_OUT1 = 0x18, + S2MPG12_PM_B2M_CTRL = 0x19, + S2MPG12_PM_B2M_OUT1 = 0x1A, + S2MPG12_PM_B3M_CTRL = 0x1B, + S2MPG12_PM_B3M_OUT1 = 0x1C, + S2MPG12_PM_B4M_CTRL = 0x1D, + S2MPG12_PM_B4M_OUT1 = 0x1E, + S2MPG12_PM_B5M_CTRL = 0x1F, + S2MPG12_PM_B5M_OUT1 = 0x20, + S2MPG12_PM_B6M_CTRL = 0x21, + S2MPG12_PM_B6M_OUT1 = 0x22, + S2MPG12_PM_B7M_CTRL = 0x23, + S2MPG12_PM_B7M_OUT1 = 0x24, + S2MPG12_PM_B8M_CTRL = 0x25, + S2MPG12_PM_B8M_OUT1 = 0x26, + S2MPG12_PM_B9M_CTRL = 0x27, + S2MPG12_PM_B9M_OUT1 = 0x28, + S2MPG12_PM_B10M_CTRL = 0x29, + S2MPG12_PM_B10M_OUT1 = 0x2A, + S2MPG12_PM_L1M_CTRL = 0x2B, + S2MPG12_PM_L2M_CTRL = 0x2C, + S2MPG12_PM_L3M_CTRL = 0x2D, + S2MPG12_PM_L3M_CTRL2 = 0x2E, + S2MPG12_PM_L4M_CTRL = 0x2F, + S2MPG12_PM_L5M_CTRL = 0x30, + S2MPG12_PM_L6M_CTRL = 0x31, + S2MPG12_PM_L7M_CTRL = 0x32, + S2MPG12_PM_L8M_CTRL = 0x33, + S2MPG12_PM_L9M_CTRL = 0x34, + S2MPG12_PM_L10M_CTRL = 0x35, + S2MPG12_PM_L11M_CTRL1 = 0x36, + S2MPG12_PM_L12M_CTRL1 = 0x37, + S2MPG12_PM_L13M_CTRL1 = 0x38, + S2MPG12_PM_L14M_CTRL = 0x39, + S2MPG12_PM_L15M_CTRL1 = 0x3A, + S2MPG12_PM_L16M_CTRL = 0x3B, + S2MPG12_PM_L17M_CTRL = 0x3C, + S2MPG12_PM_L18M_CTRL = 0x3D, + S2MPG12_PM_L19M_CTRL = 0x3E, + S2MPG12_PM_L20M_CTRL = 0x3F, + S2MPG12_PM_L21M_CTRL = 0x40, + S2MPG12_PM_L22M_CTRL = 0x41, + S2MPG12_PM_L23M_CTRL = 0x42, + S2MPG12_PM_L24M_CTRL = 0x43, + S2MPG12_PM_L25M_CTRL = 0x44, + S2MPG12_PM_L26M_CTRL = 0x45, + S2MPG12_PM_L27M_CTRL = 0x46, + S2MPG12_PM_L28M_CTRL = 0x47, + S2MPG12_PM_LDO_CTRL1 = 0x48, + S2MPG12_PM_LDO_CTRL2 = 0x49, + S2MPG12_PM_LDO_CTRL3 = 0x4A, + S2MPG12_PM_LDO_DSCH1 = 0x4B, + S2MPG12_PM_LDO_DSCH2 = 0x4C, + S2MPG12_PM_LDO_DSCH3 = 0x4D, + S2MPG12_PM_LDO_DSCH4 = 0x4E, + S2MPG12_PM_B7M_HLIMIT = 0x4F, + S2MPG12_PM_B7M_LLIMIT = 0x50, + S2MPG12_PM_L21M_HLIMIT = 0x51, + S2MPG12_PM_L21M_LLIMIT = 0x52, + S2MPG12_PM_DVS_RAMP1 = 0x53, + S2MPG12_PM_DVS_RAMP2 = 0x54, + S2MPG12_PM_DVS_RAMP3 = 0x55, + S2MPG12_PM_DVS_RAMP4 = 0x56, + S2MPG12_PM_DVS_RAMP5 = 0x57, + S2MPG12_PM_DVS_RAMP6 = 0x58, + S2MPG12_PM_DVS_RAMP7 = 0x59, + S2MPG12_PM_DVS_RAMP8 = 0x5A, + S2MPG12_PM_DVS_SYNC_CTRL1 = 0x5B, + S2MPG12_PM_DVS_SYNC_CTRL2 = 0x5C, + S2MPG12_PM_DVS_SYNC_CTRL3 = 0x5D, + S2MPG12_PM_DVS_SYNC_CTRL4 = 0x5E, + S2MPG12_PM_DVS_SYNC_CTRL5 = 0x5F, + S2MPG12_PM_DVS_SYNC_CTRL6 = 0x60, + S2MPG12_PM_DVS_OPTION1 = 0x61, + S2MPG12_PM_OFF_CTRL1 = 0x62, + S2MPG12_PM_OFF_CTRL2 = 0x63, + S2MPG12_PM_OFF_CTRL3 = 0x64, + S2MPG12_PM_OFF_CTRL4 = 0x65, + S2MPG12_PM_OFF_CTRL5 = 0x66, + S2MPG12_PM_OFF_CTRL6 = 0x67, + S2MPG12_PM_OFF_CTRL7 = 0x68, + /* ONSEQ1 ~ ONSEQ33 (0x69 ~ 0x89) */ + /* OFFSEQ1 ~ OFFSEQ17 (0x8A ~ 0x9A) */ + S2MPG12_PM_PCTRLSEL1 = 0X9B, + S2MPG12_PM_PCTRLSEL2 = 0X9C, + S2MPG12_PM_PCTRLSEL3 = 0X9D, + S2MPG12_PM_PCTRLSEL4 = 0X9E, + S2MPG12_PM_PCTRLSEL5 = 0X9F, + S2MPG12_PM_PCTRLSEL6 = 0XA0, + S2MPG12_PM_PCTRLSEL7 = 0XA1, + S2MPG12_PM_PCTRLSEL8 = 0XA2, + S2MPG12_PM_PCTRLSEL9 = 0XA3, + S2MPG12_PM_PCTRLSEL10 = 0XA4, + S2MPG12_PM_PCTRLSEL11 = 0XA5, + S2MPG12_PM_PCTRLSEL12 = 0XA6, + S2MPG12_PM_PCTRLSEL13 = 0XA7, + S2MPG12_PM_PCTRLSEL14 = 0XA8, + S2MPG12_PM_DCTRLSEL1 = 0xA9, + S2MPG12_PM_DCTRLSEL2 = 0xAA, + S2MPG12_PM_DCTRLSEL3 = 0xAB, + S2MPG12_PM_DCTRLSEL4 = 0xAC, + S2MPG12_PM_DCTRLSEL5 = 0xAD, + S2MPG12_PM_DCTRLSEL6 = 0xAE, + S2MPG12_PM_DCTRLSEL7 = 0xAF, + S2MPG12_PM_DCTRLSEL8 = 0xB0, + S2MPG12_PM_DCTRLSEL9 = 0xB1, + S2MPG12_PM_BUCK_OCP_EN1 = 0xB2, + S2MPG12_PM_BUCK_OCP_EN2 = 0xB3, + S2MPG12_PM_BUCK_OCP_PD_EN1 = 0xB4, + S2MPG12_PM_BUCK_OCP_PD_EN2 = 0xB5, + S2MPG12_PM_BUCK_OCP_CTRL1 = 0xB6, + S2MPG12_PM_BUCK_OCP_CTRL2 = 0xB7, + S2MPG12_PM_BUCK_OCP_CTRL3 = 0xB8, + S2MPG12_PM_BUCK_OCP_CTRL4 = 0xB9, + S2MPG12_PM_BUCK_OCP_CTRL5 = 0xBA, + S2MPG12_PM_PSI_CTRL1 = 0xBB, + S2MPG12_PM_PSI_CTRL2 = 0xBC, + S2MPG12_PM_PSI_CTRL3 = 0xBD, + S2MPG12_PM_PSI_CTRL4 = 0xBE, + S2MPG12_PM_SEL_HW_VGPIO = 0xBF, + S2MPG12_PM_B2M_OCP_WARN = 0xC3, + S2MPG12_PM_B3M_OCP_WARN = 0xC4, + S2MPG12_PM_B10M_OCP_WARN = 0xC5, + S2MPG12_PM_B2M_SOFT_OCP_WARN = 0xC6, + S2MPG12_PM_B3M_SOFT_OCP_WARN = 0xC7, + S2MPG12_PM_B10M_SOFT_OCP_WARN = 0xC8, + S2MPG12_PM_B1M_OUT2 = 0xC9, + S2MPG12_PM_B2M_OUT2 = 0xCA, + S2MPG12_PM_B3M_OUT2 = 0xCB, + S2MPG12_PM_B4M_OUT2 = 0xCC, + S2MPG12_PM_B5M_OUT2 = 0xCD, + S2MPG12_PM_B6M_OUT2 = 0xCE, + S2MPG12_PM_B7M_OUT2 = 0xCF, + S2MPG12_PM_B8M_OUT2 = 0xD0, + S2MPG12_PM_B9M_OUT2 = 0xD1, + S2MPG12_PM_B10M_OUT2 = 0xD2, + S2MPG12_PM_L11M_CTRL2 = 0xD3, + S2MPG12_PM_L12M_CTRL2 = 0xD4, + S2MPG12_PM_L13M_CTRL2 = 0xD5, + S2MPG12_PM_L15M_CTRL2 = 0xD6, + S2MPG12_PM_L17M_CTRL2 = 0xD7, + S2MPG12_PM_L19M_CTRL2 = 0xD8, + S2MPG12_PM_L22M_CTRL2 = 0xD9, + S2MPG12_PM_BUCK_HRMODE1 = 0xDA, + S2MPG12_PM_BUCK_HRMODE2 = 0xDB, + S2MPG12_PM_LDO_SENSE1 = 0xDC, + S2MPG12_PM_LDO_SENSE2 = 0xDD, + S2MPG12_PM_LDO_SENSE3 = 0xDE, + S2MPG12_PM_LDO_SENSE4 = 0xDF, + S2MPG12_PM_B1M_USONIC = 0xE0, + S2MPG12_PM_B2M_USONIC = 0xE1, + S2MPG12_PM_B3M_USONIC = 0xE2, + S2MPG12_PM_B4M_USONIC = 0xE3, + S2MPG12_PM_B5M_USONIC = 0xE4, + S2MPG12_PM_B6M_USONIC = 0xE5, + S2MPG12_PM_B7M_USONIC = 0xE6, + S2MPG12_PM_B8M_USONIC = 0xE7, + S2MPG12_PM_B9M_USONIC = 0xE8, + S2MPG12_PM_B10M_USONIC = 0xE9, + S2MPG12_PM_FAULTOUT_CTRL = 0xEA, + S2MPG12_PM_INT_REG_SEL = 0xEB, + S2MPG12_PM_SW_RESET = 0xEC, +}; + +/* Meter(0xA) Registers */ +enum S2MPG12_METER_REG { + S2MPG12_METER_INT1 = 0x0, + S2MPG12_METER_INT2 = 0x1, + S2MPG12_METER_INT1M = 0x4, + S2MPG12_METER_INT2M = 0x5, + S2MPG12_METER_CTRL1 = 0x8, + S2MPG12_METER_CTRL2 = 0x9, + S2MPG12_METER_CTRL4 = 0xB, + S2MPG12_METER_CTRL5 = 0xC, + S2MPG12_METER_CTRL6 = 0xD, + S2MPG12_METER_CTRL7 = 0xE, + S2MPG12_METER_BUCKEN1 = 0xF, + S2MPG12_METER_BUCKEN2 = 0x10, + S2MPG12_METER_MUXSEL0 = 0x11, + S2MPG12_METER_MUXSEL1 = 0x12, + S2MPG12_METER_MUXSEL2 = 0x13, + S2MPG12_METER_MUXSEL3 = 0x14, + S2MPG12_METER_MUXSEL4 = 0x15, + S2MPG12_METER_MUXSEL5 = 0x16, + S2MPG12_METER_MUXSEL6 = 0x17, + S2MPG12_METER_MUXSEL7 = 0x18, + S2MPG12_METER_MUXSEL8 = 0x19, + S2MPG12_METER_MUXSEL9 = 0x1A, + S2MPG12_METER_MUXSEL10 = 0x1B, + S2MPG12_METER_MUXSEL11 = 0x1C, + S2MPG12_METER_LPF_C0_0 = 0x1D, + S2MPG12_METER_LPF_C0_1 = 0x1E, + S2MPG12_METER_LPF_C0_2 = 0x1F, + S2MPG12_METER_LPF_C0_3 = 0x20, + S2MPG12_METER_LPF_C0_4 = 0x21, + S2MPG12_METER_LPF_C0_5 = 0x22, + S2MPG12_METER_LPF_C0_6 = 0x23, + S2MPG12_METER_LPF_C0_7 = 0x24, + S2MPG12_METER_LPF_C0_8 = 0x25, + S2MPG12_METER_LPF_C0_9 = 0x26, + S2MPG12_METER_LPF_C0_10 = 0x27, + S2MPG12_METER_LPF_C0_11 = 0x28, + S2MPG12_METER_PWR_WARN0 = 0x31, + S2MPG12_METER_PWR_WARN1 = 0x32, + S2MPG12_METER_PWR_WARN2 = 0x33, + S2MPG12_METER_PWR_WARN3 = 0x34, + S2MPG12_METER_PWR_WARN4 = 0x35, + S2MPG12_METER_PWR_WARN5 = 0x36, + S2MPG12_METER_PWR_WARN6 = 0x37, + S2MPG12_METER_PWR_WARN7 = 0x38, + S2MPG12_METER_PWR_WARN8 = 0x39, + S2MPG12_METER_PWR_WARN9 = 0x3A, + S2MPG12_METER_PWR_WARN10 = 0x3B, + S2MPG12_METER_PWR_WARN11 = 0x3C, + S2MPG12_METER_PWR_HYS1 = 0x55, + S2MPG12_METER_PWR_HYS2 = 0x56, + S2MPG12_METER_PWR_HYS3 = 0x57, + S2MPG12_METER_PWR_HYS4 = 0x58, + S2MPG12_METER_PWR_HYS5 = 0x59, + S2MPG12_METER_PWR_HYS6 = 0x5A, + S2MPG12_METER_ACC_DATA_CH0_1 = 0x63, + S2MPG12_METER_ACC_DATA_CH0_2 = 0x64, + S2MPG12_METER_ACC_DATA_CH0_3 = 0x65, + S2MPG12_METER_ACC_DATA_CH0_4 = 0x66, + S2MPG12_METER_ACC_DATA_CH0_5 = 0x67, + S2MPG12_METER_ACC_DATA_CH0_6 = 0x68, + S2MPG12_METER_ACC_DATA_CH1_1 = 0x69, + S2MPG12_METER_ACC_DATA_CH1_2 = 0x6A, + S2MPG12_METER_ACC_DATA_CH1_3 = 0x6B, + S2MPG12_METER_ACC_DATA_CH1_4 = 0x6C, + S2MPG12_METER_ACC_DATA_CH1_5 = 0x6D, + S2MPG12_METER_ACC_DATA_CH1_6 = 0x6E, + S2MPG12_METER_ACC_DATA_CH2_1 = 0x6F, + S2MPG12_METER_ACC_DATA_CH2_2 = 0x70, + S2MPG12_METER_ACC_DATA_CH2_3 = 0x71, + S2MPG12_METER_ACC_DATA_CH2_4 = 0x72, + S2MPG12_METER_ACC_DATA_CH2_5 = 0x73, + S2MPG12_METER_ACC_DATA_CH2_6 = 0x74, + S2MPG12_METER_ACC_DATA_CH3_1 = 0x75, + S2MPG12_METER_ACC_DATA_CH3_2 = 0x76, + S2MPG12_METER_ACC_DATA_CH3_3 = 0x77, + S2MPG12_METER_ACC_DATA_CH3_4 = 0x78, + S2MPG12_METER_ACC_DATA_CH3_5 = 0x79, + S2MPG12_METER_ACC_DATA_CH3_6 = 0x7A, + S2MPG12_METER_ACC_DATA_CH4_1 = 0x7B, + S2MPG12_METER_ACC_DATA_CH4_2 = 0x7C, + S2MPG12_METER_ACC_DATA_CH4_3 = 0x7D, + S2MPG12_METER_ACC_DATA_CH4_4 = 0x7E, + S2MPG12_METER_ACC_DATA_CH4_5 = 0x7F, + S2MPG12_METER_ACC_DATA_CH4_6 = 0x80, + S2MPG12_METER_ACC_DATA_CH5_1 = 0x81, + S2MPG12_METER_ACC_DATA_CH5_2 = 0x82, + S2MPG12_METER_ACC_DATA_CH5_3 = 0x83, + S2MPG12_METER_ACC_DATA_CH5_4 = 0x84, + S2MPG12_METER_ACC_DATA_CH5_5 = 0x85, + S2MPG12_METER_ACC_DATA_CH5_6 = 0x86, + S2MPG12_METER_ACC_DATA_CH6_1 = 0x87, + S2MPG12_METER_ACC_DATA_CH6_2 = 0x88, + S2MPG12_METER_ACC_DATA_CH6_3 = 0x89, + S2MPG12_METER_ACC_DATA_CH6_4 = 0x8A, + S2MPG12_METER_ACC_DATA_CH6_5 = 0x8B, + S2MPG12_METER_ACC_DATA_CH6_6 = 0x8C, + S2MPG12_METER_ACC_DATA_CH7_1 = 0x8D, + S2MPG12_METER_ACC_DATA_CH7_2 = 0x8E, + S2MPG12_METER_ACC_DATA_CH7_3 = 0x8F, + S2MPG12_METER_ACC_DATA_CH7_4 = 0x90, + S2MPG12_METER_ACC_DATA_CH7_5 = 0x91, + S2MPG12_METER_ACC_DATA_CH7_6 = 0x92, + S2MPG12_METER_ACC_DATA_CH8_1 = 0x93, + S2MPG12_METER_ACC_DATA_CH8_2 = 0x94, + S2MPG12_METER_ACC_DATA_CH8_3 = 0x95, + S2MPG12_METER_ACC_DATA_CH8_4 = 0x96, + S2MPG12_METER_ACC_DATA_CH8_5 = 0x97, + S2MPG12_METER_ACC_DATA_CH8_6 = 0x98, + S2MPG12_METER_ACC_DATA_CH9_1 = 0x99, + S2MPG12_METER_ACC_DATA_CH9_2 = 0x9A, + S2MPG12_METER_ACC_DATA_CH9_3 = 0x9B, + S2MPG12_METER_ACC_DATA_CH9_4 = 0x9C, + S2MPG12_METER_ACC_DATA_CH9_5 = 0x9D, + S2MPG12_METER_ACC_DATA_CH9_6 = 0x9E, + S2MPG12_METER_ACC_DATA_CH10_1 = 0x9F, + S2MPG12_METER_ACC_DATA_CH10_2 = 0xA0, + S2MPG12_METER_ACC_DATA_CH10_3 = 0xA1, + S2MPG12_METER_ACC_DATA_CH10_4 = 0xA2, + S2MPG12_METER_ACC_DATA_CH10_5 = 0xA3, + S2MPG12_METER_ACC_DATA_CH10_6 = 0xA4, + S2MPG12_METER_ACC_DATA_CH11_1 = 0xA5, + S2MPG12_METER_ACC_DATA_CH11_2 = 0xA6, + S2MPG12_METER_ACC_DATA_CH11_3 = 0xA7, + S2MPG12_METER_ACC_DATA_CH11_4 = 0xA8, + S2MPG12_METER_ACC_DATA_CH11_5 = 0xA9, + S2MPG12_METER_ACC_DATA_CH11_6 = 0xAA, + S2MPG12_METER_ACC_COUNT_1 = 0xAB, + S2MPG12_METER_ACC_COUNT_2 = 0xAC, + S2MPG12_METER_ACC_COUNT_3 = 0xAD, + S2MPG12_METER_LPF_DATA_CH0_1 = 0xAE, + S2MPG12_METER_LPF_DATA_CH0_2 = 0xAF, + S2MPG12_METER_LPF_DATA_CH0_3 = 0xB0, + S2MPG12_METER_LPF_DATA_CH1_1 = 0xB1, + S2MPG12_METER_LPF_DATA_CH1_2 = 0xB2, + S2MPG12_METER_LPF_DATA_CH1_3 = 0xB3, + S2MPG12_METER_LPF_DATA_CH2_1 = 0xB4, + S2MPG12_METER_LPF_DATA_CH2_2 = 0xB5, + S2MPG12_METER_LPF_DATA_CH2_3 = 0xB6, + S2MPG12_METER_LPF_DATA_CH3_1 = 0xB7, + S2MPG12_METER_LPF_DATA_CH3_2 = 0xB8, + S2MPG12_METER_LPF_DATA_CH3_3 = 0xB9, + S2MPG12_METER_LPF_DATA_CH4_1 = 0xBA, + S2MPG12_METER_LPF_DATA_CH4_2 = 0xBB, + S2MPG12_METER_LPF_DATA_CH4_3 = 0xBC, + S2MPG12_METER_LPF_DATA_CH5_1 = 0xBD, + S2MPG12_METER_LPF_DATA_CH5_2 = 0xBE, + S2MPG12_METER_LPF_DATA_CH5_3 = 0xBF, + S2MPG12_METER_LPF_DATA_CH6_1 = 0xC0, + S2MPG12_METER_LPF_DATA_CH6_2 = 0xC1, + S2MPG12_METER_LPF_DATA_CH6_3 = 0xC2, + S2MPG12_METER_LPF_DATA_CH7_1 = 0xC3, + S2MPG12_METER_LPF_DATA_CH7_2 = 0xC4, + S2MPG12_METER_LPF_DATA_CH7_3 = 0xC5, + S2MPG12_METER_LPF_DATA_CH8_1 = 0xC6, + S2MPG12_METER_LPF_DATA_CH8_2 = 0xC7, + S2MPG12_METER_LPF_DATA_CH8_3 = 0xC8, + S2MPG12_METER_LPF_DATA_CH9_1 = 0xC9, + S2MPG12_METER_LPF_DATA_CH9_2 = 0xCA, + S2MPG12_METER_LPF_DATA_CH9_3 = 0xCB, + S2MPG12_METER_LPF_DATA_CH10_1 = 0xCC, + S2MPG12_METER_LPF_DATA_CH10_2 = 0xCD, + S2MPG12_METER_LPF_DATA_CH10_3 = 0xCE, + S2MPG12_METER_LPF_DATA_CH11_1 = 0xCF, + S2MPG12_METER_LPF_DATA_CH11_2 = 0xD0, + S2MPG12_METER_LPF_DATA_CH11_3 = 0xD1, + S2MPG12_METER_VBAT_DATA1 = 0xD2, + S2MPG12_METER_VBAT_DATA2 = 0xD3, + S2MPG12_METER_EXT_SIGNED_DATA_1 = 0xE4, + S2MPG12_METER_EXT_SIGNED_DATA_2 = 0xE5, +}; + +/* gpio(0xC) Registers */ +enum S2MPG12_GPIO_REG { + S2MPG12_GPIO_INT1 = 0x0, + S2MPG12_GPIO_INT2 = 0x1, + S2MPG12_GPIO_INT1M = 0x2, + S2MPG12_GPIO_INT2M = 0x3, + S2MPG12_GPIO_STATUS = 0x4, + S2MPG12_GPIO_0_SET = 0x5, + S2MPG12_GPIO_1_SET = 0x6, + S2MPG12_GPIO_2_SET = 0x7, + S2MPG12_GPIO_3_SET = 0x8, + S2MPG12_GPIO_4_SET = 0x9, + S2MPG12_GPIO_5_SET = 0xA, + S2MPG12_GPIO_0_MONSEL = 0xB, + S2MPG12_GPIO_1_MONSEL = 0xC, + S2MPG12_GPIO_2_MONSEL = 0xD, + S2MPG12_GPIO_3_MONSEL = 0xE, + S2MPG12_GPIO_4_MONSEL = 0xF, + S2MPG12_GPIO_5_MONSEL = 0x10, +}; + +/* MT_TRIM(0xE) Registers */ +enum S2MPG12_MT_TRIM_REG { + S2MPG12_MT_TRIM_COMMON = 0x29, +}; + +/* S2MPG12 regulator ids */ +enum S2MPG12_REGULATOR { + S2MPG12_LDO1, + S2MPG12_LDO2, + S2MPG12_LDO3, + S2MPG12_LDO4, + S2MPG12_LDO5, + S2MPG12_LDO6, + S2MPG12_LDO7, + S2MPG12_LDO8, + S2MPG12_LDO9, + S2MPG12_LDO10, + S2MPG12_LDO11, + S2MPG12_LDO12, + S2MPG12_LDO13, + S2MPG12_LDO14, + S2MPG12_LDO15, + S2MPG12_LDO16, + S2MPG12_LDO17, + S2MPG12_LDO18, + S2MPG12_LDO19, + S2MPG12_LDO20, + S2MPG12_LDO21, + S2MPG12_LDO22, + S2MPG12_LDO23, + S2MPG12_LDO24, + S2MPG12_LDO25, + S2MPG12_LDO26, + S2MPG12_LDO27, + S2MPG12_LDO28, + S2MPG12_BUCK1, + S2MPG12_BUCK2, + S2MPG12_BUCK3, + S2MPG12_BUCK4, + S2MPG12_BUCK5, + S2MPG12_BUCK6, + S2MPG12_BUCK7, + S2MPG12_BUCK8, + S2MPG12_BUCK9, + S2MPG12_BUCK10, + S2MPG12_REGULATOR_MAX, +}; + +enum s2mpg12_irq { + /* PMIC */ + S2MPG12_IRQ_PWRONF_INT1, + S2MPG12_IRQ_PWRONR_INT1, + S2MPG12_IRQ_JIGONBF_INT1, + S2MPG12_IRQ_JIGONBR_INT1, + S2MPG12_IRQ_ACOKBF_INT1, + S2MPG12_IRQ_ACOKBR_INT1, + S2MPG12_IRQ_PWRON1S_INT1, + S2MPG12_IRQ_MRB_INT1, + + S2MPG12_IRQ_RTC60S_INT2, + S2MPG12_IRQ_RTCA1_INT2, + S2MPG12_IRQ_RTCA0_INT2, + S2MPG12_IRQ_RTC1S_INT2, + S2MPG12_IRQ_WTSR_COLDRST_INT2, + S2MPG12_IRQ_WTSR_INT2, + S2MPG12_IRQ_WRST_INT2, + S2MPG12_IRQ_SMPL_INT2, + + S2MPG12_IRQ_120C_INT3, + S2MPG12_IRQ_140C_INT3, + S2MPG12_IRQ_TSD_INT3, + S2MPG12_IRQ_SCL_SOFTRST_INT3, + S2MPG12_IRQ_WLWP_ACC_INT3, + + S2MPG12_IRQ_OCP_B1M_INT4, + S2MPG12_IRQ_OCP_B2M_INT4, + S2MPG12_IRQ_OCP_B3M_INT4, + S2MPG12_IRQ_OCP_B4M_INT4, + S2MPG12_IRQ_OCP_B5M_INT4, + S2MPG12_IRQ_OCP_B6M_INT4, + S2MPG12_IRQ_OCP_B7M_INT4, + S2MPG12_IRQ_OCP_B8M_INT4, + + S2MPG12_IRQ_OCP_B9M_INT5, + S2MPG12_IRQ_OCP_B10M_INT5, + S2MPG12_IRQ_SMPL_TIMEOUT_INT5, + S2MPG12_IRQ_WTSR_TIMEOUT_INT5, + + S2MPG12_IRQ_PMETER_OVERF_INT6, + S2MPG12_IRQ_PWR_WARN_CH0_INT6, + S2MPG12_IRQ_PWR_WARN_CH1_INT6, + S2MPG12_IRQ_PWR_WARN_CH2_INT6, + S2MPG12_IRQ_PWR_WARN_CH3_INT6, + S2MPG12_IRQ_PWR_WARN_CH4_INT6, + S2MPG12_IRQ_PWR_WARN_CH5_INT6, + + S2MPG12_IRQ_PWR_WARN_CH6_INT7, + S2MPG12_IRQ_PWR_WARN_CH7_INT7, + S2MPG12_IRQ_PWR_WARN_CH8_INT7, + S2MPG12_IRQ_PWR_WARN_CH9_INT7, + S2MPG12_IRQ_PWR_WARN_CH10_INT7, + S2MPG12_IRQ_PWR_WARN_CH11_INT7, + + S2MPG12_IRQ_NR, +}; + +/* Common(0x0) MASK */ +/* S2MPG12_COMMON_IBI0 */ +#define S2MPG12_PMIC_M_MASK BIT(0) +#define S2MPG12_PMIC_S_MASK BIT(1) + +/* S2MPG12_COMMON_IBIM1 */ +#define S2MPG12_IRQSRC_MASK BIT(0) + +/* PM(0x1) MASK */ +#define S2MPG12_BUCK_MAX 10 +#define S2MPG12_LDO_MAX 28 +#define S2MPG12_VGPIO_NUM 14 +#define S2MPG12_VGPIO_MAX_VAL (0xFF) + +/* + * _MIN(group) S2MPG12_REG_MIN##group + * _STEP(group) S2MPG12_REG_STEP##group + */ + +/* BUCK 1M~10M ## group: 1 */ +#define S2MPG12_REG_MIN1 200000 +#define S2MPG12_REG_STEP1 6250 +/* LDO 1M,3M,7M,11M~13M,15M,17M,19M,22M ## group: 2 */ +#define S2MPG12_REG_MIN2 300000 +#define S2MPG12_REG_STEP2 12500 +/* LDO 5M,6M,8M,16M,28M ## group: 3 */ +#define S2MPG12_REG_MIN3 725000 +#define S2MPG12_REG_STEP3 12500 +/* LDO 2M,4M,9M,14M,18M,20M,23M,24M,25M ## group: 4 */ +#define S2MPG12_REG_MIN4 700000 +#define S2MPG12_REG_STEP4 25000 +/* LDO 10M,21M,26M,27M ## group: 5 */ +#define S2MPG12_REG_MIN5 1800000 +#define S2MPG12_REG_STEP5 25000 + +/* _N_VOLTAGES(num) S2MPG12_REG_N_VOLTAGES_##num */ +#define S2MPG12_REG_N_VOLTAGES_64 0x40 +#define S2MPG12_REG_N_VOLTAGES_128 0x80 +#define S2MPG12_REG_N_VOLTAGES_256 0x100 + +/* _MASK(num) S2MPG12_REG_ENABLE_MASK##num */ +#define S2MPG12_REG_ENABLE_WIDTH 2 +#define S2MPG12_REG_ENABLE_MASK_1_0 MASK(S2MPG12_REG_ENABLE_WIDTH, 0) +#define S2MPG12_REG_ENABLE_MASK_3_2 MASK(S2MPG12_REG_ENABLE_WIDTH, 2) +#define S2MPG12_REG_ENABLE_MASK_4_3 MASK(S2MPG12_REG_ENABLE_WIDTH, 3) +#define S2MPG12_REG_ENABLE_MASK_5_4 MASK(S2MPG12_REG_ENABLE_WIDTH, 4) +#define S2MPG12_REG_ENABLE_MASK_7_6 MASK(S2MPG12_REG_ENABLE_WIDTH, 6) +#define S2MPG12_REG_ENABLE_MASK_7 BIT(7) + +/* _TIME(macro) S2MPG12_ENABLE_TIME##macro */ +#define S2MPG12_ENABLE_TIME_LDO 128 +#define S2MPG12_ENABLE_TIME_BUCK 130 + +/* S2MPG12_PM_DCTRLSEL1 ~ 9 */ +#define S2MPG12_DCTRLSEL_VOUT1 0x0 +#define S2MPG12_DCTRLSEL_PWREN 0x1 +#define S2MPG12_DCTRLSEL_PWREN_TRG 0x2 +#define S2MPG12_DCTRLSEL_PWREN_MIF 0x3 +#define S2MPG12_DCTRLSEL_PWREN_MIF_TRG 0x4 +#define S2MPG12_DCTRLSEL_AP_ACTIVE_N 0x5 +#define S2MPG12_DCTRLSEL_AP_ACTIVE_N_TRG 0x6 +#define S2MPG12_DCTRLSEL_PWREN_MIF_ACTIVE_N 0x7 +#define S2MPG12_DCTRLSEL_AOC_RET 0x8 +#define S2MPG12_DCTRLSEL_TPU_EN 0x9 + +/* VGPIO_RX_MONITOR ADDR. */ +#define VGPIO_I3C_BASE 0x18100000 +#define VGPIO_MONITOR_ADDR 0x1704 + +/* VGPIO_PENDING_CLEAR */ +#define SYSREG_VGPIO2AP 0x182F0000 +#define INTC0_IPEND 0x0290 + +/* POWER-KEY MASK */ +#define S2MPG12_STATUS1_PWRON BIT(0) +#define S2MPG12_FALLING_EDGE BIT(1) /* INT1 reg */ +#define S2MPG12_RISING_EDGE BIT(0) /* INT1 reg */ + +/* S2MPG12_PM_SMPL_WARN_CTRL(0x16) */ +#define S2MPG12_SMPL_WARN_LBDT_SHIFT 0 +#define S2MPG12_SMPL_WARN_HYS_SHIFT 3 +#define S2MPG12_SMPL_WARN_LVL_SHIFT 5 + +/* S2MPG12_PM_OCP_WARN */ +#define S2MPG12_OCP_WARN_EN_SHIFT 7 +#define S2MPG12_OCP_WARN_CNT_SHIFT 6 +#define S2MPG12_OCP_WARN_DVS_MASK_SHIFT 5 +#define S2MPG12_OCP_WARN_LVL_SHIFT 0 + +/* METER(0xA) MASK */ +/* S2MPG12_METER_CTRL1 */ +#define S2MPG12_METER_EN_MASK BIT(0) + +#endif /* __LINUX_MFD_S2MPG12_REGISTER_H */ diff --git a/include/linux/mfd/samsung/s2mpg12.h b/include/linux/mfd/samsung/s2mpg12.h new file mode 100644 index 000000000000..c8d8a035af8c --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg12.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg12.h + * + * Copyright (C) 2016 Samsung Electrnoics + * + * Driver for the s2mpg12 + */ + +#ifndef __S2MPG12_MFD_H__ +#define __S2MPG12_MFD_H__ + +#include +#include +#include + +#include "s2mpg1x-register.h" +#include "s2mpg12-meter.h" + +#define S2MPG12_MFD_DEV_NAME "s2mpg12" + +/** + * sec_regulator_data - regulator data + * @id: regulator id + * @initdata: regulator init data (constraints, supplies, ...) + */ +struct s2mpg12_regulator_data { + int id; + struct regulator_init_data *initdata; + struct device_node *reg_node; +}; + +enum s2mpg12_irq_source { + S2MPG12_IRQS_PMIC_INT1 = 0, + S2MPG12_IRQS_PMIC_INT2, + S2MPG12_IRQS_PMIC_INT3, + S2MPG12_IRQS_PMIC_INT4, + S2MPG12_IRQS_PMIC_INT5, + S2MPG12_IRQS_METER_INT1, + S2MPG12_IRQS_METER_INT2, + + S2MPG12_IRQ_GROUP_NR, +}; + +#define S2MPG12_NUM_IRQ_PMIC_REGS 5 +#define S2MPG12_NUM_IRQ_METER_REGS 2 + +enum s2mpg12_device_type { + S2MPG12X, +}; + +enum s2mpg12_types { + TYPE_S2MPG12, +}; + +struct s2mpg12_platform_data { + /* Device Data */ + int device_type; + + /* IRQ */ + int irq_base; + bool wakeup; + + /* VGPIO */ + u32 *sel_vgpio; + + /* Regulator */ + int num_regulators; + struct s2mpg12_regulator_data *regulators; + struct sec_opmode_data *opmode; + + int smpl_warn_pin; + unsigned int smpl_warn_lvl; + unsigned int smpl_warn_hys; + unsigned int smpl_warn_lbdt; + + int b2_ocp_warn_pin; + unsigned int b2_ocp_warn_en; + unsigned int b2_ocp_warn_cnt; + unsigned int b2_ocp_warn_dvs_mask; + unsigned int b2_ocp_warn_lvl; + + int b3_ocp_warn_pin; + unsigned int b3_ocp_warn_en; + unsigned int b3_ocp_warn_cnt; + unsigned int b3_ocp_warn_dvs_mask; + unsigned int b3_ocp_warn_lvl; + + int b10_ocp_warn_pin; + unsigned int b10_ocp_warn_en; + unsigned int b10_ocp_warn_cnt; + unsigned int b10_ocp_warn_dvs_mask; + unsigned int b10_ocp_warn_lvl; + + int b2_soft_ocp_warn_pin; + unsigned int b2_soft_ocp_warn_en; + unsigned int b2_soft_ocp_warn_cnt; + unsigned int b2_soft_ocp_warn_dvs_mask; + unsigned int b2_soft_ocp_warn_lvl; + + int b3_soft_ocp_warn_pin; + unsigned int b3_soft_ocp_warn_en; + unsigned int b3_soft_ocp_warn_cnt; + unsigned int b3_soft_ocp_warn_dvs_mask; + unsigned int b3_soft_ocp_warn_lvl; + + int b10_soft_ocp_warn_pin; + unsigned int b10_soft_ocp_warn_en; + unsigned int b10_soft_ocp_warn_cnt; + unsigned int b10_soft_ocp_warn_dvs_mask; + unsigned int b10_soft_ocp_warn_lvl; + + unsigned int buck_ocp_ctrl1; + unsigned int buck_ocp_ctrl2; + unsigned int buck_ocp_ctrl3; + unsigned int buck_ocp_ctrl4; + unsigned int buck_ocp_ctrl5; + + /* ---- RTC ---- */ + struct sec_wtsr_smpl *wtsr_smpl; + struct rtc_time *init_time; + int osc_bias_up; + int cap_sel; + int osc_xin; + int osc_xout; + + void *meter; +}; + +struct s2mpg12_dev { + /* Device Data */ + struct device *dev; + struct s2mpg12_platform_data *pdata; + struct regmap *regmap; + int device_type; + int type; + + /* pmic VER/REV register */ + enum S2MPG12_pmic_rev pmic_rev; /* pmic Rev */ + + /* I2C Client */ + struct i2c_client *i2c; + struct i2c_client *pmic; + struct i2c_client *rtc; + struct i2c_client *meter; + struct i2c_client *wlwp; + struct i2c_client *gpio; + struct i2c_client *mt_trim; + struct i2c_client *trim; + /* mutex for i2c */ + struct mutex i2c_lock; + + /* IRQ */ + int irq; + int irq_base; + bool wakeup; + + /* VGPIO_RX_MONITOR */ + void __iomem *mem_base; + + /* VGPIO_INTC0_IPEND */ + void __iomem *sysreg_pending; + + /* mutex for s2mpg12 irq handling */ + struct mutex irqlock; + int irq_masks_cur[S2MPG12_IRQ_GROUP_NR]; + int irq_masks_cache[S2MPG12_IRQ_GROUP_NR]; + + /* Work queue */ + struct workqueue_struct *irq_wqueue; + struct delayed_work irq_work; +}; + +struct s2mpg12_pmic { + struct s2mpg12_dev *iodev; + struct i2c_client *i2c; + + /* mutex for s2mpg12 regulator */ + struct mutex lock; + struct regulator_dev **rdev; + unsigned int *opmode; + int num_regulators; + int *buck_ocp_irq; + int cpu1_ocp_warn_irq; + int soft_cpu1_ocp_warn_irq; + int cpu2_ocp_warn_irq; + int soft_cpu2_ocp_warn_irq; + int tpu_ocp_warn_irq; + int soft_tpu_ocp_warn_irq; +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + struct device *dev; + u16 read_addr; +#endif +}; + +int s2mpg12_irq_init(struct s2mpg12_dev *s2mpg12); +void s2mpg12_irq_exit(struct s2mpg12_dev *s2mpg12); +void s2mpg13_call_notifier(void); + +/* S2MPG12 shared i2c API function */ +int s2mpg12_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); +int s2mpg12_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf); +int s2mpg12_write_reg(struct i2c_client *i2c, u8 reg, u8 value); +int s2mpg12_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf); +int s2mpg12_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); + +u8 s2mpg12_get_rev_id(void); +int pmic_read_pwrkey_status(void); + +#endif /* __S2MPG12_MFD_H__ */ diff --git a/include/linux/mfd/samsung/s2mpg13-meter.h b/include/linux/mfd/samsung/s2mpg13-meter.h new file mode 100644 index 000000000000..273cde01bf95 --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg13-meter.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg13-meter.h + * + * Copyright (C) 2015 Samsung Electronics + * + * header file including meter information of s2mpg13 + */ + +#ifndef __LINUX_MFD_S2MPG13_METER_H +#define __LINUX_MFD_S2MPG13_METER_H + +#include "s2mpg13-register.h" + +struct s2mpg13_meter { + struct s2mpg13_dev *iodev; + struct i2c_client *i2c; + struct i2c_client *trim; + + /* mutex for s2mpg13 meter */ + struct mutex meter_lock; + u8 meter_en; + u8 ext_meter_en; + u8 chg_mux_sel[S2MPG1X_METER_CHANNEL_MAX]; + u32 lpf_data[S2MPG1X_METER_CHANNEL_MAX]; /* 21-bit data */ + unsigned int ntc_data[8]; + struct device *dev; +}; + +/* Public s2mpg13 Meter functions */ +int s2mpg13_meter_set_muxsel(struct s2mpg13_meter *s2mpg13, int channel, + s2mpg1x_meter_muxsel m); + +int s2mpg13_meter_onoff(struct s2mpg13_meter *s2mpg13, bool onoff); +int s2mpg13_ext_meter_onoff(struct s2mpg13_meter *s2mpg13, bool onoff); +u32 s2mpg13_muxsel_to_power_resolution(s2mpg1x_meter_muxsel m); +u32 s2mpg13_muxsel_to_current_resolution(s2mpg1x_meter_muxsel m); +void s2mpg13_meter_read_lpf_data_reg(struct s2mpg13_meter *s2mpg13, + u32 *data); + +#endif /* __LINUX_MFD_S2MPG13_METER_H */ diff --git a/include/linux/mfd/samsung/s2mpg13-register.h b/include/linux/mfd/samsung/s2mpg13-register.h new file mode 100644 index 000000000000..06cb509a7561 --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg13-register.h @@ -0,0 +1,640 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg13-register.h + * + * Copyright (C) 2015 Samsung Electrnoics + * + * header file including register information of s2mpg13 + */ + +#ifndef __LINUX_MFD_S2MPG13_REGISTER_H +#define __LINUX_MFD_S2MPG13_REGISTER_H + +#include +#include "s2mpg1x-register.h" + +#define S2MPG13_REG_INVALID (0xFF) + +enum S2MPG13_pmic_rev { + S2MPG13_EVT0, + S2MPG13_EVT1, +}; + +/* Common(0x0) Registers */ +enum S2MPG13_COMMON_REG { + S2MPG13_COMMON_VGPIO0 = 0x0, + S2MPG13_COMMON_VGPIO1 = 0x1, + S2MPG13_COMMON_VGPIO2 = 0x2, + S2MPG13_COMMON_VGPIO3 = 0x3, + S2MPG13_COMMON_I3C_DAA = 0x4, + S2MPG13_COMMON_IBI0 = 0x5, + S2MPG13_COMMON_IBI1 = 0x6, + S2MPG13_COMMON_IBI2 = 0x7, + S2MPG13_COMMON_IBI3 = 0x8, + S2MPG13_COMMON_CHIPID = 0xB, + S2MPG13_COMMON_I3C_CFG1 = 0xC, + S2MPG13_COMMON_I3C_STA = 0xE, + S2MPG13_COMMON_IBIM1 = 0xF, + S2MPG13_COMMON_IBIM2 = 0x10, +}; + +/* PM(0x1) Registers */ +enum S2MPG13_PM_REG { + S2MPG13_PM_INT1 = 0x0, + S2MPG13_PM_INT2 = 0x1, + S2MPG13_PM_INT3 = 0x2, + S2MPG13_PM_INT4 = 0x3, + S2MPG13_PM_INT1M = 0x4, + S2MPG13_PM_INT2M = 0x5, + S2MPG13_PM_INT3M = 0x6, + S2MPG13_PM_INT4M = 0x7, + S2MPG13_PM_OFFSRC = 0xA, + S2MPG13_PM_COMMON_CTRL1 = 0xC, + S2MPG13_PM_COMMON_CTRL2 = 0xD, + S2MPG13_PM_COMMON_CTRL3 = 0xE, + S2MPG13_PM_B1S_CTRL = 0xF, + S2MPG13_PM_B1S_OUT1 = 0x10, + S2MPG13_PM_B2S_CTRL = 0x11, + S2MPG13_PM_B2S_OUT1 = 0x12, + S2MPG13_PM_B3S_CTRL = 0x13, + S2MPG13_PM_B3S_OUT1 = 0x14, + S2MPG13_PM_B4S_CTRL = 0x15, + S2MPG13_PM_B4S_OUT = 0x16, + S2MPG13_PM_B5S_CTRL = 0x17, + S2MPG13_PM_B5S_OUT = 0x18, + S2MPG13_PM_B6S_CTRL = 0x19, + S2MPG13_PM_B6S_OUT1 = 0x1A, + S2MPG13_PM_B7S_CTRL = 0x1B, + S2MPG13_PM_B7S_OUT1 = 0x1C, + S2MPG13_PM_B8S_CTRL = 0x1D, + S2MPG13_PM_B8S_OUT1 = 0x1E, + S2MPG13_PM_B9S_CTRL = 0x1F, + S2MPG13_PM_B9S_OUT1 = 0x20, + S2MPG13_PM_B9S_OUT2 = 0x21, + S2MPG13_PM_B10S_CTRL = 0x22, + S2MPG13_PM_B10S_OUT = 0x23, + S2MPG13_PM_BUCKD_CTRL = 0x24, + S2MPG13_PM_BUCKD_OUT = 0x25, + S2MPG13_PM_BUCKA_CTRL = 0x26, + S2MPG13_PM_BUCKA_OUT = 0x27, + S2MPG13_PM_BUCKC_CTRL = 0x28, + S2MPG13_PM_BUCKC_OUT = 0x29, + S2MPG13_PM_BB_CTRL = 0x2A, + S2MPG13_PM_BB_OUT1 = 0x2B, + S2MPG13_PM_L1S_CTRL = 0x2C, + S2MPG13_PM_L2S_CTRL = 0x2D, + S2MPG13_PM_L3S_CTRL = 0x2E, + S2MPG13_PM_L4S_CTRL = 0x2F, + S2MPG13_PM_L5S_CTRL = 0x30, + S2MPG13_PM_L6S_CTRL = 0x31, + S2MPG13_PM_L7S_CTRL = 0x32, + S2MPG13_PM_L8S_CTRL = 0x33, + S2MPG13_PM_L9S_CTRL = 0x34, + S2MPG13_PM_L10S_CTRL = 0x35, + S2MPG13_PM_L11S_CTRL = 0x36, + S2MPG13_PM_L12S_CTRL = 0x37, + S2MPG13_PM_L13S_CTRL = 0x38, + S2MPG13_PM_L14S_CTRL = 0x39, + S2MPG13_PM_L15S_CTRL = 0x3A, + S2MPG13_PM_L16S_CTRL = 0x3B, + S2MPG13_PM_L17S_CTRL = 0x3C, + S2MPG13_PM_L18S_CTRL = 0x3D, + S2MPG13_PM_L19S_CTRL = 0x3E, + S2MPG13_PM_L20S_CTRL = 0x3F, + S2MPG13_PM_L21S_CTRL = 0x40, + S2MPG13_PM_L22S_CTRL = 0x41, + S2MPG13_PM_L23S_CTRL = 0x42, + S2MPG13_PM_L24S_CTRL = 0x43, + S2MPG13_PM_L25S_CTRL = 0x44, + S2MPG13_PM_L26S_CTRL = 0x45, + S2MPG13_PM_L27S_CTRL = 0x46, + S2MPG13_PM_L28S_CTRL = 0x47, + S2MPG13_PM_LDO_CTRL1 = 0x48, + S2MPG13_PM_LDO_CTRL2 = 0x49, + S2MPG13_PM_DSCH1 = 0x4A, + S2MPG13_PM_DSCH2 = 0x4B, + S2MPG13_PM_DSCH3 = 0x4C, + S2MPG13_PM_DSCH4 = 0x4D, + S2MPG13_PM_DVS_RAMP1 = 0x4E, + S2MPG13_PM_DVS_RAMP2 = 0x4F, + S2MPG13_PM_DVS_RAMP3 = 0x50, + S2MPG13_PM_DVS_RAMP4 = 0x51, + S2MPG13_PM_DVS_RAMP5 = 0x52, + S2MPG13_PM_DVS_RAMP6 = 0x53, + S2MPG13_PM_DVS_RAMP7 = 0x54, + S2MPG13_PM_DVS_RAMP8 = 0x55, + S2MPG13_PM_DVS_SYNC_CTRL1 = 0x56, + S2MPG13_PM_PCTRLSEL1 = 0x97, + S2MPG13_PM_PCTRLSEL2 = 0x98, + S2MPG13_PM_PCTRLSEL3 = 0x99, + S2MPG13_PM_PCTRLSEL4 = 0x9A, + S2MPG13_PM_PCTRLSEL5 = 0x9B, + S2MPG13_PM_PCTRLSEL6 = 0x9C, + S2MPG13_PM_PCTRLSEL7 = 0x9D, + S2MPG13_PM_PCTRLSEL8 = 0x9E, + S2MPG13_PM_PCTRLSEL9 = 0x9F, + S2MPG13_PM_PCTRLSEL10 = 0xA0, + S2MPG13_PM_PCTRLSEL11 = 0xA1, + S2MPG13_PM_DCTRLSEL1 = 0xA2, + S2MPG13_PM_DCTRLSEL2 = 0xA3, + S2MPG13_PM_DCTRLSEL3 = 0xA4, + S2MPG13_PM_DCTRLSEL4 = 0xA5, + S2MPG13_PM_DCTRLSEL5 = 0xA6, + S2MPG13_PM_OCP_EN1 = 0xA7, + S2MPG13_PM_OCP_EN2 = 0xA8, + S2MPG13_PM_OCP_PD_EN1 = 0xA9, + S2MPG13_PM_OCP_PD_EN2 = 0xAA, + S2MPG13_PM_OCP_CTRL1 = 0xAB, + S2MPG13_PM_OCP_CTRL2 = 0xAC, + S2MPG13_PM_OCP_CTRL3 = 0xAD, + S2MPG13_PM_OCP_CTRL4 = 0xAE, + S2MPG13_PM_OCP_CTRL5 = 0xAF, + S2MPG13_PM_OCP_CTRL6 = 0xB0, + S2MPG13_PM_OCP_CTRL7 = 0xB1, + S2MPG13_PM_B2S_OCP_WARN = 0xB8, + S2MPG13_PM_B2S_SOFT_OCP_WARN = 0xB9, + S2MPG13_PM_B1S_OUT2 = 0xBA, + S2MPG13_PM_B2S_OUT2 = 0xBB, + S2MPG13_PM_B6S_OUT2 = 0xBC, + S2MPG13_PM_B8S_OUT2 = 0xBD, + S2MPG13_PM_B10S_OUT2 = 0xBE, + S2MPG13_PM_L1S_CTRL2 = 0xBF, + S2MPG13_PM_L23S_CTRL2 = 0xC0, + S2MPG13_PM_L26S_CTRL2 = 0xC1, + /* TODO : ocp_warn * oi function */ +}; + +/* Meter(0xA) Registers */ +enum S2MPG13_METER_REG { + S2MPG13_METER_INT1 = 0x0, + S2MPG13_METER_INT2 = 0x1, + S2MPG13_METER_INT3 = 0x2, + S2MPG13_METER_INT4 = 0x3, + S2MPG13_METER_INT1M = 0x4, + S2MPG13_METER_INT2M = 0x5, + S2MPG13_METER_INT3M = 0x6, + S2MPG13_METER_INT4M = 0x7, + S2MPG13_METER_CTRL1 = 0x8, + S2MPG13_METER_CTRL2 = 0x9, + S2MPG13_METER_CTRL3 = 0xA, + S2MPG13_METER_CTRL4 = 0xB, + S2MPG13_METER_CTRL5 = 0xC, + S2MPG13_METER_CTRL6 = 0xD, + S2MPG13_METER_CTRL7 = 0xE, + S2MPG13_METER_BUCKEN1 = 0xF, + S2MPG13_METER_BUCKEN2 = 0x10, + S2MPG13_METER_MUXSEL0 = 0x11, + S2MPG13_METER_MUXSEL1 = 0x12, + S2MPG13_METER_MUXSEL2 = 0x13, + S2MPG13_METER_MUXSEL3 = 0x14, + S2MPG13_METER_MUXSEL4 = 0x15, + S2MPG13_METER_MUXSEL5 = 0x16, + S2MPG13_METER_MUXSEL6 = 0x17, + S2MPG13_METER_MUXSEL7 = 0x18, + S2MPG13_METER_MUXSEL8 = 0x19, + S2MPG13_METER_MUXSEL9 = 0x1A, + S2MPG13_METER_MUXSEL10 = 0x1B, + S2MPG13_METER_MUXSEL11 = 0x1C, + S2MPG13_METER_LPF_C0_0 = 0x1D, + S2MPG13_METER_LPF_C0_1 = 0x1E, + S2MPG13_METER_LPF_C0_2 = 0x1F, + S2MPG13_METER_LPF_C0_3 = 0x20, + S2MPG13_METER_LPF_C0_4 = 0x21, + S2MPG13_METER_LPF_C0_5 = 0x22, + S2MPG13_METER_LPF_C0_6 = 0x23, + S2MPG13_METER_LPF_C0_7 = 0x24, + S2MPG13_METER_LPF_C0_8 = 0x25, + S2MPG13_METER_LPF_C0_9 = 0x26, + S2MPG13_METER_LPF_C0_10 = 0x27, + S2MPG13_METER_LPF_C0_11 = 0x28, + S2MPG13_METER_PWR_WARN0 = 0x31, + S2MPG13_METER_PWR_WARN1 = 0x32, + S2MPG13_METER_PWR_WARN2 = 0x33, + S2MPG13_METER_PWR_WARN3 = 0x34, + S2MPG13_METER_PWR_WARN4 = 0x35, + S2MPG13_METER_PWR_WARN5 = 0x36, + S2MPG13_METER_PWR_WARN6 = 0x37, + S2MPG13_METER_PWR_WARN7 = 0x38, + S2MPG13_METER_PWR_WARN8 = 0x39, + S2MPG13_METER_PWR_WARN9 = 0x3A, + S2MPG13_METER_PWR_WARN10 = 0x3B, + S2MPG13_METER_PWR_WARN11 = 0x3C, + S2MPG13_METER_NTC_OT_WARN0 = 0x3D, + S2MPG13_METER_NTC_OT_WARN1 = 0x3E, + S2MPG13_METER_NTC_OT_WARN2 = 0x3F, + S2MPG13_METER_NTC_OT_WARN3 = 0x40, + S2MPG13_METER_NTC_OT_WARN4 = 0x41, + S2MPG13_METER_NTC_OT_WARN5 = 0x42, + S2MPG13_METER_NTC_OT_WARN6 = 0x43, + S2MPG13_METER_NTC_OT_WARN7 = 0x44, + S2MPG13_METER_NTC_OT_FAULT0 = 0x45, + S2MPG13_METER_NTC_OT_FAULT1 = 0x46, + S2MPG13_METER_NTC_OT_FAULT2 = 0x47, + S2MPG13_METER_NTC_OT_FAULT3 = 0x48, + S2MPG13_METER_NTC_OT_FAULT4 = 0x49, + S2MPG13_METER_NTC_OT_FAULT5 = 0x4A, + S2MPG13_METER_NTC_OT_FAULT6 = 0x4B, + S2MPG13_METER_NTC_OT_FAULT7 = 0x4C, + S2MPG13_METER_NTC_UT_WARN0 = 0x4D, + S2MPG13_METER_NTC_UT_WARN1 = 0x4E, + S2MPG13_METER_NTC_UT_WARN2 = 0x4F, + S2MPG13_METER_NTC_UT_WARN3 = 0x50, + S2MPG13_METER_NTC_UT_WARN4 = 0x51, + S2MPG13_METER_NTC_UT_WARN5 = 0x52, + S2MPG13_METER_NTC_UT_WARN6 = 0x53, + S2MPG13_METER_NTC_UT_WARN7 = 0x54, + S2MPG13_METER_ACC_DATA_CH0_1 = 0x63, + S2MPG13_METER_ACC_DATA_CH0_2 = 0x64, + S2MPG13_METER_ACC_DATA_CH0_3 = 0x65, + S2MPG13_METER_ACC_DATA_CH0_4 = 0x66, + S2MPG13_METER_ACC_DATA_CH0_5 = 0x67, + S2MPG13_METER_ACC_DATA_CH0_6 = 0x68, + S2MPG13_METER_ACC_DATA_CH1_1 = 0x69, + S2MPG13_METER_ACC_DATA_CH1_2 = 0x6A, + S2MPG13_METER_ACC_DATA_CH1_3 = 0x6B, + S2MPG13_METER_ACC_DATA_CH1_4 = 0x6C, + S2MPG13_METER_ACC_DATA_CH1_5 = 0x6D, + S2MPG13_METER_ACC_DATA_CH1_6 = 0x6E, + S2MPG13_METER_ACC_DATA_CH2_1 = 0x6F, + S2MPG13_METER_ACC_DATA_CH2_2 = 0x70, + S2MPG13_METER_ACC_DATA_CH2_3 = 0x71, + S2MPG13_METER_ACC_DATA_CH2_4 = 0x72, + S2MPG13_METER_ACC_DATA_CH2_5 = 0x73, + S2MPG13_METER_ACC_DATA_CH2_6 = 0x74, + S2MPG13_METER_ACC_DATA_CH3_1 = 0x75, + S2MPG13_METER_ACC_DATA_CH3_2 = 0x76, + S2MPG13_METER_ACC_DATA_CH3_3 = 0x77, + S2MPG13_METER_ACC_DATA_CH3_4 = 0x78, + S2MPG13_METER_ACC_DATA_CH3_5 = 0x79, + S2MPG13_METER_ACC_DATA_CH3_6 = 0x7A, + S2MPG13_METER_ACC_DATA_CH4_1 = 0x7B, + S2MPG13_METER_ACC_DATA_CH4_2 = 0x7C, + S2MPG13_METER_ACC_DATA_CH4_3 = 0x7D, + S2MPG13_METER_ACC_DATA_CH4_4 = 0x7E, + S2MPG13_METER_ACC_DATA_CH4_5 = 0x7F, + S2MPG13_METER_ACC_DATA_CH4_6 = 0x80, + S2MPG13_METER_ACC_DATA_CH5_1 = 0x81, + S2MPG13_METER_ACC_DATA_CH5_2 = 0x82, + S2MPG13_METER_ACC_DATA_CH5_3 = 0x83, + S2MPG13_METER_ACC_DATA_CH5_4 = 0x84, + S2MPG13_METER_ACC_DATA_CH5_5 = 0x85, + S2MPG13_METER_ACC_DATA_CH5_6 = 0x86, + S2MPG13_METER_ACC_DATA_CH6_1 = 0x87, + S2MPG13_METER_ACC_DATA_CH6_2 = 0x88, + S2MPG13_METER_ACC_DATA_CH6_3 = 0x89, + S2MPG13_METER_ACC_DATA_CH6_4 = 0x8A, + S2MPG13_METER_ACC_DATA_CH6_5 = 0x8B, + S2MPG13_METER_ACC_DATA_CH6_6 = 0x8C, + S2MPG13_METER_ACC_DATA_CH7_1 = 0x8D, + S2MPG13_METER_ACC_DATA_CH7_2 = 0x8E, + S2MPG13_METER_ACC_DATA_CH7_3 = 0x8F, + S2MPG13_METER_ACC_DATA_CH7_4 = 0x90, + S2MPG13_METER_ACC_DATA_CH7_5 = 0x91, + S2MPG13_METER_ACC_DATA_CH7_6 = 0x92, + S2MPG13_METER_ACC_DATA_CH8_1 = 0x93, + S2MPG13_METER_ACC_DATA_CH8_2 = 0x94, + S2MPG13_METER_ACC_DATA_CH8_3 = 0x95, + S2MPG13_METER_ACC_DATA_CH8_4 = 0x96, + S2MPG13_METER_ACC_DATA_CH8_5 = 0x97, + S2MPG13_METER_ACC_DATA_CH8_6 = 0x98, + S2MPG13_METER_ACC_DATA_CH9_1 = 0x99, + S2MPG13_METER_ACC_DATA_CH9_2 = 0x9A, + S2MPG13_METER_ACC_DATA_CH9_3 = 0x9B, + S2MPG13_METER_ACC_DATA_CH9_4 = 0x9C, + S2MPG13_METER_ACC_DATA_CH9_5 = 0x9D, + S2MPG13_METER_ACC_DATA_CH9_6 = 0x9E, + S2MPG13_METER_ACC_DATA_CH10_1 = 0x9F, + S2MPG13_METER_ACC_DATA_CH10_2 = 0xA0, + S2MPG13_METER_ACC_DATA_CH10_3 = 0xA1, + S2MPG13_METER_ACC_DATA_CH10_4 = 0xA2, + S2MPG13_METER_ACC_DATA_CH10_5 = 0xA3, + S2MPG13_METER_ACC_DATA_CH10_6 = 0xA4, + S2MPG13_METER_ACC_DATA_CH11_1 = 0xA5, + S2MPG13_METER_ACC_DATA_CH11_2 = 0xA6, + S2MPG13_METER_ACC_DATA_CH11_3 = 0xA7, + S2MPG13_METER_ACC_DATA_CH11_4 = 0xA8, + S2MPG13_METER_ACC_DATA_CH11_5 = 0xA9, + S2MPG13_METER_ACC_DATA_CH11_6 = 0xAA, + S2MPG13_METER_ACC_COUNT_1 = 0xAB, + S2MPG13_METER_ACC_COUNT_2 = 0xAC, + S2MPG13_METER_ACC_COUNT_3 = 0xAD, + S2MPG13_METER_LPF_DATA_CH0_1 = 0xAE, + S2MPG13_METER_LPF_DATA_CH0_2 = 0xAF, + S2MPG13_METER_LPF_DATA_CH0_3 = 0xB0, + S2MPG13_METER_LPF_DATA_CH1_1 = 0xB1, + S2MPG13_METER_LPF_DATA_CH1_2 = 0xB2, + S2MPG13_METER_LPF_DATA_CH1_3 = 0xB3, + S2MPG13_METER_LPF_DATA_CH2_1 = 0xB4, + S2MPG13_METER_LPF_DATA_CH2_2 = 0xB5, + S2MPG13_METER_LPF_DATA_CH2_3 = 0xB6, + S2MPG13_METER_LPF_DATA_CH3_1 = 0xB7, + S2MPG13_METER_LPF_DATA_CH3_2 = 0xB8, + S2MPG13_METER_LPF_DATA_CH3_3 = 0xB9, + S2MPG13_METER_LPF_DATA_CH4_1 = 0xBA, + S2MPG13_METER_LPF_DATA_CH4_2 = 0xBB, + S2MPG13_METER_LPF_DATA_CH4_3 = 0xBC, + S2MPG13_METER_LPF_DATA_CH5_1 = 0xBD, + S2MPG13_METER_LPF_DATA_CH5_2 = 0xBE, + S2MPG13_METER_LPF_DATA_CH5_3 = 0xBF, + S2MPG13_METER_LPF_DATA_CH6_1 = 0xC0, + S2MPG13_METER_LPF_DATA_CH6_2 = 0xC1, + S2MPG13_METER_LPF_DATA_CH6_3 = 0xC2, + S2MPG13_METER_LPF_DATA_CH7_1 = 0xC3, + S2MPG13_METER_LPF_DATA_CH7_2 = 0xC4, + S2MPG13_METER_LPF_DATA_CH7_3 = 0xC5, + S2MPG13_METER_LPF_DATA_CH8_1 = 0xC6, + S2MPG13_METER_LPF_DATA_CH8_2 = 0xC7, + S2MPG13_METER_LPF_DATA_CH8_3 = 0xC8, + S2MPG13_METER_LPF_DATA_CH9_1 = 0xC9, + S2MPG13_METER_LPF_DATA_CH9_2 = 0xCA, + S2MPG13_METER_LPF_DATA_CH9_3 = 0xCB, + S2MPG13_METER_LPF_DATA_CH10_1 = 0xCC, + S2MPG13_METER_LPF_DATA_CH10_2 = 0xCD, + S2MPG13_METER_LPF_DATA_CH10_3 = 0xCE, + S2MPG13_METER_LPF_DATA_CH11_1 = 0xCF, + S2MPG13_METER_LPF_DATA_CH11_2 = 0xD0, + S2MPG13_METER_LPF_DATA_CH11_3 = 0xD1, + S2MPG13_METER_VBAT_DATA1 = 0xD2, + S2MPG13_METER_VBAT_DATA2 = 0xD3, + S2MPG13_METER_LPF_DATA_NTC0_1 = 0xD4, + S2MPG13_METER_LPF_DATA_NTC0_2 = 0xD5, + S2MPG13_METER_LPF_DATA_NTC1_1 = 0xD6, + S2MPG13_METER_LPF_DATA_NTC1_2 = 0xD7, + S2MPG13_METER_LPF_DATA_NTC2_1 = 0xD8, + S2MPG13_METER_LPF_DATA_NTC2_2 = 0xD9, + S2MPG13_METER_LPF_DATA_NTC3_1 = 0xDA, + S2MPG13_METER_LPF_DATA_NTC3_2 = 0xDB, + S2MPG13_METER_LPF_DATA_NTC4_1 = 0xDC, + S2MPG13_METER_LPF_DATA_NTC4_2 = 0xDD, + S2MPG13_METER_LPF_DATA_NTC5_1 = 0xDE, + S2MPG13_METER_LPF_DATA_NTC5_2 = 0xDF, + S2MPG13_METER_LPF_DATA_NTC6_1 = 0xE0, + S2MPG13_METER_LPF_DATA_NTC6_2 = 0xE1, + S2MPG13_METER_LPF_DATA_NTC7_1 = 0xE2, + S2MPG13_METER_LPF_DATA_NTC7_2 = 0xE3, + S2MPG13_METER_EXT_SIGNED_DATA1 = 0xE4, + S2MPG13_METER_EXT_SIGNED_DATA2 = 0xE5, +}; + +/* gpio(0xC) Registers */ +enum S2MPG13_GPIO_REG { + S2MPG13_GPIO_INT1 = 0x0, + S2MPG13_GPIO_INT2 = 0x1, + S2MPG13_GPIO_INT1M = 0x2, + S2MPG13_GPIO_INT2M = 0x3, + S2MPG13_GPIO_STATUS = 0x4, + S2MPG13_GPIO_0_SET = 0x5, + S2MPG13_GPIO_1_SET = 0x6, + S2MPG13_GPIO_2_SET = 0x7, + S2MPG13_GPIO_3_SET = 0x8, + S2MPG13_GPIO_4_SET = 0x9, + S2MPG13_GPIO_5_SET = 0xA, + S2MPG13_GPIO_6_SET = 0xB, + S2MPG13_GPIO_7_SET = 0xC, + S2MPG13_GPIO_0_MONSEL = 0xD, + S2MPG13_GPIO_1_MONSEL = 0xE, + S2MPG13_GPIO_2_MONSEL = 0xF, + S2MPG13_GPIO_3_MONSEL = 0x10, + S2MPG13_GPIO_4_MONSEL = 0x11, + S2MPG13_GPIO_5_MONSEL = 0x12, + S2MPG13_GPIO_6_MONSEL = 0x13, + S2MPG13_GPIO_7_MONSEL = 0x14, +}; + +/* MT_TRIM(0xE) Registers */ +enum S2MPG13_MT_TRIM_REG { + S2MPG13_MT_TRIM_COMMON2 = 0x34, +}; + +/* S2MPG13 regulator ids */ +enum S2MPG13_REGULATOR { + S2MPG13_LDO1, + S2MPG13_LDO2, + S2MPG13_LDO3, + S2MPG13_LDO4, + S2MPG13_LDO5, + S2MPG13_LDO6, + S2MPG13_LDO7, + S2MPG13_LDO8, + S2MPG13_LDO9, + S2MPG13_LDO10, + S2MPG13_LDO11, + S2MPG13_LDO12, + S2MPG13_LDO13, + S2MPG13_LDO14, + S2MPG13_LDO15, + S2MPG13_LDO16, + S2MPG13_LDO17, + S2MPG13_LDO18, + S2MPG13_LDO19, + S2MPG13_LDO20, + S2MPG13_LDO21, + S2MPG13_LDO22, + S2MPG13_LDO23, + S2MPG13_LDO24, + S2MPG13_LDO25, + S2MPG13_LDO26, + S2MPG13_LDO27, + S2MPG13_LDO28, + S2MPG13_BUCK1, + S2MPG13_BUCK2, + S2MPG13_BUCK3, + S2MPG13_BUCK4, + S2MPG13_BUCK5, + S2MPG13_BUCK6, + S2MPG13_BUCK7, + S2MPG13_BUCK8, + S2MPG13_BUCK9, + S2MPG13_BUCK10, + S2MPG13_BUCKD, + S2MPG13_BUCKA, + S2MPG13_BUCKC, + S2MPG13_BUCKBOOST, + S2MPG13_REGULATOR_MAX, +}; + +enum s2mpg13_irq { + /* PMIC */ + S2MPG13_IRQ_PWRONF_INT1, + S2MPG13_IRQ_PWRONR_INT1, + S2MPG13_IRQ_INT120C_INT1, + S2MPG13_IRQ_INT140C_INT1, + S2MPG13_IRQ_TSD_INT1, + S2MPG13_IRQ_WRST_INT1, + S2MPG13_IRQ_WTSR_INT1, + + S2MPG13_IRQ_SCL_SOFTRST_INT2, + S2MPG13_IRQ_WLWP_ACC_INT2, + + S2MPG13_IRQ_OCP_B1S_INT3, + S2MPG13_IRQ_OCP_B2S_INT3, + S2MPG13_IRQ_OCP_B3S_INT3, + S2MPG13_IRQ_OCP_B4S_INT3, + S2MPG13_IRQ_OCP_B5S_INT3, + S2MPG13_IRQ_OCP_B6S_INT3, + S2MPG13_IRQ_OCP_B7S_INT3, + S2MPG13_IRQ_OCP_B8S_INT3, + + S2MPG13_IRQ_OCP_B9S_INT4, + S2MPG13_IRQ_OCP_B10S_INT4, + S2MPG13_IRQ_OCP_BDS_INT4, + S2MPG13_IRQ_OCP_BAS_INT4, + S2MPG13_IRQ_OCP_BCS_INT4, + S2MPG13_IRQ_OCP_BBS_INT4, + + S2MPG13_IRQ_PMETER_OVERF_INT5, + S2MPG13_IRQ_NTC_CYCLE_DONE_INT5, + S2MPG13_IRQ_PWR_WARN_CH0_INT5, + S2MPG13_IRQ_PWR_WARN_CH1_INT5, + S2MPG13_IRQ_PWR_WARN_CH2_INT5, + S2MPG13_IRQ_PWR_WARN_CH3_INT5, + S2MPG13_IRQ_PWR_WARN_CH4_INT5, + S2MPG13_IRQ_PWR_WARN_CH5_INT5, + + S2MPG13_IRQ_PWR_WARN_CH6_INT6, + S2MPG13_IRQ_PWR_WARN_CH7_INT6, + S2MPG13_IRQ_PWR_WARN_CH8_INT6, + S2MPG13_IRQ_PWR_WARN_CH9_INT6, + S2MPG13_IRQ_PWR_WARN_CH10_INT6, + S2MPG13_IRQ_PWR_WARN_CH11_INT6, + + S2MPG13_IRQ_NTC_WARN_OT_CH1_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH2_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH3_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH4_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH5_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH6_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH7_INT7, + S2MPG13_IRQ_NTC_WARN_OT_CH8_INT7, + + S2MPG13_IRQ_NTC_WARN_UT_CH1_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH2_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH3_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH4_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH5_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH6_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH7_INT8, + S2MPG13_IRQ_NTC_WARN_UT_CH8_INT8, + + S2MPG13_IRQ_NR, +}; + +/* Common(0x0) MASK */ +/* S2MPG13_COMMON_IBIM */ +enum S2MPG13_IBIM1_REGION { + S2MPG13_IBIM1_PM_REGION, + S2MPG13_IBIM1_PMETER_REGION, + S2MPG13_IBIM1_CCC_PARITY, + S2MPG13_IBIM1_ADDR_PARITY, + S2MPG13_IBIM1_DATA_PARITY, + S2MPG13_IBIM1_REGION_MAX +}; + +enum S2MPG13_IBIM2_REGION { + S2MPG13_IBIM2_OCP_WARN, + S2MPG13_IBIM2_SOFT_OCP_WARN, + S2MPG13_IBIM2_REGION_MAX +}; + +/* PM(0x1) MASK */ +#define S2MPG13_BUCK_MAX 13 +#define S2MPG13_LDO_MAX 28 +#define S2MPG13_BB_MAX 1 +#define S2MPG13_VGPIO_NUM 11 +#define S2MPG13_VGPIO_MAX_VAL (0xFF) + +/* S2MPG13_PM_INT3M */ +#define S2MPG13_IRQ_INT3M_SHIFT 0 +#define S2MPG13_IRQ_INT3M_WIDTH 8 +#define S2MPG13_IRQ_INT3M_MASK MASK(S2MPG13_IRQ_INT3M_WIDTH, S2MPG13_IRQ_INT3M_SHIFT) + +#define S2MPG13_IRQ_OCP_B1S_MASK BIT(0) +#define S2MPG13_IRQ_OCP_B2S_MASK BIT(1) +#define S2MPG13_IRQ_OCP_B3S_MASK BIT(2) +#define S2MPG13_IRQ_OCP_B4S_MASK BIT(3) +#define S2MPG13_IRQ_OCP_B5S_MASK BIT(4) +#define S2MPG13_IRQ_OCP_B6S_MASK BIT(5) +#define S2MPG13_IRQ_OCP_B7S_MASK BIT(6) +#define S2MPG13_IRQ_OCP_B8S_MASK BIT(7) + +/* S2MPG13_PM_INT4M */ +#define S2MPG13_IRQ_INT4M_SHIFT 0 +#define S2MPG13_IRQ_INT4M_WIDTH 5 +#define S2MPG13_IRQ_INT4M_MASK MASK(S2MPG13_IRQ_INT4M_WIDTH, S2MPG13_IRQ_INT4M_SHIFT) + +#define S2MPG13_IRQ_OCP_B9S_MASK BIT(0) +#define S2MPG13_IRQ_OCP_B10S_MASK BIT(1) +#define S2MPG13_IRQ_OCP_BDS_MASK BIT(2) +#define S2MPG13_IRQ_OCP_BAS_MASK BIT(3) +#define S2MPG13_IRQ_OCP_BCS_MASK BIT(4) +#define S2MPG13_IRQ_OCP_BBS_MASK BIT(5) + +/* + * _MIN(group) S2MPG13_REG_MIN##group + * _STEP(group) S2MPG13_REG_STEP##group + */ + +/* BUCK1S~6S, BUCK8S~10S, BUCKC ## group: 1 */ +#define S2MPG13_REG_MIN1 200000 +#define S2MPG13_REG_STEP1 6250 +/* BUCK7S,D,A ## group: 2 */ +#define S2MPG13_REG_MIN2 600000 +#define S2MPG13_REG_STEP2 12500 +/* BUCKBOOST ## group: 3 */ +#define S2MPG13_REG_MIN3 2600000 +#define S2MPG13_REG_STEP3 12500 +/* LDO1S,23S~26S ## group: 4 */ +#define S2MPG13_REG_MIN4 300000 +#define S2MPG13_REG_STEP4 12500 +/* LDO2S,3S,8S,9S,21S ## group: 5 */ +#define S2MPG13_REG_MIN5 725000 +#define S2MPG13_REG_STEP5 12500 +/* LDO4S,7S,10S~12S,14S,17S~20S,22S,27S ## group: 6 */ +#define S2MPG13_REG_MIN6 700000 +#define S2MPG13_REG_STEP6 25000 +/* LDO5S,6S,13S,15S,16S,28S ## group: 7 */ +#define S2MPG13_REG_MIN7 1800000 +#define S2MPG13_REG_STEP7 25000 + +/* _N_VOLTAGES(num) S2MPG13_REG_N_VOLTAGES_##num */ +#define S2MPG13_REG_N_VOLTAGES_64 0x40 +#define S2MPG13_REG_N_VOLTAGES_128 0x80 +#define S2MPG13_REG_N_VOLTAGES_256 0x100 + +#define S2MPG13_REG_ENABLE_WIDTH 2 +#define S2MPG13_REG_ENABLE_MASK_1_0 MASK(S2MPG13_REG_ENABLE_WIDTH, 0) +#define S2MPG13_REG_ENABLE_MASK_3_2 MASK(S2MPG13_REG_ENABLE_WIDTH, 2) +#define S2MPG13_REG_ENABLE_MASK_4_3 MASK(S2MPG13_REG_ENABLE_WIDTH, 3) +#define S2MPG13_REG_ENABLE_MASK_5_4 MASK(S2MPG13_REG_ENABLE_WIDTH, 4) +#define S2MPG13_REG_ENABLE_MASK_7_6 MASK(S2MPG13_REG_ENABLE_WIDTH, 6) +#define S2MPG13_REG_ENABLE_MASK_7 BIT(7) + +/* _TIME(macro) S2MPG13_ENABLE_TIME##macro */ +#define S2MPG13_ENABLE_TIME_LDO 128 +#define S2MPG13_ENABLE_TIME_BUCK 130 + +/* S2MPG13_PM_DCTRLSEL1 ~ 5 */ +#define DCTRLSEL_VOUT 0x0 +#define DCTRLSEL_PWREN 0x1 +#define DCTRLSEL_PWREN_TRG 0x2 +#define DCTRLSEL_PWREN_MIF 0x3 +#define DCTRLSEL_PWREN_MIF_TRG 0x4 +#define DCTRLSEL_AP_ACTIVE_N 0x5 +#define DCTRLSEL_AP_ACTIVE_N_TRG 0x6 +#define DCTRLSEL_PWREN_MIF_AP_ACTIVE_N 0x7 +#define DCTRLSEL_AOC_VDD 0x8 + +/* S2MPG13_PM_OCP_WARN */ +#define S2MPG13_OCP_WARN_EN_SHIFT 7 +#define S2MPG13_OCP_WARN_CNT_SHIFT 6 +#define S2MPG13_OCP_WARN_DVS_MASK_SHIFT 5 +#define S2MPG13_OCP_WARN_LVL_SHIFT 0 + +#define S2MPG13_METER_NTC_BUF 2 /* 12-bit */ + +#define S2MPG13_METER_EN_MASK BIT(0) + +/* MT TRIM register for enabling NTC channels */ +#define S2MPG13_MT_TRIM_NTC_EN_REG 0x34 + +#endif /* __LINUX_MFD_S2MPG13_REGISTER_H */ diff --git a/include/linux/mfd/samsung/s2mpg13.h b/include/linux/mfd/samsung/s2mpg13.h new file mode 100644 index 000000000000..6072381600ed --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg13.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg13.h + * + * Copyright (C) 2016 Samsung Electronics + * + * Driver for the s2mpg13 + */ + +#ifndef __S2MPG13_MFD_H__ +#define __S2MPG13_MFD_H__ +#include +#include +#include + +#include "s2mpg13-meter.h" + +#define S2MPG13_MFD_DEV_NAME "s2mpg13" + +/** + * sec_regulator_data - regulator data + * @id: regulator id + * @initdata: regulator init data (constraints, supplies, ...) + */ +struct s2mpg13_regulator_data { + int id; + struct regulator_init_data *initdata; + struct device_node *reg_node; +}; + +enum s2mpg13_irq_source { + S2MPG13_IRQS_PMIC_INT1 = 0, + S2MPG13_IRQS_PMIC_INT2, + S2MPG13_IRQS_PMIC_INT3, + S2MPG13_IRQS_PMIC_INT4, + S2MPG13_IRQS_METER_INT1, + S2MPG13_IRQS_METER_INT2, + S2MPG13_IRQS_METER_INT3, + S2MPG13_IRQS_METER_INT4, + + S2MPG13_IRQ_GROUP_NR, +}; + +#define S2MPG13_NUM_IRQ_PMIC_REGS 4 +#define S2MPG13_NUM_IRQ_METER_REGS 4 + +enum s2mpg13_device_type { + S2MPG13X, +}; + +enum s2mpg13_types { + TYPE_S2MPG13, +}; + +struct s2mpg13_platform_data { + /* Device Data */ + int device_type; + + /* IRQ */ + int irq_base; + bool wakeup; + + /* VGPIO */ + u32 *sel_vgpio; + + /* Regulator */ + int num_regulators; + struct s2mpg13_regulator_data *regulators; + struct sec_opmode_data *opmode; + + unsigned int b2_ocp_warn_pin; + unsigned int b2_ocp_warn_en; + unsigned int b2_ocp_warn_cnt; + unsigned int b2_ocp_warn_dvs_mask; + unsigned int b2_ocp_warn_lvl; + + unsigned int b2_soft_ocp_warn_pin; + unsigned int b2_soft_ocp_warn_en; + unsigned int b2_soft_ocp_warn_cnt; + unsigned int b2_soft_ocp_warn_dvs_mask; + unsigned int b2_soft_ocp_warn_lvl; + + unsigned int buck_ocp_ctrl1; + unsigned int buck_ocp_ctrl2; + unsigned int buck_ocp_ctrl3; + unsigned int buck_ocp_ctrl4; + unsigned int buck_ocp_ctrl5; + unsigned int buck_ocp_ctrl6; + unsigned int buck_ocp_ctrl7; + + void *meter; +}; + +struct s2mpg13_dev { + /* Device Data */ + struct device *dev; + struct s2mpg13_platform_data *pdata; + struct regmap *regmap; + int device_type; + int type; + + /* pmic VER/REV register */ + enum S2MPG13_pmic_rev pmic_rev; /* pmic Rev */ + + /* I2C Client */ + struct i2c_client *i2c; + struct i2c_client *pmic; + struct i2c_client *meter; + struct i2c_client *trim; + struct i2c_client *gpio; + struct i2c_client *wlwp; + struct i2c_client *mt_trim; + /* mutex for i2c */ + struct mutex i2c_lock; + + /* IRQ */ + int irq; + int irq_base; + bool wakeup; + + /* mutex for s2mpg13 irq handling */ + struct mutex irqlock; + u8 irq_masks_cur[S2MPG13_IRQ_GROUP_NR]; + u8 irq_masks_cache[S2MPG13_IRQ_GROUP_NR]; + + /* Work queue */ + struct workqueue_struct *irq_wqueue; + struct delayed_work irq_work; +}; + +struct s2mpg13_pmic { + struct s2mpg13_dev *iodev; + struct i2c_client *i2c; + + /* mutex for s2mpg13 regulator */ + struct mutex lock; + struct regulator_dev **rdev; + unsigned int *opmode; + int num_regulators; +#if IS_ENABLED(CONFIG_DRV_SAMSUNG_PMIC) + struct device *dev; + u16 read_addr; +#endif +}; + +void s2mpg13_call_notifier(void); +int s2mpg13_notifier_init(struct s2mpg13_dev *s2mpg13); + +/* S2MPG13 shared i2c API function */ +int s2mpg13_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest); +int s2mpg13_bulk_read(struct i2c_client *i2c, u8 reg, int count, u8 *buf); +int s2mpg13_write_reg(struct i2c_client *i2c, u8 reg, u8 value); +int s2mpg13_bulk_write(struct i2c_client *i2c, u8 reg, int count, u8 *buf); +int s2mpg13_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask); + +#endif /* __S2MPG13_MFD_H__ */ diff --git a/include/linux/mfd/samsung/s2mpg1x-meter.h b/include/linux/mfd/samsung/s2mpg1x-meter.h index 17f6005c227f..794522cde389 100644 --- a/include/linux/mfd/samsung/s2mpg1x-meter.h +++ b/include/linux/mfd/samsung/s2mpg1x-meter.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * include/linux/mfd/samsung/s2mpg1x-meter.h + * s2mpg1x-meter.h * * Copyright (C) 2015 Samsung Electronics * @@ -12,10 +12,7 @@ #include #include -#include "s2mpg1x-register.h" -#include -#include -#include +#include #include typedef enum { @@ -23,37 +20,129 @@ typedef enum { ADDRESS_CTRL2, ADDRESS_BUCKEN1, ADDRESS_LPF_C0_0, + ADDRESS_ACC_MODE, + ADDRESS_ACC_DATA, + ADDRESS_ACC_COUNT, + ADDRESS_LPF_MODE, + ADDRESS_LPF_DATA, ADDRESS_COUNT, } address_t; -const int COMMON_ADDRESS[ADDRESS_COUNT][ID_COUNT] = { +#if IS_ENABLED(CONFIG_SOC_GS101) +static const int ADDRESS_AT[ADDRESS_COUNT][ID_COUNT] = { [ADDRESS_CTRL1] = { S2MPG10_METER_CTRL1, S2MPG11_METER_CTRL1 }, [ADDRESS_CTRL2] = { S2MPG10_METER_CTRL2, S2MPG11_METER_CTRL2 }, [ADDRESS_BUCKEN1] = { S2MPG10_METER_BUCKEN1, S2MPG11_METER_BUCKEN1 }, [ADDRESS_LPF_C0_0] = { S2MPG10_METER_LPF_C0_0, S2MPG11_METER_LPF_C0_0 }, + [ADDRESS_ACC_MODE] = { S2MPG10_METER_CTRL3, S2MPG11_METER_CTRL4 }, + [ADDRESS_ACC_DATA] = { + S2MPG10_METER_ACC_DATA_CH0_1, + S2MPG11_METER_ACC_DATA_CH0_1 + }, + [ADDRESS_ACC_COUNT] = { + S2MPG10_METER_ACC_COUNT_1, + S2MPG11_METER_ACC_COUNT_1 + }, + [ADDRESS_LPF_MODE] = { S2MPG10_METER_CTRL4, S2MPG11_METER_CTRL5 }, + [ADDRESS_LPF_DATA] = { + S2MPG10_METER_LPF_DATA_CH0_1, + S2MPG11_METER_LPF_DATA_CH0_1 + }, }; +#elif IS_ENABLED(CONFIG_SOC_GS201) +static const int ADDRESS_AT[ADDRESS_COUNT][ID_COUNT] = { + [ADDRESS_CTRL1] = { S2MPG12_METER_CTRL1, S2MPG13_METER_CTRL1 }, + [ADDRESS_CTRL2] = { S2MPG12_METER_CTRL2, S2MPG13_METER_CTRL2 }, + [ADDRESS_BUCKEN1] = { S2MPG12_METER_BUCKEN1, S2MPG13_METER_BUCKEN1 }, + [ADDRESS_LPF_C0_0] = { S2MPG12_METER_LPF_C0_0, S2MPG13_METER_LPF_C0_0 }, + [ADDRESS_ACC_MODE] = { S2MPG12_METER_CTRL4, S2MPG13_METER_CTRL4 }, + [ADDRESS_ACC_DATA] = { + S2MPG12_METER_ACC_DATA_CH0_1, + S2MPG13_METER_ACC_DATA_CH0_1 + }, + [ADDRESS_ACC_COUNT] = { + S2MPG12_METER_ACC_COUNT_1, + S2MPG13_METER_ACC_COUNT_1 + }, + [ADDRESS_LPF_MODE] = { S2MPG12_METER_CTRL6, S2MPG13_METER_CTRL6 }, + [ADDRESS_LPF_DATA] = { + S2MPG12_METER_LPF_DATA_CH0_1, + S2MPG13_METER_LPF_DATA_CH0_1 + }, +}; +#endif -const u32 s2mpg1x_int_sample_rate_uhz[S2MPG1X_INT_FREQ_COUNT] = { +static const u32 s2mpg1x_int_sample_rate_uhz[S2MPG1X_INT_FREQ_COUNT] = { [INT_7P_8125HZ] = 7812500, [INT_15P_625HZ] = 15625000, [INT_31P_25HZ] = 31250000, [INT_62P_5HZ] = 62500000, [INT_125HZ] = 125000000, [INT_250HZ] = 250000000, - [INT_500HZ] = 500000000, [INT_1000HZ] = 1000000000, +#if IS_ENABLED(CONFIG_SOC_GS101) + [INT_500HZ] = 500000000, +#endif + [INT_1000HZ] = 1000000000, }; -const u32 s2mpg1x_ext_sample_rate_uhz[S2MPG1X_EXT_FREQ_COUNT] = { +#if IS_ENABLED(CONFIG_SOC_GS101) +static const u32 s2mpg1x_ext_sample_rate_uhz[S2MPG1X_EXT_FREQ_COUNT] = { [EXT_7P_628125HZ] = 7628125, [EXT_15P_25625HZ] = 15256250, [EXT_30P_5125HZ] = 30512500, [EXT_61P_025HZ] = 61025000, [EXT_122P_05HZ] = 122050000, }; +#elif IS_ENABLED(CONFIG_SOC_GS201) +static const u32 s2mpg1x_ext_sample_rate_uhz[S2MPG1X_EXT_FREQ_COUNT] = { + [EXT_7P_8125HZ] = 7812500, [EXT_15P_625HZ] = 15625000, + [EXT_31P_25HZ] = 31250000, [EXT_62P_5HZ] = 62500000, + [EXT_125HZ] = 125000000, +}; +#endif + +#if IS_ENABLED(CONFIG_SOC_GS201) +static const u32 s2mpg1x_int_acquisition_time_us[S2MPG1X_INT_FREQ_COUNT] = { + [INT_7P_8125HZ] = 128000, [INT_15P_625HZ] = 64000, + [INT_31P_25HZ] = 32000, [INT_62P_5HZ] = 16000, + [INT_125HZ] = 8000, [INT_250HZ] = 4000, + [INT_1000HZ] = 1000, +}; +#endif + +static inline int s2mpg1x_meter_get_acquisition_time_us(s2mpg1x_int_samp_rate samp_rate) +{ +#if IS_ENABLED(CONFIG_SOC_GS101) + /* Based on the s2mpg1x datasheets, (40 us * channel count) is the + * maximum time required for acquisition of all samples across all + * channels. + */ + return (40 * S2MPG1X_METER_CHANNEL_MAX); +#elif IS_ENABLED(CONFIG_SOC_GS201) + /* The internal data and sample count are not updated at the same timing + * on Pro due to the duty cycling function, and the ASYNC_RD will depend + * on internal sampling rate. + * So at least waiting for internal rail to complete a sampling will be + * necessary to prevent the mismatch of irregular timing. (b/209886118) + */ + return s2mpg1x_int_acquisition_time_us[samp_rate]; +#endif +} -#define ACQUISITION_TIME_US (40 * S2MPG1X_METER_CHANNEL_MAX) +#if IS_ENABLED(CONFIG_SOC_GS101) +#define ACQUISITION_TIME_DIVISOR 1 +#elif IS_ENABLED(CONFIG_SOC_GS201) +#define ACQUISITION_TIME_DIVISOR 16 +#endif static inline int s2mpg1x_meter_set_async_blocking(enum s2mpg1x_id id, struct i2c_client *i2c, - u64 *timestamp_capture) + u64 *timestamp_capture, + s2mpg1x_int_samp_rate samp_rate) { u8 val = 0xFF; int ret; - u8 reg = COMMON_ADDRESS[ADDRESS_CTRL2][id]; + u8 reg = ADDRESS_AT[ADDRESS_CTRL2][id]; + + const u32 acquisition_time_us = + s2mpg1x_meter_get_acquisition_time_us(samp_rate); + const u32 min_acquisition_time_us = acquisition_time_us / + ACQUISITION_TIME_DIVISOR; + int acquisition_delay_count = 0; /* When 1 is written into ASYNC_RD bit, */ /* transfer the accumulator data to readable registers->self-cleared */ @@ -66,10 +155,8 @@ static inline int s2mpg1x_meter_set_async_blocking(enum s2mpg1x_id id, if (timestamp_capture) *timestamp_capture = ktime_get_boottime_ns(); - /* Based on the s2mpg1x datasheets, (40 us * channel count) is the - * maximum time required for acquisition of all samples across all - * channels. However, typically, we do not write 1 to ASYNC during - * acquisition, so return immediately to reduce refresh time. + /* Verify if acquisition is already complete before a polled delay. + * Return immediately to reduce refresh time if so. */ ret = s2mpg1x_read_reg(id, i2c, reg, &val); @@ -79,11 +166,14 @@ static inline int s2mpg1x_meter_set_async_blocking(enum s2mpg1x_id id, /* Reading has failed OR we sampled during acquisition, so wait the * acquisition time and return based on the values read. */ - usleep_range(ACQUISITION_TIME_US, ACQUISITION_TIME_US + 100); - - ret = s2mpg1x_read_reg(id, i2c, reg, &val); - if (ret != 0 || (val & ASYNC_RD_MASK) == 0x00) - return ret; + do { + usleep_range(min_acquisition_time_us, + min_acquisition_time_us + 100); + ret = s2mpg1x_read_reg(id, i2c, reg, &val); + if (ret != 0 || (val & ASYNC_RD_MASK) == 0x00) + return ret; + acquisition_delay_count++; + } while (acquisition_delay_count < ACQUISITION_TIME_DIVISOR); return -1; /* ASYNC value has not changed */ } @@ -100,8 +190,8 @@ static inline ssize_t s2mpg1x_meter_format_channel(char *buf, ssize_t count, u64 resolution_max = _IQ30_to_int((u64)resolution * one_billion); return scnprintf(buf + count, PAGE_SIZE - count, - "CH%d[%s]: 0x%016llx * %lld.%09llu / 0x%08x %s\n", ch, name, - acc_data, resolution_max / one_billion, + "CH%d[%s]: 0x%016llx * %lld.%09llu / 0x%08x %s\n", ch, + name, acc_data, resolution_max / one_billion, resolution_max % one_billion, acc_count, units); } @@ -112,7 +202,7 @@ static inline int s2mpg1x_meter_set_buck_channel_en(enum s2mpg1x_id id, if (num_bytes > S2MPG1X_METER_BUCKEN_BUF) return -EINVAL; - return s2mpg1x_bulk_write(id, i2c, COMMON_ADDRESS[ADDRESS_BUCKEN1][id], + return s2mpg1x_bulk_write(id, i2c, ADDRESS_AT[ADDRESS_BUCKEN1][id], num_bytes, channels); } @@ -120,7 +210,7 @@ static inline int s2mpg1x_meter_set_ext_channel_en(enum s2mpg1x_id id, struct i2c_client *i2c, u8 channels) { - return s2mpg1x_update_reg(id, i2c, COMMON_ADDRESS[ADDRESS_CTRL2][id], + return s2mpg1x_update_reg(id, i2c, ADDRESS_AT[ADDRESS_CTRL2][id], channels << EXT_METER_CHANNEL_EN_OFFSET, EXT_METER_CHANNEL_EN_MASK); } @@ -129,7 +219,7 @@ static inline int s2mpg1x_meter_set_int_samp_rate(enum s2mpg1x_id id, struct i2c_client *i2c, s2mpg1x_int_samp_rate hz) { - return s2mpg1x_update_reg(id, i2c, COMMON_ADDRESS[ADDRESS_CTRL1][id], + return s2mpg1x_update_reg(id, i2c, ADDRESS_AT[ADDRESS_CTRL1][id], hz << INT_SAMP_RATE_SHIFT, INT_SAMP_RATE_MASK); } @@ -138,7 +228,7 @@ static inline int s2mpg1x_meter_set_ext_samp_rate(enum s2mpg1x_id id, struct i2c_client *i2c, s2mpg1x_ext_samp_rate hz) { - return s2mpg1x_update_reg(id, i2c, COMMON_ADDRESS[ADDRESS_CTRL2][id], + return s2mpg1x_update_reg(id, i2c, ADDRESS_AT[ADDRESS_CTRL2][id], hz, EXT_SAMP_RATE_MASK); } @@ -150,7 +240,7 @@ static inline int s2mpg1x_meter_set_lpf_coefficient(enum s2mpg1x_id id, if (ch >= S2MPG1X_METER_CHANNEL_MAX) return -EINVAL; - return s2mpg1x_write_reg(id, i2c, COMMON_ADDRESS[ADDRESS_LPF_C0_0][id] + + return s2mpg1x_write_reg(id, i2c, ADDRESS_AT[ADDRESS_LPF_C0_0][id] + ch, val); } @@ -164,4 +254,165 @@ static inline const u32 *s2mpg1x_meter_get_ext_samping_rate_table(void) return s2mpg1x_ext_sample_rate_uhz; } +static inline void s2mpg1x_meter_set_mode(enum s2mpg1x_id id, + struct i2c_client *i2c, + s2mpg1x_meter_mode mode, + bool is_acc_mode) // else lpf + +{ + address_t mode_addr = ADDRESS_ACC_MODE; + + if (!is_acc_mode) + mode_addr = ADDRESS_LPF_MODE; + + switch (mode) { + case S2MPG1X_METER_POWER: + s2mpg1x_write_reg(id, i2c, ADDRESS_AT[mode_addr][id], 0x00); +#if IS_ENABLED(CONFIG_SOC_GS201) + s2mpg1x_update_reg(id, i2c, ADDRESS_AT[mode_addr][id] + 1, 0x00, + /* mask= */ 0x0F); +#endif + break; + + case S2MPG1X_METER_CURRENT: + s2mpg1x_write_reg(id, i2c, ADDRESS_AT[mode_addr][id], 0xFF); +#if IS_ENABLED(CONFIG_SOC_GS201) + s2mpg1x_update_reg(id, i2c, ADDRESS_AT[mode_addr][id] + 1, 0x0F, + /* mask= */ 0x0F); +#endif + break; + } +} + +static inline void s2mpg1x_meter_set_acc_mode(enum s2mpg1x_id id, + struct i2c_client *i2c, + s2mpg1x_meter_mode mode) +{ + s2mpg1x_meter_set_mode(id, i2c, mode, /* is_acc_mode= */ true); +} + +static inline void s2mpg1x_meter_set_lpf_mode(enum s2mpg1x_id id, + struct i2c_client *i2c, + s2mpg1x_meter_mode mode) +{ + s2mpg1x_meter_set_mode(id, i2c, mode, /* is_acc_mode= */ false); +} + +static inline void s2mpg1x_meter_read_acc_data_reg(enum s2mpg1x_id id, + struct i2c_client *i2c, + u64 *data) +{ + int i; + u8 buf[S2MPG1X_METER_ACC_BUF]; + u8 reg = ADDRESS_AT[ADDRESS_ACC_DATA][id]; /* first acc data register */ + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_bulk_read(id, i2c, reg, S2MPG1X_METER_ACC_BUF, buf); + + /* 41 bits of data */ + data[i] = ((u64)buf[0] << 0) | ((u64)buf[1] << 8) | + ((u64)buf[2] << 16) | ((u64)buf[3] << 24) | + ((u64)buf[4] << 32) | (((u64)buf[5] & 0x1) << 40); + + reg += S2MPG1X_METER_ACC_BUF; + } +} + +static inline void s2mpg1x_meter_read_acc_count(enum s2mpg1x_id id, + struct i2c_client *i2c, + u32 *count) +{ + u8 data[S2MPG1X_METER_COUNT_BUF]; + u8 reg = ADDRESS_AT[ADDRESS_ACC_COUNT][id]; /* first count register */ + + s2mpg1x_bulk_read(id, i2c, reg, S2MPG1X_METER_COUNT_BUF, data); + + /* ACC_COUNT is 20-bit data */ + *count = (data[0] << 0) | (data[1] << 8) | ((data[2] & 0x0F) << 16); +} + +static inline void s2mpg1x_meter_read_lpf_data_reg(enum s2mpg1x_id id, + struct i2c_client *i2c, + u32 *data) +{ + int i; + u8 buf[S2MPG1X_METER_LPF_BUF]; + u8 reg = ADDRESS_AT[ADDRESS_LPF_DATA][id]; /* first lpf data register */ + + for (i = 0; i < S2MPG1X_METER_CHANNEL_MAX; i++) { + s2mpg1x_bulk_read(id, i2c, reg, S2MPG1X_METER_LPF_BUF, buf); + + /* LPF is 21-bit data */ + data[i] = buf[0] + (buf[1] << 8) + ((buf[2] & 0x1F) << 16); + + reg += S2MPG1X_METER_LPF_BUF; + } +} + +/** + * Load measurement into registers and read measurement from the registers + * + * Note: data must be an array with length S2MPG1X_METER_CHANNEL_MAX + */ +static inline int s2mpg1x_meter_measure_acc(enum s2mpg1x_id id, + struct i2c_client *i2c, + struct mutex *meter_lock, + s2mpg1x_meter_mode mode, + u64 *data, + u32 *count, + u64 *timestamp_capture, + s2mpg1x_int_samp_rate samp_rate) +{ + mutex_lock(meter_lock); + + s2mpg1x_meter_set_acc_mode(id, i2c, mode); + + s2mpg1x_meter_set_async_blocking(id, i2c, + timestamp_capture, + samp_rate); + + if (data) + s2mpg1x_meter_read_acc_data_reg(id, i2c, data); + + if (count) + s2mpg1x_meter_read_acc_count(id, i2c, count); + + mutex_unlock(meter_lock); + + return 0; +} + +#if IS_ENABLED(CONFIG_SOC_GS201) +#define SW_RESET_DELAYTIME_US 2 +static inline int s2mpg1x_meter_sw_reset(enum s2mpg1x_id id, + struct i2c_client *i2c, + struct i2c_client *mt_trim, + u8 mt_trim_reg) +{ + int ret; + + ret = s2mpg1x_update_reg(id, mt_trim, mt_trim_reg, 0x00, + /* mask= */ BIT(7)); + if (ret != 0) { + pr_err("odpm: s2mpg1%d-odpm: failed to update mt_trim bit_7 to 0\n", id + 2); + return ret; + } + ret = s2mpg1x_update_reg(id, mt_trim, mt_trim_reg, 0x80, + /* mask= */ BIT(7)); + if (ret != 0) { + pr_err("odpm: s2mpg1%d-odpm: failed to update mt_trim bit_7 to 1\n", id + 2); + return ret; + } + + usleep_range(SW_RESET_DELAYTIME_US, SW_RESET_DELAYTIME_US + 100); + + ret = s2mpg1x_update_reg(id, i2c, ADDRESS_AT[ADDRESS_CTRL1][id], 0x01, + METER_EN_MASK); + if (ret != 0) + pr_err("odpm: s2mpg1%d-odpm: failed to update meter_ctrl1 bit_0 to 1\n", id + 2); + + return ret; +} +#endif + #endif /* __LINUX_MFD_S2MPG1X_METER_H */ diff --git a/include/linux/mfd/samsung/s2mpg1x-register.h b/include/linux/mfd/samsung/s2mpg1x-register.h index 8176dc5573c2..4629053d02f9 100644 --- a/include/linux/mfd/samsung/s2mpg1x-register.h +++ b/include/linux/mfd/samsung/s2mpg1x-register.h @@ -2,9 +2,9 @@ /* * include/linux/mfd/samsung/s2mpg1x-register.h * - * Copyright (C) 2015 Samsung Electronics + * Copyright (C) 2021 Samsung Electronics * - * header file including common register information of s2mpg10, s2mpg11 + * header file including common register information of s2mpg10, s2mpg11, 2mpg12, s2mpg13 */ #ifndef __LINUX_MFD_S2MPG1X_REGISTER_H @@ -12,9 +12,12 @@ #include -#if defined(CONFIG_SOC_GS101) +#if IS_ENABLED(CONFIG_SOC_GS101) #define S2MPG1X_METER_CHANNEL_MAX 8 +#elif IS_ENABLED(CONFIG_SOC_GS201) +#define S2MPG1X_METER_CHANNEL_MAX 12 #endif + #define MASK(width, shift) GENMASK(shift + width - 1, shift) typedef enum { @@ -135,7 +138,7 @@ typedef enum { INT_62P_5HZ, INT_125HZ, INT_250HZ, -#if defined(CONFIG_SOC_GS101) +#if IS_ENABLED(CONFIG_SOC_GS101) INT_500HZ, #endif INT_1000HZ, @@ -144,11 +147,19 @@ typedef enum { } s2mpg1x_int_samp_rate; typedef enum { +#if IS_ENABLED(CONFIG_SOC_GS101) EXT_7P_628125HZ = 0, EXT_15P_25625HZ, EXT_30P_5125HZ, EXT_61P_025HZ, EXT_122P_05HZ, +#elif IS_ENABLED(CONFIG_SOC_GS201) + EXT_7P_8125HZ = 0, + EXT_15P_625HZ, + EXT_31P_25HZ, + EXT_62P_5HZ, + EXT_125HZ, +#endif S2MPG1X_EXT_FREQ_COUNT, S2MPG1X_EXT_FREQ_NONE, } s2mpg1x_ext_samp_rate; @@ -169,6 +180,9 @@ typedef enum { #define S2MPG1X_METER_COUNT_BUF 3 /* 20-bit */ #define S2MPG1X_METER_BUCKEN_BUF 2 +/* MT_TRIM(0xE) MASK */ +#define S2MPG1X_PMETER_MRST_MASK BIT(7) + /* S2MPG1x_METER_CTRL1 */ #define METER_EN_MASK BIT(0) #define EXT_METER_EN_MASK BIT(1) @@ -234,6 +248,8 @@ typedef enum { #define DVS_NLDO_POWER_450mA _IQ30(u32, 0.000686813) #define NLDO_CURRENT_450mA _IQ30(u32, 0.10989011) #define NLDO_POWER_450mA _IQ30(u32, 0.001373626) +#define PLDO_CURRENT_600mA _IQ30(u32, 0.146520147) +#define PLDO_POWER_600mA _IQ30(u32, 0.003663004) #define DVS_NLDO_CURRENT_800mA _IQ30(u32, 0.195360195) #define DVS_NLDO_POWER_800mA _IQ30(u32, 0.001221001) #define NLDO_CURRENT_800mA _IQ30(u32, 0.195360195) @@ -242,7 +258,13 @@ typedef enum { #define PLDO_POWER_800mA _IQ30(u32, 0.004884005) #define NLDO_CURRENT_1000mA _IQ30(u32, 0.244200244) #define NLDO_POWER_1000mA _IQ30(u32, 0.001418251) +#define NLDO_CURRENT_1200mA _IQ30(u32, 0.244200244) +#define NLDO_POWER_1200mA _IQ30(u32, 0.001418251) +#if IS_ENABLED(CONFIG_SOC_GS101) #define EXTERNAL_RESOLUTION_VRAIL _IQ30(u32, 1.3186813) +#elif IS_ENABLED(CONFIG_SOC_GS201) +#define EXTERNAL_RESOLUTION_VRAIL _IQ30(u32, 2.1978021) +#endif #define EXTERNAL_RESOLUTION_VSHUNT _IQ30(u32, 0.0079356982) #define EXTERNAL_RESOLUTION_TRIM BIT(3) // 3 bits diff --git a/include/linux/mfd/samsung/s2mpg1x.h b/include/linux/mfd/samsung/s2mpg1x.h index 3a886f62b77b..49348b43e8b7 100644 --- a/include/linux/mfd/samsung/s2mpg1x.h +++ b/include/linux/mfd/samsung/s2mpg1x.h @@ -9,14 +9,17 @@ #define __LINUX_MFD_S2MPG1X_H enum s2mpg1x_id { -#if defined(CONFIG_SOC_GS101) +#if IS_ENABLED(CONFIG_SOC_GS101) ID_S2MPG10, ID_S2MPG11, +#elif IS_ENABLED(CONFIG_SOC_GS201) + ID_S2MPG12, + ID_S2MPG13, #endif ID_COUNT, }; -#if defined(CONFIG_SOC_GS101) +#if IS_ENABLED(CONFIG_SOC_GS101) #define SWITCH_ID_FUNC(id, func, args...) \ do { \ switch (id) { \ @@ -33,7 +36,24 @@ enum s2mpg1x_id { #include #include +#elif IS_ENABLED(CONFIG_SOC_GS201) +#define SWITCH_ID_FUNC(id, func, args...) \ + do { \ + switch (id) { \ + case ID_S2MPG12: \ + ret = s2mpg12_##func(args); \ + break; \ + case ID_S2MPG13: \ + ret = s2mpg13_##func(args); \ + break; \ + default: \ + break; \ + } \ + } while (0) +#include +#include #endif + static inline int s2mpg1x_update_reg(enum s2mpg1x_id id, struct i2c_client *i2c, u8 reg, u8 val, u8 mask) { @@ -70,4 +90,13 @@ static inline int s2mpg1x_bulk_write(enum s2mpg1x_id id, struct i2c_client *i2c, return ret; } +static inline int s2mpg1x_bulk_read(enum s2mpg1x_id id, struct i2c_client *i2c, + u8 reg, int count, u8 *buf) +{ + int ret = -1; + + SWITCH_ID_FUNC(id, bulk_read, i2c, reg, count, buf); + return ret; +} + #endif /* __LINUX_MFD_S2MPG1X_H */ diff --git a/include/linux/mfd/slg51002.h b/include/linux/mfd/slg51002.h new file mode 100644 index 000000000000..c38b1dd38646 --- /dev/null +++ b/include/linux/mfd/slg51002.h @@ -0,0 +1,698 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * slg51002 driver header + * + * Copyright (C) 2021 Google, LLC. + */ + +#ifndef __LINUX_MFD_SLG51002_H +#define __LINUX_MFD_SLG51002_H + +#include +#include + +/* Registers */ + +#define SLG51002_SYSCTL_PATN_ID_B0 0x1105 +#define SLG51002_SYSCTL_PATN_ID_B1 0x1106 +#define SLG51002_SYSCTL_PATN_ID_B2 0x1107 +#define SLG51002_SYSCTL_SYS_CONF_A 0x1109 +#define SLG51002_SYSCTL_SYS_CONF_D 0x110c +#define SLG51002_SYSCTL_MATRIX_CONF_A 0x110d +#define SLG51002_SYSCTL_MATRIX_CONF_B 0x110e +#define SLG51002_SYSCTL_REFGEN_CONF_C 0x1111 +#define SLG51002_SYSCTL_UVLO_CONF_A 0x1112 +#define SLG51002_SYSCTL_FAULT_LOG1 0x1115 +#define SLG51002_SYSCTL_EVENT 0x1116 +#define SLG51002_SYSCTL_STATUS 0x1117 +#define SLG51002_SYSCTL_IRQ_MASK 0x1118 +#define SLG51002_SYSCTL_TEST_EN 0x1119 +#define SLG51002_SW_TEST_MODE_1 0x111a +#define SLG51002_SW_TEST_MODE_2 0x111b +#define SLG51002_SW_TEST_MODE_3 0x111c +#define SLG51002_SW_TEST_MODE_4 0x111d +#define SLG51002_SYSCTL_DIG_VOUT_FLAG_MUX_SEL0 0x1131 +#define SLG51002_SYSCTL_MEM_STATUS 0x1132 +#define SLG51002_LDO_HP_STARTUP_ILIM 0x1133 +#define SLG51002_I2C_ADDR_SEL 0x113f +#define SLG51002_IO_GPIO1_CONF 0x1500 +#define SLG51002_IO_GPIO2_CONF 0x1501 +#define SLG51002_IO_GPIO3_CONF 0x1502 +#define SLG51002_IO_GPIO4_CONF 0x1503 +#define SLG51002_IO_GPIO5_CONF 0x1504 +#define SLG51002_IO_GPIO6_CONF 0x1505 +#define SLG51002_IO_GPIO_STATUS 0x1506 +#define SLG51002_IO_GPIO1_MODE 0x1507 +#define SLG51002_IO_GPIO2_MODE 0x1508 +#define SLG51002_IO_GPIO3_MODE 0x1509 +#define SLG51002_IO_GPIO4_MODE 0x150a +#define SLG51002_IO_GPIO_QCHG 0x150b +#define SLG51002_LUTARRAY_LUT_VAL_0 0x1600 +#define SLG51002_LUTARRAY_LUT_VAL_1 0x1601 +#define SLG51002_LUTARRAY_LUT_VAL_2 0x1602 +#define SLG51002_LUTARRAY_LUT_VAL_3 0x1603 +#define SLG51002_LUTARRAY_LUT_VAL_4 0x1604 +#define SLG51002_LUTARRAY_LUT_VAL_5 0x1605 +#define SLG51002_LUTARRAY_LUT_VAL_6 0x1606 +#define SLG51002_LUTARRAY_LUT_VAL_7 0x1607 +#define SLG51002_LUTARRAY_LUT_VAL_8 0x1608 +#define SLG51002_LUTARRAY_LUT_VAL_9 0x1609 +#define SLG51002_LUTARRAY_LUT_VAL_10 0x160a +#define SLG51002_LUTARRAY_LUT_VAL_11 0x160b +#define SLG51002_MUXARRAY_INPUT_SEL_0 0x1700 +#define SLG51002_MUXARRAY_INPUT_SEL_1 0x1701 +#define SLG51002_MUXARRAY_INPUT_SEL_2 0x1702 +#define SLG51002_MUXARRAY_INPUT_SEL_3 0x1703 +#define SLG51002_MUXARRAY_INPUT_SEL_4 0x1704 +#define SLG51002_MUXARRAY_INPUT_SEL_5 0x1705 +#define SLG51002_MUXARRAY_INPUT_SEL_6 0x1706 +#define SLG51002_MUXARRAY_INPUT_SEL_7 0x1707 +#define SLG51002_MUXARRAY_INPUT_SEL_8 0x1708 +#define SLG51002_MUXARRAY_INPUT_SEL_9 0x1709 +#define SLG51002_MUXARRAY_INPUT_SEL_10 0x170a +#define SLG51002_MUXARRAY_INPUT_SEL_11 0x170b +#define SLG51002_MUXARRAY_INPUT_SEL_12 0x170c +#define SLG51002_MUXARRAY_INPUT_SEL_13 0x170d +#define SLG51002_MUXARRAY_INPUT_SEL_14 0x170e +#define SLG51002_MUXARRAY_INPUT_SEL_15 0x170f +#define SLG51002_MUXARRAY_INPUT_SEL_16 0x1710 +#define SLG51002_MUXARRAY_INPUT_SEL_17 0x1711 +#define SLG51002_MUXARRAY_INPUT_SEL_18 0x1712 +#define SLG51002_MUXARRAY_INPUT_SEL_19 0x1713 +#define SLG51002_MUXARRAY_INPUT_SEL_20 0x1714 +#define SLG51002_MUXARRAY_INPUT_SEL_21 0x1715 +#define SLG51002_MUXARRAY_INPUT_SEL_22 0x1716 +#define SLG51002_MUXARRAY_INPUT_SEL_23 0x1717 +#define SLG51002_MUXARRAY_INPUT_SEL_24 0x1718 +#define SLG51002_MUXARRAY_INPUT_SEL_25 0x1719 +#define SLG51002_MUXARRAY_INPUT_SEL_26 0x171a +#define SLG51002_MUXARRAY_INPUT_SEL_27 0x171b +#define SLG51002_MUXARRAY_INPUT_SEL_28 0x171c +#define SLG51002_MUXARRAY_INPUT_SEL_29 0x171d +#define SLG51002_MUXARRAY_INPUT_SEL_30 0x171e +#define SLG51002_MUXARRAY_INPUT_SEL_31 0x171f +#define SLG51002_MUXARRAY_INPUT_SEL_32 0x1720 +#define SLG51002_MUXARRAY_INPUT_SEL_33 0x1721 +#define SLG51002_MUXARRAY_INPUT_SEL_34 0x1722 +#define SLG51002_MUXARRAY_INPUT_SEL_35 0x1723 +#define SLG51002_MUXARRAY_INPUT_SEL_36 0x1724 +#define SLG51002_MUXARRAY_INPUT_SEL_37 0x1725 +#define SLG51002_MUXARRAY_INPUT_SEL_38 0x1726 +#define SLG51002_MUXARRAY_INPUT_SEL_39 0x1727 +#define SLG51002_MUXARRAY_INPUT_SEL_40 0x1728 +#define SLG51002_MUXARRAY_INPUT_SEL_41 0x1729 +#define SLG51002_MUXARRAY_INPUT_SEL_42 0x172a +#define SLG51002_MUXARRAY_INPUT_SEL_43 0x172b +#define SLG51002_MUXARRAY_INPUT_SEL_44 0x172c +#define SLG51002_MUXARRAY_INPUT_SEL_45 0x172d +#define SLG51002_MUXARRAY_INPUT_SEL_46 0x172e +#define SLG51002_MUXARRAY_INPUT_SEL_47 0x172f +#define SLG51002_MUXARRAY_INPUT_SEL_48 0x1730 +#define SLG51002_MUXARRAY_INPUT_SEL_49 0x1731 +#define SLG51002_MUXARRAY_INPUT_SEL_50 0x1732 +#define SLG51002_MUXARRAY_INPUT_SEL_51 0x1733 +#define SLG51002_MUXARRAY_INPUT_SEL_52 0x1734 +#define SLG51002_MUXARRAY_INPUT_SEL_53 0x1735 +#define SLG51002_MUXARRAY_INPUT_SEL_54 0x1736 +#define SLG51002_MUXARRAY_INPUT_SEL_55 0x1737 +#define SLG51002_MUXARRAY_INPUT_SEL_56 0x1738 +#define SLG51002_MUXARRAY_INPUT_SEL_57 0x1739 +#define SLG51002_MUXARRAY_INPUT_SEL_58 0x173a +#define SLG51002_MUXARRAY_INPUT_SEL_59 0x173b +#define SLG51002_MUXARRAY_INPUT_SEL_60 0x173c +#define SLG51002_MUXARRAY_INPUT_SEL_61 0x173d +#define SLG51002_MUXARRAY_INPUT_SEL_62 0x173e +#define SLG51002_MUXARRAY_INPUT_SEL_63 0x173f +#define SLG51002_PWRSEQ_RESOURCE_EN_0 0x1900 +#define SLG51002_PWRSEQ_RESOURCE_EN_1 0x1901 +#define SLG51002_PWRSEQ_RESOURCE_EN_2 0x1902 +#define SLG51002_PWRSEQ_RESOURCE_EN_3 0x1903 +#define SLG51002_PWRSEQ_RESOURCE_EN_4 0x1904 +#define SLG51002_PWRSEQ_RESOURCE_EN_5 0x1905 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910 +#define SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911 +#define SLG51002_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912 +#define SLG51002_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913 +#define SLG51002_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914 +#define SLG51002_PWRSEQ_INPUT_SENSE_CONF_A 0x1915 +#define SLG51002_PWRSEQ_INPUT_SENSE_CONF_B 0x1916 +#define SLG51002_LDO1_VSEL 0x2000 +#define SLG51002_LDO1_MINV 0x2060 +#define SLG51002_LDO1_MAXV 0x2061 +#define SLG51002_LDO1_TRIM2 0x2063 +#define SLG51002_LDO1_CONF1 0x2064 +#define SLG51002_LDO1_CONF2 0x2065 +#define SLG51002_LDO1_VSEL_ACTUAL 0x2066 +#define SLG51002_LDO1_CONF3 0x2067 +#define SLG51002_LDO1_EVENT 0x20c0 +#define SLG51002_LDO1_STATUS 0x20c1 +#define SLG51002_LDO1_IRQ_MASK 0x20c2 +#define SLG51002_LDO2_VSEL 0x2200 +#define SLG51002_LDO2_MINV 0x2260 +#define SLG51002_LDO2_MAXV 0x2261 +#define SLG51002_LDO2_TRIM2 0x2263 +#define SLG51002_LDO2_CONF1 0x2264 +#define SLG51002_LDO2_CONF2 0x2265 +#define SLG51002_LDO2_VSEL_ACTUAL 0x2266 +#define SLG51002_LDO2_CONF3 0x2267 +#define SLG51002_LDO2_EVENT 0x22c0 +#define SLG51002_LDO2_STATUS 0x22c1 +#define SLG51002_LDO2_IRQ_MASK 0x22c2 +#define SLG51002_LDO3_VSEL 0x2300 +#define SLG51002_LDO3_MINV 0x2360 +#define SLG51002_LDO3_MAXV 0x2361 +#define SLG51002_LDO3_TRIM2 0x2363 +#define SLG51002_LDO3_CONF1 0x2364 +#define SLG51002_LDO3_CONF2 0x2365 +#define SLG51002_LDO3_VSEL_ACTUAL 0x2366 +#define SLG51002_LDO3_CONF3 0x2367 +#define SLG51002_LDO3_EVENT 0x23c0 +#define SLG51002_LDO3_STATUS 0x23c1 +#define SLG51002_LDO3_IRQ_MASK 0x23c2 +#define SLG51002_LDO4_VSEL 0x2500 +#define SLG51002_LDO4_MINV 0x2560 +#define SLG51002_LDO4_MAXV 0x2561 +#define SLG51002_LDO4_TRIM2 0x2563 +#define SLG51002_LDO4_CONF1 0x2564 +#define SLG51002_LDO4_CONF2 0x2565 +#define SLG51002_LDO4_VSEL_ACTUAL 0x2566 +#define SLG51002_LDO4_CONF3 0x2567 +#define SLG51002_LDO4_CONF4 0x2568 +#define SLG51002_LDO4_EVENT 0x25c0 +#define SLG51002_LDO4_STATUS 0x25c1 +#define SLG51002_LDO4_IRQ_MASK 0x25c2 +#define SLG51002_LDO5_VSEL 0x2700 +#define SLG51002_LDO5_MINV 0x2760 +#define SLG51002_LDO5_MAXV 0x2761 +#define SLG51002_LDO5_TRIM2 0x2763 +#define SLG51002_LDO5_CONF1 0x2764 +#define SLG51002_LDO5_CONF2 0x2765 +#define SLG51002_LDO5_VSEL_ACTUAL 0x2766 +#define SLG51002_LDO5_CONF3 0x2767 +#define SLG51002_LDO5_CONF4 0x2768 +#define SLG51002_LDO5_EVENT 0x27c0 +#define SLG51002_LDO5_STATUS 0x27c1 +#define SLG51002_LDO5_IRQ_MASK 0x27c2 +#define SLG51002_LDO6_VSEL 0x2900 +#define SLG51002_LDO6_MINV 0x2960 +#define SLG51002_LDO6_MAXV 0x2961 +#define SLG51002_LDO6_TRIM2 0x2963 +#define SLG51002_LDO6_TRIM3 0x2964 +#define SLG51002_LDO6_CONF1 0x2965 +#define SLG51002_LDO6_CONF2 0x2966 +#define SLG51002_LDO6_VSEL_ACTUAL 0x2967 +#define SLG51002_LDO6_CONF3 0x2968 +#define SLG51002_LDO6_EVENT 0x29c0 +#define SLG51002_LDO6_STATUS 0x29c1 +#define SLG51002_LDO6_IRQ_MASK 0x29c2 +#define SLG51002_LDO7_VSEL 0x3100 +#define SLG51002_LDO7_MINV 0x3160 +#define SLG51002_LDO7_MAXV 0x3161 +#define SLG51002_LDO7_TRIM2 0x3163 +#define SLG51002_LDO7_TRIM3 0x3164 +#define SLG51002_LDO7_CONF1 0x3165 +#define SLG51002_LDO7_CONF2 0x3166 +#define SLG51002_LDO7_VSEL_ACTUAL 0x3167 +#define SLG51002_LDO7_CONF3 0x3168 +#define SLG51002_LDO7_EVENT 0x31c0 +#define SLG51002_LDO7_STATUS 0x31c1 +#define SLG51002_LDO7_IRQ_MASK 0x31c2 +#define SLG51002_LDO8_VSEL 0x3200 +#define SLG51002_LDO8_MINV 0x3260 +#define SLG51002_LDO8_MAXV 0x3261 +#define SLG51002_LDO8_TRIM2 0x3263 +#define SLG51002_LDO8_TRIM3 0x3264 +#define SLG51002_LDO8_CONF1 0x3265 +#define SLG51002_LDO8_CONF2 0x3266 +#define SLG51002_LDO8_VSEL_ACTUAL 0x3267 +#define SLG51002_LDO8_CONF3 0x3268 +#define SLG51002_LDO8_EVENT 0x32c0 +#define SLG51002_LDO8_STATUS 0x32c1 +#define SLG51002_LDO8_IRQ_MASK 0x32c2 +#define SLG51000_LDO_DUMMY_VSEL 0x3200 +#define SLG51000_LDO_DUMMY_MINV 0x3260 +#define SLG51002_OTP_EVENT 0x782b +#define SLG51002_OTP_IRQ_MASK 0x782d +#define SLG51002_OTP_LOCK_OTP_PROG 0x78fe +#define SLG51002_OTP_LOCK_CTRL 0x78ff +#define SLG51002_LOCK_GLOBAL_LOCK_CTRL1 0x8000 +#define SLG51002_LOCK_GLOBAL_LOCK_CTRL2 0x8001 + +/* Register Bit Fields */ + +/* SLG51002_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */ +#define SLG51002_PATTERN_ID_BYTE0_SHIFT 0 +#define SLG51002_PATTERN_ID_BYTE0_MASK (0xff << 0) + +/* SLG51002_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */ +#define SLG51002_PATTERN_ID_BYTE1_SHIFT 0 +#define SLG51002_PATTERN_ID_BYTE1_MASK (0xff << 0) + +/* SLG51002_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */ +#define SLG51002_PATTERN_ID_BYTE2_SHIFT 0 +#define SLG51002_PATTERN_ID_BYTE2_MASK (0xff << 0) + +/* SLG51002_SYSCTL_SYS_CONF_A = 0x1109 */ +#define SLG51002_I2C_ADDRESS_SHIFT 0 +#define SLG51002_I2C_ADDRESS_MASK (0x7f << 0) +#define SLG51002_I2C_DISABLE_SHIFT 7 +#define SLG51002_I2C_DISABLE_MASK BIT(7) + +/* SLG51002_SYSCTL_SYS_CONF_D = 0x110c */ +#define SLG51002_CS_T_DEB_SHIFT 6 +#define SLG51002_CS_T_DEB_MASK (0x03 << 6) +#define SLG51002_I2C_CLR_MODE_SHIFT 5 +#define SLG51002_I2C_CLR_MODE_MASK BIT(5) + +/* SLG51002_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */ +#define SLG51002_RESOURCE_CTRL_SHIFT 0 +#define SLG51002_RESOURCE_CTRL_MASK (0xff << 0) + +/* SLG51002_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */ +#define SLG51002_MATRIX_EVENT_SENSE_SHIFT 0 +#define SLG51002_MATRIX_EVENT_SENSE_MASK (0x07 << 0) + +/* SLG51002_SYSCTL_REFGEN_CONF_C = 0x1111 */ +#define SLG51002_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2 +#define SLG51002_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2) +#define SLG51002_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0 +#define SLG51002_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0) + +/* SLG51002_SYSCTL_UVLO_CONF_A = 0x1112 */ +#define SLG51002_VMON_UVLO_SEL_THR_SHIFT 0 +#define SLG51002_VMON_UVLO_SEL_THR_MASK (0x1f << 0) + +/* SLG51002_SYSCTL_FAULT_LOG1 = 0x1115 */ +#define SLG51002_FLT_POR_SHIFT 5 +#define SLG51002_FLT_POR_MASK BIT(5) +#define SLG51002_FLT_RST_SHIFT 4 +#define SLG51002_FLT_RST_MASK BIT(4) +#define SLG51002_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2 +#define SLG51002_FLT_POWER_SEQ_CRASH_REQ_MASK BIT(2) +#define SLG51002_FLT_OVER_TEMP_SHIFT 1 +#define SLG51002_FLT_OVER_TEMP_MASK BIT(1) + +/* SLG51002_SYSCTL_EVENT = 0x1116 */ +#define SLG51002_EVT_MATRIX_SHIFT 1 +#define SLG51002_EVT_MATRIX_MASK BIT(1) +#define SLG51002_EVT_HIGH_TEMP_WARN_SHIFT 0 +#define SLG51002_EVT_HIGH_TEMP_WARN_MASK BIT(0) + +/* SLG51002_SYSCTL_STATUS = 0x1117 */ +#define SLG51002_STA_MATRIX_SHIFT 1 +#define SLG51002_STA_MATRIX_MASK BIT(1) +#define SLG51002_STA_HIGH_TEMP_WARN_SHIFT 0 +#define SLG51002_STA_HIGH_TEMP_WARN_MASK BIT(0) + +/* SLG51002_SYSCTL_IRQ_MASK = 0x1118 */ +#define SLG51002_IRQ_MATRIX_SHIFT 1 +#define SLG51002_IRQ_MATRIX_MASK BIT(1) +#define SLG51002_IRQ_HIGH_TEMP_WARN_SHIFT 0 +#define SLG51002_IRQ_HIGH_TEMP_WARN_MASK BIT(0) + +/* SLG51002_SYSCTL_TEST_EN = 0x1119 */ +#define SLG51002_TEST_EN_OFF 0x00 +#define SLG51002_TEST_EN_ON_MASK 0x04 + +/* SLG51002_SW_TEST_MODE = 0x111a */ +#define SLG51002_SW_TEST_MODE_1_ON 0x45 +#define SLG51002_SW_TEST_MODE_1_OFF 0x00 +#define SLG51002_SW_TEST_MODE_2_ON 0x53 +#define SLG51002_SW_TEST_MODE_2_OFF 0x00 +#define SLG51002_SW_TEST_MODE_3_ON 0x54 +#define SLG51002_SW_TEST_MODE_3_OFF 0x00 +#define SLG51002_SW_TEST_MODE_4_ON 0x4d +#define SLG51002_SW_TEST_MODE_4_OFF 0x00 + +/* SLG51002_LDO_HP_STARTUP_ILIM = 0x1133 */ +/* unset [7:5] and keep [4:0] for original value */ +#define SLG51002_LDO_HP_STARTUP_ILIM_ORI_MASK (0xFF >> 3) +/* set [7:5] for 240mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_0_MASK (0x00 << 5) +/* set [7:5] for 11mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_1_MASK BIT(5) +/* set [7:5] for 31mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_2_MASK (0x02 << 5) +/* set [7:5] for 48mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_3_MASK (0x03 << 5) +/* set [7:5] for 72mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_4_MASK (0x04 << 5) +/* set [7:5] for 91mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_5_MASK (0x05 << 5) +/* set [7:5] for 116mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_6_MASK (0x06 << 5) +/* set [7:5] for 136mA */ +#define SLG51002_LDO_HP_STARTUP_ILIM_7_MASK (0x07 << 5) + +/* SLG51002_IO_GPIO1_CONF ~ SLG51002_IO_GPIO5_CONF = + * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504 + */ +#define SLG51002_GPIO_DIR_SHIFT 7 +#define SLG51002_GPIO_DIR_MASK BIT(7) +#define SLG51002_GPIO_SENS_SHIFT 5 +#define SLG51002_GPIO_SENS_MASK (0x03 << 5) +#define SLG51002_GPIO_INVERT_SHIFT 4 +#define SLG51002_GPIO_INVERT_MASK BIT(4) +#define SLG51002_GPIO_BYP_SHIFT 3 +#define SLG51002_GPIO_BYP_MASK BIT(3) +#define SLG51002_GPIO_T_DEB_SHIFT 1 +#define SLG51002_GPIO_T_DEB_MASK (0x03 << 1) +#define SLG51002_GPIO_LEVEL_SHIFT 0 +#define SLG51002_GPIO_LEVEL_MASK BIT(0) + +/* SLG51002_IO_GPIO6_CONF = 0x1505 */ +#define SLG51002_GPIO6_SENS_SHIFT 5 +#define SLG51002_GPIO6_SENS_MASK (0x03 << 5) +#define SLG51002_GPIO6_INVERT_SHIFT 4 +#define SLG51002_GPIO6_INVERT_MASK BIT(4) +#define SLG51002_GPIO6_T_DEB_SHIFT 1 +#define SLG51002_GPIO6_T_DEB_MASK (0x03 << 1) +#define SLG51002_GPIO6_LEVEL_SHIFT 0 +#define SLG51002_GPIO6_LEVEL_MASK BIT(0) + +/* SLG51002_IO_GPIO_STATUS = 0x1506 */ +#define SLG51002_GPIO6_STATUS_SHIFT 5 +#define SLG51002_GPIO6_STATUS_MASK BIT(5) +#define SLG51002_GPIO5_STATUS_SHIFT 4 +#define SLG51002_GPIO5_STATUS_MASK BIT(4) +#define SLG51002_GPIO4_STATUS_SHIFT 3 +#define SLG51002_GPIO4_STATUS_MASK BIT(3) +#define SLG51002_GPIO3_STATUS_SHIFT 2 +#define SLG51002_GPIO3_STATUS_MASK BIT(2) +#define SLG51002_GPIO2_STATUS_SHIFT 1 +#define SLG51002_GPIO2_STATUS_MASK BIT(1) +#define SLG51002_GPIO1_STATUS_SHIFT 0 +#define SLG51002_GPIO1_STATUS_MASK BIT(0) + +/* SLG51002_LUTARRAY_LUT_VAL_0 ~ SLG51002_LUTARRAY_LUT_VAL_11 + * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605, + * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b + */ +#define SLG51002_LUT_VAL_SHIFT 0 +#define SLG51002_LUT_VAL_MASK (0xff << 0) + +/* SLG51002_MUXARRAY_INPUT_SEL_0 ~ SLG51002_MUXARRAY_INPUT_SEL_63 + * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705, + * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b, + * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711, + * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717, + * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d, + * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723, + * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729, + * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f, + */ +#define SLG51002_INPUT_SEL_SHIFT 0 +#define SLG51002_INPUT_SEL_MASK (0x3f << 0) + +/* SLG51002_PWRSEQ_RESOURCE_EN_0 ~ SLG51002_PWRSEQ_RESOURCE_EN_5 + * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905 + */ +#define SLG51002_RESOURCE_EN_DOWN0_SHIFT 4 +#define SLG51002_RESOURCE_EN_DOWN0_MASK (0x07 << 4) +#define SLG51002_RESOURCE_EN_UP0_SHIFT 0 +#define SLG51002_RESOURCE_EN_UP0_MASK (0x07 << 0) + +/* SLG51002_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51002_PWRSEQ_SLOT_TIME_MIN_UP5 + * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910 + */ +#define SLG51002_SLOT_TIME_MIN_UP_SHIFT 0 +#define SLG51002_SLOT_TIME_MIN_UP_MASK (0xff << 0) + +/* SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51002_PWRSEQ_SLOT_TIME_MIN_DOWN5 + * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911 + */ +#define SLG51002_SLOT_TIME_MIN_DOWN_SHIFT 0 +#define SLG51002_SLOT_TIME_MIN_DOWN_MASK (0xff << 0) + +/* SLG51002_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51002_PWRSEQ_SLOT_TIME_MAX_CONF_C + * 0x1912, 0x1913, 0x1914 + */ +#define SLG51002_SLOT_TIME_MAX_DOWN1_SHIFT 6 +#define SLG51002_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6) +#define SLG51002_SLOT_TIME_MAX_UP1_SHIFT 4 +#define SLG51002_SLOT_TIME_MAX_UP1_MASK (0x03 << 4) +#define SLG51002_SLOT_TIME_MAX_DOWN0_SHIFT 2 +#define SLG51002_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2) +#define SLG51002_SLOT_TIME_MAX_UP0_SHIFT 0 +#define SLG51002_SLOT_TIME_MAX_UP0_MASK (0x03 << 0) + +/* SLG51002_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */ +#define SLG51002_TRIG_UP_SENSE_SHIFT 6 +#define SLG51002_TRIG_UP_SENSE_MASK BIT(6) +#define SLG51002_UP_EN_SENSE5_SHIFT 5 +#define SLG51002_UP_EN_SENSE5_MASK BIT(5) +#define SLG51002_UP_EN_SENSE4_SHIFT 4 +#define SLG51002_UP_EN_SENSE4_MASK BIT(4) +#define SLG51002_UP_EN_SENSE3_SHIFT 3 +#define SLG51002_UP_EN_SENSE3_MASK BIT(3) +#define SLG51002_UP_EN_SENSE2_SHIFT 2 +#define SLG51002_UP_EN_SENSE2_MASK BIT(2) +#define SLG51002_UP_EN_SENSE1_SHIFT 1 +#define SLG51002_UP_EN_SENSE1_MASK BIT(1) +#define SLG51002_UP_EN_SENSE0_SHIFT 0 +#define SLG51002_UP_EN_SENSE0_MASK BIT(0) + +/* SLG51002_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */ +#define SLG51002_CRASH_DETECT_SENSE_SHIFT 7 +#define SLG51002_CRASH_DETECT_SENSE_MASK BIT(7) +#define SLG51002_TRIG_DOWN_SENSE_SHIFT 6 +#define SLG51002_TRIG_DOWN_SENSE_MASK BIT(6) +#define SLG51002_DOWN_EN_SENSE5_SHIFT 5 +#define SLG51002_DOWN_EN_SENSE5_MASK BIT(5) +#define SLG51002_DOWN_EN_SENSE4_SHIFT 4 +#define SLG51002_DOWN_EN_SENSE4_MASK BIT(4) +#define SLG51002_DOWN_EN_SENSE3_SHIFT 3 +#define SLG51002_DOWN_EN_SENSE3_MASK BIT(3) +#define SLG51002_DOWN_EN_SENSE2_SHIFT 2 +#define SLG51002_DOWN_EN_SENSE2_MASK BIT(2) +#define SLG51002_DOWN_EN_SENSE1_SHIFT 1 +#define SLG51002_DOWN_EN_SENSE1_MASK BIT(1) +#define SLG51002_DOWN_EN_SENSE0_SHIFT 0 +#define SLG51002_DOWN_EN_SENSE0_MASK BIT(0) + +/* SLG51002_LDO1_VSEL ~ SLG51002_LDO7_VSEL = + * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100 + */ +#define SLG51002_VSEL_SHIFT 0 +#define SLG51002_VSEL_MASK (0xff << 0) + +/* SLG51002_LDO1_MINV ~ SLG51002_LDO7_MINV = + * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160 + */ +#define SLG51002_MINV_SHIFT 0 +#define SLG51002_MINV_MASK (0xff << 0) + +/* SLG51002_LDO1_MAXV ~ SLG51002_LDO7_MAXV = + * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161 + */ +#define SLG51002_MAXV_SHIFT 0 +#define SLG51002_MAXV_MASK (0xff << 0) + +/* SLG51002_LDO1_MISC1 = 0x2064, SLG51002_LDO2_MISC1 = 0x2264 */ +#define SLG51002_SEL_VRANGE_SHIFT 0 +#define SLG51002_SEL_VRANGE_MASK BIT(0) + +/* SLG51002_LDO1_VSEL_ACTUAL ~ SLG51002_LDO7_VSEL_ACTUAL = + * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166 + */ +#define SLG51002_VSEL_ACTUAL_SHIFT 0 +#define SLG51002_VSEL_ACTUAL_MASK (0xff << 0) + +/* SLG51002_LDO1_EVENT ~ SLG51002_LDO7_EVENT = + * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0 + */ +#define SLG51002_EVT_ILIM_FLAG_SHIFT 0 +#define SLG51002_EVT_ILIM_FLAG_MASK BIT(0) +#define SLG51002_EVT_VOUT_OK_FLAG_SHIFT 1 +#define SLG51002_EVT_VOUT_OK_FLAG_MASK BIT(1) + +/* SLG51002_LDO1_STATUS ~ SLG51002_LDO7_STATUS = + * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1 + */ +#define SLG51002_STA_ILIM_FLAG_SHIFT 0 +#define SLG51002_STA_ILIM_FLAG_MASK BIT(0) +#define SLG51002_STA_VOUT_OK_FLAG_SHIFT 1 +#define SLG51002_STA_VOUT_OK_FLAG_MASK BIT(1) + +/* SLG51002_LDO1_IRQ_MASK ~ SLG51002_LDO7_IRQ_MASK = + * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2 + */ +#define SLG51002_IRQ_ILIM_FLAG_SHIFT 0 +#define SLG51002_IRQ_ILIM_FLAG_MASK BIT(0) + +/* SLG51002_LDO3_CONF1 ~ SLG51002_LDO7_CONF1 = + * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164 + */ +#define SLG51002_SEL_START_ILIM_SHIFT 0 +#define SLG51002_SEL_START_ILIM_MASK (0x7f << 0) + +/* SLG51002_LDO3_CONF2 ~ SLG51002_LDO7_CONF2 = + * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165 + */ +#define SLG51002_SEL_FUNC_ILIM_SHIFT 0 +#define SLG51002_SEL_FUNC_ILIM_MASK (0x7f << 0) + +/* SLG51002_LDO5_TRIM2 = 0x2763, SLG51002_LDO6_TRIM2 = 0x2963 */ +#define SLG51002_SEL_BYP_SLEW_RATE_SHIFT 2 +#define SLG51002_SEL_BYP_SLEW_RATE_MASK (0x03 << 2) +#define SLG51002_SEL_BYP_VGATE_SHIFT 1 +#define SLG51002_SEL_BYP_VGATE_MASK BIT(1) +#define SLG51002_SEL_BYP_MODE_SHIFT 0 +#define SLG51002_SEL_BYP_MODE_MASK BIT(0) + +/* + * SLG51002_LDO1_TRIM2 = 0x2063, SLG51002_LDO2_TRIM2 = 0x2263, + * SLG51002_LDO3_TRIM2 = 0x2363, SLG51002_LDO4_TRIM2 = 0x2563, + * SLG51002_LDO5_TRIM3 = 0x2764, SLG51002_LDO6_TRIM3 = 0x2964, + * SLG51002_LDO7_TRIM2 = 0x3163 + */ +#define SLG51002_ILIM_FLAG_DEB_SHIFT 3 +#define SLG51002_ILIM_FLAG_DEB_MASK (0x03 << 3) +#define SLG51002_VOUT_OK_DEB_SHIFT 1 +#define SLG51002_VOUT_OK_DEB_MASK (0x03 << 1) + +/* SLG51002_OTP_EVENT = 0x782b */ +#define SLG51002_EVT_CRC_SHIFT 0 +#define SLG51002_EVT_CRC_MASK BIT(0) + +/* SLG51002_OTP_IRQ_MASK = 0x782d */ +#define SLG51002_IRQ_CRC_SHIFT 0 +#define SLG51002_IRQ_CRC_MASK BIT(0) + +/* SLG51002_OTP_LOCK_OTP_PROG = 0x78fe */ +#define SLG51002_LOCK_OTP_PROG_SHIFT 0 +#define SLG51002_LOCK_OTP_PROG_MASK BIT(0) + +/* SLG51002_OTP_LOCK_CTRL = 0x78ff */ +#define SLG51002_LOCK_DFT_SHIFT 1 +#define SLG51002_LOCK_DFT_MASK BIT(1) +#define SLG51002_LOCK_RWT_SHIFT 0 +#define SLG51002_LOCK_RWT_MASK BIT(0) + +/* SLG51002_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */ +#define SLG51002_LDO7_LOCK_SHIFT 7 +#define SLG51002_LDO7_LOCK_MASK BIT(7) +#define SLG51002_LDO6_LOCK_SHIFT 6 +#define SLG51002_LDO6_LOCK_MASK BIT(6) +#define SLG51002_LDO5_LOCK_SHIFT 5 +#define SLG51002_LDO5_LOCK_MASK BIT(5) +#define SLG51002_LDO4_LOCK_SHIFT 4 +#define SLG51002_LDO4_LOCK_MASK BIT(4) +#define SLG51002_LDO3_LOCK_SHIFT 3 +#define SLG51002_LDO3_LOCK_MASK BIT(3) +#define SLG51002_LDO2_LOCK_SHIFT 2 +#define SLG51002_LDO2_LOCK_MASK BIT(2) +#define SLG51002_LDO1_LOCK_SHIFT 1 +#define SLG51002_LDO1_LOCK_MASK BIT(1) + +/* Customized control register masks */ +#define GPIO1_CTRL SLG51002_MUXARRAY_INPUT_SEL_16 +#define GPIO2_CTRL SLG51002_MUXARRAY_INPUT_SEL_17 +#define GPIO3_CTRL SLG51002_MUXARRAY_INPUT_SEL_18 +#define GPIO4_CTRL SLG51002_MUXARRAY_INPUT_SEL_19 + +#define SLG51002_PHYSICAL_GPIO_NR 4 +#define SLEEP_10000_USEC 10000 +#define SLEEP_RANGE_USEC 1000 + +/* PMIC OTP revisions */ +#define REVISION_AA 0xAFDA01 +#define REVISION_AB 0xB13103 + +enum slg51002_regulators { + SLG51002_REGULATOR_LDO1 = 0, + SLG51002_REGULATOR_LDO2, + SLG51002_REGULATOR_LDO3, + SLG51002_REGULATOR_LDO4, + SLG51002_REGULATOR_LDO5, + SLG51002_REGULATOR_LDO6, + SLG51002_REGULATOR_LDO7, + SLG51002_REGULATOR_LDO8, + SLG51002_REGULATOR_GPIO1, + SLG51002_REGULATOR_GPIO2, + SLG51002_REGULATOR_GPIO3, + SLG51002_REGULATOR_GPIO4, + SLG51002_MAX_REGULATORS, +}; + +/* + * GPIOs and sequences for mode SLG51002_OP_MODE_DEFAULT and + * SLG51002_OP_MODE_SEQ_GPIO + */ +enum { + SLG51002_GPIO1, + SLG51002_GPIO2, + SLG51002_GPIO3, + SLG51002_GPIO4, + SLG51002_SEQ1, + SLG51002_SEQ2, + SLG51002_SEQ3, + SLG51002_SEQ4, + SLG51002_GPIO_NR, +}; + +/* Sequences for mode SLG51002_OP_MODE_SEQ_GENERIC */ +enum { + SLG51002_GENERIC_SEQ0, + SLG51002_GENERIC_SEQ1, + SLG51002_GENERIC_SEQ2, + SLG51002_GENERIC_SEQ3, + SLG51002_GENERIC_SEQ4, + SLG51002_GENERIC_SEQ5, + SLG51002_GENERIC_SEQ6, + SLG51002_GENERIC_SEQ7, + SLG51002_GENERIC_SEQ_NR, +}; + +/* Operation mode */ +enum { + SLG51002_OP_MODE_LDO_GPIO, + SLG51002_OP_MODE_CONTROL_REG, + SLG51002_OP_MODE_LDO_ONLY, + SLG51002_OP_MODE_SEQ_GPIO, + SLG51002_OP_MODE_SEQ_GENERIC, +}; + +struct slg51002_dev { + struct device *dev; + struct regmap *regmap, *i2c_regmap; + struct regulator_desc *rdesc[SLG51002_MAX_REGULATORS]; + struct regulator_dev *rdev[SLG51002_MAX_REGULATORS]; + struct gpio_desc *cs_gpiod; + struct workqueue_struct *slg51002_wq; + struct work_struct slg51002_work; + int chip_irq; + int chip_cs_pin; + int chip_buck_pin; + int chip_bb_pin; + int chip_pu_pin; + int chip_id; + u32 op_mode; + bool chip_always_on; + bool gpio_op_on_sw_test_mode; + + bool is_power_on; + struct timer_list timer; + struct work_struct timeout_work; + struct mutex pwr_lock; + + int (*enter_sw_test_mode)(struct regmap *map); + int (*exit_sw_test_mode)(struct regmap *map); +}; + +struct slg51002_register_setting { + unsigned int addr; + unsigned int val; +}; + +#endif /* __LINUX_MFD_SLG51002_H */ diff --git a/include/linux/modem_notifier.h b/include/linux/modem_notifier.h index 8ab7d13a1a4c..4204280cd5b0 100644 --- a/include/linux/modem_notifier.h +++ b/include/linux/modem_notifier.h @@ -11,6 +11,7 @@ enum modem_event { MODEM_EVENT_RESET = 1, MODEM_EVENT_EXIT, MODEM_EVENT_ONLINE = 4, + MODEM_EVENT_OFFLINE = 5, MODEM_EVENT_WATCHDOG = 9, }; diff --git a/include/linux/s2mpg12-key.h b/include/linux/s2mpg12-key.h new file mode 100644 index 000000000000..ed41a3b45d8d --- /dev/null +++ b/include/linux/s2mpg12-key.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * s2mpg12-key.h + * + * Copyright (C) 2015 Samsung Electronics + * + * header file including key information of s2mpg12 + */ + +#ifndef _POWER_KEYS_H +#define _POWER_KEYS_H + +struct device; + +struct power_keys_button { + /* Configuration parameters */ + unsigned int code; /* input event code (KEY_*, SW_*) */ + int gpio; /* -1 if this key does not support gpio */ + int active_low; + const char *desc; + unsigned int type; /* input event type (EV_KEY, EV_SW, EV_ABS) */ + int wakeup; + int always_wakeup; /* configure the button as a wake-up source */ + int debounce_interval; /* debounce ticks interval in msecs */ + bool can_disable; + int value; /* axis value for EV_ABS */ + unsigned int irq; /* Irq number in case of interrupt keys */ +}; + +struct power_keys_platform_data { + struct power_keys_button *buttons; + int nbuttons; + unsigned int poll_interval; /* polling interval in msecs for polling driver only */ + unsigned int rep:1; /* enable input subsystem auto repeat */ + + int (*enable)(struct device *dev); + void (*disable)(struct device *dev); + const char *name; /* input device name */ +}; + +#endif diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h index fa75f325dad5..cea4bdfd0f05 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -55,8 +55,8 @@ extern asmlinkage void schedule_tail(struct task_struct *prev); extern void init_idle(struct task_struct *idle, int cpu); extern int sched_fork(unsigned long clone_flags, struct task_struct *p); -extern void sched_post_fork(struct task_struct *p, - struct kernel_clone_args *kargs); +extern void sched_cgroup_fork(struct task_struct *p, struct kernel_clone_args *kargs); +extern void sched_post_fork(struct task_struct *p); extern void sched_dead(struct task_struct *p); void __noreturn do_task_dead(void); diff --git a/include/linux/soc/samsung/exynos-smc.h b/include/linux/soc/samsung/exynos-smc.h index 61435b99a61e..87b0c5dee80a 100644 --- a/include/linux/soc/samsung/exynos-smc.h +++ b/include/linux/soc/samsung/exynos-smc.h @@ -53,16 +53,7 @@ #define SMC_CMD_FMP_SMU_RESUME (0xC2001860) #define SMC_CMD_FMP_SMU_DUMP (0xC2001870) #define SMC_CMD_UFS_LOG (0xC2001880) - -/* For FMP/SMU Ctrl */ -#define SMC_CMD_FMP_SECURITY (0xC2001810) -#define SMC_CMD_FMP_DISK_KEY_STORED (0xC2001820) -#define SMC_CMD_FMP_DISK_KEY_SET (0xC2001830) -#define SMC_CMD_FMP_DISK_KEY_CLEAR (0xC2001840) -#define SMC_CMD_SMU (0xC2001850) -#define SMC_CMD_FMP_SMU_RESUME (0xC2001860) -#define SMC_CMD_FMP_SMU_DUMP (0xC2001870) -#define SMC_CMD_UFS_LOG (0xC2001880) +#define SMC_CMD_FMP_USE_OTP_KEY (0xC2001890) /* SMU IDs (third parameter to FMP/SMU Ctrls) */ #define SMU_EMBEDDED 0 diff --git a/include/soc/google/acpm_ipc_ctrl.h b/include/soc/google/acpm_ipc_ctrl.h index f0ff6c6a0d5f..a1240bbe0922 100644 --- a/include/soc/google/acpm_ipc_ctrl.h +++ b/include/soc/google/acpm_ipc_ctrl.h @@ -47,6 +47,7 @@ enum acpm_framework_debug_commands { ACPM_FRAMEWORK_COMMAND_DEBUG_SOFT_LOCKUP, ACPM_FRAMEWORK_COMMAND_DEBUG_HARD_LOCKUP, ACPM_FRAMEWORK_COMMAND_DEBUG_EXCEPTION, + ACPM_FRAMEWORK_COMMAND_DEBUG_NOTIFY_SHUTDOWN, ACPM_FRAMEWORK_COMMAND_DEBUG_MAX, }; @@ -65,6 +66,7 @@ int acpm_ipc_send_data_lazy(unsigned int channel_id, int acpm_ipc_set_ch_mode(struct device_node *np, bool polling); int acpm_ipc_get_buffer(const char *name, char **addr, u32 *size); void exynos_acpm_reboot(void); +void acpm_prepare_reboot(void); void acpm_stop_log_and_dumpram(void); u64 get_frc_time(void); bool is_acpm_ipc_flushed(void); @@ -115,6 +117,10 @@ static inline void exynos_acpm_reboot(void) { } +static inline void acpm_prepare_reboot(void) +{ +} + static inline void acpm_stop_log_and_dumpram(void) { } diff --git a/include/soc/google/bcl.h b/include/soc/google/bcl.h index 2d16b79911bb..48cfc1c3c08b 100644 --- a/include/soc/google/bcl.h +++ b/include/soc/google/bcl.h @@ -40,32 +40,21 @@ enum TRIGGERED_SOURCE { TRIGGERED_SOURCE_MAX, }; -enum GRAN_MAIN_THERMAL_SOURCE { - TS_SMPL_WARN, - TS_OCP_WARN_CPUCL1, - TS_OCP_WARN_CPUCL2, - TS_SOFT_OCP_WARN_CPUCL1, - TS_SOFT_OCP_WARN_CPUCL2, - TS_OCP_WARN_TPU, - TS_SOFT_OCP_WARN_TPU, -}; - -enum GRAN_SUB_THERMAL_SOURCE { - TS_OCP_WARN_GPU, - TS_SOFT_OCP_WARN_GPU, -}; - enum BCL_THERMAL_SOURCE { - TS_PMIC_SOC, - TS_UVLO1, TS_UVLO2, - TS_BATOILO, - TS_PMIC_120C, - TS_PMIC_140C, - TS_PMIC_OVERHEAT, + TS_UVLO1, }; -enum PMIC_REG { S2MPG10, S2MPG11 }; +enum PMIC_REG { +#if IS_ENABLED(CONFIG_SOC_GS101) + S2MPG10, + S2MPG11 +#endif +#if IS_ENABLED(CONFIG_SOC_GS201) + S2MPG12, + S2MPG13 +#endif +}; struct ocpsmpl_stats { ktime_t _time; @@ -142,12 +131,18 @@ struct bcl_device { bool batt_psy_initialized; bool enabled; + bool ready; unsigned int offsrc; unsigned int pwronsrc; unsigned int vdroop1_pin; unsigned int vdroop2_pin; + + /* debug */ + struct dentry *debug_entry; + unsigned int gpu_clk_out; + unsigned int tpu_clk_out; }; extern void google_bcl_irq_update_lvl(struct bcl_device *bcl_dev, int index, unsigned int lvl); diff --git a/include/soc/google/debug-test.h b/include/soc/google/debug-test.h index 2ef353bb08b1..192a02f9dbe4 100644 --- a/include/soc/google/debug-test.h +++ b/include/soc/google/debug-test.h @@ -10,11 +10,14 @@ struct debug_trigger { void (*hard_lockup)(char *arg); +#if IS_ENABLED(CONFIG_SOC_GS101) void (*cold_reset)(char *arg); +#endif void (*watchdog_emergency_reset)(char *arg); void (*halt)(char *arg); void (*arraydump)(char *arg); void (*scandump)(char *arg); + void (*hyp_panic)(char *arg); }; #if IS_ENABLED(CONFIG_PIXEL_DEBUG_TEST) diff --git a/include/soc/google/exynos-devfreq.h b/include/soc/google/exynos-devfreq.h index 118c5d3c0342..74b926ab56a6 100644 --- a/include/soc/google/exynos-devfreq.h +++ b/include/soc/google/exynos-devfreq.h @@ -250,8 +250,8 @@ static inline int exynos_devfreq_lock_freq(unsigned int devfreq_type, unsigned i return 0; } -static int exynos_devfreq_get_boundary(unsigned int devfreq_type, - unsigned int *max_freq, unsigned int *min_freq); +static inline int exynos_devfreq_get_boundary(unsigned int devfreq_type, + unsigned int *max_freq, unsigned int *min_freq) { return 0; } diff --git a/include/soc/google/exynos-modem-ctrl.h b/include/soc/google/exynos-modem-ctrl.h index d04a91f3a5dc..c93160cf9857 100644 --- a/include/soc/google/exynos-modem-ctrl.h +++ b/include/soc/google/exynos-modem-ctrl.h @@ -14,8 +14,7 @@ struct vnet { void *iod; - bool enable_zerocopy; - bool (*free_head)(struct sk_buff *skb); + bool hiprio_ack_only; }; #if IS_ENABLED(CONFIG_EXYNOS_MODEM_IF) diff --git a/include/soc/google/exynos-pd.h b/include/soc/google/exynos-pd.h index 207c4737e995..6e13d6cc0607 100644 --- a/include/soc/google/exynos-pd.h +++ b/include/soc/google/exynos-pd.h @@ -59,6 +59,7 @@ struct exynos_pm_domain { atomic_t need_sync; bool turn_off_on_sync; unsigned int need_smc; + unsigned int cmu_id; bool skip_idle_ip; bool always_on; struct exynos_pd_stat pd_stat; @@ -67,6 +68,7 @@ struct exynos_pm_domain { #if IS_ENABLED(CONFIG_EXYNOS_PD) struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name); +void *exynos_pd_lookup_cmu_id(u32 cmu_id); int exynos_pd_status(struct exynos_pm_domain *pd); int exynos_pd_power_on(struct exynos_pm_domain *pd); int exynos_pd_power_off(struct exynos_pm_domain *pd); @@ -79,6 +81,11 @@ struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name) return NULL; } +static inline void *exynos_pd_lookup_cmu_id(u32 cmu_id) +{ + return NULL; +} + static inline int exynos_pd_status(struct exynos_pm_domain *pd) { return 1; @@ -105,6 +112,7 @@ static inline int exynos_pd_get_pd_stat(struct exynos_pm_domain *pd, extern u32 dwc3_otg_is_connect(void); extern void exynos_usbdrd_ldo_manual_control(bool on); extern void exynos_usbdrd_vdd_hsi_manual_control(bool on); +extern void exynos_usbdrd_s2mpu_manual_control(bool on); #else static inline u32 dwc3_otg_is_connect(void) { @@ -118,6 +126,10 @@ static inline void exynos_usbdrd_vdd_hsi_manual_control(bool on) { return; } +static inline void exynos_usbdrd_s2mpu_manual_control(bool on) +{ + return; +} #endif #endif /* __EXYNOS_PD_H */ diff --git a/include/soc/google/exynos-pmu-if.h b/include/soc/google/exynos-pmu-if.h index 76d9f8a4044a..e94a200693eb 100644 --- a/include/soc/google/exynos-pmu-if.h +++ b/include/soc/google/exynos-pmu-if.h @@ -32,7 +32,7 @@ extern struct exynos_cpu_power_ops exynos_cpu; #if defined(CONFIG_SOC_EXYNOS9820) #define phy_cluster(cpu) MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1) #define phy_cpu(cpu) MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) -#elif defined(CONFIG_SOC_GS101) +#elif defined(CONFIG_SOC_GS101) || defined(CONFIG_SOC_GS201) #define phy_cluster(cpu) MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 2) #define phy_cpu(cpu) MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1) #else diff --git a/include/soc/google/exynos_cpu_cooling.h b/include/soc/google/exynos_cpu_cooling.h index f74c698d7dd7..347211fe3564 100644 --- a/include/soc/google/exynos_cpu_cooling.h +++ b/include/soc/google/exynos_cpu_cooling.h @@ -11,7 +11,7 @@ struct thermal_cooling_device * exynos_cpufreq_cooling_register(struct device_node *np, struct cpufreq_policy *policy); #else static inline struct thermal_cooling_device * -exynos_cpufreq_cooling_register(struct device_node *np, struct cpufreq_policy *policy); +exynos_cpufreq_cooling_register(struct device_node *np, struct cpufreq_policy *policy) { return NULL; } diff --git a/include/soc/google/gs101_tmu.h b/include/soc/google/gs_tmu.h similarity index 91% rename from include/soc/google/gs101_tmu.h rename to include/soc/google/gs_tmu.h index ddd80a523705..051ae5d7db2f 100644 --- a/include/soc/google/gs101_tmu.h +++ b/include/soc/google/gs_tmu.h @@ -1,24 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only * - * gs101_tmu.h - Samsung GS101 TMU (Thermal Management Unit) + * gs_tmu.h - Samsung GS TMU (Thermal Management Unit) * * Copyright (C) 2019 Samsung Electronics * Hyeonseong Gil */ -#ifndef _GS101_TMU_H -#define _GS101_TMU_H +#ifndef _GS_TMU_H +#define _GS_TMU_H #include +#include #include #include #define MCELSIUS 1000 -struct gs101_pi_param { +struct gs_pi_param { s64 err_integral; int trip_switch_on; int trip_control_temp; + int prev_control_temp; + int control_temp_step; + u32 sustainable_power; s32 k_po; s32 k_pu; @@ -35,7 +39,7 @@ struct gs101_pi_param { #define TRIP_LEVEL_NUM 8 /** - * struct gs101_tmu_data : A structure to hold the private data of the TMU + * struct gs_tmu_data : A structure to hold the private data of the TMU driver * @id: identifier of the one instance of the TMU controller. * @base: base address of the single instance of the TMU controller. @@ -52,7 +56,7 @@ struct gs101_pi_param { * @tmu_set_emulation: SoC specific TMU emulation setting method * @tmu_clear_irqs: SoC specific TMU interrupts clearing method */ -struct gs101_tmu_data { +struct gs_tmu_data { int id; /* Throttle hotplug related variables */ bool pause_enable; @@ -77,6 +81,8 @@ struct gs101_tmu_data { int limited_frequency; int limited_threshold; int limited_threshold_release; + int dfs_trig_threshold; + int dfs_clr_threshold; struct exynos_pm_qos_request thermal_limit_request; bool limited; void __iomem *base; @@ -91,7 +97,7 @@ struct gs101_tmu_data { struct kthread_work hotplug_work; struct kthread_work cpu_hw_throttle_work; struct kthread_delayed_work cpu_hw_throttle_init_work; - struct mutex lock; /* lock to protect gs101 tmu */ + struct mutex lock; /* lock to protect gs tmu */ struct thermal_zone_device *tzd; struct bcl_device *bcl_dev; unsigned int ntrip; @@ -104,18 +110,21 @@ struct gs101_tmu_data { bool is_hardlimited; bool is_cpu_hotplugged_out; bool is_cpu_hw_throttled; + bool is_dfs_throttled; int temperature; bool use_pi_thermal; struct kthread_delayed_work pi_work; - struct gs101_pi_param *pi_param; + struct gs_pi_param *pi_param; struct cpumask pause_cpus; struct cpumask hotplug_cpus; + struct cpumask dfs_throttled_cpus; struct cpumask tmu_work_affinity; struct cpumask hotplug_work_affinity; char cpuhp_name[CPUHP_USER_NAME_LEN + 1]; void *disable_stats; void *hardlimit_stats; atomic64_t trip_counter[TRIP_LEVEL_NUM]; + bool has_dfs_support; }; enum throttling_stats_type { @@ -217,6 +226,7 @@ enum tmu_sensor_t { #define TMU_REG_P0_INTPEND (0x00F8) #define TMU_REG_INTPEND(p) ((p) * 0x50 + TMU_REG_P0_INTPEND) #define TMU_REG_INTPEND_RISE_MASK(l) (1 << (l)) +#define TMU_REG_INTPEND_FALL_MASK(l) (1 << (l+16)) #define TMU_REG_P0_PAST_TEMP1_0 (0x0100) #define TMU_REG_PAST_TEMP1_0(p) ((p) * 0x50 + TMU_REG_P0_PAST_TEMP1_0) #define TMU_REG_P0_PAST_TEMP3_2 (0x0104) @@ -233,12 +243,14 @@ enum tmu_sensor_t { #define TMU_REG_PAST_TEMP13_12(p) ((p) * 0x50 + TMU_REG_P0_PAST_TEMP13_12) #define TMU_REG_P0_PAST_TEMP15_14 (0x011C) #define TMU_REG_PAST_TEMP15_14(p) ((p) * 0x50 + TMU_REG_P0_PAST_TEMP15_14) +#define DFS_IRQ_BIT (6) enum thermal_feature { CPU_THROTTLE = 0, HARD_LIMIT = 1, HOTPLUG = 2, PAUSE = 3, + DFS = 4 }; struct sensor_data { @@ -261,4 +273,9 @@ typedef int (*tpu_pause_cb)(enum thermal_pause_state action, void *data); void register_tpu_thermal_pause_cb(tpu_pause_cb tpu_cb, void *data); +/* Callback for registering to dfs events */ +typedef void (*dfs_throttle_cb)(struct cpumask *maskp, bool is_dfs_throttled); + +void register_dfs_throttle_cb(dfs_throttle_cb dfs_cb); + #endif /* _GS101_TMU_H */ diff --git a/include/linux/mcu_ipc.h b/include/soc/google/mcu_ipc.h similarity index 100% rename from include/linux/mcu_ipc.h rename to include/soc/google/mcu_ipc.h diff --git a/include/soc/google/odpm.h b/include/soc/google/odpm.h new file mode 100644 index 000000000000..4deda88b63d5 --- /dev/null +++ b/include/soc/google/odpm.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * ODPM Support. + * + * Copyright 2022 Google LLC + */ + +#ifndef __ODPM_H +#define __ODPM_H + +#include + +#if IS_ENABLED(CONFIG_SOC_GS101) +#include +#include +#include +#include +#elif IS_ENABLED(CONFIG_SOC_GS201) +#include +#include +#include +#include +#endif + +#define ODPM_CHANNEL_MAX S2MPG1X_METER_CHANNEL_MAX +#define ODPM_BUCK_EN_BYTES S2MPG1X_METER_BUCKEN_BUF + +enum odpm_rail_type { + ODPM_RAIL_TYPE_REGULATOR_LDO, + ODPM_RAIL_TYPE_REGULATOR_BUCK, + ODPM_RAIL_TYPE_SHUNT, +}; + +enum odpm_sampling_rate_type { + ODPM_SAMPLING_RATE_INTERNAL, + ODPM_SAMPLING_RATE_EXTERNAL, + ODPM_SAMPLING_RATE_ALL, +}; + +struct odpm_rail_data { + /* Config */ + const char *name; + const char *schematic_name; + const char *subsys_name; + enum odpm_rail_type type; + u32 mux_select; + + /* Buck specific */ + int channel_en_byte_offset; + + /* External rail specific config */ + u32 shunt_uohms; + + /* Bucks and external rails */ + u8 channel_en_index; + + /* Data */ + u64 acc_power_uW_sec_cached; + u64 measurement_stop_ms; + u64 measurement_start_ms_cached; + + bool disable_in_sleep; +}; + +struct odpm_chip { + /* Config */ + const char *name; + enum s2mpg1x_id hw_id; + int hw_rev; + u32 max_refresh_time_ms; + + int num_rails; + struct odpm_rail_data *rails; + + const u32 *sampling_rate_int_uhz; + int sampling_rate_int_count; + const u32 *sampling_rate_ext_uhz; + int sampling_rate_ext_count; + + s2mpg1x_int_samp_rate int_config_sampling_rate_i; + s2mpg1x_ext_samp_rate ext_config_sampling_rate_i; + + /* Data */ + u64 acc_timestamp_ms; + s2mpg1x_int_samp_rate int_sampling_rate_i; + s2mpg1x_ext_samp_rate ext_sampling_rate_i; + + bool rx_ext_config_confirmation; +}; + +struct odpm_channel_data { + int rail_i; + bool enabled; + + u64 measurement_start_ms; + u64 acc_power_uW_sec; +}; + +/** + * dynamic struct odpm_info + */ +struct odpm_info { + struct odpm_chip chip; + void *meter; /* Parent meter device data */ + struct i2c_client *i2c; + struct i2c_client *mt_trim; + struct mutex *meter_lock; /* Meter lock */ + struct mutex lock; /* Global HW lock */ + + struct odpm_channel_data channels[ODPM_CHANNEL_MAX]; + + struct workqueue_struct *work_queue; + struct work_struct work_refresh; + struct alarm alarmtimer_refresh; + struct wakeup_source *ws; + + u64 last_poll_ktime_boot_ns; + bool sleeping; +}; + +void odpm_get_lpf_values(struct odpm_info *info, s2mpg1x_meter_mode mode, + u64 micro_unit[ODPM_CHANNEL_MAX]); +#endif /* __ODPM_H */ diff --git a/include/soc/google/pkvm-s2mpu.h b/include/soc/google/pkvm-s2mpu.h new file mode 100644 index 000000000000..1e589dee0283 --- /dev/null +++ b/include/soc/google/pkvm-s2mpu.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + */ + +#ifndef __PKVM_S2MPU_H +#define __PKVM_S2MPU_H + +#include + +/* + * Parse the 's2mpus' DT property of 'parent' and create a device link + * to all referenced S2MPU devices. + */ +int pkvm_s2mpu_of_link(struct device *parent); + +/* + * Parse the 's2mpu' DT property of 'parent' and return a pointer to + * the referenced S2MPU device, or NULL if the property does not exist. + */ +struct device *pkvm_s2mpu_of_parse(struct device *parent); + +int pkvm_s2mpu_suspend(struct device *dev); +int pkvm_s2mpu_resume(struct device *dev); + +static inline bool pkvm_s2mpu_ready(struct device *dev) +{ + return !!platform_get_drvdata(to_platform_device(dev)); +} + +#endif /* __PKVM_S2MPU_H */ diff --git a/include/linux/shm_ipc.h b/include/soc/google/shm_ipc.h similarity index 61% rename from include/linux/shm_ipc.h rename to include/soc/google/shm_ipc.h index ee80d736ba90..af37c11c702d 100644 --- a/include/linux/shm_ipc.h +++ b/include/soc/google/shm_ipc.h @@ -10,30 +10,28 @@ #define MAX_CP_NUM 2 #if IS_ENABLED(CONFIG_SHM_IPC) -extern int cp_shmem_get_mem_map_on_cp_flag(u32 cp_num); -extern void __iomem *cp_shmem_get_region(u32 cp, u32 idx); -extern void __iomem *cp_shmem_get_nc_region(unsigned long base, u32 size); -extern void cp_shmem_release_region(u32 cp, u32 idx); -extern void cp_shmem_release_rmem(u32 cp, u32 idx); -extern unsigned long cp_shmem_get_base(u32 cp, u32 idx); -extern u32 cp_shmem_get_size(u32 cp, u32 idx); +int cp_shmem_get_mem_map_on_cp_flag(u32 cp_num); +void __iomem *cp_shmem_get_region(u32 cp, u32 idx); +void __iomem *cp_shmem_get_nc_region(unsigned long base, u32 size); +void cp_shmem_release_region(u32 cp, u32 idx); +void cp_shmem_release_rmem(u32 cp, u32 idx, u32 headroom); +unsigned long cp_shmem_get_base(u32 cp, u32 idx); +u32 cp_shmem_get_size(u32 cp, u32 idx); /* Legacy functions */ -extern unsigned long shm_get_msi_base(void); -extern void __iomem *shm_get_vss_region(void); -extern unsigned long shm_get_vss_base(void); -extern u32 shm_get_vss_size(void); -extern void __iomem *shm_get_vparam_region(void); -extern unsigned long shm_get_vparam_base(void); -extern u32 shm_get_vparam_size(void); - +unsigned long shm_get_msi_base(void); +void __iomem *shm_get_vss_region(void); +unsigned long shm_get_vss_base(void); +u32 shm_get_vss_size(void); +void __iomem *shm_get_vparam_region(void); +unsigned long shm_get_vparam_base(void); +u32 shm_get_vparam_size(void); #else /* CONFIG_SHM_IPC */ - static inline int cp_shmem_get_mem_map_on_cp_flag(u32 cp_num) { return 0; } static inline void __iomem *cp_shmem_get_region(u32 cp, u32 idx) { return NULL; } static inline void __iomem *cp_shmem_get_nc_region(unsigned long base, u32 size) { return NULL; } static inline void cp_shmem_release_region(u32 cp, u32 idx) { return; } -static inline void cp_shmem_release_rmem(u32 cp, u32 idx) { return; } +static inline void cp_shmem_release_rmem(u32 cp, u32 idx, u32 headroom) { return; } static inline unsigned long cp_shmem_get_base(u32 cp, u32 idx) { return 0; } static inline u32 cp_shmem_get_size(u32 cp, u32 idx) { return 0; } @@ -45,7 +43,6 @@ static inline u32 shm_get_vss_size(void) { return 0; } static inline void __iomem *shm_get_vparam_region(void) { return NULL; } static inline unsigned long shm_get_vparam_base(void) { return 0; } static inline u32 shm_get_vparam_size(void) { return 0; } - #endif /* CONFIG_SHM_IPC */ #endif /* __SHMEM_IPC_H__ */ diff --git a/include/soc/google/tpu-ext.h b/include/soc/google/tpu-ext.h new file mode 100644 index 000000000000..bfc638158d80 --- /dev/null +++ b/include/soc/google/tpu-ext.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Utility functions for interfacing other modules with Edge TPU ML + * accelerator. + * + * Copyright (C) 2021 Google, Inc. + */ + +#ifndef __TPU_EXT_H__ +#define __TPU_EXT_H__ + +#include +#include + +/* + * Data structures to be used for ALLOCATE_EXTERNAL_MAILBOX command + */ +struct edgetpu_ext_mailbox_descriptor { + phys_addr_t cmdq_pa, respq_pa; +}; + +struct edgetpu_ext_client_info { + u32 tpu_fd; /* fd of the opened TPU device */ + u32 mbox_map; /* bitmap of requested mailboxes */ + struct edgetpu_mailbox_attr __user *attr; +}; + +/* + * Structure to hold information about mailboxes. + * Length of @mailboxes should be at least number of set bits in @mbox_map + */ +struct edgetpu_ext_mailbox_info { + size_t cmdq_size, respq_size; + /* + * array length is equal to number of set bits in + * edgetpu_ext_client_info.mbox_map + */ + struct edgetpu_ext_mailbox_descriptor mailboxes[]; +}; + +enum edgetpu_ext_commands { + /* in_data: edgetpu_ext_client_info, out_data: edgetpu_ext_mailbox_info */ + ALLOCATE_EXTERNAL_MAILBOX, + /* in_data: edgetpu_ext_client_info, out_data: unused */ + FREE_EXTERNAL_MAILBOX, +}; + +enum edgetpu_ext_client_type { + EDGETPU_EXTERNAL_CLIENT_TYPE_DSP, + EDGETPU_EXTERNAL_CLIENT_TYPE_AOC, +}; + +/* + * Interface used by other modules to send commands to EdgeTPU driver. + * + * @edgetpu_dev: edgetpu device to send command to + * @client_type: type for identification of client by EdgeTPU driver + * @cmd_id: type of command to send to EdgeTPU driver + * @in_data: (in param) any data required to be sent based on cmd_id + * @out_data: (out param) any data expected to receive based on cmd_id + * + * Returns: + * 0 on success or negative error code on error. + */ +int edgetpu_ext_driver_cmd(struct device *edgetpu_dev, + enum edgetpu_ext_client_type client_type, + enum edgetpu_ext_commands cmd_id, void *in_data, void *out_data); + +#endif /*__TPU_EXT_H__*/ diff --git a/include/trace/hooks/buffer.h b/include/trace/hooks/buffer.h new file mode 100644 index 000000000000..50e8f71dab9f --- /dev/null +++ b/include/trace/hooks/buffer.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM buffer + +#define TRACE_INCLUDE_PATH trace/hooks + +#if !defined(_TRACE_HOOK_BUFFER_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_HOOK_BUFFER_H + +#include +#include + +DECLARE_HOOK(android_vh_bh_lru_install, + TP_PROTO(struct page *page, bool *flush), + TP_ARGS(page, flush)); + +/* macro versions of hooks are no longer required */ + +#endif /* _TRACE_HOOK_BUFFER_H */ + +/* This part must be outside protection */ +#include diff --git a/include/trace/hooks/mm.h b/include/trace/hooks/mm.h index 263b867d453c..d9be2be468de 100644 --- a/include/trace/hooks/mm.h +++ b/include/trace/hooks/mm.h @@ -61,6 +61,9 @@ DECLARE_HOOK(android_vh_rmqueue, unsigned int alloc_flags, int migratetype), TP_ARGS(preferred_zone, zone, order, gfp_flags, alloc_flags, migratetype)); +DECLARE_HOOK(android_vh_pagevec_drain, + TP_PROTO(struct page *page, bool *ret), + TP_ARGS(page, ret)); DECLARE_HOOK(android_vh_pagecache_get_page, TP_PROTO(struct address_space *mapping, pgoff_t index, int fgp_flags, gfp_t gfp_mask, struct page *page), @@ -97,6 +100,30 @@ DECLARE_HOOK(android_vh_alloc_pages_slowpath, DECLARE_HOOK(android_vh_cma_alloc_adjust, TP_PROTO(struct zone *zone, bool *is_cma_alloc), TP_ARGS(zone, is_cma_alloc)); +DECLARE_HOOK(android_vh_do_madvise_blk_plug, + TP_PROTO(int behavior, bool *do_plug), + TP_ARGS(behavior, do_plug)); +DECLARE_HOOK(android_vh_shrink_inactive_list_blk_plug, + TP_PROTO(bool *do_plug), + TP_ARGS(do_plug)); +DECLARE_HOOK(android_vh_shrink_lruvec_blk_plug, + TP_PROTO(bool *do_plug), + TP_ARGS(do_plug)); +DECLARE_HOOK(android_vh_reclaim_pages_plug, + TP_PROTO(bool *do_plug), + TP_ARGS(do_plug)); +DECLARE_HOOK(android_vh_zap_pte_range_tlb_start, + TP_PROTO(void *ret), + TP_ARGS(ret)); +DECLARE_HOOK(android_vh_zap_pte_range_tlb_force_flush, + TP_PROTO(struct page *page, bool *flush), + TP_ARGS(page, flush)); +DECLARE_HOOK(android_vh_zap_pte_range_tlb_end, + TP_PROTO(void *ret), + TP_ARGS(ret)); +DECLARE_HOOK(android_vh_skip_lru_disable, + TP_PROTO(bool *skip), + TP_ARGS(skip)); DECLARE_HOOK(android_vh_print_slabinfo_header, TP_PROTO(struct seq_file *m), TP_ARGS(m)); diff --git a/include/trace/hooks/sched.h b/include/trace/hooks/sched.h index 4f345029ea09..4233384f6ff8 100644 --- a/include/trace/hooks/sched.h +++ b/include/trace/hooks/sched.h @@ -392,6 +392,10 @@ DECLARE_HOOK(android_vh_pidfd_open, DECLARE_HOOK(android_vh_mmput, TP_PROTO(void *unused), TP_ARGS(unused)); + +DECLARE_HOOK(android_vh_rebuild_root_domains_bypass, + TP_PROTO(bool tasks_frozen, bool *bypass), + TP_ARGS(tasks_frozen, bypass)); /* macro versions of hooks are no longer required */ #endif /* _TRACE_HOOK_SCHED_H */ diff --git a/include/trace/hooks/wqlockup.h b/include/trace/hooks/wqlockup.h deleted file mode 100644 index 2572ebf5eff4..000000000000 --- a/include/trace/hooks/wqlockup.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM wqlockup -#define TRACE_INCLUDE_PATH trace/hooks - -#if !defined(_TRACE_HOOK_WQLOCKUP_H) || defined(TRACE_HEADER_MULTI_READ) -#define _TRACE_HOOK_WQLOCKUP_H -#include -/* - * Following tracepoints are not exported in tracefs and provide a - * mechanism for vendor modules to hook and extend functionality - */ -DECLARE_HOOK(android_vh_wq_lockup_pool, - TP_PROTO(int cpu, unsigned long pool_ts), - TP_ARGS(cpu, pool_ts)); - -/* macro versions of hooks are no longer required */ - -#endif /* _TRACE_HOOK_WQLOCKUP_H */ -/* This part must be outside protection */ -#include diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 41a33a887861..282143029ab1 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -569,6 +569,8 @@ extern "C" { #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x5 (5ULL) #define SBWC_FORMAT_MOD_BLOCK_SIZE_32x6 (6ULL) +#define SBWC_FORMAT_MOD_LOSSY (1 << 12) + #define DRM_FORMAT_MOD_SAMSUNG_SBWC(blk_size) \ fourcc_mod_code(SAMSUNG, \ (SBWC_BLOCK_SIZE_SET(blk_size) | SBWC_IDENTIFIER)) diff --git a/include/uapi/drm/samsung_drm.h b/include/uapi/drm/samsung_drm.h index ad88b8b64aff..22668b3970d0 100644 --- a/include/uapi/drm/samsung_drm.h +++ b/include/uapi/drm/samsung_drm.h @@ -117,6 +117,23 @@ struct cgc_lut { __u32 b_values[DRM_SAMSUNG_CGC_LUT_REG_CNT]; }; +#define DRM_SAMSUNG_CGC_DMA_LUT_ENTRY_CNT 4913 +/** + * struct cgc_dma_lut - color gammut control format for cgc dma to set by user-space + * + * @r_value: value for red color + * @g_value: value for green color + * @b_value: value for blue color + * + * A cgc_dma_lut represents a format to support cgc dma. cgc coefficients should be + * located in dram according to this format. + */ +struct cgc_dma_lut { + __u16 r_value; + __u16 g_value; + __u16 b_value; +}; + #define DRM_SAMSUNG_MATRIX_DIMENS 3 /** diff --git a/include/uapi/linux/bigo.h b/include/uapi/linux/bigo.h deleted file mode 100644 index 3ab10b82e0bf..000000000000 --- a/include/uapi/linux/bigo.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ -/* - * Copyright 2020 Google LLC. - * - * Author: Vinay Kalia - */ - -#ifndef _UAPI_BIGO_H_ -#define _UAPI_BIGO_H_ - -#include -#ifdef __KERNEL__ -#include -#else -#define __user -#include -#endif - -/* - * Structures as parameters for BigOcean commands. It should be passed - * into ioctl() as the third parameter. - * - * The usage and meaning of each field is documented in command - * identifiers. - */ - -struct bigo_ioc_regs { - __u64 regs; - __u32 regs_size; -}; - -struct bigo_ioc_mapping { - int fd; - __u32 iova; - __u32 offset; - __u32 size; -}; - -struct bigo_ioc_frmsize { - __u32 height; - __u32 width; -}; - -struct bigo_cache_info { - __u32 size; - __u32 pid; -}; - -/* - * Helpers for defining command identifiers. User space should not - * use these macros directly. - * - * - */ -#define BIGO_IOC_MAGIC 'B' - -#define _BIGO_IO(nr) _IO(BIGO_IOC_MAGIC, nr) -#define _BIGO_IOR(nr, size) _IOR(BIGO_IOC_MAGIC, nr, size) -#define _BIGO_IOW(nr, size) _IOW(BIGO_IOC_MAGIC, nr, size) -#define _BIGO_IOWR(nr, size) _IOWR(BIGO_IOC_MAGIC, nr, size) - -enum bigo_cmd_id { - BIGO_CMD_PROCESS, - BIGO_CMD_ABORT, - BIGO_CMD_MAP, - BIGO_CMD_UNMAP, - BIGO_CMD_CONFIG_FRMRATE, - BIGO_CMD_CONFIG_FRMSIZE, - BIGO_CMD_GET_CACHE_INFO, - BIGO_CMD_CONFIG_SECURE, - BIGO_CMD_MAXNR, -}; -/* */ - -#define BIGO_IOCX_PROCESS _BIGO_IOWR(BIGO_CMD_PROCESS, struct bigo_ioc_regs) -#define BIGO_IOCX_MAP _BIGO_IOWR(BIGO_CMD_MAP, struct bigo_ioc_mapping) -#define BIGO_IOCX_UNMAP _BIGO_IOW(BIGO_CMD_UNMAP, struct bigo_ioc_mapping) -#define BIGO_IOCX_CONFIG_FRMRATE _BIGO_IOW(BIGO_CMD_CONFIG_FRMRATE, __u32) -#define BIGO_IOCX_CONFIG_FRMSIZE \ - _BIGO_IOW(BIGO_CMD_CONFIG_FRMSIZE, struct bigo_ioc_frmsize) -#define BIGO_IOCX_GET_CACHE_INFO \ - _BIGO_IOR(BIGO_CMD_GET_CACHE_INFO, struct bigo_cache_info) -#define BIGO_IOCX_ABORT _BIGO_IO(BIGO_CMD_ABORT) -#define BIGO_IOCX_CONFIG_SECURE _BIGO_IOW(BIGO_CMD_CONFIG_SECURE, __u32) - -#endif /* _UAPI_BIGO_H_ */ diff --git a/include/uapi/linux/videodev2_exynos_media.h b/include/uapi/linux/videodev2_exynos_media.h index f15c782405a8..509c929239ac 100644 --- a/include/uapi/linux/videodev2_exynos_media.h +++ b/include/uapi/linux/videodev2_exynos_media.h @@ -136,39 +136,58 @@ #define S10B_2B_STRIDE(w) (__ALIGN_UP(((w + 3) / 4), 16)) /* Compress format */ -#define SBWC_8B_STRIDE(w) (128 * (((w) + 31) / 32)) -#define SBWC_10B_STRIDE(w) (160 * (((w) + 31) / 32)) -#define SBWC_HEADER_STRIDE(w) ((((((w) + 63) / 64) + 15) / 16) * 16) -#define AFBC_8B_STRIDE(w) __ALIGN_UP(w, 16) -#define AFBC_10B_STRIDE(w) __ALIGN_UP(w * 2, 16) -#define SBWC_8B_Y_SIZE(w, h) \ - ((SBWC_8B_STRIDE(w) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWC_8B_Y_HEADER_SIZE(w, h) \ - __ALIGN_UP(((SBWC_HEADER_STRIDE(w) * \ - ((__ALIGN_UP((h), 16) + 3) / 4)) + 256), 32) -#define SBWC_8B_CBCR_SIZE(w, h) \ - ((SBWC_8B_STRIDE(w) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) -#define SBWC_8B_CBCR_HEADER_SIZE(w, h) \ - ((SBWC_HEADER_STRIDE(w) * \ - (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 128) -#define AFBC_8B_Y_SIZE(w, h) \ - (((((w + 31) / 32) * ((h + 7) / 8) * 16 + 127) / 128) * 128 + \ - ((w + 31) / 32) * ((h + 7) / 8) * 384) -#define AFBC_10B_Y_SIZE(w, h) \ - (((((w + 31) / 32) * ((h + 7) / 8) * 16 + 127) / 128) * 128 + \ - ((w + 31) / 32) * ((h + 7) / 8) * 512) - -#define SBWC_10B_Y_SIZE(w, h) \ - ((SBWC_10B_STRIDE(w) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWC_10B_Y_HEADER_SIZE(w, h) \ - __ALIGN_UP((((__ALIGN_UP((w), 16) * \ - __ALIGN_UP((h), 16) * 2) + 256) - SBWC_10B_Y_SIZE(w, h)), 32) -#define SBWC_10B_CBCR_SIZE(w, h) \ - ((SBWC_10B_STRIDE(w) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) -#define SBWC_10B_CBCR_HEADER_SIZE(w, h) \ - (((__ALIGN_UP((w), 16) * \ - __ALIGN_UP((h), 16)) + 256) - SBWC_10B_CBCR_SIZE(w, h)) +/* SBWC */ +#define __COUNT_BLOCKS(x, a) (((x) + ((a) - 1)) / (a)) + +#define SBWC_HEADER_STRIDE_ALIGN 16 +#define SBWC_PAYLOAD_STRIDE_ALIGN 64 + +#define SBWC_BLOCK_WIDTH 32 +#define SBWC_BLOCK_HEIGHT 4 + +#define SBWC_ALIGNED_H(h, a) __ALIGN_UP((h), a) + +#define SBWC_H_BLOCKS(w) __COUNT_BLOCKS((w), SBWC_BLOCK_WIDTH) + +#define SBWC_8B_STRIDE(w) (__ALIGN_UP((8 / 2) * \ + SBWC_BLOCK_WIDTH, \ + SBWC_PAYLOAD_STRIDE_ALIGN) * \ + SBWC_H_BLOCKS(w)) +#define SBWC_10B_STRIDE(w) (__ALIGN_UP((10 / 2) * \ + SBWC_BLOCK_WIDTH, \ + SBWC_PAYLOAD_STRIDE_ALIGN) * \ + SBWC_H_BLOCKS(w)) +#define SBWC_HEADER_STRIDE(w) (__ALIGN_UP(__COUNT_BLOCKS(w, \ + SBWC_BLOCK_WIDTH * 2), \ + SBWC_HEADER_STRIDE_ALIGN)) + +#define SBWC_Y_VSTRIDE_BLOCKS(h, a) __COUNT_BLOCKS(SBWC_ALIGNED_H(h, a), \ + SBWC_BLOCK_HEIGHT) +#define SBWC_CBCR_VSTRIDE_BLOCKS(h, a) __COUNT_BLOCKS(SBWC_ALIGNED_H(h, a) / 2,\ + SBWC_BLOCK_HEIGHT) + +/* Height aligned to 16 for H.264 */ +#define SBWC_8B_Y_SIZE(w, h) ((SBWC_8B_STRIDE(w) * \ + SBWC_Y_VSTRIDE_BLOCKS(h, 16)) + 64) +#define SBWC_8B_CBCR_SIZE(w, h) ((SBWC_8B_STRIDE(w) * \ + SBWC_CBCR_VSTRIDE_BLOCKS(h, 16)) + 64) + +#define SBWC_8B_Y_HEADER_SIZE(w, h) ((SBWC_HEADER_STRIDE(w) * \ + SBWC_Y_VSTRIDE_BLOCKS(h, 16)) + 256) + +#define SBWC_8B_CBCR_HEADER_SIZE(w, h) ((SBWC_HEADER_STRIDE(w) * \ + SBWC_CBCR_VSTRIDE_BLOCKS(h, 16)) + 128) + +/* Height aligned to 8 for H.265 and VP9 */ +#define SBWC_10B_Y_SIZE(w, h) ((SBWC_10B_STRIDE(w) * \ + SBWC_Y_VSTRIDE_BLOCKS(h, 8)) + 64) +#define SBWC_10B_CBCR_SIZE(w, h) ((SBWC_10B_STRIDE(w) * \ + SBWC_CBCR_VSTRIDE_BLOCKS(h, 8)) + 64) +#define SBWC_10B_Y_HEADER_SIZE(w, h) ((SBWC_HEADER_STRIDE(w) * \ + SBWC_Y_VSTRIDE_BLOCKS(h, 8)) + 256) +#define SBWC_10B_CBCR_HEADER_SIZE(w, h) ((SBWC_HEADER_STRIDE(w) * \ + SBWC_CBCR_VSTRIDE_BLOCKS(h, 8)) + 128) /* SBWC - single fd */ #define SBWC_8B_CBCR_BASE(base, w, h) \ @@ -194,4 +213,15 @@ ((base) + SBWCL_8B_Y_SIZE(w, h, r)) #define SBWCL_10B_CBCR_BASE(base, w, h, r) \ ((base) + SBWCL_10B_Y_SIZE(w, h, r)) + +/* AFBC */ +#define AFBC_8B_STRIDE(w) __ALIGN_UP(w, 16) +#define AFBC_10B_STRIDE(w) __ALIGN_UP(w * 2, 16) + +#define AFBC_8B_Y_SIZE(w, h) \ + ((((((w) + 31) / 32) * (((h) + 7) / 8) * 16 + 127) / 128) * 128 + \ + (((w) + 31) / 32) * (((h) + 7) / 8) * 384) +#define AFBC_10B_Y_SIZE(w, h) \ + ((((((w) + 31) / 32) * (((h) + 7) / 8) * 16 + 127) / 128) * 128 + \ + (((w) + 31) / 32) * (((h) + 7) / 8) * 512) #endif /* __LINUX_VIDEODEV2_EXYNOS_MEDIA_H */ diff --git a/include/uapi/video/mfc_macros.h b/include/uapi/video/mfc_macros.h deleted file mode 100644 index cbbbacb53bd0..000000000000 --- a/include/uapi/video/mfc_macros.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * drivers/media/platform/exynos/mfc/mfc_macros.h - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __MFC_MACROS_H -#define __MFC_MACROS_H __FILE__ - -#define WIDTH_MB(x_size) ((x_size + 15) / 16) -#define HEIGHT_MB(y_size) ((y_size + 15) / 16) - -/* - * Note that lcu_width and lcu_height are defined as follows : - * lcu_width = (frame_width + lcu_size - 1)/lcu_size - * lcu_height = (frame_height + lcu_size - 1)/lcu_size. - * (lcu_size is 32(encoder) or 64(decoder)) - * - * Note that ctb_width and ctb_height are defined as follows : - * ctb_width = (frame_width + ctb_size - 1)/ctb_size - * ctb_height = (frame_hegiht + ctb_size - 1)/ctb_size - * (ctb_size is 128(AV1 decoder)) - * - */ -#define DEC_LCU_WIDTH(x_size) ((x_size + 63) / 64) -#define ENC_LCU_WIDTH(x_size) ((x_size + 31) / 32) -#define DEC_LCU_HEIGHT(y_size) ((y_size + 63) / 64) -#define ENC_LCU_HEIGHT(y_size) ((y_size + 31) / 32) - -#define DEC_CTB_WIDTH(x_size) ((x_size + 127) / 128) -#define DEC_CTB_HEIGHT(y_size) ((y_size + 127) / 128) - -#define STREAM_BUF_ALIGN 512 -#define MFC_LINEAR_BUF_SIZE 256 - -#define DEC_STATIC_BUFFER_SIZE 20480 -/* STATIC buffer for AV1 will be aligned by 32 */ -#define DEC_AV1_STATIC_BUFFER_SIZE(x_size, y_size) \ - __ALIGN_UP((440192 + (DEC_LCU_WIDTH(x_size) * DEC_LCU_HEIGHT(y_size) * 8192)), 32) - -#define DEC_MV_SIZE_MB(x, y) (WIDTH_MB(x) * (((HEIGHT_MB(y)+1)/2)*2) * 64 + 1024) -#define DEC_HEVC_MV_SIZE(x, y) (DEC_LCU_WIDTH(x) * DEC_LCU_HEIGHT(y) * 256 + 512) -#define DEC_AV1_MV_SIZE(x, y) ((DEC_CTB_WIDTH(x) * DEC_CTB_HEIGHT(y) * 1536) * 10) - -/* helper macros */ -#ifndef __ALIGN_UP -#define __ALIGN_UP(x, a) (((x) + ((a) - 1)) & ~((a) - 1)) -#endif - -#define ENC_HEVC_LUMA_DPB_10B_SIZE(x, y) \ - (((x + 63) / 64) * 64 * ((y + 31) / 32) * 32 + \ - (((((ENC_LCU_WIDTH(x) * 32 + 3) / 4) + 15) / 16) * 16) * \ - ((y + 31) / 32) * 32 + 64) -#define ENC_HEVC_CHROMA_DPB_10B_SIZE(x, y) \ - (((x + 63) / 64) * 64 * ((y + 31) / 32) * 32 + \ - (((((ENC_LCU_WIDTH(x) * 32 + 3) / 4) + 15) / 16) * 16) * \ - ((y + 31) / 32) * 32 + 64) -#define ENC_VP9_LUMA_DPB_10B_SIZE(x, y) \ - ((((x * 2 + 127) / 128) * 128) * \ - ((y + 31) / 32) * 32 + 64) -#define ENC_VP9_CHROMA_DPB_10B_SIZE(x, y) \ - ((((x * 2 + 127) / 128) * 128) * \ - ((y + 31) / 32) * 32 + 64) -#define ENC_LUMA_DPB_SIZE(x, y) \ - (((x + 63) / 64) * 64 * ((y + 31) / 32) * 32 + 64) -#define ENC_CHROMA_DPB_SIZE(x, y) \ - (((x + 63) / 64) * 64 * ((((y + 31) / 32) * 32) / 2) + 64) - -#define ENC_SBWC_LUMA_8B_SIZE(x, y) \ - ((128 * ((x + 31) / 32) * ((__ALIGN_UP(y, 32) + 3) / 4)) + 64) -#define ENC_SBWC_LUMA_10B_SIZE(x, y) \ - ((160 * ((x + 31) / 32) * ((__ALIGN_UP(y, 32) + 3) / 4)) + 64) -#define ENC_SBWC_LUMA_HEADER_SIZE(x, y) \ - ((((((x + 63) / 64) + 15) / 16) * 16) * \ - ((__ALIGN_UP(y, 32) + 3) / 4) + 256) - -#define ENC_SBWC_CHROMA_8B_SIZE(x, y) \ - ((128 * ((x + 31) / 32) * (((__ALIGN_UP(y, 32) / 2) + 3) / 4)) + 64) -#define ENC_SBWC_CHROMA_10B_SIZE(x, y) \ - ((160 * ((x + 31) / 32) * (((__ALIGN_UP(y, 32) / 2) + 3) / 4)) + 64) -#define ENC_SBWC_CHROMA_HEADER_SIZE(x, y) \ - ((((((x + 63) / 64) + 15) / 16) * 16) * \ - (((__ALIGN_UP(y, 32) / 2) + 3) / 4) + 128) - -#define ENC_SBWC_LUMA_8B_DPB_SIZE(x, y) \ - (ENC_SBWC_LUMA_8B_SIZE(x, y) + ENC_SBWC_LUMA_HEADER_SIZE(x, y)) -#define ENC_SBWC_LUMA_10B_DPB_SIZE(x, y) \ - (ENC_SBWC_LUMA_10B_SIZE(x, y) + ENC_SBWC_LUMA_HEADER_SIZE(x, y)) -#define ENC_SBWC_CHROMA_8B_DPB_SIZE(x, y) \ - (ENC_SBWC_CHROMA_8B_SIZE(x, y) + ENC_SBWC_CHROMA_HEADER_SIZE(x, y)) -#define ENC_SBWC_CHROMA_10B_DPB_SIZE(x, y) \ - (ENC_SBWC_CHROMA_10B_SIZE(x, y) + ENC_SBWC_CHROMA_HEADER_SIZE(x, y)) - -#define ENC_V100_H264_ME_SIZE(x, y) \ - (((x + 3) * (y + 3) * 8) + ((((x * y) + 63) / 64) * 32) + (((y * 64) + 2304) * (x + 7) / 8)) -#define ENC_V100_MPEG4_ME_SIZE(x, y) \ - (((x + 3) * (y + 3) * 8) + ((((x * y) + 127) / 128) * 16) + (((y * 64) + 2304) * (x + 7) / 8)) -#define ENC_V100_VP8_ME_SIZE(x, y) \ - (((x + 3) * (y + 3) * 8) + (((y * 64) + 2304) * (x + 7) / 8)) -#define ENC_V100_VP9_ME_SIZE(x, y) \ - ((((x * 2) + 3) * ((y * 2) + 3) * 128) + (((y * 256) + 2304) * (x + 1) / 2)) -#define ENC_V100_HEVC_ME_SIZE(x, y) \ - (((x + 3) * (y + 3) * 32) + (((y * 128) + 2304) * (x + 3) / 4)) - -#define NV12N_Y_SIZE(w, h) \ - (__ALIGN_UP((w), 16) * __ALIGN_UP((h), 16) + 256) -#define NV12N_CBCR_SIZE(w, h) \ -(__ALIGN_UP((__ALIGN_UP((w), 16) * (__ALIGN_UP((h), 16) / 2) + 256), 16)) -#define NV12N_CBCR_BASE(base, w, h) \ - ((base) + NV12N_Y_SIZE((w), (h))) -#define NV12N_10B_Y_8B_SIZE(w, h) \ - (__ALIGN_UP((w), 64) * __ALIGN_UP((h), 16) + 256) -#define NV12N_10B_Y_2B_SIZE(w, h) \ - ((__ALIGN_UP((w) / 4, 16) * __ALIGN_UP((h), 16) + 64)) -#define NV12N_10B_CBCR_8B_SIZE(w, h) \ -(__ALIGN_UP((__ALIGN_UP((w), 64) * (__ALIGN_UP((h), 16) / 2) + 256), 16)) -#define NV12N_10B_CBCR_2B_SIZE(w, h) \ - ((__ALIGN_UP((w) / 4, 16) * (__ALIGN_UP((h), 16) / 2) + 64)) -#define NV12N_10B_CBCR_BASE(base, w, h) \ - ((base) + NV12N_10B_Y_8B_SIZE((w), (h)) + NV12N_10B_Y_2B_SIZE((w), (h))) - -#define YUV420N_Y_SIZE(w, h) \ - (__ALIGN_UP((w), 16) * __ALIGN_UP((h), 16) + 256) -#define YUV420N_CB_SIZE(w, h) \ -(__ALIGN_UP((__ALIGN_UP((w) / 2, 16) * (__ALIGN_UP((h), 16) / 2) + 256), 16)) -#define YUV420N_CR_SIZE(w, h) \ -(__ALIGN_UP((__ALIGN_UP((w) / 2, 16) * (__ALIGN_UP((h), 16) / 2) + 256), 16)) -#define YUV420N_CB_BASE(base, w, h) ((base) + YUV420N_Y_SIZE((w), (h))) -#define YUV420N_CR_BASE(base, w, h) \ - (YUV420N_CB_BASE((base), (w), (h)) + YUV420N_CB_SIZE((w), (h))) - -#define NV12M_Y_SIZE(w, h) \ - (__ALIGN_UP((w), 64) * __ALIGN_UP((h), 16) + 256) -#define NV12M_CBCR_SIZE(w, h) \ - ((__ALIGN_UP((w), 64) * __ALIGN_UP((h), 16) / 2) + 256) -#define NV12M_Y_2B_SIZE(w, h) \ - (__ALIGN_UP((w / 4), 16) * __ALIGN_UP((h), 16) + 256) -#define NV12M_CBCR_2B_SIZE(w, h) \ - ((__ALIGN_UP((w / 4), 16) * __ALIGN_UP((h), 16) / 2) + 256) - -#define NV16M_Y_SIZE(w, h) \ - (__ALIGN_UP((w), 64) * __ALIGN_UP((h), 16) + 256) -#define NV16M_CBCR_SIZE(w, h) \ - (__ALIGN_UP((w), 64) * __ALIGN_UP((h), 16) + 256) -#define NV16M_Y_2B_SIZE(w, h) \ - (__ALIGN_UP((w / 4), 16) * __ALIGN_UP((h), 16) + 256) -#define NV16M_CBCR_2B_SIZE(w, h) \ - (__ALIGN_UP((w / 4), 16) * __ALIGN_UP((h), 16) + 256) - -#define S10B_8B_STRIDE(w) (__ALIGN_UP((w), 64)) -#define S10B_2B_STRIDE(w) (__ALIGN_UP(((w + 3) / 4), 16)) - -/* Compress format */ -#define SBWC_8B_STRIDE(w) (128 * (((w) + 31) / 32)) -#define SBWC_10B_STRIDE(w) (160 * (((w) + 31) / 32)) -#define SBWC_HEADER_STRIDE(w) ((((((w) + 63) / 64) + 15) / 16) * 16) -#define AFBC_8B_STRIDE(w) __ALIGN_UP(w, 16) -#define AFBC_10B_STRIDE(w) __ALIGN_UP(w * 2, 16) - -#define SBWC_8B_Y_SIZE(w, h) \ - ((SBWC_8B_STRIDE(w) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWC_8B_Y_HEADER_SIZE(w, h) \ - __ALIGN_UP(((SBWC_HEADER_STRIDE(w) * \ - ((__ALIGN_UP((h), 16) + 3) / 4)) + 256), 32) -#define SBWC_8B_CBCR_SIZE(w, h) \ - ((SBWC_8B_STRIDE(w) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) -#define SBWC_8B_CBCR_HEADER_SIZE(w, h) \ - ((SBWC_HEADER_STRIDE(w) * \ - (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 128) -#define AFBC_8B_Y_SIZE(w, h) \ - (((((w + 31) / 32) * ((h + 7) / 8) * 16 + 127) / 128) * 128 + \ - ((w + 31) / 32) * ((h + 7) / 8) * 384) -#define AFBC_10B_Y_SIZE(w, h) \ - (((((w + 31) / 32) * ((h + 7) / 8) * 16 + 127) / 128) * 128 + \ - ((w + 31) / 32) * ((h + 7) / 8) * 512) - -#define SBWC_10B_Y_SIZE(w, h) \ - ((SBWC_10B_STRIDE(w) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWC_10B_Y_HEADER_SIZE(w, h) \ - __ALIGN_UP((((__ALIGN_UP((w), 16) * \ - __ALIGN_UP((h), 16) * 2) + 256) - SBWC_10B_Y_SIZE(w, h)), 32) -#define SBWC_10B_CBCR_SIZE(w, h) \ - ((SBWC_10B_STRIDE(w) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) -#define SBWC_10B_CBCR_HEADER_SIZE(w, h) \ - (((__ALIGN_UP((w), 16) * \ - __ALIGN_UP((h), 16)) + 256) - SBWC_10B_CBCR_SIZE(w, h)) - -/* SBWC - single fd */ -#define SBWC_8B_CBCR_BASE(base, w, h) \ - ((base) + SBWC_8B_Y_SIZE(w, h) + SBWC_8B_Y_HEADER_SIZE(w, h)) -#define SBWC_10B_CBCR_BASE(base, w, h) \ - ((base) + SBWC_10B_Y_SIZE(w, h) + SBWC_10B_Y_HEADER_SIZE(w, h)) - -/* SBWC Lossy */ -#define SBWCL_8B_STRIDE(w, r) (((128 * (r)) / 100) * (((w) + 31) / 32)) -#define SBWCL_10B_STRIDE(w, r) (((160 * (r)) / 100) * (((w) + 31) / 32)) - -#define SBWCL_8B_Y_SIZE(w, h, r) \ - ((SBWCL_8B_STRIDE(w, r) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWCL_8B_CBCR_SIZE(w, h, r) \ - ((SBWCL_8B_STRIDE(w, r) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) - -#define SBWCL_10B_Y_SIZE(w, h, r) \ - ((SBWCL_10B_STRIDE(w, r) * ((__ALIGN_UP((h), 16) + 3) / 4)) + 64) -#define SBWCL_10B_CBCR_SIZE(w, h, r) \ - ((SBWCL_10B_STRIDE(w, r) * (((__ALIGN_UP((h), 16) / 2) + 3) / 4)) + 64) - -#define SBWCL_8B_CBCR_BASE(base, w, h, r) \ - ((base) + SBWCL_8B_Y_SIZE(w, h, r)) -#define SBWCL_10B_CBCR_BASE(base, w, h, r) \ - ((base) + SBWCL_10B_Y_SIZE(w, h, r)) - -#endif /* __MFC_MACROS_H */ diff --git a/init/do_mounts_initrd.c b/init/do_mounts_initrd.c index 533d81ed74d4..cd4a81114f75 100644 --- a/init/do_mounts_initrd.c +++ b/init/do_mounts_initrd.c @@ -83,7 +83,7 @@ static void __init handle_initrd(void) * In case that a resume from disk is carried out by linuxrc or one of * its children, we need to tell the freezer not to wait for us. */ - current->flags |= PF_FREEZER_SKIP; + freezer_do_not_count(); info = call_usermodehelper_setup("/linuxrc", argv, envp_init, GFP_KERNEL, init_linuxrc, NULL, NULL); diff --git a/kernel/cgroup/Makefile b/kernel/cgroup/Makefile index 5d7a76bfbbb7..c8bc5cbe1d45 100644 --- a/kernel/cgroup/Makefile +++ b/kernel/cgroup/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_CGROUP_PIDS) += pids.o obj-$(CONFIG_CGROUP_RDMA) += rdma.o obj-$(CONFIG_CPUSETS) += cpuset.o obj-$(CONFIG_CGROUP_DEBUG) += debug.o +obj-$(CONFIG_ANDROID_VENDOR_HOOKS) += vendor_hooks.o diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 3a0204d880db..76440c9e545b 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -941,6 +941,12 @@ static void rebuild_root_domains(void) { struct cpuset *cs = NULL; struct cgroup_subsys_state *pos_css; + bool bypass = false; + + trace_android_vh_rebuild_root_domains_bypass(cpuhp_tasks_frozen, &bypass); + + if (bypass) + return; lockdep_assert_held(&cpuset_mutex); lockdep_assert_cpus_held(); diff --git a/kernel/cgroup/vendor_hooks.c b/kernel/cgroup/vendor_hooks.c new file mode 100644 index 000000000000..95f7e3410d7d --- /dev/null +++ b/kernel/cgroup/vendor_hooks.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* vendor_hook.c + * + * Android Vendor Hook Support + * + * Copyright 2022 Google LLC + */ +#ifndef __GENKSYMS__ +#include "cgroup-internal.h" +#else +/* + * Needed to preserve CRC for cgroup-related hooks + */ +#include +#include <../drivers/gpio/gpiolib.h> +#endif + +#define CREATE_TRACE_POINTS +#include +#include +#include + +/* + * Export tracepoints that act as a bare tracehook (ie: have no trace event + * associated with them) to allow external modules to probe them. + */ +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cgroup_set_task); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_cpuset_fork); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_cgroup_force_kthread_migration); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_refrigerator); +EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_cgroup_attach); + +/* + * For type visibility + */ +const struct cgroup_taskset *GKI_struct_cgroup_taskset; +EXPORT_SYMBOL_GPL(GKI_struct_cgroup_taskset); diff --git a/kernel/fork.c b/kernel/fork.c index a33cb21a05a5..8d2c3eb1b8fa 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -2260,6 +2260,17 @@ static __latent_entropy struct task_struct *copy_process( if (retval) goto bad_fork_put_pidfd; + /* + * Now that the cgroups are pinned, re-clone the parent cgroup and put + * the new task on the correct runqueue. All this *before* the task + * becomes visible. + * + * This isn't part of ->can_fork() because while the re-cloning is + * cgroup specific, it unconditionally needs to place the task on a + * runqueue. + */ + sched_cgroup_fork(p, args); + /* * From this point on we must avoid any synchronous user-space * communication until we take the tasklist-lock. In particular, we do @@ -2367,7 +2378,7 @@ static __latent_entropy struct task_struct *copy_process( fd_install(pidfd, pidfile); proc_fork_connector(p); - sched_post_fork(p, args); + sched_post_fork(p); cgroup_post_fork(p, args); perf_event_fork(p); diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index e2999a070a99..79cb6d063b80 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -200,6 +200,7 @@ int irq_gc_set_wake(struct irq_data *d, unsigned int on) irq_gc_unlock(gc); return 0; } +EXPORT_SYMBOL_GPL(irq_gc_set_wake); static u32 irq_readl_be(void __iomem *addr) { diff --git a/kernel/power/main.c b/kernel/power/main.c index d6140ed15d0b..f985c3ccbf2f 100644 --- a/kernel/power/main.c +++ b/kernel/power/main.c @@ -23,7 +23,7 @@ void lock_system_sleep(void) { - current->flags |= PF_FREEZER_SKIP; + freezer_do_not_count(); mutex_lock(&system_transition_mutex); } EXPORT_SYMBOL_GPL(lock_system_sleep); diff --git a/kernel/sched/core.c b/kernel/sched/core.c index c8d980c95842..1a11dc60e691 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -3506,6 +3506,7 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) init_entity_runnable_average(&p->se); trace_android_rvh_finish_prio_fork(p); + #ifdef CONFIG_SCHED_INFO if (likely(sched_info_on())) memset(&p->sched_info, 0, sizeof(p->sched_info)); @@ -3521,18 +3522,23 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) return 0; } -void sched_post_fork(struct task_struct *p, struct kernel_clone_args *kargs) +void sched_cgroup_fork(struct task_struct *p, struct kernel_clone_args *kargs) { unsigned long flags; -#ifdef CONFIG_CGROUP_SCHED - struct task_group *tg; -#endif + /* + * Because we're not yet on the pid-hash, p->pi_lock isn't strictly + * required yet, but lockdep gets upset if rules are violated. + */ raw_spin_lock_irqsave(&p->pi_lock, flags); #ifdef CONFIG_CGROUP_SCHED - tg = container_of(kargs->cset->subsys[cpu_cgrp_id], - struct task_group, css); - p->sched_task_group = autogroup_task_group(p, tg); + if (1) { + struct task_group *tg; + tg = container_of(kargs->cset->subsys[cpu_cgrp_id], + struct task_group, css); + tg = autogroup_task_group(p, tg); + p->sched_task_group = tg; + } #endif rseq_migrate(p); /* @@ -3543,7 +3549,10 @@ void sched_post_fork(struct task_struct *p, struct kernel_clone_args *kargs) if (p->sched_class->task_fork) p->sched_class->task_fork(p); raw_spin_unlock_irqrestore(&p->pi_lock, flags); +} +void sched_post_fork(struct task_struct *p) +{ uclamp_post_fork(p); } @@ -4617,23 +4626,6 @@ pick_next_task(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) BUG(); } -static bool __task_can_run(struct task_struct *prev) -{ - if (__fatal_signal_pending(prev)) - return true; - - if (!frozen_or_skipped(prev)) - return true; - - /* - * We can't safely go back on the runqueue if we're an asymmetric - * task skipping the freezer. Doing so can lead to migration failures - * later on if there aren't any suitable CPUs left around for us to - * move to. - */ - return task_cpu_possible_mask(prev) == cpu_possible_mask; -} - /* * __schedule() is the main scheduler function. * @@ -4727,7 +4719,7 @@ static void __sched notrace __schedule(bool preempt) */ prev_state = prev->state; if (!preempt && prev_state) { - if (signal_pending_state(prev_state, prev) && __task_can_run(prev)) { + if (signal_pending_state(prev_state, prev)) { prev->state = TASK_RUNNING; } else { prev->sched_contributes_to_load = diff --git a/kernel/sched/cpupri.c b/kernel/sched/cpupri.c index 450a724b4542..2896860c8333 100644 --- a/kernel/sched/cpupri.c +++ b/kernel/sched/cpupri.c @@ -150,7 +150,7 @@ int cpupri_find_fitness(struct cpupri *cp, struct task_struct *p, { int task_pri = convert_prio(p->prio); int idx, cpu; - bool drop_nopreempts = task_pri <= MAX_RT_PRIO; + bool drop_nopreempts = task_pri <= MAX_RT_PRIO + 1; BUG_ON(task_pri >= CPUPRI_NR_PRIORITIES); diff --git a/kernel/sched/psi.c b/kernel/sched/psi.c index f46ac0f39777..e14917cd2a1d 100644 --- a/kernel/sched/psi.c +++ b/kernel/sched/psi.c @@ -1020,7 +1020,7 @@ void psi_cgroup_free(struct cgroup *cgroup) */ void cgroup_move_task(struct task_struct *task, struct css_set *to) { - unsigned int task_flags = 0; + unsigned int task_flags; struct rq_flags rf; struct rq *rq; @@ -1035,15 +1035,31 @@ void cgroup_move_task(struct task_struct *task, struct css_set *to) rq = task_rq_lock(task, &rf); - if (task_on_rq_queued(task)) { - task_flags = TSK_RUNNING; - if (task_current(rq, task)) - task_flags |= TSK_ONCPU; - } else if (task->in_iowait) - task_flags = TSK_IOWAIT; - - if (task->in_memstall) - task_flags |= TSK_MEMSTALL; + /* + * We may race with schedule() dropping the rq lock between + * deactivating prev and switching to next. Because the psi + * updates from the deactivation are deferred to the switch + * callback to save cgroup tree updates, the task's scheduling + * state here is not coherent with its psi state: + * + * schedule() cgroup_move_task() + * rq_lock() + * deactivate_task() + * p->on_rq = 0 + * psi_dequeue() // defers TSK_RUNNING & TSK_IOWAIT updates + * pick_next_task() + * rq_unlock() + * rq_lock() + * psi_task_change() // old cgroup + * task->cgroups = to + * psi_task_change() // new cgroup + * rq_unlock() + * rq_lock() + * psi_sched_switch() // does deferred updates in new cgroup + * + * Don't rely on the scheduling state. Use psi_flags instead. + */ + task_flags = task->psi_flags; if (task_flags) psi_task_change(task, task_flags, 0); diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 9334aef949f5..d89b24db809f 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -54,7 +54,6 @@ #include "workqueue_internal.h" -#include #include /* events/workqueue.h uses default TRACE_INCLUDE_PATH */ #undef TRACE_INCLUDE_PATH @@ -5845,7 +5844,6 @@ static void wq_watchdog_timer_fn(struct timer_list *unused) pr_cont_pool_info(pool); pr_cont(" stuck for %us!\n", jiffies_to_msecs(now - pool_ts) / 1000); - trace_android_vh_wq_lockup_pool(pool->cpu, pool_ts); } } diff --git a/mm/OWNERS b/mm/OWNERS deleted file mode 100644 index e953c3e048a7..000000000000 --- a/mm/OWNERS +++ /dev/null @@ -1,2 +0,0 @@ -hridya@google.com -surenb@google.com diff --git a/mm/madvise.c b/mm/madvise.c index 8920a7125389..937301fb9bc5 100644 --- a/mm/madvise.c +++ b/mm/madvise.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -1266,6 +1267,7 @@ int do_madvise(struct mm_struct *mm, unsigned long start, size_t len_in, int beh int write; size_t len; struct blk_plug plug; + bool do_plug = true; start = untagged_addr(start); @@ -1300,10 +1302,13 @@ int do_madvise(struct mm_struct *mm, unsigned long start, size_t len_in, int beh mmap_read_lock(mm); } - blk_start_plug(&plug); + trace_android_vh_do_madvise_blk_plug(behavior, &do_plug); + if (do_plug) + blk_start_plug(&plug); error = madvise_walk_vmas(mm, start, end, behavior, madvise_vma_behavior); - blk_finish_plug(&plug); + if (do_plug) + blk_finish_plug(&plug); if (write) mmap_write_unlock(mm); else diff --git a/mm/memory.c b/mm/memory.c index a038d72a8110..83b715ed6577 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -1230,15 +1230,18 @@ static unsigned long zap_pte_range(struct mmu_gather *tlb, pte_t *start_pte; pte_t *pte; swp_entry_t entry; + int v_ret = 0; tlb_change_page_size(tlb, PAGE_SIZE); again: + trace_android_vh_zap_pte_range_tlb_start(&v_ret); init_rss_vec(rss); start_pte = pte_offset_map_lock(mm, pmd, addr, &ptl); pte = start_pte; flush_tlb_batched_pending(mm); arch_enter_lazy_mmu_mode(); do { + bool flush = false; pte_t ptent = *pte; if (pte_none(ptent)) continue; @@ -1279,8 +1282,9 @@ static unsigned long zap_pte_range(struct mmu_gather *tlb, page_remove_rmap(page, false); if (unlikely(page_mapcount(page) < 0)) print_bad_pte(vma, addr, ptent, page); + trace_android_vh_zap_pte_range_tlb_force_flush(page, &flush); if (unlikely(__tlb_remove_page(tlb, page)) || - lru_cache_disabled()) { + lru_cache_disabled() || flush) { force_flush = 1; addr += PAGE_SIZE; break; @@ -1346,6 +1350,7 @@ static unsigned long zap_pte_range(struct mmu_gather *tlb, tlb_flush_mmu(tlb); } + trace_android_vh_zap_pte_range_tlb_end(&v_ret); if (addr != end) { cond_resched(); goto again; diff --git a/mm/mmap.c b/mm/mmap.c index cb5fded3aa0b..7d91528c3400 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -2768,11 +2768,28 @@ static void unmap_region(struct mm_struct *mm, { struct vm_area_struct *next = vma_next(mm, prev); struct mmu_gather tlb; + struct vm_area_struct *cur_vma; lru_add_drain(); tlb_gather_mmu(&tlb, mm, start, end); update_hiwater_rss(mm); unmap_vmas(&tlb, vma, start, end); + + /* + * Ensure we have no stale TLB entries by the time this mapping is + * removed from the rmap. + * Note that we don't have to worry about nested flushes here because + * we're holding the mm semaphore for removing the mapping - so any + * concurrent flush in this region has to be coming through the rmap, + * and we synchronize against that using the rmap lock. + */ + for (cur_vma = vma; cur_vma; cur_vma = cur_vma->vm_next) { + if ((cur_vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP)) != 0) { + tlb_flush_mmu(&tlb); + break; + } + } + free_pgtables(&tlb, vma, prev ? prev->vm_end : FIRST_USER_ADDRESS, next ? next->vm_start : USER_PGTABLES_CEILING); tlb_finish_mmu(&tlb, start, end); diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 7588d6df717c..b18bd7a511df 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -8826,6 +8826,8 @@ static int __alloc_contig_migrate_range(struct compact_control *cc, unsigned int tries = 0; unsigned int max_tries = 5; int ret = 0; + bool skip = false; + struct page *page; struct migration_target_control mtc = { .nid = zone_to_nid(cc->zone), @@ -8835,7 +8837,9 @@ static int __alloc_contig_migrate_range(struct compact_control *cc, if (cc->alloc_contig && cc->mode == MIGRATE_ASYNC) max_tries = 1; - lru_cache_disable(); + trace_android_vh_skip_lru_disable(&skip); + if (!skip) + lru_cache_disable(); while (pfn < end || !list_empty(&cc->migratepages)) { if (fatal_signal_pending(current)) { @@ -8870,7 +8874,8 @@ static int __alloc_contig_migrate_range(struct compact_control *cc, info->nr_migrated += cc->nr_migratepages; } - lru_cache_enable(); + if (!skip) + lru_cache_enable(); if (ret < 0) { if (ret == -EBUSY) { alloc_contig_dump_pages(&cc->migratepages); diff --git a/mm/swap.c b/mm/swap.c index 2f69e44ca737..467282ac2e96 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -43,6 +43,9 @@ #define CREATE_TRACE_POINTS #include +#undef CREATE_TRACE_POINTS +#include + /* How many pages do we try to swap or page in/out together? */ int page_cluster; @@ -267,6 +270,7 @@ static bool pagevec_add_and_need_flush(struct pagevec *pvec, struct page *page) lru_cache_disabled()) ret = true; + trace_android_vh_pagevec_drain(page, &ret); return ret; } diff --git a/mm/vmscan.c b/mm/vmscan.c index d09d63861544..8a6f6479cd71 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -70,6 +70,9 @@ #undef CREATE_TRACE_POINTS #include +#undef CREATE_TRACE_POINTS +#include + EXPORT_TRACEPOINT_SYMBOL_GPL(mm_vmscan_direct_reclaim_begin); EXPORT_TRACEPOINT_SYMBOL_GPL(mm_vmscan_direct_reclaim_end); @@ -2005,6 +2008,8 @@ shrink_inactive_list(unsigned long nr_to_scan, struct lruvec *lruvec, enum vm_event_item item; struct pglist_data *pgdat = lruvec_pgdat(lruvec); bool stalled = false; + struct blk_plug plug; + bool do_plug = false; while (unlikely(too_many_isolated(pgdat, file, sc))) { if (stalled) @@ -2038,6 +2043,9 @@ shrink_inactive_list(unsigned long nr_to_scan, struct lruvec *lruvec, if (nr_taken == 0) return 0; + trace_android_vh_shrink_inactive_list_blk_plug(&do_plug); + if (do_plug) + blk_start_plug(&plug); nr_reclaimed = shrink_page_list(&page_list, pgdat, sc, &stat, false); spin_lock_irq(&pgdat->lru_lock); @@ -2054,6 +2062,9 @@ shrink_inactive_list(unsigned long nr_to_scan, struct lruvec *lruvec, spin_unlock_irq(&pgdat->lru_lock); + if (do_plug) + blk_finish_plug(&plug); + mem_cgroup_uncharge_list(&page_list); free_unref_page_list(&page_list); @@ -2188,6 +2199,8 @@ unsigned long reclaim_pages(struct list_head *page_list) LIST_HEAD(node_page_list); struct reclaim_stat dummy_stat; struct page *page; + struct blk_plug plug; + bool do_plug = false; struct scan_control sc = { .gfp_mask = GFP_KERNEL, .priority = DEF_PRIORITY, @@ -2196,6 +2209,10 @@ unsigned long reclaim_pages(struct list_head *page_list) .may_swap = 1, }; + trace_android_vh_reclaim_pages_plug(&do_plug); + if (do_plug) + blk_start_plug(&plug); + while (!list_empty(page_list)) { page = lru_to_page(page_list); if (nid == NUMA_NO_NODE) { @@ -2231,6 +2248,8 @@ unsigned long reclaim_pages(struct list_head *page_list) putback_lru_page(page); } } + if (do_plug) + blk_finish_plug(&plug); return nr_reclaimed; } @@ -5257,6 +5276,7 @@ static void shrink_lruvec(struct lruvec *lruvec, struct scan_control *sc) unsigned long nr_reclaimed = 0; unsigned long nr_to_reclaim = sc->nr_to_reclaim; struct blk_plug plug; + bool do_plug = true; bool scan_adjusted; if (lru_gen_enabled()) { @@ -5283,7 +5303,9 @@ static void shrink_lruvec(struct lruvec *lruvec, struct scan_control *sc) scan_adjusted = (!cgroup_reclaim(sc) && !current_is_kswapd() && sc->priority == DEF_PRIORITY); - blk_start_plug(&plug); + trace_android_vh_shrink_lruvec_blk_plug(&do_plug); + if (do_plug) + blk_start_plug(&plug); while (nr[LRU_INACTIVE_ANON] || nr[LRU_ACTIVE_FILE] || nr[LRU_INACTIVE_FILE]) { unsigned long nr_anon, nr_file, percentage; @@ -5355,7 +5377,8 @@ static void shrink_lruvec(struct lruvec *lruvec, struct scan_control *sc) scan_adjusted = true; } - blk_finish_plug(&plug); + if (do_plug) + blk_finish_plug(&plug); sc->nr_reclaimed += nr_reclaimed; /* diff --git a/net/key/af_key.c b/net/key/af_key.c index d1364b858fdf..91da57dcb7f0 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -1701,9 +1701,12 @@ static int pfkey_register(struct sock *sk, struct sk_buff *skb, const struct sad pfk->registered |= (1<sadb_msg_satype); } + mutex_lock(&pfkey_mutex); xfrm_probe_algs(); supp_skb = compose_sadb_supported(hdr, GFP_KERNEL); + mutex_unlock(&pfkey_mutex); + if (!supp_skb) { if (hdr->sadb_msg_satype != SADB_SATYPE_UNSPEC) pfk->registered &= ~(1<sadb_msg_satype); diff --git a/net/mac80211/ieee80211_i.h b/net/mac80211/ieee80211_i.h index fe8f586886b4..5bfa4e1ff9b8 100644 --- a/net/mac80211/ieee80211_i.h +++ b/net/mac80211/ieee80211_i.h @@ -1480,7 +1480,6 @@ struct ieee802_11_elems { const u8 *supp_rates; const u8 *ds_params; const struct ieee80211_tim_ie *tim; - const u8 *challenge; const u8 *rsn; const u8 *rsnx; const u8 *erp_info; @@ -1533,7 +1532,6 @@ struct ieee802_11_elems { u8 ssid_len; u8 supp_rates_len; u8 tim_len; - u8 challenge_len; u8 rsn_len; u8 rsnx_len; u8 ext_supp_rates_len; @@ -1548,6 +1546,8 @@ struct ieee802_11_elems { u8 country_elem_len; u8 bssid_index_len; + void *nontx_profile; + /* whether a parse error occurred while retrieving these elements */ bool parse_error; }; diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c index 0dba353d3f8f..2d133e5c5799 100644 --- a/net/mac80211/mlme.c +++ b/net/mac80211/mlme.c @@ -2899,14 +2899,14 @@ static void ieee80211_auth_challenge(struct ieee80211_sub_if_data *sdata, { struct ieee80211_local *local = sdata->local; struct ieee80211_mgd_auth_data *auth_data = sdata->u.mgd.auth_data; + const struct element *challenge; u8 *pos; - struct ieee802_11_elems elems; u32 tx_flags = 0; pos = mgmt->u.auth.variable; - ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, - mgmt->bssid, auth_data->bss->bssid); - if (!elems.challenge) + challenge = cfg80211_find_elem(WLAN_EID_CHALLENGE, pos, + len - (pos - (u8 *)mgmt)); + if (!challenge) return; auth_data->expected_transaction = 4; drv_mgd_prepare_tx(sdata->local, sdata, 0); @@ -2914,7 +2914,8 @@ static void ieee80211_auth_challenge(struct ieee80211_sub_if_data *sdata, tx_flags = IEEE80211_TX_CTL_REQ_TX_STATUS | IEEE80211_TX_INTFL_MLME_CONN_TX; ieee80211_send_auth(sdata, 3, auth_data->algorithm, 0, - elems.challenge - 2, elems.challenge_len + 2, + (void *)challenge, + challenge->datalen + sizeof(*challenge), auth_data->bss->bssid, auth_data->bss->bssid, auth_data->key, auth_data->key_len, auth_data->key_idx, tx_flags); @@ -3299,7 +3300,7 @@ static bool ieee80211_assoc_success(struct ieee80211_sub_if_data *sdata, } capab_info = le16_to_cpu(mgmt->u.assoc_resp.capab_info); ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, elems, - mgmt->bssid, assoc_data->bss->bssid); + mgmt->bssid, NULL); if (elems->aid_resp) aid = le16_to_cpu(elems->aid_resp->aid); @@ -3393,6 +3394,7 @@ static bool ieee80211_assoc_success(struct ieee80211_sub_if_data *sdata, sdata_info(sdata, "AP bug: VHT operation missing from AssocResp\n"); } + kfree(bss_elems.nontx_profile); } /* @@ -3701,7 +3703,7 @@ static void ieee80211_rx_mgmt_assoc_resp(struct ieee80211_sub_if_data *sdata, return; ieee802_11_parse_elems(pos, len - (pos - (u8 *)mgmt), false, &elems, - mgmt->bssid, assoc_data->bss->bssid); + mgmt->bssid, NULL); if (status_code == WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY && elems.timeout_int && @@ -4038,6 +4040,7 @@ static void ieee80211_rx_mgmt_beacon(struct ieee80211_sub_if_data *sdata, ifmgd->assoc_data->timeout = jiffies; ifmgd->assoc_data->timeout_started = true; run_again(sdata, ifmgd->assoc_data->timeout); + kfree(elems.nontx_profile); return; } @@ -4215,7 +4218,7 @@ static void ieee80211_rx_mgmt_beacon(struct ieee80211_sub_if_data *sdata, ieee80211_report_disconnect(sdata, deauth_buf, sizeof(deauth_buf), true, WLAN_REASON_DEAUTH_LEAVING); - return; + goto free; } if (sta && elems.opmode_notif) @@ -4230,6 +4233,8 @@ static void ieee80211_rx_mgmt_beacon(struct ieee80211_sub_if_data *sdata, elems.cisco_dtpc_elem); ieee80211_bss_info_change_notify(sdata, changed); +free: + kfree(elems.nontx_profile); } void ieee80211_sta_rx_queued_ext(struct ieee80211_sub_if_data *sdata, diff --git a/net/mac80211/rx.c b/net/mac80211/rx.c index 1e7614abd947..c033ac60c41f 100644 --- a/net/mac80211/rx.c +++ b/net/mac80211/rx.c @@ -1976,10 +1976,11 @@ ieee80211_rx_h_decrypt(struct ieee80211_rx_data *rx) if (mmie_keyidx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS || mmie_keyidx >= NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + - NUM_DEFAULT_BEACON_KEYS) { - cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, - skb->data, - skb->len); + NUM_DEFAULT_BEACON_KEYS) { + if (rx->sdata->dev) + cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, + skb->data, + skb->len); return RX_DROP_MONITOR; /* unexpected BIP keyidx */ } @@ -2127,7 +2128,8 @@ ieee80211_rx_h_decrypt(struct ieee80211_rx_data *rx) /* either the frame has been decrypted or will be dropped */ status->flag |= RX_FLAG_DECRYPTED; - if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE)) + if (unlikely(ieee80211_is_beacon(fc) && result == RX_DROP_UNUSABLE && + rx->sdata->dev)) cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, skb->data, skb->len); diff --git a/net/mac80211/scan.c b/net/mac80211/scan.c index 6b50cb5e0e3c..ad088324a6d3 100644 --- a/net/mac80211/scan.c +++ b/net/mac80211/scan.c @@ -227,6 +227,8 @@ ieee80211_bss_info_update(struct ieee80211_local *local, rx_status, beacon); } + kfree(elems.nontx_profile); + return bss; } diff --git a/net/mac80211/util.c b/net/mac80211/util.c index a1f129292ad8..7fa6efa8b83c 100644 --- a/net/mac80211/util.c +++ b/net/mac80211/util.c @@ -1124,10 +1124,6 @@ _ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, } else elem_parse_failed = true; break; - case WLAN_EID_CHALLENGE: - elems->challenge = pos; - elems->challenge_len = elen; - break; case WLAN_EID_VENDOR_SPECIFIC: if (elen >= 4 && pos[0] == 0x00 && pos[1] == 0x50 && pos[2] == 0xf2) { @@ -1409,6 +1405,8 @@ static size_t ieee802_11_find_bssid_profile(const u8 *start, size_t len, for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, start, len) { if (elem->datalen < 2) continue; + if (elem->data[0] < 1 || elem->data[0] > 8) + continue; for_each_element(sub, elem->data + 1, elem->datalen - 1) { u8 new_bssid[ETH_ALEN]; @@ -1485,6 +1483,11 @@ u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, nontransmitted_profile, nontransmitted_profile_len); + if (!nontransmitted_profile_len) { + nontransmitted_profile_len = 0; + kfree(nontransmitted_profile); + nontransmitted_profile = NULL; + } } crc = _ieee802_11_parse_elems_crc(start, len, action, elems, filter, @@ -1514,7 +1517,7 @@ u32 ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, offsetofend(struct ieee80211_bssid_index, dtim_count)) elems->dtim_count = elems->bssid_index->dtim_count; - kfree(nontransmitted_profile); + elems->nontx_profile = nontransmitted_profile; return crc; } diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c index 78acc4e9ac93..b8939ebaa6d3 100644 --- a/net/nfc/netlink.c +++ b/net/nfc/netlink.c @@ -1244,7 +1244,7 @@ int nfc_genl_fw_download_done(struct nfc_dev *dev, const char *firmware_name, struct sk_buff *msg; void *hdr; - msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_ATOMIC); if (!msg) return -ENOMEM; @@ -1260,7 +1260,7 @@ int nfc_genl_fw_download_done(struct nfc_dev *dev, const char *firmware_name, genlmsg_end(msg, hdr); - genlmsg_multicast(&nfc_genl_family, msg, 0, 0, GFP_KERNEL); + genlmsg_multicast(&nfc_genl_family, msg, 0, 0, GFP_ATOMIC); return 0; diff --git a/net/wireless/scan.c b/net/wireless/scan.c index fd614a5a00b4..45f0ec0398af 100644 --- a/net/wireless/scan.c +++ b/net/wireless/scan.c @@ -143,18 +143,12 @@ static inline void bss_ref_get(struct cfg80211_registered_device *rdev, lockdep_assert_held(&rdev->bss_lock); bss->refcount++; - if (bss->pub.hidden_beacon_bss) { - bss = container_of(bss->pub.hidden_beacon_bss, - struct cfg80211_internal_bss, - pub); - bss->refcount++; - } - if (bss->pub.transmitted_bss) { - bss = container_of(bss->pub.transmitted_bss, - struct cfg80211_internal_bss, - pub); - bss->refcount++; - } + + if (bss->pub.hidden_beacon_bss) + bss_from_pub(bss->pub.hidden_beacon_bss)->refcount++; + + if (bss->pub.transmitted_bss) + bss_from_pub(bss->pub.transmitted_bss)->refcount++; } static inline void bss_ref_put(struct cfg80211_registered_device *rdev, @@ -304,7 +298,8 @@ static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, tmp_old = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); tmp_old = (tmp_old) ? tmp_old + tmp_old[1] + 2 : ie; - while (tmp_old + tmp_old[1] + 2 - ie <= ielen) { + while (tmp_old + 2 - ie <= ielen && + tmp_old + tmp_old[1] + 2 - ie <= ielen) { if (tmp_old[0] == 0) { tmp_old++; continue; @@ -364,7 +359,8 @@ static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, * copied to new ie, skip ssid, capability, bssid-index ie */ tmp_new = sub_copy; - while (tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { + while (tmp_new + 2 - sub_copy <= subie_len && + tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { if (!(tmp_new[0] == WLAN_EID_NON_TX_BSSID_CAP || tmp_new[0] == WLAN_EID_SSID)) { memcpy(pos, tmp_new, tmp_new[1] + 2); @@ -429,6 +425,15 @@ cfg80211_add_nontrans_list(struct cfg80211_bss *trans_bss, rcu_read_unlock(); + /* + * This is a bit weird - it's not on the list, but already on another + * one! The only way that could happen is if there's some BSSID/SSID + * shared by multiple APs in their multi-BSSID profiles, potentially + * with hidden SSID mixed in ... ignore it. + */ + if (!list_empty(&nontrans_bss->nontrans_list)) + return -EINVAL; + /* add to the list */ list_add_tail(&nontrans_bss->nontrans_list, &trans_bss->nontrans_list); return 0; @@ -1590,6 +1595,23 @@ struct cfg80211_non_tx_bss { u8 bssid_index; }; +static void cfg80211_update_hidden_bsses(struct cfg80211_internal_bss *known, + const struct cfg80211_bss_ies *new_ies, + const struct cfg80211_bss_ies *old_ies) +{ + struct cfg80211_internal_bss *bss; + + /* Assign beacon IEs to all sub entries */ + list_for_each_entry(bss, &known->hidden_list, hidden_list) { + const struct cfg80211_bss_ies *ies; + + ies = rcu_access_pointer(bss->pub.beacon_ies); + WARN_ON(ies != old_ies); + + rcu_assign_pointer(bss->pub.beacon_ies, new_ies); + } +} + static bool cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, struct cfg80211_internal_bss *known, @@ -1613,7 +1635,6 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); } else if (rcu_access_pointer(new->pub.beacon_ies)) { const struct cfg80211_bss_ies *old; - struct cfg80211_internal_bss *bss; if (known->pub.hidden_beacon_bss && !list_empty(&known->hidden_list)) { @@ -1641,16 +1662,7 @@ cfg80211_update_known_bss(struct cfg80211_registered_device *rdev, if (old == rcu_access_pointer(known->pub.ies)) rcu_assign_pointer(known->pub.ies, new->pub.beacon_ies); - /* Assign beacon IEs to all sub entries */ - list_for_each_entry(bss, &known->hidden_list, hidden_list) { - const struct cfg80211_bss_ies *ies; - - ies = rcu_access_pointer(bss->pub.beacon_ies); - WARN_ON(ies != old); - - rcu_assign_pointer(bss->pub.beacon_ies, - new->pub.beacon_ies); - } + cfg80211_update_hidden_bsses(known, new->pub.beacon_ies, old); if (old) kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); @@ -1727,6 +1739,8 @@ cfg80211_bss_update(struct cfg80211_registered_device *rdev, new->refcount = 1; INIT_LIST_HEAD(&new->hidden_list); INIT_LIST_HEAD(&new->pub.nontrans_list); + /* we'll set this later if it was non-NULL */ + new->pub.transmitted_bss = NULL; if (rcu_access_pointer(tmp->pub.proberesp_ies)) { hidden = rb_find_bss(rdev, tmp, BSS_CMP_HIDE_ZLEN); @@ -1963,9 +1977,14 @@ cfg80211_inform_single_bss_data(struct wiphy *wiphy, */ if (cfg80211_add_nontrans_list(non_tx_data->tx_bss, &res->pub)) { - if (__cfg80211_unlink_bss(rdev, res)) + if (__cfg80211_unlink_bss(rdev, res)) { rdev->bss_generation++; + res = NULL; + } } + + if (!res) + return NULL; } trace_cfg80211_return_bss(&res->pub); @@ -2084,6 +2103,8 @@ static void cfg80211_parse_mbssid_data(struct wiphy *wiphy, for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, ie, ielen) { if (elem->datalen < 4) continue; + if (elem->data[0] < 1 || (int)elem->data[0] > 8) + continue; for_each_element(sub, elem->data + 1, elem->datalen - 1) { u8 profile_len; @@ -2219,7 +2240,7 @@ cfg80211_update_notlisted_nontrans(struct wiphy *wiphy, size_t new_ie_len; struct cfg80211_bss_ies *new_ies; const struct cfg80211_bss_ies *old; - u8 cpy_len; + size_t cpy_len; lockdep_assert_held(&wiphy_to_rdev(wiphy)->bss_lock); @@ -2286,6 +2307,8 @@ cfg80211_update_notlisted_nontrans(struct wiphy *wiphy, } else { old = rcu_access_pointer(nontrans_bss->beacon_ies); rcu_assign_pointer(nontrans_bss->beacon_ies, new_ies); + cfg80211_update_hidden_bsses(bss_from_pub(nontrans_bss), + new_ies, old); rcu_assign_pointer(nontrans_bss->ies, new_ies); if (old) kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); diff --git a/tools/testing/selftests/filesystems/fuse/fuse_test.c b/tools/testing/selftests/filesystems/fuse/fuse_test.c index 58a0dd587fec..461b79656973 100644 --- a/tools/testing/selftests/filesystems/fuse/fuse_test.c +++ b/tools/testing/selftests/filesystems/fuse/fuse_test.c @@ -1911,7 +1911,117 @@ static int bpf_test_revalidate_handle_backing_fd(const char *mount_dir) return result; } -static int parse_options(int argc, char *const *argv) +static int bpf_test_lookup_postfilter(const char *mount_dir) +{ + const char *file1_name = "file1"; + const char *file2_name = "file2"; + const char *file3_name = "file3"; + int result = TEST_FAILURE; + int bpf_fd = -1; + int src_fd = -1; + int fuse_dev = -1; + int file_fd = -1; + int pid = -1; + int status; + + TEST(file_fd = s_creat(s_path(s(ft_src), s(file1_name)), 0777), + file_fd != -1); + TESTSYSCALL(close(file_fd)); + TEST(file_fd = s_creat(s_path(s(ft_src), s(file2_name)), 0777), + file_fd != -1); + TESTSYSCALL(close(file_fd)); + file_fd = -1; + TESTEQUAL(install_elf_bpf("test_bpf.bpf", "test_lookup_postfilter", + &bpf_fd, NULL, NULL), 0); + TEST(src_fd = open(ft_src, O_DIRECTORY | O_RDONLY | O_CLOEXEC), + src_fd != -1); + TESTEQUAL(mount_fuse(mount_dir, bpf_fd, src_fd, &fuse_dev), 0); + FUSE_ACTION + int fd = -1; + + TESTEQUAL(s_open(s_path(s(mount_dir), s(file1_name)), O_RDONLY), + -1); + TESTEQUAL(errno, ENOENT); + TEST(fd = s_open(s_path(s(mount_dir), s(file2_name)), O_RDONLY), + fd != -1); + TESTSYSCALL(close(fd)); + TESTEQUAL(s_open(s_path(s(mount_dir), s(file3_name)), O_RDONLY), + -1); + FUSE_DAEMON + struct fuse_in_header *in_header = + (struct fuse_in_header *)bytes_in; + struct fuse_entry_out *feo; + struct fuse_entry_bpf_out *febo; + + TESTFUSELOOKUP(file1_name, FUSE_POSTFILTER); + TESTFUSEOUTERROR(-ENOENT); + + TESTFUSELOOKUP(file2_name, FUSE_POSTFILTER); + feo = (struct fuse_entry_out *) (bytes_in + + sizeof(struct fuse_in_header) + strlen(file2_name) + 1); + febo = (struct fuse_entry_bpf_out *) ((char *)feo + + sizeof(*feo)); + TESTFUSEOUT2(fuse_entry_out, *feo, fuse_entry_bpf_out, *febo); + + TESTFUSELOOKUP(file3_name, FUSE_POSTFILTER); + TESTEQUAL(in_header->error_in, -ENOENT); + TESTFUSEOUTERROR(-ENOENT); + FUSE_DONE + + result = TEST_SUCCESS; +out: + close(file_fd); + close(fuse_dev); + umount(mount_dir); + close(src_fd); + close(bpf_fd); + return result; +} + +static void parse_range(const char *ranges, bool *run_test, size_t tests) +{ + size_t i; + char *range; + + for (i = 0; i < tests; ++i) + run_test[i] = false; + + range = strtok(optarg, ","); + while (range) { + char *dash = strchr(range, '-'); + + if (dash) { + size_t start = 1, end = tests; + char *end_ptr; + + if (dash > range) { + start = strtol(range, &end_ptr, 10); + if (*end_ptr != '-' || start <= 0 || start > tests) + ksft_exit_fail_msg("Bad range\n"); + } + + if (dash[1]) { + end = strtol(dash + 1, &end_ptr, 10); + if (*end_ptr || end <= start || end > tests) + ksft_exit_fail_msg("Bad range\n"); + } + + for (i = start; i <= end; ++i) + run_test[i - 1] = true; + } else { + char *end; + long value = strtol(range, &end, 10); + + if (*end || value <= 0 || value > tests) + ksft_exit_fail_msg("Bad range\n"); + run_test[value - 1] = true; + } + range = strtok(NULL, ","); + } +} + +static int parse_options(int argc, char *const *argv, bool *run_test, + size_t tests) { signed char c; @@ -1922,7 +2032,7 @@ static int parse_options(int argc, char *const *argv) break; case 't': - test_options.test = strtol(optarg, NULL, 10); + parse_range(optarg, run_test, tests); break; case 'v': @@ -1941,7 +2051,8 @@ struct test_case { const char *name; }; -static void run_one_test(const char *mount_dir, struct test_case *test_case) +static void run_one_test(const char *mount_dir, + const struct test_case *test_case) { ksft_print_msg("Running %s\n", test_case->name); if (test_case->pfunc(mount_dir) == TEST_SUCCESS) @@ -1957,37 +2068,11 @@ int main(int argc, char *argv[]) int i; int fd, count; - if (parse_options(argc, argv)) - ksft_exit_fail_msg("Bad options\n"); - - // Seed randomness pool for testing on QEMU - // NOTE - this abuses the concept of randomness - do *not* ever do this - // on a machine for production use - the device will think it has good - // randomness when it does not. - fd = open("/dev/urandom", O_WRONLY | O_CLOEXEC); - count = 4096; - for (int i = 0; i < 128; ++i) - ioctl(fd, RNDADDTOENTCNT, &count); - close(fd); - - ksft_print_header(); - - if (geteuid() != 0) - ksft_print_msg("Not a root, might fail to mount.\n"); - - if (tracing_on() != TEST_SUCCESS) - ksft_exit_fail_msg("Can't turn on tracing\n"); - - src_dir = setup_mount_dir(ft_src); - mount_dir = setup_mount_dir(ft_dst); - if (src_dir == NULL || mount_dir == NULL) - ksft_exit_fail_msg("Can't create a mount dir\n"); - #define MAKE_TEST(test) \ { \ test, #test \ } - struct test_case cases[] = { + const struct test_case cases[] = { MAKE_TEST(basic_test), MAKE_TEST(bpf_test_real), MAKE_TEST(bpf_test_partial), @@ -2017,27 +2102,51 @@ int main(int argc, char *argv[]) MAKE_TEST(bpf_test_lseek), MAKE_TEST(bpf_test_readdirplus_not_overriding_backing), MAKE_TEST(bpf_test_no_readdirplus_without_nodeid), - MAKE_TEST(bpf_test_revalidate_handle_backing_fd) + MAKE_TEST(bpf_test_revalidate_handle_backing_fd), + MAKE_TEST(bpf_test_lookup_postfilter), }; #undef MAKE_TEST - if (test_options.test) { - if (test_options.test <= 0 || - test_options.test > ARRAY_SIZE(cases)) - ksft_exit_fail_msg("Invalid test\n"); - - ksft_set_plan(1); - delete_dir_tree(mount_dir, false); - delete_dir_tree(src_dir, false); - run_one_test(mount_dir, &cases[test_options.test - 1]); - } else { - ksft_set_plan(ARRAY_SIZE(cases)); - for (i = 0; i < ARRAY_SIZE(cases); ++i) { + bool run_test[ARRAY_SIZE(cases)]; + + for (int i = 0; i < ARRAY_SIZE(cases); ++i) + run_test[i] = true; + + if (parse_options(argc, argv, run_test, ARRAY_SIZE(cases))) + ksft_exit_fail_msg("Bad options\n"); + + // Seed randomness pool for testing on QEMU + // NOTE - this abuses the concept of randomness - do *not* ever do this + // on a machine for production use - the device will think it has good + // randomness when it does not. + fd = open("/dev/urandom", O_WRONLY | O_CLOEXEC); + count = 4096; + for (int i = 0; i < 128; ++i) + ioctl(fd, RNDADDTOENTCNT, &count); + close(fd); + + ksft_print_header(); + + if (geteuid() != 0) + ksft_print_msg("Not a root, might fail to mount.\n"); + + if (tracing_on() != TEST_SUCCESS) + ksft_exit_fail_msg("Can't turn on tracing\n"); + + src_dir = setup_mount_dir(ft_src); + mount_dir = setup_mount_dir(ft_dst); + if (src_dir == NULL || mount_dir == NULL) + ksft_exit_fail_msg("Can't create a mount dir\n"); + + ksft_set_plan(ARRAY_SIZE(run_test)); + + for (i = 0; i < ARRAY_SIZE(run_test); ++i) + if (run_test[i]) { delete_dir_tree(mount_dir, false); delete_dir_tree(src_dir, false); run_one_test(mount_dir, &cases[i]); - } - } + } else + ksft_cnt.ksft_xskip++; umount2(mount_dir, MNT_FORCE); delete_dir_tree(mount_dir, true); diff --git a/tools/testing/selftests/filesystems/fuse/test_bpf.c b/tools/testing/selftests/filesystems/fuse/test_bpf.c index 472a02aef5b5..b47445735ab6 100644 --- a/tools/testing/selftests/filesystems/fuse/test_bpf.c +++ b/tools/testing/selftests/filesystems/fuse/test_bpf.c @@ -524,3 +524,16 @@ int readdirplus_test(struct fuse_bpf_args *fa) } return FUSE_BPF_BACKING; } + +SEC("test_lookup_postfilter") +int lookuppostfilter_test(struct fuse_bpf_args *fa) +{ + switch(fa->opcode) { + case FUSE_LOOKUP | FUSE_PREFILTER: + return FUSE_BPF_BACKING | FUSE_BPF_POST_FILTER; + case FUSE_LOOKUP | FUSE_POSTFILTER: + return FUSE_BPF_USER_FILTER; + default: + return FUSE_BPF_BACKING; + } +} diff --git a/tools/testing/selftests/filesystems/fuse/test_framework.h b/tools/testing/selftests/filesystems/fuse/test_framework.h index 945f141e9a66..7e832e901d50 100644 --- a/tools/testing/selftests/filesystems/fuse/test_framework.h +++ b/tools/testing/selftests/filesystems/fuse/test_framework.h @@ -40,7 +40,6 @@ static int test_case_fail; struct _test_options { int file; - int test; bool verbose; }; diff --git a/update_symbol_list.sh b/update_symbol_list.sh index 78d9dbe0ca78..9fe4d3932c50 100755 --- a/update_symbol_list.sh +++ b/update_symbol_list.sh @@ -4,8 +4,8 @@ function usage { echo "USAGE: $0 [-p|--prepare-aosp-abi BUG_NUMBER [-c|--continue] [--change-id CHANGE_ID]]" echo - echo " -p | --prepare-aosp-abi BUG_NUMBER Update the AOSP ABI xml and symbol list in aosp/ and" - echo " create a commit with the provide BUG_NUMBER." + echo " -p | --prepare-aosp-abi BUG_NUMBER Update the AOSP ABI xml and symbol list in ${GKI_KERNEL_DIR}/ " + echo " and create a commit with the provide BUG_NUMBER." echo " -c | --continue Continue after the rebase failure" echo " --change-id CHANGE_ID Use this Change-Id when creating the AOSP commit" } @@ -52,15 +52,15 @@ function verify_aosp_tree { return fi - pushd aosp >/dev/null + pushd ${GKI_KERNEL_DIR} >/dev/null if ! git diff --quiet HEAD; then exit_if_error 1 \ - "Found uncommitted changes in aosp/. Commit your changes before updating the ABI" + "Found uncommitted changes in ${GKI_KERNEL_DIR}/. Commit your changes before updating the ABI" fi if [ "${CONTINUE_AFTER_REBASE}" = "0" ]; then if git branch | grep "\<${FOR_AOSP_PUSH_BRANCH}\>" 2>&1 >/dev/null; then - echo "The branch '${FOR_AOSP_PUSH_BRANCH}' already exists in aosp/. Please delete" >&2 + echo "The branch '${FOR_AOSP_PUSH_BRANCH}' already exists in ${GKI_KERNEL_DIR}/. Please delete" >&2 echo "this branch (git branch -D ${FOR_AOSP_PUSH_BRANCH}) before continuing." >&2 exit 1 fi @@ -84,22 +84,22 @@ function update_aosp_abi { local out_dir="out_aosp_abi" local pixel_symbol_list="android/abi_gki_aarch64_generic" - # Rebase to aosp/android13-5.10 ToT before updating the ABI - pushd aosp/ >/dev/null + # Rebase to ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH} ToT before updating the ABI + pushd ${GKI_KERNEL_DIR}/ >/dev/null if [ "${CONTINUE_AFTER_REBASE}" = "0" ]; then git checkout -b ${FOR_AOSP_PUSH_BRANCH} fi - git fetch aosp android13-5.10 && git rebase FETCH_HEAD + git fetch ${GKI_KERNEL_REMOTE} ${GKI_KERNEL_BRANCH} && git rebase FETCH_HEAD err=$? if [ "${err}" != "0" ]; then - echo "ERROR: Failed to rebase your aosp/ change(s) to the AOSP ToT." >&2 + echo "ERROR: Failed to rebase your ${GKI_KERNEL_DIR}/ change(s) to the ${GKI_KERNEL_REMOTE} ToT." >&2 echo "To resolve this, please manually resolve the rebase conflicts" >&2 echo "and run: git rebase --continue. Then resume this script" >&2 echo "using the command:" >&2 echo >&2 echo " $0 --prepare-aosp-abi ${BUG} --continue" >&2 echo >&2 - echo "To return to your original tree in aosp/ after finishing the" >&2 + echo "To return to your original tree in ${GKI_KERNEL_DIR}/ after finishing the" >&2 echo "ABI update, run this git command:" >&2 echo >&2 echo " git checkout ${AOSP_CUR_BRANCH_OR_SHA1}" >&2 @@ -108,20 +108,20 @@ function update_aosp_abi { fi popd >/dev/null - # First, rollback any symbol list changes in aosp/ and then regenerate the + # First, rollback any symbol list changes in ${GKI_KERNEL_DIR}/ and then regenerate the # list based on AOSP ToT and the updated pixel symbol list. This ensures that # we only add symbols needed based on the current pixel changes. # # Note: we are purposefully not using `--additions-only` in order to avoid # adding symbols in the pixel tree during development that later get removed. # To retain symbols in the same way as `--additions-only` does, we are - # cat'ing the private/gs-google/ and ToT aosp/ symbol lists together when + # cat'ing the private/gs-google/ and ToT ${GKI_KERNEL_DIR}/ symbol lists together when # preparing for the AOSP ABI update. This retains all symbols in the aosp # version of the pixel symbol list. - git -C aosp show aosp/android13-5.10:"${pixel_symbol_list}" \ - > aosp/android/abi_gki_aarch64_generic + git -C ${GKI_KERNEL_DIR} show ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH}:"${pixel_symbol_list}" \ + > ${GKI_KERNEL_DIR}/android/abi_gki_aarch64_generic extract_pixel_symbols 0 "private/gs-google/${pixel_symbol_list}" - merge_and_sort_symbol_lists "aosp/${pixel_symbol_list}" \ + merge_and_sort_symbol_lists "${GKI_KERNEL_DIR}/${pixel_symbol_list}" \ "private/gs-google/${pixel_symbol_list}" # Create the symbol list commit and check if the ABI xml needs to be updated @@ -134,7 +134,7 @@ function update_aosp_abi { if [ -n "${CHANGE_ID}" ]; then echo "Change-Id: ${CHANGE_ID}" >> ${COMMIT_TEXT} fi - git -C aosp commit -s -F ${COMMIT_TEXT} -- android/ + git -C ${GKI_KERNEL_DIR} commit -s -F ${COMMIT_TEXT} -- android/ commit_ret=$? rm -f ${COMMIT_TEXT} @@ -145,7 +145,7 @@ function update_aosp_abi { # Update the AOSP ABI xml now rm -rf ${out_dir} OUT_DIR=${out_dir} \ - BUILD_CONFIG=aosp/build.config.gki.aarch64 \ + BUILD_CONFIG=${GKI_KERNEL_DIR}/build.config.gki.aarch64 \ SKIP_CP_KERNEL_HDR=1 \ LTO=full \ DIST_DIR= \ @@ -154,13 +154,13 @@ function update_aosp_abi { build/build_abi.sh --update "$@" # TODO: How do I know if the build failed or the ABI xml was updated?? - # Create the git ABI xml commit for aosp/android13-5.10 if needed + # Create the git ABI xml commit for ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH} if needed if [ -f "${out_dir}/dist/abi.report.short" ]; then if [ "${commit_ret}" = "0" ]; then # The ACK team requires the symbol list and xml changes to be committed # in a single patch. So reset the git repo to drop the symbol list # commit we made above. - git -C aosp reset HEAD~1 + git -C ${GKI_KERNEL_DIR} reset HEAD~1 fi COMMIT_TEXT=$(mktemp -t abi_xml_commit_text.XXXXX) @@ -172,34 +172,34 @@ function update_aosp_abi { if [ -n "${CHANGE_ID}" ]; then echo "Change-Id: ${CHANGE_ID}" >> ${COMMIT_TEXT} fi - git -C aosp commit -s -F ${COMMIT_TEXT} -- android/ + git -C ${GKI_KERNEL_DIR} commit -s -F ${COMMIT_TEXT} -- android/ commit_ret=$? rm -f ${COMMIT_TEXT} fi fi echo "========================================================" - if ! git -C aosp diff --quiet aosp/android13-5.10..HEAD; then + if ! git -C ${GKI_KERNEL_DIR} diff --quiet ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH}..HEAD; then if [ "${commit_ret}" = "0" ]; then if [ -n "${FOR_AOSP_PUSH_BRANCH}" ]; then - echo " An ABI commit in aosp/ was created for you on the branch ${FOR_AOSP_PUSH_BRANCH}." + echo " An ABI commit in ${GKI_KERNEL_DIR}/ was created for you on the branch ${FOR_AOSP_PUSH_BRANCH}." else - echo " An ABI commit in aosp/ was created for you on the current branch." + echo " An ABI commit in ${GKI_KERNEL_DIR}/ was created for you on the current branch." fi else echo " The ABI xml and symbol list is up-to-date." fi echo " Please verify your commit(s) before pushing. Here are the steps to perform:" echo - echo " cd aosp" + echo " cd ${GKI_KERNEL_DIR}" echo " git log --oneline ${FOR_AOSP_PUSH_BRANCH}" - echo " git push aosp ${FOR_AOSP_PUSH_BRANCH:-HEAD}:refs/for/android13-5.10" + echo " git push ${GKI_KERNEL_REMOTE} ${FOR_AOSP_PUSH_BRANCH:-HEAD}:refs/for/${GKI_KERNEL_BRANCH}" echo if [ -n "${FOR_AOSP_PUSH_BRANCH}" ]; then - echo " After pushing your changes to aosp/, you can delete the temporary" + echo " After pushing your changes to ${GKI_KERNEL_DIR}/, you can delete the temporary" echo " branch: ${FOR_AOSP_PUSH_BRANCH} using the command:" echo - echo " cd aosp" + echo " cd ${GKI_KERNEL_DIR}" echo " git branch -D ${FOR_AOSP_PUSH_BRANCH}" echo fi @@ -209,13 +209,13 @@ function update_aosp_abi { # Rollback to the original branch/commit if [ -n "${AOSP_CUR_BRANCH_OR_SHA1}" ]; then - git -C aosp checkout ${AOSP_CUR_BRANCH_OR_SHA1} + git -C ${GKI_KERNEL_DIR} checkout ${AOSP_CUR_BRANCH_OR_SHA1} fi } # Extract the kernel module symbols. Additionally, we strip out the core ABI # symbols and sort the symbol list. We do our own sort in order to retain -# a predictable order when cat'ing the symbol lists in the pixel tree and aosp/ +# a predictable order when cat'ing the symbol lists in the pixel tree and ${GKI_KERNEL_DIR}/ # tree. # $1 Specifies if --additions-only should be used # $2 The symbol list to update/create @@ -245,7 +245,7 @@ function extract_pixel_symbols { exit_if_error $? "Failed to extract symbols!" # Strip the core ABI symbols from the pixel symbol list - grep "^ " aosp/android/abi_gki_aarch64_core | while read l; do + grep "^ " ${GKI_KERNEL_DIR}/android/abi_gki_aarch64_core | while read l; do sed -i "/\<$l\>/d" ${pixel_symbol_list} done @@ -260,8 +260,8 @@ function extract_pixel_symbols { function verify_new_symbols_require_abi_update { local pixel_symbol_list=$1 - pushd aosp/ >/dev/null - git diff --name-only aosp/android13-5.10..HEAD | grep -v "\<${pixel_symbol_list}\>" + pushd ${GKI_KERNEL_DIR}/ >/dev/null + git diff --name-only ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH}..HEAD | grep -v "\<${pixel_symbol_list}\>" err=$? if [ "${err}" = "0" ]; then # Found other files beside the pixel symbol list @@ -270,7 +270,7 @@ function verify_new_symbols_require_abi_update { return fi - local added_symbols=$(git diff aosp/android13-5.10..HEAD "${pixel_symbol_list}" \ + local added_symbols=$(git diff ${GKI_KERNEL_REMOTE}/${GKI_KERNEL_BRANCH}..HEAD "${pixel_symbol_list}" \ | sed -n 's/^+ \([a-zA-Z_0-9]\+\)/\1/p') for s in ${added_symbols}; do grep "^ $s\>" --exclude=abi_gki_aarch64.xml \ @@ -292,6 +292,19 @@ export DIST_DIR=${DIST_DIR:-${BASE_OUT}/dist/} VMLINUX_TMP=${BASE_OUT}/device-kernel/private/vmlinux # Use mktemp -u to create a random branch name FOR_AOSP_PUSH_BRANCH="update_symbol_list-delete-after-push" +BUILD_AOSP_KERNEL=${BUILD_AOSP_KERNEL:-1} +if [ -z "${GKI_KERNEL_DIR}" ];then + GKI_KERNEL_DIR="aosp" +fi +if [ -z "${GKI_KERNEL_REMOTE}" ];then + GKI_KERNEL_REMOTE="aosp" +fi +if [ -z "${GKI_KERNEL_BRANCH}" ];then + GKI_KERNEL_BRANCH="android13-5.10" +fi +if [ -z "${BUILD_SCRIPT}" ];then + BUILD_SCRIPT="./build_slider.sh" +fi PREPARE_AOSP_ABI=${PREPARE_AOSP_ABI:-0} CONTINUE_AFTER_REBASE=0 CHANGE_ID= @@ -342,22 +355,30 @@ fi verify_aosp_tree if [ "${CONTINUE_AFTER_REBASE}" = "0" ]; then - BUILD_KERNEL=1 TRIM_NONLISTED_KMI=0 ENABLE_STRICT_KMI=0 ./build_slider.sh "$@" - exit_if_error $? "Failed to run ./build_slider.sh!" + if [ "${BUILD_AOSP_KERNEL}" = "1" ]; then + BUILD_AOSP_KERNEL=1 TRIM_NONLISTED_KMI=0 ENABLE_STRICT_KMI=0 ${BUILD_SCRIPT} "$@" + elif [ "${BUILD_STAGING_KERNEL}" = "1" ]; then + BUILD_STAGING_KERNEL=1 TRIM_NONLISTED_KMI=0 ENABLE_STRICT_KMI=0 ${BUILD_SCRIPT} "$@" + fi + exit_if_error $? "Failed to run ${BUILD_SCRIPT}!" fi if [ "${PREPARE_AOSP_ABI}" != "0" ]; then update_aosp_abi "$@" else extract_pixel_symbols 1 "private/gs-google/android/abi_gki_aarch64_generic" - merge_and_sort_symbol_lists "aosp/android/abi_gki_aarch64_generic" \ + merge_and_sort_symbol_lists "${GKI_KERNEL_DIR}/android/abi_gki_aarch64_generic" \ "private/gs-google/android/abi_gki_aarch64_generic" echo "========================================================" - echo " The symbol list has been updated locally in aosp/ and private/gs-google." - echo " Compiling with BUILD_KERNEL=1 is now required until the new symbol(s)" - echo " are merged. Re-compile using the below command:" + echo " The symbol list has been updated locally in ${GKI_KERNEL_DIR}/ and private/gs-google." + echo " Compiling with BUILD_AOSP_KERNEL=1 or BUILD_STAGING_KERNEL=1 is now required until" + echo " the new symbol(s) are merged. Re-compile using the below command:" echo - echo " SKIP_MRPROPER=1 BUILD_KERNEL=1 ./build_slider.sh" + if [ "${BUILD_AOSP_KERNEL}" = "1" ]; then + echo " SKIP_MRPROPER=1 BUILD_AOSP_KERNEL=1 ${BUILD_SCRIPT}" + elif [ "${BUILD_STAGING_KERNEL}" = "1" ]; then + echo " SKIP_MRPROPER=1 BUILD_STAGING_KERNEL=1 ${BUILD_SCRIPT}" + fi echo fi diff --git a/update_symbol_list_cloudripper-aosp.sh b/update_symbol_list_cloudripper-aosp.sh new file mode 100755 index 000000000000..cf50370a175f --- /dev/null +++ b/update_symbol_list_cloudripper-aosp.sh @@ -0,0 +1,7 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +BUILD_AOSP_KERNEL=1 \ +BUILD_STAGING_KERNEL=0 \ +BUILD_SCRIPT="./build_cloudripper.sh" \ +DEVICE_KERNEL_BUILD_CONFIG=private/gs-google/build.config.cloudripper \ +private/gs-google/update_symbol_list.sh "$@" diff --git a/update_symbol_list_cloudripper-staging.sh b/update_symbol_list_cloudripper-staging.sh new file mode 100755 index 000000000000..9997efb5f3ec --- /dev/null +++ b/update_symbol_list_cloudripper-staging.sh @@ -0,0 +1,10 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +BUILD_AOSP_KERNEL=0 \ +BUILD_STAGING_KERNEL=1 \ +GKI_KERNEL_DIR=aosp-staging \ +GKI_KERNEL_REMOTE=partner-common \ +GKI_KERNEL_BRANCH=android13-5.10-pixel-staging \ +BUILD_SCRIPT="./build_cloudripper.sh" \ +DEVICE_KERNEL_BUILD_CONFIG=private/gs-google/build.config.cloudripper \ +private/gs-google/update_symbol_list.sh "$@" diff --git a/vendor_boot_modules.gs101 b/vendor_boot_modules.gs101 index 0dcf75714f4e..2a03c99ada64 100644 --- a/vendor_boot_modules.gs101 +++ b/vendor_boot_modules.gs101 @@ -21,13 +21,13 @@ bbd.ko bc_max77759.ko bcm47765.ko bcm_dbg.ko -bigocean.ko boot_control_sysfs.ko boot_device_spi.ko clk_exynos.ko cmupmucal.ko cp_thermal_zone.ko cpif.ko +cpif_page.ko dbgcore-dump.ko debug-reboot.ko debug-snapshot-debug-kinfo.ko @@ -43,8 +43,7 @@ exynos-acme.ko exynos-adv-tracer-s2d.ko exynos-adv-tracer.ko exynos-bcm_dbg-dump.ko -exynos-bts.ko -exynos-btsopsgs101.ko +bts.ko exynos-coresight-etm.ko exynos-coresight.ko exynos-cpuhp.ko @@ -78,9 +77,9 @@ google_dual_batt_gauge.ko governor_memlat.ko gpu_cooling.ko gs-chipid.ko -gs101-itmon.ko +itmon.ko gs101_spmic_thermal.ko -gs101_thermal.ko +gs_thermal.ko gs_acpm.ko gsa.ko gsa_gsc.ko @@ -92,6 +91,7 @@ heatmap.ko i2c-acpm.ko i2c-dev.ko i2c-exynos5.ko +kernel-top.ko keycombo.ko keydebug.ko logbuffer.ko @@ -141,7 +141,7 @@ s2mpg10-regulator.ko s2mpg11-mfd.ko s2mpg11-powermeter.ko s2mpg11-regulator.ko -s2mpg1x-gpio.ko +s2mpg1x-gpio-gs101.ko s2mpu.ko s3c2410_wdt.ko samsung-dma.ko diff --git a/vendor_dlkm.blocklist.cloudripper b/vendor_dlkm.blocklist.cloudripper new file mode 100644 index 000000000000..fbc0a615069b --- /dev/null +++ b/vendor_dlkm.blocklist.cloudripper @@ -0,0 +1,14 @@ +blocklist bcmdhd4389 +blocklist synadhd +blocklist focal_touch +blocklist fst2 +blocklist ftm5 +blocklist goodix_brl_touch +blocklist nvt_touch +blocklist sec_touch +blocklist syna_touch +blocklist uwb_desense.ko +blocklist uwb-hal.ko +blocklist uwbcore.ko +blocklist cl_dsp +blocklist input-cs40l26-i2c diff --git a/vendor_kernel_boot_modules.cloudripper b/vendor_kernel_boot_modules.cloudripper new file mode 100644 index 000000000000..96af451d1b38 --- /dev/null +++ b/vendor_kernel_boot_modules.cloudripper @@ -0,0 +1,12 @@ +# +# cloudripper specific modules loaded during first stage init from vendor_kernel_boot +# (platform common modules are from vendor_boot_modules.gs201) +# +panel-samsung-s6e3fc3.ko +panel-samsung-s6e3fc3-p10.ko +panel-samsung-s6e3hc2.ko +panel-samsung-s6e3hc3.ko +panel-samsung-s6e3hc3-c10.ko +panel-samsung-s6e3hc4.ko +panel-samsung-sofef01.ko +panel-boe-nt37290.ko diff --git a/vendor_kernel_boot_modules.gs201 b/vendor_kernel_boot_modules.gs201 new file mode 100644 index 000000000000..8efd94ce1ad5 --- /dev/null +++ b/vendor_kernel_boot_modules.gs201 @@ -0,0 +1,185 @@ +# List of modules loaded during first stage init from vendor_kernel_boot +# Sort order defined by +# LC_ALL=C sort +acpm_flexpmu_dbg.ko +acpm_mbox_test.ko +aoc_alsa_dev.ko +aoc_alsa_dev_util.ko +aoc_channel_dev.ko +aoc_char_dev.ko +aoc_control_dev.ko +aoc_core.ko +aoc_usb_driver.ko +aoc_uwb_platform_drv.ko +aoc_uwb_service_dev.ko +arm-memlat-mon.ko +at24.ko +bbd.ko +bc_max77759.ko +bcm47765.ko +boot_device_spi.ko +bts.ko +clk_exynos.ko +cmupmucal.ko +cp_thermal_zone.ko +cpif.ko +cpif_page.ko +dbgcore-dump.ko +debug-reboot.ko +debug-snapshot-debug-kinfo.ko +dss.ko +dw3000.ko +dwc3-exynos-usb.ko +ect_parser.ko +eh.ko +ehld.ko +exynos-acme.ko +exynos-adv-tracer-s2d.ko +exynos-adv-tracer.ko +exynos-bcm_dbg-dump.ko +exynos-coresight-etm.ko +exynos-coresight.ko +exynos-cpuhp.ko +exynos-cpupm.ko +exynos-debug-test.ko +exynos-dm.ko +exynos-drm.ko +exynos-ecc-handler.ko +exynos-pcie-iommu.ko +exynos-pd-dbg.ko +exynos-pd.ko +exynos-pd_el3.ko +exynos-pm.ko +exynos-pmu-if.ko +exynos-reboot.ko +exynos-seclog.ko +exynos_devfreq.ko +exynos_dit.ko +exynos_mct.ko +exynos_mfc.ko +exynos_pm_qos.ko +exynos_tty.ko +g2d.ko +google-battery.ko +google-bms.ko +google-charger.ko +google-cpm.ko +google_bcl.ko +governor_memlat.ko +gs-chipid.ko +gs_acpm.ko +gs_thermal.ko +gsa.ko +gsa_gsc.ko +gvotable.ko +hardlockup-debug.ko +hardlockup-watchdog.ko +heatmap.ko +i2c-acpm.ko +i2c-dev.ko +i2c-exynos5.ko +itmon.ko +janeiro.ko +kernel-top.ko +keycombo.ko +keydebug.ko +logbuffer.ko +lzo-rle.ko +lzo.ko +mailbox-wc.ko +max1720x-battery.ko +max20339.ko +max77729-pmic.ko +max77729_uic.ko +max77759_charger.ko +max77759_contaminant.ko +max77759_helper.ko +mcps802154.ko +mcps802154_region_fira.ko +mcps802154_region_nfcc_coex.ko +memlat-devfreq.ko +nitrous.ko +odpm.ko +p9221.ko +panel-samsung-drv.ko +panel-samsung-emul.ko +pca9468.ko +pcie-exynos-core.ko +pcie-exynos-gs201-rc-cal.ko +phy-exynos-mipi-dsim.ko +phy-exynos-mipi.ko +phy-exynos-usbdrd-super.ko +pinctrl-samsung-core.ko +pixel-boot-metrics.ko +pixel-debug-test.ko +pixel-em.ko +pkvm-s2mpu.ko +pl330.ko +pmic_class.ko +power_stats.ko +rtc-s2mpg12.ko +s2mpg12-key.ko +s2mpg12-mfd.ko +s2mpg12-powermeter.ko +s2mpg12-regulator.ko +s2mpg13-mfd.ko +s2mpg13-powermeter.ko +s2mpg13-regulator.ko +s2mpg13_spmic_thermal.ko +s2mpg1x-gpio-gs201.ko +s3c2410_wdt.ko +samsung-dma.ko +samsung-iommu-group.ko +samsung-secure-iova.ko +samsung_dma_heap.ko +samsung_iommu.ko +sched_tp.ko +sg.ko +shm_ipc.ko +sjtag-driver.ko +slc_acpm.ko +slc_dummy.ko +slc_pmon.ko +slc_pt.ko +smfc.ko +snd-soc-cs35l41-spi.ko +snd-soc-cs35l41.ko +snd-soc-cs35l45-spi.ko +snd-soc-cs35l45.ko +snd-soc-wm-adsp.ko +softdog.ko +spi-s3c64xx.ko +spidev.ko +sscoredump.ko +st21nfc.ko +st33spi.ko +st54spi.ko +sysrq-hook.ko +systrace.ko +tcpci_max77759.ko +touch_bus_negotiator.ko +touch_offload.ko +trusty-core.ko +trusty-ipc.ko +trusty-irq.ko +trusty-log.ko +trusty-test.ko +trusty-virtio.ko +ufs-exynos-core.ko +ufs-pixel-fips140.ko +usb_f_dm.ko +usb_f_dm1.ko +usb_f_rndis.ko +usb_psy.ko +vh_cgroup.ko +vh_fs.ko +vh_i2c.ko +vh_preemptirq_long.ko +vh_sched.ko +vh_thermal.ko +videobuf2-dma-sg.ko +xhci-exynos.ko +zcomp_cpu.ko +zcomp_eh.ko +zram.ko +zsmalloc.ko