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fsmc_debug.cdc
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#ChipScope Core Inserter Project File Version 3.0
#Thu Dec 17 16:08:19 EET 2015
Project.device.designInputFile=/home/barthess/projects/xilinx/fsmc2bram/root_cs.ngc
Project.device.designOutputFile=/home/barthess/projects/xilinx/fsmc2bram/root_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/barthess/projects/xilinx/fsmc2bram/_ngo
Project.device.useSRL16=true
Project.filter.dimension=6
Project.filter<0>=
Project.filter<1>=*170*
Project.filter<2>=*180*
Project.filter<3>=*205*
Project.filter<4>=*270*
Project.filter<5>=*360*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_170mhz
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=FSMC_A_22_IBUF
Project.unit<0>.dataChannel<10>=FSMC_A_12_IBUF
Project.unit<0>.dataChannel<11>=FSMC_A_11_IBUF
Project.unit<0>.dataChannel<12>=FSMC_A_10_IBUF
Project.unit<0>.dataChannel<13>=FSMC_A_9_IBUF
Project.unit<0>.dataChannel<14>=FSMC_A_8_IBUF
Project.unit<0>.dataChannel<15>=FSMC_A_7_IBUF
Project.unit<0>.dataChannel<16>=FSMC_A_6_IBUF
Project.unit<0>.dataChannel<17>=FSMC_A_5_IBUF
Project.unit<0>.dataChannel<18>=FSMC_A_4_IBUF
Project.unit<0>.dataChannel<19>=FSMC_A_3_IBUF
Project.unit<0>.dataChannel<1>=FSMC_A_21_IBUF
Project.unit<0>.dataChannel<20>=FSMC_A_2_IBUF
Project.unit<0>.dataChannel<21>=FSMC_A_1_IBUF
Project.unit<0>.dataChannel<22>=FSMC_A_0_IBUF
Project.unit<0>.dataChannel<23>=FSMC_NOE_IBUF
Project.unit<0>.dataChannel<24>=FSMC_NWE_IBUF
Project.unit<0>.dataChannel<25>=FSMC_NCE_IBUF
Project.unit<0>.dataChannel<26>=DEV_NULL_BANK0_OBUF
Project.unit<0>.dataChannel<27>=ram_addr_test/addr_cnt<0>
Project.unit<0>.dataChannel<28>=ram_addr_test/addr_cnt<1>
Project.unit<0>.dataChannel<29>=ram_addr_test/addr_cnt<2>
Project.unit<0>.dataChannel<2>=FSMC_A_20_IBUF
Project.unit<0>.dataChannel<30>=ram_addr_test/addr_cnt<3>
Project.unit<0>.dataChannel<31>=ram_addr_test/addr_cnt<4>
Project.unit<0>.dataChannel<32>=ram_addr_test/addr_cnt<5>
Project.unit<0>.dataChannel<33>=ram_addr_test/addr_cnt<6>
Project.unit<0>.dataChannel<34>=ram_addr_test/addr_cnt<7>
Project.unit<0>.dataChannel<35>=ram_addr_test/addr_cnt<8>
Project.unit<0>.dataChannel<36>=ram_addr_test/addr_cnt<9>
Project.unit<0>.dataChannel<37>=ram_addr_test/addr_cnt<10>
Project.unit<0>.dataChannel<38>=ram_addr_test/addr_cnt<11>
Project.unit<0>.dataChannel<39>=ram_addr_test/addr_cnt<12>
Project.unit<0>.dataChannel<3>=FSMC_A_19_IBUF
Project.unit<0>.dataChannel<40>=ram_addr_test/addr_cnt<13>
Project.unit<0>.dataChannel<41>=ram_addr_test/addr_cnt<14>
Project.unit<0>.dataChannel<42>=ram_addr_test/addr_cnt<15>
Project.unit<0>.dataChannel<43>=wire_bram_do<15>
Project.unit<0>.dataChannel<44>=wire_bram_do<14>
Project.unit<0>.dataChannel<45>=wire_bram_do<13>
Project.unit<0>.dataChannel<46>=wire_bram_do<12>
Project.unit<0>.dataChannel<47>=wire_bram_do<11>
Project.unit<0>.dataChannel<48>=wire_bram_do<10>
Project.unit<0>.dataChannel<49>=wire_bram_do<9>
Project.unit<0>.dataChannel<4>=FSMC_A_18_IBUF
Project.unit<0>.dataChannel<50>=wire_bram_do<8>
Project.unit<0>.dataChannel<51>=wire_bram_do<7>
Project.unit<0>.dataChannel<52>=wire_bram_do<6>
Project.unit<0>.dataChannel<53>=wire_bram_do<5>
Project.unit<0>.dataChannel<54>=wire_bram_do<4>
Project.unit<0>.dataChannel<55>=wire_bram_do<3>
Project.unit<0>.dataChannel<56>=wire_bram_do<2>
Project.unit<0>.dataChannel<57>=wire_bram_do<1>
Project.unit<0>.dataChannel<58>=wire_bram_do<0>
Project.unit<0>.dataChannel<59>=fsmc2bram/bram_ce
Project.unit<0>.dataChannel<5>=FSMC_A_17_IBUF
Project.unit<0>.dataChannel<60>=fsmc2bram/bram_we_0
Project.unit<0>.dataChannel<6>=FSMC_A_16_IBUF
Project.unit<0>.dataChannel<7>=FSMC_A_15_IBUF
Project.unit<0>.dataChannel<8>=FSMC_A_14_IBUF
Project.unit<0>.dataChannel<9>=FSMC_A_13_IBUF
Project.unit<0>.dataDepth=8192
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=60
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=FSMC_A_22_IBUF
Project.unit<0>.triggerChannel<0><10>=FSMC_A_12_IBUF
Project.unit<0>.triggerChannel<0><11>=FSMC_A_11_IBUF
Project.unit<0>.triggerChannel<0><12>=FSMC_A_10_IBUF
Project.unit<0>.triggerChannel<0><13>=FSMC_A_9_IBUF
Project.unit<0>.triggerChannel<0><14>=FSMC_A_8_IBUF
Project.unit<0>.triggerChannel<0><15>=FSMC_A_7_IBUF
Project.unit<0>.triggerChannel<0><16>=FSMC_A_6_IBUF
Project.unit<0>.triggerChannel<0><17>=FSMC_A_5_IBUF
Project.unit<0>.triggerChannel<0><18>=FSMC_A_4_IBUF
Project.unit<0>.triggerChannel<0><19>=FSMC_A_3_IBUF
Project.unit<0>.triggerChannel<0><1>=FSMC_A_21_IBUF
Project.unit<0>.triggerChannel<0><20>=FSMC_A_2_IBUF
Project.unit<0>.triggerChannel<0><21>=FSMC_A_1_IBUF
Project.unit<0>.triggerChannel<0><22>=FSMC_A_0_IBUF
Project.unit<0>.triggerChannel<0><23>=FSMC_NOE_IBUF
Project.unit<0>.triggerChannel<0><24>=FSMC_NWE_IBUF
Project.unit<0>.triggerChannel<0><25>=FSMC_NCE_IBUF
Project.unit<0>.triggerChannel<0><26>=DEV_NULL_BANK0_OBUF
Project.unit<0>.triggerChannel<0><27>=ram_addr_test/addr_cnt<0>
Project.unit<0>.triggerChannel<0><28>=ram_addr_test/addr_cnt<1>
Project.unit<0>.triggerChannel<0><29>=ram_addr_test/addr_cnt<2>
Project.unit<0>.triggerChannel<0><2>=FSMC_A_20_IBUF
Project.unit<0>.triggerChannel<0><30>=ram_addr_test/addr_cnt<3>
Project.unit<0>.triggerChannel<0><31>=ram_addr_test/addr_cnt<4>
Project.unit<0>.triggerChannel<0><32>=ram_addr_test/addr_cnt<5>
Project.unit<0>.triggerChannel<0><33>=ram_addr_test/addr_cnt<6>
Project.unit<0>.triggerChannel<0><34>=ram_addr_test/addr_cnt<7>
Project.unit<0>.triggerChannel<0><35>=ram_addr_test/addr_cnt<8>
Project.unit<0>.triggerChannel<0><36>=ram_addr_test/addr_cnt<9>
Project.unit<0>.triggerChannel<0><37>=ram_addr_test/addr_cnt<10>
Project.unit<0>.triggerChannel<0><38>=ram_addr_test/addr_cnt<11>
Project.unit<0>.triggerChannel<0><39>=ram_addr_test/addr_cnt<12>
Project.unit<0>.triggerChannel<0><3>=FSMC_A_19_IBUF
Project.unit<0>.triggerChannel<0><40>=ram_addr_test/addr_cnt<13>
Project.unit<0>.triggerChannel<0><41>=ram_addr_test/addr_cnt<14>
Project.unit<0>.triggerChannel<0><42>=ram_addr_test/addr_cnt<15>
Project.unit<0>.triggerChannel<0><43>=wire_bram_do<15>
Project.unit<0>.triggerChannel<0><44>=wire_bram_do<14>
Project.unit<0>.triggerChannel<0><45>=wire_bram_do<13>
Project.unit<0>.triggerChannel<0><46>=wire_bram_do<12>
Project.unit<0>.triggerChannel<0><47>=wire_bram_do<11>
Project.unit<0>.triggerChannel<0><48>=wire_bram_do<10>
Project.unit<0>.triggerChannel<0><49>=wire_bram_do<9>
Project.unit<0>.triggerChannel<0><4>=FSMC_A_18_IBUF
Project.unit<0>.triggerChannel<0><50>=wire_bram_do<8>
Project.unit<0>.triggerChannel<0><51>=wire_bram_do<7>
Project.unit<0>.triggerChannel<0><52>=wire_bram_do<6>
Project.unit<0>.triggerChannel<0><53>=wire_bram_do<5>
Project.unit<0>.triggerChannel<0><54>=wire_bram_do<4>
Project.unit<0>.triggerChannel<0><55>=wire_bram_do<3>
Project.unit<0>.triggerChannel<0><56>=wire_bram_do<2>
Project.unit<0>.triggerChannel<0><57>=wire_bram_do<1>
Project.unit<0>.triggerChannel<0><58>=wire_bram_do<0>
Project.unit<0>.triggerChannel<0><59>=fsmc2bram/bram_ce
Project.unit<0>.triggerChannel<0><5>=FSMC_A_17_IBUF
Project.unit<0>.triggerChannel<0><60>=
Project.unit<0>.triggerChannel<0><6>=FSMC_A_16_IBUF
Project.unit<0>.triggerChannel<0><7>=FSMC_A_15_IBUF
Project.unit<0>.triggerChannel<0><8>=FSMC_A_14_IBUF
Project.unit<0>.triggerChannel<0><9>=FSMC_A_13_IBUF
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=60
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro