From bc69b1d3eb2f74ff7c30bf5e96db285431ed54a3 Mon Sep 17 00:00:00 2001 From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> Date: Sat, 22 Feb 2025 22:58:49 +0800 Subject: [PATCH] sakurapi-rk3308b: bump dts and vop patches to kernel 6.13 --- .../dt/rk3308-sakurapi-rk3308b.dts | 93 ++++- .../rk3308-internal-rgb-lcdc.patch | 42 ++ .../rockchip64-6.13/rk3308-vop-output.patch | 358 ++++++++++++++++++ 3 files changed, 490 insertions(+), 3 deletions(-) mode change 100644 => 100755 patch/kernel/archive/rockchip64-6.13/dt/rk3308-sakurapi-rk3308b.dts create mode 100755 patch/kernel/archive/rockchip64-6.13/rk3308-internal-rgb-lcdc.patch create mode 100755 patch/kernel/archive/rockchip64-6.13/rk3308-vop-output.patch diff --git a/patch/kernel/archive/rockchip64-6.13/dt/rk3308-sakurapi-rk3308b.dts b/patch/kernel/archive/rockchip64-6.13/dt/rk3308-sakurapi-rk3308b.dts old mode 100644 new mode 100755 index 7d942a8f5e54..d5ed769dbf9f --- a/patch/kernel/archive/rockchip64-6.13/dt/rk3308-sakurapi-rk3308b.dts +++ b/patch/kernel/archive/rockchip64-6.13/dt/rk3308-sakurapi-rk3308b.dts @@ -2,7 +2,7 @@ /* * Copyright (c) 2019 Akash Gajjar * Copyright (c) 2019 Jagan Teki - * Copyright (C) 2024 Chiyuki Akatsuki + * Copyright (C) 2024 TheSnowfield */ /dts-v1/; @@ -108,6 +108,65 @@ pinctrl-0 = <&otg_vbus_drv>; vin-supply = <&vcc5v0_sys>; }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + display: panel { + compatible = "olimex,lcd-olinuxino-43-ts"; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <20>; + status = "okay"; + + panel_in: port { + #address-cells = <1>; + #size-cells = <0>; + + panel_in_rgb: endpoint { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; + }; + }; &cpu0 { @@ -156,7 +215,14 @@ }; }; -&spi2 { +/* SPI0 for external gpio pin */ +&spi0 { + status = "okay"; + max-freq = <10000000>; +}; + +/* SPI1 for ws2812*/ +&spi1 { status = "okay"; max-freq = <10000000>; }; @@ -194,6 +260,28 @@ status = "okay"; }; +&vop { + status = "okay"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2m0_xfer>; @@ -223,4 +311,3 @@ &usb_host_ohci{ status = "okay"; }; - diff --git a/patch/kernel/archive/rockchip64-6.13/rk3308-internal-rgb-lcdc.patch b/patch/kernel/archive/rockchip64-6.13/rk3308-internal-rgb-lcdc.patch new file mode 100755 index 000000000000..fce83d5415d2 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.13/rk3308-internal-rgb-lcdc.patch @@ -0,0 +1,42 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> +Date: Sat, 22 Feb 2025 01:09:54 +0000 +Subject: rk3308: set pinmux for internal RGB output + +Signed-off-by: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> +--- + drivers/gpu/drm/rockchip/rockchip_rgb.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c +index c677b71ae516..43e9120bbad4 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_rgb.c ++++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c +@@ -6,10 +6,11 @@ + */ + + #include + #include + #include ++#include + + #include + #include + #include + #include +@@ -167,10 +168,12 @@ struct rockchip_rgb *rockchip_rgb_init(struct device *dev, + DRM_DEV_ERROR(drm_dev->dev, + "failed to attach encoder: %d\n", ret); + goto err_free_connector; + } + ++ pinctrl_pm_select_default_state(dev); ++ + return rgb; + + err_free_connector: + drm_connector_cleanup(connector); + err_free_encoder: +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/archive/rockchip64-6.13/rk3308-vop-output.patch b/patch/kernel/archive/rockchip64-6.13/rk3308-vop-output.patch new file mode 100755 index 000000000000..29a90e4873a4 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.13/rk3308-vop-output.patch @@ -0,0 +1,358 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> +Date: Sat, 22 Feb 2025 09:22:52 +0000 +Subject: rk3308: rk3308 vop output + +Signed-off-by: TheSnowfield <17957399+TheSnowfield@users.noreply.github.com> +--- + arch/arm64/boot/dts/rockchip/rk3308.dtsi | 110 ++++++++++ + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 102 +++++++++ + drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 60 +++++ + 3 files changed, 272 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3308.dtsi b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +index e6b57ae06934..10b8605631d1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi +@@ -141,10 +141,16 @@ arm-pmu { + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + ++ display_subsystem: display-subsystem { ++ compatible = "rockchip,display-subsystem"; ++ ports = <&vop_out>; ++ status = "disabled"; ++ }; ++ + mac_clkin: external-mac-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "mac_clkin"; + #clock-cells = <0>; +@@ -685,10 +691,30 @@ dmac1: dma-controller@ff2d0000 { + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + ++ vop: vop@ff2e0000 { ++ compatible = "rockchip,rk3308-vop"; ++ reg = <0x0 0xff2e0000 0x0 0x1fc>; ++ interrupts = ; ++ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; ++ clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; ++ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; ++ reset-names = "axi", "ahb", "dclk"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lcdc_ctl>; ++ ++ status = "disabled"; ++ ++ vop_out: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + i2s_8ch_0: i2s@ff300000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff300000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, +@@ -2109,7 +2135,91 @@ uart4_rts: uart4-rts { + uart4_rts_pin: uart4-rts-pin { + rockchip,pins = + <4 RK_PA7 0 &pcfg_pull_none>; + }; + }; ++ ++ lcdc { ++ lcdc_ctl: lcdc-ctl { ++ rockchip,pins = ++ /* dclk */ ++ <1 RK_PA0 1 &pcfg_pull_none_12ma>, ++ /* hsync */ ++ <1 RK_PA1 1 &pcfg_pull_none>, ++ /* vsync */ ++ <1 RK_PA2 1 &pcfg_pull_none>, ++ /* den */ ++ <1 RK_PA3 1 &pcfg_pull_none>, ++ /* d0 */ ++ <1 RK_PA4 1 &pcfg_pull_none>, ++ /* d1 */ ++ <1 RK_PA5 1 &pcfg_pull_none>, ++ /* d2 */ ++ <1 RK_PA6 1 &pcfg_pull_none>, ++ /* d3 */ ++ <1 RK_PA7 1 &pcfg_pull_none>, ++ /* d4 */ ++ <1 RK_PB0 1 &pcfg_pull_none>, ++ /* d5 */ ++ <1 RK_PB1 1 &pcfg_pull_none>, ++ /* d6 */ ++ <1 RK_PB2 1 &pcfg_pull_none>, ++ /* d7 */ ++ <1 RK_PB3 1 &pcfg_pull_none>, ++ /* d8 */ ++ <1 RK_PB4 1 &pcfg_pull_none>, ++ /* d9 */ ++ <1 RK_PB5 1 &pcfg_pull_none>, ++ /* d10 */ ++ <1 RK_PB6 1 &pcfg_pull_none>, ++ /* d11 */ ++ <1 RK_PB7 1 &pcfg_pull_none>, ++ /* d12 */ ++ <1 RK_PC0 1 &pcfg_pull_none>, ++ /* d13 */ ++ <1 RK_PC1 1 &pcfg_pull_none>, ++ /* d14 */ ++ <1 RK_PC2 1 &pcfg_pull_none>, ++ /* d15 */ ++ <1 RK_PC3 1 &pcfg_pull_none>, ++ /* d16 */ ++ <1 RK_PC4 1 &pcfg_pull_none>, ++ /* d17 */ ++ <1 RK_PC5 1 &pcfg_pull_none>; ++ }; ++ ++ lcdc_rgb888_m0: lcdc-rgb888-m0 { ++ rockchip,pins = ++ /* d18 */ ++ <1 RK_PC6 6 &pcfg_pull_none>, ++ /* d19 */ ++ <1 RK_PC7 6 &pcfg_pull_none>, ++ /* d20 */ ++ <2 RK_PB1 3 &pcfg_pull_none>, ++ /* d21 */ ++ <2 RK_PB2 3 &pcfg_pull_none>, ++ /* d22 */ ++ <2 RK_PB7 3 &pcfg_pull_none>, ++ /* d23 */ ++ <2 RK_PC0 3 &pcfg_pull_none>; ++ }; ++ ++ lcdc_rgb888_m1: lcdc-rgb888-m1 { ++ rockchip,pins = ++ /* d18 */ ++ <3 RK_PA6 3 &pcfg_pull_none>, ++ /* d19 */ ++ <3 RK_PA7 3 &pcfg_pull_none>, ++ /* d20 */ ++ <3 RK_PB0 3 &pcfg_pull_none>, ++ /* d21 */ ++ <3 RK_PB1 3 &pcfg_pull_none>, ++ /* d22 */ ++ <3 RK_PB2 4 &pcfg_pull_none>, ++ /* d23 */ ++ <3 RK_PB3 4 &pcfg_pull_none>; ++ }; ++ }; ++ ++ + }; + }; +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +index 37602d9c2690..17547f375ea0 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +@@ -1184,10 +1184,110 @@ static const struct vop_data rk3328_vop = { + .win = rk3328_vop_win_data, + .win_size = ARRAY_SIZE(rk3328_vop_win_data), + .max_output = { 4096, 2160 }, + }; + ++static const struct vop_intr rk3308_lit_intr = { ++ .intrs = rk3368_vop_intrs, ++ .nintrs = ARRAY_SIZE(rk3368_vop_intrs), ++ .line_flag_num[0] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 0), ++ .line_flag_num[1] = VOP_REG(RK3308_LIT_LINE_FLAG, 0xfff, 16), ++ .status = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_STATUS, 0xffff, 0), ++ .enable = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_EN, 0xffff, 0), ++ .clear = VOP_REG_MASK_SYNC(RK3308_LIT_INTR_CLEAR, 0xffff, 0), ++}; ++ ++static const struct vop_output rk3308_ctrl_data = { ++ .rgb_en = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 0), ++ .rgb_pin_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x7, 2), ++ .rgb_dclk_pol = VOP_REG(RK3308_LIT_DSP_CTRL0, 0x1, 1), ++}; ++ ++static const struct vop_common rk3308_common = { ++ .standby = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 1), ++ .cfg_done = VOP_REG(RK3308_LIT_REG_CFG_DONE, 0x1, 0), ++ .dsp_blank = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 14), ++ .dither_down_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 8), ++ .dither_down_sel = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 7), ++ .dither_down_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 6), ++ .dither_up = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 2), ++ .dsp_lut_en = VOP_REG(RK3308_LIT_DSP_CTRL2, 0x1, 5), ++ .gate_en = VOP_REG(RK3308_LIT_SYS_CTRL2, 0x1, 0), ++ .out_mode = VOP_REG(RK3308_LIT_DSP_CTRL2, 0xf, 16), ++}; ++ ++static const struct vop_scl_regs rk3308_lit_win_scl = { ++ .scale_yrgb_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), ++ .scale_yrgb_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), ++ .scale_cbcr_x = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), ++ .scale_cbcr_y = VOP_REG(RK3308_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), ++}; ++ ++static const struct vop_win_phy rk3308_lit_win0_data = { ++ .scl = &rk3308_lit_win_scl, ++ .data_formats = formats_win_full, ++ .nformats = ARRAY_SIZE(formats_win_full), ++ ++ .enable = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 0), ++ .format = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x7, 1), ++ .rb_swap = VOP_REG(RK3308_LIT_WIN0_CTRL0, 0x1, 12), ++ .act_info = VOP_REG(RK3308_LIT_WIN0_ACT_INFO, 0xffffffff, 0), ++ .dsp_info = VOP_REG(RK3308_LIT_WIN0_DSP_INFO, 0xffffffff, 0), ++ .dsp_st = VOP_REG(RK3308_LIT_WIN0_DSP_ST, 0xffffffff, 0), ++ .yrgb_mst = VOP_REG(RK3308_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), ++ .uv_mst = VOP_REG(RK3308_LIT_WIN0_CBR_MST0, 0xffffffff, 0), ++ .yrgb_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 0), ++ .uv_vir = VOP_REG(RK3308_LIT_WIN0_VIR, 0x1fff, 16), ++ ++ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 2), ++ .alpha_mode = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 1), ++ .alpha_en = VOP_REG(RK3308_LIT_WIN0_ALPHA_CTRL, 0x1, 0), ++}; ++ ++static const struct vop_win_phy rk3308_lit_win1_data = { ++ .data_formats = formats_win_lite, ++ .nformats = ARRAY_SIZE(formats_win_lite), ++ ++ .enable = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 0), ++ .format = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x7, 4), ++ .rb_swap = VOP_REG(RK3308_LIT_WIN1_CTRL0, 0x1, 12), ++ .dsp_info = VOP_REG(RK3308_LIT_WIN1_DSP_INFO, 0xffffffff, 0), ++ .dsp_st = VOP_REG(RK3308_LIT_WIN1_DSP_ST, 0xffffffff, 0), ++ .yrgb_mst = VOP_REG(RK3308_LIT_WIN1_MST, 0xffffffff, 0), ++ .yrgb_vir = VOP_REG(RK3308_LIT_WIN1_VIR, 0x1fff, 0), ++ ++ .alpha_pre_mul = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 2), ++ .alpha_mode = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 1), ++ .alpha_en = VOP_REG(RK3308_LIT_WIN1_ALPHA_CTRL, 0x1, 0), ++}; ++ ++static const struct vop_win_data rk3308_vop_lit_win_data[] = { ++ { .base = 0x00, .phy = &rk3308_lit_win0_data, ++ .type = DRM_PLANE_TYPE_PRIMARY }, ++ { .base = 0x00, .phy = &rk3308_lit_win1_data, ++ .type = DRM_PLANE_TYPE_CURSOR }, ++}; ++ ++static const struct vop_modeset rk3308_modeset = { ++ .htotal_pw = VOP_REG(RK3308_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), ++ .hact_st_end = VOP_REG(RK3308_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), ++ .vtotal_pw = VOP_REG(RK3308_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), ++ .vact_st_end = VOP_REG(RK3308_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), ++}; ++ ++static const struct vop_data rk3308_vop = { ++ .version = VOP_VERSION(2, 7), ++ .output = &rk3308_ctrl_data, ++ .common = &rk3308_common, ++ .modeset = &rk3308_modeset, ++ .intr = &rk3308_lit_intr, ++ .win = rk3308_vop_lit_win_data, ++ .win_size = ARRAY_SIZE(rk3308_vop_lit_win_data), ++ .feature = VOP_FEATURE_INTERNAL_RGB, ++ .max_output = { 1280, 800 }, ++}; ++ + static const struct vop_common rv1126_common = { + .standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1), + .out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16), + .dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14), + .dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8), +@@ -1252,10 +1352,12 @@ static const struct of_device_id vop_driver_dt_match[] = { + .data = &rk3066_vop }, + { .compatible = "rockchip,rk3188-vop", + .data = &rk3188_vop }, + { .compatible = "rockchip,rk3288-vop", + .data = &rk3288_vop }, ++ { .compatible = "rockchip,rk3308-vop", ++ .data = &rk3308_vop }, + { .compatible = "rockchip,rk3368-vop", + .data = &rk3368_vop }, + { .compatible = "rockchip,rk3366-vop", + .data = &rk3366_vop }, + { .compatible = "rockchip,rk3399-vop-big", +diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +index fbf1bcc68625..5f345dd66dc1 100644 +--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h ++++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +@@ -1031,6 +1031,66 @@ + #define RK3066_MCU_BYPASS_RPORT 0x200 + #define RK3066_WIN2_LUT_ADDR 0x400 + #define RK3066_DSP_LUT_ADDR 0x800 + /* rk3066 register definition end */ + ++/* rk3308 register definition */ ++#define RK3308_LIT_REG_CFG_DONE 0x00000 ++#define RK3308_LIT_VERSION 0x00004 ++#define RK3308_LIT_DSP_BG 0x00008 ++#define RK3308_LIT_MCU_CTRL 0x0000c ++#define RK3308_LIT_SYS_CTRL0 0x00010 ++#define RK3308_LIT_SYS_CTRL1 0x00014 ++#define RK3308_LIT_SYS_CTRL2 0x00018 ++#define RK3308_LIT_DSP_CTRL0 0x00020 ++#define RK3308_LIT_DSP_CTRL2 0x00028 ++#define RK3308_LIT_VOP_STATUS 0x0002c ++#define RK3308_LIT_LINE_FLAG 0x00030 ++#define RK3308_LIT_INTR_EN 0x00034 ++#define RK3308_LIT_INTR_CLEAR 0x00038 ++#define RK3308_LIT_INTR_STATUS 0x0003c ++#define RK3308_LIT_WIN0_CTRL0 0x00050 ++#define RK3308_LIT_WIN0_CTRL1 0x00054 ++#define RK3308_LIT_WIN0_COLOR_KEY 0x00058 ++#define RK3308_LIT_WIN0_VIR 0x0005c ++#define RK3308_LIT_WIN0_YRGB_MST0 0x00060 ++#define RK3308_LIT_WIN0_CBR_MST0 0x00064 ++#define RK3308_LIT_WIN0_ACT_INFO 0x00068 ++#define RK3308_LIT_WIN0_DSP_INFO 0x0006c ++#define RK3308_LIT_WIN0_DSP_ST 0x00070 ++#define RK3308_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 ++#define RK3308_LIT_WIN0_SCL_FACTOR_CBR 0x00078 ++#define RK3308_LIT_WIN0_SCL_OFFSET 0x0007c ++#define RK3308_LIT_WIN0_ALPHA_CTRL 0x00080 ++#define RK3308_LIT_WIN1_CTRL0 0x00090 ++#define RK3308_LIT_WIN1_CTRL1 0x00094 ++#define RK3308_LIT_WIN1_VIR 0x00098 ++#define RK3308_LIT_WIN1_MST 0x000a0 ++#define RK3308_LIT_WIN1_DSP_INFO 0x000a4 ++#define RK3308_LIT_WIN1_DSP_ST 0x000a8 ++#define RK3308_LIT_WIN1_COLOR_KEY 0x000ac ++#define RK3308_LIT_WIN1_ALPHA_CTRL 0x000bc ++#define RK3308_LIT_DSP_HTOTAL_HS_END 0x00100 ++#define RK3308_LIT_DSP_HACT_ST_END 0x00104 ++#define RK3308_LIT_DSP_VTOTAL_VS_END 0x00108 ++#define RK3308_LIT_DSP_VACT_ST_END 0x0010c ++#define RK3308_LIT_DSP_VS_ST_END_F1 0x00110 ++#define RK3308_LIT_DSP_VACT_ST_END_F1 0x00114 ++#define RK3308_LIT_BCSH_CTRL 0x00160 ++#define RK3308_LIT_BCSH_COL_BAR 0x00164 ++#define RK3308_LIT_BCSH_BCS 0x00168 ++#define RK3308_LIT_BCSH_H 0x0016c ++#define RK3308_LIT_FRC_LOWER01_0 0x00170 ++#define RK3308_LIT_FRC_LOWER01_1 0x00174 ++#define RK3308_LIT_FRC_LOWER10_0 0x00178 ++#define RK3308_LIT_FRC_LOWER10_1 0x0017c ++#define RK3308_LIT_FRC_LOWER11_0 0x00180 ++#define RK3308_LIT_FRC_LOWER11_1 0x00184 ++#define RK3308_LIT_MCU_RW_BYPASS_PORT 0x0018c ++#define RK3308_LIT_DBG_REG_000 0x00190 ++#define RK3308_LIT_BLANKING_VALUE 0x001f4 ++#define RK3308_LIT_FLAG_REG_FRM_VALID 0x001f8 ++#define RK3308_LIT_FLAG_REG 0x001fc ++#define RK3308_LIT_GAMMA_LUT_ADDR 0x00a00 ++/* rk3308 register definition end */ ++ + #endif /* _ROCKCHIP_VOP_REG_H */ +-- +Created with Armbian build tools https://github.com/armbian/build +