From d3be200d979893323417f3f9993fd4d2b6741e97 Mon Sep 17 00:00:00 2001 From: Robin Heinemann Date: Tue, 25 Aug 2020 18:45:14 +0200 Subject: [PATCH] [os] fix failing ethernet link on micro Silicon Errata Issues Module 1: Device fails to link after Asymmetric Pause capability is set DESCRIPTION Whenever the device's Asymmetric Pause capability (Register 4h, Bit [11]) is set to 1, link-up may fail after a link-up to link-down transition (e.g., a cable disconnect). END USER IMPLICATIONS The device may fail to establish link when the Asymmetric Pause capability bit is set to 1. Work around Do not enable (set to 1) the Asymmetric Pause capability bit. If enabling this bit is required, a second link-up attempt (e.g., disconnect and reconnect cable) is required to establish link. PLAN This erratum will not be corrected in a future revision. --- boot/axiom-micro/devicetree.dts | 9 +-------- boot/kernel.config | 2 +- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/boot/axiom-micro/devicetree.dts b/boot/axiom-micro/devicetree.dts index a8590400..3b335a6a 100644 --- a/boot/axiom-micro/devicetree.dts +++ b/boot/axiom-micro/devicetree.dts @@ -324,14 +324,7 @@ interrupt-parent = <&intc>; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - phy0: phy@0 { -// compatible = "ethernet-phy-id004d.d072", "ethernet-phy-ieee802.3-c22"; - device_type = "ethernet-phy"; - reg = <0>; - }; + phy-mode = "rgmii-id"; }; gem1: ethernet@e000c000 { diff --git a/boot/kernel.config b/boot/kernel.config index 1b0eebb9..a12978e9 100644 --- a/boot/kernel.config +++ b/boot/kernel.config @@ -1800,7 +1800,7 @@ CONFIG_FIXED_PHY=y # CONFIG_LXT_PHY is not set CONFIG_MARVELL_PHY=y # CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MICREL_PHY is not set +CONFIG_MICREL_PHY=y CONFIG_MICROCHIP_PHY=m # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set